S93WD462S-2.7T

S93WD462_98 SUMMIT | Alldatasheet

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SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com S93WD462/S93WD463 © SUMMIT MICROELECTRONICS, Inc. 1998 2029-01 4/14/98 Characteristics subject to change without notice Precision Supply-Voltage Monitor and Reset Controller With a Watchdog Timer and 1k-bit Microwire Memory SUMMIT MICROELECTRONICS, Inc.

FEATURES

• Precision Monitor & RESET Controller — RESET and RESETRESETRESETRESETRESET Outputs — Guaranteed RESET Assertion to VCC = 1V — 150ms Reset Pulse Width — Internal 1.26V Reference with ±1% Accuracy — ZERO External Components Required
• Watchdog Timer — Nominal 1.6 Second Timeout Period — Reset by Any Transition of CS
• Memory — 1K-bit Microwire Memory — S93WD462 – Internally Ties ORG Low – 100% Compatible With all 8-bit Implementations Sixteen Byte Page Write Capability — S93WD463 – Internally Ties ORG High – 100% Compatible With all 16-bit Implementations – Eight Word Page Write Capability OVERVIEW The S93WD462 and S93WD463 are precision power supervisory circuits providing both active high and active low reset output. Both devices also incorporate a watchdog timer with a nominal timeout value of 1.6 seconds. Both devices have 1k-bits of E 2PROM memory that is accessible via the industry standard microwire bus. The S93WD462 is configured with an internal ORG pin tied low providing a 8-bit byte organization and the S93WD463 is configured with an internal ORG pin tied high providing a 16-bit word organization. Both the S93WD462 and S93WD463 have page write capabil- ity. The devices are designed for a minimum 1,000,000 program/erase cycles and have data retention in ex- cess of 100 years. BLOCK DIAGRAM - 7 RESET RESET CS DI DO SK 5GND 2029 ILL2.1 MEMORY ARRAY 1K-Bit E2PROM WRITE CONTROLADDRESS DECODER MODE DECODE DATA I/O RESET CONTROL WATCHDOG TIMER RESET PULSE GENERATOR 5KHz Oscillator VTRIP 1.26V VCC VCC

VCC +2.7 to 6.0V Power Supply GND Ground RESET/ RESET RESET I/O PIN CONFIGURATION DEVICE OPERATION

APPLICATIONS

The S93WD462/WD463 is ideal for applications requir- ing low voltage and low power consumption. This device provides microcontroller RESET control and can be manually resettable. RESET CONTROLLER DESCRIPTION The S93WD462/WD463 provides a precision reset con- troller that ensures correct system operation during brown-out and power-up/-down conditions. It is config- ured with two open drain reset outputs; pin 7 is an active high output and pin 6 is an active low output. During power-up, the reset outputs remain active until V CC reaches the VTRIP threshold. The outputs will con- tinue to be driven for approximately 150 ms after reach- ing V TRIP. The reset outputs will be valid so long as VCC is ≥ 1.0V. During power-down, the reset outputs will begin driving active when VCC falls below VTRIP. The reset pins are I/Os; therefore, the S93WD462/ WD463 can act as a signal conditioning circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset timeout after detecting a low to high transition and the RESET input will initiate a reset timeout after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a debounce/ reset extender circuit. It should be noted the reset outputs are open drain. When used as outputs driving a circuit they need to be either tied high (RESET) or tied to ground (RESET) through the use of pull-up or pull-down resistors. Refer to the applications aid section for help in determining the value of resistor to be used. Internally these pins are weakly pulled up (RESET) and pulled down (RESET): therefore, if the signals are not being used the pins may be left unconnected. WATCHDOG TIMER DESCRIPTION The S93WD462/WD463 has a watchdog timer with a nominal timeout period of 1.6 seconds. Whenever the watchdog times out, it will generate a reset output to both pins 6 and 7. The watchdog timer is reset by any transition on CS. The watchdog timer will be held in a reset state during power-on while V CC is less than VTRIP. Once VCC exceeds VTRIP the watchdog will continue to be held in a reset state for the tPURST period. After tPURST it will be released and the timer will begin operation. If either reset input is asserted the watchdog timer will be reset and remain in the reset condition until either t PURST has expired or the reset input is released, whichever is longer. GENERAL OPERATION The S93WD462/WD463 is a 1024-bit nonvolatile memory intended for use with industry standard microproces- sors. The S93WD463 is organized as X16, seven 9-bit instructions control the reading, writing and erase operations of the device. The S93WD462 is organized as X8, seven 10-bit instructions control the reading, writing and erase operations of the device. The device operates on a single 3V or 5V supply and will generate 2029 ILL1.0 CS SK DI DO VCC RESET RESET GND CS SK DI DO VCC RESET RESET GND

Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deselected for a minimum of 250ns (t CSMIN ). The falling edge of CS will start the auto erase cycle of the selected memory location. The ready/busy status of the S93WD462/WD463 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. Erase/Write Enable and Disable The S93WD462/WD463 powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write in- struction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all S93WD462/WD463 write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. Page Write 93WD462 - Assume WEN has been issued. The host will then take CS high, and begin clocking in the start bit, write command and 7-bit address immediately followed by the first byte of data to be written. The host can then continue clocking in 8-bit bytes of data with each byte to be written to the next higher address. Internally the address pointer is incremented after receiving each group of eight clocks; however, once the address counter reaches xxx 1111 it will roll over to xxx 0000 with the next clock. After the last bit is clocked in no internal write operation will occur until CS is brought low. 93WD463 - Assume WEN has been issued. The host will then take CS high, and begin clocking in the start bit, write command and 6-bit address immediately followed by the first 16-bit word of data to be written. The host can then continue clocking in 16-bit words of data with each word to be written to the next higher address. Internally the address pointer is incremented after receiving each group of sixteen clocks; however, once the address counter reaches xxx x111 it will roll over to xx x000 with the next clock. After the last bit is clocked in no internal write operation will occur until CS is brought low. Continuous Read This begins just like a standard read with the host issuing a read instruction and clocking out the data byte [word]. If the host then keeps CS high and continues generating clocks on SK, the S93WD462/ WD463 will output data from the next higher address location. The S93WD462/WD463 will continue incrementing the address and outputting data so long as CS stays high. If the highest address is reached, the address counter will roll over to address 0000. CS going low will reset the instruction register and any subsequent read must be initiated in the normal man- ner of issuing the command and address. Erase All Upon receiving an ERAL command, the CS (Chip Se- lect) pin must be deselected for a minimum of 250ns CSMIN ). The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the S93WD462/WD463 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits will be in a logical “1” state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of 250ns (t CSMIN ). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/ busy status of the S93WD462/WD463 can be deter- mined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed.

ABSOLUTE MAXIMUM RATINGS* *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V. D.C. OPERATING CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC Power Supply Current 3 mA DI = 0.0V, f SK = 1MHz (Operating) V CC = 5.0V, CS = 5.0V, Output Open ISB Power Supply Current 50 µA CS = 0V (Standby) Reset Outputs Open ILI Input Leakage Current 2 µAV IN = 0V to VCC ILO Output Leakage Current 10 µAV OUT = 0V to VCC , (Including ORG pin) CS = 0V VIL1 Input Low Voltage -0.1 0.8 V 4.5V ≤VCC <5.5V VIH1 Input High Voltage 2 V CC +1 V VIL2 Input Low Voltage 0 V CC X0.2 V 1.8V ≤VCC <2.7V VIH2 Input High Voltage V CC X0.7 V CC +1 V VOL1 Output Low Voltage 0.4 V 4.5V ≤VCC <5.5V VOH1 Output High Voltage 2.4 V I OL = 2.1mA IOH = -400µA VOL2 Output Low Voltage 0.2 V 1.8V ≤VCC <2.7V VOH2 Output High Voltage V CC -0.2 V I OL = 1mA IOH = -100µA 2029 PGM T3.0 RELIABILITY CHARACTERISTICS Symbol Parameter Min. Max. Units Reference Test Method N END (3) Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 TDR (3) Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP (3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH (3)(4) Latch-Up 100 mA JEDEC Standard 17 2029 PGM T2.1 Temperature Min Max Commercial 0 °C +70 °C Industrial -40 °C +85 °C RECOMMENDED OPERATING CONDITIONS 2029 PGM T7.0

VCC =2.7V-4.5V VCC =4.5V-5.5V Test SYMBOL PARAMETER Min. Max. Min. Max. UNITS Conditions tCSS CS Setup Time 100 50 ns tCSH CS Hold Time 0 0 ns V IL = 0.45V tDIS DI Setup Time 200 100 ns V IH = 2.4V tDIH DI Hold Time 200 100 ns C L = 100pF tPD1 Output Delay to 1 0.5 0.25 µsV OL = 0.8V tPD0 Output Delay to 0 0.5 0.25 µsV OH = 2.0v tHZ (1) Output Delay to High-Z 200 100 ns tEW Program/Erase Pulse Width 10 10 ms tCSMIN Minimum CS Low Time 0.5 0.25 µs tSKHI Minimum SK High Time 0.5 0.25 µs tSKLOW Minimum SK Low Time 0.5 0.25 µs tSV Output Delay to Status Valid 0.5 0.25 µsC L = 100pF SK MAX Maximum Clock Frequency DC 500 DC 1000 KHZ Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. A.C. CHARACTERISTICS (over recommended operating conditions unless otherwise specified) C L = 100pF 2029 PGM T6.0 PIN CAPACITANCE Symbol Test Max. Units Conditions C OUT (1) OUTPUT CAPACITANCE (DO) 5 pF V OUT =OV C IN(1) INPUT CAPACITANCE (CS, SK, DI, ORG) 5 pF V IN=OV 2029 PGM T4.0

Figure 8. RESET Timing Diagram

.228 (5.80) .035 (.90) .020 (.50) .010 (.25) x45° .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .275 (6.99) TYP. .030 (.762) TYP.

8 Places

.050 (1.27) TYP. .050 (1.270) TYP. .157 (4.00) .150 (3.80) .196 (5.00)1 .189 (4.80) FOOTPRINT 8pn JEDEC SOIC ILL.2 .375 (9.525) PIN 1 INDICATOR .015 (.381) Min. .130 (3.302) .100 (2.54) TYP. .018 (.457) TYP. .060 – .005 (1.524) – .127 TYP. .130 (3.302) SEATING PLANE .070 (1.778) .0375 (0.952) .300 (7.620) 5°-7°TYP. (4 PLCS) .350 (8.89) .009 – .002 (.229 – .051) 0°-15° .250 (6.350) 8pn PDIP/P ILL.3

8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

8 Pin PDIP (Type P) Package

Frequently the reset controller will be deployed on a PC board that provides a peripheral function to a system. Examples might be modem or network cards in a PC or a PCMCIA card in a laptop. In instances like this the peripheral card may have a requirement for a clean reset function to insure proper operation. The system may or may not provide a reset pulse of sufficient duration to clear the peripheral or to protect data stored in a nonvolatile memory. The I/O capability of the RESET pins can provide a solution. The system’s reset signal to the peripheral can be fed into the S93WD462/WD463 and it in turn can clean up the signal and provide a known entity to the peripheral’s circuits. The figure below shows the basic timing characteristics under the assumption the reset input is shorter in duration than t PURST . The same reset output affect can be attained by using the active high reset input. When planning your resistor pull-up and pull-down values, use the following chart to help determine min. resistances. Condition Min Typ Max Units VCC = 1.0V, IOL =100µA 0.3 V VCC = 1.2V, IOL =100µA 0.3 V VCC = 3.0V, IOL =500µA 0.3 V VCC = 3.6V, IOL =500µA 0.3 V VCC = 4.5V, IOL =750µA 0.3 V VCC = 1.0V, IOL =100µA 0.4 V VCC = 1.2V, IOL =150µA 0.4 V VCC = 3.0V, IOL =750µA 0.4 V VCC = 3.6V, IOL =1mA 0.4 V VCC = 4.5V, IOL =1mA 0.4 V VCC = 1.0V, IOH =400µAV CC -0.75 V VCC = 1.2V, IOH =800µAV CC -0.75 V VCC = 3.0V, IOH =800µAV CC -0.5 V VCC = 3.6V, IOH =800µAV CC -0.5 V VCC = 4.5V, IOH =800µAV CC -0.5 V Worst Case RESET Sink/Source Capabilities at Various VCC Levels Parameter Symbol RESET Output V OL Voltage RESET Output V OL Voltage RESET Output V OH Voltage 2029 PGM T5.0 RESET Input RESET Output RESET Output 2029 ILL 12.0 tPURST

During the internal write operation the S93WD462/WD463 memory array is inaccessible. After starting the write operation (taking CS low) the host can implement a 10ms timeout routine or alternatively it can employ a polling routine that tests the state of the DO pin. After starting the write, testing for the status is easily accomplished by taking CS high and testing the state of DO. If it is low the device is still busy with the internal write. If it is high the write operation has completed. For the polling routine the host has the option of toggling CS for each test of DO, or it can place CS high and then intermittently test DO. SK is not required for any of these operations. Once the device is ready, it will continue to drive DO high whenever the S93WD462/WD463 is selected. The ready state of DO can be cleared by clocking in a start bit; this start bit can either be the beginning of a new command sequence or it can be a dummy start bit with CS returning low before the host issues a new command. SK 2029 ILL 13.0 CS DI DO tCS HIGH-Z HIGH-Z STATUS CLEARED BUSY READY STATUS VERIFY tSV tHZ tEW

ORDERING INFORMATION

S93WD463 = 16-bit configuration S93WD462 = 8-bit configuration Tape and Reel Option Blank = Tube T = Tape and Reel Package P = 8 Lead PDIP S = 8 Lead 150mil SOIC Operating Voltage Range A = 4.5V to 5.5V V TRIP Min. @ 4.25V B = 4.5V to 5.5V VTRIP Min. @ 4.50V P -2.7 T 2029 ILL11.1

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 1998 SUMMIT Microelectronics, Inc.