S9318 SUMMIT | Alldatasheet

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SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com © SUMMIT MICROELECTRONICS, Inc. 1999 2016-04 4/24/99 Characteristics subject to change without notice SUMMIT MICROELECTRONICS, Inc.

FEATURES

  • Digitally Controlled Electronic Potentiometer
  • 8-Bit Digital-to-Analog Converter (DAC) – Independent Reference Inputs – Differential Non-Linearity - ±0.5LSB max – Integral Non-Linearity - ±1LSB max
  • V OUT Value in E2PROM for Power-On Recall – Equivalent to 256-Step Potentiometer
  • Unity Gain Op Amp Drives up to 1mA
  • Simple Trimming Adjustment – Up/Down Counter Style Operation
  • Low Noise Operation
  • “Clickless” Transitions between DAC Steps
  • No Mechanical Wearout Problem – 1,000,000 Stores (typical) – 100 Year Data Retention
  • Operation from +2.7V to +5.5V Supply
  • Low Power, 1mW max at +5V Nonvolatile DACPOT™ Electronic Potentiometer With Up/Down Counter Interface S9318 OVERVIEW The S9318 DACPOT™ trimmer is an 8-bit nonvolatile DAC designed to replace mechanical potentiometers. The S9318 includes a unity-gain amplifier to buffer the DAC output and enables V OUT to swing from rail to rail. The DACPOT trimmer operates over a supply voltage range of 2.7V to 5.5V. The S9318’s simple up/down counter input provides an ideal interface for automatic test equipment to dither and monitor the V OUT voltage. This interface allows for quick and consistent calibration of even the most sophisticated systems. The S9318 is a pin-compatible performance upgrade for other industry nonvolatile potentiometers. The S9318 offers double the resolution of these devices and provides ‘clickless’ transitions of V OUT . FUNCTIONAL BLOCK DIAGRAM Counter Write Control INC UP/DN CS GND VH VOUT VDD 8-bit E2 PROM VL 8-bit Data Register 8-bit DAC 2016 ILL2.1 AMP

The S9318 is an 8-bit, voltage output digital-to-analog converter (DAC). The DAC consists of a resistor network that converts an 8-bit value into equivalent analog output voltages in proportion to the applied reference voltage. Reference Inputs The voltage differential between the V L and VH inputs sets the full-scale output voltage range. VL must be equal to or greater than ground (i.e. a positive voltage). VH must be greater than VL and less than or equal to VDD . See table on page 3 for guaranteed operating limits. Output Buffer Amplifier The voltage output is a precision unity-gain follower that can slew up to 1V/µs. Digital Interface The interface is designed to emulate a simple up/down counter, but instead of a parallel count output, a ratiometric voltage output is provided. PINOUT Chip Select (CSCSCSCSCS) is an active low input. Whenever CS is high the S9318 is in standby mode and consumes the least power. This mode is equivalent to a potentiometer that is adjusted to the required setting. When CS is low the S9318 will recognize transitions on the INC input and will move the V OUT either toward the VH reference or toward the VL reference depending upon the state of the UP/DN input. The host may exit an adjustment routine in two ways: deselecting the S9318 while INC is low will not perform a store operation (a subsequent power cycle will recall the original data); deselecting the S9318 while INC is high will store the current V OUT setting into nonvolatile memory. Increment (INCINCINCINCINC) is an edge triggered input. Whenever CS is low and a high to low transition occurs on the INC input, the VOUT voltage will either move toward VH or VL depending upon the state of the UP/DN input. UP/Down (UP/DNDNDNDNDN) is an input that will determine the VOUT movement relative to VH and VL. When CS is low, UP/DN is high and there is a high to low transition on INC, the VOUT voltage will move (1/256th x VH -VL) toward VH . When CS and UP/DN are low, and there is a high to low transition on INC, the VOUT will move (1/256th x VH -VL) toward VL. INC UP/DN VH GND 2016 ILL1.1 VDD CS VL VOUT PIN NAMES Symbol Description INC Increment Input, High to Low Edge Trigger UP/DN Up/Down Input controlling relative VOUT movement VH V+ reference input GND Analog and Digital Ground VOUT Trimmed Voltage Output VL V- reference input CS Active low chip select input VDD Supply Voltage (2.7V to 5.5V)

ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias -55 °C to +125°C Storage Temperature -65 °C to +150°C Voltage on pins with reference to GND: Analog Inputs -0.5V to V DD +.5V Digital Inputs -0.5V to VDD +.5V Analog Outputs -0.5V to V DD +.5V Digital Outputs -0.5V to V DD +.5V Lead Solder Temperature (10 secs) 300 °C *COMMENT Stresses above those listed under Absolute Maxi- mum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the opera- tion sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Symbol Parameter Conditions Min. Typ. Max. Units Accuracy INL Integral Non-Linearity I LOAD = 100µA, - 0.5 ±1 LSB DNL Differential Non-Linearity ILOAD = 100µA, - 0.1 ±0.5 LSB Guaranteed but not tested References VH VrefH Input Voltage V refL -V DD V VL VrefL Input Voltage Gnd - V refH V R IN VrefH to VrefL Resistance - 38K - Ω TCR IN Temperature Coefficient VrefH to VrefL - 600 - ppm/ °C of RIN Analog G EFS Full-Scale Gain Error DATA = FF - - ±1 LSB Output VOUT ZS Zero-Scale Output Voltage DATA = 00 0 20 mV TCV OUT VOUT Temperature V DD = +5, ILOAD = 50µA, Coefficient V refH = +5V, VrefL = 0V - - 50 µV/°C Guaranteed but not tested IL Amplifier Output Load Current -200 +1000 µA R OUT Amplifier Output ResistanceIL = 100µA VDD = +5V - 10 Ω VDD = +3V - 20 Ω PSRR Power Supply Rejection I LOAD = 10µA - - 1 LSB/V eN Amplifier Output Noise f = 1KHz, VDD = +5V - 90 - nV/ H Z THD Total Harmonic Distortion V IN = 1V rms, f = 1KHz - 0.08 - % BW Bandwidth - 3dB V IN = 100mV rms - 300 - kHz DAC DC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VrefH = VDD , VrefL = 0V, TA = -40°C to +85°C, unless specified otherwise 2016 PGM T3.4 Condition Min Max Temperature -40 °C +85 °C VDD +2.7V +5.5V RECOMMENDED OPERATING CONDITIONS 2016 PGM T1.1

Symbol Parameter Conditions Min Max Units IDD Supply Current CS = V IL 1.2 mA during store, note 1 ISB Supply Standby Current CS = V IH 200 µA IIH Input Leakage Current V IN = VDD 10 µA IIL Input Leakage Current, note 2 V IN = 0V -25 µA VIH High Level Input Voltage 2 V DD V VIL Low Level Input Voltage 0 0.8 V 2016 PGM T4.3 DC ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, VH = VDD , VL = 0V, Unless otherwise specified Notes: 1. IDD is the supply current drawn while the EEPROM is being updated. IDD does not include the current that flows through the Reference resistor chain. 2. CS, UP/DN and INC have internal pull-up resistors of approximately 200kΩ . When the input is pulled to ground the resulting output current will be VDD /200kΩ . Symbol Parameter Min Max Unit Test Method VZAP ESD Susceptibility 2000 V MS-883, TM 3015 ILTH Latch-Up 100 mA JEDEC Standard 17 TDR Data Retention 100 Years MS-883, TM 1008 N END Endurance 1,000,000 Stores MS-883, TM 1033 RELIABILITY CHARACTERISTICS 2016 PGM T2.0

INCINCINCINCINC CSCSCSCSCS UP/DNDNDNDNDN Operation HITO LO L H V OUT toward VH HITO LO L L V OUT toward VL HL O TO HI X Store Setting LL O TO HI X Maintain Setting, NO Store VDD VDD VDD Standby 2016 PGM T5.1 OPERATIONAL TRUTH TABLE Symbol Parameter Min Max Units tCLIL CS to INC Setup 100 ns tIHDC INC High to UP/DN Change 100 ns tDCIL UP/DN to INC Setup 100 ns tIL INC Low Period 200 ns tIH INC High Period 200 ns tIHCH INC Inactive to CS Inactive 100 ns tWP Write Cycle Time 5 ms tILVOUT INC to VOUT Delay 5 µs 2016 PGM T6.1 AC TIMING CHARACTERISTICS V DD = +4.5V to +5.5V AC TIMING DIAGRAM tCLIL tIL tIHDC tIH tIHDHLD tIHCH tWP tILVOUT CS INC UP/DN VOUT 2016 ILL3.1

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 1999 SUMMIT Microelectronics, Inc.

8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

ORDERING INFORMATION

.228 (5.80) .035 (.90) .020 (.50) .010 (.25) x45° .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .275 (6.99) TYP. .030 (.762) TYP.

8 Places

.050 (1.27) TYP. .050 (1.270) TYP. .157 (4.00) .150 (3.80) .196 (5.00)1 .189 (4.80) FOOTPRINT 8pn JEDEC SOIC ILL.2 Package S = 8 Pin SOICBase Part Number S9318 S 2016 ILL4.1