S80KS2562

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• PDF pages: 54

Technical content

Features

• I n t e r f a c e -H Y P E R B U S ™ I n t e r f a c e - 1.8 V Interface support
• Single-ended clock (CK) - 11 bus signals
• Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) -H a r d w a r e r e s e t ( R E S E T # ) - Bidirectional read-write data strobe (RWDS)
• Output at the start of all transactions to indicate refresh latency
• Output during read transactions as read data strobe
• Input during write transactions as write data mask
• Performance, power, and packages - 200-MHz maximum clock rate - DDR - transfers data on both edges of the clock - Data throughput up to 400 MBps (3,200 Mbps) - Configurable burst characteristics
• L i n e a r b u r s t
• Wrapped burst lengths: 16 bytes (8 clocks) 32 bytes (16 clocks) 64 bytes (32 clocks) 128 bytes (64 clocks)
• Hybrid option - one wrapped burst followed by linear burst - Configurable output drive strength -P o w e r m o d e s
• Hybrid sleep mode
• Deep power down -A r r a y r e f r e s h
• Partial memory array(1/8, 1/4, 1/2, and so on)
• F u l l -P a c k a g e
• 24-ball FBGA - Operating temperature range
• I n d u s t r i a l ( I ) : –40 °C to +85 °C
• Industrial Plus (V): –40 °C to +105 °C
• Automotive, AEC-Q100 Grade 3: –40 °C to +85 °C
• Automotive, AEC-Q100 Grade 2: –40 °C to +105 °C
• Automotive, AEC-Q100 Grade 1: –40 °C to +125 °C
• Technology - 25-nm DRAM

Datasheet 2 of 54 002-31337 Rev. *C 2021-09-27

256 Mb: HYPERRAM™ self-refresh dynamic RAM (DRAM) with HYPERBUS™

1.8 V Performance summary Performance summary Logic block diagram Read transaction timings Unit Maximum clock rate at 1.8 V VCC/VCCQ 200 MHz Maximum access time (tACC) 35 ns Maximum current consumption Unit Burst read or write (linear burst at 200 MHz) 20 mA/22 mA Standby (105 °C) 1.55 mA Deep power down (105 °C) 15 μA Memory Control Logic Data Path X Decoders CS# CK/CK# RWDS DQ[7:0] RESET# I/O Y Decoders Data Latch

Datasheet 3 of 54 002-31337 Rev. *C 2021-09-27 Table of contents 1.8 V Table of contents

Datasheet 4 of 54 002-31337 Rev. *C 2021-09-27 Table of contents 1.8 V

Datasheet 5 of 54 002-31337 Rev. *C 2021-09-27 1.8 V General description

1 General description

The 256 Mb HYPERRAM™ device is a high-speed CMOS, self-refresh DRAM, with HYPERBUS™ interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS™ interface master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as pseudo static RAM (PSRAM). Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed. The host must confine the duration of transactions and allow additional initial access latency, at the beginning of a new transaction, if the memory indicates a refresh operation is needed.

1.1 HYPERBUS™ interface

HYPERBUS™ is a low signal count, DDR interface, that achieves high-speed read and write throughput. The DDR protocol transfers two data bytes per clock cycle on the DQ[7:0] input/output signals. A read or write transaction on HYPERBUS™ consists of a series of 16-bit wide, one clock cycle data transfers at the internal HYPERRAM™ array with two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. All inputs and outputs are LV-CMOS compatible. Device are available as 1.8 V V CC/(VCCQ (nominal) for array (VCC) and I/O buffer (VCCQ) supplies, through different ordering part numbers (OPN). Command, address, and data information is transferred over the eight HYPERBUS™ DQ [7:0] signals. The clock (CK#, CK) is used for information capture by a HYPERBUS™ slave device when receiving command, address, or data on the DQ signals. Command or address values are center-aligned with clock transitions. Every transaction begins with the assertion of CS# and command-address (CA) signals, followed by the start of clock transitions to transfer six CA bytes, followed by initial access latency and either read or write data transfers, until CS# is deasserted. Figure 1 Read transaction, single initial latency count The RWDS is a bidirectional signal that indicates:

• when data will start to transfer from a HYPERRAM™ device to the master device in read transactions (initial read latency)
• when data is being transferred from a HYPERRAM™ device to the master device during read transactions (as a source synchronous read data strobe)
• when data may start to transfer from the master device to a HYPERRAM™ device in write transactions (initial write latency)
• data masking during write data transfers CS# CK,CK# RWDS DQ[7:0] tRWR=Read Write Recovery t ACC = Access Latency Count Command-Address 47:40 39:32 31:24 23:16 15:8 7:0 High = 2x Latency Count Low = 1x Latency Count Dn A Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and Memory drives RWDS Memory drives DQ[7:0] and RWDS RWDS and Data are edge aligned

Datasheet 6 of 54 002-31337 Rev. *C 2021-09-27 1.8 V General description During the CA transfer portion of a read or write transaction, RWDS acts as an output from a HYPERRAM™ device to indicate whether additional initial access latency is needed in the transaction. During read data transfers, RWDS is a read data strobe with data values edge-aligned with the transitions of RWDS. Figure 2 Read transaction, additional latency count During write data transfers, RWDS indicates whether each data byte transfer is masked with RWDS HIGH (invalid and prevented from changing the byte location in a memory) or not masked with RWDS Low (valid and written to a memory). Data masking may be used by the host to byte align write data within a memory or to enable merging of multiple non-word aligned writes in a single burst write. During write transactions, data is center-aligned with clock transitions. Figure 3 Write transaction, single initial latency count Read and write transactions are burst oriented, transferring the next sequential word during each clock cycle. Each individual read or write transaction can use either a wrapped or linear burst sequence. Figure 4 Linear versus wrapped burst sequence CS# #KC ,KC RWDS DQ[7:0] tRWR=Read Write Recovery tACC = AccessAdditional Latency Latency Count 1 Latency Count 2 Command-Address 47:40 39:32 31:24 23:16 15:8 7:0 High = 2x Latency Count Low = 1x Latency Count Dn A Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and Memory drives RWDS Memory drives DQ[7:0] and RWDS RWDS and Data are edge aligned CS# #KC ,KC RWDS DQ[7:0] tRWR =Read Write Recovery tACC = Access Latency Count Command-Address 47:40 39:32 31:24 23:16 15:8 7:0 High = 2x Latency Count Low = 1x Latency Count Dn A Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and Memory drives RWDS Host drives DQ[7:0] and RWDS CK and Data are center aligned 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh0h 1h 2h 3h 16 word group alignment boundaries Initial address = 4h Linear Burst Wrapped Burst

Datasheet 7 of 54 002-31337 Rev. *C 2021-09-27 1.8 V General description During wrapped transactions, accesses start at a selected location and continue to the end of a configured word group aligned boundary, then wrap to the beginning location in the group, then continue back to the starting location. Wrapped bursts are generally used for critical word first cache line fill read transactions. During linear transactions, accesses start at a selected location and continue in a sequential manner until the transaction is terminated when CS# returns HIGH. Linear transactions are generally used for large contiguous data transfers such as graphic images. Since each transaction command selects the type of burst sequence for that transaction, wrapped and linear bursts transactions can be dynamically intermixed as needed.

Datasheet 8 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Product overview 2P r o d u c t o v e r v i e w The 256 Mb HYPERRAM™ device is 1.8 V array and I/O, synchronous self-refresh DRAM. The HYPERRAM™ device provides a HYPERBUS™ slave interface to the host system. The HYPERBUS™ interface has an 8-bit (1 byte) wide DDR data bus and use only word-wide (16-bit data) address boundaries. Read transactions provide 16 bits of data during each clock cycle (8 bits on both clock edges). Write transactions take 16 bits of data from each clock cycle (8 bits on each clock edge). Figure 5 HYPERRAM™ interface [1]

2.1 HYPERBUS™ interface

Read and write transactions require two clock cycles to define the target row address and burst type, then an initial access latency of tACC. During the CA part of a transaction, the memory will indicate whether an additional latency for a required refresh time (tRFH) is added to the initial latency; by driving the RWDS signal to the HIGH state. During the CA period, the third clock cycle will specify the target word address within the target row. During a read (or write) transaction, after the initial data value has been output (or input), additional data can be read from (or written to) the row on subsequent clock cycles in either a wrapped or linear sequence. When configured in linear burst mode, the device will automatically fetch the next sequential row from the memory array to support a continuous linear burst. Simultaneously accessing the next row in the array while the read or write data transfer is in progress, allows for a linear sequential burst operation that can provide a sustained data rate of 400 MBps [1b y t e ( 8 b i t d a t a b u s ) * 2 (data clock edges) * 200 MHz = 400 MBps]. CS# CK# CK DQ[7:0] RWDS VSS VSSQ VCC VCCQ RESET# Note 1. CK# is used in differential clock mode, but optional.

Datasheet 9 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Signal description

3 Signal description

3.1 Input/output summary

HYPERRAM™ signals are shown in Table 1. Active Low signal names have a hash symbol (#) suffix. Table 1 I/O summary Symbol Type Description CS# Input Chip select. Bus transactions are initiated with a HIGH to LOW transition. Bus transactions are terminated with a LOW to HIGH transition. The master device has a separate CS# for each slave. CK, CK# [2] Input Differential clock. Command, address, and data information is output with respect to the crossing of the CK and CK# signals. Use of differential clock is optional. Single ended clock. CK# is not used, only a single ended CK is used. The clock is not required to be free-running. DQ[7:0] Input/output Data input/output. Command, address, and data information is transferred on these signals during Read and Write transactions. RWDS Input/output Read-write data strobe. During the command/address portion of all bus transactions, RWDS is a slave output and indicates whether additional initial latency is required. Slave outp ut during read data transfer, data is edge-aligned with RWDS. Slave input during data transfer in write transactions to function as a data mask. (HIGH = additional latency, LOW = no additional latency). RESET# Input, internal pull-up Hardware RESET . When LOW, the slave device will self initialize and return to the STANDBY state. RWDS and DQ[7:0] are placed into the H I G H - Z s t a t e w h e n R E S E T # i s L O W . The slave RESET# input includes a weak pull-up, if RESET# is left unconnected it will be pulled up to the HIGH state. V CC Power supply Array power. VCCQ Power supply Input/output power. VSS Power supply Array ground. VSSQ Power supply Input/output ground. RFU No connect Reserved for future use. May or may not be connected internally, the signal/ball location should be left unconnected and unused by PCB routing channel for future compatibility. The signal/ball may be used by a signal in the future. Note 2. CK# is used in differential clock mode, but opti onal connection. Tie the CK# input pin to either V CCQor VSSQ if not connected to the host controller, but do not leave it floating.

Datasheet 10 of 54 002-31337 Rev. *C 2021-09-27 1.8 V HYPERBUS™ transaction details

4 HYPERBUS™ transaction details

4.1 Command/address bit assignments

All HYPERRAM™ bus transactions can be classified as either read or write. A bus transaction is started with CS# going LOW with clock in idle state (CK = LOW and CK# = HIGH). The first three clock cycles transfer three words of command/address (CA0, CA1, CA2) information to define the transaction characteristics. The Command/Address words are presented with DDR timing, using the first six clock edges. The following characteristics are defined by the command/address information:

• Read or write transaction
• Address space: memory array space or register space - Register space is used to access device identification (ID) registers and configuration registers (CR) that identify the device characteristics and determine the slave specific behavior of read and write transfers on the HYPER- BUS™ interface.
• Whether a transaction will use a linear or wrapped burst sequence.
• The target row (and half-page) address (upper order address)
• The target column (word within half-page) address (lower order address) Figure 6 Command-address (CA) sequence [3-6] Table 2 CA bit assignment to DQ signals Signal CA0[47:40] CA0[39:32] CA1[31:24] CA1[23:16] CA2[15:8] CA2[7:0] DQ[7] CA[47] CA[39] CA[31] CA[23] CA[15] CA[7] DQ[6] CA[46] CA[38] CA[30] CA[22] CA[14] CA[6] DQ[5] CA[45] CA[37] CA[29] CA[21] CA[13] CA[5] DQ[4] CA[44] CA[36] CA[28] CA[20] CA[12] CA[4] DQ[3] CA[43] CA[35] CA[27] CA[19] CA[11] CA[3] DQ[2] CA[42] CA[34] CA[26] CA[18] CA[10] CA[2] DQ[1] CA[41] CA[33] CA[25] CA[17] CA[9] CA[1] DQ[0] CA[40] CA[32] CA[24] CA[16] CA[8] CA[0] CS# CK# , CK Notes 3. Figure 6 shows the initial three clock cycles of all transactions on the HYPERBUS™. 4. CK# of differential clock is shown as dashed line waveform. 5. CA information is “center-aligned” with the clock during both read and write transactions. 6. Data bits in each byte are always in high to low order with bit 7 on DQ7 and bit 0 on DQ0.

Datasheet 11 of 54 002-31337 Rev. *C 2021-09-27 1.8 V HYPERBUS™ transaction details Table 3 Command/Address bit assignments [7-10] CA bit# Bit name Bit function

47 R/W#

Identifies the transaction as a read or write. R/W# = 1 indicates a read transaction R/W# = 0 indicates a write transaction

46 Address space

(AS) Indicates whether the read or write transaction accesses the memory or register space. AS = 0 indicates memory space AS = 1 indicates the register space The register space is used to access device ID and configuration registers.

45 Burst type

Indicates whether the burst will be linear or wrapped. Burst type = 0 indicates wrapped burst Burst type = 1 indicates linear burst 44-16 Row & upper column address Row & upper column component of the target address: system word address bits A31-A3 Any upper Row address bits not used by a particular device density should be set to 0 by the host controller master interface. The size of rows and therefore the address bit boundary between row and column address is slave device dependent. 15-3 Reserved Reserved for future column address expansion. Reserved bits are don’t care in current HYPERBUS™ devices but should be set to 0 by the host controller master interface for future compatibility. 2-0 Lower column address Lower column component of the target address: system word address bits A2-A0 selecting the starting word within a half-page. Notes 7. A row is a group of words relevant to the internal memo ry array structure. The number of rows is also used in the calculation of a distributed refresh interval for HYPERRAM™ memory. 8. The column address selects the burst transaction starti ng word location within a row. The column address is split into an upper and lower portion. The upper portion selects an 8-word (16-byte) half-page and the lower portion selects the word within a half-page where a read or write transaction burst starts. 9. The initial read access time starts when the row and upper column (half-page) address bits are captured by a slave interface. Continuous linear read burst is enabled by memory devices internally interleaving access to 16 byte half-pages. 10. HYPERBUS™ protocol address space limit, assuming:

29 Row & upper column address bits

3 Lower column address bits

Each address selects a word wide (16 bit = 2 byte) data value 29 + 3 = 32 address bits = 4G addresses supporting 8GB (64Gb) maximum address space Future expansion of the column address can allow for 29 row &upper column + 16 lower column address bits = 35 Tera-word = 70 Tera-byte address space.

Datasheet 12 of 54 002-31337 Rev. *C 2021-09-27 1.8 V HYPERBUS™ transaction details Figure 7 Data placement during a read transaction [11-15] Data placement during memory read/write is dependent upon the host. The device will output data (read) as it was written in (write). Hence both Big Endian and Little Endian are supported for the memory array. Data placement during register read/write is Big Endian. CS# CK# , CK RWDS DQ[7:0] Dn A Dn B Dn+1 A Dn+1 B Dn+2 A Notes 11. Figure 7 shows a portion of a read transaction on the HYPERBUS™. CK# of differential clock is shown as dashed line waveform. 12. Data is “edge-aligned” with the RWDS serving as a read data strobe during read transactions. 13. Data is always transferred in full word increments (word granularity transfers). 14. Word address increments in each clock cycle. Byte A is between RWDS rising and falling edges and is followed by byte B between RWDS falling and rising edges, of each word. 15. Data bits in each byte are always in high to low order with bit 7 on DQ7 and bit 0 on DQ0.

Datasheet 13 of 54 002-31337 Rev. *C 2021-09-27 1.8 V HYPERBUS™ transaction details Table 4 Data bit placement during read or write transaction Address space Byte order Byte position Word data bit DQ Bit order Memory Big- endian A 15 7 When data is being accessed in memory space: The first byte of each word read or written is the “A” byte and the second is the “B” byte. The bits of the word within the A and B bytes depend on how the data was written. If the word lower address bits 7-0 are written in the A byte position and bits 15-8 are written into the B byte position, or vice versa, they will be read back in the same order. Memory space can be stored and read in either little-endian or big-endian order. 14 6 13 5 12 4 11 3 10 2 B Little- endian A B 15 7 14 6 13 5 12 4 11 3 10 2

Datasheet 14 of 54 002-31337 Rev. *C 2021-09-27 1.8 V HYPERBUS™ transaction details Figure 8 Data placement during a write transaction [16-19] Register Big- endian A 15 7 When data is being accessed in register space: During a read transaction on the HYPERBUS™ two bytes are trans- ferred on each clock cycle. The upper order byte A (Word[15:8]) is transferred between the rising and falling edges of RWDS (edge-aligned). The lower order byte B (Word[7:0]) is transferred between the falling and rising edges of RWDS. During a write, the upper order byte A (Word[15:8]) is transferred on the CK rising edge and the lower order byte B (Word[7:0]) is trans- ferred on the CK falling edge. So, register space is always read and written in Big-endian order because registers have device dependent fixed bit location and meaning definitions. 14 6 13 5 12 4 11 3 10 2 B Table 4 Data bit placement during read or write transaction (continued) Address space Byte order Byte position Word data bit DQ Bit order CS# CK# , CK RWDS DQ[7:0] Dn A Dn B Dn+1 A Dn+1 B Dn+2 A Notes 16. Figure 8 shows a portion of a write transaction on the HYPERBUS™. 17. Data is “center-aligned” with the clock during a write transaction. 18. RWDS functions as a data mask during write data transfers with initial latency. Masking of the first and last byte is shown to illustrate an unaligned 3 byte write of data. 19. RWDS is not driven by the master during write data transfers with zero initial latency. Full data words are always written in this case. RWDS may be driven LOW or left HIGH-Z by the slave in this case.

Datasheet 15 of 54 002-31337 Rev. *C 2021-09-27 1.8 V HYPERBUS™ transaction details

4.2 Read transactions (Memory array and registers)

The HYPERBUS™ master begins a transaction by driving CS# LOW while clock is idle. The clock then begins toggling while CA words are transferred. In CA0, CA[47] = 1 indicates that a read transaction is to be performed. CA[46] = 0 indicates the memory space is being read or CA[46] = 1 indicates the register space is being read. CA[45] indicates the burst type (wrapped or linear). Read transactions can begin the internal array access as soon as the row and upper column address has been presented in CA0 and CA1 (CA[47:16]). CA2 (CA(15:0]) identifies the target word address within the chosen row. The HYPERBUS™ master then continues clocking for a number of cycles defined by the latency count setting in configuration register 0. The initial latency count required for a particular clock frequency is based on RWDS. If RWDS is LOW during the CA cycles, one latency count is inserted. If RWDS is HIGH during the CA cycles, an additional latency count is inserted. Once these latency clocks have been completed the memory starts to simul- taneously transition the RWDS and output the target data. New data is output edge-aligned with every transition of RWDS. Data will continue to be output as long as the host continues to transition the clock while CS# is LOW. Note that burst transactions should not be so long as to prevent the memory from doing distributed refreshes. Wrapped bursts will continue to wrap within the burst length and linear burst will output data in a sequential manner across row boundaries. When a linear burst read reaches the last address in the array, continuing the burst beyond the last address will provide data from the beginning of the address range. Read transfers can be ended at any time by bringing CS# HIGH when the clock is idle. The clock is not required to be free-running. The clock may remain idle while CS# is HIGH. Figure 9 Read transaction with additional initial latency [20-28] CS# CK, CK# RWDS DQ[7:0] tRWR = Read Write Recovery tACC = Access Additional Latency Latency Count 1 Latency Count 2 Command-Address 47:40 39:32 31:24 23:16 15:8 7:0 High = 2x Latency Count Low = 1x Latency Count Dn A Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and Memory drives RWDS Memory drives DQ[7:0] and RWDS RWDS and Data are edge aligned Notes 20. Transactions are initiated with CS# falling while CK = LOW and CK# = HIGH. 21. CS# must return HIGH before a new transaction is initiated. 22. CK# is the complement of the CK signal.CK# of a differential clock is shown as a dashed line waveform. 23. Read access array starts once CA[23:16] is captured. 24. The read latency is defined by the initial latency value in a configuration register. 25. In this read transaction example the initial latency count was set to four clocks. 26. In this read transaction a RWDS HIGH indication during CA delays output of target data by an additional four clocks. 27. The memory device drives RWDS during read transactions. 28. For register read, the output data Dn A is RG[15:8], Dn B is RG[7:0], Dn+1 A is RG[15:8], Dn+1 B is RG[7:0].

Datasheet 16 of 54 002-31337 Rev. *C 2021-09-27 1.8 V HYPERBUS™ transaction details Figure 10 Read transaction without additional initial latency [29, 30]

4.3 Write transactions (Memory array write)

The HYPERBUS™ master begins a transaction by driving CS# LOW while clock is idle. Then the clock begins toggling while CA words are transferred. In CA0, CA[47] = 0 indicates that a write transaction is to be performed. CA[46] = 0 indicates the memory space is being written. CA[45] indicates the burst type (wrapped or linear). Write transactions can begin the internal array access as soon as the row and upper column address has been presented in CA0 and CA1 (CA[47:16]). CA2 (CA(15:0]) identifies the target word address within the chosen row. The HYPERBUS™ master then continues clocking for a number of cycles defined by the latency count setting in configuration register 0. The initial latency count required for a particular clock frequency is based on RWDS. If RWDS is LOW during the CA cycles, one latency count is inserted. If RWDS is HIGH during the CA cycles, an additional latency count is inserted. Once these latency clocks have been completed, the HYPERBUS™ master starts to output the target data. Write data is center-aligned with the clock edges. The first byte of data in each word is captured by the memory on the rising edge of CK and the second byte is captured on the falling edge of CK. During the CA clock cycles, RWDS is driven by the memory. During the write data transfers, RWDS is driven by the host master interface as a data mask. When data is being written and RWDS is HIGH, the byte will be masked and the array will not be altered. When data is being written and RWDS is LOW, the data will be placed into the array. Because the master is driving RWDS during write data transfers, neither the master nor the HYPERRAM™ device are able to indicate a need for latency within the data transfer portion of a write transaction. The acceptable write data burst length setting is also shown in configu- ration register 0. Data will continue to be transferred as long as the HYPERBUS™ master continues to transition the clock while CS# is LOW. Note that burst transactions should not be so long as to prevent the memory from doing distributed refreshes. Legacy format wrapped bursts will continue to wrap within the burst length. Hybrid wrap will wrap once then switch to linear burst starting at the next wrap boundary. Linear burst accepts data in a sequential manner across page boundaries. Write transfers can be ended at any time by bringing CS# HIGH when the clock is idle. CS# CK#, CK RWDS DQ[7:0] t RWR =Read Write Recovery t ACC = Initial Access 4 cycle latency Command-Address 47:40 39:32 31:24 23:16 15:8 7:0 High = 2x Latency Count Low = 1x Latency Count Dn A Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and Memory drives RWDS Memory drives DQ[7:0] and RWDS RWDS and Data are edge aligned Notes 29. RWDS is LOW during the CA cycles. In this read transaction, there is a single initial latency count for read data access because, this read transaction does not begin at a time when additional latency is required by the slave. 30 For register read the output data Dn A is RG[15:8] Dn B is RG[7:0] Dn+1 A is RG[15:8] Dn+1 B is RG[7:0]

Datasheet 17 of 54 002-31337 Rev. *C 2021-09-27 1.8 V HYPERBUS™ transaction details When a linear burst write reaches the last address in the memory array space, continuing the burst will write to the beginning of the address range. The clock is not required to be free-running. The clock may remain idle while CS# is HIGH. Figure 11 Write transaction with additional initial latency[31-37] Figure 12 Write transaction with out additional initial latency[33-37] CS# CK#, CK RWDS DQ[7:0] tRWR = Read Write Recovery tACC = Initial Access Additional Latency Latency Count 1 Latency Count 2 Command-Address 47:40 39:32 31:24 23:16 15:8 7:0 High = 2x Latency Count Low = 1x Latency Count Dn A Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and Memory drives RWDS CK and Data are center aligned Host drives DQ[7:0] and RWDS Notes 31. Transactions must be initiated with CK = LOW and CK# = HIGH. 32. CS# must return HIGH before a new transaction is initiated. 33. During CA, RWDS is driven by the memory and indicates whether additional latency cycles are required. 34. In this example, RWDS indicates that additional initial latency cycles are required. 35. At the end of CA cycles the memory stops driving RWDS to allow the host HYPERBUS™ master to begin driving RWDS. The master must drive RWDS to a valid LOW before the end of the initial latency to provide a data mask preamble period to the slave. 36. During data transfer, RWDS is driven by the host to indicate which bytes of data should be either masked or loaded into the array. 37. The figure shows RWDS masking byte Dn A and byte Dn+1 B to perform an unaligned word write to bytes Dn B and Dn+1 A. CS# CK, CK# RWDS DQ[7:0] tRWR=Read Write Recovery tACC = Access Latency Count Command-Address 47:40 39:32 31:24 23:16 15:8 7:0 High = 2x Latency Count Dn A Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and Memory drives RWDS Host drives DQ[7:0] and RWDS CK and Data are center aligned Low = 1x Latency Count

Datasheet 18 of 54 002-31337 Rev. *C 2021-09-27 1.8 V HYPERBUS™ transaction details

4.4 Write transactions (Register write)

A write transaction starts with the first three clock cycles providing the command/address information indicating the transaction characteristics. CA0 may indicate that a write transaction is to be performed and also indicates the address space and burst type (wrapped or linear). Writes without initial latency are used for register space writes. HYPERRAM™ device write transactions with zero latency mean that the CA cycles are followed by write data transfers. Writes with zero initial latency, do not have a turn around period for RWDS. The HYPERRAM™ device will always drive RWDS during the CA period to indicate whether extended latency is required for a transaction that has initial latency. However, the RWDS is driven before the HYPERRAM™ device has received the first byte of CA i.e., before the HYPERRAM™ device knows whether the transaction is a read or write to register space. In the case of a write with zero latency, the RWDS state during the CA period does not affect the initial latency of zero. Since master write data immediately follows the CA period in this case, the HYPERRAM™ device may continue to drive RWDS LOW or may take RWDS to HIGH-Z during write data transfer. The master must not drive RWDS during Writes with zero latency. Writes with zero latency do not use RWDS as a data mask function. All bytes of write data are written (full word writes). The first byte of data in each word is presented on the rising edge of CK and the second byte is presented on the falling edge of CK. Write data is center-aligned with the clock inputs. Write transfers can be ended at any time by bringing CS# HIGH when clock is idle. The clock is not required to be free-running. Figure 13 Register write operation [38, 39] CK#, CK RWDS DQ[7:0] CA [47:40] CA [39:32] CA [31:24] CA [23:16] CA [15:8] CA [7:0] Command - Address RG [15:8] RG [7:0] Write Data High: 2X Latency Count Low: 1X Latency Count (Host drives DQ[7:0], Memory drives RWDS) Notes 38. Latency is not applicable during the register write. The RWDS driven LOW or HIGH after the CS# LOW should be ignored by the host. The register write data byte immediately follows the last CA byte (zero clock latency). 39. RWDS is not driven by the host during register write. The HyperRAM ignores the RWDS status and always writes full data. RWDS may be driven Low or left High-Z by the slave during write data transfer.

Datasheet 19 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Memory space 5M e m o r y s p a c e

5.1 HYPERBUS™ interface

Table 5 Memory space address map (word based - 16 bits) Unit type Count System word address bits CA bits Notes Rows within 256 Mb device 32768 (rows) A23 - A9 36 - 22 - Row 64 (half-pages) A8 - A3 21 - 16 Each row has 64 half-pages. Each half-page has 8 words. Each column has 512 words (1K bytes). Half-page 8 (words) A2 - A0 2 - 0 Half-page (HP) address is also referenced as upper column address. A word within a HP address is also referenced as lower column address.

Datasheet 20 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Register space 6R e g i s t e r s p a c e

6.1 HYPERBUS™ interface

When CA[46] is 1, a read or write transaction accesses the register space.

6.2 Device identification registers

There are two read only, nonvolatile word registers, that provide information on the device selected when CS# is LOW. The device information fields identify:

• Manufacturer
• T y p e
• D e n s i t y
• R o w a d d r e s s b i t c o u n t
• Column address bit count Table 6 Register space address map Register System address — — — 31-27 26-19 18-11 10-3 — 2-0 CA bits 47 46 45 [40] 44-40 39-32 31-24 23-16 15-8 7-0 Identification register 0 read[41] C0h or E0h 00h 00h 00h 00h 00h Identification register 1 read[41] C0h or E0h 00h 00h 00h 00h 01h Configuration register 0 read C0h or E0h 00h 01h 00h 00h 00h Configuration register 0 write 60h 00h 01h 00h 00h 00h Configuration register 1 read C0h or E0h 00h 01h 00h 00h 01h Configuration register 1 write 60h 00h 01h 00h 00h 01h Notes 40. CA45 may be either 0 or 1 for either wrapped or linear read. CA45 must be 1 as only linear single word register writes are supported. 41. The burst type (wrapped/linear) definition is not supported in register reads. Hence C0h/E0h have the same effect. Table 7 Identification register 0 (ID0) bit assignments Bits Function Settings (Binary) [15:14] MCP die address 00 - Default [13] Reserved 0 - Default [12:8] Row address bit count 01110b - 256 Mb ; fifteen row address bits (256 Mbit) [7:4] Column address bit count 1000b - Ni ne column address bits (default) [3:0] Manufacturer 0110b

Datasheet 21 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Register space

6.2.1 Density and row boundaries

The DRAM array size (density) of the device can be determined from the total number of system address bits used for the row and column addresses as indicated by the row address bit count and column address bit count fields in the ID0 register. For example: a 256 Mb HYPERRAM™ device has 9 column address bits and 15 row address bits for a total of 24 word address bits = 2 24 = 16 Mwords = 32 MB. The 9 column address bits indicate that each row holds 29 = 512 words = 1 KB. The row address bit count indicates there are 32,784 rows to be refreshed within each array refresh interval. The row count is used in calculating the refresh interval. ID0 value for the 256 Mb HYPERRAM™ is 0x0E86.

6.3 Register space access

Register default values are loaded upon power-up or hardware reset. The registers can be altered at any time while the device is in the STANDBY state. Loading a register is accomplished with write transaction without initial latency using a single 16-bit word write transaction. Each register is written with a separate single word write transaction. Register write transactions have zero latency, the single word of data immediately follows the CA. RWDS is not driven by the host during the write because RWDS is always driven by the memory during the CA cycles to indicate whether a memory array refresh is in progress. Because a register space write goes directly to a register, rather than the memory array, there is no initial write latency, related to an array refresh that may be in progress. In a register write, RWDS is also not used as a data mask because both bytes of a register are always written and never masked. Reserved register fields must be written with their default value. Writing reserved fields with other than default values may produce undefined results. Notes

• The host must not drive RWDS during a write to register space.
• The RWDS signal is driven by the memory during the CA period based on whether the memory array is being refreshed. This refresh indication does not affect the writing of register data.
• The RWDS signal returns to high impedance after the CA period. Register data is never masked. Both data bytes of the register data are loaded into the selected register. Reading of a register is accomplished with read transaction with single or double initial latency using a single 16 bit read transaction. If more than one word is read, the output becomes indeterminate. The contents of the register is returned in the same manner as reading the memory array, as shown in Figure 9, with one or two latency counts, based on the state of RWDS during the CA period. The latency count is defined in the configuration register 0 read latency field (CR0[7:4]). Table 8 Identification register 1 (ID1) bit assignments Bits Function Settings (Binary) [15:4] Reserved 0000_0000_0000b (default) [3:0] Device type 0001 - HYPERRAM™ 2.0

Datasheet 22 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Register space

6.3.1 Configuration register 0

Configuration register 0 (CR0) is used to define the power state and access protocol operating conditions for the HYPERRAM™ device. Configurable characteristics include:

• Wrapped burst length (16, 32, 64, or 128 byte aligned and length data group)
• Wrapped burst type - Legacy wrap (Sequential access with wrap around within a selected length and aligned group) - Hybrid wrap (Legacy wrap once then linear burst at start of the next sequential group)
• Initial latency
• V a r i a b l e l a t e n c y - Whether an array read or write transaction will use fixed or variable latency. If fixed latency is selected the memory will always indicate a refresh latency and delay the read data transfer accordingly. If variable latency is selected, latency for a refresh is only added when a refresh is required at the same time a new transaction is starting.
• Output drive strength
• Deep power down (DPD) mode Table 9 Configuration register 0 (CR0) bit assignments CR0 bit Function Settings (Binary) [15] Deep power down enable 1 - Normal operation (default). HYPERRAM™ will automatically set this value to “1” after DPD exit 0 - Writing 0 causes the device to enter deep power down [14:12] Drive strength 000 - 34 ohms (default) 001 - 115 ohms 010 - 67 ohms 011 - 46 ohms 100 - 34 ohms 101 - 27 ohms 110 - 22 ohms 111 - 19 ohms [11:8] Reserved 1 - Reserved (default) Reserved for future use. When writing this register, these bits should be set to 1 for future compatibility. [7:4] Initial latency 0000 - 5 clock latency @ 133 MHz Max frequency 0001 - 6 Clock latency @ 166 MHz Max frequency 0010 - 7 clock latency @ 200 MHz Max frequency (default) 0011 - Reserved 0100 - Reserved ... 1101 - Reserved 1110 - 3 clock latency @ 85 MHz Max frequency 1111 - 4 clock latency @ 104 MHz Max frequency [3] Fixed latency enable 0 - Variable latency - 1 or 2 times initial latency depending on RWDS during CA cycles. 1 - Fixed 2 times initial latency (default)

Datasheet 23 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Register space Wrapped burst A wrapped burst transaction accesses memory within a group of words aligned on a word boundary matching the length of the configured group. Wrapped access groups can be configured as 16, 32, 64, or 128 bytes alignment and length. During wrapped transactions, access starts at the CA selected location within the group, continues to the end of the configured word group aligned boundary, then wraps around to the beginning location in the group, then continues back to the starting location. Wrapped bursts are generally used for critical word first instruction or data cache line fill read accesses. Hybrid burst The beginning of a hybrid burst will wrap within the target address wrapped burst group length before continuing to the next half-page of data beyond the end of the wrap group. Continued access is in linear burst order until the transfer is ended by returning CS# HIGH. This hybrid of a wrapped burst followed by a linear burst starting at the beginning of the next burst group, allows multiple sequential address cache lines to be filled in a single access. The first cache line is filled starting at the critical word. Then the next sequential line in memory can be read in to the cache while the first line is being processed. [2] Hybrid burst enable 0: Wrapped burst sequence to follow hybrid burst sequencing 1: Wrapped burst sequence in legacy wrapped burst manner (default) This bit setting is effective only when the "Burst type" bit in the command/address register is set to '0' , i.e. CA[45] = '0'; otherwise, it is ignored. [1:0] Burst length 00 - 128 bytes 01 - 64 bytes 10- 16 bytes 11 - 32 bytes (default) Table 10 CR0[2] control of wrapped burst sequence Bit Default value Name Hybrid burst enable CR0[2] = 0: Wrapped burst sequence to follow hybrid burst sequencing CR0[2] = 1: Wrapped burst sequence in legacy wrapped burst manner Table 9 Configuration register 0 (CR0) bit assignments (continued) CR0 bit Function Settings (Binary)

Datasheet 24 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Register space Table 11 Example wrapped burst sequences (HYPERBUS™ addressing) Burst type Wrap boundary (bytes) Start address (Hex) Sequence of word addresses (Hex) of data words Hybrid 128 128 wrap once then linear XXXXXX03 3F, 00, 01, 02 (Wrap complete, now linear beyond the end of the initial 128 byte wrap group) Hybrid 64 64 wrap once then linear XXXXXX03 17, 18, 19, 1A, 1B, 1C, 1D, 1E, 1F, 00, 01, 02 (wrap complete, now linear beyond the end of the initial 64 byte wrap group) Hybrid 64 64 wrap once then linear XXXXXX2E 22, 23, 24, 25, 26, 27, 28, 29, 2A, 2B, 2C, 2D (wrap complete, now linear beyond the end of the initial 64 byte wrap group) Hybrid 16 16 wrap once then linear XXXXXX02 02, 03, 04, 05, 06, 07, 00, 01 (wrap complete, now linear beyond the end of the initial 16 byte wrap group) Hybrid 16 16 wrap once then linear XXXXXX0C 0C, 0D, 0E, 0F, 08, 09, 0A, 0B (wrap complete, now linear beyond the end of the initial 16 byte wrap group) Hybrid 32 32 wrap once then linear XXXXXX0A 0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09 (wrap complete, now linear beyond the end of the initial 32 byte wrap group) Wrap 64 64 XXXXXX03 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, Wrap 64 64 XXXXXX2E 2E, 2F, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 3A, 3B, 3C, 3D, 3E, 3F, 20, 21, Wrap 16 16 XXXXXX02 02, 03, 04, 05, 06, 07, 00, 01, ... Wrap 16 16 XXXXXX0C 0C, 0D, 0E, 0F, 08, 09, 0A, 0B, ... Wrap 32 32 XXXXXX0A 0A, 0B, 0C, 0D, 0E, 0F, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, ... Linear Linear burst XXXXXX03 03, 04, 05, 06, 07, 08, 09, 0A, 0B, 0C, 0D, 0E, 0F, 10, 11, 12, 13, 14, 15, 16, 17, 18, ...

Datasheet 25 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Register space Initial latency Memory space read and write transactions or register space read transactions require some initial latency to open the row selected by the CA. This initial latency is tACC. The number of latency clocks needed to satisfy tACC depends on the HYPERBUS™ frequency can vary from 3 to 7 clocks. The value in CR0[7:4] selects the number of clocks for initial latency. The default value is 7 clocks, allowing for operation up to a maximum frequency of 200 MHz prior to the host system setting a lower initial latency value that may be more optimal for the system. In the event a distributed refresh is required at the time a memory space read or write transaction or register space read transaction begins, the RWDS signal goes HIGH during the CA to indicate that an additional initial latency is being inserted to allow a refresh operation to complete before opening the selected row. Register space write transactions always have zero initial latency. RWDS may be HIGH or LOW during the CA period. The level of RWDS during the CA period does not affect the placement of register data immediately after the CA, as there is no initial latency needed to capture the register data. A refresh operation may be performed in the memory array in parallel with the capture of register data. Fixed latency A configuration register option bit CR0[3] is provided to make all memory space read and write transactions or register space read transactions require the same initial latency by always driving RWDS HIGH during the CA to indicate that two initial latency periods are required. This fixed initial latency is independent of any need for a distributed refresh, it simply provides a fixed (deterministic) initial latency for all of these transaction types. The fixed latency option may simplify the design of some HYPERBUS™ memory controllers or ensure deterministic transaction performance. Fixed latency is the default POR or reset configuration. The system may clear this configuration bit to disable fixed latency and allow variable initial latency with RWDS driven HIGH only when additional latency for a refresh is required. Drive strength DQ and RWDS signal line loading, length, and impedance vary depending on each system design. Configuration register bits CR0[14:12] provide a means to adjust the DQ[7:0] and RWDS signal output impedance to customize the DQ and RWDS signal impedance to the system conditions to minimize high speed signal behaviors such as overshoot, undershoot, and ringing. The default POR or reset configuration value is 000b to select the mid point of the available output impedance options. The impedance values shown are typical for both pull-up and pull-down drivers at typical silicon process condi- tions, nominal operating voltage (1.8 V) and 50°C. The impedance values may vary from the typical values depending on the process, voltage, and temperature (PVT) conditions. Impedance will increase with slower process, lower voltage, or higher temperature. Impedance will decrease with faster process, higher voltage, or lower temperature. Each system design should evaluate the data signal integrity across the operating voltage and temperature ranges to select the best drive strength settings for the operating conditions. Deep power down When the HYPERRAM™ device is not needed for system operation, it may be placed in a very low power consuming state called deep power down (DPD), by writing 0 to CR0[15]. When CR0[15] is cleared to 0, the device enters the DPD state within t DPDIN time and all refresh operations stop. The data in RAM is lost, (becomes invalid without refresh) during DPD state. Exiting DPD requires driving CS# LOW then HIGH, POR, or a reset. Only CS# and RESET# signals are monitored during DPD mode. For additional details, see “Deep power down” on page 30.

Datasheet 26 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Register space

6.3.2 Configuration register 1

Configuration register 1 (CR1) is used to define the refresh array size, refresh rate and hybrid sleep for the HYPERRAM™ device. Configurable characteristics include:

• Partial array refresh
• Hybrid sleep state
• R e f r e s h r a t e Master clock type Two clock types, namely single ended and differential, are supported. CR1[6] selects which type to use.
• In the single ended clock mode (by default), CK# input is not enabled; hence it may be left either floating or biased to HIGH or LOW.
• In the differential clock mode (when enabled), the CK# input can't be left floating. It must be either driven by the host, or biased to HIGH or LOW. Partial array refresh The partial array refresh configuration restricts the refresh operation in HYPERRAM™ to a portion of the memory array specified by CR1[5:3]. This reduces the standby current. The default configuration refreshes the whole array. Hybrid sleep (HS) When the HYPERRAM™ is not needed for system operation but data in the device needs to be retained, it may be placed in hybrid sleep state to save more power. Enter hybrid sleep state by writing 1 to CR1[5]. Bringing CS# LOW will cause the device to exit HS state and set CR1[5] to 0. Also, POR, or a hardware reset will cause the device to exit hybrid sleep state. Note that a POR or a hardware reset disables refresh where the memory core data can potentially get lost. Table 12 Configuration regist er 1 (CR1) bit assignments CR1 bit Function Setting (binary) [15:8] Reserved 11111111 - reserved (default) When writing this register, these bits should keep 0xFFh for future compatibility [7] Reserved 1 - reserved (default) [6] Master clock type 1 - single-ended - CK (default) 0 - differential - CK#, CK [5] Hybrid sleep 1 - causes the device to enter hybrid sleep state 0 - normal operation (default) [4:2] Partial array refresh 000 - full array (default) 001 - bottom 1/2 Array 010 - bottom 1/4 Array 011 - bottom 1/8 Array 100 - none 101 - top 1/2 Array 110 - top 1/4 Array 111 - top 1/8 Array [1:0] Distributed refresh interval (read only) 10 - 1μs t CSM (Industrial plus temperature range devices) 11 - reserved 00 - reserved 01 - 4μs tCSM (Industrial temperature range devices)

Datasheet 27 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Register space Distributed refresh interval The HYPERRAM™ device is built with volatile DRAM array which requires periodic refresh of all bits in it. The refresh operation can be done by an internal self-refresh logic that will evenly refresh the memory array automatically. The automatic refresh operation can only be done when the memory array is not actively read or written by the host system. The refresh logic waits for the end of any active read or write before doing a refresh, if a refresh is needed at that time. If a new read or write begins before the refresh is completed, the memory will drive RWDS high during the CA period to indicate that an additional initial latency time is required at the start of the new access in order to allow the refresh operation to complete before starting the new access. The evenly distributed refresh operations require a maximum refresh interval between two adjacent refresh operations. The maximum distributed refresh interval varies with temperature as shown in Table 13. The distributed refresh operation requires that the host does not perform burst transactions longer than the distributed refresh interval to prevent the memory from unable doing the distributed refreshes operation when it is needed. This sets an upper limit on the length of read and write transactions so that the automatic distributed refresh operation can be done between transactions. This limit is called the CS# low maximum time (tCSM) and the tCSM will be equal to the maximum distributed refresh interval. The host system is required to respect the tCSM value by terminating each transaction before violating tCSM. This can be done by host memory controller splitting long transactions when reaching the tCSM limit, or by host system hardware or software not performing a single burst read or write transaction that would be longer than tCSM. As noted in Table 13, the maximum refresh interval is longer at lower temperatures such that tCSM could be increased to allow longer transactions. The host may determine the operating temperature from a temperature sensor in the system and use the tCSM value from the table accordingly, or it may determine dynamically by reading the read only CR1[1:0] bits in order to set the distributed refresh interval prior to the HYPERRAM™ access. Table 13 Array refresh interval per temperature Operating temperature (°C) Refresh interval t CSM (µs) CR1[1:0] TA ≤ 85 °C 4 01b 85 °C < TA ≤ 125 °C 1 10b

Datasheet 28 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Interface states

7 Interface states

Table 14 describes the required value of each signal for each interface state. Legend L = VIL; H = VIH; X = Either VIL or VIH; Y = either VIL or VIH or VOL or VOH; Z = Either VOL or VOH; L/H = Rising edge; H/L = Falling edge; T = Toggling during information transfer; Idle = CK is LOW and CK# is HIGH; Valid = All bus signals have stable L or H level Table 14 Interface states Interface state V CC / VCCQ CS# CK, CK# DQ7-DQ0 RWDS RESET# Power-off < V LKO X X HIGH-Z HIGH-Z X Power-on (cold) reset ≥ VCC / VCCQ min X X HIGH-Z HIGH-Z X Hardware (warm) reset ≥ VCC / VCCQ min X X HIGH-Z HIGH-Z L Interface standby ≥ VCC / VCCQ min H X HIGH-Z HIGH-Z H CA ≥ VCC / VCCQ min L T Master output valid YH Read initial access latency (data bus turn around period) ≥ VCC / VCCQ min L T HIGH-Z L H Write initial access latency (RWDS turn around period) ≥ VCC / VCCQ min L T HIGH-Z HIGH-Z H Read data transfer ≥ VCC / VCCQ min L T Slave output valid Slave output valid Z or T H Write data transfer with initial latency ≥ VCC / VCCQ min L T Master output valid Master output valid X or T H Write data transfer without initial latency[42] ≥ VCC / VCCQ min L T Master output valid Slave output L or HIGH-Z H Active clock stop[43] ≥ VCC / VCCQ min L Idle Master or slave output valid or HIGH-Z YH Deep power down ≥ VCC / VCCQ min H X or T HIGH-Z HIGH-Z H Hybrid sleep ≥ VCC / VCCQ min H X or T HIGH-Z HIGH-Z H Notes 42. Writes without initial latency (with zero initial latency), do not have a turn around period for RWDS. The HYPERRAM™ device will always drive RWDS during the CA period to indicate whether extended latency is required. Since master write data immediately follows the CA period the HYPERRAM™ device may continue to drive RWDS LOW or may take RWDS to HIGH-Z. The master must not drive RWDS during Writes with zero latency. Writes with zero latency do not use RWDS as a data mask function. All bytes of write data are written (full word writes). 43. Active clock stop is described in “Active clock stop” on page 29. DPD is described in “Deep power down” on page 30.

Datasheet 29 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Power conservation modes

8 Power conservation modes

8.1 Interface standby

STANDBY is the default, low power, state for the interface while the device is not selected by the host for data transfer (CS# = HIGH). All inputs, and outputs other than CS# and RESET# are ignored in this state.

8.2 Active clock stop

Design note: Active clock stop feature is pending device characterization to determine if it will be supported. The Active clock stop state reduces device interface energy consumption to the ICC6 level during the data transfer portion of a read or write operation. The device automatically enables this state when clock remains stable for tACC + 30 ns. While in active clock stop state, read data is latched and always driven onto the data bus. ICC6 shown in “DC characteristics” on page 33. Active clock stop state helps reduce current consumption when the host system clock has stopped to pause the data transfer. Even though CS# may be LOW throughout these extended data transfer cycles, the memory device host interface will go into the active clock stop current level at tACC + 30 ns. This allows the device to transition into a lower current state if the data transfer is stalled. Active read or write current will resume once the data transfer is restarted with a toggling clock. The active clock stop state must not be used in violation of the tCSM limit. CS# must go HIGH before tCSM is violated. Clock can be stopped during any portion of the active transaction as long as it is in the LOW state. Note that it is recommended to avoid stopping the clock during register access. Figure 14 Active clock stop during read transaction (DDR) [44]

8.3 Hybrid sleep

In the hybrid sleep (HS) state, the current consumption is reduced (iHS). HS state is entered by writing a 0 to CR1[5]. The device reduces power within tHSIN time. The data in memory space and register space is retained during HS state. Bringing CS# LOW will cause the device to exit HS state and set CR1[5] to 1. Also, POR, or a hardware reset will cause the device to exit hybrid sleep state. Note that a POR or a hardware reset disables refresh where the memory core data can potentially get lost. Returning to STANDBY state requires t EXITHS time. Following the exit from HS due to any of these events, the device is in the same state as entering hybrid sleep. Figure 15 Enter HS transaction CS# CK#, CK RWDS DQ[7:0] CMD [7:0] CMD [7:0] ADR [31:24] ADR [23:16] ADR [15:8] ADR [7:0] Command - Address DoutA [7:0] DoutB [7:0] DoutA+1 [7:0] DoutB+1 [7:0] Read Data RWDS & Data are edge aligned High: 2X Latency Count Low: 1X Latency Count (Host drives DQ[7:0] and Memory drives RWDS) Clock Stopped Output Driven Latency Count (1X) Note 44. RWDS is LOW during the CA cycles. In this read transaction, there is a single initial latency count for read data access because, this read transaction does not begin at a time when additional latency is required by the CS# CK#, CK RWDS DQ[7:0] CMD [7:0] CMD [7:0] ADR [31:24] ADR [23:16] ADR [15:8] ADR [7:0] Command - Address RG [15:8] RG [7:0] Wr i t e Dat a CR0 Value High: 2X Latency Count Low: 1X Latency Count (Host drives DQ[7:0], Memory drives RW DS) Enter Hybrid Sleep tHSIN HS tHSIN

Datasheet 30 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Power conservation modes Figure 16 Exit HS transaction

8.4 Deep power down

In the deep power down (DPD) state, current consumption is driven to the lowest possible level (IDPD). DPD state is entered by writing a 0 to CR0[15]. The device reduces power within tDPDIN time and all refresh operations stop. The data in memory space is lost, (becomes invalid without refresh) during DPD state. Driving CS# LOW then HIGH will cause the device to exit DPD state. Also, POR, or a hardware reset will cause the device to exit DPD state. Returning to STANDBY state requires tEXTDPD time. Returning to STANDBY state following a POR requires tVCS time, as with any other POR. Following the exit from DPD due to any of these events, the device is in the same state as following POR. Figure 17 Enter DPD transaction Figure 18 Exit DPD transaction Table 15 Hybrid sleep timing parameters Parameter Description Min Max Unit tHSIN Hybrid sleep CR1[5] = 0 register write to DPD power level - 3 µs tCSHS CS# pulse width to exit HS 60 3000 ns tEXTHS CS# exit hybrid sleep to standby wakeup time - 100 µs Table 16 Deep power down timing parameters Parameter Description Min Max Unit tDPDIN Deep power down CR0[15] = 0 register write to DPD power level -3 µ s tCSDPD CS# pulse width to exit DPD 200 3000 ns tEXTDPD CS# exit deep power down to standby wakeup time - 150 µs tCSHS tEXTHS CS# CS# CK#, CK RWDS DQ[7:0] CMD [7:0] CMD [7:0] ADR [31:24] ADR [23:16] ADR [15:8] ADR [7:0] Command - Address RG [15:8] RG [7:0] Wri te Dat a CR0 Value High: 2X Latency Count Low: 1X Latency Count (Host drives DQ[7:0], Memory drives RWDS) Enter Deep Power Down tDPDIN DPD tDPDIN tCSDPD tEXTDPD CS#

Datasheet 31 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Electrical specifications

9 Electrical specifications

9.1 Absolute maximum ratings [47]

9.2 Input signal overshoot

During DC conditions, input or I/O signals should remain equal to or between VSS and VCC. During voltage transi- tions, inputs or I/Os may negative overshoot VSS to -1.0 V or positive overshoot to VCC +1.0 V, for periods up to 20 ns. Figure 19 Maximum negative overshoot waveform Figure 20 Maximum positive overshoot waveform Storage temperature plastic packages -65 °C to +150 °C Ambient temperature with power applied -65 °C to +135 °C Voltage with respect to ground all signals[45] -0.5 V to + (VCC + 0.5 V) Output short circuit current[46] 100 mA Voltage on VCC, VCCQ pins relative to VSS -0.5 V to +2.5 V Electrostatic discharge voltage: Human body model (JEDEC Std JESD22-A114-B) Charged device model (JEDEC Std JESD22-C101-A) 2000 V 500 V Notes 45. Minimum DC voltage on input or I/O signal is -1.0 V. During voltage transitions, input or I/O signals may undershoot VSS to -1.0 V for periods of up to 20 ns. See Figure 19. Maximum DC voltage on input or I/O signals is VCC +1.0 V. During voltage transitions, input or I/O signals may overshoot to VCC +1.0 V for periods up to 20 ns. See Figure 20. 46. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 47. Stresses above those listed under “Absolute maximum ratings[47]” on page 31 may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. VSSQ to VCCQ - 1.0V 20 ns≤ VCCQ + 1.0V 20 ns VSSQ to VCCQ

Datasheet 32 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Electrical specifications

9.3 Latch-up characteristics

9.3.1 Latch-up specification

9.4 Operating ranges

Operating ranges define those limits between which the functionality of the device is guaranteed.

9.4.1 Temperature ranges

Table 18 Temperature ranges

9.4.2 Power supply voltages

Table 17 Latch-up specification [48] Description Min Max Unit Input voltage with respect to VSSQ on all input only connections -1.0 V CCQ + 1.0 V Input voltage with respect to VSSQ on all I/O connections -1.0 V CCQ + 1.0 V VCCQ current -100 +100 mA Note 48. Excludes power supplies VCC/VCCQ. Test conditions: VCC = VCCQ, one connection at a time tested, connections not being tested are at VSS. Parameter Symbol Device Spec UnitMin Max Ambient temperature T A Industrial (I) -40 85 Industrial plus (V) -40 105 Automotive, AEC-Q100 grade 3 (A) -40 85 Automotive, AEC-Q100 grade 2 (B) -40 105 Automotive, AEC-Q100 grade 1 (M) -40 125 Table 19 Power supply voltages Description Min Max Unit VCC power supply 1.7 2.0 V

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9.5 DC characteristics

Table 20 DC characteristics (CMOS compatible) Parameter Description Test conditions Value UnitMin Typ [49] Max ILI2 Input leakage current device reset signal high only VIN = VSS to VCC, VCC = VCC max --2 µA ILI4 Input leakage current device reset signal low only[50] VIN = VSS to VCC, VCC = VCC max -- 1 5 ICC1 VCC active read current operating temperature range CS# = VSS, CK@200 MHz, VCC = VCC max -1 4 2 0 mA ICC2 VCC active write current operating temperature range -1 6 2 2 ICC4 VCC standby current (-40 °C to +85 °C) CS# = VCC, VCC = VCC max; full array - 470 1200 µA CS# = VCC, VCC = VCC max; bottom 1/2 array - - 850 CS# = VCC, VCC = VCC max; bottom 1/4 array - - 700 CS# = VCC, VCC = VCC max; bottom 1/8 array - - 600 CS# = VCC, VCC = VCC max; top 1/2 array - - 850 CS# = VCC, VCC = VCC max; top 1/4 array - - 700 CS# = VCC, VCC = VCC max; top 1/8 array - - 600 VCC standby current CS# = VCC, VCC = VCC max; full array - 470 1550 CS# = VCC, VCC = VCC max; bottom 1/2 array 1150 CS# = VCC, VCC = VCC max; bottom 1/4 array - - 950 CS# = VCC, VCC = VCC max; bottom 1/8 array - - 850 CS# = VCC, VCC = VCC max; top 1/2 array - - 1150 CS# = VCC, VCC = VCC max; top 1/4 array - - 950 CS# = VCC, VCC = VCC max; top 1/8 array - - 850 ICC4 VCC standby current CS# = VCC, VCC = VCC max; full array - 470 2000 Notes 49. Not 100% tested. 50. RESET# LOW initiates exits from DPD and hybrid state and initiates the draw of ICC5 reset current, making ILI during RESET# LOW insignificant.

Datasheet 34 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Electrical specifications ICC4 VCC standby current CS# = VCC, VCC = VCC max; bottom 1/2 array - - 1550 µA CS# = VCC, VCC = VCC max; bottom 1/4 array - - 1250 CS# = VCC, VCC = VCC max; bottom 1/8 array - - 1100 CS# = VCC, VCC = VCC max; top 1/2 array - - 1550 CS# = VCC, VCC = VCC max; top 1/4 array - - 1250 CS# = VCC, VCC = VCC max; top 1/8 array - - 1100 ICC5 Reset current (-40°C to +85°C) CS# = VCC, RESET# = VSS, VCC = VCCmax - - 0.55 mA Reset current (-40°C to +105°C) - - 0.75 Reset current (-40°C to +125°C) - - 1 ICC6 Active clock stop current (-40 °C to +85 °C) CS# = VSS, RESET# = VCC, VCC = VCC max -1 7 2 5 Active clock stop current (-40 °C to +105 °C) -1 7 3 0 Active clock stop current (-40 °C to +125 °C) -1 7 4 0 ICC7 VCC current during power up[49] CS# = VCC, VCC = VCC max, VCCQ = VCC -- 3 5 m A IDPD [50] Deep power down current (-40 °C to +85 °C) CS# = VCC, VCC = VCC max - - 12 µA IDPD [50] Deep power down current (-40 °C to +105 °C) CS# = VCC, VCC = VCC max - - 15 IDPD [50] Deep power down current (-40 °C to +125 °C) CS# = VCC, VCC = VCC max - - 20 IHS [50] Hybrid sleep current (-40 °C to +85 °C) CS# = VCC, VCC = VCC max; full array - 140 1100 CS# = VCC, VCC = VCC max; bottom 1/2 array - - 800 CS# = VCC, VCC = VCC max; bottom 1/4 array - - 600 CS# = VCC, VCC = VCC max; bottom 1/8 array - - 500 CS# = VCC, VCC = VCC max; top 1/2 array - - 800 Table 20 DC characteristics (CMOS compatible) (continued) Parameter Description Test conditions Value UnitMin Typ [49] Max Notes 49. Not 100% tested. 50. RESET# LOW initiates exits from DPD and hybrid state and initiates the draw of ICC5 reset current, making ILI during RESET# LOW insignificant.

Datasheet 35 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Electrical specifications IHS [50] Hybrid sleep current (-40 °C to +85 °C) CS# = VCC, VCC = VCC max; top 1/4 array - - 600 µA CS# = VCC, VCC = VCC max; top 1/8 array - - 500 Hybrid sleep current CS# = VCC, VCC = VCC max; full array - 140 1250 CS# = VCC, VCC = VCC max; bottom 1/2 array - - 850 CS# = VCC, VCC = VCC max; bottom 1/4 array - - 650 CS# = VCC, VCC = VCC max; bottom 1/8 array - - 550 CS# = VCC, VCC = VCC max; top 1/2 array - - 850 CS# = VCC, VCC = VCC max; top 1/4 array - - 650 CS# = VCC, VCC = VCC max; top 1/8 array - - 550 Hybrid sleep current CS# = VCC, VCC = VCC max; full array - 140 1500 CS# = VCC, VCC = VCC max; bottom 1/2 array - - 1150 CS# = VCC, VCC = VCC max; bottom 1/4 array - - 900 CS# = VCC, VCC = VCC max; bottom 1/8 array - - 750 CS# = VCC, VCC = VCC max; top 1/2 array - - 1150 CS# = VCC, VCC = VCC max; top 1/4 array - - 900 CS# = VCC, VCC = VCC max; top 1/8 array - - 750 VIL Input low voltage - -0.15 x VCCQ - 0.30 x VCCQ VVIH Input high voltage - 0.70 x VCCQ - 1.15 x VCCQ VOL Output low voltage IOL = 100 µA for DQ[7:0] - - 0.20 VOH Output high voltage V CCQ-0.20 - - Table 20 DC characteristics (CMOS compatible) (continued) Parameter Description Test conditions Value UnitMin Typ [49] Max Notes 49. Not 100% tested. 50. RESET# LOW initiates exits from DPD and hybrid state and initiates the draw of ICC5 reset current, making ILI during RESET# LOW insignificant.

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9.5.1 Capacitance characteristics

Table 21 Capacitive characteristics [51-53] Description Parameter 256 Mb UnitMax Input capacitance (CK, CK#, CS#) CI 3.0 pF Delta input capacitance (CK, CK#) CID 0.25 Output capacitance (RWDS) CO 3.0 IO capacitance (DQx) CIO 3.0 IO capacitance delta (DQx) CIOD 0.25 Notes 51. These values are guaranteed by design and are tested on a sample basis only. 52. Contact capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. V CC, VCCQ are applied and all other signals (except the signal under test) floating. DQs should be in the high impedance state. 53. Note that the capacitance values for the CK, CK#, RWDS and DQx signals must have similar capacitance values to allow for signal propagation time matching in the system. The capacitance value for CS# is not as critical because there are no critical timings between CS# going active (LOW) and data being presented on the DQ’s bus. Table 22 Thermal resistance Parameter [54] Description Test conditions 24-ball FBGA package Unit θJA Thermal resistance (junction t o ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 40.8 °C/W θ JC Thermal resistance (junction to case) 8 Note 54. This parameter is guaranteed by characterization; not tested in production.

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9.6 Power-up initialization

HYPERRAM™ products include an on-chip voltage sensor used to launch the power-up initialization process. VCC and VCCQ must be applied simultaneously. When the power supply reaches a stable level at or above VCC(min), the device will require tVCS time to complete its self-initialization process. The device must not be selected during power-up. CS# must follow the voltage applied on VCCQ until VCC (min) is reached during power-up, and then CS# must remain HIGH for a further delay of tVCS. A simple pull-up resistor from VCCQ to chip select (CS#) can be used to insure safe and proper power-up. If RESET# is LOW during power up, the device delays start of the tVCS period until RESET# is HIGH. The tVCS period is used primarily to perform refresh operations on the DRAM array to initialize it. When initialization is complete, the device is ready for normal operation. Figure 21 Power-up with RESET# HIGH Figure 22 Power-up with RESET# LOW Table 23 Power up and reset parameters [55, 56, 57] Parameter Description Min Max Unit VCC VCC power supply 1.7 2.0 V tVCS VCC and VCCQ ≥ minimum and RESET# HIGH to first access - 150 µs Notes 55. Bus transactions (read and write) are not allowed during the power-up reset time (tVCS). 56. VCCQ must be the same voltage as VCC. 57. VCC ramp rate may be non-linear. Vcc_VccQ CS# RESET# tVCS VCC Minimum Device Access Allowed Vcc_VccQ CS# RESET# tVCS VCC Minimum Device Access Allowed

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9.7 Power down

HYPERRAM™ devices are considered to be powered-off when the array power supply (VCC) drops below the VCC lock-out voltage (VLKO). During a power supply transition down to the VSS level, VCCQ should remain less than or equal to VCC. At the VLKO level, the HYPERRAM™ device will have lost configuration or array data. VCC must always be greater than or equal to VCCQ (VCC ≥ VCCQ). During power-down or voltage drops below VLKO, the array power supply voltages must also drop below VCC Reset (VRST) for a power down period (tPD) for the part to initialize correctly when the power supply again rises to VCC minimum. See Figure 23. If during a voltage drop the VCC stays above VLKO the part will stay initialized and will work correctly when VCC is again above VCC minimum. If VCC does not go below and remain below VRST for greater than tPD, then there is no assurance that the POR process will be performed. In this case, a hardware reset will be required ensure the HYPERBUS™ device is properly initialized. Figure 23 Power down or voltage drop The following section describes the HYPERRAM™ device -dependent aspects of power down specifications. Table 24 Power-down voltage and timing [57] Symbol Parameter Min Max Unit VCC VCC power supply 1.7 2.0 VVLKO VCC lock-out below which re-initialization is required 1.5 - VRST VCC low voltage needed to ensure initialization will occur 0.7 - tPD Duration of VCC ≤ VRST 50 - µs VCC (Max) VCC (Min) VLKO VRST tVCS Device Access Allowed No Device Access Allowed t Time VCC PD

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9.8 Hardware reset

The RESET# input provides a hardware method of returning the device to the STANDBY state. During tRPH the device will draw ICC5 current. If RESET# continues to be held LOW beyond tRPH, the device draws CMOS standby current (ICC4). While RESET# is LOW (during tRP), and during tRPH, bus transactions are not allowed. A hardware reset will do the following:

• Cause the configuration registers to return to their default values
• Halt self-refresh operation while RESET# is LOW - memory array data is considered as invalid
• Force the device to exit the hybrid sleep state
• Force the device to exit the deep power down state After RESET# returns HIGH, the self-refresh operation will resume. Because self-refresh operation is stopped during RESET# LOW, and the self-refresh row counter is reset to its default value, some rows may not be refreshed within the required array refresh interval per Table 13. This may result in the loss of DRAM array data during or immediately following a hardware reset. The host system should assume DRAM array data is lost after a hardware reset and reload any required data. Figure 24 Hardware reset timing diagram Table 25 Power up and reset parameters Parameter Description Min Max Unit t RP RESET# pulse width 200 - nstRH Time between RESET# (HIGH) and CS# (LOW) 200 - tRPH RESET# LOW to CS# LOW 400 - RESET# CS# tRP tRH tRPH

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10 Timing specifications

The following section describes HYPERRAM™ device dependent aspects of timing specifications.

10.1 Key to switching waveforms

Figure 25 Key to switching waveforms

10.2 AC test conditions

Table 26 Test specification [59] Parameter All speeds Unit Output load capacitance, CL 15 pF Minimum input rise and fall slew rates (1.8 V)[58] 1.13 V/ns Input pulse levels 0.0-V CCQ VInput timing measurement reference levels V CCQ/2 Output timing measurement reference levels V CCQ/2 Notes 58. All AC timings assume this input slew rate. 59. Input and output timing is referenced to VCCQ/2 or to the crossing of CK/CK#. Valid_High_or_Low High_to_Low_Transition Low_to_High_Transition Invalid High_Impedance Device Under Test CL

Datasheet 41 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Timing specifications Figure 27 Input waveforms and measurement levels [60]

10.3 CLK characteristics

Figure 28 Clock characteristics Table 27 Clock timings [61-63] Parameter Symbol 200 MHZ UnitMin Max CK period t CK 5– n s CK half period - duty cycle t CKHP 0.45 0.55 t CK CK half period at frequency Min = 0.45 tCK Min Max = 0.55 tCK Min tCKHP 2.25 2.75 ns VccQ Vss Input VccQ / 2 Measurement Level VccQ / 2 Output tCK tCKHP tCKHP CK# CK VIX (Max) VIX (Min) VCCQ / 2 Notes 60. Input timings for the differential CK/CK# pair are measured from clock crossings. 61. Clock jitter of ±5% is permitted. 62. Minimum frequency (Maximum t CK) is dependent upon maximum CS# LOW time (tCSM), initial latency and burst length. 63. CK and CK# input slew rate must be ≥ 1 V/ns (2 V/ns if measured differentially).

Datasheet 42 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Timing specifications Figure 29 Differential clock (CK/CK#) input swing Table 28 Clock AC/DC electrical characteristics [64, 65] Parameter Symbol Min Max Unit DC input voltage V IN –0.3 V CCQ+ 0.3 VDC input differential voltage V ID(DC) VCCQ x 0.4 V CCQ+ 0.6 AC input differential voltage V ID(AC) VCCQ x 0.6 V CCQ + 0.6 AC differential crossing voltage V IX VCCQ x 0.4 V CCQ x 0.6 Notes 64. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 65. The value of VIX is expected to equal VCCQ/2 of the transmitting device and must track variations in the DC level of VCCQ. half cycle VID (AC) (min) VID (DC) (min) -VID (DC) (min) -VID (AC) (min) time Differential Input Voltage (CK-CK#)

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10.4 AC characteristics

10.4.1 Read transactions

Table 29 HYPERRAM™ specific read timing parameters Parameter Symbol 200 MHz UnitMin Max Chip select high between transactions tCSHI 6– ns HYPERRAM™ read-write recovery time tRWR 35 – Chip select setup to next CK rising edge tCSS 4.0 – Data strobe valid tDSV –5 . 0 Input setup tIS 0.5 – Input hold tIH 0.5 – HYPERRAM™ read initial access time tACC 35 – Clock to DQs low Z tDQLZ 0– CK transition to DQ valid tCKD 15 . 0 CK transition to DQ invalid tCKDI 04 . 2 Data valid (tDV min = the lesser of: tCKHP min - tCKD max + tCKDI max) or tCKHP min - tCKD min + tCKDI min) tDV [66, 67] 1.45 – CK transition to RWDS valid t CKDS 1.0 5.0 RWDS transition to DQ valid tDSS –0.4 +0.4 RWDS transition to DQ invalid t DSH –0.4 +0.4 Chip select hold after CK falling edge tCSH 0– Chip select inactive to RWDS High-Z t DSZ –5 . 0 Chip select inactive to DQ High-Z t OZ –5 . 0 Refresh time tRFH 35 – CK transition to RWDS Low @CA phase @Read tCKDSR 1.0 5.5 Notes 66. Refer to Figure 32 for data valid timing. 67. The tDV timing calculation is provided for reference only, not to determine the spec limit. The spec limit is guaranteed by testing

Datasheet 44 of 54 002-31337 Rev. *C 2021-09-27 1.8 V Timing specifications Figure 30 Read timing diagram — No additional latency required Figure 31 Read timing diagram — with additional latency required Figure 32 Data valid timing [68-70] CS# CK#,CK RWDS DQ[7:0] tRWR =Read Write Recovery tACC = Access 4 cycle latency Command-Address tCKD tCSHI tCSS tCSS tCSM tDSV tIS tIH tCKDS tDQLZ tCSH tDSZ tOZtDSS tDSH 47:40 39:32 31:24 23:16 15:8 7:0 High = 2x Latency Count Low = 1x Latency Count Dn A Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and Memory drives RWDS Memory drives DQ[7:0] and RWDS RWDS and Data are edge aligned CS# CK#,CK RWDS DQ[7:0] tRWR =Read Write Recovery tACC = AccessAdditional Latency 4 cycle latency 1 4 cycle latency 2 Command-Address tCKDStDSV 47:40 39:32 31:24 23:16 15:8 7:0 High = 2x Latency Count Low = 1x Latency Count Dn A Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and Memory drives RWDS Memory drives DQ[7:0] tCKDS tCKD and RWDS Notes 68. tCKD and tCKDI parameters define the beginning and end position of data valid period. 69. tDSS and tDSH define how early or late DQ may transition relative to RWDS. This is a potential skew between the CK to DQ delay tCKD and CK to RWDS delay tCKDS. 70. Since DQ and RWDS are the same output types, the tCKD, and tCKDS values track together (vary by the same ratio). CS# CK CK# RWDS DQ[7:0] tCKHP tCSHS tCSS tOZ tDSZ tDQLZ tCKD tCKDS tCKD tCKDI tDV tDSH tDSS Dn A Dn B Dn+1 A Dn+1 B

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10.4.2 Write transactions

Figure 33 Write timing diagram — No additional latency Table 30 Write timing parameters Parameter Symbol 200 MHz Unit Min Max Read-write recovery time t RWR 35 - nsAccess time t ACC 35 - Refresh time t RFH 35 - Chip select maximum low time (85 °C) t CSM -4 µsChip select maximum low time (105 °C and 125 °C) t CSM -1 RWDS data mask valid t DMV 0- CS# CK#,CK RWDS DQ[7:0] tRWR =Read Write Recovery tACC = Access 4 cycle latency Command-Address tCSHI tCSM tCSS tCSS tDSV tDSZ tIS tIS tIS tIH tIH tIH tCSH tDMV 47:40 39:32 31:24 23:16 15:8 7:0 High = 2x Latency Count Low = 1x Latency Count Dn A Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and Memory drives RWDS Host drives DQ[7:0] and RWDS CK and Data are center aligned

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10.5 Timing reference levels

Figure 34 DDR input timing reference levels Figure 35 DDR output timing reference levels tCK tIS tIH tIS tIH VCCQ VSSQ VIH(min) VIL(max) VCCQ VSSQ CK, CK# DQ[7:0] VT VT tIS tIH tIS tIH VCCQ VSSQ VIH(min) VIL(max) RWDS VT tSCK RWDS VOH(min) VOL(max) VCCQ VSSQ DQ[7:0] tDS S tDS H VCCQ VSSQ VT VT

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11 Physical interface

11.1 FBGA 24-ball 5 x 5 array footprint

HYPERRAM™ devices are provided in fortified ball grid array (FBGA), 1-mm pitch, 24-ball, 5 x 5 ball array footprint, with 6 mm x 8 mm body. Figure 36 24-ball FBGA, 6 x 8 mm, 5 x 5 ball footprint, top view 3241 CS#RFU RESET# B D E A C VssCK VccCK# RWDSRFU DQ2VssQ DQ0DQ1 DQ3VccQ DQ5DQ6 VccQDQ7 RFU RFU RFU DQ4 VssQ

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11.2 Package diagrams

Figure 37 Fortified ball grid array 24-ball 6 x 8 x 1.0 mm (VAA024) N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0. POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. "e" REPRESENTS THE SOLDER BALL GRID PITCH. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION9. NOTES: ALL DIMENSIONS ARE IN MILLIMETERS. SD b eD eE ME N 0.35

0.00 BSC

1.00 BSC

0.40 0.45 MD E D A A1 0.20

4.00 BSC

6.00 BSC

8.00 BSC

• 1.00 SE 0.00 BSC DIMENSIONS SYMBOL MIN. NOM. MAX. OR OTHER MEANS. JEDEC SPECIFICATION NO. REF: N/A10. 002-15550 *A

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Ordering information

12.1 Ordering part number

The ordering part number is formed by a valid combination of the following: S80KS 256 2 GA B H I 02 0 Packing type 0 = Tray 3 = 13” Tape and Reel Model number (additional ordering options) 02 = Standard 6 x 8 x 1.0 mm package (VAA024) Temperature range / grade I = Industrial (–40 °C to + 85 °C) V= Industrial Plus (–40 °C to + 105 °C) A = Automotive, AEC-Q100 Grade3 (–40 °C to + 85 °C) B = Automotive, AEC-Q100 Grade2 (–40 °C to + 105 °C) M =Automotive, AEC-Q100 Grade1 (–40 °C to + 125 °C) Package materials H = Low-Halogen, Pb-free Package type B = 24-ball FBGA, 1.00 mm pitch (5x5 ball footprint) Speed GA = 200 MHz Device technology 2 = HYPERBUS™ 3 = Octal xSPI 4 = HYPERBUS™ Extended-IO Density 256 = 256 Mb Device family S80KS - Infineon Memory 1.8 V-only, HYPERRAM™ Self-refresh DRAM

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12.2 Valid combinations

The recommended combinations table lists configurations planned to be available in volume. Table 31 will be updated as new combinations are released. Contact your local sales representative to confirm availability of specific combinations and to check on newly released combinations.

12.3 Valid combinations - Automotive grade / AEC-Q100

Table 32 list configurations that are Automotive grade / AEC-Q100 qualified and are planned to be available in volume. The table will be updated as new combinations are released. Contact your local sales representative to confirm availability of specific combinations and to check on newly released combinations. Production part approval process (PPAP) support is only provided for AEC-Q100 grade products. Products to be used in end-use applications that require ISO/TS-16949 compliance must be AEC-Q100 grade products in combination with PPAP . Non-AEC-Q100 grade products are not manufactured or documented in full compliance with ISO/TS-16949 requirements. AEC-Q100 grade products are also offered without PPAP support for end-use applications that do not require ISO/TS-16949 compliance. Table 31 Valid combinations - standard Device family Density Technology Speed Package, material, and temperature Model number Packing type Ordering part number Package marking S80KS 256 2 GA BHI 02 0 S80KS2562GABHI020 8KS2562GAHI02 S80KS 256 2 GA BHI 02 3 S80KS2562GABHI023 8KS2562GAHI02 S80KS 256 2 GA BHV 02 0 S80KS2562GABHV020 8KS2562GAHV02 S80KS 256 2 GA BHV 02 0 S80KS2562GABHV023 8KS2562GAHV02 Table 32 Valid combinations - Automotive grade / AEC-Q100 Device family Density Technology Speed Package, material, and temperature Model number Packing type Ordering part number Package marking S80KS 256 2 GA BHA 02 0 S80KS2562GABHA020 8KS2562GAHA02 S80KS 256 2 GA BHA 02 3 S80KS2562GABHA023 8KS2562GAHA02 S80KS 256 2 GA BHB 02 0 S80KS2562GABHB020 8KS2562GAHB02 S80KS 256 2 GA BHB 02 3 S80KS2562GABHB023 8KS2562GAHB02 S80KS 256 2 GA BHM 02 0 S80KS2562GABHM020 8KS2562GAHM02 S80KS 256 2 GA BHM 02 3 S80KS2562GABHM023 8KS2562GAHM02

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13 Acronyms

Table 33 Acronyms used in this document Acronym Description CMOS complementary metal oxide semiconductor DDR double data rate DPD deep power down DRAM dynamic RAM HS hybrid sleep MSb most significant bit POR power-on reset PSRAM pseudo static RAM PVT process, voltage, and temperature RWDS read-write data strobe SPI serial peripheral interface xSPI expanded serial peripheral interface

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14 Document conventions

14.1 Units of measure

°C degree Celsius MHz megahertz µA microampere µs microsecond mA milliampere mm millimeter ns nanosecond Ω ohm %p e r c e n t pF picofarad Vv o l t Ww a t t

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Revision history

version Date of release Description of changes *C 2021-09-27 Publish to web.

81726 Munich, Germany

© 2021 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? Go to www.cypress.com/support Document reference 002-31337 Rev. *C IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in th is document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Te chnologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. Trademarks All referenced product or service names and trademarks are the property of their respective owners.