S6E63D6

S6E63D6 SAMSUNG | Alldatasheet

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240 RGB X 320 Dot 1-Chip Driver IC with LTPS Interface

for 262,144 Color AMOLED Display Panel November 7, 2006 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. System LSI Division Device Solution Network SAMSUNG ELECTRONICS CO., LTD. (http://www.samsung.com/Products/Semiconductor/DisplayDriverIC)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary INTRODUCTION The S6E63D6 is a single chip solution for Gate-IC-less AMOLED panel. Source driver with built-in memory, gate-IC-less level shifter and power circuits are integrated on this LSI. It can display to the maximum of 240-RGB x 320-dot graphics on 260k-color AMOLED panel. Moreover, the chip supports LTPS panel. The S6E63D6 supports Qualcomm’s high-speed serial interfac e, MDDI (Mobile Display Digital Interface) type I, which is an implementation of client device Video Electronics Standards Association (VESA) standard. The MDDI is a cost-effective low-power solution that enables high-speed short-range communication with a display device using a digital packet data link. The S6E63D6 also supports 18-/16-/9-/8-bit high-speed bus interface to enable efficient data transfer to the GRAM. There is an external interface. In case of display data , the S6E63D6 offers a flexib le 18-/16-/6-bits bus of RGB interface for transferring the 260k colors display data. The motion picture area can be designated in GRAM by window function. The specified window area can be updated selectively so that motion picture can be displayed simultaneously independent of still picture area. The LSI operates at low voltage and has internal GRAM s to store 240-RGB x 320-dot 260k-color image data. Additionally, it has an internal booster that generates t he OLED driving voltage and the voltage follower circuit for OLED driver. The S6E63D6 is suitable for any medium-sized or small portable mobile solution requiring long-term driving capabilities such as digital cellular phones supporting a web browser, bi-directional pagers, PMP, MP3P and small PDAs.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary

FEATURES

− 240-RGBx320-dot AM-OLED display controller/driver IC for 262,144 colors − Gate IC less − 240 channel source driver with time shared driving function Various color-display control functions − 262,144 colors can be displayed at the same time with RGB separated gamma adjust. − 262,144 / 65,536/ 8 colors can be displayed. − Vertical scroll display function in line units Various interfaces − 18-/16-/9-/8-bit high-speed parallel bus interface (80- and 68- system) − Serial peripheral interface (SPI) − 18-/16-/6-bit RGB interface − MDDI (Mobile Display Digital Interface) support Internal ram capacity: 240 x 18 x 320 = 1,382,400 bits Writing to a window-ram address area by using a window-address function Efficiently panel driving signals − SOUT[1:240] : V0~V63 grayscale − FLM, SFTCLK, SFTCLKB, SCLK1, SCLK2, CLA, CLB, CLC, BICTL_L, BI CTL_R, EX_FLM, EX_CLK, EX_CLKB, ESR : VGL to VGH level Low-power operation supports: − Power-save mode: standby mode − Partial display mode in any position Internal oscillation circuit and external hardware reset Internal power supply circuit Operating voltage

• Apply voltage − I/O power-supply VDD3 to VSS = 1.65 to 3.3V − Analog power-supply VCI to VSS = 2.5 to 3.3V
• Generated voltage − VGH = 4.6 to 6.6V (gate circuit power supply) − VGL = -7.8 to -5.0V (gate circuit power supply) − VINT = - 4.0 to -1.0V (OLED pixel initialization first power supply) − Source output range = 0.96 to 4.2V Released package type − S6E63D6 is released COG type package format only.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary BLOCK DIAGRAM Figure1: S6E63D6 Block Diagram

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary PAD CONFIGURATION Figure2: Pad Configuration

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Table1: S6E63D6 Pad Dimensions Size Items Pad name. X Y Unit Chip size (With scribe lane; 80um) - 15,580 1,330 Chip thickness - 300 Input pad 60 Bump pitch Output pad 54 Input pad (1-251) 30 91 Output pad (264-539) 36 91 Pad size Output pad (252-263, 540-551) 91 36 Bump Height All PADs 15 ± 3 um Pitch Y X PITCH Y X OUTPUT BUMP INPUT BUMP

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary ALIGN KEY CONFIGURATION AND COORDINATE Figure3: COG Align Key

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary PAD CENTER COORDINATES Table2: Pad Center Coordinates [Unit: um] NO NAME X Y NO NAME X Y NO NAME X Y

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Table3: Pad Center Coordinates (continued) [Unit: um] NO NAME X Y NO NAME X Y NO NAME X Y

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Table4: Pad Center Coordinates (continued) [Unit: um] NO NAME X Y NO NAME X Y NO NAME X Y

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Table5: Pad Center Coordinates (continued) [Unit: um] NO NAME X Y NO NAME X Y NO NAME X Y 452 SOUT[169] -2727.0 572.5 502 SOUT[219] -5427.0 572.5 453 SOUT[170] -2781.0 572.5 503 SOUT[220] -5481.0 572.5 454 SOUT[171] -2835.0 572.5 504 SOUT[221] -5535.0 572.5 455 SOUT[172] -2889.0 572.5 505 SOUT[222] -5589.0 572.5 456 SOUT[173] -2943.0 572.5 506 SOUT[223] -5643.0 572.5 457 SOUT[174] -2997.0 572.5 507 SOUT[224] -5697.0 572.5 458 SOUT[175] -3051.0 572.5 508 SOUT[225] -5751.0 572.5 459 SOUT[176] -3105.0 572.5 509 SOUT[226] -5805.0 572.5 460 SOUT[177] -3159.0 572.5 510 SOUT[227] -5859.0 572.5 461 SOUT[178] -3213.0 572.5 511 SOUT[228] -5913.0 572.5 462 SOUT[179] -3267.0 572.5 512 SOUT[229] -5967.0 572.5 463 SOUT[180] -3321.0 572.5 513 SOUT[230] -6021.0 572.5 464 SOUT[181] -3375.0 572.5 514 SOUT[231] -6075.0 572.5 465 SOUT[182] -3429.0 572.5 515 SOUT[232] -6129.0 572.5 466 SOUT[183] -3483.0 572.5 516 SOUT[233] -6183.0 572.5 467 SOUT[184] -3537.0 572.5 517 SOUT[234] -6237.0 572.5 468 SOUT[185] -3591.0 572.5 518 SOUT[235] -6291.0 572.5 469 SOUT[186] -3645.0 572.5 519 SOUT[236] -6345.0 572.5 470 SOUT[187] -3699.0 572.5 520 SOUT[237] -6399.0 572.5 471 SOUT[188] -3753.0 572.5 521 SOUT[238] -6453.0 572.5 472 SOUT[189] -3807.0 572.5 522 SOUT[239] -6507.0 572.5 473 SOUT[190] -3861.0 572.5 523 SOUT[240] -6561.0 572.5 474 SOUT[191] -3915.0 572.5 524 SOUT_DUM240 -6615.0 572.5 475 SOUT[192] -3969.0 572.5 525 DUMMY -6669.0 572.5 476 SOUT[193] -4023.0 572.5 526 DUMMY -6723.0 572.5 477 SOUT[194] -4077.0 572.5 527 BICTI_L -6777.0 572.5 478 SOUT[195] -4131.0 572.5 528 BICTI_L -6831.0 572.5 479 SOUT[196] -4185.0 572.5 529 SCLK1 -6885.0 572.5 480 SOUT[197] -4239.0 572.5 530 SCLK1 -6939.0 572.5 481 SOUT[198] -4293.0 572.5 531 SCLK2 -6993.0 572.5 482 SOUT[199] -4347.0 572.5 532 SCLK2 -7047.0 572.5 483 SOUT[200] -4401.0 572.5 533 SFTCLK -7101.0 572.5 484 SOUT[201] -4455.0 572.5 534 SFTCLK -7155.0 572.5 485 SOUT[202] -4509.0 572.5 535 SFTCLKB -7209.0 572.5 486 SOUT[203] -4563.0 572.5 536 SFTCLKB -7263.0 572.5 487 SOUT[204] -4617.0 572.5 537 FLM -7317.0 572.5 488 SOUT[205] -4671.0 572.5 538 FLM -7371.0 572.5 489 SOUT[206] -4725.0 572.5 539 DUMMY -7425.0 572.5 490 SOUT[207] -4779.0 572.5 540 DUMMY -7697.5 298.0 491 SOUT[208] -4833.0 572.5 541 DUMMY -7697.5 244.0 492 SOUT[209] -4887.0 572.5 542 DUMMY -7697.5 190.0 493 SOUT[210] -4941.0 572.5 543 DUMMY -7697.5 136.0 494 SOUT[211] -4995.0 572.5 544 DUMMY -7697.5 82.0 495 SOUT[212] -5049.0 572.5 545 DUMMY -7697.5 28.0 496 SOUT[213] -5103.0 572.5 546 DUMMY -7697.5 -26.0 497 SOUT[214] -5157.0 572.5 547 DUMMY -7697.5 -80.0 498 SOUT[215] -5211.0 572.5 548 DUMMY -7697.5 -134.0 499 SOUT[216] -5265.0 572.5 549 DUMMY -7697.5 -188.0 500 SOUT[217] -5319.0 572.5 550 DUMMY -7697.5 -242.0

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary PIN DESCRIPTION POWER SUPPLY PINS Table6: Power supply pin description Symbol I/O Description VDD Power Power supply for internal logic and internal RAM. Internally, voltage regulator output is connected to this pin. Connect a capacitor for stabilization. Don’t apply any external power to this pin. MVDD Power Internal power for RAM. C onnect this pin to VDD externally. RVDD Power Regulated logic power voltage (1.5V) VDD3 Power I/O power supply. (1.65V ~ 3.3V) VCI Power Power supply for analog circuits. (VCI : 2.5 ~ 3.3V) An internal reference power supply for VCI1 amp. VCI_MDDI Power Analog power supply (VCI_MDDI : 2.5 ~ 3.3V) VSS VSSA VSSC Ground System ground (0V). VSS_MDDI Power System ground level for I/O VGS I A reference level for the grayscale voltage generation circuit. Connect this pin to an external resistor when a source driver is used to adjust grayscale levels for each panel. VCI1 I/O A reference voltage for 1 st booster. VCIRIN I A reference voltage input pin for power block when using an external VCIR generation mode. VLIN1 / VLOUT1 I/O Input pin for applying VLOUT1 voltage level / st booster output pin. Recommend to connect VLIN1 to VLOUT1. VLIN2 / VLOUT2 I/O Input pin for applying VLOUT2 voltage level / nd booster output pin. Recommend to connect VLIN2 to VLOUT2. VLIN3 / VLOUT3 I/O Input pin for applying VLOUT3 voltage level / rd booster output pin. Recommend to connect VLIN3 to VLOUT3. C11P,C11M C12P,C12M I/O External capacitor connection pins used for the 1’st booster circuit. C21P,C21M I/O External capacitor connection pins used for the 2nd booster circuit.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Table7: Power supply pin description(Continued) Symbol I/O Description C31P,C31M C32P,C32M I/O External capacitor connection pins used for the 3rd booster circuit. VREG1OUT I/O A reference level for the grayscale voltage with the amplitude between VLOUT1 and GND. VGH O The positive voltage used in the gate driver. VGL O The negative voltage used in the gate driver. VINT O A voltage for initializing an OLED panel. VSP O Power supply for the external photo sensor. If not use, this pin must be open. ELVDD I Power supply for the generation of VSP. If not use, this pin must be fixed to VSS level. MTPG I A voltage for the MTP programming (Initialization, Erasing, and Programming). If not use, this pin must be open. MTPD I A voltage for the MTP programming (Initialization, Erasing, and Programming). If not use, this pin must be open. Vex I Must be fixed to VSS level.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary SYSTEM / RGB INTERFACE PINS Table8: System interface pin description Symbol I/O Description S_PB I Selects the CPU interface mode “Low” = Parallel Interface, “High” = Serial Interface MDDI_EN I Selects the MDDI interface “Low” = MDDI Disable, “High” = MDDI Enable ID_MIB I Selects the CPU type “Low” = Intel 80x-system, “High” = Motorola 68x-system If S-PB = “High”, the pin is used as ID setting bit for a device code. CSB I Chip select signal input pin. Low: S6E63D6 is selected and can be accessed High: S6E63D6 is not selected and cannot be accessed RS I Register select pin. Low: Index/status, High: Instruction parameter, GRAM data Must be fixed at VDD3 level when not used. Pin function CPU type Pin description RW 68-system Read/Write operation selection pin. Low: Write, High: Read WRB 80-system Write strobe signal. (Input pin) Data is fetched at the rising edge. RW_WRB/ SCL I SCL Serial Peripheral Interface (SPI) The synchronous clock signal. (Input pin) Pin function CPU type Pin description E 68-system Read/Write operation enable pin. RDB 80-system Read strobe signal. (Input pin) Read out data at the low level. E_RDB I When SPI mode is selected, fix this pin at VDD3 level. SDI I For a serial peripheral interface (SPI), input data is fetched at the rising edge of the SCL signal. Fix SDI pin at VSS level if the pin is not used. SDO O For a serial peripheral interface (SPI), serves as the serial data output pin (SDO). Successive bits are output at the falling edge of the SCL signal. RESETB I Reset pin Initializes the IC wh en low. Should be reset after power-on. DB17-DB0 I/O Bi-directional data bus. When CPU I/F, 18-bit interface : DB 17-0 16-bit interface : DB 17-10, DB 8-1 9-bit interface : DB 8-0 8-bit interface : DB 8-1 When RGB I/F, 18-bit interface : DB 17-0 16-bit interface : DB 17-10, DB 8-1 6-bit interface : DB 8-3 Fix unused pin to the VSS level.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Table9: System interface pin description (Continued) Symbol I/O Description Data enable signal pin for RGB interface. EPL=”0”: Only in case of ENABLE=”Low”, the IC can be access via RGB interface. EPL=”1”: Only in case of ENABLE=”High”, the IC can be access via RGB interface EPL ENABLE GRAM write GRAM address 0 0 Valid Updated 0 1 Invalid Held 1 0 Invalid Held 1 1 Valid Updated ENABLE I Fix ENABLE pin at VSS level if the pin is not used. VSYNC I Frame-synchronizing signal. VSPL= “0”: Low active, VSPL=”1”: High active Fix this pin at VSS level if the pin is not used. HSYNC I Line-synchronizing signal. HSPL=”0”: Low active, HSPL=”1”: High active Fix this pin at VSS level if the pin is not used. DOTCLK I Input pin for clock signal of external interface: dot clock. DPL=”0”: Display data is fetched at DOTCLK’s rising edge DPL=”1”: Display data is fetched at DOTCLK’s falling edge Fix this pin at VSS level if the pin is not used.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Tabel10: MDDI pin description Symbol I/O Description MDP I/O Positive MDDI data input/output. If M DDI is not used, this pad should be floating. MDN I/O Negative MDDI data input/output. If MDDI is not used, this pad should be floating. MSP I Positive MDDI strobe input. If MDDI is not used, this pad should be floating. MSN I Negative MDDI strobe input. If MDDI is not used, this pad should be floating. GPIO[9:0] (DB[17:8]) I/O General purpose input/output If GPIO is not used in MDDI mode, this pin should be fixed at VSS level. S_CSB (DB[7]) O Chip select for Sub Panel Driver IC Low: Sub Panel Driver IC is selected and can be accessed. High: Sub Panel Driver IC is not selected and can not be accessed. If sub panel is not used in MDDI mode, this pin should be floating S_RS (DB[6]) O Register select for Sub Panel Driver IC Low : Index/status, High : Control Must be fixed at VSS level, when this signal is not used. If sub panel is not used in MDDI mode, this pin should be floating S_WRB (DB[5]) O Write Strobe signal for Sub Panel Driver IC Only 80-system 18/16 bit mode is enabled, so Data is fetched at the rising edge. If sub panel is not used in MDDI mode, this pin should be floating S_DB[8-0] (DB[4:0], TE, TEST_OUT[2:0]) O For Sub Panel, this pin can be used to transfer DB[8:0] data to Sub Panel Driver IC. If sub panel is not used in MDDI mode, this pin should be floating. HSYNC VSYNC ENABLE DOTCLK I In MDDI mode, Fixed at VSS level. RW_WRB E_RDB RS I In MDDI mode, Fixed at VDD3 level. CSB I In MDDI mode, Fixed at VDD3 level.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary DISPLAY PINS Table11: Display pin description Symbol I/O Description SOUT[1:240] O Source driver output pins. The direction of them is determined by the value of SS register. FLM O Start pulse of vertical line shift. SFTCLK, SFTCLKB O Clock for gate driver shift. SCLK1, SCLK2 O LTPS signals CLA, CLB, CLC O LTPS signals BICTL_L O LTPS signal BICTL_R O LTPS signal EX_FLM O Don’t use this pin. IC maker’s test pins. EX_CLK, EX_CLKB O Don’t use this pin. IC maker’s test pins. ESR O Shift register enable signal EL_ON O The external ELVDD regulator enable pin MISCELLANEOUS PINS Table12: Oscillator and internal power regulator pin description Symbol I/O Description DUMMYR[3:1] DUMMYL[3:1] - Contact resistance measurement pin. In normal operation, leave this pin open DUMMY - Dummy pins don’t care. Leave these pins open. V0/V63 O Gamma voltage monitoring pin. VDD3DUM O This pin is connected to VDD3 line inte rnally. Use for to connect neighbor-setting pins. VSSDUM O This pin is connected to VSS line intern ally. Use for to connect neighbor-setting pins. FUSE_EN I Don’t use this pin. IC maker’s test pins. This pin must be tied to VDD3. RTEST I Don’t use this pin. IC maker’s test pins. This pin must be tied to VSS. EN_EXCLK I Don’t use this pin. IC maker’s test pins. Fix this pin at VSS level if the pin is not used. EXCLK I Don’t use this pin. IC maker’s test pins. Fix this pin at VSS level if the pin is not used. TEST_MODE[1:0] I Don’t use this pin. IC maker’s test pins. Fix this pin at VSS level if the pin is not used. TEST_IN[6:0] I Don’t use this pin. IC maker’s test pins. Fix this pin at VSS level if the pin is not used. TE O Tearing effect output pin. In normal operation, leave this pin open. TEST_OUT[2:0] O Output pins used only for test purpose at vendor-side. In normal operation, leave this pin open.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary FUNCTIONAL DESCRIPTION SYSTEM INTERFACE The S6E63D6 has ten high-speed system interfaces: an 80-system 18-/16-/9-/8-bit bus, a 68-system 18-/16-/9-/8-bit and two type serial interface (SPI: Serial Peripheral Interface). The S6E63D6 has three 18-bit registers: an index register (IR), a write data register (WDR), and a read data register (RDR). The IR stores index information for control r egister and GRAM. The WDR temporarily stores data to be written into control register and GRAM . The RDR temporarily stores data read from GRAM. Data written into the GRAM from CPU is initially written to the WDR and then written to the GRAM automatically. Data is read through the RDR when reading from the GRAM, and the first read data is invalid and the second and the following data are valid. Execution time for instruction, except oscillation start, is 0-clock cycle so that instructions can be written in succession. Table13: Register Selection (18-/16-/9-/8- Parallel Interface) SYSTEM RW_WRB E_RDB RS Operations 0 1 0 Write index to IR 1 1 0 Read internal status 0 1 1 Write to control register and GRAM through WDR 68 1 1 1 Read from GRAM through RDR 0 1 0 Write index to IR 1 0 0 Read internal status 0 1 1 Write to control register and GRAM through WDR 80 1 0 1 Read from GRAM through RDR Table14: CSB signal (GRAM update control) CSB Operation

0 Data is written to GRAM, GRAM address is updated

1 Data is not written to GRAM, GRAM address is not updated

Table15: Register Selection (Serial Peripheral Interface) R/W bit RS bit Operation 0 0 Write index to IR 1 0 Read internal status 0 1 Write data to control register and GRAM through WDR 1 1 Read data from GRAM through RDR

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary HIGH SPEED SERIAL INTERFACE (MDDI) This interface will be introduced, see the section “Description of MDDI Interface” SUB PANEL CONTROL Sub panel control block will be introduced, see the section “Description of Sub Panel Control” EXTERNAL INTERFACE (RGB-I/F) The S6E63D6 incorporates RGB interface as external interface for motion picture display. When the RGB interface is selected, the synchronization signals (VSYNC, HSYNC, and DOTCLK) are available for display. The RGB data for display (DB17-0) are written according to enable signal (ENABLE) in synchronization with VSYNC, HSYNC, and DOTCLK signal. This allows flicke r-free updating of the screen . See the section on the EXTERNAL DISPLAY INTERFACE. ADDRESS COUNTER (AC) The address counter (AC) assigns address to GRAM. When an address-set-instruction is written to the IR, the address information is sent from IR to AC. After writing to the GRAM, the ad dress value of AC is automatically increased/ decreased by 1 according to ID1-0 bit of cont rol register. After reading data from GRAM, the AC is updated automatically. GRAPHICS RAM (GRAM) The graphics RAM (GRAM) has 18-bits/pixel and stores the bit-pattern data for 240-RGB x 320-dot display. TIMING GENERATOR The Panel Interface Controller generates timing signals for LTPS drive. Also it generates control signals for the operation of internal circuits such as source driv er and GRAM. The GRAM read operations done by this Timing Generator and GRAM write operations done through syst em interface are performed independently to avoid the interference between them. GRAYSCALE VOLTAGE GENERATOR The grayscale voltage circuit generates OLED driving voltage that corresponds to the grayscale levels as specified in the grayscale gamma-adjusting registers. 262,144 possible colors can be displayed at the same time by this LSI. Gamma is set for R,G, and B individually. OSCILLATION CIRCUIT (OSC) The S6E63D6 can provide R-C oscillation simply through the internal oscillation-resistor. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the internal register. Since R-C oscillation stops during the standby mode, curre nt consumption can be redu ced. For details, see the OSCILLATION CIRCUIT section.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary SOURCE DRIVER CIRCUIT The source driving circuit of S6E63D6 consists of a 240 source drivers (SOUT[1] to SOUT[240]). Image data is latched when 240-pixel data has arrived. The latched data then enables the source drivers to generate drive waveform outputs. The SS register can change the shift direction of 240 source driver output data for the device-mount configuration. LTPS PANEL INTERFACE CIRCUIT LTPS panel interface circuit does level–shift operation and outputs to control LTPS panel.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary GRAM ADDRESS MAP The image data stored in GRAM corresponds to pixel data on display as shown below: Figure4: GRAM address (SS=”0”) Figure5: GRAM address (SS=”1” )

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary INSTRUCTIONS The S6E63D6 uses the 18-bit bus architecture. Before the internal operation of the S6E63D6 starts, control information is stored temporarily in the registers described below to allow high-speed interfacing with a high-performance microcomputer. The internal operation of the S6E63D6 is determined by signals sent from the microcomputer. These signals, which include the register selection signal (RS), the read/write signal (R/W), and the data bus signals (DB17 to DB0), make up the S6E63D6 instructions. There are seven categories of instructions that: - Specify the index - Control the display - Control power management - Set internal GRAM addresses - Transfer data to and from the internal GRAM - Set grayscale level for the internal grayscale palette table - Interface with the LTPS driver and power supply IC Normally, instructions that write data are used the most. However, an auto-update of internal GRAM addresses after each data write can lighten the microcomputer program load. As instructions are executed in 0 cycles, they can be written in succession. The 16-bit instruction assignment differs from interface-setup (18-/16-/9-/8-/SPI), so instructions should be fetched according to the data format shown below: 68/80-system 18-bit Interface DB 17INPUT DATA Instruction Bit (IB) DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB 68/80-system 16-bit Interface/SPI(Serial Peripheral Interface) DB 17INPUT DATA Instruction Bit (IB) DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 68/80-system 9-bit Interface 1st Transmission 2nd Transmission DB 8INPUT DATA Instruction Bit (IB) DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB DB DB DB DB DB DB DB DB DB 68/80-system 8-bit Interface DB 17INPUT DATA Instruction Bit (IB) DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB 1st Transmission 2nd Transmission DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary INSTRUCTION TABLE Table16: Instruction Table Index Reg. No R/W RS IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IR W 0 Set index register value X X X X X X X X ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 SR R 0 Status Read X X X X X X X L8 L7 L6 L5 L4 L3 L2 L1 L0 I/F Control R0h W 0 No Operation No operation R01h W 1 Display Duty control FP3 FP2 FP1 FP0 BP3 BP2 BP1 BP0 X X NL5 NL4 NL3 NL2 NL1 NL0 R02h W 1 RGB Interface Control X X X X X X X RM DM X RIM1 RIM0 VSPL HSPL EPL DPL R03h W 1 Entry Mode CLS MDT1 MDT0 BGR X X X SS X X I/D1 I/D0 X X X AM R04h W 1 Clock Control X X X X X X X X X X DCR1 DCR0 X X X X R05h W 1 Display Control1 X X X X X X X X X X X X X X X DISP_O N R06h W 1 Display Control2 X X X X X X X X X X X CL X X TEMON REV R07h W 1 Panel IF Control1 X X X CLWEA CLWEA CLWEA CLWEA CLWEA

0 X X X X X X X X

R08h W 1 Panel IF Control2 X X X CLWEB CLWEB CLWEB CLWEB CLWEB

0 X X X CLWEC

R09h W 1 Panel IF Control3 SCTE3 SCTE2 SCTE1 SCTE0 SCWE3 SCWE2 SCWE1 SCWE0 X SHE2 SHE1 SHE0 X CLTE2 CLTE1 CLTE0 Display Control R0Ah W 1 Panel IF Control4 X X X X X X X X X X X X X X GTCON GTCON Device Read R0Fh R 0 Device code read 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 R10h W 1 Stand By X X X X X X X X X X X X X X X STB R12h W 1 Power Gen1 X X X X X X X X X X X X VC3 VC2 VC1 VC0 R13h W 1 Power Gen2 X X VINT3 VINT2 VINT1 VINT0 X VGH3 VGH2 VGH1 VGH0 X VGL3 VGL2 VGL1 VGL0 R14h W 1 Power Step Up Control1 X DC22 DC21 DC0 DC12 DC11 DC10 X X X X X X BT1 BT0 R18h W 1 Oscillator Control X X X X X X X X X X RADJ5 RADJ4 RADJ3 RADJ2 RADJ1 RADJ0 Power Control R1Ah W 1 Source Driver Control X X X X X X X X X X GAMM A_TES T SDUM_ ON X SAP2 SAP1 SAP0 R20h W 1 X X X X X X X X AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R21h W 1 GRAM address set AD16-0: Set GRAM X X X X X X X AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 W 1 GRAM Write WD17-0 : Pin assignment varies according to the interface method GRAM Access R22h R 1 GRAM Read RD17-0 : Pin assignment varies according to the interface method

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Table17: Instruction Table(Continued) Index Reg. No R/W RS IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB R23h W 0 Select 18/16-Bit Data Bus Interface I/F Control R24h W 0 I/F Select Select 9/8-Bit Data Bus Interface R30h W 1 X X X X X X X SSA8 SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0 R31h W 1 Vertical Scroll Control X X X X X X X SEA8 SEA7 SEA6 SEA5 SEA4 SEA3 SEA2 SEA1 SEA0 R32h W 1 Vertical Scroll Control 2 X X X X X X X SST8 SST7 SST6 SST5 SST4 SST3 SST2 SST1 SST0 R33h W 1 X X X X X X X SS18 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 R34h W 1 Partial Screen Driving Position X X X X X X X SE18 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 R35h W 1 X X X X X X X VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 R36h W 1 Vertical RAM Address Position X X X X X X X VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 Position Control R37h W 1 Horizontal RAM Address Position HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 38h W 1 Client initiated wake-up X X X X X X X X X X X X X X X VWAKE _EN 39h W 1 MDDI Link wake-up start position WKL8 WKL7 WKL6 WKL5 WKL4 WKL3 WKL2 WKL1 WKL0 X WKF3 WKF2 WKF1 WKF0 X X 3Ah W 1 X X X X X X X X SUB_S EL7 SUB_S EL 6 SUB_S EL 5 SUB_S EL 4 SUB_S EL 3 SUB_S EL 2 SUB_S EL 1 SUB_S EL 0 3Bh W 1 X X X X X X X X SUB_W SUB_W R 6 SUB_W R 5 SUB_W R 4 SUB_W R 3 SUB_W R 2 SUB_W R 1 SUB_W R 0 MDDI I/F 3C W 1 Sub panel control X X X X X X X X FCV_E N X X X MPU_M ODE STN_E N SUB_I SUB_I

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Table19: Instruction Table(Continued) Index Reg. No R/W RS IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB R60h W 1 Test Key X X X X X X X X 0 0 0 0 1 1 1 1 R61h W 1 MTP Selection X X X X X X X MTP_W RB X X X MTP_S EL X X X MTP_E RB R62h W 1 MTP Register Setting R X R21_D R21_D R21_D R21_BT R21_BT R21_BT

0 X R63_D

R63_D R63_D R63_D R63_BT R63_BT R63_BT R63_BT R63h W 1 MTP Register Setting G X G21_D G21_D G21_D G21_B G21_B G21_B T0 X G63_D G63_D G63_D G63_D G63_B G63_B G63_B G63_B R64h W 1 MTP Register Setting B X B21_D B21_D B21_D B21_BT B21_BT B21_BT

0 X B63_D

B63_D B63_D B63_D B63_BT B63_BT B63_BT B63_BT MTP Control R65h W 1 MTP Register Offset X X X X X X X X X X X X X E_OST E_OST E_OST R66h W 1 GPIO value X X X X X X GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 R67h W 1 in/output control X X X X X X GPIO_ CON9 GPIO_ CON8 GPIO_ CON7 GPIO_ CON6 GPIO_ CON5 GPIO_ CON4 GPIO_ CON3 GPIO_ CON2 GPIO_ CON1 GPIO_ CON0 R68h W 1 GPIO Clear X X X X X X GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR GPCLR R69h W 1 GPIO interrupt enable X X X X X X GPIO_ EN9 GPIO_ EN8 GPIO_ EN7 GPIO_ EN6 GPIO_ EN5 GPIO_ EN4 GPIO_ EN3 GPIO_ EN2 GPIO_ EN1 GPIO_ EN0 GPIO Control R6Ah W 1 GPIO polarity selection X X X X X X GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL GPPOL R70h W 1 Gamma Top Bottom Control R X X CR56 CR55 CR54 CR53 CR52 CR51 CR50 X X X CR03 CR02 CR01 CR00 R71h W 1 Gamma Top Bottom Control G X X CG56 CG55 CG54 CG 53 CG52 CG51 CG50 X X X CG03 CG02 CG01 CG00 R72h W 1 Gamma Top Bottom Control B X X CB56 CB55 CB54 CB53 CB52 CB51 CB50 X X X CB03 CB02 CB01 CB00 R73h W 1 Gamma Control R 1,2 X X CR15 CR14 CR13 CR12 CR11 CR10 X X CR25 CR24 CR23 CR22 CR21 CR20 R74h W 1 Gamma Control R 3,4 X X CR35 CR34 CR33 CR32 CR31 CR30 X X CR45 CR44 CR43 CR42 CR41 CR40 R75h W 1 Gamma Control G 1,2 X X CG15 CG14 CG13 CG 12 CG11 CG10 X X CG25 CG24 CG23 CG22 CG21 CG20 R76h W 1 Gamma Control G 3,4 X X CG35 CG34 CG33 CG 32 CG31 CG30 X X CG45 CG44 CG43 CG44 CG41 CG40 R77h W 1 Gamma Control B 1,2 X X CB15 CB14 CB13 CB12 CB11 CB10 X X CB25 CB24 CB23 CB22 CB21 CB20 R78h W 1 Gamma Control B 3,4 X X CB35 CB34 CB33 CB32 CB31 CB30 X X CB45 CB44 CB43 CB42 CB41 CB40 Gamma Control R80h W 1 Gamma Select X X X X X X X X X X X X GS_SE GS_SE GS_SE GS_SE

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Instruction Descriptions Index The index instruction specifies indexes. It sets the register number in the range of 0000000b to 1111111b in binary form. However, do not access index registers and instruction bits that are not allocated in this document. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 0 X X X X X X X X X ID6 ID5 ID4 ID3 ID2 ID1 ID0 Status Read The status read instruction reads out the internal status of the IC. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R 0 0 0 0 0 0 0 0 L8 L7 L6 L5 L4 L3 L2 L1 L0 L8–0: Indicate the position of horizontal line currently being driven. No Operation (R00h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 0 No Operation This command does not have any effect on the display module. However it can be used to terminate Memory Write and Read in 22h command.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary DISPLAY DUTY CONTROL (R01h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 FP3 FP2 FP1 FP0 BP3 BP2 BP1 BP0 X X NL5 NL4 NL3 NL2 NL1 NL0 *01h Initial Value = 1000_1000_XX10_1000 FP / BP Sets the period of Blank Area, which is placed at the beginning and the end of a frame. FP[3:0] is for a Front Porch and BP[3:0] is for a Back Porch. When Front Porch and Back Porch are set, the settings should meet the following conditions. BP+FP ≤TBD lines FP ≥ TBD lines BP ≥ TBD lines When S6E63D6 operates in External Clock Operation mode, the Back Porch (BP) will start on the falling edge of the VSYNC signal and display operation begins just after the Back Porch period. The Front Porch (FP) will start when data of the number of lines specified by the NL has been displayed. During the period between the completion of the Front Porch and the next VSYNC signal, the display will remain blank. Table20: Blank Period Control with FP and BP FP[3:0] (BP[3:0]) Number of Raster Periods In Front (Back) Porch

0000 SETTING DISABLE

0001 SETTING DISABLE

--- --- 1000 8 --- --- 1100 12 1101 13 1110 14

1111 SETTING DISABLE

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary NL Specifies the number of lines driving OLED drive. The number of lines for the OLED drive can be adjusted for every eight lines. The selected value should be equal to or larger than the size of the panel to be driven. GRAM address mapping is not affected by the value of the drive duty ratio. Table21: NL and Drive Duty NL[5:0] Display Size Drive Line 00_0000 ~ 01_0011 SETTING DISABLE 01_0100 240 X 160 160 01_0101 240 X168 168 01_0110 240X176 176 01_0111 240X184 184 --- --- --- 10_0111 240 X 312 312 10_1000 240 X 320 320 10_1001 ~ 11_1111 SETTING DISABLE [NOTE] A back porch period and a front porch period will be inserted as a blank period before and after driving all LTPS lines.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary RGB INTERFACE CONTROL (R02h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X RM DM X RIM RIM VSP L HSP L EPL DPL *02h Initial Value = XXXX_XXX0_0X00_0000 RM Specifies the interface for GRAM accesse as shown below. This register and DM register can be set independently. DM Specifies the display operation mode. The interface can be set based on the bit of DM. In Internal Clock Opeartion mode the source clock for display operation comes from internal oscillator while in External Clock Opeartion mode it comes from RGB interface(DOTCLK, VSYNC, HSYNC). Table22: RM, DM, GRAM Access Interface and Display Operation Mode RM DM GRAM Access Interface Display operation mode 0 0 System interface Internal clock operation 1 1 RGB interface External clock operation [NOTE] [RM, DM]= 01, [RM, DM]=10 setting disable. RIM Specifies RGB interface mode when the RGB interface is used. This register is valid when RM is set to “1”. DM and this register should be set before proper display operation is performed through the RGB interface. Table23: RIM and RGB Interface Mode RIM[1:0] RGB Interface mode 00 18-bit RGB interface (one transfer per pixel) 01 16-bit RGB interface (one transfer per pixel) 10 6-bit RGB interface (three transfers per pixel)

11 SETTING DISABLE

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary You should notice that some display functions, which will be described later, cannot be used according to the display mode shown below. Table24: Display Functions and Display Modes Function External Clock Operation Mode Internal Clock Operation Mode Partial Display Cannot be used Can be used Scroll Function Cannot be used Can be used Rotation Cannot be used Can be used Mirroring Cannot be used Can be used Window Function Cannot be used Can be used Depending on the external display interface setting, various interfaces can be specified to match the display state. While displaying motion pictures (RGB interface), the data for display can be written in high-speed write mode, which achieves both low power consumption and high-speed access. Table25: Display State and Interface Display State Operation Mode RAM Access (RM) Display Operation Mode (DM) Still Pictures Internal Clock System interface (RM=0) Internal clock (DM=0) Motion Pictures RGB interface RGB interface (RM=1) RGB interface (DM=1) [NOTE] 1) The instruction register can only be set through the system interface(SPI). 2) The RGB interface mode should not be set during operation. For the transition flow for each operation mode, see the External Display Interface section. Internal Clock Mode All display operation is controlled by signals generated by the internal clock in internal clock mode. All inputs through the external display interface are invalid. The internal RAM can be accessed only via the system interface. RGB Interface Mode The display operations are controlled by the frame sy nchronization clock (VSYNC), raster-row synchronization signal (HSYNC), and dot clock (DOTCLK) in RGB interface mode. These signals should be supplied during display operation in this mode. The display data is transferred to the internal RAM via DB17-0 for each pixel. Combining the function of the high-speed write mode and the window address enables disp lay of both the motion picture area and the internal RAM area simultaneously. In this method, data is only transferred when the screen is updated, which reduces the amount of data transferred. The periods of the front (FP), back (BP) porch, and the display are automatically gen erated in the S6E63D6 by counting the raster-row synchronization signal (HSYNC) based on the frame synchronization signal (VSYNC).

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary VSPL Determines the active polarity of VSYNC. Table26: VSPL and VSYNC VSPL VSYNC Description 0 (1) 0 (1) Valid (Valid) 0 (1) 1 (0) Invalid (Invalid) HSPL Determines the active polarity of HSYNC. Table27: HSPL and VSYNC HSPL HSYNC Description 0 (1) 0 (1) Valid (Valid) 0 (1) 1 (0) Invalid (Invalid) EPL Determines the active polarity of ENABLE for using RGB interface. Table28: EPL, ENABLE and RAM access EPL ENABLE RAM Write RAM Address 0 (1) 0 (1) Valid (Valid) Updated (Updated) 0 (1) 1 (0) Invalid (Invalid) Hold (Hold) DPL Determines the active polarity of DOTCLK. Table29: HSPL and VSYNC DPL DOTCLK Description 0 (1) ↑(↓) Valid (Valid) 0 (1) ↓ (↑) Invalid (Invalid)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary ENTRY MODE (R03h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 CLS MDT MDT

0 BGR X X X SS X X I/D1 I/D0 X X X AM

*03h Initial Value = 0000_XXX0_XX11_XXX0 CLS: This bit is used to define the color and interface bus format, When MDT0-1 = 00 CLS = 0 : 65K-color mode through 8-bit(Index address 24h) or 16-bit bus(Index address 23h) CLS = 1 : 262K-color mode through 9-bit(Index address 24h) or 18-bit bus(Index address 23h) MDT1: This bit is active on the 80-system of 8-bit bus, and t he data for 1-pixel is transported to the memory for 3 write cycles. This bit is on the 80-system of 16-bit bus, and the data for 1-pixel is transported to the memory for 2 write cycles. When the 80-system interface mode is not set in the 8-bit or16-bit mode, set MDT1 bit to be “0”. MDT0: When 8-bit or16-bit 80 interface mode and MDT1 bit =1, MDT0 defines color depth for the IC. 8-bit (80-system), MDT0 = 0: 262k-color mode (3 times of 6-bit data transfer to GRAM) 8-bit (80-system), MDT0 = 1: 65k-color mode (5-bit, 6-bit, 5-bit data transfer to GRAM) 16-bit (80-system), MDT0 = 0: 262k-color mode (16-bit, 2-bit data transfer to GRAM) 16-bit (80-system), MDT0 = 1: 262k-color mode (2-bit, 16-bit data transfer to GRAM) Interface Mode MDT1 MDT0 Write data to GRAM * 0 0 Default value. Multiple Data Transfe r(MDT1-0) function is not available. Data Transfer is controlled by interface mode. (Depends on S_PB, ID_MIB pins, CLS register and Index address 23h or 24h) 0 1 Multiple Data Transfer(MDT1-0) function is not available. DB DB DB DB DB DB DB DB DB 15INPUT DATA R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 S(n) B5 B4 B3 B2 B1 B0RGB Arrangement Output Note: n= 1 to 240 DB DB DB DB DB DB DB DB DB 1st Transmission 2nd Transmission 3rd Transmission DB DB DB DB DB DB DB DB DB DB DB DB system 8-bit DB DB DB DB DB DB DB DB DB 15INPUT DATA R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 S(n) B5 B4 B3 B2 B1 B0RGB Arrangement Output Note: n= 1 to 240 DB DB DB DB DB DB DB DB DB 1st Transmission 2nd Transmission 3rd Transmission DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Interface Mode MDT1 MDT0 Data Assignment 0 1 DB DB DB DB DB DB DB DB DB 8INPUT DATA R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 S(n) B5 B4 B3 B2 B1 B0RGB Arrangement Output Note: n= 1 to 240 DB DB DB DB DB DB DB DB DB 1st Transmission 2nd Transmission system 16-bit DB DB DB DB DB DB DB DB DB 11INPUT DATA R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 S(n) B5 B4 B3 B2 B1 B0RGB Arrangement Output Note: n= 1 to 240 DB DB DB DB DB DB DB DB DB 1st Transmission 2nd Transmission

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary BGR: About writing 18-bit data to GRAM, it is changed <R><G><B> into <B><G><R>. - BGR = 0 ; {DB[17:12], DB[11:6], DB[5:0]} is assigned to {R , G, B}. Actually the analog value that corresponds to DB[17:12] is output firstly at source output - BGR = 1 ; {DB[17:12], DB[11:6], DB[5:0]} is assigned to {B , G, R}. Actually the analog value that corresponds to DB[5:0] is output firstly at source output. SS Selects the direction of the source driver channel in pixel unit. When user changes the value of SS, memory should be updated to apply the change. Table30: Source Output Direction Control with SS (SS = “1”) S240 S239 S238 S3 S2 S1 M M M M M M M M [NOTE] For the case of SS = “0”, refer to “GRAM ADDRESS MAP” presented earlier. You should notice that the order of source output is reversed.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary ID When ID[1], ID[0] = 1, the address counter (AC) is automatically increased by 1 after the data is written to the GRAM. When ID[1], ID[0] = 0, the AC is automatically decreased by 1 after the data is written to the GRAM. The increment/decrement setting of the address counter using ID[1:0] is done independently for the horizontal address and vertical address. AM Sets the automatic update method of the AC after the dat a is written to GRAM. When AM = “0”, the data is continuously written in horizontally. When AM = “1”, t he data is continuously written vertically. When window addresses are specified, the GRAM in the window range can be written to according to the ID[1:0] and AM. Table31: Address Direction Setting ID[1:0] = “00” H: decrement V: decrement ID[1:0] = “01” H: increment V: decrement ID[1:0] = “10” H: decrement V: increment ID[1:0] = “11” H: increment V: increment AM=”0” Horizontal Update 00000h 13FEFh 00000h 13FEFh 00000h 13FEFh 00000h 13FEFh AM=”1” Vertical Update 0000h 13FEFh 0000h 13FEFh 0000h 13FEFh 0000h 13FEFh [NOTE] When window addresses have been set, the GRAM can only be written within the window. When AM or ID is set, the start address should be written accordingly prior to memory write.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary CLOCK CONTROL (R04h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X X X DCR DCR X X X X *04h Initial Value = XXXX_XXXX_XX00_XXXX DCR Sets the division ratio of step –up clock, DCCLK, in External Clock Operation mode. In this case, DOTCLK must be input periodically and continuously. Table32: DCR and Division Ratio of DCCLK DCR[1:0] Division ratio of DCCLK

00 DOTCLK / 4

01 DOTCLK / 8

10 DOTCLK / 16

11 DOTCLK / 32

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary DISPLAY CONTROL – 1 (R05h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X X X X x X X X DISP_ ON *05h Initial Value = XXXX_XXXX_XXXX_XXX0 DISP_ON Output from the Frame Memory is enabled. This register makes No Change of contents of frame memory DISP_ON = 0 (Display is black image), DISP_ON = 1, For more information, see the Instruction Set Up Sequence. Memory Display (Example) Memory Display (Example)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary DISPLAY CONTROL – 2 (R06h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X X X X CL X X TEM ON REV *06h Initial Value = XXXX_XXXX_XXX0_XX00 CL Sets color depth of display. Table33: Color Control by CL CL Description 0 262,144 / 65,536 colors [NOTE] 1 8 colors [NOTE] It depend on interface mode(18bit or 16bit). TEMON : TEMON = 0, Disable the TE output signal from the FLM signal line for preventing Tearing Effect. TEMON = 1, Enable the TE output signal from the FLM signal line for preventing Tearing Effect. REV Displays all characters and graphics display sections wi th reversal when REV = 1. The grayscale level can be reversed. Table34: REV and Source Output Level in Normal Display Area REV GRAM Data Source Output Level in Displayed Area 6’b000000 6’b111111 V0 (High Voltage) V63(Low Voltage) 6’b000000 6’b111111 V63 (Low Voltage) V0 (High Voltage)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary PANEL INTERFACE CONTROL – 1 (R07h) PANEL INTERFACE CONTROL – 2 (R08h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X CLWE CLW EA3 CLW EA2 CLW EA1 CLW EA0 X X X X X X X X *07h Initial Value = XXX0_1100_XXXX_XXXX R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X CLWE CLW EB3 CLW EB2 CLW EB1 CLW EB0 X X X CLW EC4 CLW EC3 CLW EC2 CLW EC1 CLW EC0 *08h Initial Value = XXX0_1100_XXX0_1100 CLWEA, CLWEB, CLWEC Specifies the interval time of CLA, CLB, CLC respectively. Table35: CLWEx and the intervals CLWEx[4:0] Description 0_0000 SETTING DISABLE 0_0001 0.5 HCLK 0_0010 1 HCLK --- --- 0_1100 6 HCLK --- --- 1_1110 15 HCLK 1_1111 15.5 HCLK [NOTE] For the information of HCLK, refer to “FRAME FREQUENCY CACULATION”

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary PANEL INTERFACE CONTROL – 3 (R09h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 SCT SCT SCT E1 SCTE0 SC WE3 SC WE2 SC WE1 SC WE0 X SHE SHE SHE X CLT CLT CLT *09h Initial Value = 1000_0101_X001_X010 SCTE Specifies the rising position of SCLK1, SCLK2 Table36: SCTE and the rising position of SCLK1, SCLK2 SCTE[3:0] Description 0000 16.5 HCLKs 0001 17 HCLKs 0010 17.5 HCLKs --- ---- 1000 20.5 HCLKs --- ---- 1110 23.5 HCLKs 1111 24 HCLKs SCWE Specifies the width of SCLK1, SCLK2 Table37: SCWE and the width of SCLK1, SCLK2 SCWE[3:0] Description 0000 8 HCLKs 0001 8.5 HCLKs 0010 9 HCLKs --- --- 0101 10.5 HCLKs --- --- 1110 15 HCLKs 1111 15.5 HCLKs

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary SHE Specifies the latency of CLB and CLC. Table38: SHE and the latency of CLB and CLC SHE[2:0] Description

000 SETTING DISABLE

001 0.5 HCLK 010 1 HCLK --- --- 110 3 HCLK 111 3.5 HCLK CLTE Specifies the falling position of CLA. Table39: CLTE and the falling position of CLA CLTE[2:0] Description 001 0.5 HCLK 010 1 HCLK 011 1.5 HCLKs --- --- 110 3 HCLKs 111 3.5 HCLKs

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary PANEL INTERFACE CONTROL – 4 (R0Ah) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X X X X X X X GTC ON1 GTC ON0 *0Ah Initial Value = XXXX_XXXX_XXXX_XX00 GTCON Specifies the panel interface signals. Table40: GTCON and the panel interface signals Output Signal Output Pin GTCON[1:0]=00 GTCON[1:0]=01 GTCON[1:0]=10 GTCON[1:0]=11 BICTL_L VGH VGL VGH VGL BICTL_R VGH VGL VGH VGL FLM FLM FLM FLM FLM SFTCLK SFTCLK SFTCLK VGL VGL SFTCLKB SFTCLKB SFTCLKB VGH VGH SCLK1 SCLK1 SCLK2 SCLK1 SCLK2 SCLK2 SCLK2 SCLK1 SCLK2 SCLK1 EX_FLM EX_FLM EX_FLM EX_FLM EX_FLM EX_CLK EX_CLK EX_CLKB VGL VGL EX_CLKB EX_CLKB EX_CLK VGH VGH ESR ESR ESR ESR ESR CLA CLA CLA CLA CLA CLB CLB CLB CLB CLB CLC CLC CLC CLC CLC

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary STAND BY (R10h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X X X X X X X X STB *10h Initial Value = XXXX_XXXX_XXXX_XXX1 STB When STB = “1”, S6E63D6 enters Standby mode, where display operation completely stops including the internal R-C oscillation. Furthermore, no ex ternal clock pulses are supplied. For details, see the “STANDBY SEQENCE” described later. Only the following instructions can be executed during the standby mode. − Standby mode cancel ; STB = “0”

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary POWER GEN1 (R12h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X X X X X VC3 VC2 VC1 VC0 *12h Initial Value = XXXX_XXXX_XXXX_1000 V reference voltage of VLOUT1, VLOUT2 and VLOUT3. [NOTE] Set VCI1 in the range of VCI > VCI1 + 0.3V VC[3:0] VCI1 [Without Load] 0000 2.10 V 0001 2.15 V 0010 2.20 V 0011 2.25 V 0100 2.30 V 0101 2.35 V 0110 2.40 V 0111 2.45 V 1000 2.50 V 1001 2.55 V 1010 2.60 V 1011 2.65 V 1100 2.70 V 1101 2.75 V

1110 Setting Disable

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary POWER GEN2 (R13h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X VINT3 VINT2 VINT1 VINT0 X VGH3 VGH2 VGH1 VGH0 X VGL3 VGL2 VGL1 VGL0 *13h Initial Value = XX01_01X0_011X_1010 VINT3[3:0] set VINT (control voltage of OLED Panel). It can be amplified -2.0 to -0.5 times of VCIR. VINT[3:0] VINT value 0000 -1.0 V 0001 -1.2 V 0010 -1.4 V 0011 -1.6 V 0100 -1.8 V 0101 -2.0 V 0110 -2.2 V 0111 -2.4 V 1000 -2.6 V 1001 -2.8 V 1010 -3.0 V 1011 -3.2 V 1100 -3.4 V 1101 -3.6 V 1110 -3.8 V 1111 -4.0 V [NOTE] Set VINIT in the range of V VINT > VLOUT3 + 1.0V VGH[3:0] set VGH (High Voltage Level for Gate). VGH[3:0] VGH value 0000 4.6 V 0001 4.8 V 0010 5.0 V 0011 5.2 V 0100 5.4 V 0101 5.6 V 0110 5.8 V 0111 6.0 V

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 1000 6.2 V 1001 6.4 V 1010 6.6 V

1011 Setting disable

1100 Setting disable

1101 Setting disable

[NOTE] Set VGH in the range of VGH < VLOUT2-1.0V VGL[3:0] bits set VGL (Low Voltage Level for Gate). VGL[3:0] VGL Value 0000 -5.0 V 0001 -5.2 V 0010 -5.4 V 0011 -5.6 V 0100 -5.8 V 0101 -6.0 V 0110 -6.2 V 0111 -6.4 V 1000 -6.6 V 1001 -6.8 V 1010 -7.0 V 1011 -7.2 V 1100 -7.4 V 1101 -7.6 V 1110 -7.8 V [NOTE] Set VGL in the range of VGL > VLOUT3 + 1.0V

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary POWER STEP UP CONTROL 1 (R14h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X DC2 DC2 DC2

0 X DC1

0 X X X X X X BT1 BT0

*14h Initial Value = X100_X010_XXXX_XX00 DC2[2:0] is the operating frequency in the step-up circuit 2 is selected. DC1[2:0] is the operating frequency in the step-up circuit 1 is selected. Step-up Cycle in Step-up Circuit 2 Step-up Cycle in Step-up Circuit 1 DC2[2:0] DM=0 DM=1 DC1[2:0] DM=0 DM=1

000 OSC_CK/16 DCCLK/16 000 OSC_CK/16 DCCLK/16

001 OSC_CK/24 DCCLK/24 001 OSC_CK/24 DCCLK/24

010 OSC_CK/32 DCCLK/32 010 OSC_CK/32 DCCLK/32

011 OSC_CK/48 DCCLK/48 011 OSC_CK/48 DCCLK/48

100 OSC_CK/64 DCCLK/64 100 OSC_CK/64 DCCLK/ 64

101 OSC_CK/96 DCCLK/96 101 OSC_CK/96 DCCLK/96

110 OSC_CK/128 DCCLK/128 110 OSC_CK/128 DCCLK/128

111 OSC_CK/256 DCCLK/256 111 OSC_CK/256 DCCLK/256

[NOTE] DM is Display Method. DCCLK is for External I/F. See instruction R02h, R04h. BT[1:0] switch the output factor of step-up. Adjust scale factor of the step-up circuit by the voltage used. BT[1:0] VLOUT1 VLOUT2 VLOUT3

00 VCI1 x 2 VCI1 x 4 -(VCI1 x 4)

01 VCI1 x 2 VCI1 x 4 -(VCI1 x 3)

10 VCI1 x 2 VCI1 x 3 -(VCI1 x 4)

11 VCI1 x 2 VCI1 x 3 -(VCI1 x 3)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary START OSCILLATION (R18h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X X X RADJ5 RADJ4 RADJ3 RADJ2 RADJ1 RADJ0 *18h Initial Value = XXXX_XXXX_XX01_1111 Select the oscillation frequency of internal oscillator. RADJ[5:0] Oscillation Speed RADJ[5:0] Oscillation Speed 000000 x 0.543(Min.) 010101 x 0.782 000001 x 0.551 010110 x 0.800 000010 x 0.560 010111 x 0.818 000011 x 0.568 011000 x 0.835 000100 x 0.578 011001 x 0.855 000101 x 0.586 011010 x 0.877 000110 x 0.596 011011 x 0.899 000111 x 0.606 011100 x 0.921 001000 x 0.615 011101 x 0.946 001001 x 0.626 011110 x 0.972 001010 x 0.637 011111 x 1.000 001011 x 0.647 100000 x 1.037 001100 x 0.660 100001 x 1.067 001101 x 0.671 100010 x 1.101 001110 x 0.685 100011 x 1.135 001111 x 0.697 100100 x 1.172 010000 x 0.707 100101 x 1.212 010001 x 0.721 100110 x 1.256 010010 x 0.736 100111 x 1.302 010011 x 0.751 101000 X1.352(Max.) 010100 x 0.766 101001 ~

111111 Setting disable

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary SOURCE DRIVER CONTROL (R1Ah) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X X X GAMMA _TEST SDUM _ON X SAP SAP SAP *1Ah Initial Value = XXXX _XXXX_XX00_X101 When GAMMA_TEST=’1’, V0/V63 pins are shorted to each gamma voltage V0/V63 and gamma voltage V0/V63 can be monitored or be forced by external voltage level. GAMMA_TEST V0 / V63

0 Hi-z

1 V0 / V63

When SDUM_ON=’1’, SOUT_DUM1 and SOUT_DUM240 pins are shorted to SOUT[1], SOUT[240] output and can be monitored. SDUM_ON SOUT_DUM1 / SOUT_DUM240

1 SOUT[1] / SOUT[240]

Adjust the slew-rate of the operational amplifier of the source driver. If higher SAP[2:0] is set, OLED panel having higher resolution of higher frame frequency can be driven be cause the slew-rate of the operational amplifier is increased. But, these bits must be set as adequate value because the amount of fixed current of the operational amplifier is also adjusted. During non-display, when SAP[2:0]=”000”, operational amplifiers are turned off, so current consumption can be reduced SAP[2:0] Slew-Rate of Operational Amplifier Amount of Current in Operational Amplifier 000 Operation of the operational amplifier stops.

001 Slow Small

010 Slow or medium Small or medium

011 Medium Medium

100 Medium or small fast Medium or small large

101 Small fast Small large

110 Fast large

111 Big fast Big large

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary GRAM ADDRESS SET (R20h) GRAM ADDRESS SET (R21h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 *20h Initial Value = XXXX _XXXX_0000_0000 R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X AD1 AD1 AD1 AD1 AD1 AD1 AD1

0 AD9 AD8

*21h Initial Value = XXXX _XXX0_0000_0000 AD You can write initial GRAM address into internal Addres s Counter (AC). When GRAM data is transferred through System Interface or RGB Interface, the AC is automat ically updated according to AM and ID. This allows consecutive write without re-setting address in AC. But when GRAM data is read, the AC is not automatically updated. GRAM address setting is not allowed in Standby mode. Ensure that the address is set within the specified window area. When RGB interface is used (RM=”1”) to access GRAM, AD[16:0] will be set in the address counter at the falling edge of the VSYNC signal. And when one uses System Interface to access GRAM (RM = “0”), AD[16:0] will be set upon the execution of an instruction. Table41: GRAM Address Range AD[16:0] GRAM setting “00000h” to “00AFh” Bitmap data for G1 “00100h” to “01AFh” Bitmap data for G2 “00200h” to “02AFh” Bitmap data for G3 “00300h” to “03AFh” Bitmap data for G4 M M M M “13C00h” to “13CEFh” Bitmap data for G317 “13D00h” to “13DEFh” Bitmap data for G318 “13E00h” to “13EEFh” Bitmap data for G319 “13F00h” to “13FEFh” Bitmap data for G320

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary WRITE DATA TO GRAM (R22h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 RAM write data (WD17-0): Pin assignment varies according to the interface method. (see the following figure for more information) WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0W 1 When RGB-interface WD17-0: Input data for GRAM can be expanded to 18 bits. The expansion format varies according to the interface method. The input data selects the grayscale level. After a write, the address is automatically updated according to I/D bit settings. The GRAM cannot be accessed in standby mode. When 16- or 8-bit interface is in use, the write data is expanded to 18 bits by writing the MSB of the <R><B> data to its LSB. When data is written to RAM used by RGB interface via t he system interface, please make sure that write data conflicts do not occur. When the 18-bit RGB interface is in use, 18-bit data is written to RAM via DB17-0 and 262,144-colors are available. When the 16-bit RGB interface is in use, the MSB is written to its LSB and 65,536-colors are available. Write Index 00h or another where, Address hold Write More ? Address is updated by 1 Start Yes No Index Write (22h) ( Memory Write ) Window Address Set (index 35h, 36h, 37h) Write Data Start Address Set (index 20h, 21h) Figure6: Memory Data Write Sequence

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary READ DATA FROM GRAM (R22h) W R S DB1 DB1 DB1 DB1 DB1 DB1 DB1 DB1

0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

R 1 RAM Read data (RD17-0): Pin assignment varies according to the interface method. (see the following figure for more information) RD17–0: Read 18-bit data from the GRAM. When the data is read to the CPU, the first-word read immediately after the GRAM address setting is latched from the GRAM to the internal read-data latch. The data on the data bus (DB17–0) becomes invalid and the second-word read is normal. In case of 16-/8-bit interface, the LSB of <R><B> color data will not be read. This function is not available in RGB interface mode. Read More ? Yes No 18-/16- System Interface Read Valid Data Set Index 23h and RM = 0 Read Dummy Data 9-/8- System Interface Write Index 00h or another Where, Address hold Address is updated by 1 Read More ? Yes No Read Upper Valid Data Read Lower Valid Data Read Dummy Data 2 times Write Index 00h or another Where, Address hold Address is updated by 1 Window Address Set (index 35h, 36h, 37h) Start Address Set (index 20h, 21h) Index Write (22h) Start Set Index 24h and RM = 0 Window Address Set (index 35h, 36h, 37h) Start Address Set (index 20h, 21h) Index Write (22h) Start Figure7: Memory Data Read Sequence

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary SELECT DATA BUS 1 (R23h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 0 Select 18-/16-bit Data Bus Interface SELECT DATA BUS 2 (R24h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 0 Select 9-/8-bit Data Bus Interface We can select system interface mode by pins and instruction as following. Table42: System Interface mode Pins Registers MDDI _EN S_PB ID_MIB Index Address Command ( CLS ) Command MDT[1] Command MDT[0] Description 0 x 80-system 8-bit 65k bus interface 0 80-system 8-bit 260k bus interface 0 (80 8bit) 1 80-system 8-bit 65k bus interface default & 24h (9/8bit) 1( 80 9bit) x X 80-system 9-bit 260k bus interface 0 80-system 16-bit 65k bus interface 0 1 80-system 16-bit 260k bus interface 0 (80 16bit)

1 X 80-system 16-bit 260k bus interface

(80 mode) Index 23 h (18/16bit) 1( 80 18bit) x X 80-system 18-bit 260k bus interface

0 X 68-system 8-bit 65k bus interface

0 68-system 8-bit 260k bus interface 0 (68 8bit) 1 68-system 8-bit 65k bus interface default & 24h (9/8bit) 1 (68 9bit) x X 68-system 9-bit 260k bus interface 0 68-system 16-bit 65k bus interface 0 1 68-system 16-bit 260k bus interface 0 (68 16bit) 1 x 68-system 16-bit 260k bus interface (Parallel (68 mode) Index 23 h (18/16bit) 1 (68 18bit) x x 68-system 18-bit 260k bus interface (Serial) ID x x x x Serial peripheral interface (SPI) 1 x x x x x x [NOTE] For details, see the ENTRY MODE (Instruction R03h).

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary VERTICAL SCROLL CONTROL 1 (R30h, R31h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X SSA SSA SSA SSA SSA SSA SSA SSA SSA W 1 X X X X X X X SEA SEA SEA SEA SEA SEA SEA SEA SEA *30h Initial Value = XXXX_XXX0_0000_0000 *31h Initial Value = XXXX_XXX1_0011_1111 SSA8-0: Specify scroll start address at the scroll display for vertical smooth scrolling. SSA8 SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0 Scroll Start Address 0 0 0 0 0 0 0 0 0 0 raster-row 0 0 0 0 0 0 0 0 1 1 raster-row 0 0 0 0 0 0 0 1 0 2 raster-row 0 0 0 0 0 0 0 1 1 3 raster-row 0 0 0 0 0 0 1 0 0 4 raster-row 0 0 0 0 0 0 1 0 1 5 raster-row : : : : : : : : 1 0 0 1 1 1 1 0 0 316 raster-row 1 0 0 1 1 1 1 0 1 317 raster-row 1 0 0 1 1 1 1 1 0 318 raster-row 1 0 0 1 1 1 1 1 1 319 raster-row SEA8-0: Specify scroll end address at the scroll display for vertical smooth scrolling. SEA8 SEA7 SEA6 SEA5 SEA4 SEA3 SEA2 SEA1 SEA0 Scroll End Address 0 0 0 0 0 0 0 0 0 0 raster-row 0 0 0 0 0 0 0 0 1 1 raster-row 0 0 0 0 0 0 0 1 0 2 raster-row 0 0 0 0 0 0 0 1 1 3 raster-row 0 0 0 0 0 0 1 0 0 4 raster-row 0 0 0 0 0 0 1 0 1 5 raster-row : : : : : : : : 1 0 0 1 1 1 1 0 0 316 raster-row 1 0 0 1 1 1 1 0 1 317 raster-row 1 0 0 1 1 1 1 1 0 318 raster-row 1 0 0 1 1 1 1 1 1 319 raster-row [NOTE] Don’t set any higher raster-row than 319 (“13F”H) Set SS18-10 ≤ SSA8-0, if set out of range, SSA8-0 = SS18-10. Set SE18-10 ≥ SEA8-0, if set out of range, SEA8-0 = SE18-10

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary VERTICAL SCROLL CONTROL 2 (R32h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X SST SST SST SST SST SST SST SST SST *32h Initial Value = XXXX_XXX0_0000_0000 SST8-0: Specify scroll start and step at the scroll display for vertical smooth scrolling. Any raster-row from the 1st to 320th can be scrolled for the number of the raster-row. After 319th raster-row is displayed, the display restarts from the first raster-row. When SST8-0 = 00000000, Vertical Scroll Function is disabled. SST8 SST7 SST6 SST5 SST4 SST3 SST2 SST1 SST0 Scroll Step 0 0 0 0 0 0 0 0 0 Scroll Disabled 0 0 0 0 0 0 0 0 1 1 raster-row 0 0 0 0 0 0 0 1 0 2 raster-row 0 0 0 0 0 0 0 1 1 3 raster-row 0 0 0 0 0 0 1 0 0 4 raster-row 0 0 0 0 0 0 1 0 1 5 raster-row : : : : : : : : 1 0 0 1 1 1 1 0 0 316 raster-row 1 0 0 1 1 1 1 0 1 317 raster-row 1 0 0 1 1 1 1 1 0 318 raster-row 1 0 0 1 1 1 1 1 1 319 raster-row [NOTE] Don’t set any higher raster-row than 319 (“13F”H) Set SS18-10 < SSA8-0 + SST8-0 ≤ SEA8-0 ≤ SE18-10, if set out of range, Scroll function is disabled

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Figure8: Vertical Scroll Display

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary PARTIAL SCREEN DRIVING POSITION (R33h, R34h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X SS18 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 W 1 X X X X X X X SE18 SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 *33h Initial Value = XXXX_XXX0_0000_0000 *34h Initial Value = XXXX_XXX1_0011_1111 SS18–10: Specify the drive starting position for the first screen in a line unit. The OLED driving starts from the ‘set value +1’ gate driver. SE18–10: Specify the driving end position for the screen in a li ne unit. The OLED driving is performed to the ‘set value + 1’ gate driver. For instance, when SS18–10 = 019h and SE18–10 = 029h are set, the OLED driving is performed from G26 to G42, and non-display driving is pe rformed for G1 to G25, G43, and others. Ensure that SS18–10 ≤ SE18–10 ≤13Fh. [NOTE] DO NOT set the partial setting when the operation is in the normal display condition. Set this register only when in the partial display condition. Ex) SS18-0=007h and SE18-0=010h are performed from G8 to G17. The S6E63D6 can select and drive partial screens at any position with the screen-driving position registers (R33h, R34h). Any partial screens required for display are selectively driven and reducing OLED-driving voltage and power consumption. OCT 1st 08:00 AM G26 G42 Non-display area Partial screen 17 raster-row driving Non-display area

• Driving raster-row: NL5-0 = 101000 (320 lines)
• Partial screen setting: SS18-10 = 019H, SE18-10 = 029H Figure9: Driving On Partial Screen

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary RESTRICTION ON PARTIAL DISPLAY AREA SETTING The following restrictions must be satisfied when setting the start line (SS18 to 10) and end line (SE18 to 10) of the partial screen driving position register (R33h, R34h) for the S6E63D6. Note t hat incorrect display may occur if the restrictions are not satisfied. Table43: Restrictions on the partial Screen Driving Position Register Setting Register setting Display operation (SE18 to 10) – (SS18 to 10) = NL*8 Full screen display Normally displays (SS18 to 10) to (SE18 to 10) (SE18 to 10) – (SS18 to 10) < NL*8 Partial display Normally displays (SS18 to 10) to (SE18 to 10) Black display for all other times (RAM data is not related at all) (SE18 to 10) – (SS18 to 10) > NL*8 Setting disabled [NOTE] 000h ≤ SS18 to 10 ≤ SE18 to 10 ≤ 13Fh

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary VERTICAL RAM ADDRESS POSITION (R35h,R36h) HORIZONTAL RAM ADDRESS POSITION (R37h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X VSA VSA VSA VSA VSA VSA VSA VSA VSA W 1 X X X X X X X VEA VEA VEA VEA VEA VEA VEA VEA VEA W 1 HSA HSA HSA HSA HSA HSA HSA HSA HEA HEA HEA HEA HEA HEA HEA HEA *35h Initial Value = XXXX_XXX0_0000_0000 *36h Initial Value = XXXX_XXX1_0011_1111 *37h Initial Value = 0000_0000_1110_1111 VSA8-0/VEA8-0: Specify the vertical start/end positions of a window for access in memory. Data can be written to the GRAM from the address specified by VSA8-0 to the address specified by VEA8-0. Note that an address must be set before RAM is written. HSA7-0/HEA7-0: Specify the horizontal start/end positions of a window for access in memory. Data can be written to the GRAM from the address specified by HSA7-0 to the address specified by HEA 7-0. Note that an address must be set before RAM is written.. 00000h 13F00h 000EFh 13FEFh HSA HEA VSA VEA GRAM Window Window Address Range - 0 - 0 HSA VSA HEA VEA EFh 13Fh Figure10: Window Address Function [NOTE] Ensure that the Window addresses are within the GRAM address space.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary CLIENT INITIATED WAKE-UP (R38h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X X X X X X X X VWAK E_EN *38h Initial Value = XXXX_XXXX_XXXX_XXX0 VWAKE_EN : When VWAKE_EN is 1, client initiated wake-up is enabled. But parameter data IB[15:1] must be “0000h”, otherwise, client initiated wake-up is disabled. MDDI LINK WAKE-UP START POSITION (R39h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 WKL WKL WKL WKL WKL WKL WKL WKL WKL

0 X WKF

0 X X

*39h Initial Value = 0000_0000_0X00_00XX WKF3-0 : When client initiated wake-up is used at MDDI, the frame position that data is updated is set by the value of WKF 3-0. The range of WKF is from ‘0000’ to ‘1111’. If WKF is ‘0000’, data is updated at the first frame, and if “1111” data update starts after 16th frame. WKL8-0 : When client initiated wakeup is used at MDDI, data is updated at the line the value of WKL7-0 in the frame that is set by WKF3-0. The range of WKL is from ‘000h’ to ‘1FFh’. If WKL is ‘000h’, data is updated at the first line, and if WKL is ‘0FFh’, data update starts at the 256 th line. Setting of WFK and WKL is needed for client-initiated link wake-up. For example, WKF is “0010” and WKL is “0001”, data is updated at second line of third frame. SUB PANEL CONTROL 1 (R3Ah / R3Bh) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X SUB_SEL W 1 X X X X X X X X SUB_WR *3Ah Initial Value = XXXX_XXXX_0111_1010 *3Bh Initial Value = XXXX_XXXX_0010_0010 SUB_SEL : SUB_SEL is the index of main/sub panel selection. Initial value of SUB_SEL is ‘7Ah’. In MDDI mode, If written register address is ‘7Ah’ (ini tial state: SUB_SEL is ‘7Ah’) and register data is ‘0001h’, then main panel is selected, and if that is “0000h”, then sub panel is selected. Using SUB_SEL register, Main / Sub panel selection index change is possible. SUB_WR : SUB_WR is the index of sub panel data write. Initial value of SUB_WR is ‘22h’. When MDDI host transfer GRAM data to sub panel dr iver IC via video stream packet, SUB_WR (initially 22h), index for GRAM access is automatically transferred before GRAM data transfer. When sub panel driver IC uses other address, 22h address have to be changed. Then user can change SUB_WR value from 22h to other value.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary SUB PANEL CONTROL 2 (R3Ch) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X FCV_ EN X X X MPU_ MODE STN _EN SUB _IM1 SUB _IM0 *3Ch Initial Value = XXXX_XXXX_0XXX_0000 SUB_IM1-0: set the sub-panel interface SUB_ IM1 SUB_ IM0 Interface 0 0 18bit 0 1 9bit 1 0 16bit 1 1 8bit STN_EN: set the panel property. STN_EN = “1”: STN panel. STN_EN = “0”: TFT panel . MPU_MODE: set the MPU interfaces MPU_MODE = “1”: 68 mode MPU_MODE = “0”: 80 mode FCV_EN : data format conversion enable signal FCV_EN = “1”: 16 bit data format conversion (not used) FCV_EN = “0”: current 16bit data format

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary TEST KEY COMMAND (R60h) MTP CONTROL (R61h) MTP REGISTER SETTING (R62h, R63h, R64h, R65h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X 0 0 0 0 1 1 1 1 W 1 X X X X X X X MTP_ WRB X X X MTP_ SEL X X X MTP_ ERB W 1 X R21_DK2 R21_DK1 R21_DK0 R21_BT2 R21_BT1 R21_BT0 X R63_DK3 R63_DK2 R63_DK1 R63_DK0 R63_BT3 R63_BT2 R63_BT1 R63_BT0 W 1 X G21_DK2 G21_DK1 G21_DK0 G21_BT2 G21_BT1 G21_BT0 X G63_DK3 G63_DK2 G63_DK1 G63_DK0 G63_BT3 G63_BT2 G63_BT1 G63_BT0 W 1 X B21_DK2 B21_DK1 B21_DK0 B21_BT2 B21_BT1 B21_BT0 X B63_DK3 B63_DK2 B63_DK1 B63_DK0 B63_BT3 B63_BT2 B63_BT1 B63_BT0 W 1 X X X X X X X X X X X X X E_OST2 E_OST1 E_OST_0 *Initial Value MTP_WRB: 1’b1, MTP_SEL: 1’b1, MTP_ERB: 1’b1 E_OST[2:0]:3’d0 Test Key Command : Protection command. When Test Key Command =8Ch, MTP_WRB and MTP_ERB are valid MTP_WRB: MTP Write enable signal. If you want to write data to MTP cell, set MTP_WRB = 0 MTP_SEL: Selects MTP value or register value added to CR5[ 6:0], CG5[6:0], CB5[6:0], CR3[5:0], CG3[5:0], and CB3[5:0] MTP_ERB: Enable for MTP initial or erase. When MTP_ERB = 0, MTP initialization or erase is enabled. R21_DK[3:0], R21_BT[[3:0]: V21(Red) offset compensation value. G21_DK[3:0], G21_BT[[3:0]: V21(Green) offset compensation value. B21_DK[3:0], B21_BT[[3:0]: V21(Blue) offset compensation value. R63_DK[4:0], R63_BT[[4:0]: V63(Red) offset compensation value. G63_DK[4:0], G63_BT[[4:0]: V63(Green) offset compensation value. B63_DK[4:0], B63_BT[[4:0]: V63(Blue) offset compensation value. E_OST[2:0]: ELVDD offset compensation value

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary R(G,B)_21[2:0] complement offset value R(G,B)_63[3:0] complement offset value E_OST[2:0] complement offset value 011 +3 0111 +7 011 +3 010 +2 0110 +6 010 +2 001 +1 0101 +5 001 +1 000 0 0100 +4 000 0 111 -1 0011 +3 111 -1 110 -2 0010 +2 110 -2 101 -3 0001 +1 101 -3 100 -4 0000 0 100 -4 1111 -1 1110 -2 1101 -3 1100 -4 1011 -5 1010 -6 1001 -7 1000 -8

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Enter Standby Mode ( STB = "1" ) Start Enable Initialization ( MTP_ERB = "0" ) Enable MTP Write ( MTP_WRB = "0" ) Wait 1ms or more Wait 100ms or more End RESET Disable MTP Write ( MTP_WRB = "1" ) Supply MTPG, MTPD ( MTPG = 21.5V), MTPD = 0V) Cut Off MTPG, MTPD ( MTPG = MTPD = floating ) RESET Set Test Key ( TEST_KEY parameter = "0Fh" ) Start Display On after a RESET Initialization & Erase Flow Enter Standby Mode ( STB = "1" ) Supply MTPG, MTPD ( MTPG = 0V), MTPD = 16.5V) End Initialization & Erase Flow Set Test Key ( TEST_KEY Parameter = "0Fh" ) Set Desired MTP Value Find Desired MTP value with MTP_SEL = "0" Bad Good A. Flow of MTP Initialization & Erase B. Flow of MTP Program Figure16: MTP Initialization, Erase and program

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Figure17: Timing of MTP Program Figure18: Timing of MTP Load

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary GPIO CONTROL (R66h/R67h/R68h/R69h/R6Ah) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X GPI GPI GPI GPI GPI GPI GPI GPI GPI GPI W 1 X X X X X X GPI O_C ON9 GPI O_C ON8 GPI O_C ON7 GPI O_C ON6 GPI O_C ON5 GPI O_C ON4 GPI O_C ON3 GPI O_C ON2 GPI O_C ON1 GPI O_C ON0 W 1 X X X X X X GPC LR9 GPC LR8 GPC LR7 GPC LR6 GPC LR5 GPC LR4 GPC LR3 GPC LR2 GPC LR1 GPC LR0 W 1 X X X X X X GPI O_E GPI O_E GPI O_E GPI O_E GPI O_E GPI O_E GPI O_E GPI O_E GPI O_E GPI O_E W 1 X X X X X X GPP OL9 GPP OL8 GPP OL7 GPP OL6 GPP OL5 GPP OL4 GPP OL3 GPP OL2 GPP OL1 GPP OL0 *66h Initial Value = XXXX_XX00_0000_0000 *67h Initial Value = XXXX_XX00_0000_0000 *68h Initial Value = XXXX_XX00_0000_0000 *69h Initial Value = XXXX_XX00_0000_0000 *6Ah Initial Value = XXXX_XX11_1111_1111 GPIO: GPIO value. When GPIO is input mode, GPIO value is set to the register. GPIO_CON: Control of GPIO, When GPIO_CON is “0”, then GPIO is input mode, and when “1”, then GPIO is output mode GPCLR: After client is wakeup, GPIO GPIO_EN: When GPIO is set input, if GPIO_EN is “1”, it acts as enable internal interrupt. GPPOL: If the bit is set to “1”, GPIO interrupt happens at rising edge of GPIN, If set to “0”, it happens at falling edge. For more information about these registers, refer to GPIO CONTROL section

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary GAMMA CONTROL (R70h to R78h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X CR56 CR55 CR54 CR53 CR52 CR51 CR50 X X X CR03 CR02 CR01 CR00 W 1 X X CG56 CG55 CG54 CG53 CG52 CG51 CG50 X X X CG03 CG02 CG01 CG00 W 1 X X CB56 CB55 CB54 CB53 CB52 CB51 CB50 X X X CB03 CB02 CB01 CB00 W 1 X X CR15 CR14 CR13 CR12 CR11 CR10 X X CR25 CR24 CR23 CR22 CR21 CR20 W 1 X X CR35 CR34 CR33 CR32 CR31 CR30 X X CR45 CR44 CR43 CR42 CR41 CR40 W 1 X X CG15 CG14 CG13 CG12 CG11 CG10 X X CG25 CG24 CG23 CG22 CG21 CG20 W 1 X X CG35 CG34 CG33 CG32 CG31 CG30 X X CG45 CG44 CG43 CG44 CG41 CG40 W 1 X X CB15 CB14 CB13 CB12 CB11 CB10 X X CB25 CB24 CB23 CB22 CB21 CB20 W 1 X X CB35 CB34 CB33 CB32 CB31 CB30 X X CB45 CB44 CB43 CB42 CB41 CB40 These registers set the one of the 9 gamma sets according to GS_SEL[3:0] CR5[6:0]: The amplitude adjust register CR4[4:0]: The amplitude adjust register CR3[4:0]: The amplitude adjust register CR2[4:0]: The amplitude adjust register CR1[4:0]: The amplitude adjust register CR0[3:0]: The amplitude adjust register CG5[6:0]: The amplitude adjust register CG4[4:0]: The amplitude adjust register CG3[4:0]: The amplitude adjust register CG2[4:0]: The amplitude adjust register CG1[4:0]: The amplitude adjust register CG0[3:0]: The amplitude adjust register CB5[6:0]: The amplitude adjust register CB4[4:0]: The amplitude adjust register CB3[4:0]: The amplitude adjust register CB2[4:0]: The amplitude adjust register CB1[4:0]: The amplitude adjust register CB0[3:0]: The amplitude adjust register For details, see the GAMMA ADJUSTMENT FUNCTION. GAMMA SELECT (R80h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 W 1 X X X X X X X X X X X X GS_ SEL3 GS_ SEL2 GS_ SEL1 GS_ SEL0 *80h Initial Value = XXXX_XXXX_XXXX_0100 Selects the gamma set controlled by 70H ~ 78H

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary RESET FUNCTION The S6E63D6 is initialized internally by RESET input. The reset input should be held ‘L’ for at least 10us. Do not access the GRAM nor initially set the instructions until the R-C oscillation frequency is stable after power has been supplied (10 ms). INSTRUCTION SET INITIALIZATION 1. Display duty control (R01h) : FP3_0=1000, BP3_0=1000, NL5_0=10_1000 2. RGB interface control (R02h) : RM=0, DM=0, RIM1_0=00, VSPL=0, HSPL=0, EPL=0, DPL=0 3. Entry mode (R03h) : CLS=0, MDT1_0=00, BGR=0, SS=0, ID1_0=11, AM=0 4. Clock control (R04h) : DCR1_0=00 5. Display control 1 (R05h) : DISP_ON=0 6. Display control 2 (R06h) : CL=0, TEMON=0, REV=0 7. Panel interface control 1 (R07h) : CLWEA4_0=0_1100 8. Panel interface control 2 (R08h) : CLWEB4_0=0_1100, CLWEC4_0=0_1100 9. Panel interface control 3 (R09h) : SCTE3_0=1000, SCWE3_0=0101, SHE2_0=001, CLTE2_0=010 10. Panel interface control 4 (R0Ah) : GTCON1_0=00 11. Stand by (R10h) : STB=1 12. Power gen 1 (R12h) : VC3_0=1000 13. Power gen 2 (R13h) : VINT3_0=0101, VGH3_0=0011, VGL3_0=1010 14. Power step up control 1 (R14h) : DC22_0=100, DC12_0=010, BT1_0=00 15. Start oscillation (R18h) : RADJ5_0=01_1111 16. Source driver control (R1Ah) : GAMMA_TEST=0, SDUM_ON=0, SAP2_0=101 17. GRAM address set (R20h) : AD7_0=0000_0000 18. GRAM address set (R21h) : AD16_8=0_0000_0000 19. Vertical scroll control 1 (R30h, R31h) : SSA8_0=0_0000_0000, SEA8_0=1_0011_1111 20. Vertical scroll control 2 (R32h) : SST8_0=0_0000_0000 21. Partial screen driving position (R33h, R34h) : SS18_0=0_0000_0000, SE18_0=1_0011_1111 22. Vertical RAM address position (R35h, R36h) : VSA8_0=0_0000_0000, VEA8_0=1_0011_1111 23. Horizontal RAM address position (R37h) : HAS7_0=0000_0000, HEA7_0=1110_1111 24. Client initiated wake up (R38h) : VWAKE_EN=0 25. MDDI link wake up start position (R39h) : WKL8_0=0_0000_0000, WKF3_0=0000 26. Sub panel control 1(R3Ah, R3Bh) : SUB_SEL7_0=0111_1010, SUB_WR7_0=0010_0010 27. Sub panel control 2 (R3Ch) : FCV_EN=0, MPU_MODE=0, STN_EN=0, SUB_IM1_0=00 28. MTP control (R61h) : MTP_WRB=1, MTP_SEL=1, MTP_ERB=1 29. MTP register setting 1 (R62h) : R21_DK2_0=000, R21_BT2_0=000, R63_DK3_0=0000, R63_BT3_0=0000 30. MTP register setting 2 (R63h) : G21_DK2_0=000, G21_BT2_0=000, G63_DK3_0=0000, G63_BT3_0=0000 31. MTP register setting 3 (R64h) : B21_DK2_0=000, B21_BT2_0=000, B63_DK3_0=0000, B63_BT3_0=0000 32. MTP register setting 4 (R65h) : E_OST2_0=000 33. GPIO control (R66h, R67h, R68h. R69h, R6Ah) : GPIO9_0=00_0000_0000, GPIO_CON9_0=00_0000_0000 GPCLR9_0=00_0000_0000, GPIO_EN9_0=00_0000_0000, GPPOL9_0=11_1111_1111

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary POWER SUPPLY PATTERN DIAGRAMS FOR VOLTAGE SETTING The following figure shows a pattern diagram for the voltage setting and an example of waveforms. Figure19: Pattern Diagram for Voltage Setting

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary VOLTAGE REGULATION FUNCTION The S6E63D6 has the internal voltage regulator. By the use of this function, unexpected damages on internal logic circuit can be avoided. Furthermore, power consumption can also be obtained. Detailed function description and application configuration is described in the following diagram. Figure20: Voltage Regulation Function

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary INTERFACE SPECIFICATION The S6E63D6 incorporates a system interface, which is used to set instructions, and an external display interface, which is used to display motion pictures. Selecting these interfaces to match the screen data (motion picture or still picture) enables efficient transfer of data for display. The external display interface includes RGB interface. This allows flicker-free screen update. When RGB interface is selected, the synchronization signals (VSYNC, HSYNC, and DOTCLK) are available for use in operating the display. The display data (DB17-0) is wr itten according to the values of the data enable signal (ENABLE) in synchronization with the VSYNC, HSYNC, and DOTCLK signals. In addition, using the window address function enables rewriting only to the internal RAM area to display motion pictures. Using this function also enables simultaneously display of the motion picture area and the RAM data that was written. HOSTs S6E63D3 CSB RS RW_WRB E_RDB DB RW_WRB/SCL SDI SDO (CSB) VSYNC HSYNC ENABLE DOTCLK (DB) 18/16/9/8 18/16/6 CPU Interface Serial Peripheral Interface System Interface RGB Interface RGB Interface S_PB ID_MIB Figure21: System Interface and RGB Interface

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary SYSTEM INTERFACE S6E63D6 is enabling to set instruction and access to RAM by selecting S_PB, ID_MIB pins and Instruction in the system interface mode. Table44: System Interface mode Pins Registers MDDI _EN S_PB ID_MIB Index Address Command ( CLS ) Command MDT[1] Command MDT[0] Description 0 x 80-system 8-bit 65k bus interface 0 80-system 8-bit 260k bus interface 0 (80 8bit) 1 80-system 8-bit 65k bus interface default & 24h (9/8bit) 1( 80 9bit) x X 80-system 9-bit 260k bus interface 0 80-system 16-bit 65k bus interface 0 1 80-system 16-bit 260k bus interface 0 (80 16bit) (80 mode) Index 23 h (18/16bit) 1( 80 18bit) x X 80-system 18-bit 260k bus interface 0 68-system 8-bit 260k bus interface 0 (68 8bit) 1 68-system 8-bit 65k bus interface default & 24h (9/8bit) 1 (68 9bit) x X 68-system 9-bit 260k bus interface 0 68-system 16-bit 65k bus interface 0 1 68-system 16-bit 260k bus interface 0 (68 16bit) 1 x 68-system 16-bit 260k bus interface (Parallel (68 mode) Index 23 h (18/16bit) 1 (68 18bit) x x 68-system 18-bit 260k bus interface (Serial) ID x x x x Serial peripheral interface (SPI) 1 x x x x x x [NOTE] For details, see the ENTRY MODE (Instruction R03h). We can select system interface mode by pins and instruction, don’t care 8-/16-bit bus system after power on. 1. In case of 8/9-bit bus system. Figure21: 8/9-bit bus system

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 2. In case of 18/16-bit bus system Figure22: 18/16-bit bus system

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 68-SYSTEM 18-BIT BUS INTERFACE Bit Assignment DB 17INPUT DATA Instruction Bit (IB) DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB Figure23: Instruction Format For 18-Bit Interface GRAM DATA R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0RGB Arrangement DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Figure24: RAM Data Write Format For 18-Bit Interface Timing Diagram There are 4 timing conditions for 68-system 18-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. Figure25: Timing Diagram of 68-System 18-Bit bus interface

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 68-SYSTEM 16-BIT BUS INTERFACE Bit Assignment DB 17INPUT DATA Instruction Bit (IB) DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB Figure26: Instruction Format For 16-Bit Interface DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 1GRAM DATA R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0RGB Arrangement Figure27: RAM Data Write Format For 16-Bit Interface Timing Diagram There are 4 timing conditions for 68-system 16-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. Figure28: Timing Diagram of 68-System 16-Bit bus interface

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 68-SYSTEM 9-BIT BUS INTERFACE Bit Assignment 1st Transmission 2nd Transmission DB 8INPUT DATA Instruction Bit (IB) DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Figure29: Instruction Format For 9-Bit Interface DB DB DB DB DB DB DB DB DB 0GRAM DATA R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0RGB Arrangement 1st Transmission DB DB DB DB DB DB DB DB DB 2nd Transmission Figure30: RAM Data Write Format For 9-Bit Interface Timing Diagram There are 4 timing conditions for 68-system 9-bit CPU inte rface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. In this mode, 16-bit instructions and GRAM data are divi ded into two half words and the transfer starts from the upper half word. Note that the upper byte must also be written when the index register is written. Figure31: Timing Diagram of 68-System 9-Bit bus interface

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 68-SYSTEM 8-BIT BUS INTERFACE Bit Assignment DB 8INPUT DATA Instruction Bit (IB) DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB 1st Transmission 2nd Transmission DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Figure32: Instruction Format For 8-Bit Interface DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 10GRAM DATA R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0RGB Arrangement 1st Transmission 2nd Transmission DB DB DB DB DB DB DB DB Figure33: RAM Data Write Format For 8-Bit Interface Timing Diagram There are 4 timing conditions for 68-system 8-bit CPU inte rface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. In this mode, 16-bit instructions and GRAM data are divi ded into two half words and the transfer starts from the upper half word. Note that the upper byte must also be written when the index register is written. Figure34: Timing Diagram of 68-System 8-Bit bus interface

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 80-SYSTEM 18-BIT BUS INTERFACE Bit Assignment DB 17INPUT DATA Instruction Bit (IB) DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB Figure35: Instruction Format For 18-Bit Interface GRAM DATA R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0RGB Arrangement DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Figure36: RAM Data Write Format For 18-Bit Interface Timing Diagram There are 4 timing conditions for 80-system 18-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. Figure37: Timing Diagram of 80-System 18-Bit bus interface

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 80-SYSTEM 16-BIT BUS INTERFACE Bit Assignment DB 17INPUT DATA Instruction Bit (IB) DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB Figure38: Instruction Format For 16-Bit Interface DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 1GRAM DATA R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0RGB Arrangement Figure39: RAM Data Write Format For 16-Bit Interface Timing Diagram There are 4 timing conditions for 80-system 16-bit CPU interface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. Figure40: Timing Diagram of 80-System 16-Bit bus interface

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 80-SYSTEM 9-BIT BUS INTERFACE Bit Assignment 1st Transmission 2nd Transmission DB 8INPUT DATA Instruction Bit (IB) DB DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB Figure41: Instruction Format For 9-Bit Interface DB DB DB DB DB DB DB DB DB 0GRAM DATA R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0RGB Arrangement 1st Transmission DB DB DB DB DB DB DB DB DB 2nd Transmission Figure42: RAM Data Write Format For 9-Bit Interface Timing Diagram There are 4 timing conditions for 80-system 9-bit CPU inte rface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. In this mode, 16-bit instructions and GRAM data are divi ded into two half words and the transfer starts from the upper half word. Note that the upper byte must also be written when the index register is written. Figure43: Timing Diagram of 80-System 9-Bit bus interface

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 80-SYSTEM 8-BIT BUS INTERFACE Bit Assignment DB 8INPUT DATA Instruction Bit (IB) DB DB DB DB DB DB DB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB IB 1st Transmission 2nd Transmission DB DB DB DB DB DB DB DB Figure44: Instruction Format For 8-Bit Interface DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 1GRAM DATA R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0RGB Arrangement 1st Transmission 2nd Transmission Figure45: RAM Data Write Format For 8-Bit Interface Timing Diagram There are 4 timing conditions for 80-system 8-bit CPU inte rface, which are index write timing condition, data write timing condition, data read timing condition and status read timing condition. In this mode, 16-bit instructions and GRAM data are divi ded into two half words and the transfer starts from the upper half word. Note that the upper byte must also be written when the index register is written. Figure46: Timing Diagram of 80-System 8-Bit bus interface

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 68-/80-SYSTEM 8-/9-BIT INTERFACE SYNCHRONIZATION FUNCTION The S6E63D6 supports the transfer synchronization func tion, which resets the upper/lower counter to count upper/lower 8-/9-bit data transfer in the 8-/9-bit bus interface. Noise causing transfer mismatch between the upper and lower bits can be corrected by a reset triggered by writing a “22h” instruction. The next transfer starts from the upper bits. Executing synchronization function periodically can recover any runaway in the display system. Figure47: 8-/9-bit Interface Transfer Synchronization

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary SERIAL PERIPHERAL INTERFACE Setting the S_PB pin to the VDD3 level allows serial periphe ral interface (SPI) transfer, using the chip select line (CS*), serial transfer clock line (SCL), serial input data (SDI), and serial output data (SDO). For a serial interface, the IM0/ID pin function uses an ID pin. If the chip is set up for serial interface, the DB17-0 pins are used only data bus of RGB Interface. The S6E63D6 initiates serial data transfer by transferring the start byte at the falling edge of CSB input. It ends serial data transfer at the rising edge of CSB input. The S6E63D6 is selected when the 6-bit chip address in the start byte matches the 6-bit device identification code that is assigned to the S6E63D6. Wh en selected, the S6E63D6 receives the subsequent data string. The least significant bit (LSB) of the identification code can be dete rmined by the ID pin. The five upper bits must be 01110. Two different chip addresses must be assigned to a single S6E63D6 because the seventh bit of the start byte is used as a register select bit (RS). That is, when RS = 0, data can be written to the index register or status can be read, and when RS = 1, an instruction can be issued or data can be written to or read from RAM. Read or write operation is selected according to the eighth bit of the start byte (R/W bit). The data is received when the R/W bit is 0, and is transmitted when the R/W bit is 1. After receiving the start byte, the S6E63D6 receives or transmits the subsequent data byte-by-byte. The data is transferred with the MSB first. All S6E63D6 instructions are 16 bits. Two bytes are received with the MSB first (DB17 to DB0), then the instructions are internally executed. After the start byte has been received, the first byte is fetched as the upper eight bits of the instruction and the second byte is fetched as the lower eight bits of the instruction. Four bytes of RAM read data after the start byte are invalid. The S6E63D6 starts to read correct RAM data from the fifth byte. Table45: Start Byte Format Transfer bit S 1 2 3 4 5 6 7 8 Device ID code RS R/W Start byte format Transfer start 0 1 1 1 0 ID NOTE: ID bit is selected by the ID_MIB pin. Table46: RS and R/W Bit Function RS R/W Function 0 0 Set index register 0 1 Read status Bit Assignment Figure48: Bit Assignment of Instructions on SPI

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Timing Diagram Figure49: Basic Timing Diagram of Register Data Transfer through SPI Figure50: Timing Diagram of Consecutive Register Data-Write through SPI Figure51: Timing Diagram of Register Read through SPI

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary INDEX AND PARAMETER RECOGNITION If more parameter command is being sent, exceed parameters are ignored. Figure52: Index and parameter recognition with 8-/9-bit interface Figure53: Index and parameter recognition with 18-/16-bit interface

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary EXTERNAL DISPLAY INTERFACE The following interfaces are available as external display interface. It is determined by bit setting of RIM1-0. RAM accesses can be performed via the RGB interface. Table47: RIM Bits RIM1 RIM0 RGB Interface DB Pin 0 0 18-bit RGB interface DB17 to 0 0 1 16-bit RGB interface DB17 to10, 8 to 1 1 0 6-bit RGB interface DB8 to3 1 1 Setting disabled ENABLE SIGNAL The relationship between EPL and ENABLE signals is shown below. When ENABLE is not active, the address is not updates. When ENABLE is active, the address is updated. Table48: Relationship between EPL and ENABLE EPL ENABLE RAM WRITE RAM ADDRESS 0 0 Valid Updated 0 1 Invalid Hold 1 0 Invalid Hold 1 1 Valid Update

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 18-Bit RGB interface Bit Assignment Figure54: Bit Assignment of GRAM Data on 18bit RGB Interface 16-Bit RGB interface Bit Assignment Figure55: Bit Assignment of GRAM Data on 16bit RGB Interface Timing Diagram Back Porch

1 Frame

= 1H >= 256CLK 1CLK A B VSYNC HSYNC ENABLE DB[17:0] DOTCLK HSYNC DOTCLK ENABLE DB[17:0] Figure56: Timing Diagram of 18/16bit RGB Interface [NOTE] 1. 1 HSYNC Period must be >= 256 DOTCLK

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 6-Bit RGB interface In order to transfer data on 6bit RGB Interface there should be three transfers. Bit Assignment Figure57: Bit Assignment of GRAM Data on 6bit RGB Interface Timing Diagram Figure58: Timing Diagram of 6bit RGB Interface [NOTE] 1. Three clocks are regarded as one clock for transfer when data is transferred in 6-bit interface. VSYNC, HSYNC, ENABLE, DOTCLK, and DB[8:3] should be transferred in units of three clocks. 2. 1 HSYNC Period must be >= 256 * 3 DOTCLK

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Transfer Synchronization Figure59: Transfer Synchronization Function in 6-bit RGB Interface mode [NOTE] The figure shows Transfer Synchronization function for 6bit RGB Interface. S6E63D6 has a transfer counter to count 1st, 2nd and 3rd data transfer of 6bit RGB Interface. The transfer counter is reset on the falling edge of HSYNC and enters the 1st data transmission state. Transfer mismatch can be corrected at every new transfer restarts with HSYNC signal. In this method, when data is consecutively transferred in such a way as displaying motion pictures, the effect of transfer mismatch will be reduced and recovered by normal operation. [NOTE] The internal display is operated in units of three DOTCLKs. When DOTCLK is not input in units of pixels, clock mismatch occurs and the frame, which is operated, and the next frame are not displayed correctly. Time chart for RGB interface is shown below. (In case of EPL = 0)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary INTERFACE SWAPPING FOR MEMORY ACCESS DISPLAY MODES AND GRAM ACCESS CONTROL Display mode and RAM Access is controlled as shown below. For each display status, display mode control and RAM Access control are combined properly. Table49: DISPLAY MODE & RAM ACCESS CONTROL Display Status GRAM Access (RM) Display Mode (DM) Internal Clock Operation (Still Picture Display) System Interface (RM = 0) Internal Clock Operation (DM = 0) RGB I/F (Displaying Motion Picture) RGB Interface (RM = 1) External Clock Operation (DM = 1) MDDI interface (Displaying motion Pictures) System interface (RM=0) MDDI interface (D=0) [NOTE 1] Only system interface can set Instruction register. [NOTE 2] When the RGB Interface is being operated do not change the RGB Interface mode (RIM). Internal Clock Operation mode with System Interface Every operation in Internal Clock Operation mode is done in synchronization with the internal clock which is generated by internal OSC. The signals input through RGB interface are all meaningless. Access to internal GRAM is done via system interface. External Clock Operation mode with RGB Interface In External Clock Operation mode, frame sync signal (VSYNC), line sync signal (HSYNC) and DOTCLK are used for display operation. Display data is transferred in the unit of pixel through DB bus and saved to GRAM.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary USAGE ON EXTERNAL DISPLAY INTERFACE 1. When external display interface is in use, the following functions are not available. Table50: External Display Interface and Internal Display Operation Function External Display Interface Internal Display Operation Partial Display Not Available Available Scroll Function Not Available Available Rotation Not Available Available Mirroring Not Available Available Window Function Not Available Available 2. VSYNC, HSYNC, and DOTCLK signals should be supplied during display operation via RGB interface. 3. RGB data are transferred for three clock cycles in 6-bi t RGB interface. Data transf erred, therefore, should be transferred in units of RGB. 4. Interface signals, VSYNC, HSYNC, DOTCLK, ENABLE and DB17-0 should be set in units of RGB (pixels) to match RGB transfer. 5. Transitions between internal operation mode and exter nal display interface should follow the mode transition sequence shown below. 6. During the period between the completion of displaying one frame data and the next VSYNC signal, the display will remain front porch period.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary MDDI (MOBILE DISPLAY DIGITAL INTERFACE) INTRODUCTION OF MDDI The S6E63D6 supports MDDI. The MDDI is a differential & serial interface with high speed. Both command and image data transfer can be achieved with MDDI. MDDI host & client are linked with Data and STB line. Through Data line, command or image data is transferred from MDDI host to MDDI client, and vice versa. Data is transferred by packet unit. Through STB line, strobe signal is transfer red. When the link is in “FORWARD direction”, data is transferred from host to client; in “REVERSE direction”, client transfer reverse data to MDDI host. DATA+ DATA- MDDI HOST DATA+ DATA- STB+ STB- STB+ STB- Host Pwr Host GND MDDI CLIENT Forward Direction Reverse Direction Figure60: Physical connection of MDDI host and client DATA-STB ENCODING Data is encoded using a DATA-STB method. DATA is carried over a bi-directional differential cable, while STB is carried over a unidirectional differential cable driven onl y by the host. Figure below illustrates how the data sequence “1110001011” is transmitted using DATA-STB encoding. Figure61: Data-STB encoding The Following figure shows a sample circuit to generate DATA and STB from input data, and then recover the input data from DATA and STB.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary Figure62: Data / STB Generation & Recovery circuit MDDI DATA / STB The Data (MDP/MDN) and STB(MSP/MSN) signals are alwa ys operated in a differential mode to maximize noise immunity. Each differential pair is parallel-terminated with the characteristic impedance of the cable. All parallel-terminations are in the client device. Figure below illustrates the configuration of the drivers, receivers, and terminations. The driver of each signal pair has a diffe rential current output. While receiving MDDI packets the MDDI_DATA and MDDI_STB pairs use a conventional different ial receiver with a differential voltage threshold of zero volts. In the hibernation state the driver outputs are disabled and t he parallel termination resistors pull the differential voltage on each signal pair to zero volts. During hibernation a special receiver on the MDDI_DATA pairs has an offset input differential voltage threshold of posit ive 125 mV, which causes the hibernation line receiver to interpret the un-driven signal pair as logic-zero level. STB(host) Data (host to client) Enable(host) Data (client to host) wake-up (client to host) HOST VT = 0 VT = 125mV MDDI STB+ MDDI STB- MDDI DATA+ MDDI DATA- CLIENT STB(client) VT = 0 VT = 0 Rterm Rterm VT = 125mV Enable(client) Data (host to client) Data (client to host) wake-up (host to client) Figure63: Differential connection between host and client

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary HIBERNATION / WAKE-UP S6E63D6 support hibernation mode for reducing interface power consumption. The MDDI link can enter the hibernation state quickly and wake up from hibernation quickly. This allows the system to force the MDDI link into hibernation frequently to reduce power consumption. In hibernation mode, hi-speed transceivers and receivers are disabled and low-speed & low-power receivers are enabled to detect wake-up sequence. STB(host) Data (host to client) Enable(host) Data (client to host) wake-up (client to host) HOST OFF OFF OFF VT = 0 VT = 125mV MDDI STB+ MDDI STB- MDDI DATA+ MDDI DATA- CLIENT STB(client) OFF VT = 0 OFF VT = 0 Rterm Rterm VT = 125mV Enable(client) Data (host to client) Data (client to host) wake-up (host to client) ON ON OFF Figure64: MDDI Transceiver / Receiver state in hibernation When the link wakes up from hibernation the host and client exchange a sequence of pulses. These pulses can be detect using low-speed, low-power receivers that consume only a fraction of the current of the differential receivers required to receive the signals at the maximum link operating speed. Both the client and the host can wake up the link, so 2-types of wake-up are supported in S6E63D6: Host-initiated link wakeup and Client-initiated link wakeup.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 100 MDDI LINK WAKE-UP PROCEDURE Rules for Entering the Hibernation State : z The host sends 64 MDDI_Stb cycles after the CRC of the Link Shutdown Packet. Also after this CRC the host shall drive MDDI_Data0 to a logic-zero level and disable the MDDI_Data0 output of the host in the range of after the rising edge of the 16 th to before the rising edge of the 48 th MDDI_Stb cycles (including output disable propagation delays). z The host shall finish sending the 64 MDDI_Stb cycles after the CRC of the Link Shutdown packet before it initiates the wake-up sequence. z The client shall wait until after the rigins edge of the 48 th MDDI_Stb cycle after the CRC of the Link Shutdown Packet or later before it drives MDDI_Data0 to a logic-one level to attempt to wake-up the host. z The client shall place its high-speed receivers for MDDI_Data0 and MDDI_Stb into hibernation any time after the rising edge of the 48 th MDDI_Stb cycle after the CRC of the Link Shutdown Packet. It is recommended that the client place its high-speed MDDI_Data0 and MDDI_Stb receivers into hiber nation before the rising edge of the 64th MDDI_Stb cycle after the CRC of the Link Shutdown Packet. Rules for Wake-up from the Hibernation State : z When the client needs service from the host it generate s a request pulse by driving MDDI_Data0 to a logic-one level for 70 to 1000μsec while MDDI_Stb is inactive and keeps M DDI_Data0 driven to a logic-one level for 70 MDDI_Stb cycles(range of 60 to 80) after MDDI_Stb becomes active. Then the client disables the MDDI_Data0 driver by placing it into a high-impedance state. z If MDDI_Stb is active during hibernation(which is unlikely, but allowed per the spec) then the client may only drive MDDI_Data0 to a logic one level for 70 MDDI_Stb cycle s (range of 60 to 80). This action causes the host to restart data traffic on the forward link and to poll the client for its status. z The host shall detect the presence of the request pulse fr om the client (using the low-power differential receiver with a +125mV offset) and begin the startup sequence by first driving MDDI_Stb to a logic-zero level and MDDI_Data0 to a logic-high level for at least 200nsec, and then while toggling MDDI_Stb it shall continue to drive MDDI_Data0 to a logic-one level fo r 150 MDDI_Stb cycles (range of 140 to 160) and to logic-zero for 50 MDDI_Stb cycles. The client shall not send a service request pulse if it detects MDDI_Data0 at a logic-one level for more than 80 MDDI_Stb cycles. After the client has detected MDDI_Data0 at a logic-one level for 60 to80 MDDI_Stb cycles it shall begin to search for the interv al where drives MDDI_Data0 to a logic-zero level for 50 MDDI_Stb cycles then the host starts sending packets on the link. The first packet sent shall be a Sub-frame Header Packet. The client begins to look for the Sub-fram e header Packet after MDDI_Data0 is at a logic-zero level for 40 MDDI_Stb cycles of the 50 cycle interval. z The host may initiate the wake-up by first enabling MDDI_S tb and simultaneously drive it to a logic-zero level. MDDI_Stb shall not be driven to a logic-one level until pulses are output as described below. After MDDI_Stb reaches a valid logic-zero level the host shall enable MDDI_Data0 and simultaneously drive it to a logic-one level. MDDI_Data0 shall not be driven to a logic-zero level duri ng the wake-up process until the interval where it is

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 101 driven to a logic-zero level for an interval of 50 MDDI_Stb pulses as described below. The host shall wait at least 200 nsec after MDDI_Data0 reaches a valid logic-one level before driving pulses on MDDI_Stb. This timing relationship shall always occur while considering the worst-case output enable delays. This guarantees that the client has sufficient time to fully enable its MDDI_Stb receiver after being woken up by a logic-one level on MDDI_Data0 that was driven by the host. Figure65: Process from entering Hibernation To exiting Hibernation

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 102 1) Host-initiated Link Wake-up Procedure The simple case of a host-initiated wake-up is described below without contention from the client trying to wake up at the same time. The following sequence of events is illustrated in the following figure. Figure66: Host-initiated link wakeup sequence The Detailed descriptions for labeled events are as follows: A. The host sends a Link Shutdown Packet to inform t he client that the link will transition to the low-power hibernation state. B. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for 64 cycles to allow processing in the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in the client device. Also during this interval the host initially sets MDDI_Data0 to a logic-zero level, and then disables the MDDI_Data0 output in the range of 16 to 48 MDDI_Stb cycles (including output disable propagation delays) after the CRC. It may be desirable for the client to place its high-speed receivers for MDDI_Data0 and MDDI_Stb into a low power state any time after 48 MDDI_Stb cycles after the CRC and before point C. C. The host enters the low-power hi bernation state by disabling the MD DI_Data0 and MDDI_Stb drivers and by placing the host controller into a low-power hibernation state. It is also allowable for MDDI_Stb to be driven to logic-zero level or to continue toggling during hibernation. The client is also in the low-power hibernation state. D. After a while, the host begins the link restart se quence by enabling the MDDI_D ata0 and MDDI_Stb driver outputs. The host drives MDDI_Data0 to a logic-one level and MDDI_Stb to logic-zero level for at least the time it takes for the drivers to fully enable their outputs. The host shall wait at least 200 nsec after MDDI_Data0 reaches a valid l ogic-one level and MDDI_Stb reaches a valid logic-zero level before driving pulses on MDDI_Stb. This gives the client sufficient time to prepare to receive high-speed pulses on MDDI_Stb. The client first detects t he wake-up pulse using a low-power differential receiver having a +125mV input offset voltage. E. The host drivers are fully enabled and MDDI_Data0 is being driven to a logic-one level. The host begins to toggle MDDI_Stb in a manner consist ent with having a logic-zero level on MDDI_Data0 for a duration of 150 MDDI_Stb cycles. F. The host drives MDDI_Data0 to logic-zero level for 50 MDDI_Stb cycles. The client begins to look for the Sub-frame Header Packet after MDDI_Data0 is at logic-zero level for 40 MDDI_Stb cycles. G. The host begins to transmit data on the forward link by sending a Sub-frame Header Packet. Beginning at point G the MDDI host gen erates MDDI_Stb based on the logic level on MDDI_Data0 so that proper data-strobe encoding commences from point G.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 103 Figure67: Host-initiated link wakeup sequence 2) Client-initiated Link Wake-up Procedure An example of a typical client-initiated service request event with no contention is illustrated in the following figure. Figure68: Client-initiated link wake-up sequence The Detailed descriptions for labeled events are as follows: A. The host sends a Link Shutdown Packet to inform t he client that the link will transition to the low-power hibernation state. B. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for 64 cycles to allow processing in the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in the client device. Also during this interval the host initially sets MDDI_Data0 to a logic-zero level, and then disables the MDDI_Data0 output in the range of 16 to 48 MDDI_Stb cycles (including output disable propagation delays) after the CRC. It may be desirable for the client to place its high-speed receivers for MDDI_Data0 and MDDI_Stb into a low power state any time after 48 MDDI_Stb cycles after the CRC and before point C. C. The host enters the low-power hibernation state by disabling its MDDI_Data0 and MDDI_Stb driver outputs. It is also allowable for MDDI_Stb to be driven to logic-zero level or to continue toggling during hibernation. The client is also in the low-power hibernation state. D. After a while, the client begins the link restart sequence by enabling the MDDI_Stb receiver and also enabling an

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 104 offset in its MDDI_Stb receiver to guarantee the state of the received version of MDDI_Stb is a logic-zero level in the client before the host enables its MDDI_Stb driver. The client will need to enable the offset in MDDI_Stb immediately before enabling its MDDI_Stb receiver to ensure that the MDDI_Stb receiver in the client is always re ceiving a valid differential signal and to prevent erroneous received signals from propagating into the client. After that, the client enables its MDDI_Data0 driver while driving MDDI_Data0 to a logic-one level. It is allowed for MDDI_Data0 and MDDI_Stb to be enabled simultaneously if the time to enable the offset and enable the standard MDDI_Stb differential receiver is less than 200 nsec. E. Within 1 msec the host recognizes the service reques t pulse, and the host begins the link restart sequence by enabling the MDDI_Data0 and MDDI_Stb driver outputs. The host drives MDDI_Data0 to a logic-one level and MDDI_Stb to a logic-zero level for at least the time it takes for the drivers to fully enable their outputs. The host shall wait at least 200 nsec after MDDI_Data0 reaches a valid logic-one level and MDDI_Stb reaches a valid fully-driven logic-zero level before driving pulses on MDDI_Stb. This gives the client sufficient time to prepare to receive high-speed pulses on MDDI_Stb. F. The host begins outputting pulses on MDDI_Stb and sha ll keep MDDI_Data0 at a logic-one level for a total duration of 150 MDDI_Stb pulses throu gh point H. The host generates MDDI _Stb in a manner consistent with sending a logic-zero level on MDDI_Data0. When the client recognizes the first pulse on MDDI_Stb it shall disable the offset in its MDDI_Stb receiver. G. The client continues to drive MDDI_Data0 to a logic-one level for 70 MDDI_Stb pulses, and the client disables its MDDI_Data0 driver at point G. The host continues to drive MDDI_Dat a0 to a logic-one level for duration of 80 additional MDDI_Stb pulses, and at point H drives MDDI_Data0 to logic-zero level. H. The host drives MDDI_Data0 to logic-zero level for 50 MDDI_Stb cycles. The client begins to look for the Sub-frame Header Packet after MDDI_Data0 is at logic-zero level for 40 MDDI_Stb cycles. I. After asserting MDDI_Data0 to logic-zero level and dr iving MDDI_Stb for duration of 50 MDDI_Stb pulses the host begins to transmit data on the forward link at point I by sending a Sub-frame Header Packet. The client begins to look for the Sub-frame Header Packet after MDDI_Data0 is at logic-zero level for 40 MDDI_Stb cycles.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 105 Figure69: Client-initiated link wake-up sequence S6E63D6 supports 2-types of client -initiated link wake-up: VSYNC based Link Wake-up & GPIO based Link Wake-up. As client-initiated wake-up action is executed in hibernation state only, register setting for each wake-up have to be set before link shut-down. VSYNC Based Link Wake-up In display-ON state, when the IC finishes displaying all internal GRAM data, data request must be transferred to MDDI host for new video data. As MDDI link is usually in hibernation for re ducing interface power consumption, MDDI link wake-up must be done before internal GRAM updat e. In that case, client initiated link wake-up can be used as data request.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 106 When VSYNC based link wake-u p register (50h: VWAKE_EN) is set, clie nt initiated wake-up is executed in synchronization with the vertical-sync signal which generated in S6E63D6. Using VSYNC based link wake-up, tearing-less display can be accomplished if interface speed and wake-up time is well known. The following figure shows detailed timing for VSYNC based link wake-up. VWAKE_EN link_active frame_update client_wakeup AB C D E F SYNC STATE HIBERNATION STATE WAKE-UP STATE SYNC STATE Figure70: VSYNC based link wake-up procedure The Detailed descriptions for labeled events are as follows: A. MDDI host writes to the VSYNC based link wakeup register to enable a wake-up based on internal vertical-sync signal. B. link_active goes low when the host puts in the link into hibernation after no more data needs to be sent to the S6E63D6. C. frame_update, the internal vertical-sync signal goes high indicating that update pointer has wrapped around and is now reading from the beginning of the frame buffer. Link wake-up point can be set using WKF and WKL (51h) registers. WKF specifies the number of frame before wake-up; WKL specifies the number of lines before wake-up. D. client_wakeup input to the MDDI client goes high to start the client initiated link wake-up. E. link_active goes high after the host brings the link out of hibernation. F. After link wake-up, client_wakeup signal and the VWAKE_EN register are cleared automatically. GPIO Based Link Wake-up In VSYNC-based link wake-up, wake-up enable register setting prior to link shut-down. GPIO based Link wake-up is enabled by interrupt from outside of the IC. For GPIO based link wake-up, GPIO interrupt enable and GPIO PAD mode (to input mode) setting must be set. Once S6E63D6 receive interrupt, internal GPIO base link wake-up flag set to high, and the following procedure is similar to that of VSYNC based link wake-up. The following figure shows detailed timing for GPIO based link wake-up.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 107 GPIO_EN link_active frame_update client_wakeup AB D E F G SYNC STATE HIBERNATION STATE WAKE-UP STATE SYNC STATE GPIO(input)* GPIO_INT* C H Figure71: GPIO based link wake-up procedure The Detailed descriptions for labeled events are as follows: A. Host sets the GPIO interrupt enable register (69h : GPIO_EN) for a particular GPIO through register access packet. B. Link goes into hibernation (and link_active)goes low) when the host has no more data to send to the IC. C. GPIO input goes high, and the GPIO interrupt (GPIO_INT) is latched. D. Frame_update signal goes high indicating that the di splay has wrapped around. Link wake-up point can be set using WKF and WKL (51h) registers. E. Client_wakeup input to the MDDI client goes high to start the client initiated link wake-up. F. Link_active goes high after the host brings the link out of hibernation. G. After link wake-up, client_wakeup signal is reset to low. H. MDDI host clears the interrupt by writing to the interrupt clear register with the bit set for that particular interrupt (GPCLR: 68h). Between point G and H the host will have read the GPIO_INT values to see what interrupts are active.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 108 GPIO CONTROL S6E63D6 offers 10(maximum) GPIO that can be used as input or output independently. Some application or device on the upper clamshell needs several control signals which are supplied by base band modem or application processor directly. If number of applic ation on the upper clamshell increases, also control signals increase, causing the interface more costly. In S6E63D6, GPIO can be the solution for that problem. User may control the 10 GPIOs as input or output by use of simple register setting. So additional connection betw een base band modem / AP (application processor) and components on upper clamshell are not needed. The following table shows several set of register for GPIO. Register width Description Reset value Write For GPIO output mode: output GPIO register(66h) value to GPIO PAD GPIO (66h) [9:0] Read GPIO PAD status 10’h000 Write GPIO PAD input/output mode control : (0 : input / 1 : output) GPIO_CON (67h) [9:0] Read GPIO_CON (67h) register value 10’h000 Write For GPIO input mode: clear spec ified GPIO interrupt (set by GPIO PAD input). GPCLR (68h) [9:0] Read GPIO interrupt state (set by GPIO PAD input). 10’h000 Write For GPIO input mode: enable specified GPIO interrupt GPIO_EN (69h) [9:0] Read GPIO_EN (69h) register value. 10’h000 Write For GPIO input mode: GPIO interrupt polarity setting GPPOL (6Ah) [9:0] Read GPPOL (6Ah) register value. 10’h3FF In GPIO output mode, the IC output GPIO (66h) register value to the defined PAD. Set GPIO_CON register as output mode before use GPIO output. 10 different GPIO output can be controlled simultaneously using 1-register access packet (66h register access) so that minimum access time for each GPIO output will be 1-register access time. GPIO input mode can only be used as client-initiated link wake-up. For more information, refer to GPIO based link wake-up section.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 109 3) Host-initiated Wake-up from Hibernation with Connection from client This is actually a host-initiated wake-up, but we have included the case where the client also wants to wake up the link with the latest possible request. The labeled events are : A. The host sends a Link Shutdown Packet to inform t he client that the link will transition to the low-power hibernation state. B. Following the CRC of the Link Shutdown Packet the host toggles MDDI_Stb for 64 cycles to allow processing in the client to finish before it stops MDDI_Stb from toggling which stops the recovered clock in the client device. Also during this interval the host disables the MDDI_Data0 output in the range of 16 to 48 MDDI_Stb cycles(including output disable propagatio n delays) after the CRC. It may be desirable for the client to place its high-speed receivers for MDDI_Data0 and MDDI_Stb into a low power state any time after 48 MDDI_Stb cycles after the CRC and before point C. C. The host enters the low-power hibe rnation state by disabling its MDDI_Data0 and MDDI_Stb driver outputs. It is also allowable for MDDI_Stb to be driven to a logic-zero level or to continue toggling during hibernation. The client is also in the low-power hibernation state. D. After a while, the host begins t he link restart sequence by enabling the MDDI_Data0 and MDDI_Stb driver outputs. The host drives MDDI_Data0 to a logic-one level and MDDI_Stb to a logic-zero level for at least the time it takes for the drivers to fully enable their outputs. The host shall wait at least 200 nsec after MDDI_Data0 reaches a valid logic-one level and MDDI_Stb reaches a valid logic-zero level before driving pulses on MDDI_Stb. This gives the client sufficient time to prepare to receive high-speed pulses on MDDI_Stb. E. The host drivers are fully enabled and MDDI_Data0 is being driven to a logic-one level. The host begins to toggle MDDI_Stb in a manner consistent with having a logic-zero level on MDDI_Data0 for a duration of 150 MDDI_Stb cycles. F. At up to 70 MDDI_Stb cycles after point E the cli ent has not yet recognized t hat the host is driving MDDI_Data0 to a logic-one level so the client also drives MDDI_Data0 to a logi c-one level. This occurs because the client has a need to request service fr om the host and does not recognize that the host has already begun the link restart sequence. G. The client ceases to drive MDDI _Data0, and places its driver into a high-impedance state by disabling its output. The host continues to drive MDDI_Data0 to a logic-one level for 80 additional MDDI_Stb cycles. H. The host drives MDDI_Data0 to a logic-zero level fo r 50 MDDI_Stb cycles. The client begins to look for the Sub-frame Header Packet after MDDI_Data0 is at a logic-zero level for 40 MDDI_Stb cycles. I. The host begins to transmit data on the forward link by sending a Sub-frame Header Packet. Beginning at point I the MDDI host generates MDDI_Stb based on the logic leve l on MDDI_Data0 so that proper data-strobe encoding commences from point I.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 110 Figure72: Host-initiated Wake-up process from Hibernation with Connection from client

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 111 MDDI PACKET MDDI transfer data by packet format. MDDI host can make many packets and transfer them. In S6E63D6, several packets format is supported. Most pa ckets are transferred from MDDI host to client (forward direction); but reverse encapsulation packet is transferred from MDDI client to host (reverse direction). A number of packets, started by sub-frame header packet, construct 1 sub frame. Figure73: MDDI packet structure Refer to MDDI packet structure, sub- frame header packet is placed in front of a sub-frame, and some sub-frame construct media-frame together. The following table describes 9 types of packet which is supported in S6E63D6. PACKET FUNCTION DIRECTION Sub-frame header packet Header of each sub frame Forward Register access packet Register setting Forward Video stream packet Video data transfer Forward Filler packet Fill empty packet space Forward Reverse link encapsulation packet Reverse data packet Reverse Round-trip delay measurement packet Host->client->host delay check Forward/Reverse Client capability packet Capability of client check Reverse Clinet request and status packet Information about client status Reverse Link shutdown packet End of frame Forward Sub-frame header packet Figure74: Sub-frame header packet structure

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 112 Register access packet Figure75: Register access packet structure Video Stream packet Figure76: Video stream packet structure

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 113 Filler packet Figure77: Filler packet structure Link shutdown packet Figure78: Link shutdown packet structure : fixed value For More information about MDDI packet, please refer to VESA MDDI spec.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 114 MDDI OPERATING STATE In MDDI, six operation modes are available. The following table describes six modes. STATE OSC Step-up Circuit Internal Logic status MDDI I/O Wake-up by SLEEP ON Disabled Display OFF MDDI Link hibernation Hibernation driver ON Host – Initiated WAIT ON Disabled Display OFF MDDI Link in SYNC standard driver ON - Normal ON Enabled Display ON MDDI Link in SYNC standard driver ON - NAP ON Disabled Display OFF MDDI Link in SYNC standard driver ON - IDLE ON Enabled Display ON MDDI Link hibernation Hibernation driver ON Host – Initiated Client – Initiated (Vsync, GPIO) STOP OFF Disabled Display OFF MDDI Link OFF Driver All OFF RESET SLEEP: Initial status when external power is connected to the IC. In this state, internal oscillator is operating, and MDDI link is in hibernation state. As no command or signal is applied to the IC except RESET input, internal logic or step-up circuit is OFF. WAIT: After the wake-up sequence, the IC is in WAIT state. MDDI link is in SYNC, and internal logic or step-up is still OFF because no other register access or video stream packet is transferred to the IC. NORMAL: MDDI link, step-up circuit, and internal logic ci rcuit is ON. Register access or Video data transfer is available in NORMAL state. IDLE: When no more video data update is needed, MDDI lin k is in hibernation so that interface power can be reduced. Internal step-up & logic circuits are still operating. MDDI link wa keup will be accomplished when vsync wakeup register is set before hibernation or GPIO interrupt is set. NAP: This state is set by register access. Step-up and Internal logic is OFF, but MDDI link is ON. MDDI link have to be in SYNC because the IC must receive commands for power save or normal operation STOP: STOP state is set by register access (R10h). In this state, MDDI link, internal oscillator, step-up, and logic circuit are all OFF. To release STOP state, input reset signal. After reset, status is SLEEP state.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 115 System power ON SLEEP System Reset input - OSC : OSC ON - Step-up : Disabled - MDDI link : Hibernation - Logic : Display OFF MDDI link synchronization procedure - OSC : OSC ON - Step-up : Disabled - MDDI link : in SYNC - Logic : Display OFF - OSC : OSC ON - Step-up : Enabled - MDDI link : in SYNC - Logic : Display ON 1) Power setting using register packet 2) Step-up enable sequence using register packet 3) Frame buffer access using video packet 4) Display ON sequence using register packet WAIT POWER ON NORMAL IDLE - STOP state setting using register packet (both standard & offset receiver disabled) - OSC: OSC ON - Step-up: Enabled - MDDI link:Hibernation - Logic: Display ON MDDI Link wak e-up! - VSYNC wakeup - GPIO wakeup - Host initiated wakeup NAP - OSC: OSC ON - Step-up: Disabled - MDDI link: in SYNC - Logic: Display OFF STOP - OSC: OSC OFF - Step-up: Disabled - MDDI link:Link disabled - Logic: Display OFF Only RESET signal is admitted for wake-up from STOP state ! 1 32 NAP state set sequence 1) Display OFF sequence using register packet 2) NAP state setting(SLP=1) using register packet IDLE state (when frame buffer update not needed) 1) Vsync wakeup enable register setting (optional) 2) Link shut-down using link shut-down packet (MDDI link is in hibernation state) NAP state release sequence 1) NAP state register disable 2) Step-up enable sequence 3) Frame buffer update (optional) 4) Display ON sequence Figure79: Operating state in MDDI mode

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 116 TEARING-LESS DISPLAY In S6E63D6, the matching between data write timing and wr itten data display timing is important. If timing is mismatched, tearing effect can occur. To avoid display tearing effect, two possible ways are suggested. First case is that data write is slower than speed of disp laying written data. In this case, data write speed is not critical, but current consumption in interface will be increased because data transfer time is long. Data write time is selected widely (?) in this case. Other case is that data write is faster than speed of displaying written data. In this case, data update speed is very high so that transfer time is short. So current consumpti on in interface can be minimiz ed, but it requires fast data transfer. The most important thing is to avoid data scan conflicts with data update. The following figures describe some examples to avoid display tearing phenomenon. . 1. Display speed is faster than data write. Figure80: Tearing-less display: display speed is faster than data write 2. Display speed is slower than data write. Figure81: Tearing-less display: data write speed is faster than display

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 117 SUB PANEL CONTROL S6E63D6 support sub panel control function which controls sub panel driver IC using 80-mode protocol (CSB, RS, WRB & DB). When MDDI host (Base band modem) sends several packets to S6E63D6, if the packet is for sub panel, the IC converts the packet to 80-mode protocol & sends them to sub panel driver IC. So separated line for sub panel control are not needed. After all, S6E63D6 enables the sub panel driver IC which doesn’t support MDDI to be applied to the system. S6E63D6 supports only 80-mode 18/16 bit format for sub panel control. LCD driver IC TFT-LCD Module (SUB display) LCD driver IC Sub Panel (Normal LDI) MSM (Baseband Modem) MDDI HOST MDDI TRX/ RX 80 mode Parallel I/F MDDI Main Panel (MDDl-Supported LDI) OLED Module (MAIN display) Figure82: Schematic diagram of sub panel control function

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 118 MAIN / SUB PANEL SELECTION Using 7Ah register (7Ah address can be changed using SUB_SEL register), main / sub panel data path can be selected. When S6E63D6 receives register access packet (Initially 7Ah index) from MDDI host, it decodes the packet and checks the last bit of the register data field is ‘1’ or ‘0’. If the last bit is ‘0’, the following register access packet or video stream packet is transferred to the sub panel control signal generation block. Sub panel selection address (Initially 7Ah) can be changed using SUB_SEL register. Do not change the SUB_SEL value to previously occupied address. Register Address = SUB_SEL Register Data = 0000h Register Data = 0001h MAIN panel Selection Procedure Command Transfer (Register Access packet) SUB panel Selection Procedure Video Data Transfer (Video Stream packet) Register Address = SUB_SEL Command / Data transfer to Sub Panel driver IC (80-mode protocol) Note: Initial value of SUB_SEL = 7Ah Figure83: Main / Sub panel selection procedure When video data is transferred to the sub panel driver IC via S6E63D6, additional GRAM access command (normally 22h) is automatically generated in S6E63D6.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 119 SUB PANEL CONTROL TIMING 1. TFT type sub panel timing

1.1 Register data transfer timing

If sub panel is selected, and sub panel type is TFT, register setting is executed like below figure. Register data is transferred through S_DB[17:10] & S_DB[8:1] in 18/16 bit type. If 9/8 bit type is used, data is transferred thorough S_DB[17:10]. Refer to sub panel control(15h index) section. C R C S_DB[17:0] S_CSB S_RS S_WRB 0000Eh (index 07h) 00C1Eh (030Fh 16bit data) index write parameter write MDDI Data Stream Register Address (0007h) Header C R C Register Data (030Fh)

1 Register Access Packet

Figure84: 18/16 bit type register access data transfer In 9/8 bit mode, S_DB[17:10] is used. In this mode, data is transferred at two times. First transfer is MSB 8bit and second transfer is LSB 8bit. C R C S_DB[17:10] S_CSB S_RS S_WRB index write parameter write MDDI Data Stream Register Address (0007h) Header C R C Register Data (030Fh) (MSB 8bit) 07h (LSB 8bit) 03h (MSB 8bit) 0Fh (LSB 8bit) Figure85: 9/8 bit type register access data transfer

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 120 This figure shows register setting in 18/16 bit & 68 mode. In 68 mode, S_WRB must be connected to E_RDB of sub panel module. RW_WRB of sub panel module must be tied to VSS. Because S6E63D6 only writes data to sub panel module. C R C S_DB[17:0] S_CSB S_RS S_WRB 0000Eh (index 07h) 00C1Eh (030Fh 16bit data) index write parameter write MDDI Data Stream Register Address (0007h) Header C R C Register Data (030Fh) Figure86: 68 mode 18 bit register data transfer

1.2 Video data transfer timing

In TFT type sub panel, STN_EN register in 15h index is “0”, and if user wants to use 68-mode interface protocol, then MPU_MODE is set to “1”. 18/16/9/8 mode is selected as setting SUB_IM register. Refer to 15h index description. This figure shows 80 mode 18 bit Video data transfer. Header 00044h GRAM write enable (index 22h) GRAM Write Enable (22h index) pixel write C R C Pixel data #1 (01ABCh) C R C

1 Video Stream Packet(18-bpp)

Pixel data #2 (100FFh) Pixel data #4 (000FFh) Pixel data #3 (0FF00h) Pixel data #5 (00001h) Pixel data #1 01ABCh Pixel data #2 100FFh Pixel data #3 0FF00h Pixel data #4 000FFh Pixel data #5 00001h pixel write pixel write pixel write pixel write DB[17:0] (data output to sub LDI) S_CSB (chip select for sub LDI) S_RS (command / data select) S_WRB (write enable for sub LDI) MDDI Data Stream Figure87: 80 mode 18 bit video data transfer

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 121 This fugure shows 68 mode 18 bit. In 68 mode, S_WRB must be connected to E_RDB of sub panel module. RW_WRB of sub panel module must be tied to VSS. Because S6E63D6 only writes data to sub panel module. Figure88: 68 mode 18 bit video data transfer This figure shows 80-mode 16 bit Video data transfer. Header 00022h GRAM write enable (index 22h) GRAM Write Enable (22h index) pixel write C R C Pixel data #1 (1ABCh) C R C

1 Video Stream Packet(16-bpp)

Pixel data #2 (00FFh) Pixel data #4 (01FFh) Pixel data #3 (FF00h) Pixel data #5 (0001h) Pixel data #1 1ABCh Pixel data #2 00FFh Pixel data #3 FF00h Pixel data #4 01FFh Pixel data #5 0001h pixel write pixel write pixel write pixel write DB[17:10],[8:1] (data output to sub LDI) S_CSB (chip select for sub LDI) S_RS (command / data select) S_WRB (write enable for sub LDI) MDDI Data Stream Figure89: 80 mode 16 bit video data transfer

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 122 This figure shows 80-mode 9 bit Video data transfer. Header 044h GRAM Write Enable (22h index) pixel write C R C Pixel data #1 (01ABCh) C R C Pixel data #2 (100FFh) Pixel data #4 (000FFh) Pixel data #3 (0FF00h) Pixel data #5 (00001h) 00Dh MSB pixel write pixel write pixel write pixel write DB[17:9] (data output to sub LDI) S_CSB (chip select for sub LDI) S_RS (command / data select) S_WRB (write enable for sub LDI) MDDI Data Stream 0BCh LSB Pixel data #1 080h MSB 0FFh LSB Pixel data #2 07Fh MSB 100h LSB 000h MSB 0FFh LSB Pixel data #3 Pixel data #4GRAM write enable 044h 000h MSB 001h LSB Pixel data #5 Figure90: 80 mode 9 bit video data transfer This figure shows 80-mode 8 bit Video data transfer. Header 22h GRAM Write Enable (22h index) pixel write C R C Pixel data #1 (1ABCh) C R C Pixel data #2 (00FFh) Pixel data #4 (01FFh) Pixel data #3 (FF00h) Pixel data #5 (0001h) 1Ah MSB pixel write pixel write pixel write pixel write DB[17:10] (data output to sub LDI) S_CSB (chip select for sub LDI) S_RS (command / data select) S_WRB (write enable for sub LDI) MDDI Data Stream BCh LSB Pixel data #1 00h MSB FFh LSB Pixel data #2 FFh MSB 00h LSB 01h MSB FFh LSB Pixel data #3 Pixel data #4GRAM write enable 22h 00h MSB 01h LSB Pixel data #5 Figure91: 80 mode 8 bit video data transfer

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 123 2. STN type sub panel timing

2.1 Register data transfer timing

This figure shows conventional type STN mode register data setting. Conventional type does not include parameter. Instruction type is only 8bit. To use STN type, STN_EN is set to “1”. In STN type, S6E63D6 controls S_RS pin using register address[0] in register access packet. Register address[0] is “0”, then S_RS is set to “0”, and register address[0] is “1”, S_RS is set to “1”. Refer to sub panel control(15h index) section. 00002h (0001h parameter) 000AAh (55h index) C R C S_DB[17:0] S_CSB S_RS S_WRB index write MDDI Data Stream Register Address (0000h) Header C R C Register Data (0055h) C R C Register Address (0000h) Header C R C Register Data (0001h) parameter write Figure92: 80 mode STN type convetional register instruction This type is used to include parameter. When instruction is transferred, S_RS is zero, and when parameter is transferred, S_RS is “1”. S_RS is controlled using register address[0] of register access packet. 000AAh (55h index) 00002h (0001h parameter) C R C S_DB[17:0] S_CSB S_RS S_WRB index write MDDI Data Stream Register Address (0000h) Header C R C Register Data (0055h) C R C Register Address (0001h) Header C R C Register Data (0001h) parameter write (RS = 1) Figure93: 80 mode STN type included parameter

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 124

2.2 Video data transfer timing

In STN mode, video data start register (like 22H is TFT mode) does not need generally. But some STN type needs video data start register. If those type STN DDI is used, user has to set the register index. This figure shows STN 16 bit mode video data transfer. Header 00044h (write disabled) pixel write C R C Pixel data #1 (01ABCh) C R C Pixel data #2 (100FFh) Pixel data #4 (000FFh) Pixel data #3 (0FF00h) Pixel data #5 (00001h) Pixel data #1 01ABCh Pixel data #2 100FFh Pixel data #3 0FF00h Pixel data #4 000FFh Pixel data #5 00001h pixel write pixel write pixel write pixel write DB[17:0] (data output to sub LDI) S_CSB (chip select for sub LDI) S_RS (command / data select) S_WRB (write enable for sub LDI) MDDI Data Stream Figure94: 80 mode STN type 16 bit video data transfer This figure shows STN 8bit mode video data transfer. If STN video data is 16bit mode, data transfer is executed during 2 times. Fist transfer is MSB 8bits, and second is LSB 8bits. Header 22h pixel write C R C Pixel data #1 (1ABCh) C R C Pixel data #2 (00FFh) Pixel data #4 (01FFh) Pixel data #3 (FF00h) Pixel data #5 (0001h) 1Ah MSB pixel write pixel write pixel write pixel write DB[17:10] (data output to sub LDI) S_CSB (chip select for sub LDI) S_RS (command / data select) S_WRB (write enable for sub LDI) MDDI Data Stream BCh LSB Pixel data #1 00h MSB FFh LSB Pixel data #2 FFh MSB 00h LSB 01h MSB FFh LSB Pixel data #3 Pixel data #422h write disabled 22h 00h MSB 01h LSB Pixel data #5 Figure95: 80 mode STN type video data transfer

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 125 SUB PANEL CONTROL TIMING 1. Index/parameter write for sub panel LDI 2. Image data write for sub panel LDI 3. Change data path from sub panel to main panel mddi_rxbyte_ena S_RS DB S_WRB data6 data7 data8 data9pixel_data(internal) data6 data7 data8 data9 S_CSB data2 data3 data4 data5data1 data3 data4 data5

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 126 AMOLED PANEL CONTROL INTERFACE S6E63D6 outputs some timing signals (FLM, SFTCLK, SFTC LKB, SCLK1, SCLK2, CLA, CLB, CLC, BICTL_L, BICTL_R, EX_FLM, EX_CLK, EX_CLKB, ESR) for controlling an AMOLED panel with built-in gates. S6E63D6 has built-in level shifter for AMOLED panel. Output voltage level for high is VGH voltage, for low is VGL voltage. Figure96: An Exemplary Combination

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 127 PANEL INTERFACE TIMING Figure97: Timing Diagram of Panel Interface Signals (GTCON=00)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 128 In Internal Clock Operation mode, the panel interface signals are generated based on internally generated oscillator clock. But in External Clock Operation mode, those are generated based on RGB I/F Signals. The Figure below shows the relation between them for External Clock Operation mode. Figure98: VSYNC and Panel Interface Signals in External Clock Operation mode

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 129 R, G, B INDEPENDENT GAMMA ADJUSTMENT FUNCTION S6E63D6 provides the gamma adjustment function to display 262,144 colors simultaneously. The gamma adjustment is executed by the amplitude adjusting registers and curve adjusting registers. Since, those control registers incorporate independent adjustment of the gamma function for R, G, B independently, it is highly possible that user determine the best appropriate configuration according to the trait of the display panel. Figure99: Grayscale Control

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 130 STRUCTURE of GRAYSCALER Grayscale level can be determined by registers that adjust both amplitude and curve. Also, the period of each level is split by the internal ladder resistor and generates level between V0 to V63. Amplitude adjusting part determines upper (V0) and lower (V63) bound voltage and curve adjusting part determines each 4 point (V4, V10, V21, V42) voltages independently for flexible curve control. Figure100: Structure of gray scaler

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 131 R, G, B INDEPENDENT GAMMA ADJUSTMENT REGISTERS These are registers to set up the grayscale voltage in ac cordance with the gamma specification of the AMOLED panel. The registers can set up both amplitude and curve ch aracter of grayscale voltage respectively with corresponding bits as the function of grayscale number. Each configuration can be made for R, G, B independently. There shows the operation of each register below. Figure101: The Operation of Adjusting Register Gray Scale Data Grqy Scale Voltage a) Top level control (4bit : 16step) V0 V63 Gray Scale Data Gray Scale Voltage b) Bottom level control (7bit : 128step) V0 V63 Gray Scale Data Gray Scale Voltage Flexible curve by 4 point control (6bits: 64step) VREG1OUT V63 Amplitude adjustment Curve adjustment

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 132 AMPLITUDE ADJUSTING REGISTERS These are the registers for adjusting the amplitude of grayscale voltage. The registers for adjusting amplitude consists of two parts, one of which is for top level voltage (V0) and the other of which is for bottom level voltage (V63). CR0[3:0], CG0[3:0] and CB0[3:0] registers control the top level voltage. CR5[6:0], CG5[6:0] and CB5[6:0] registers control the bottom level voltage. V0 and V63 are selected in divided voltage from ladder resistor strings between VGS and VREG1OUT. Separate registers are prepared for R, G, B respectively. Table52: Amplitude adjusting register Register for R for G for B Content of configuration CR0[3:0] CG0[3:0] CB0[3:0] Grayscale voltage adjusting for top level voltage R40H ~ R41H CR5[6:0] CG5[6:0] CB5[6:0] Grayscale voltage adjusting for bottom level voltage Table53: Relationship between amplitude adjusting register and V0 Register value CR0[3:0], CG0[3:], CB0[3:0] Formula 0 0 0 0 VREG1OUT – VREG1OUT x ( 0 /105) 0 0 0 1 VREG1OUT – VREG1OUT x ( 1 / 105) 0 0 1 0 VREG1OUT – VREG1OUT x ( 2 / 105) 0 0 1 1 VREG1OUT – VREG1OUT x ( 3 / 105) 0 1 0 0 VREG1OUT – VREG1OUT x ( 4 / 105) 0 1 0 1 VREG1OUT – VREG1OUT x ( 5 / 105) 0 1 1 0 VREG1OUT – VREG1OUT x ( 6 / 105) 0 1 1 1 VREG1OUT – VREG1OUT x ( 7 / 105) 1 0 0 0 VREG1OUT – VREG1OUT x ( 8 / 105) 1 0 0 1 VREG1OUT – VREG1OUT x ( 9 / 105) 1 0 1 0 VREG1OUT – VREG1OUT x ( 10 / 105) 1 0 1 1 VREG1OUT – VREG1OUT x ( 11 / 105) 1 1 0 0 VREG1OUT – VREG1OUT x ( 12 / 105) 1 1 0 1 VREG1OUT – VREG1OUT x ( 13 / 105) 1 1 1 0 VREG1OUT – VREG1OUT x ( 14 / 105) 1 1 1 1 VREG1OUT – VREG1OUT x ( 15 / 105)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 133 Table54: Relation between amplitude adjusting register and V63 Register value CR5[6:0] CG5[[6:0], CB5[6:0] Formula 0 0 0 0 0 0 0 VREG1OUT – VREG1OUT x ( 35 / 210) 0 0 0 0 0 0 1 VREG1OUT – VREG1OUT x ( 36 / 210) 0 0 0 0 0 1 0 VREG1OUT – VREG1OUT x ( 37 / 210) 0 0 0 0 0 1 1 VREG1OUT – VREG1OUT x ( 38 / 210) 0 0 0 0 1 0 0 VREG1OUT – VREG1OUT x ( 39 / 210) 0 0 0 0 1 0 1 VREG1OUT – VREG1OUT x ( 40 / 210) 0 0 0 0 1 1 0 VREG1OUT – VREG1OUT x ( 41 / 210) 0 0 0 0 1 1 1 VREG1OUT – VREG1OUT x ( 42 / 210) 0 0 0 1 0 0 0 VREG1OUT – VREG1OUT x ( 43 / 210) 1 1 1 0 0 0 0 VREG1OUT – VREG1OUT x (147 / 210) 1 1 1 0 0 0 1 VREG1OUT – VREG1OUT x (148 / 210) 1 1 1 0 0 1 0 VREG1OUT – VREG1OUT x (149 / 210) 1 1 1 0 0 1 1 VREG1OUT – VREG1OUT x (150 / 210) 1 1 1 0 1 0 0 VREG1OUT – VREG1OUT x (151 / 210) 1 1 1 0 1 0 1 VREG1OUT – VREG1OUT x (152 / 210) 1 1 1 0 1 1 0 VREG1OUT – VREG1OUT x (153 / 210) 1 1 1 0 1 1 1 VREG1OUT – VREG1OUT x (154 / 210) 1 1 1 1 0 0 0 VREG1OUT – VREG1OUT x (155 / 210) 1 1 1 1 0 0 1 VREG1OUT – VREG1OUT x (156 / 210) 1 1 1 1 0 1 0 VREG1OUT – VREG1OUT x (157 / 210) 1 1 1 1 0 1 1 VREG1OUT – VREG1OUT x (158 / 210) 1 1 1 1 1 0 0 VREG1OUT – VREG1OUT x (159 / 210) 1 1 1 1 1 0 1 VREG1OUT – VREG1OUT x (160 / 210) 1 1 1 1 1 1 0 VREG1OUT – VREG1OUT x (161 / 210) 1 1 1 1 1 1 1 VREG1OUT – VREG1OUT x (162 / 210)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 134 CURVE ADJUSTING REGISTERS The curve adjusting registers are used for adjusting the characteristic curve of the grayscale voltage as the function of grayscale number. The registers also control R, G, B independently like the amplitude adjusting register. To accomplish the adjustment, these registers control the each 4 reference voltage by three 47 to 1 selector and a 64 to 1 selector. The 47 or 64 leveled reference voltage generated from the ladder re sistor strings between V0 and V63. The registers for adjusting curve consist of 4 reference point – V4, V10, V21 and V42. Table55: Gamma Curve Adjusting Register Register For R for G for B Content of configuration CR1[5:0] CG1[5:0] CB1[5:0] Grayscale voltage adjusting for V4 CR2[5:0] CG2[5:0] CB2[5:0] Grayscale voltage adjusting for V10 CR3[5:0] CG3[5:0] CB3[5:0] Grayscale voltage adjusting for V21 R43H ~ R46H CR4[5:0] CG4[5:0] CB4[5:0] Grayscale voltage adjusting for V42 CR1[5:0], CG1[5:0], CB1[5:0] Register Control for V 4 Grayscale data Grayscale voltage CR2[5:0], CG2[5:0], CB2[5:0] Register Control for V1 0 Grayscale data Grayscale voltage CR3[5:0], CG3[5:0], CB3[5:0] Register Control for V2 1 Grayscale data Grayscale voltage CR4[5:0], CG4[5:0], CB4[5:0] Regis ter Control for V4 2 Grayscale data Grayscale voltage Figure102: Gamma curve adjustment

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 135 CURVE ADJUSTING BLOCK Below appears the table indicating the relation between the value of these registers and voltage-dividing ratio. Table56: Relationship between value of curve adjusting register and voltage-dividing ratio Register value Voltage dividing resistor value Register value Voltage dividing resistor value CR1[5:0] CG1[5:0] CB1[5:0] V4 formula CR2[5:0] CG2[5:0] CB2[5:0] V10 formula

000000 V0 - (V0 – V10) x 98/210 000000 V0 - (V0 – V21) x 193/300

000001 V0 - (V0 – V10) x 99/210 000001 V0 - (V0 – V21) x 194/300

000010 V0 - (V0 – V10) x 100/210 000010 V0 - (V0 – V21) x 195/300

000011 V0 - (V0 – V10) x 101/210 000011 V0 - (V0 – V21) x 196/300

000100 V0 - (V0 – V10) x 102/210 000100 V0 - (V0 – V21) x 197/300

111011 V0 - (V0 – V10) x 157/210 101010 V0 - (V0 – V21) x 235/300

111100 V0 - (V0 – V10) x 158/210 101011 V0 - (V0 – V21) x 236/300

111101 V0 - (V0 – V10) x 159/210 101100 V0 - (V0 – V21) x 237/300

111110 V0 - (V0 – V21) x 160/210 101101 V0 - (V0 – V21) x 238/300

111111 V0 - (V0 – V21) x 161/210 101110

~ 111111 V0 - (V0 – V21) x 239/300 CR3[5:0] CG3[5:0] CB3[5:0] V21 formula CR4[5:0] CG4[5:0] CB4[5:0] V42 formula

000000 V0 - (V0 – V42) x 85/150 000000 V0 - (V0 – V63) x 95/150

000001 V0 - (V0 – V42) x 86/150 000001 V0 - (V0 – V63) x 96/150

000010 V0 - (V0 – V42) x 87/150 000010 V0 - (V0 – V63) x 97/150

000011 V0 - (V0 – V42) x 88/150 000011 V0 - (V0 – V63) x 98/150

000100 V0 - (V0 – V42) x 89/150 000100 V0 - (V0 – V63) x 99/150

101010 V0 - (V0 – V42) x 127/150 101010 V0 - (V0 – V63) x 137/150

101011 V0 - (V0 – V42) x 128/150 101011 V0 - (V0 – V63) x 138/150

101100 V0 - (V0 – V42) x 129/150 101100 V0 - (V0 – V63) x 139/150

101101 V0 - (V0 – V42) x 130/150 101101 V0 - (V0 – V63) x 140/150

~ 111111 V0 - (V0 – V42) x 131/150 101110 ~ 111111 V0 - (V0 – V63) x 141/150

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 136

64 GRAY SCALE OUTPUT VOLTAGE

Below appears the table indicating the relation between the GRAM data value and output voltage value. Table57: Grayscale Output Voltage Formula Gray date Output value Gray data Output value

0 V0 32 V42 + ( V21 – V42 ) x 10/21

1 V4 + ( V0 – V4 ) x 28/48 33 V42 + ( V21 – V42 ) x 9/21

2 V4 + ( V0 – V4 ) x 12/48 34 V42 + ( V21 – V42 ) x 8/21

3 V4 + ( V0 – V4 ) x 6/48 35 V42 + ( V21 – V42 ) x 7/21

4 V4 36 V42 + ( V21 – V42 ) x 6/21

5 V10 + ( V4 – V10 ) x 20/25 37 V42 + ( V21 – V42 ) x 5/21

6 V10 + ( V4 – V10 ) x 15/25 38 V42 + ( V21 – V42 ) x 4/21

7 V10 + ( V4 – V10 ) x 10/25 39 V42 + ( V21 – V42 ) x 3/21

8 V10 + ( V4 – V10 ) x 7/25 40 V42 + ( V21 – V42 ) x 2/21

9 V10 + ( V4 – V10 ) x 3/25 41 V42 + ( V21 – V42 ) x 1/21

10 V10 42 V42

11 V21 + ( V10 – V21 ) x 21/24 43 V63 + ( V42 – V63) x 20/21

12 V21 + ( V10 – V21 ) x 19/24 44 V63 + ( V42 – V63) x 19/21

13 V21 + ( V10 – V21 ) x 17/24 45 V63 + ( V42 – V63) x 18/21

14 V21 + ( V10 – V21 ) x 14/24 46 V63 + ( V42 – V63) x 17/21

15 V21 + ( V10 – V21 ) x 12/24 47 V63 + ( V42 – V63) x 16/21

16 V21 + ( V10 – V21 ) x 10/24 48 V63 + ( V42 – V63) x 15/21

17 V21 + ( V10 – V21 ) x 8/24 49 V63 + ( V42 – V63) x 14/21

18 V21 + ( V10 – V21 ) x 6/24 50 V63 + ( V42 – V63) x 13/21

19 V21 + ( V10 – V21 ) x 4/24 51 V63 + ( V42 – V63) x 12/21

20 V21 + ( V10 – V21 ) x 2/24 52 V63 + ( V42 – V63) x 11/21

21 V21 53 V63 + ( V42 – V63) x 10/21

22 V42 + ( V21 – V42 ) x 20/21 54 V63 + ( V42 – V63) x 9/21

23 V42 + ( V21 – V42 ) x 19/21 55 V63 + ( V42 – V63) x 8/21

24 V42 + ( V21 – V42 ) x 18/21 56 V63 + ( V42 – V63) x 7/21

25 V42 + ( V21 – V42 ) x 17/21 57 V63 + ( V42 – V63) x 6/21

26 V42 + ( V21 – V42 ) x 16/21 58 V63 + ( V42 – V63) x 5/21

27 V42 + ( V21 – V42 ) x 15/21 59 V63 + ( V42 – V63) x 4/21

28 V42 + ( V21 – V42 ) x 14/21 60 V63 + ( V42 – V63) x 3/21

29 V42 + ( V21 – V42 ) x 13/21 61 V63 + ( V42 – V63) x 2/21

30 V42 + ( V21 – V42 ) x 12/21 62 V63 + ( V42 – V63) x 1/21

31 V42 + ( V21 – V42 ) x 11/21 63 V63

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 137 OUTPUT LEVEL AS THE FUNCTION OF GRAM DATA Output level could be described as the function of GRAM DATA like below. REV = 0 REV = 1V0 V63 Output Level RAM data 000000 111111 V63 Output Level RAM data 000000 111111 V63 Output Level RAM data 000000 111111 V63 Output Level RAM data (Independently controlable characteristics to RGB) 000000 111111 Figure103: Relationship between RAM Data and Output Voltage

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 138 Table58: GRAM Data and Grayscale Level GRAM data Grayscale GRAM data Grayscale GRAM data Grayscale GRAM data Grayscale RGB REV=0 REV=1 RGB REV=0 REV=1 RGB REV=0 REV=1 RGB REV=0 REV=1

000000 V0 V63 010000 V16 V47 100000 V32 V31 110000 V48 V15

000001 V1 V62 010001 V17 V46 100001 V33 V30 110001 V49 V14

000010 V2 V61 010010 V18 V45 100010 V34 V29 110010 V50 V13

000011 V3 V60 010011 V19 V44 100011 V35 V28 110011 V51 V12

000100 V4 V59 010100 V20 V43 100100 V36 V27 110100 V52 V11

000101 V5 V58 010101 V21 V42 100101 V37 V26 110101 V53 V10

000110 V6 V57 010110 V22 V41 100110 V38 V25 110110 V54 V9

000111 V7 V56 010111 V23 V40 100111 V39 V24 110111 V55 V8

001000 V8 V55 011000 V24 V39 101000 V40 V23 111000 V56 V7

001001 V9 V54 011001 V25 V38 101001 V41 V22 111001 V57 V6

001010 V10 V53 011010 V26 V37 101010 V42 V21 111010 V58 V5

001011 V11 V52 011011 V27 V36 101011 V43 V20 111011 V59 V4

001100 V12 V51 011100 V28 V35 101100 V44 V19 111100 V60 V3

001101 V13 V50 011101 V29 V34 101101 V45 V18 111101 V61 V2

001110 V14 V49 011110 V30 V33 101110 V46 V17 111110 V62 V1

001111 V15 V48 011111 V31 V32 101111 V47 V16 111111 V63 V0

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 139 THE 8-COLOR DISPLAY MODE The S6E63D6 incorporates 8-color display mode. The voltage levels to be used are VREG1OUT and V63 and all the other grayscale levels V0~V62are halt. So that it attempts to lower power consumption. During the 8-color mode, the Gamma micro adjustment register, C1R~C4R, C1G~C4G and C1B~C4B are invalid. The level power supply (V0-V62) is in OFF condition during the 8-color mode in order to select VREG1OUT/V63. Figure104: 8-color display control

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 140 SET UP FLOW OF STANDBY Figure105: Setup flow of STNADBY

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 141 OSCILLATION CIRCUIT The S6E63D6 can provide R-C oscillation. S6E63D6 internal oscillator does not need to attach the external resistor. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the oscillator frequency control register setting. Since R-C oscillation stop s during the standby mode, power consumption can be reduced. FRAME FREQUENCY CALCULATION The relation between the AMOLED driver duty and the frame frequency can be found by the following expression. Figure106: Formula for the Frame Frequency EXAMPLE CALCULATION Parameters Description Line Number 320 Frame Frequency 60 BP 8 FP 8 fosc 1,290,240 Hz „ Display Clock Frequency Table59: DISPLAY CLOCK FREQUENCY

1 HCLK 1 Horizontal Period

Internal Clock Operation Fosc / 2 32 HCLKs External Clock Operation Fdotclk / 8(RIM=00,01) Fdotclk/24(RIM = 10) 32 HCLKs

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 142 APPLICATION CIRCUIT The following figure indicates a typical application circuit for S6E63D6. Figure107: S6E63D6 Application (80 System CPU Parallel Interface)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 143 SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Table60: Absolute Maximum Rating (VSS = 0V) Item Symbol Rating Unit Supply voltage VDD3 -0.3 ~ 5.0 V Supply voltage for step-up circuit VCI -0.3 ~ 5.0 V Supply Voltage range |VLIN2 – VLIN3| 20 V Input Voltage range Vin -0.3 to VDD + 0.5 V Notes: 1. Absolute maximum rating is the limit value. When the IC is exposed operating environment beyond this range, the IC do not assure operations and may be damaged permanently, not be able to be recovered. 2. Absolute maximum rating is guaranteed only when our company’s package used.

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 144 DC CHARACTERISTICS Table61: DC Characteristics (VSS = 0V) Characteristic Symbol CONDITION MIN TYP MAX Unit Note VGH 4.6 - 6.6 V VGL -7.8 - -5.0 V Driving voltage VINT - -4.0 - -1.0 V Photo Sensor Power VSP - 2.9 3.0 3.1 V Logic Operating Voltage RVDD - 1.45 1.5 1.55 V Operating frequency fosc Frame frequency = 60Hz Display line = 320 line 1192.3 1324.8 1457.2 kHz 1st step-up input voltage VCI1 - 2.1 - 2.75 V 1st step-up output voltage VLOUT1 Without load +4.2 - +5.5 V 1st step-up output efficiency VLOUT1 I_ VLOUT1_LOAD = 2.3mA 90 95 - % 2nd step-up output voltage VLOUT2 Wi thout load +6.3 - +11.0 V 2nd step-up output efficiency VLOUT2 I_ VLOUT2_LOAD = 0.1mA 90 93 - % 3rd step-up output voltage VLOUT3 Without load -11.0 - -6.3 V 3rd step-up output efficiency VLOUT3 I_ VLOUT3_LOAD = 0.1mA 90 93 - % Source Output voltage deviation (channel to channel) - - - ±TBD - mV Output voltage deviation (Chip to Chip) - - - ±TBD - mV Source driver output voltage range Vso - 0.96 - 4.2 V LTPS driver output voltage deviation - - - - TBD V Driving voltage dVGH voltage deviation - - TBD V dVGL - - TBD V IVDD3 - - TBD uA - Current consumption during normal operation IVCI No load, Ta = 25 °C VCI=2.8V Frame(f)=60Hz - - TBD mA -

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 145 Characteristic Symbol CONDITION MIN TYP MAX Unit Note Power Supply Voltage VCI O perating Voltage 2.5 2.8 3.3 V Power Supply Voltage VDD3 I/O supply Voltage 1.65 1.8 3.3 V Logic High level input voltage VIH 0.7*VDD3 VDD3 V Logic Low level input voltage VIL 0.0 0.3*VDD3 V Logic High level output voltage VOH I OUT = -1mA 0.8*VDD3 VDD3 V Logic Low level output voltage VOL I OUT = +1mA 0.0 0.2*VDD3 V Analog High level output voltage EL_ONOH 8uA 1.6 V Analog Low level output voltage EL_ONOL 8uA 0 0.4 V Characteristic Symbol CONDITION MIN TYP MAX Unit Note VREG1OUT . 4.185 4.2 4.215 V

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 146 PANEL INTERFACE GATE IC LESS LEVEL SHIFTER OUTPUT CHARACTERISTICS Figure108: AC Characteristics of Level Shifter Output Figure109: LTPS Signal Load Test Point

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 147 Table62: AC Parameters of Level Shifter Outputs Total Load Level Shifter Output R(ohm) C(pF) High Level Low Level Item Symbol Min Typ Max Unit Rising Time tr - - 2000 ns BICTL 1320 78 VGH VGL Falling Time tf - - 2000 ns Rising Time tr - - 500 ns CLA, CLB, CLC 3500 39 VGH VGL Falling Time tf - - 500 ns Rising Time tr - - 1000 ns FLM 900 42 VGH VGL Falling Time tf - - 1000 ns Rising Time tr - - 300 ns Falling Time tf - - 300 ns SFTCLK, SFTCLKB 895 61 VGH VGL Cross Point rCross 40 50 60 % Rising Time tr - - 300 ns SCLK1, SCLK2 895 61 VGH VGL Falling Time tf - - 300 ns Rising Time tr - - 1000 ns EX_FLM 910 42 VGH VGL Falling Time tf - - 1000 ns Rising Time tr - - 350 ns Falling Time tf - - 350 ns EX_CLK, EX_CLKB 910 68 VGH VGL Cross Point rCross 40 50 60 % Rising Time tr - - 2000 ns ESR 1320 60 VGH VGL Falling Time tf - - 2000 ns SOURCE OUTPUT S1 ~ S240 Certain Grayscale VoltagetDD mV Certain Grayscale Voltage mV Figure110: AC Characteristics of Source Driver Output Table63: AC Parameters of Source Driver Output Symbol Test Condition Value tDD VCI1 = 2.75 V Fosc = 1324.8 kHz Grayscale to be reached = ±10mV Load Resistance R = 32 Kohm Load Capacitance C = 20pF SAP[2:0]=101 9 usec / 4V max. (with demux)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 148 VINT Source - Functions and conditions of VINT output - During 1H(=51.2us, 1 horizontal line) time, turn on Tr to reset Cst for about 10us - Peak current = 3.15mA - VINT ripple(at saturation position) < 100mV - VINT Saturation time < 7us Figure111: Current Wave of VINT

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 149 AC CHARACTERISTICS Table64: Parallel Write Interface Characteristics (68 Mode) (VDD = 1.5V, VDD3 = 1.65 to 3.3V, TA = -40 to +85oC) Specification Characteristic Symbol Min. Max. Unit Write t CYCW68 TBD - Cycle time Read t CYCR68 TBD - Pulse rise / fall time t R, tF - TBD Write t WHW68 TBD - Pulse width low Read t WHR68 TBD - Write t WLW68 TBD - Pulse width high Read t WLR68 TBD - RS,RW to CSB, E setup time t AS68 TBD - RS,RW to CSB, E hold time tAH68 TBD - CSB to E time tCW68 TBD - Write data setup time t WDS68 TBD - Write data hold time t WDH68 TBD - Read data delay time t RDD68 - TBD Read data hold time t RDH68 TBD TBD ns Figure112: AC Characteristics (68 Mode)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 150 Table65: Parallel Write Interface Characteristics (80 Mode) (VDD = 1.5V, VDD3 = 1.65 to 3.3V, TA = -40 to +85oC) Specification Characteristic Symbol Min. Max. Unit Write t CYCW80 TBD - Cycle time Read t CYCR80 TBD - Pulse rise / fall time t R, tF - TBD Write t WLW80 TBD - Pulse width low Read t WLR80 TBD - Write t WHW80 TBD - Pulse width high Read t WHR80 TBD - RS to CSB, WRB(RDB) setup time t AS80 TBD - RS to CSB, WRB(RDB) hold time tAH80 TBD - CSB to WRB(RDB) time tcw 80 TBD - Write data setup time t WDS80 TBD - Write data hold time t WDH80 TBD - Read data delay time t RDD80 - TBD Read data hold time t RDH80 TBD TBD ns Figure113: AC Characteristics (80 Mode)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 151 Table66: Clock Synchronized Serial Write Mode Characteristics (VDD = 1.5V, VDD3 = 1.65 to 3.3V, TA = -40 to +85oC) specification Characteristic Symbol Min. Max. Unit Serial clock write cycle time tscyc TBD - ns Serial clock read cycle time tscyc TBD - ns Serial clock rise / fall time t R, tF - TBD ns Pulse width high for write t SCHW TBD - ns Pulse width high for read t SCHR TBD - ns Pulse width low for write t SCLW TBD - ns Pulse width low for read t SCLR TBD - ns Chip Select setup time t CSS TBD - ns Chip Select hold time t CSH TBD - ns Serial input data setup time t SIDS TBD - ns Serial input data hold time t SIDH TBD - ns Serial output data delay time t SODD - TBD ns Serial output data hold time t SODH TBD - ns Transfer Start VOH1 VOL1 VIL VIH VIL VOH1 VOL1 VIH tSIDS tSIDH tSODH SCL SDI SDO VIL VIL VIH VIH VIL VIL VIH VIH CSB VIH VIL tSODD tCSS tCSH tR tFtSCHW / tSCHR tSCLW / tSCLR tscyc INPUT DATA INPUT DATA OUTPUT DATA OUTPUT DATA Transfer End Figure114: AC Characteristics (SPI Mode)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 152 Table67: RGB Data Interface Characteristics (VDD = 1.5V, VDD3 = 1.65 to 3.3V, TA = -40 to +85oC) 18/16bit RGB interface 6bit RGB interface Unit Characteristic Symbol Min. Max. Min. Max. DOTCLK cycle time t DCYC TBD - TBD - DOTCLK rise / fall time t R, tF - TBD - TBD DOTCLK Pulse width high t DCHW TBD - TBD - DOTCLK Pulse width low t DCLW TBD - TBD - Vertical Sync Setup Time tvsys TBD - TBD - Vertical Sync Hold Time tvsyh TBD - TBD - Horizontal Sync Setup Time thsys TBD TBD Horizontal Sync Hold Time thsyh TBD TBD ENABLE setup time t ENS TBD - TBD - ENABLE hold time t ENH TBD - TBD - PD data setup time t PDS TBD - TBD - PD data hold time t PDH TBD - TBD - ns HSYNC-ENABLE Time tHE TBD HBP TBD HBP VSYNC-HSYNC Time thv TBD TBD TBD TBD tDCYC Note : HBP is Horizontal Back-porch. (When VSPL=0, HSPL=0, DPL=0, EPL=1) Figure115: AC Characteristics (RGB Interface Mode)

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 153 RESET TIMING tRES RESETB VIL VIL Note : Reset low pulse width shorter than 10us do not make reset. It means undesired short pulse such as glitch, bouncing noise or electrostatic discharge do not cause irregular system reset. Please refer to the table below. Figure116: AC characteristics (RESET timing) Parameter Description Min Max Unit tRES Reset low pulse width 10 - us Table68: Reset Operation regarding tRES Pulse Width tRES Pulse Action Shorter than 5 us No reset Longer than 10 us Reset Between 5 us and 10 us Not determined 1. User may or may not use RESETB pin. In order to use it, user should satisfy the conditions described in the above tables. But when not wants to use RESETB, user may fix this pin to VDD3 level because internally generated POR (Power-On-Reset) is used. 2. Spike Rejection also applies during a valid reset pulse as shown below: Less than 20ns width positive spike will be rejected. 10us Reset is accepted 20ns

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 154 EXTERNAL POWER ON / OFF SEQUENCE VDD3 must be applied earlier than VCI or at least app lied simultaneously with VCI. When regulator cap is 1μF, RESETB must be applied after VCI have been applied. The applied time gap between VCI and RESETB is minimum 1ms. As regulator cap becomes larger, this time gap must be increased. Otherwise function is not guaranteed. Figure117: External power on sequence b) EXTERNAL POWER OFF SEQUENCE VDD3 must be powered down later than VCI or at least powered down simultaneously with VCI. VCI must be powered down after RESETB have been powered down. The time gap of powered down between RESETB and VCI is minimum 1ms. Otherwise function is not guaranteed. Figure118: External Power Off sequence

S6E63D6 PRELIMINARY VER. 0.0 240 RGB X 320 DOT 1-CHIP DRIVER IC WITH LTPS INTERFACE FOR 262,144 COLOR AMOLED Preliminary 155 NOTICE Precautions for Light Light has characteristics to move electrons in the inte grated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, botto m and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate (board or glass) or product design stage. 2. Always test and inspect products under t he environment with no penetration of light.