S6B33A2

S6B33A2 SAMSUNG | Alldatasheet

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128 RGB Segment & 129 Common Driver For 4,096 Color STN LCD

Sep. 06. 2002. Ver. 1.3 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team S6B33A2

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD S6B33A2 Specification Revision History Version Content Date 0.0 Original Oct. 2001 0.1 1. Page11 Added & Changed Test Pin 2. Page24 Deleted “ Data Bus Mode Set” Instruction Deleted “ Driving Current Mode & Bias Set” Instruction Deleted “ Row Vector Mode Set” Instruction Added “ DDRAM Burst Mode On/Off” Instruction 3. Page25 Deleted “ Data Bus Mode Set” description 4. Page26 Reduced bus bandwidth of DIV(1) and DIV(2) 5. Page28 Deleted “ Driving Current Mode and Bias Set” description 6. Page33 Deleted “ Row Vector Mode Set” description Added “ DDRAM Burst Mode On/Off” description 7. Page37 Deleted “ MDI” bit in “ Entry Mode Set” parameters 8. Page49 - Modified the register list and parameters according to modification Nov. 2001 0.2 - Page2 Deleted C24+, C24- pin in block diagram 2.Page 9 Deleted C24+, C24- pin in pin description 3.Page12 - Deleted “ REG_ENB” pin - Deleted “ TEST2” , “ TEST3” pin 4.Page23 - Delete “ REG_ENB” pin on figure20 5.Page25 Added “ Red, Green and Blue Palette Set” instruction. 6.Page 28 Changed DCDC clock division ratio 7.Page 35 Added “ GSM” bit for gray scale selection at “ Gray Scale Mode Set” instruction Page 37 Added “ Red, Green and Blue Palette Set” description Page38 Added “ HL” bit at “ Entry Mode Set” instruction Page 50 Modified the register list and parameters according to modification 11.Page 54 Changed Oscillator frequency tolerance and range 12.Page41,43,44,55,56 - The duty of partial mode1 is changed from 1/69 to 1/66 Dec. 2001

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD S6B33A2 Specification Revision History Version Content Date 0.3 - Page4~9 Added key coordinates, pad dimension, configuration and coordinates 2. Page59 Added “ the limitation of usage of analog circuit” in detail 3. Page65~66 - Added system application diagram Jan. 2002 0.4 1. Page3 Deleted CK Pin 2. Page10 Modified pin description 3. Page16 - Collected the code of X,Y address 4. Page 50 - Described write/read data which is accessed by MCU I/F in 256 color mode Jan. 2002 0.5 1. Page5 - Deleted *note about ILB, TOM align key Jan.2002 0.6 - Page26, 50 - Added display format select command(60H/61H) 2. Page27 Added “ DIV2” bit at “ Oscillation Mode Set” instruction 3. Page66 - Add maximum rating voltage of capacitors Mar.2002 0.7 - Page 26,35,36 - Delete Burst mode on/off instruction 2. Page 59,60 – Add MPU 68/80 Parallel I/F AC Timing May.2002 0.8 1. Page 65 - Add shot-key diode at application circuit May.2002 0.9 1. Page 26, 35, 51 - Add ROW Vector Mode Set Command May.2002 1.0 1. Page 65 - Add Values of Schottky barrier diode. Jun.2002 1.1 1. Page 30 - Corrected Miss-typing. Jul.2002 1.2 1. Page 53~61 - Filled TBD items Jul.2002 1.3 1. Page 18 - Delete “ Block NO” on figure15. 2. Page 59-60 - Delete a word of “ 25°C” from condition item on table17. 3. Page 54 - Add DC Spec of DC2IN, VIN2 and VIN45 4. Page 55 - Add Current Measure data Sep.2002

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD INTRODUCTION S6B33A2 is a mid-display-size-compatible driver for liquid crystal dot matrix gray-scale graphic systems. With on- chip RC oscillator circuit, the display-timing signal is generated without being sent from MPU. Also, it is capable of using 8bit/16bit data bus alternatively and operating with 68/80-series MPU in asynchronous. Due to the internal bit- map display RAM of 128 ×128 ×12-bit, S6B33A2 is capable of operating max. 128 RGB x 128 dot LCD panels in low-power consumption. Being the segment RGB 3-output, one pixel is 12-bit data and S6B33A2 can display 4,096 color.

FEATURES

129 COM X 128 RGB SEG

4,096 color display of R: 16 gray scale, G: 16 gray scale, B: 16 gray scale 256 color display of R: 8 gray scale, G: 8 gray scale, B: 4 gray scale On-chip Display Data RAM Capacity: 128 x 128 x 12 = 196,608 bits Display Mode Normal display mode: Entire duty displaying Partial display mode: Partial displaying Standby mode: Internal display clocks off Area scroll mode: Particular area scrolling Microprocessor Interface 8-bit/16 bit parallel bi-directional interface with 6800-series or 8080-series 3/4 Pin SPI (only write operation) On-chip Low Power Analog Circuit On-chip RC oscillator (Internal cap. & external resistor), external clock available Voltage converter Voltage regulator Voltage follower On-chip electronic contrast control (256 steps) Bias ratio: 1/6 Operating Voltage Range VDD : 1.8 to 3.3 [V] (without Internal Regulator), 2.4 to 3.3 [V] (With internal Regulator) VIN1: 2.4 to 3.6 [V] Display operating voltage(V1): 2.0 to 3.3 V LCD Operating Voltage Range : 20 V Low Power Consumption - 650 uA Typ. Package Type - COG

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Output Pad Pitch - 38um Min.

128 X 1536

Figure 1. Block Diagram

Figure 2. S6B33A2 Chip Pad Configuration Table 1. S6B33A2 Pad Dimensions

Figure 7. S6B33A2 Chip Pin Configuration

Table 2. Pad Center Coordinates

Table 2. Pad Center Coordinates (Continued)

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD PIN DESCRIPTION Table 3. Power Supply Pins

Description

Supply Power supply(Logic) VDD3R Supply Internal regulator power supply This pin is connected to VDD. VDD1 Supply Regulated power supply input pin for internal digital and DDRAM block. This pin is connected to REG_OUT outside the chip with stabilization capacitor. When the internal regulator is not used, VDD1 should be tied to VDD directly. VSS,VSSA VSSB,VSSO GND Ground VCC I LCD common high selected driving voltage input pin V1IN I LCD segment high selected driving voltage input pin VMIN I LCD common/segment non-selected driving voltage input pin V0IN I LCD segment low selected driving voltage input pin VEE,VEES I LCD common low selected driving voltage input pin The relationship between VCC, V1, VM, V0 and VEE: VCC > V1 > VM > V0(=VSS) > VEE (V1 – VM = VM – V0, VCC –VM = VM – VEE) VIN1,VIN1A I Power supply for 1’ st booster circuit and VM amp VIN2 I Power supply for 2’ nd booster circuit VOUT45 O 1’ st booster output pin VIN45 I Power supply for V1. Connect to VOUT45 or VIN1 C11+ C11- C12+ C12- O External capacitor connection pins used for 1’ st booster circuit V1OUT O LCD segment high driving voltage output pin V1T I Thermistor resistor connection pin INTRS I External resister select pin for temperature compensation circuit – INTRS = L : External resistor mode, INTRS = H : Internal resistor mode VMOUT O LCD common/segment non-selected driving voltage output pin DC2OUT O Power output pin for 2’ nd booster input DC2IN I Power supply for 2’ nd booster. Connect to DC2OUT pin C21+ C21- C22+ C22- C23+ C23- O External capacitor connection pins used for 2’ nd booster circuit -VR O LCD common low selected driving voltage output pin C31+ C31- O External capacitor connection pins used for 3’ rd booster circuit +VR O LCD common high selected driving voltage output pin

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Table 4. MPU Interface Pins /RST I Reset input pin. When /RST is “ L” , initialization is executed. MPU interface select pin PS MPU[1] MPU[0] H L L 8080-series 8bit interface H L H 8080-series 16bit interface H H L 6800-series 8bit interface H H H 6800-series 16bit interface L L X 3 pin SPI(Write only) PS MPU[1:0] I L H X 4 pin SPI(Write only) /CS1 CS2 I Chip select input pins Data / instruction I/O is enabled only when /CS1 is “ L” and CS2 is “ H” . When chip select is non-active, DB0 to DB15 may be high impedance. D/I I Data / Instruction select input pin − D/I = “ H” : DB0 to DB15 are display data − D/I = “ L” : DB0 to DB7 are instruction data Read / Write execution control pin PS MPU MPU Type /WR H H 6800-series R/W Read/Write control input pin − R/W = “ H” : read − R/W = “ L” : write /WR (R/W) I H L 8080-series /WR Write enable clock input pin The data on DB0 to DB15 are latched at the rising edge of the /WR signal. Read / Write execution control pin MPU[1] MPU type /RD H 6800- series E Read / Write control input pin − R/W = “ H” : When E is “ H” , DB0 to DB15 are in an output status. − R/W = “ L” : The data on DB0 to DB15 are latched at the falling edge of the E signal. /RD (E) I L 8080- series /RD Read enable clock input pin When /RD is “ L” , DB0 to DB15 are in an output status. DB[15:8] DB[7]/SDI DB[6]/SCL DB[5:0] I/O -DB[15:0]: 16-bit bi-directional data bus. -SDI: Serial data input pin. The data is latched at the rising edge of SCL. -SCL: Serial clock input pin. CDIR I Common direction select pin.

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Table 5. Oscillator and Power Regulator Pins O CR oscillator output pin When the internal CR oscillator is used, connect to OSC1, OSC3 through a resistor. OSC1 – OSC2: Using in normal display mode, partial display mode 0 OSC3 – OSC4: Using in partial display mode 1 When an external oscillator is used, OSC1 pin is connected to VDD or VSS. OSC5 I External clock input pin When an external input is used, it is input to this pin. But the internal oscillator is used, this pin is connected to VDD or VSS. REG_OUT O Internal voltage regulator output pin The regulator output port from this pin is used as a power supplier for an internal digital block via VDD1 pins. Table 6. Timing signal Pins for monitoring O Shift clock output pin PM O Field delimiter output pin FR O Liquid crystal alternating current output pin Table 7. LCD driver output pins O LCD driving segment output (Red or Blue) SEGB0 to 127 O LCD driving segment output (Green) SEGC0 to127 O LCD driving segment output (Blue or Red) COM0 to 128 O LCD common outputs Table 8. Test pins TEST [4:0] I Don’ t use these pins. IC maker’ s test pins. Fix “ High” in normal mode.

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD FUNCTIONAL DESCRIPTION MPU INTERFACE Chip Select Input There are /CS1 and CS2 pins for chip selection. The S6B33A2 can interface with an MPU only when /CS1 is “ L” and CS2 is “ H” . When these pins are set to any other combination, D/I, /RD, and /WR inputs are disabled and DB0 to DB15 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel/Serial Interface The S6B33A2 has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in Table9. Table 9. Parallel / Serial Interface Mode. Table 10. Microprocessor Selection for Parallel Int erface Table 11. Parallel Data Transfer H H H L H Read display data H H L H L Write display data L H H L H Read out internal status register L H L H L Write instruction data

functions are accomplished by the internal instructions. area, the addresses become the start address. Figure 12. DDRAM Address Area Table 13. X address Control Table 14. Y address Control

Figure 15. Display Data RAM Map

the various display duties. It is set as display start/end line number. The S6B33A2 realizes the specific area scroll function. (1/128 duty case).

100 Lines

Figure 16. Area scroll examples (duty = 1/128, center scroll mode)

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD CDIR The direction of common scanning is selected by CDIR pin. COM 0 Line number 0 Display Area 128Display Lines <CDIR=0> COM 128 Line number 127 COM 0 Display Area <CDIR=1> COM 128 Line number 0 COM 127 COM 1 Line number 127 Driver SEG128RGB COM128 COM 62 COM 0 COM63

Figure 21. The relationship between SEG outputs and RGB color

When partial display mode 1 is not used. When partial display mode 1 is used. Figure 24. Internal oscillator application Driving voltage level discharge time at stand by ON. The relation between voltage level and discharge time from when “ Stand By ON” command is inputted.

Table 15. Instruction Table Parameter: The number of parameter bytes that follows instruction data.

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Non Operation (00H) This instruction is Non operation. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Oscillation Mode Set (02H) Setting internal function mode. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DIV2 EXT OSC DIV2: Display clock selecting DIV2 = 0: Display clock = OSC clock (Initial status) DIV2= 1: Display clock = OSC/2 clock EXT: External clock selecting EXT = 0: Internal clock mode (Initial status) EXT = 1: External clock mode OSC: Internal oscillator ON/OFF OSC = 0: Internal oscillator OFF(Initial status) OSC = 1: Internal oscillator ON Driver Output Mode Set(10H) This instruction sets the display direction. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDIR SWP SDIR: Segment direction This bit is for controlling the direction of segment driver. SDIR = 0 (Initial status) SWP: Swap segment output SEGAi and SEGCi This bit is for swapping the output of segment driver. SWP = 0 (Initial status)

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC-DC Select (20H) Selects DC-DC step-up of the common driver in normal and partial mode D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DC(2) DC(1) DC(1) : 1’ st DC-DC booster boosting step select for V1 generation in normal mode and partial mode 0. DC(2) : 1’ st DC-DC booster boosting step select for V1 generation in partial mode 1. DC(2) : In partial mode 1 DC(1) : In normal mode, partial mode 0 DB1 DC-DC step up DB0 DC-DC step up X1.0 X1.0 X1.5 X1.5

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC-DC Select and power supply for V1 Op-Amp. Even if VIN45 is connected to VOUT45 or VIN1, a setup by software must be able to be performed. Power supply for V1 Op.Amp. is decided by Hardware setting and Software setting. The example of usage is shown below. Hardware setting : VIN45 connected to (1) VIN1 (when 1’ st boosting is not used) (2) VOUT45 (when 1’ st boosting is used) Software setting : DC-DC Select(20H) - DC(1), DC(2) Set value “ 00” Power supply for V1 Op.Amp. uses VIN1 directly. Set value “ 01” or “ 10” Power supply for V1 Op.Amp. uses VOUT45. 1st Booster Circuit Reference voltage generator Temperature Compensation Control Circuit VIN1 C11- C11+ C12- C12+ VOUT45 VIN45 EV_256 Software Setting Hardware Setting V1 generation circuit Figure28. Example : Hardware Setting Software Setting : VIN45 connected to VOUT45 : Power supply for V1 Op.Amp. uses VIN1 ( not VOUT45). VSS

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DCDC Clock Division (24H) This instruction sets the internal booster clock frequency. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DIV(2) DIV(1) DIV(1) : DC-DC Charge Pump Division Ratio in Normal Mode Display and Partial Display Mode0 - DIV(1) = 10 (Initial status) DIV(2) : Division Ratio in Partial Display Mode1 - DIV(2) = 10 (Initial status) DB5 DB4 DIV(2) DB1 DB0 DIV(1) fPCK = fOSC/2x fPCK = fOSC/2x fPCK = fOSC/4x fPCK = fOSC/4x fPCK = fOSC/6x fPCK = fOSC/6x fPCK = fOSC/8x fPCK = fOSC/8x Note: fOSC = ( ROUNDUP (Duty/3) + dummy) x 4 x 4 x frame frequency DC/DC and AMP ON/OFF Set (26H) This instruction set up the DC/DC and Op-amp in common start up setting. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AMP DCDC3 DCDC2 DCDC1 AMP : Built-in OP-AMP ON/OFF. - AMP=0 :OP-AMP OFF(Initial status) - AMP=1 :OP-AMP ON DCDC1: Built-in 1st Booster ON/OFF (Initial status) - DCDC1= 0: 1st Booster OFF (Initial status) - DCDC1= 1: 1st Booster ON DCDC2: Built-in 1st Booster ON/OFF (Initial status) - DCDC2= 0: 2nd Booster OFF (Initial status) - DCDC2= 1: 2nd Booster ON DCDC3: Built-in 1st Booster ON/OFF (Initial status) - DCDC3= 0: 3rd Booster OFF (Initial status) - DCDC3= 1: 3rd Booster ON

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Temperature Compensation Set (28H) This Instruction sets up the driving voltage slope for temperature compensation. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TCS TCS: Temperature compensation slope set TCS = 00 : 0.00%/degC TCS = 01 : -0.05%/degC TCS = 10 : -0.10%/degC TCS = 11 : -0.15%degC 00: 0.00 %/degC Driving voltage 01: -0.05 %/degC 10: -0.10 %/degC 11: -0.15 %/degC Temperature

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Temperature Compensation If external temperature compensation is needed, circuit diagram is described as below. To use temperature compensation, two resistors and one thermistor are needed. External Chip Internal V1-i V1-o V1-t INTRS

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Contrast Control (1) (2AH) This instruction updates the contrast control value in normal display mode and partial display mode 0. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Contrast control value (0 to 255) The relation between V1 voltage (typ.) and Contrast(1) set value ( 3bit step case) Contrast(1) (HEX) V1[V] Contrast(1) (HEX) V1[V] Contrast(1) (HEX) V1[V] Contrast(1) (HEX) V1[V] Contrast(1) (HEX) V1[V] Contrast(1) (HEX) V1[V] 00h 2.000 30h 2.244 60h 2.488 90h 2.731 C0h 2.975 F0h 3.219 08h 2.041 38h 2.284 68h 2.528 98h 2.772 C8h 3.016 F8h 3.259 10h 2.081 40h 2.325 70h 2.569 A0h 2.813 D0h 3.056 FFh 3.300 18h 2.122 48h 2.366 78h 2.609 A8h 2.853 D8h 3.097 20h 2.163 50h 2.406 80h 2.650 B0h 2.894 E0h 3.138 28h 2.203 58h 2.447 88h 2.691 B8h 2.934 E8h 3.178 Contrast Control (2) (2BH) This instruction updates the contrast control value in partial display mode 1. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Contrast control value (0 to 255) The relation between V1 voltage (typ.) and Contrast(2) set value ( 3bit step case) Contrast(1) (HEX) V1[V] Contrast(1) (HEX) V1[V] Contrast(1) (HEX) V1[V] Contrast(1) (HEX) V1[V] Contrast(1) (HEX) V1[V] Contrast(1) (HEX) V1[V] 00h 2.000 30h 2.244 60h 2.488 90h 2.731 C0h 2.975 F0h 3.219 08h 2.041 38h 2.284 68h 2.528 98h 2.772 C8h 3.016 F8h 3.259 10h 2.081 40h 2.325 70h 2.569 A0h 2.813 D0h 3.056 FFh 3.300 18h 2.122 48h 2.366 78h 2.609 A8h 2.853 D8h 3.097 20h 2.163 50h 2.406 80h 2.650 B0h 2.894 E0h 3.138 28h 2.203 58h 2.447 88h 2.691 B8h 2.934 E8h 3.178

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Standby Mode OFF (2CH) This instruction releases the standby mode. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 The internal statuses during standby off are as following: All common and segment output: refer to following Oscillator circuit: On (EXT = 0, OSC=1),OFF (others) Displaying clocks (FR, PM, CL, CK): In operation Function and Pin condition at standby OFF Function/Pin Condition DC/DC booster(1’ st,2’ nd,3’ rd) ON(Operate) COM outputs +VR /VM / VSS /–VR SEG outputs V1 /VSS Standby Mode ON (2DH) This instruction enters the standby mode to reduce the power consumption to the static power consumption value (Initial status). The following instructions, standby off and display on, cause returning to the normal operation status. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 The internal statuses during standby on are as following: All common and segment output: refer to following table Oscillator circuit: OFF Displaying clocks (FR, PM, CL, CK) are held. Function and Pin condition at standby ON Function/Pin Condition DC/DC booster(1’ st,2’ nd,3’ rd) OFF SEG and COM outputs VSS LCD driving power output condition at Standby ON. Level Condition +VR VSS VSS VM VSS -VR VSS

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Addressing Mode Set (30H) D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 GSM DSG SGF SGP SGM GSM: Gray Scale Mode 0 : 4,096 Color mode(Initial status) 1 : 256 Color mode 1. 8 bit mode : DB[7:0] :RRRGGGBB 2.16bit mode: DB[15:0] :RRRGGGBBRRRGGGBB 3. 3bits of R and G, 2bits of B are expanded to 4 bit internally by red, green and blue palette set instruction DSG : Duty Adjust Setting 0 : Dummy subgroup is one subgroup (Initial status) 1 : Dummy subgroup is none SGF : SG Frame Inversion mode setting 0: SG Frame inversion OFF (Initial status) 1: SG Frame inversion ON SGM : SG inversion mode setting 0: SG inversion OFF (Initial status) 1: SG inversion ON SGP : SG Phase mode setting 00 : Same phase in all pixels 01 : Different phase by 1pixel-unit 10 : Different phase by 2pixel-unit 11 : Different phase by 4pixel-unit Row Vector Mode Set (32H) Setting ROW function. D/I WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 INC VEC INC: Row Vector Increment Mode. This Parameter set up Row vector increment period DB3 DB2 DB1 Row Vector Increment Period Every subgroup Every 2subgroup Every 4subgroup Every 8subgroup Every 16subgroup Every 16subgroup Every 16subgroup Every subframe VEC: ROW Vector Sequence Mode - 0: R1->R2->R3->R4 -> R1….. (initial status)

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD N-block inversion Set (34H) This instruction set up N block inversion for AC driving. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 FIM FIP N-block inversion FIM: Forcing Inversion Mode FIM = 0: Forcing Inversion OFF (Initial status) FIM = 1: Forcing Inversion ON FIP: Forcing Inversion Period FIP = 0: Forcing Inversion Period is one frame FIP = 1: Forcing Inversion Period is two frames N-block Inversion : This parameter indicates the basic period of polarity inversion. The whole period of polarity inversion is decided by FIM, FIP and this parameter. DB7 DB6 DB5 DB4 – DB0 Polarity Inversion Period X x x every frame x x every 1 block x x every 31 blocks x every 1 block and every frame x every 31 blocks and every frame x every 1 block and every 2 frames x every 31 blcks and every 2 frames

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Red palette Set (38H) Setting red gray scale data for 256 Color mode. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RAM data “000” to GS data RAM data “001” to GS data RAM data “010” to GS data RAM data “011” to GS data RAM data “100” to GS data RAM data “101” to GS data RAM data “110” to GS data RAM data “111” to GS data Green palette Set (3AH) Setting green gray scale data for 256 Color mode. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RAM data “000” to GS data RAM data “001” to GS data RAM data “010” to GS data RAM data “011” to GS data RAM data “100” to GS data RAM data “101” to GS data RAM data “110” to GS data RAM data “111” to GS data Blue palette Set (3CH) Setting blue gray scale data for 256 Color mode. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RAM data “000” to GS data RAM data “001” to GS data RAM data “010” to GS data RAM data “011” to GS data

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Entry Mode Set (40H) Setting internal function mode. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 HL X/Y RMW HL: Exchange higher and lower byte only for “ Display Data Write/Read” in 256 color & 16-bit data bus . HL = 0 : Exchange status(initial status) HL = 1 : Not exchange status X/Y: Memory address counter mode setting X/Y = 0: Y address counter mode (Initial status) X/Y = 1: X address counter mode (Don’ t use in 256 color & 16bit data bus mode) RMW: Read modify write mode ON/OFF select RMW = 0: Read modify write OFF (Initial status) RMW = 1: Read modify write ON. When this mode is on, X(Y) address of on-chip display RAM is increment not in reading display data but in writing display data. X Address Area Set (42H) This instruction and parameter set up the X address areas of the on-chip display data RAM. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X start address set (Initial Status = 00H) X end address set (Initial Status = 7FH) The current X address of the on-chip display data RAM is the X start address by setting this instruction. In X address count mode (X/Y = “ H” ), the X address is increased from X start address to X end address. When X address is equal to the X end address, the Y address is increased by 1 and the X address returns to X start address. The X start and X end addresses must be set as a pair and X start address must be less than X end address. Address Area Set (43H) This instruction and parameter set up the Y address areas of the on-chip display data RAM. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Y start address set (Initial Status = 00H) Y end address set (Initial Status = 7FH) The current Y address of the on-chip display data RAM is the Y start address by setting this instruction. In Y address count mode (X/Y = “ L” ), the Y address is increased from Y start address to Y end address. When Y address is equal to the Y end address, the X address is increased by 1 and the Y address returns to Y start address. The Y start and Y end address must be set as a pair and Y start address must be less than Y end address.

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Display OFF (50H) Turn the display OFF(Initial status). When display is off, all segment and common output are VSS level. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function and Pin condition at Display OFF Function/Pin Condition DC/DC booster(1st,2nd,3rd) ON(Operate) SEG and COM outputs VSS Display ON (51H) Turns the display ON. In case of being standby mode, this instruction does not work. This instruction is executed after standby mode off. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function and Pin condition at Display ON Function/Pin Condition DC/DC booster(1st,2nd,3rd) ON(Operate) COM outputs +VR /VM /-VR SEG outputs V1 /VSS Specified Display Pattern Set (53H) This instruction sets the specified display pattern. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SDP SDP : Specified Display Pattern set - SDP = 00 : Normal display - SDP = 01 : Reverse display : Display data reversing mode setting without the contents of the display RAM SDP = 10 : Whole display pattern becomes OFF regardless of the RAM data. SDP = 11 : Whole display pattern becomes ON regardless of the RAM data.

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial Display Mode Set (55H) D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PDM PT PT: Partial Display ON/OFF PT = 0: Partial display OFF = Normal mode (Initial status) PT = 1: Partial display ON PDM: Partial Display mode set PDM = 0: Partial mode 0 : Duty ratio is same as Normal display mode(initial status) PDM = 1: Partial mode 1 : Duty ratio is changed from Normal display mode(66 duty fixed) Applied parameter in PDM0 and PDM1 are summarized as below PDM Contrast Duty Bias DC-DC Select OSC PCK Contrast control(1) Normal Bias(1) DC-DC(1),DC(1) OSC1-OSC2 DIV(1) Contrast control(1) Bias(2) DC-DC(1),DC(2) OSC3-OSC4 DIV(2) Operation in Partial Display Mode 0 (PDM=0) On scanning except partial display area -SEG output select V0 or V1 level depend on “ FR” value. Refer to 44 -All of COM output is fixed VM level. On scanning partial display area -It is equal to be in normal mode Operation in Partial Display Mode 1 (PDM=1) Display area is from partial start line to partial end line. (COM driver output is fixed VM except display area, only max66 line output COM signal. On scanning except partial display area -SEG output select V0 or V1 level depend on “ FR” value. Refer to Page44 -All of COM output is fixed VM level. On scanning partial display area -It is equal to be in normal mode Display Area Partial Start Line Partial End Line N line PDM 0 Partial Start Line M line Max. 66 line PDM 1 No display Area : No COM Scanning field (COM = Vm fixed) Except Partial Display Area : COM Timing is existing, but COM = Vm fixed Partial Display Area : Real display field Partial End Line

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial Display Mode0 Item Partial Display Area Out of Partial Display Area Duty Same as normal display mode Contrast Same as normal display mode ( Contrast(1) setting ) Oscillator Same as normal display mode ( OSC1 – OSC2 ) SEG Output level Same as normal mode (V1,V0) Depends on Internal “ FR” signal See page 44 COM Output level Same as normal mode (+VR,VM,-VR) VM fixed <COM0-2> In case of COM 6 to COM11 Partial display <COM3-5> <COM6-8> <COM9-11> <COM12-14> Normal Display Mode Partial Display Mode 0 +VR VM -VR

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial display mode1 Item Partial Display Area Out of Partial Display Area Out of Display Area Duty 1/66duty Contrast Contrast(2) setting Oscillator ( OSC3 – OSC4 ) setting value SEG Output level Same as normal mode (V1,V0) Depends on “ FR” signal See page 44 COM Output level Same as normal mode (+VR, VM, -VR) VM fixed VM fixed <COM0-2> In case of COM 6 to COM11 Partial display <COM3-5> <COM6-8> <COM9-11> <COM12-14> Normal Display Mode Partial Display Mode 1 +VR VM -VR

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Partial Display Start Line Set (56H), Partial Display End Line Set(57H) These 2 instructions set the partial display area and it is possible to display a part. Partial Display Start Line Set (56H) D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Partial start line Partial Display End Line Set (57H) D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Partial end line Parameter set appoints display line number. At PDM 0, Parameter Size is able to be in a number of Display lines. But that is not able to be over max 66 line at PDM 1. Partial end line must set bigger number than Partial start line. line 0 line 1 COM 0 COM 1 line 2 line 3 COM 2 COM 3 line 126 line 127 COM 126 line 128 COM 127 COM 128

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Example of Segment Voltage in non-display area COM Partial Display VM Subframe +VR VM -VR Addressing Duty Display Off internal polarity counter (FR) VM VM VM N N+1 SEG Frame

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Area scroll Set (59H) This instruction sets up area scroll field (start line, end line, Lower fixed line number), and it is possible to make screen to display as partial scroll field. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SCM Scroll area start line Scroll area end line Lower fixed number Note: In lower and center scroll mode, scroll area end line must be smaller than duty - lower fixed number. SCM: Scroll mode setting DB1 DB0 Mode Entire display(Initial status) Upper scroll display Lower scroll display Center scroll display Entire Display Upper Display Lower Display Center Display

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Scroll Start Line Set (5AH) This instruction and parameter set up scroll start line. On this instruction, scroll start line becomes the first of area scroll field. Scroll operation is occurred every issue of this instruction. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Scroll start line <Example> -SCM : 2’ b11 (Center display mode) -Scroll area start line : 6 -Scroll area end line : 119 -Lower fixed number : 8 -Scroll start line : 40 Upper fIx <DUTY BLOCK> <RAM BLOCK> COM6 COM127 COM0 Scroll area Upper fix Scroll display Lower fix <DISPLAY> Xadr=6 Xadr=0 Xadr=120 Xadr=127 RAM Address. COM120 COM0 COM6 COM120 Lower fix Addr0 Addr5 Addr40 Addr120 Addr127 Addr119 Addr6 Addr39 Xadr=40 COM127

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Data Format Select (60H/61H) D/I WRB RDB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DFS DFS: 4,096 Color Mode Data Format Select - 0 : 4,096 Color Data Format A (Initial Status) 8 bit mode : DB[7:0] : XXXXRRRR (1’ st write) DB[7:0] : GGGGBBBB(2’ nd write) 16 bit mode : DB[15:0] :XXXXRRRRGGGGBBBB (12 bit) - 1 : 4,096 Color Data Format B 8 bit mode : DB[7:0] : RRRRGGGG(1’ st write) DB[7:0] : BBBBRRRR (2’ nd write) DB[7:0] : GGGGBBBB(3’ rd write) 16 bit mode : DB[15:0] :RRRRGGGGBBBBXXXX (12 bit) Normal Mode Normal Mode Partial Mode 0 Scroll Mode Scroll/Partial Mode 0 Set partial start line Set partial end line Set partial mode 0 Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line no. Set scroll start line Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line Set scroll start line Set partial start line Set partial end line Set partial mode 0 Release partial mode Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line no. Set scroll start line Set scroll mode Set scroll area start line Set scroll area end line Set lower fixed line no. Set scroll start line Release partial mode

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Display Data Write/Read D/I /WR /RD DB15 ~ DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display RAM write in data Display RAM read out data 1. 4,096 Color mode (1) 16bit access mode 1st cycle X X X X 2nd cycle X X X X (2) 8bit access mode 1st cycle X X X X 2nd cycle 3rd cycle X X X X 4th cycle 2. 256 color mode (1) 16bit access mode 1st cycle (3) 8bit access mode 1st cycle Status Read D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BSY X/Y PDM PT STB REV DP This instruction indicates the internal status of the S6B33A2. DP: ( 0 : Display OFF Status, 1 : Display ON Status ) REV: ( 0 : Display Image Non-Reversing, 1 : Display Image Reversing ) STB: ( 0 : Standby Mode OFF Status, 1 : Standby Mode ON Status ) PT: ( 0 : Partial Display Mode OFF Status, 1 : Partial Display Mode ON Status ) PDM: ( 0 : Partial Display Mode 0, 1 : Partial Display Mode 1 ) X/Y: ( 0 : Y-address Count Mode, 1 : X-address Count Mode ) BSY: ( 0 : No Busy, 1 : Busy )

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Set Display Data Length This Instruction is only used in 3-pin SPI MPU interface mode(PS=” L” , MPU[1]=” L” ). It consists of two continuous commands, the first byte control the data direction(write mode only) and inform the LCD driver the second and third bytes will be number of data bytes will be write. When DI is not used, the Display Data Length instruction is used to indicate that a specified number of display data bytes are to be transmitted. The next byte after the display data string is handled as command data. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Number of display data upper 8bits (DDL_H) Number of display data lower 8bits (DDL_L) Test Mode1 (FFH) This Instruction is for testing IC. User is not permitted to access. If access ,have to reset. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Test Mode2 (FEH) This Instruction is for testing IC. User is not permitted to access. If access ,have to reset. D/I /WR /RD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Table 16. Instruction Parameter

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Number of display data upper word Set Display Data Length FCH Number of display data lower word SDP Specified Display Pattern Set 53H PDM PT Partial Display Mode Set 55H Partial start line Partial Display Start Line Set 56H Partial end line Partial Display End Line Set 57H SCM Scroll area start line Scroll area end line Lower Fixed number Area Scroll Mode Set 59H Scroll start line Scroll Start Line Set 5AH

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD Reset Operation When /RST becomes “ L” , following procedure is occurred. - X address: 0 - Y address: 0 - Display OFF - Read Modify Write Mode OFF - Function Mode Set OSC = 0: Oscillator OFF EXT = 0: Internal Oscillator Mode REV = 0: Reversing mode OFF X/Y = 0: Y-address Count Mode HL = 0 Standby Mode ON - PCK Generation mode Set DIV(1) = 10: fPCK = fOSC/6x DIV(2) = 10: fPCK = fOSC/6x - DC-DC Select DC(1) = 0: X1 step-up DC(2) = 0: X1 step-up - DC/DC and AMP ON/OFF Set AMP =0: Built-in OP-AMP OFF DCDC1 =0: Built-in 1st booster OFF DCDC2 =0: Built-in 2nd booster OFF DCDC3 =0: Built-in 3rd booster OFF - N-block inversion FIM =0: Forcing Inversion OFF FIP =0: Forcing Inversion Period in one frame N-block inversion = 00H: frame inversion - Partial Display Mode PT = 0: Partial Display Mode OFF PDM = 0: Partial Mode 0 - Partial Display Area Set Partial start line = 00H Partial end line = 00H -Area Scroll Set Mode = 00H : Entire Display Scroll Mode Area Start Line: 00H Area End Line: 7FH Lower Fixed Line Number: 00H - Scroll Start Line Set Scroll Start Line: 00H - Addressing Mode Set GSM =0: 4,096 color mode DSG = 0: Mode 0 SGF = 0: SG Frame Inversion OFF SGM = 0: SG Reverse Mode OFF SGP=00:Same phase in all pixel

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Unit Supply Voltage range VDD -0.3 to +4.0 V LCD Supply Voltage range |VCC – VEE| V Input Voltage range Vin - 0.3 to VDD +0.3 V Operating Temperature range TOPR -30 to +70 Storage Temperature range TSTR -55 to +150 OPERATING VOLTAGE Item Symbol Min. Typ. Max. Unit Supply Voltage (1) VDD 1.8 3.3 V Supply Voltage (2) 2Vr V Supply Voltage (3) VIN 2.4 3.0 3.6 V

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (1) (Vss = 0V, VDD = 1.8 to 3.3V, Ta = -30 to 70 °C) Item Symbol Condition Min Typ Max Unit Remarks Operating voltage VDD 1.8 3.3 V VDD Operating voltage VIN1 2.4 3.6 V VCI Operating voltage DC2IN 1.66 2.75 V DC2IN Operating voltage VIN2 2.4 5.4 V VIN2 Operating voltage VIN45 2.4 5.4 V VIN45 Operating voltage 2Vr 2Vr = |(+VR)- (-VR)| 4.0 V +VR, -VR VM 1.0 1.65 V VM VCC 7.0 11.55 V VCC Driving voltage input range VEE External power supply mode -8.25 -5.0 V VEE High VIH 0.8VDD VDD Input voltage Low VIL VSS 0.2VDD V High VOH IOH = 0.5mA 0.8VDD VDD Output voltage Low VOL IOL = 0.5mA VSS 0.2VDD V Input leakage current IIL VIN = VDD or VSS -1.0 +1.0 µA Output leakage current IOZ VIN = VDD or VSS -3.0 +3.0 µA Normal or Partial 0 FOSC1 R1=? (fFR=80Hz target), DSG=0, 128 display lines 50.688 56.32 61.952 kHz OSC1 - OSC2 Oscillator Frequency Tolerance Partial 1 FOSC2 R1=? (fFR=80Hz target), DSG=0, 66 display lines 26.496 29.44 32.384 kHz OSC3 - OSC4 Normal or Partial 0 FOSC1 (*1) 35.200 70.400 kHz OSC1 - OSC2 Oscillator Frequency Range Partial 1 FOSC2 (*2) 18.400 36.800 kHz OSC3 - OSC4 Driving voltage input range VM 2.0 1.0 3.3 1.65 V (*1) Minimum oscillator frequency range is defined at fFR=50Hz and display line number=128 Maximum oscillator frequency range is defined at fFR=100Hz and display line number=128 (*2) Minimum oscillator frequency range is defined at fFR=50Hz and display line number=66 Maximum oscillator frequency range is defined at fFR=100Hz and display line number=66

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (2) (Vss = 0V, VDD = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 °C) Item Symbol Condition Min Typ Max Unit Remarks SEG RON-Seg V1=3.3 V, VM=1.65V, V0=0V, Ta = 25°C, Iload=100uA 1.5 3.0 kΩ SEGn Driver output resistance COM RON-Com VCC=12 V, VM=1.5V, VEE=-9.0V, Ta = 25°C, Iload=100uA 1.0 1.5 kΩ COMn VDD=3V VIN1=3.0V, V1=3.3V, Bias(1)=1/6, DC(1)=x1.5, Ta=25°C, Display line=128 DSG=0 (1dummy) fOSC1=49.3kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern 400 µΑ VDD=1.8V Normal Mode IDD1 VIN1=3.0V, V1=3.3V, Bias(1)=1/6, DC(1)=x1.5, Ta=25°C, Display line=128 DSG=0 (1dummy) fOSC1=49.3kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern 270 µΑ VDD=3V VIN1=3.0V, V1=3.3V, Bias(2)=1/6, DC(2)=x1.5, Ta=25°C, Display line=66 DSG=0 (1dummy) fOSC1=25.8kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern 240 µΑ VDD=1.8V Current consumption Partial1 Mode IDD2 VIN1=3.0V, V1=3.3V, Bias(2)=1/6, DC(2)=x1.5, Ta=25°C, Display line=66 DSG=0 (1dummy) fOSC1=25.8kHz (fFR=70Hz) Low current mode, No load, No access, All white pattern 180 µΑ VDD * : “ IDD1 and IDD2” are determined from lowest power consumption for dc-dc converter.

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (3) (Vss = 0V, VDD = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 °C) Item Symbol Condition Min Typ Max Unit Remarks Low current mode Isource = 80uA ∆ (+VR) High current mode Isource = 150 or 250uA 100 mV +VR Low current mode Isource = 250uA ∆ (V1) High current mode Isource = 500 or 1000uA mV Low current mode Isource,sink = 250uA ∆ (VM) High current mode Isource,sink = 500 or 1000uA mV VM Low current mode Isink = 80uA Voltage shift range(*1) ∆ (-VR) High current mode Isink = 150 or 250uA 100 mV -VR (*1) Voltage shift means output voltage deference between output current = Iload and no-load. Refer to the following figure. (in case of source current mode) Item Symbol Condition Min Typ Max Unit Remarks Tolerance of Bias ratio ∆ (+VR)_0 ∆ (-VR)_0(*1) No load -100 +100 mV +VR -VR (*1) Tolerance of bias ratio definition No-load Vx Vx Vy Vy I=0 I=ILoad Vshift = |Vx-Vy| Current = I Load

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (4) (Vss = 0V, VDD = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 °C) Item Symbol Condition Min Typ Max Unit Remarks Temperature compensation ∆Vt VDD=VIN1=V1=3.0V, -20 to 70 °C -0.02 +0.02 %/°C Tolerance of Contrast step of V1 ∆Vstep 2.539 5.078 7.617 mV 3.25 3.3 3.35 V Contrast set = FFh VM 1.60 1.65 1.70 V VM 1.95 2.00 2.05 V Voltage range ∆V1 ∆VM Contrast set = 00h VM 0.95 1.00 1.05 V VM Condition Item Load current Voltage range Max Unit Ref I Load = +100uA (+VR) I Load = -100uA (-VR) 100 mV Fig.1 A I Load = +100uA ( V1, VM ) Offset Voltage B I Load = +100uA (+VR) I Load = -100uA (-VR) +VR=7.0~11.55 V V1=2.0~3.3V VM=1.0~1.65V -VR=-8.25~-5 V mV Fig.2 +VR Fig. 1: Offset voltage definition (+VR,VM,-VR) Vx |Vx-Vy| < 100mV VM -VR Vy +100uA -100uA Va |Va-Vb| < 50mV VM Vb +100uA (both Case A and B) -100uA (Case B) +100uA (Case A) Fig. 2: Offset voltage definition (V1,VM,V0)

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD DC CHARACTERISTICS (5) (Vss = 0V, VDD = 1.8 to 3.3V, VIN1=2.4 to 3.6V, Ta = -30 to 70 °C) Range Item Min Max (DC(1) and DC(2) = X1.5) V1OUT 2.0 V

3.3 V(*1)

1.0 V

1.65 V(*2)

1.67 V

2.75 V(*3)

If V1OUT input voltage is set over VIN45, V1OUT output voltage must be clipped near VIN45. In this case, V1OUT output level must not be unstable. Refer to Fig.1 V1OUT VIN45 Δ V > 0.3 V (External VIN45) Δ V (*1) This definition is shown as below VIN45 V1OUT Output VIN45 VIN45 - Δ V Fig. 1 V1OUT Input Δ V > 0.5 V (VIN45 = VOUT45) If VMOUT input voltage is set over VIN1, VMOUT output voltage must be clipped near VIN1. In this case, VMOUT output level must not be unstable. Refer to Fig.2 VMOUT VIN1 Δ V > 0.3 V Δ V (*2) This definition is shown as below VIN1 VMOUT Output VIN1 VIN1 - Δ V Fig. 2 VMOUT Input If DC2OUT input voltage is set over VIN2, DC2OUT output voltage must be clipped near VIN2. In this case, VMOUT output level must not be unstable. Refer to Fig.3 DC2OUT VIN2 Δ V > 0.3 V (External VIN2) Δ V (*3) This definition is shown as below VIN2 DC2OUT Output VIN2 VIN2 - Δ V DC2OUT Input Δ V > 0.5 V (VIN2 = VOUT45) Fig.3

Figure 27. Parallel Interface (8080-series MPU) Timing Diagram Table 17. AC Characteristics (8080-series Parallel Mode) NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 10 ns or less.

Figure 28. Parallel Interface (6800-series MPU) Timing Diagram Table 18. AC Characteristics (6800-series Parallel Mode) NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 10 ns or less.

Table 19. Serial Data Interface Timing

Figure 29. Reset Input Timing Diagram Table 20. AC Characteristics (Reset mode)

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD SYSTEM APPLICATION DIAGRAM Internal Power Mode External Components Name Device R1,R2 Resistors C1,C2,C3 Capacitors Schottky barrier diode Values of external Capacitors and D1 Item Capacitance 1.0 to 4.7µF 1.0 to 2.2µF 1.0 to 2.2µF Vforward = Max. 0.3V at 1mA Vreverse = Min. 15V Maximum rating voltage of capacitors Item Maximum rating voltage REG_OUT to VSS VOUT45 to VSS C11P to C11M C12P to C12M VMOUT to VSS DC2OUT to VSS V1OUT to VSS C21P to C21M C22P to C22M 10V C23P to C23M 13V VSS to VRN 13V C31P to C31M 17V VRP to VSS 18V S6B33A2 OSC1 OSC2 OSC3 OSC4 OSC5 /WR /RD DB15DB0 D/I /CS1 /WR /RD DB15 to DB0 MPU CS2 D/I /CS1 CS2 C11P C11M C12P C12M VOUT45 VIN45 VIN1 VIN1 VDD VDD1 REG_OUT VDD or REG_OUT C21P C21M C22P C22M C23M VRN VEE VIN2 VIN2 DC2OUT DC2IN V1OUT V1IN VMOUT VMIN C31P C31M VRP VCC C23P V0IN VSS

S6B33A2 PRELIMINARY VER 1.3 128 RGB SEGMENT & 129 COMMON DRIVER FOR 4,096 COLOR STN LCD External Power Mode S6B33A2 OSC1 OSC2 OSC3 OSC4 OSC5 /WR /RD DB15 to DB0 D/I /CS1 /WR /RD DB15 to DB0 MPU CS2 D/I /CS1 CS2 C11P C11M C12P C12M VDD VDD1 REG_OUT VDD or REG_OUT C VOUT45 VIN45 VIN1 VIN1 C21P C21M C22P C22M C23P C23M VRN VEE VIN2 VIN2 DC2OUT DC2IN V1OUT V1IN VMOUT VMIN C31P C31M VRP VCC V1IN VMIN VEE VCC V0IN VSS