S6B2104 SAMSUNG | Alldatasheet

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80CH SEGMENT DRIVE R FOR DOT MATRIX LCD S6B2104 INTRODUCTION The S6B2104 is a LCD driver IC , which is fabricated by low power CMOS high voltage process technology. This device consists of 80 - bit bi - directional shift register, 80 - bit data latch and 80 bit driver. FE ATURES

  • Power supply voltage: +5V ± 10%, +3V ± 10%
  • Supply voltage for display: 6 to 28V (VDD - VEE)
  • Parallel data processing (4 bit)
  • Applicable LCD duty: 1/64 to 1/256
  • Interface Drivers COM SEG (cascade) S6B0086 Other S6B2104
  • High voltage CMOS process
  • 100 QFP or bare chip available

S6B2104 80CH SEGMEN T DRIVER FOR DOT MAT RIX LCD BLOCK DIAGRAM 80 bit 4- Level Driver 80 bit Level Shifter 80 bit Data Latch 20 x 4 bit Bidirectional Register Power Down Function S78 S79 S80 VEE M DISPOFFB CL1 CL2 EIB VDD VSS EOB SHL Shift CL

80CH SEGMENT DRIVE R FOR DOT MATRIX LCD S6B2104 PIN CONFIGURATION S6B2104 100 SC31 SC32 SC33 SC34 SC35 SC36 SC37 SC38 SC39 SC40 SC41 SC42 SC43 SC44 SC45 SC46 SC47 SC48 SC49 SC50 EIB CL1 NC CL2 VSS SHL VDD DISPOFFB M NC VEE NC EOB SC30 SC29 SC28 SC27 SC26 SC25 SC24 SC23 SC22 SC21 SC20 SC19 SC18 SC17 SC16 SC15 SC14 SC13 SC12 SC11 SC10 SC51 SC52 SC53 SC54 SC55 SC56 SC57 SC58 SC59 SC60 SC61 SC62 SC63 SC64 SC65 SC66 SC67 SC68 SC69 SC70 SC71 SC72 SC73 SC74 SC75 SC76 SC77 SC78 SC79 SC80

S6B2104 80CH SEGMEN T DRIVER FOR DOT MAT RIX LCD MAXIMUM ABSOLUTE LIM IT Characteristic Symbol Value Unit Operating voltage V DD - 0.3 - 6.0 V Driver sup ply voltage V LCD 0 - 30 Input voltage V IN - 0.3 - VDD +0.3 Operating temperature T OPR - 30 - +85 °C Storage temperature T STG - 55 - +150 Voltage greater than above may result in damage to the circuit. S6B2104 VDD (V1) VEE S1 - S80To LCD Panel VSS VDD-VEE +V V1 > V3 > V4 > VEE V1 < VDD-V

80CH SEGMENT DRIVE R FOR DOT MATRIX LCD S6B2104 ELECTRICAL CHARACTER ISTICS DC Characteristics (VDD = 2.7 to 5.5V, VSS = 0V, Ta = - 30 to +85 °C, C L = 15pF) Characteristics Symbol Condition Min Typ Max Unit Operating voltage V DD - 2.7 - 5.5 V Driver supply volta ge V LCD V LCD = VDD - VEE 6 - 28 Input voltage (1) V IH - 0.8VDD - - V IL - 0 - 0.2VDD Output voltage (2) V OH IOH = - 0.4mA VDD - 0.4 - - V V OL IOL = 0.4mA - - 0.4 Input leakage current 1 (1) IIL1 V IN = VDD to VSS - 1 - 1 µA Input leakage current 2 ( 3) IIL2 V IN = VDD to VEE - 25 - 25 On resistance (4) R ON ION = 100 µA - 2 4 k Ω Supply current ISTB fCL2 = 1MHz, VDD = 5.5V (5) - - 200 µA IDD fCL2 = 19.2kHz, VDD = 5.5V (6) - - 3 mA fM = 40Hz, VLCD = 26V VDD = 2.7V (6) - - 1 mA IEE No Load VDD = 5.5V (7) - 150 500 µA NOTES: 1. Applied to CL1, CL2, EIB, EOB, D0 to D3, SHL, DISPOFFB, M pin. 2. EIB, EOB pin 3. V1, V3, V4 pin 4. VDD - VEE = 26V(VDD = 3V), VEE = 28V(VDD = 5V), V1 = VDD, V3 = VDD - 2/10(VDD - VEE), V4 = VEE+2/10( VDD - VEE), S1 to S80 pin 5. Display data pattern: 0000, Current from VDD to VSS when the display data is not processing (SHL = VSS, D0 to D3 = VSS, DISPOFFB = VDD, M = VSS) 6. Display data pattern: 1010, Current from VDD to VSS when the display data is processing 7. Display data pattern: 1010, Current on VEE pin

S6B2104 80CH SEGMEN T DRIVER FOR DOT MAT RIX LCD AC Characteristics (VDD = +5V ± 10%, VSS = 0V, Ta = - 30 to +85 °C, C L = 15pF) Characteristic Symbol Condition Min Typ Max Unit Clock cycle time tCYC Duty = 50% 125 - - ns Clock pulse width tW - 45 - - Clock rise/fall time tR /t F - - - 30 Data set - up time tDS - 30 - - Data hold time tDH - 30 - - Clock set - up time1 T CS1 - 80 - - Clock set - up time2 T CS2 - 10 - - Clock hold time tCH - 80 - - Propagation delay time tPHL EOB output - - 80 EIB output 80 EIB, EOB set - up time tPSU EOB input 30 - - EIB input 30 (VDD = +3V ± 10%, VSS = 0V, Ta = - 30 to +85 °C, C L = 15pF) Characteristic Symbol Condition Min Typ Max Unit Clock cycle time tCYC Duty = 50% 250 - - ns Clock pulse width tW - 95 - - Clock rise/fall time tR /t F - - - 30 Data set - up time tDS - 50 - - Data hold time tDH - 50 - - Clock set - up time1 T CS1 - 80 Clock set - up time2 tCS2 - 15 - - Clock hold time tCH - 120 - - Propagation delay time tPHL EOB output - - 155 EIB output 155 EIB, EOB set - up time tPSU EOB input 65 - - EIB input 65

80CH SEGMENT DRIVE R FOR DOT MATRIX LCD S6B2104 Timing Chara cteristics tw tw twtF 0.8VDD 0.2VDD 0.2VDD 0.8VDD tDS tDH 0.8VDD 0.2VDD 0.8VDD 0.2VDD tCS1 tw tR tF tCS2 tCH CL2 D0 to D3 CL1 0.2VDD 0.8VDD1 2 19 20 tPHL 0.2VDD tPUS CL2 CL1 EOB, EIB (output) EIB, EOB (input)

Table 1. Pin Description Bias supply voltage terminals to drive the LCD. CL2 (47) I Data shift clock Clock pulse input for the 4 bit parallel shift register. Alternate signal input pin for LCD driving. power - down function block. are described in the table below. (refer to note 3).

80CH SEGMENT DRIVE R FOR DOT MATRIX LCD S6B2104 T able 1. Pin Description (Continued) Pin No I/O Nam e Function Interface E OB ,E IB (31,50) I/O Pin I/O SHL Display data shift d irection Description EOB I L D0: S1 → S5 … → S77 D1: S2 → S6 … → S78 Enable input terminal of S6B2104. EIB O D2: S3 → S7 … → S79 D3: S4 → S8 … → S80 Enab le output terminal of S6B2104. EIB is connected to next S6B2104's EOB when the S6B2104's are connected in series (cascade connection). EIB I H D0: 80 → S76… → S4 D1: 79 → S75… → S3 Enable input terminal of S6B2104. EOB O D2: 78 → S74… → S2 D3: 77 → S73… → S1 Enable output terminal of S6B2104. EOB is connected to next S6B2104's EIB when the S6B2104's are connected in series (cascade connection) D0 - D3 (43 - 46) I EOB I L D D D D D D D D D D D D Shift Direction Last Data First Data Shift S73 S74 S75 S76 S77 S78 S79 S80 EIB O EIB I H D D D D D D D D D D D D Shift Direction Last DataFirst Data Shift S73 S74 S75 S76 S77 S78 S79 S80 EOB O

S6B2104 80CH SEGMEN T DRIVER FOR DOT MAT RIX LCD Display data input Display data input pins for 4 bit parallel shift register and it is input synchronized with the clock pulse. The combination of D0 - D3 level, M signal, display data output level and the display on the LCD panel is described on the table below. (DISPOFFB = H ) L L H L L H H H OFF ON OFF ON VEE D0-D3 M Display on the LCDDisplay Data Output Level Controller NOTES: S6B2104 V1 VDD VDD C C C C C R R R R V 2 (to S6B0103) V 5 (to S6B0103) C VEE VSS S1 - S80 To LCD Panel V1, VEE V3, V4 Selected Level Nonselected Level n = 5 (1/64 duty) to 13 (1/256 duty) M Latched Data DISPOFFB Output level (S1 - S80) L L H V3 L H H V1 H L H V4 H H H VEE X X L V1 X: Don’t care.

80CH SEGMENT DRIVE R FOR DOT MATRIX LCD S6B2104 3. - EOB and EIB pins works as input terminals. EN ABLE F/F stops display data at "H" level input. ENABLE F/F starts display data at "L" level input. - EOB and EIB pins work as output terminals. These terminals are set to the "H" level immediately after ENABLE F/F is initialized by the load pulse. Up on completion of 80 - bit serial/parallel conversion using the shift clock input from the CL2 terminal, these terminals are then set to the "L" level. - The operation of ENABLE F/F is terminated and held unchanged until the next load pulse is detected. (For cascade connection, refer to the application circuit drawing) POWER DOWN FUNCTION In order to reduce the power consumption, in case of cascade connection, S6B2104 has a "power down function". EIB Enable input Enable L Disable H EOB Enab le output EOB of Nth driver is connected to EIB of (N+1)th driver S6B2104 ~~ ~~ 1 2 19 20 1 2 19 20 20 1 2 19 20 CL1 CL2 1st EIB (input) 1st EOB (output) Shift CL2 2nd EIB (input) 2nd EOB (output) Shift CL2 SHL = H (EIB = Input, EOB = Output) First S6B2104’s EOB should be connected to second S6B2104’s EIB.

S6B2104 80CH SEGMEN T DRIVER FOR DOT MAT RIX LCD Timing Chart - 1/200 Duty, 1/15 Bias 200 1 2 200 1 2 200 1 2 CL1 200 H 2 200 1 2 200 1 2 L L HL L HL L Latched Data M M CL1 D0 - D3 CL2 Latched Data CL1 Latched Data M VEE (V6) V2V3 V4V5 V1 = VDD V4 = VDD-8/10V LCD V2 = VDD-1/10V LCD V5 = VDD-9/10V LCD V3 = VDD-2/10V LCD V LCD = VDDVEE VDD (V1)