S6B1713 SAMSUNG | Alldatasheet
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- 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Datasheet sections
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713
S6B1713 Specification Revision History Version Content Date 2.0 Neglect the more past version than version 2.0 Nov.1998 2.1 fOSC = 16kHz (Typ.) → 22kHz (Typ.): For removing flicker phenomenon Temperature coefficient (when TEMPS = L): -0.0%/°C → -0.05%/°C Nov.1998 3.0 Modified some syntax errors Voltage regulator reference voltage [VREF]: TBD → 2.0 Modified voltage regulator block of “Functional Description” Nov.1998 3.1 VLCD absolute maximum rating: 15.0V → 17.0V Power consumption: 100µA → 80µA 3.2 Oscillator frequency (1): 19 (Min.) → 17 (Min.), 25 (Max.) → 27 (Max.) Oscillator frequency (2): 22 (Min.) → 20 (Min.), 28 (Max.) → 30 (Max.) 3.3 Modified Y-axis values of “Pad Center Coordinates” Modified the contents of “Referential Instruction Setup Flow” 3.4 Word-processor version change Apr.1999 3.5 Modified error: pad No.113 (COMS) Y Coordinate: -1210 → -1140 (after) Oct.1999 4.1 Added detail information for several items Mar.2001
S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD INTRODUCTION The S6B1713 is a driver & controller LSI for graphic dot -matrix liquid crystal display systems. It contains 65 commons and 132 segment s driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8-bit parallel display data and stores in an on -chip Display Data RAM of 65 x 1 32 bits. It provides a high -flexible display section due to 1 -to-1 correspondence between on -chip display data RAM bits and LCD panel pixels. And it performs display data RAM read/write operation with no externally operating clock to m inimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
FEATURES
− 65 common outputs / 1 32 segment outputs On-chip Display Data RAM − Capacity: 65 x 132 = 8,580 bits Applicable Duty Ratios Duty ratio Applicable LCD bias Maximum display area 1/65 1/7 or 1/9 65 × 132 1/49 1/6 or 1/8 49 × 132 1/33 1/5 or 1/6 33 × 132 Microprocessor Interface − 8-bit parallel bi-directional interface with 6800-series or 8080-series − Serial interface (only write operation) available Function Set − Various instructions sets − H/W, S/W reset capable Built-in Analog Circuit − On-chip oscillator circuit − Voltage converter (x2, x3, x4, x5) − Voltage regulator (temperature coefficient: -0.05%/°C, -0.2%/°C) − Voltage follower − Electronic contrast control function (64 steps) Operating Voltage Range − Supply voltage2 (VDD): 2.4 to 5.5 V − LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V Low Power Consumption − 70 µΑ Typ. (VDD = 3V, x 4 boosting, V0 = 1 1V, internal power supply ON) − 10 µΑ Max. (during power save [standby] mode) Package Type − Gold bumped chip or TCP
S6B1713A05-B0CZ 670 µm S6B1713A05-B0CY (VSS connected) -0.05%/°C 470 µm S6B1713A15-B0CZ 670 µm S6B1713A15-B0CY (VDD connected) -0.2%/°C COG 470 µm S6B1713A05-xxX0 670 µm S6B1713A05-xxXN (VSS connected) -0.05%/°C 470 µm S6B1713A15-xxX0 670 µm S6B1713A15-xxXN (VDD connected) -0.2%/°C TCP 470 µm * xx: TCP ordering number
33 COMMON
65 X 132 = 8,580 Bits
132 SEGMENT
Figure 1. Block Diagram
Figure 2. S6B1713 Chip Configuration Table 1. S6B1713 Pad Dimensions **Figure 3. COG Align Key Coordinate Figure 4. ILB Align Key Coordinate (with Gold Bump *)** routing over this area, it can be happened pattern-short through gold bump pattern on ILB Align Key.
Table 2. Pad Center Coordinates
1 DUMMY -4905 -1336 51 VDD -405 -1336 101 BSTS 4095 -1336
2 DUMMY -4815 -1336 52 VDD -315 -1336 102 DCDC5B 4185 -1336
3 FRS -4725 -1336 53 VDD -225 -1336 103 VDD 4275 -1336
4 M -4635 -1336 54 VDD -135 -1336 104 HPM 4365 -1336
5 CL -4545 -1336 55 VDD -45 -1336 105 INTRS 4455 -1336
6 DISP -4455 -1336 56 VDD 45 -1336 106 VSS 4545 -1336
7 VSS -4365 -1336 57 VOUT 135 -1336 107 TEMPS 4635 -1336
8 CS1B -4275 -1336 58 VOUT 225 -1336 108 VDD 4725 -1336
9 CS2 -4185 -1336 59 VOUT 315 -1336 109 DUMMY 4815 -1336
10 VDD -4095 -1336 60 VOUT 405 -1336 110 DUMMY 4905 -1336
11 RESETB -4005 -1336 61 C3+ 495 -1336 111 DUMMY 5271 -1280
12 RS -3915 -1336 62 C3+ 585 -1336 112 DUMMY 5271 -1210
13 VSS -3825 -1336 63 C3+ 675 -1336 113 COMS 5271 -1140
14 RW_WR -3735 -1336 64 C3+ 765 -1336 114 COM1 5271 -1070
15 E_RD -3645 -1336 65 C3- 855 -1336 115 COM2 5271 -1000
16 VDD -3555 -1336 66 C3- 945 -1336 116 COM3 5271 -930
17 DB0 -3465 -1336 67 C3- 1035 -1336 117 COM4 5271 -860
18 DB1 -3375 -1336 68 C3- 1125 -1336 118 COM5 5271 -790
19 DB2 -3285 -1336 69 C1+ 1215 -1336 119 COM6 5271 -720
20 DB3 -3195 -1336 70 C1+ 1305 -1336 120 COM7 5271 -650
21 DB4 -3105 -1336 71 C1+ 1395 -1336 121 COM8 5271 -580
22 DB5 -3015 -1336 72 C1+ 1485 -1336 122 COM9 5271 -510
23 DB6 -2925 -1336 73 C1- 1575 -1336 123 COM10 5271 -440
24 DB7 -2835 -1336 74 C1- 1665 -1336 124 COM11 5271 -370
25 VSS -2745 -1336 75 C1- 1755 -1336 125 COM12 5271 -300
26 VDD -2655 -1336 76 C1- 1845 -1336 126 COM13 5271 -230
27 VDD -2565 -1336 77 C2+ 1935 -1336 127 COM14 5271 -160
28 VDD -2475 -1336 78 C2+ 2025 -1336 128 COM15 5271 -90
29 DUTY0 -2385 -1336 79 C2+ 2115 -1336 129 COM16 5271 -20
30 DUTY1 -2295 -1336 80 C2+ 2205 -1336 130 COM17 5271 50
31 VSS -2205 -1336 81 C2- 2295 -1336 131 COM18 5271 120
32 MS -2115 -1336 82 C2- 2385 -1336 132 COM19 5271 190
33 CLS -2025 -1336 83 C2- 2475 -1336 133 COM20 5271 260
34 VDD -1935 -1336 84 C2- 2565 -1336 134 COM21 5271 330
35 MI -1845 -1336 85 VSS 2655 -1336 135 COM22 5271 400
36 PS -1755 -1336 86 VSS 2745 -1336 136 COM23 5271 470
37 VSS -1665 -1336 87 VR 2835 -1336 137 COM24 5271 540
38 VSS -1575 -1336 88 VR 2925 -1336 138 COM25 5271 610
39 VSS -1485 -1336 89 V0 3015 -1336 139 COM26 5271 680
40 VSS -1395 -1336 90 V0 3105 -1336 140 COM27 5271 750
41 VSS -1305 -1336 91 V1 3195 -1336 141 COM28 5271 820
42 VSS -1215 -1336 92 V1 3285 -1336 142 COM29 5271 890
43 VSS -1125 -1336 93 V2 3375 -1336 143 COM30 5271 960
44 VSS -1035 -1336 94 V2 3465 -1336 144 COM31 5271 1030
45 VSS -945 -1336 95 V3 3555 -1336 145 COM32 5271 1100
46 VSS -855 -1336 96 V3 3645 -1336 146 DUMMY 5271 1170
47 VDD -765 -1336 97 V4 3735 -1336 147 DUMMY 5271 1240
48 VDD -675 -1336 98 V4 3825 -1336 148 DUMMY 4865 1301
49 VDD -585 -1336 99 VSS 3915 -1336 149 DUMMY 4795 1301
50 VDD -495 -1336 100 VSS 4005 -1336 150 DUMMY 4725 1301
Table 2 . Pad Center Coordinates (Continued) [Unit: µm] No. Name X Y No. Name X Y No. Name X Y
151 DUMMY 4655 1301 201 SEG50 1155 1301 251 SEG100 -2345 1301
152 SEG1 4585 1301 202 SEG51 1085 1301 252 SEG101 -2415 1301
153 SEG2 4515 1301 203 SEG52 1015 1301 253 SEG102 -2485 1301
154 SEG3 4445 1301 204 SEG53 945 1301 254 SEG103 -2555 1301
155 SEG4 4375 1301 205 SEG54 875 1301 255 SEG104 -2625 1301
156 SEG5 4305 1301 206 SEG55 805 1301 256 SEG105 -2695 1301
157 SEG6 4235 1301 207 SEG56 735 1301 257 SEG106 -2765 1301
158 SEG7 4165 1301 208 SEG57 665 1301 258 SEG107 -2835 1301
159 SEG8 4095 1301 209 SEG58 595 1301 259 SEG108 -2905 1301
160 SEG9 4025 1301 210 SEG59 525 1301 260 SEG109 -2975 1301
161 SEG10 3955 1301 211 SEG60 455 1301 261 SEG110 -3045 1301
162 SEG11 3885 1301 212 SEG61 385 1301 262 SEG111 -3115 1301
163 SEG12 3815 1301 213 SEG62 315 1301 263 SEG112 -3185 1301
164 SEG13 3745 1301 214 SEG63 245 1301 264 SEG113 -3255 1301
165 SEG14 3675 1301 215 SEG64 175 1301 265 SEG114 -3325 1301
166 SEG15 3605 1301 216 SEG65 105 1301 266 SEG115 -3395 1301
167 SEG16 3535 1301 217 SEG66 35 1301 267 SEG116 -3465 1301
168 SEG17 3465 1301 218 SEG67 -35 1301 268 SEG117 -3535 1301
169 SEG18 3395 1301 219 SEG68 -105 1301 269 SEG118 -3605 1301
170 SEG19 3325 1301 220 SEG69 -175 1301 270 SEG119 -3675 1301
171 SEG20 3255 1301 221 SEG70 -245 1301 271 SEG120 -3745 1301
172 SEG21 3185 1301 222 SEG71 -315 1301 272 SEG121 -3815 1301
173 SEG22 3115 1301 223 SEG72 -385 1301 273 SEG122 -3885 1301
174 SEG23 3045 1301 224 SEG73 -455 1301 274 SEG123 -3955 1301
175 SEG24 2975 1301 225 SEG74 -525 1301 275 SEG124 -4025 1301
176 SEG25 2905 1301 226 SEG75 -595 1301 276 SEG125 -4095 1301
177 SEG26 2835 1301 227 SEG76 -665 1301 277 SEG126 -4165 1301
178 SEG27 2765 1301 228 SEG77 -735 1301 278 SEG127 -4235 1301
179 SEG28 2695 1301 229 SEG78 -805 1301 279 SEG128 -4305 1301
180 SEG29 2625 1301 230 SEG79 -875 1301 280 SEG129 -4375 1301
181 SEG30 2555 1301 231 SEG80 -945 1301 281 SEG130 -4445 1301
182 SEG31 2485 1301 232 SEG81 -1015 1301 282 SEG131 -4515 1301
183 SEG32 2415 1301 233 SEG82 -1085 1301 283 SEG132 -4585 1301
184 SEG33 2345 1301 234 SEG83 -1155 1301 284 DUMMY -4655 1301
185 SEG34 2275 1301 235 SEG84 -1225 1301 285 DUMMY -4725 1301
186 SEG35 2205 1301 236 SEG85 -1295 1301 286 DUMMY -4795 1301
187 SEG36 2135 1301 237 SEG86 -1365 1301 287 DUMMY -4865 1301
188 SEG37 2065 1301 238 SEG87 -1435 1301 288 DUMMY -5271 1240
189 SEG38 1995 1301 239 SEG88 -1505 1301 289 DUMMY -5271 1170
190 SEG39 1925 1301 240 SEG89 -1575 1301 290 COMS -5271 1100
191 SEG40 1855 1301 241 SEG90 -1645 1301 291 COM64 -5271 1030
192 SEG41 1785 1301 242 SEG91 -1715 1301 292 COM63 -5271 960
193 SEG42 1715 1301 243 SEG92 -1785 1301 293 COM62 -5271 890
194 SEG43 1645 1301 244 SEG93 -1855 1301 294 COM61 -5271 820
195 SEG44 1575 1301 245 SEG94 -1925 1301 295 COM60 -5271 750
196 SEG45 1505 1301 246 SEG95 -1995 1301 296 COM59 -5271 680
197 SEG46 1435 1301 247 SEG96 -2065 1301 297 COM58 -5271 610
198 SEG47 1365 1301 248 SEG97 -2135 1301 298 COM57 -5271 540
199 SEG48 1295 1301 249 SEG98 -2205 1301 299 COM56 -5271 470
200 SEG49 1225 1301 250 SEG99 -2275 1301 300 COM55 -5271 400
Table 2. Pad Center Coordinates (Continued)
301 COM54 -5271 330
302 COM53 -5271 260
303 COM52 -5271 190
304 COM51 -5271 120
305 COM50 -5271 50
306 COM49 -5271 -20
307 COM48 -5271 -90
308 COM47 -5271 -160
309 COM46 -5271 -230
310 COM45 -5271 -300
311 COM44 -5271 -370
312 COM43 -5271 -440
313 COM42 -5271 -510
314 COM41 -5271 -580
315 COM40 -5271 -650
316 COM39 -5271 -720
317 COM38 -5271 -790
318 COM37 -5271 -860
319 COM36 -5271 -930
320 COM35 -5271 -1000
321 COM34 -5271 -1070
322 COM33 -5271 -1140
323 DUMMY -5271 -1210
324 DUMMY -5271 -1280
Table 3. Power Supply Pin Description according to the state of LCD Bias. Table 4. LCD Driver Supply Pin Description It is valid only when on-chip resistors are not used (INTRS = “L”).
Table 5. System Control Pin Description The following table depends on the MS status. This pin is used together with the M pin. This pin selects the resistors for adjusting V0 voltage level. − INTRS = "H": use the internal resistors. − INTRS = "L": use the external resistors. V0 voltage is controlled with VR pin and external resistive divider. This pin is valid in master operation.
Table 5. System Control Pin Description (Continued) recommend that BSTS pin should be fixed to “H”.
Table 6. Microprocessor Interface Pin Description When RESETB is “L”, initialization is executed. are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”. Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”. When chip select is non -active, DB0 to DB7 may be high impedance.
Table 6. Microprocessor Interface Pin Description (Continued) the falling edge of the E signal. When /RD is “L”, DB0 to DB7 are in an output status. When chip select is not active, DB0 to DB7 may be high im pedance.
Table 7. LCD Driver Outputs Pin Description The display data and the M signal control the output voltage of segment driver. The internal scanning data and M signal control the output voltage of common driver. The output signals of two pins are same. When not used, these pins should be left open. NOTE: DUMMY - These pins should be opened (floated).
There are CS1B and CS2 pins for Chip Selection. The S6B1713 can interface with an MPU only when CS1B is “L” and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface S6B1713 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 8. Table 8. Parallel / Serial Interface Mode
- The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table10.
Table 9. Microprocessor Selection for Parallel Interface Table 10. Parallel Data Transfer
Description
H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register (instruction)
Figure 7. Serial Interface Timing needs not to check this flag before each instruction, which improves the MPU performance. (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 9. instruction right after the address sets, but can be output at the second read of data. Figure 8. Write Timing
Figure 9. Read Timing
Figure 10. RAM-to-LCD Data Transfer impossible to access to on -chip RAM. can not access Line Address of icons.
independent of page address register. Figure 11. The Relationship between the Column Address and the Segment Outputs OFF instructions without changing the data in the display data RAM.
82 When the initial display
Figure 12. Display Data RAM Map
the voltage converter and display timing generation circuit. Figure 13. VDD vs. fOSC internal timing signal are shown in figure 14. Table 11. Master and Slave Timing Signal Status
Figure 14. 2-frame AC Driving Waveform (Duty ratio = 1/ 65) Instruction specifies the scanning direction of the common output pins . Table 12. The Relationship between Duty Ratio and Common Output
0 COM[1:16] *NC COM[17:32] 1/33 1 COM[32:17] *NC COM[16:1] COMS
0 COM[1:24] *NC COM[25:48] 1/49 1 COM[48:25] *NC COM[24:1] COMS
0 COM[1:64] 1/65 1 COM[64:1] COMS
segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal.
1 SEG3
Figure 15. Segment and Common Timing
Table 13. Recommended Power Supply Combinations
Voltage Regulator Circuits The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in figure 20, it is necessary to be applied internally or externally. For the Eq. 1, we determine V0 by Ra, Rb and V EV. The Ra and Rb are connected internally or externally by INTRS pin. And V EV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is the value selected by instruction, "Set Referen ce Voltage Register", within the range 0 to 63. V REF voltage at Ta = 25°C is shown in table 14-1. Rb Ra (63 - α) 300 Table 14-1. VREF Voltage at Ta = 25 °C TEMPS Temp. coefficient VREF [V] L -0.05% / °C 2.0 H -0.2% / °C 2.0 Table 14-2. Reference Voltage Parameter s (a) SV5 SV4 SV3 SV2 SV1 SV0 Reference voltage p arame ter (a) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 62 1 1 1 1 1 1 63
Figure 20. Internal Voltage Regulator Circuit
V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 15. Internal Rb / Ra Ratio depending on 3 -bit Data (R2 R1 R0) electronic volume registers for each temperature coefficient at Ta = 25 °C. Figure 21. Electronic Volume Level
- LCD driver voltage, V0 = 10V
- 6-bit reference voltage register = (1, 0, 0, 0, 0, 0)
- Maximum current flowing Ra, Rb = 1 uA
The following table shows the range of V0 depending on the above requirements. Table 16. V0 Depending on Electronic Volume Level
between V1 to V4 level and each duty ratio. Table 17. The Relationship between V1 to V4 level and Duty Ratio
Figure 24. When Using some LCD Power Circuits (V/C: O FF, V/R: OFF, V/F: ON) Figure 25. When Not Using any Internal LCD Power Supply Circuits (V/C: O FF, V/R: OFF, V/F: OFF)
S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD RESET CIRCUIT Setting RESETB to “L” or Reset instruction can initialize internal function. When RESETB becomes “L”, following procedure is occurred. Display ON / OFF: OFF Entire display ON / OFF: OFF (normal) ADC select: OFF (normal) Reverse display ON / OFF: OFF (normal) Power control register (VC, VR, VF) = (0, 0, 0) LCD bias ratio: 1/7 (1/65 duty), 1/6 (1/49 duty), 1/5 (1/33 duty) Read-modify-write: OFF SHL select: OFF (normal) Static indicator mode: OFF Static indicator register: (S 1, S0) = (0, 0) Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) When RESET instruction is issued, following procedure is occurred. Read-modify-write: OFF Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) SHL select: 0 Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) While RESETB is “L” or Reset instruction is executed, no instruction except read status can b e accepted. Reset status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used.
Table 18. Instruction Table When EON = 0: normal display. Test instruction 0 0 1 1 1 1 × × × × Don't use this instruction.
an address into the column address register. Display Data cannot be read through the serial interface. continuously write data to the addressed page. Figure 26. Sequence for Writing Display Data Figure 27. Sequence for Reading Display Data
Indicates the internal status of the S6B1713. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY ADC ON / OFF RESETB 0 0 0 0 Flag Description BUSY The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy. ADC Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG132 → SEG1), 1: normal direction (SEG1 → SEG132) ON / OFF Indicates display ON / OFF status 0: display ON, 1: display OFF RESETB Indicates the initialization is in progress by RESETB signal. 0: chip is active, 1: chip is bei ng reset. Display ON / OFF Turns the display ON or OFF RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 1 DON DON = 1: display ON DON = 0: display OFF Initial Display Line Sets the line address of display RAM to determine the Initial Display Line. The RAM display data is displayed at the top row (COM1 when SHL = L, COM64 when SHL = H) of LCD panel. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0 ST5 ST4 ST3 ST2 ST1 ST0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63
The 1st instruction sets reference voltage mode, the 2nd one updates the contents of reference voltage register. After second instruction, reference voltage mode is released. Figure 28. Sequence for Setting the R eference Voltage
Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of th e display RAM to write or read display data. Changing the Page Address doesn't effect to the display status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 P3 P2 P1 P0 P3 P2 P1 P0 Page 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8 Set Column Address Sets the Column Address of display RAM from the microprocessor into the Column Address register. Along with the Column Address, the Column Address defines the address of the display RAM to write or read display data. When the microprocessor read s or writes display data to or from display RAM, column addresses are automatically increased. Set Column Address MSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set Column Address LSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131
S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD ADC Select Changes the relationship between RAM column address and segment driver. The direction of se gment driver output pins can be reversed by software. This makes IC layout flexible in LCD module assembly. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 0 ADC ADC = 0: normal direction (SEG1 → SEG132) ADC = 1: reverse direction (SEG132 → SEG1) Reverse Display ON / OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 1 REV REV RAM bit data = “1” RAM bit data = “0” 0 (normal) LCD pixel is illuminated LCD pixel is not illuminated 1 (reverse) LCD pixel is not illuminated LCD pixel is illuminated Entire Display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of th e display data RAM are held. This instruction has priority over the reverse display ON / OFF instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 0 EON EON = 0: normal display EON = 1: entire display ON Select LCD Bias Selects LCD bias ratio of the voltage required for driving the LCD. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 1 Bias LCD bias Duty ratio DUTY1 DUTY0 Bias = 0 Bias = 1 1/33 0 0 1/5 1/6 1/49 0 1 1/6 1/8 1/65 1 0/1 1/7 1/9
mode is canceled by the reset Modify -read instruction. before the set Modify-read instruction is started. Figure 29. Sequence for Cursor Display
S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD Reset This instruction resets initi al display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply which is initialized by the RESETB pin. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 0 SHL Select COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 SHL × × × × : Don’t care SHL = 0: normal direction (COM1 → COM64) SHL = 1: reverse direction (COM64 → COM1) Power control Selects one of eight power circuit functions by using 3 -bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 VC VR VF VC VR VF Status of internal power supply circuits
1 Internal voltage converter circuit is OFF
Internal voltage converter circuit is ON
1 Internal voltage regulator circuit is OFF
Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON
Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the table 15. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 R2 R1 R0 R2 R1 R0 1 + (Rb / Ra) 0 0 0 1.90 0 0 1 2.19 0 1 0 2.55 0 1 1 3.02 1 0 0 3.61 1 0 1 4.35 1 1 0 5.29 1 1 1 6.48 Set Static Indicator State Consists of two bytes instruction. The first byte instruction (set Static Indicator mode) enables the second byte instruction (set Static Indicator register) to be valid. The first byte sets the static indicator ON / OFF. When it is on, the second byte updates the contents of static indicator register without issuing any other i nstruction and this static indicator state is released after setting the data of indicator register. The 1st Instruction: Set Static Indicator Mode (ON / OFF) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 0 SM SM = 0: static indicator OFF SM = 1: static indicator ON The 2nd Instruction: Set Static Indicator Register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S1 S0 Status of static indicator output 0 0 OFF 0 1 ON (about 1 second blinking) 1 0 ON (about 0.5 second blinking ) 1 1 ON (always ON)
by the display ON and entire display OFF instruction. Figure 30. Power Save Routine
Figure 31. Initializing with the Built-in Power Supply Circuits
Figure 32. Initializing without the Built-in Power Supply Circuits
Figure 33. Data Displaying
Figure 34. Power O FF
Table 19. Absolute Maximum Ratings
- VDD and VLCD are based on VSS = 0V.
- Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied. (VLCD = V0 – VSS)
- If supply voltage exceeds its abso lute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.
Table 20. DC Characteristics
Dynamic Current Consumption (1) when the Built-in Power C ircuit is OFF (At Operate Mode) (Ta = 25 °C) Item Symbol Condition Min. Typ. Max. Unit Pin used Dynamic current consumption (1) IDD1 VDD = 3.0V V0 – VSS = 11.0V 1/65 duty ratio Display pattern OFF - - 20 µΑ *11 Dynamic Current Consumption (2) when the built-in power circuit is ON (At operate mode) (Ta = 25 °C) Item Symbol Condition Min. Typ. Max. Unit Pin used VDD = 3.0V, quad boosting, V0 – VSS = 11.0V, 1/65 duty ratio, Display pattern OFF, Normal power mode - 70 100 µΑ *12 Dynamic current consumption (2) IDD2 VDD = 3.0V, quad boosting, V0 – VSS = 11.0V, 1/65 duty ratio, Display pattern checker, Normal power mode - 95 160 µΑ *12 Current Consumption During Power Save Mode (Ta = 25 °C) Item Symbol Condition Min. Typ. Max. Unit Pin used Sleep mode current IDDS1 VDD = 3.0V During sleep - - 2.0 µA Standby mode current IDDS2 VDD = 3.0V During standby - - 10.0 µA
Table 21. The Relationship between Oscillation Frequency and Frame Frequency assurance during access from the MPU. *2. In case of external power supply is applied. DCDC5B, CLS, CL, M, DISP pins. *4. DB0 to DB7, M, FRS, DISP, CL pins. *6. Applies when the DB [7:0], M, DISP, and CL pins are in high impedance. *7. Resistance value when ± 0.1[mA] is applied during the ON status of the output pin SEGn or COMn. *8. See table 21 for the relationship between oscillation frequency and frame frequency. *10. On-chip reference voltage source of the voltage regulator circuit to adjust V0. *11,12. Applies to the case where the on -chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built -in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors (Ra and Rb) is not included. It does not include the current of the LCD panel capac ity, wiring capacity, etc.
Figure 35. Display Pattern is OFF
Figure 38. Read / Write Characteristics (8080 -series MPU)
S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD (VDD = 2.4 to 3.6V, Ta = -40 to +85°C) Item Signal Symbol Min. Typ. Max. Unit Remark Address setup time Address hold time RS tAS80 tAH80 17 - - ns System cycle time /WR, /RD tCY80 400 - - ns Read tPWL80 (R) 125 - - ns Enable Pulse Low width Write /WR, /RD tPWL80 (W) 55 - - ns Read tPWH80 (R) 245 - - ns Enable Pulse High width Write /WR, /RD tPWH80 (W) 315 - - ns Data setup time Data hold time tDS80 tDH80 13 - - ns Read access time Output disable time DB7 To DB0 tACC80 tOD80 10 - 125 90 ns CL = 100 pF (VDD = 4.5 to 5.5V, Ta = -40 to +85°C) Item Signal Symbol Min. Typ. Max. Unit Remark Address setup time Address hold time RS tAS80 tAH80 10 - - ns System cycle time /WR, /RD tCY80 160 - - ns Read tPWL80 (R) 65 - - ns Enable Pulse Low width Write /WR, /RD tPWL80 (W) 25 - - ns Read tPWH80 (R) 65 - - ns Enable Pulse High width Write /WR, /RD tPWH80 (W) 105 - - ns Data setup time Data hold time tDS80 tDH80 10 - - ns Read access time Output disable time DB7 To DB0 tACC80 tOD80 10 - 65 45 ns CL = 100 pF Note The input signal rising time and falling time (tr, tf) is specified at 15ns or less . Or (tr + tf) < (tCY80 – tPWL80 (W) – tPWH80 (W) ) for write, (tr + tf) < (tCY80 – tPWL80 (R) – tPWH80 (R)) for read
Figure 39. Read / Write Characteristics (6800-series Microprocessor)
S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD (VDD = 2.4 to 3.6V, Ta = -40 to +85°C) Item Signal Symbol Min. Typ. Max. Unit Remark Address setup time Address hold time RS,RW tAS68 tAH68 17 - - ns System cycle time E tCY68 400 - - ns Read tPWL68 (R) 125 - - Enable Pulse Low Width Write E tPWL68 (W) 55 - - ns Read tPWH68 (R) 245 - - Enable Pulse High Width Write E tPWH68 (W) 315 - - ns Data setup time Data hold time tDS68 tDH68 13 - - ns Access time Output disable time DB7 To DB0 tACC68 tOD68 10 - 125 90 ns CL = 100 pF (VDD = 4.5 to 5.5V, Ta = -40 to +85°C) Item Signal Symbol Min. Typ. Max. Unit Remark Address setup time Address hold time RS,RW tAS68 tAH68 10 - - ns System cycle time E tCY68 160 - - ns Read tPWL68 (R) 65 - - Enable Pulse Low Width Write E tPWL68 (W) 25 - - ns Read tPWH68 (R) 65 - - Enable Pulse High Width Write E tPWH68 (W) 105 - - ns Data setup time Data hold time tDS68 tDH68 10 - - ns Access time Output disable time DB7 To DB0 tACC68 tOD68 10 - 65 45 ns CL = 100 pF Note: 1. The input signal rising time and falling time (tr, tf) is specified at 15ns or less . Or (tr + tf) < (tCY68 – tPWL68 (W) – tPWH68 (W) ) for write, (tr + tf) < (tCY68 – tPWL68 (R) – tPWH68 (R)) for read.
Figure 40. Serial Interface Characteristics
Figure 43. Interfacing with 6800 -series (PS = “H”, MI = “H”) Figure 44. Interfacing with 8080 -series (PS = “H”, MI = “L”) Figure 45. Serial Interface (PS = “L”, MI = “H/L”)
Figure 50. SHL = 0, ADC = 0 Figure 51. SHL = 0, ADC = 1 Figure 52. SHL = 1, ADC = 0 Figure 53. SHL = 1, ADC = 1
Figure 58. SHL = 0, ADC = 0 Figure 59. SHL = 1, ADC = 1
Figure 60. 130COM (128COM + 2COMS) ´ 132SEG
Figure 61. TCP Pin Layout