S6B1400X SAMSUNG | Alldatasheet
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- 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
Datasheet sections
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X S6B1400X Specification Revision History Version Content Date 0.0 Initial version 2002.03
S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD INTRODUCTION The S6B1400X is a single-chip driver & controller LSI for graphic dot -matrix liquid crystal display systems. This chip can be connected directly to a microprocessor, accepts serial or 8 -bit parallel display data from the microprocessor, stores the display data in an on-chip display data RAM of 65 x 104 bits and generates a liquid crystal display drive signal independent of the microprocessor . It provides a high -flexible display section due to 1 -to-1 correspondence between on -chip display data RAM bits and LCD panel pixels. It contains 65 common driver circuits and 1 04 segment driver circuits, so that a single chip can drive a 65 x 104 dot display. This chip is able to minimize power consumption because it performs display data RAM read/write operation w ith no external operation clock . In addition, because it contains power supply circuits necessary to drive liquid crystal, which is a display clock oscillator circuit, high performance voltage converter circuit, high -accuracy voltage regulator circuit, low power consumption voltage divider resistors and OP -Amp for liquid crystal driver power voltage, it is possible to make the lowest power consumption display system with the fewest components for high performance portable systems.
FEATURES
Display Driver Output Circuits − 65 common outputs and 104 segment outputs On-chip Display Data RAM − Capacity: 65 x 104 = 6,760 bits − RAM bit data “1”: a dot of display is illuminated − RAM bit data “0”: a dot of display is not illuminated Applicable Duty Ratios Duty ratio Applicable LCD bias Maximum display area 1/65 1/7 or 1/9 65 × 104 1/55 1/6 or 1/8 55 × 104 1/49 1/6 or 1/8 49 × 104 1/33 1/5 or 1/6 33 × 104 Microprocessor Interface − High-speed 8-bit parallel bi-directional interface with 6800-series or 8080-series − SPI (Serial Peripheral Interface) available. (only write operation) Various Function Set − Display ON / OFF, set initial display line, set page address, set column address, read status, write/read display data, select segment driver output, reverse di splay ON / OFF, entire display ON / OFF, select LCD bias, set/reset modify -read, select common driver output, control display power circuit, select internal regulator resistor ratio for VLCD voltage regulation, electronic volume, set static indicator state . − H/W and S/W Reset available − Static drive circuit equipped internally for indicators with 4 flashing mode
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X Built-in Analog Circuit − On-chip oscillator circuit for display clock − High performance voltage converter (with booster ratios of x3 and x4) − High accuracy voltage regulator (temperature coefficient: -0.05 ± 0.03%/°C or external input) − Electronic contrast control function (64 steps) − Vref = 2.1V ± 3% (VLCD voltage adjustment voltage) − High performance voltage follower (V1 to V4 voltage divider resistors and OP-Amp for increasing drive capacity) Operating Voltage Range − Supply voltage (VDD): 2.4 to 3.6 V − Booster input voltage (VCI): VDD to 3.0 V (x4), VDD to 3.6 V (x3) − LCD driving voltage (VLCD): 4.5 to 9.0 V Low Power Consumption − Operating power: 120 µΑ typical (conditions: VDD = 3V, x 3 boosting (VCI = VDD), VLCD = 7.6V, Internal power supply ON, display OFF and normal mode is selected) − Standby power: 10 µΑ maximum (during power save[standby] mode) Operating Temperatures − Wide range of operating temperatures : -40 to 85°C CMOS Process Package Type − Gold bumped chip
33 COMMON
65 X 104 = 6,760 Bits
104 SEGMENT
Figure 1. Block Diagram
Figure 2. S6B1400X Chip Configuration Table 1. S6B1400X Pad Dimensions
S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD COG Align Key Coordinate ILB Align Key Coordinate (with Gold Bump *) 30µm 30µm 30µm (-5295, -830) 30µm 30µm 30µm (5425, 845.05) 30µm30µm30µm 60µm30µm 42µm 108µm 42µm108µm 42µm108µm 42µm 108µm (-5470, 915) (5460, -895) * When des igning C OG pattern, ITO pattern must be prohibited on ILB Align Key, DUMMY pads , TEST pads. If ITO pattern is used for routing over th ese area, it can be happened pattern -short through bumped pattern on these area. TOM (TEG On Main chip) Coordinate The TOM has test items for process evaluation. There are many bumped PADs in this area as like main chip. So when designing COG pattern, ITO pattern must be prohibited on this area (TOM). If ITO pattern is used for routing over this area, it can be happened pattern-short through bumped PAD on TOM. 600µm 220µm (4480,-915) (5080 ,-695)
Table 2. Pad Center Coordinates
1 DUMMY<0> -5020 -870 51 VSS -1088 -870 101 VSS 2412 -870
2 FRS -4950 -870 52 C68 -1018 -870 102 VR 2482 -870
3 FRI -4880 -870 53 VDD -948 -870 103 VSS 2552 -870
4 CL -4810 -870 54 E_RDB -878 -870 104 TESTA0 2622 -870
5 TEST -4740 -870 55 RW_WRB -808 -870 105 TESTB0 2692 -870
6 VDD -4670 -870 56 VSS -738 -870 106 VSS 2762 -870
7 VDD -4600 -870 57 CS1B -668 -870 107 VLCD 2832 -870
8 VDD -4530 -870 58 CS2 -598 -870 108 VLCD 2902 -870
9 VDD -4460 -870 59 VDD -528 -870 109 VLCD 2972 -870
10 VDD -4390 -870 60 VCI -458 -870 110 VLCD 3042 -870
11 VDD -4320 -870 61 VCI -388 -870 111 VLCD 3112 -870
12 VDD -4250 -870 62 VCI -318 -870 112 VLCD 3182 -870
13 VDD -4180 -870 63 VCI -248 -870 113 TESTA1 3252 -870
14 VDD -4110 -870 64 VCI -178 -870 114 TESTB1 3322 -870
15 VDD -4040 -870 65 VCI -108 -870 115 TESTA2 3392 -870
16 VDD -3970 -870 66 VCI -38 -870 116 TESTB2 3462 -870
17 VDD -3900 -870 67 VCI 32 -870 117 TESTA3 3532 -870
18 VCI -3830 -870 68 VCI 102 -870 118 TESTB3 3602 -870
19 VCI -3760 -870 69 VCI 172 -870 119 TESTA4 3888 -870
20 VCI -3690 -870 70 VCI 242 -870 120 TESTB4 3958 -870
21 VCI -3620 -870 71 VCI 312 -870 121 DUMMY<5> 4244 -870
22 VCI -3550 -870 72 VDD 382 -870 122 RESETB 4314 -870
23 VCI -3480 -870 73 VEXT 452 -870 123 DUMMY<6> 4384 -870
24 VCI -3410 -870 74 VSS 522 -870 124 DUMMY<7> 5420 722
25 VCI -3340 -870 75 REF 592 -870 125 DUMMY<8> 5284 838
26 VCI -3270 -870 76 VDD 662 -870 126 COM<31> 5224 838
27 VCI -3200 -870 77 DCDC4B 732 -870 127 COM<30> 5164 838
28 VCI -3130 -870 78 VSS 802 -870 128 COM<29> 5104 838
29 VCI -3060 -870 79 HPMB 872 -870 129 COM<28> 5044 838
30 VDD -2990 -870 80 VDD 942 -870 130 COM<27> 4984 838
31 DB<0> -2920 -870 81 INTRS 1012 -870 131 COM<26> 4924 838
32 DB<1> -2850 -870 82 VSS 1082 -870 132 COM<25> 4864 838
33 DB<2> -2780 -870 83 VSS 1152 -870 133 COM<24> 4804 838
34 DB<3> -2710 -870 84 VSS 1222 -870 134 COM<23> 4744 838
35 DB<4> -2640 -870 85 VSS 1292 -870 135 COM<22> 4684 838
36 DB<5> -2570 -870 86 VSS 1362 -870 136 COM<21> 4624 838
37 DB<6> -2500 -870 87 VSS 1432 -870 137 COM<20> 4564 838
38 DUMMY<1> -2430 -870 88 VSS 1502 -870 138 COM<19> 4504 838
39 DUMMY<2> -2144 -870 89 VSS 1572 -870 139 COM<18> 4444 838
40 DB<7> -2074 -870 90 VSS 1642 -870 140 COM<17> 4384 838
41 DUMMY<3> -2004 -870 91 VSS 1712 -870 141 COM<16> 4324 838
42 DUMMY<4> -1718 -870 92 VSS 1782 -870 142 COM<15> 4264 838
43 VSS -1648 -870 93 VSS 1852 -870 143 COM<14> 4204 838
44 DUTY0 -1578 -870 94 VSS 1922 -870 144 COM<13> 4144 838
45 VDD -1508 -870 95 VSS 1992 -870 145 COM<12> 4084 838
46 DUTY1 -1438 -870 96 VSS 2062 -870 146 COM<11> 4024 838
47 VSS -1368 -870 97 VSS 2132 -870 147 COM<10> 3964 838
48 RS -1298 -870 98 VSS 2202 -870 148 COM<9> 3904 838
49 VDD -1228 -870 99 VSS 2272 -870 149 COM<8> 3844 838
50 PS -1158 -870 100 VSS 2342 -870 150 COM<7> 3784 838
S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD Table 2 . Pad Center Coordinates (Continued) [Unit: µm] X Y X Y X Y
151 COM<6> 3724 838 201 SEG<63> 724 838 251 SEG<13> -2276 838
152 COM<5> 3664 838 202 SEG<62> 664 838 252 SEG<12> -2336 838
153 COM<4> 3604 838 203 SEG<61> 604 838 253 SEG<11> -2396 838
154 COM<3> 3544 838 204 SEG<60> 544 838 254 SEG<10> -2456 838
155 COM<2> 3484 838 205 SEG<59> 484 838 255 SEG<9> -2516 838
156 COM<1> 3424 838 206 SEG<58> 424 838 256 SEG<8> -2576 838
157 COM<0> 3364 838 207 SEG<57> 364 838 257 SEG<7> -2636 838
158 COMS<0> 3304 838 208 SEG<56> 304 838 258 SEG<6> -2696 838
159 DUMMY<9> 3244 838 209 SEG<55> 244 838 259 SEG<5> -2756 838
160 DUMMY<10> 3184 838 210 SEG<54> 184 838 260 SEG<4> -2816 838
161 SEG<103> 3124 838 211 SEG<53> 124 838 261 SEG<3> -2876 838
162 SEG<102> 3064 838 212 SEG<52> 64 838 262 SEG<2> -2936 838
163 SEG<101> 3004 838 213 SEG<51> 4 838 263 SEG<1> -2996 838
164 SEG<100> 2944 838 214 SEG<50> -56 838 264 SEG<0> -3056 838
165 SEG<99> 2884 838 215 SEG<49> -116 838 265 DUMMY<11> -3116 838
166 SEG<98> 2824 838 216 SEG<48> -176 838 266 DUMMY<12> -3176 838
167 SEG<97> 2764 838 217 SEG<47> -236 838 267 COM<32> -3236 838
168 SEG<96> 2704 838 218 SEG<46> -296 838 268 COM<33> -3296 838
169 SEG<95> 2644 838 219 SEG<45> -356 838 269 COM<34> -3356 838
170 SEG<94> 2584 838 220 SEG<44> -416 838 270 COM<35> -3416 838
171 SEG<93> 2524 838 221 SEG<43> -476 838 271 COM<36> -3476 838
172 SEG<92> 2464 838 222 SEG<42> -536 838 272 COM<37> -3536 838
173 SEG<91> 2404 838 223 SEG<41> -596 838 273 COM<38> -3596 838
174 SEG<90> 2344 838 224 SEG<40> -656 838 274 COM<39> -3656 838
175 SEG<89> 2284 838 225 SEG<39> -716 838 275 COM<40> -3716 838
176 SEG<88> 2224 838 226 SEG<38> -776 838 276 COM<41> -3776 838
177 SEG<87> 2164 838 227 SEG<37> -836 838 277 COM<42> -3836 838
178 SEG<86> 2104 838 228 SEG<36> -896 838 278 COM<43> -3896 838
179 SEG<85> 2044 838 229 SEG<35> -956 838 279 COM<44> -3956 838
180 SEG<84> 1984 838 230 SEG<34> -1016 838 280 COM<45> -4016 838
181 SEG<83> 1924 838 231 SEG<33> -1076 838 281 COM<46> -4076 838
182 SEG<82> 1864 838 232 SEG<32> -1136 838 282 COM<47> -4136 838
183 SEG<81> 1804 838 233 SEG<31> -1196 838 283 COM<48> -4196 838
184 SEG<80> 1744 838 234 SEG<30> -1256 838 284 COM<49> -4256 838
185 SEG<79> 1684 838 235 SEG<29> -1316 838 285 COM<50> -4316 838
186 SEG<78> 1624 838 236 SEG<28> -1376 838 286 COM<51> -4376 838
187 SEG<77> 1564 838 237 SEG<27> -1436 838 287 COM<52> -4436 838
188 SEG<76> 1504 838 238 SEG<26> -1496 838 288 COM<53> -4496 838
189 SEG<75> 1444 838 239 SEG<25> -1556 838 289 COM<54> -4556 838
190 SEG<74> 1384 838 240 SEG<24> -1616 838 290 COM<55> -4616 838
191 SEG<73> 1324 838 241 SEG<23> -1676 838 291 COM<56> -4676 838
192 SEG<72> 1264 838 242 SEG<22> -1736 838 292 COM<57> -4736 838
193 SEG<71> 1204 838 243 SEG<21> -1796 838 293 COM<58> -4796 838
194 SEG<70> 1144 838 244 SEG<20> -1856 838 294 COM<59> -4856 838
195 SEG<69> 1084 838 245 SEG<19> -1916 838 295 COM<60> -4916 838
196 SEG<68> 1024 838 246 SEG<18> -1976 838 296 COM<61> -4976 838
197 SEG<67> 964 838 247 SEG<17> -2036 838 297 COM<62> -5036 838
198 SEG<66> 904 838 248 SEG<16> -2096 838 298 COM<63> -5096 838
199 SEG<65> 844 838 249 SEG<15> -2156 838 299 COMS<1> -5156 838
200 SEG<64> 784 838 250 SEG<14> -2216 838 300 DUMMY<13> -5216 838
301 DUMMY<14> -5420 662
No. Pad Name Coordinate Pad No. Pad Name Coordinate Pad No. Pad Name
Table 3. Power Supply Pins Description Table 4. LCD Driver Supply Pins Description It is valid only when internal voltage regulator resistors are not used (INTRS = “L”). This is the reference voltage for the voltage converter circuit for the LCD driving. Whether internal voltage converter use or not use, this pin should be fixed. This is the external-input reference voltage (VREF) for the internal voltage regulator. It is valid only when external VREF is used (REF = “L”).
Table 5. System Control Pins Description This pin is used together with the FR pin. This pin is used together with the FRS pin. This pin selects the resistors for adjusting V LCD voltage level. VLCD voltage is controlled by VR pin and external resistive divider. The LCD driver duty ratio depends on the following table. Power control pin of the power supply circuits for LCD driver.
Table 6. Microprocessor Interface Pins Description When RESETB is “L”, initialization is executed. DB5 are high impedance and E_RDB and RW_WRB must be fixed to either “H” or “L”. select is non-active, DB0 to DB7 may be high impedance.
Table 6. Microprocessor Interface Pins Description (Continued) l atched at the falling edge of the E_RDB signal. When chip select is not active, DB0 to DB7 may be hig h impedance. TESTs I/O These are pins for chip test. NOTE: DUMMYs – These pins should be opened (floated).
Table 7. LCD Driver Output Pins Description The display data and the FR signal control the output voltage of segment driver. The internal scanning data and FR signal control the output voltage of common driver. The output signals of two pins are same. When not used, these pins should be left open.
S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD FUNCTIONAL DESCRIPTION MICROPROCESSOR INTERFACE Chip Select Input There are CS1B and CS2 pins fo r chip selection. The S6B1400X can interface with an MPU only when CS1B is “L” and CS2 is “H”. When these pins are set to any other combination, RS, E_RDB, and RW_WRB inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial inter face, the internal shift register and the counter are reset. Parallel / Serial Interface S6B1400X has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 8. Table 8. Parallel / Serial Interface Mode table 9. The type of data transfer is determined by signals at RS, E_RDB and RW_WRB as shown in table 10. Table 9. Microprocessor Selection for Parallel Interface Table 10. Parallel Data Transfer
Description
H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register (instruction)
When the S6B1400X is active (CS1B=”L”, CS2=”H”), serial data (DB7) and serial clock (DB6 ) inputs are enabled. the operation check on the actual machine is recommended. The serial interface type is selected by setting C68 as shown in table 11. Table 11. Parallel / Serial Interface Mode
4 Pin SPI Serial Interface (PS = "L", C68 = "H")
In 4-pin serial interface mode, RS pin is used for indicating whether serial data input is di splay or instruction data. Data is display data when RS is high and instruction data when RS is low. Figure 3. 4 Pin SPI s erial Interface Timing (RS used)
3 Pin-SPI Interface (PS = "L", C68 = "L")
handled as instruction data. For details, refers to figure 4.
3 Byte (1) 2 Byte (2) 104 Byte
(1) Set Page and Column Address. (2) Set DDC(Data Direction Command) and No. of Data Bytes. Figure 4. 3 Pin SPI Timing (RS is not used) commands sending out, the following messages will be dat a. If data is stopped in transmitting, it is not valid data. New data will be transferred serially with most significant bit first.
- In spite of transmission of d ata, if CS1B will be disable, state terminates abnormally. Next state is initial ized.
needs not to check this flag before each instruction, which improves the MPU performance.
Figure 7. RAM-to-LCD Data Transfer access line address of icons.
independent of page address register. Figure 8. The Relationship between the Column Address and the Segment Outputs instructions without changing the data in the display data RAM.
66 When the initial display
Figure 9. Display Data RAM Map
display timing generation circuit. generated from the display clock. 2 -frame AC driver waveforms with internal timing signal are shown in figure 10. Figure 10. 2-frame AC Driving Waveform ( Duty Ratio = 1/65)
Instruction specifies the scanning direction of the common output pins . Table 12. The Relationship between Duty Ratio and Common Output
0 COM[0:15] *NC COM[16:31] 1/33 1 COM[31:16] *NC COM[15:0] COMS
0 COM[0:23] *NC COM[24:47] 1/49 1 COM[47:24] *NC COM[23:0] COMS
0 COM[0:26] *NC COM[27:53] 1/55 1 COM[53:27] *NC COM[26:0] COMS
0 COM[0:63] 1/65 1 COM[63:0] COMS
segment driver. This LCD panel driver voltage depends on the combination of display data and FR signal.
0 SEG2
Figure 11. Segment and Common Timing
These circuits boost up the electric potential between VCI and V SS to 3 or 4 times toward positive side. Figure 12. Three Times Boosting Circuit Figure 13. Four Times Boosting Circuit
operational-amplifier circuits shown in figure 14, it is necessary to be applied inte rnally. Table 13. VREF Voltage at Ta = 25 °C Table 14. Electronic Contrast Control Register (64 Steps)
Figure 14. Internal Voltage Regulator Circuit
VLCD and VR. We determine VLCD by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 15. Internal Rb / Ra ratio depending on 3 -bit data (R2 R1 R0) electronic volume registers for each temperature coefficient at Ta = 25 °C. Figure 15. Electronic Volume Level
- LCD driver voltage, VLCD = 6V
- 6-bit reference voltage register = (1, 0, 0, 0, 0, 0)
- Maximum current flowing Ra, Rb = 1 uA
The following table shows the range of VLCD depending on the above requirements. Table 16. VLCD Depending on Electronic Volume Level
V1 to V4 level and each duty ratio. Table 17. The Relationship between V1 to V4 Level and Duty Ratio to degrade. When this occurs, setting the HPMB pin to “L”(high power mode) can improve the quality of the display.
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X RESET CIRCUIT Setting RESETB to “L” or Reset instruction can initialize internal function. When RESETB becomes “L”, the initialized driver has following states. Display ON / OFF: OFF Entire display ON / OFF: OFF (normal) ADC select: OFF (normal) Reverse display ON / OFF: OFF (normal) Power control register (VC, VR, VF) = (0, 0, 0) Serial interface internal register data clear LCD bias ratio: 1/9 (1/65 duty), 1/8 (1/55 duty), 1/8 (1/49 duty), 1/6 (1/33 duty) On-chip oscillator OFF Power save release Read-modify-write: OFF SHL select: OFF (normal) Static indicat or mode: OFF Static indicator register: (S1, S0) = (0, 0) Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 1, 1) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) Test mode release When RESET instruction is issued, the initialized driver has following states. Read-modify-write: OFF Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) SHL select: 0 Display start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 1, 1) Reference voltage set: OFF Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0) Test mode release While RESETB is “L” or Reset instruction is executed, no instruction except read status c ould be accepted. Reset status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initializ e the MPU and this LSI at the same time. The initialization by RESETB is essential before used.
Table 18. Instruction Table When EON = 0: normal display.
Table 18. Instruction Table (Continued)
S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD DISPLAY ON / OFF Turns the display ON or OFF RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 1 DON DON = 1: display ON DON = 0: display OFF INITIAL DISPLAY LINE Sets the line address of display RAM to determine the initial display line . The RAM display data is displayed at the top row (COM0 when SHL = L, COM63 when SHL = H) of LCD panel. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0 ST5 ST4 ST3 ST2 ST1 ST0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63 SET PAGE ADDRESS Sets the page address of display data RAM from the microprocessor into the page address register. Any RAM data bit can be accessed when its page address and column address are specified. Along with the column address, the page address defines the address of t he display RAM to write or read display data. Changing the page address doesn't effect to the display status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 P3 P2 P1 P0 P3 P2 P1 P0 Page 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X SET COLUMN ADDRESS Sets the column address of display RAM from the microprocessor into the column address register. Along with the column address, the column address defines the address of the display RAM to write or read display data. When the microprocessor r eads or writes display data to or from display RAM, column addresses are automatically increased. Set Column Address MSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 x Y6 Y5 Y4 Set Column Address LSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Column address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 1 0 0 1 1 0 102 1 1 0 0 1 1 1 103 READ STATUS Indicates the internal status of the S6B1400X RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY ADC ON / OFF RESETB 0 0 0 0 Flag Description BUSY The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy ADC Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG103 → SEG0), 1: normal direction (SEG0 → SEG103) ON / OFF Indicates display ON / OFF status. 0: display ON, 1: display OFF RESETB Indicates the initialization is in progress by RESETB signal. 0: chip is active, 1: ch ip is being reset
continuously write data to the addressed page. Figure 16. Sequence for Writing Display Data Figure 17. Sequence for Reading Display Data an address into the column address register. Display data cannot be read through the serial interface. output pins can be reversed by software. This makes IC layout flexible in LCD module assembly.
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X REVERSE DISPLAY ON / OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 1 REV REV RAM bit data = “1” RAM bit data = “0” 0 (normal) LCD pixel is illuminated LCD pixel is not illuminated 1 (reverse) LCD pixel is not illuminated LCD pixel is illuminated ENTIRE DISPLAY ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the Reverse Display On/Off instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 0 EON EON = 0: normal display EON = 1: entire display ON SELECT LCD BIAS Selects LCD bias ratio of the voltage required for driving the LCD. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 1 Bias LCD bias Duty ratio DUTY1 DUTY0 Bias = 0 Bias = 1 1/33 0 0 1/6 1/5 1/49 0 1 1/8 1/6 1/55 1 0 1/8 1/6 1/65 1 1 1/9 1/7 SET MODIFY-READ This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify -read instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 0 0
before the set Modify-read instruction is started. Figure 18. Sequence for Cursor Display power supply, which is initialized by the RESETB pin.
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X SHL SELECT (COMMON OUTPUT MODE SELECT) COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 SHL × × × × : Don’t care SHL = 0: normal direction (COM0 → COM63) SHL = 1: reverse direction (COM63 → COM0) POWER CONTROL Selects one of eight power circuit functions by using 3 -bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 VC VR VF VC VR VF Status of internal power supply circuits
1 Internal voltage converter circuit is OFF
Internal voltage converter circuit is ON
1 Internal voltage regulator circuit is OFF
Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON REGULATOR RESISTOR SELECT Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the Table 15. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 R2 R1 R0 R2 R1 R0 (1 + Rb / Ra) ratio 0 0 0 3.0 0 0 1 3.5 0 1 0 4.0 0 1 1 4.5 (default) 1 0 0 5.0 1 0 1 5.5 1 1 0 Not available 1 1 1 Not available
of reference voltage register. After second instruction, reference voltage mode is released. Figure 19. Sequence for Setting the R eference Voltage
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X SET STATIC INDICATOR STATE Consists of two bytes instruction. The first byte instruction (Set Static Indicator Mode) enables the second byte instruction (Set Static Indicator Register) to be valid. The first byte sets the static indicator on/off. When it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this static indicator state is released after settin g the data of indicator register. The 1st Instruction: Set Static Indicator Mode (ON / OFF) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 0 SM SM = 0: static indicator OFF SM = 1: static indicator ON The 2nd Instruction: Set Static Indicator Re gister RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S1 S0 Status of static indicator output 0 0 OFF 0 1 ON (about 1 second blinking) 1 0 ON (about 0.5 second blinking) 1 1 ON (always ON)
S6B1400X SPEC. VER. 0.0 104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SET DATA DIRECTION & DISPLAY DATA LENGTH (3-PIN SPI MODE) Consists of two bytes instruction. This command is used in 3-Pin SPI mode only (PS = ”L” and C68 = ”L”). It will be two continuous commands, the first byte control the data direction (write mode only) and inform the LCD driver the second byt e will be number of data bytes will be write. When RS is not used, the Display Data Length instruction is used to indicate that a specified number of display data bytes are to be transmitted. The next byte after the display data string is handled as command data. The 1st Instruction: Set Data Direction (Only Write Mode) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x x 1 0 0 0 0 0 0 0 The 2nd Instruction: Set Display Data Length (DDL) Register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x x D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Display Data Length 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 1 0 3 : : : : : : : : : 1 1 1 1 1 1 0 1 254 1 1 1 1 1 1 1 0 255 1 1 1 1 1 1 1 1 256 NOP Non-Operation Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 1 TEST INSTRUCTION (TEST INSTRUCTION_1 & TEST INSTRUCTION_2) These are the instruction for IC chip testing. Please do not use it. If the test instruction is used by accident, it can be cleared by applying “0” signal to the RESETB in put pin or the reset instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 1 × × × × 0 0 1 0 0 1 × × × ×
entire display OFF instruction.
2 Bytes Command
Figure 20. Power Save (Compound Instruction) a. The oscillator circuit and the LCD power supply circuit are halted. b. All liquid crystal driv e circuits are halted, and the segment and common outputs go to the VSS level. continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. a. The LCD power supply circuits are halted. The oscillator circuit continues to operate. go to the VSS level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enters sleep mode.
Figure 21. Initializing with the Built-in Power Supply Circuits
Figure 22. Data Displaying
Figure 23. Power OFF
Table 19. Absolute Maximum Ratings
- VDD and VLCD are based on VSS = 0V.
- Voltages VLCD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied.
- If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.
Table 20. DC Characteristics
104 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD SPEC. VER. 0.0 S6B1400X Dynamic Current Consumption when the Built-in Power Circuit is ON (At Operate Mode) (Ta = 25°C) Item Symbol Condition Min. Typ. Max. Unit Pin used VDD = 3.0V, (VCI = VDD, 3 times boosting) VLCD – VSS = 7.64V, 1/65 duty ratio, Display pattern OFF, Normal power mode - 120 - µΑ *11 VDD = 3.0V, (VCI = VDD, 3 times boosting) VLCD – VSS = 7.64V, 1/65 duty ratio, Display pattern checker, Normal power mode - 140 - µΑ *11 VDD = 3.0V, (VCI = VDD, 4 times boosting) VLCD – VSS = 8.40V, 1/65 duty ratio, Display pattern OFF, Normal power mode - 180 - µΑ *11 Dynamic current consumption (2) IDD2 VDD = 3.0V, (VCI = VDD, 4 times boosting) VLCD – VSS = 8.40V, 1/65 duty ratio, Display pattern checker, Normal power mode - 200 - µΑ *11 Current Consumption during Power Save Mode (Ta = 25°C) Item Symbol Condition Min. Typ. Max. Unit Pin used Sleep mode current IDDS1 During sleep - - 2 µA Standby mode current IDDS2 During standby - - 10 µA
Table 21. The Relationship between Oscillation Frequency and Frame Frequency assurance during access from the MPU. *2. In case of external power supply is applied. *3. CS1B, CS2, RS, DB0 to DB7, E_RDB, RW_WRB, RESETB, C68, PS, INTRS, HPMB pins. *4. DB0 to DB7, FR, FRS, CL pins. *5. CS1B, CS2, RS, DB[7:0], E_RDB, RW_WRB, RESETB, C68, PS, INTRS, HPMB pins. *6. Applies when the DB[7:0], FR, FRS and CL pins are in high impedance. *7. Resistance value when ± 0.1[mA] is applied during the ON status of the output pin SEGn or COMn. *8. See table 21 for the relationship between oscillation frequency and frame frequency. *9. On-chip reference voltage source of the voltage regulator circuit to adjust VLCD. *10,11. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors (Ra and Rb) is not included. It does not include the current of the LCD panel capacity, wiring capacity , etc.
Figure 24. Read / Write Characteristics (8080 -series MPU) Note: 1. The input signal rising time and falling time (tr,tf) is specified at 15ns or less.
Figure 25. Read / Write Characteristics (6800 -series Microprocessor) Note: 1. The input signal rising time and falling time (tr,tf) is specified at 15ns or less.
Figure 26. Serial Interface Characteristics Note: 1. The input signal rising time and falling time (tr,tf) is specified at 15ns or less.
Figure 27. Reset Input Timing
Figure 49. S6B1400X Application Circuit for 4 Pin SPI Serial Interface