S6B0721 SAMSUNG | Alldatasheet
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1 32 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD June .2000 . Ver. 0.1 Prepared by : Jae-Su, Ko Ko1942@samsung.co.kr Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 S6B0721 Specification Revision History Version Content Date 0.0 Initial version Nov.1999 0.1 Read timing is changed (Figure 5) Jun.2000
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD CO NTENTS
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD INTRODUCTION The S6B0721 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 6 5 common s and 1 32 segment s driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8-bit parallel display data and stores in an on-chip D isplay D ata RAM of 65 x 1 32 bits. It provides a high-flexible display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it performs display data RAM read/write operation with no externally operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
FEATURES
− 6 5 common outputs / 1 32 segment outputs On-chip Display Data RAM − Capacity: 65 x 1 32 = 8 ,58 0 bits Applicable Duty Ratios D uty ratio Applicable LCD bias Maximum display area 1/ 6 5 1/ 7 or 1/ 9 6 5 × 1 32 1/49 1/6 or 1/8 49 × 132 1/33 1/5 or 1/6 33 × 132 Microprocessor Interface − 8-bit parallel bi-directional interface with 6800-series or 8080-series − Serial interface (only write operation) available Function Set − Various instructions s ets − H/W, S/W r eset capable Built-in A nalog C ircuit − On-chip oscillator circuit − Voltage converter (x2 , x3, x4, x5) − Voltage regulator ( temperature coefficient: -0.05%/ °C , -0. 2 %/ °C) − Voltage follower − E lectronic contrast control function (64 steps) Operating Voltage Range − Supply voltage (V DD ): 2.4 to 3.6 V − LCD driving voltage (V LCD = V0 - V SS ): 4.0 to 1 5 .0 V Low Power Consumption − 70 µΑ Typ. (V DD = 3V, x 4 boosting, V0 = 1 1 V, internal power supply ON) − 10 µΑ Max. ( during power save [standby] mode) Package Type − Gold bump chip or TCP
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 Series Specifications Product c ode Internal TEMPS Temp. c oefficient Package Chip t hickness S6B0721X01-B0CZ 670 µm S6B0721X01-B0CY (V SS c onnected) -0.05%/ °C 470 µm S6B0721X11-B0CZ 670 µm S6B0721X11-B0CY (V DD c onnected) -0.2%/ °C COG 470 µm S6B0721X01-xxX0 670 µm S6B0721X01-xxXN (V SS c onnected) -0.05%/ °C 470 µm S6B0721X11-xxX0 670 µm S6B0721X11-xxXN (V DD c onnected) -0.2%/ °C TCP 470 µm * XX: TCP ordering number
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD BLOCK DIAGRAM MS CL M FRS DISP DUTY0 DUTY1 VDD VSS HPM VR INTRS VOUT C1- C1+ C2- C2+ C3 - C 3+ DCDC5B V / C CIRCUIT V / R CIRCUIT V / F CIRCUIT
33 COMMON
MPU INTERFACE (PARALLEL & SERIAL) INSTRUCTION DECODERBUS HOLDER COLUMN ADDRESS CIRCUIT LINE ADDRESS CIRCUIT PAGE ADDRESS CIRCUIT DISPLAY DATA RAM
65 X 1 32 = 8 ,58 0 Bits
DB6(SCLK) DB7(SID) MI RESETB PS RW_WR E_RD RS CS2 CS1B COMS COM64 COM33 SEG132 SEG131 SEG130 SEG3 SEG2 SEG1 COM32 COM1 COMS OSCILLATOR 1 32 SEGMENT DRIVER CIRCUITS STATUS REGISTER INSTRUCTION REGISTER CLS Figure 1 . Block Diagram
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 PAD CONFIGURATION ð ðð ððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððð ðð ð Y 1 382 83 1 372 84 109312 108 1 S6B 0721 (TOP VIEW) (0,0) X ð ðððððððððððððððððð - - - - - - - - - - ðððððððððððððððððð ð ð ðððð - - - - ðððð ð ð ðððð - - - - ðððð ð Figure 2 . S6B0721 Chip Configuration Table 1 . S6B0721 Pad Dimensions Size Items Pad No. X Y Unit Chip size - 9640 2020 284,312 90 2 to 107 70Pad pitch 110 to 136, 139 to 282 285 to 311 60 1,108 70 100 2 to 107 50 100 109,137,284,312 110 60 110 to 136,285 to 311 110 45 139 to 282 45 110 µm Bumped pad size (Top size) 138,283 60 110 Bumped pad height 1 to 312 14( Typ.) COG Align Key Coordinate ILB Align Key Coordinate 30 µm 30 µm 30 µm (+4089, + 312 ) 30 µm 30 µm 30 µm (-4094, -565 ) 30µm30µm30µm 60µm 30µm 42 µm 108 µm 42µm 108µm 42µm 108µm (-4161, +473 ) (+4161, - 597 ) 42 µm108 µm
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD PAD CENTER COORDINATES Table 2 . P ad Center Coordinates [Unit: µm] Pad Pad Pad Pad Pad Pad No Name No Name No Name
1 DUMMY -3765 -895 55 VDD 35 -895 109 DUMMY 4673 -850
2 FRS -3675 -895 56 VOUT 105 -895 110 COMS 4673 -780
3 M -3605 -895 57 VOUT 175 -895 111 COM1 4673 -720
4 CL -3535 -895 58 VOUT 245 -895 112 COM2 4673 -660
5 DISP -3465 -895 59 VOUT 315 -895 113 COM3 4673 -600
6 VSS -3395 -895 60 C3+ 385 -895 114 COM4 4673 -540
7 CS1B -3325 -895 61 C3+ 455 -895 115 COM5 4673 -480
8 CS2 -3255 -895 62 C3+ 525 -895 116 COM6 4673 -420
9 VDD -3185 -895 63 C3+ 595 -895 117 COM7 4673 -360
10 RESETB -3115 -895 64 C3- 665 -895 118 COM8 4673 -300
11 RS -3045 -895 65 C3- 735 -895 119 COM9 4673 -240
12 VSS -2975 -895 66 C3- 805 -895 120 COM10 4673 -180
13 RW_WR -2905 -895 67 C3- 875 -895 121 COM11 4673 -120
14 E_RD -2835 -895 68 C1+ 945 -895 122 COM12 4673 -60
15 VDD -2765 -895 69 C1+ 1015 -895 123 COM13 4673 0
16 DB0 -2695 -895 70 C1+ 1085 -895 124 COM14 4673 60
17 DB1 -2625 -895 71 C1+ 1155 -895 125 COM15 4673 120
18 DB2 -2555 -895 72 C1- 1225 -895 126 COM16 4673 180
19 DB3 -2485 -895 73 C1- 1295 -895 127 COM17 4673 240
20 DB4 -2415 -895 74 C1- 1365 -895 128 COM18 4673 300
21 DB5 -2345 -895 75 C1- 1435 -895 129 COM19 4673 360
22 DB6 -2275 -895 76 C2+ 1505 -895 130 COM20 4673 420
23 DB7 -2205 -895 77 C2+ 1575 -895 131 COM21 4673 480
24 VSS -2135 -895 78 C2+ 1645 -895 132 COM22 4673 540
25 DUMMY -2065 -895 79 C2+ 1715 -895 133 COM23 4673 600
26 DUMMY -1995 -895 80 C2- 1785 -895 134 COM24 4673 660
27 VDD -1925 -895 81 C2- 1855 -895 135 COM25 4673 720
28 DUTY0 -1855 -895 82 C2- 1925 -895 136 COM26 4673 780
29 DUTY1 -1785 -895 83 C2- 1995 -895 137 DUMMY 4673 850
30 VSS -1715 -895 84 VSS 2065 -895 138 DUMMY 4380 863
31 MS -1645 -895 85 VSS 2135 -895 139 COM27 4290 863
32 CLS -1575 -895 86 VR 2205 -895 140 COM28 4230 863
33 VDD -1505 -895 87 VR 2275 -895 141 COM29 4170 863
34 MI -1435 -895 88 V0 2345 -895 142 COM30 4110 863
35 PS -1365 -895 89 V0 2415 -895 143 COM31 4050 863
36 VSS -1295 -895 90 V1 2485 -895 144 COM32 3990 863
37 VSS -1225 -895 91 V1 2555 -895 145 SEG1 3930 863
38 VSS -1155 -895 92 V2 2625 -895 146 SEG2 3870 863
39 VSS -1085 -895 93 V2 2695 -895 147 SEG3 3810 863
40 VSS -1015 -895 94 V3 2765 -895 148 SEG4 3750 863
41 VSS -945 -895 95 V3 2835 -895 149 SEG5 3690 863
42 VSS -875 -895 96 V4 2905 -895 150 SEG6 3630 863
43 VSS -805 -895 97 V4 2975 -895 151 SEG7 3570 863
44 VSS -735 -895 98 VSS 3045 -895 152 SEG8 3510 863
45 VSS -665 -895 99 VSS 3115 -895 153 SEG9 3450 863
46 VDD -595 -895 100 DUMMY 3185 -895 154 SEG10 3390 863
47 VDD -525 -895 101 DCDC5B 3255 -895 155 SEG11 3330 863
48 VDD -455 -895 102 VDD 3325 -895 156 SEG12 3270 863
49 VDD -385 -895 103 HPM 3395 -895 157 SEG13 3210 863
50 VDD -315 -895 104 INTRS 3465 -895 158 SEG14 3150 863
51 VDD -245 -895 105 VSS 3535 -895 159 SEG15 3090 863
52 VDD -175 -895 106 DUMMY 3605 -895 160 SEG16 3030 863
53 VDD -105 -895 107 VDD 3675 -895 161 SEG17 2970 863
54 VDD -35 -895 108 TESTCK 3765 -895 162 SEG18 2910 863
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 Table 2 . P ad Center Coordinates (Continued) [Unit: µm] Pad Pad Pad Pad Pad Pad No Name No Name No Name
163 SEG19 2850 863 217 SEG73 -390 863 271 SEG127 -3630 863
164 SEG20 2790 863 218 SEG74 -450 863 272 SEG128 -3690 863
165 SEG21 2730 863 219 SEG75 -510 863 273 SEG129 -3750 863
166 SEG22 2670 863 220 SEG76 -570 863 274 SEG130 -3810 863
167 SEG23 2610 863 221 SEG77 -630 863 275 SEG131 -3870 863
168 SEG24 2550 863 222 SEG78 -690 863 276 SEG132 -3930 863
169 SEG25 2490 863 223 SEG79 -750 863 277 COMS -3990 863
170 SEG26 2430 863 224 SEG80 -810 863 278 COM64 -4050 863
171 SEG27 2370 863 225 SEG81 -870 863 279 COM63 -4110 863
172 SEG28 2310 863 226 SEG82 -930 863 280 COM62 -4170 863
173 SEG29 2250 863 227 SEG83 -990 863 281 COM61 -4230 863
174 SEG30 2190 863 228 SEG84 -1050 863 282 COM60 -4290 863
175 SEG31 2130 863 229 SEG85 -1110 863 283 DUMMY -4380 863
176 SEG32 2070 863 230 SEG86 -1170 863 284 DUMMY -4673 850
177 SEG33 2010 863 231 SEG87 -1230 863 285 COM59 -4673 780
178 SEG34 1950 863 232 SEG88 -1290 863 286 COM58 -4673 720
179 SEG35 1890 863 233 SEG89 -1350 863 287 COM57 -4673 660
180 SEG36 1830 863 234 SEG90 -1410 863 288 COM56 -4673 600
181 SEG37 1770 863 235 SEG91 -1470 863 289 COM55 -4673 540
182 SEG38 1710 863 236 SEG92 -1530 863 290 COM54 -4673 480
183 SEG39 1650 863 237 SEG93 -1590 863 291 COM53 -4673 420
184 SEG40 1590 863 238 SEG94 -1650 863 292 COM52 -4673 360
185 SEG41 1530 863 239 SEG95 -1710 863 293 COM51 -4673 300
186 SEG42 1470 863 240 SEG96 -1770 863 294 COM50 -4673 240
187 SEG43 1410 863 241 SEG97 -1830 863 295 COM49 -4673 180
188 SEG44 1350 863 242 SEG98 -1890 863 296 COM48 -4673 120
189 SEG45 1290 863 243 SEG99 -1950 863 297 COM47 -4673 60
190 SEG46 1230 863 244 SEG100 -2010 863 298 COM46 -4673 0
191 SEG47 1170 863 245 SEG101 -2070 863 299 COM45 -4673 -60
192 SEG48 1110 863 246 SEG102 -2130 863 300 COM44 -4673 -120
193 SEG49 1050 863 247 SEG103 -2190 863 301 COM43 -4673 -180
194 SEG50 990 863 248 SEG104 -2250 863 302 COM42 -4673 -240
195 SEG51 930 863 249 SEG105 -2310 863 303 COM41 -4673 -300
196 SEG52 870 863 250 SEG106 -2370 863 304 COM40 -4673 -360
197 SEG53 810 863 251 SEG107 -2430 863 305 COM39 -4673 -420
198 SEG54 750 863 252 SEG108 -2490 863 306 COM38 -4673 -480
199 SEG55 690 863 253 SEG109 -2550 863 307 COM37 -4673 -540
200 SEG56 630 863 254 SEG110 -2610 863 308 COM36 -4673 -600
201 SEG57 570 863 255 SEG111 -2670 863 309 COM35 -4673 -660
202 SEG58 510 863 256 SEG112 -2730 863 310 COM34 -4673 -720
203 SEG59 450 863 257 SEG113 -2790 863 311 COM33 -4673 -780
204 SEG60 390 863 258 SEG114 -2850 863 312 DUMMY -4673 -850
205 SEG61 330 863 259 SEG115 -2910 863
206 SEG62 270 863 260 SEG116 -2970 863
207 SEG63 210 863 261 SEG117 -3030 863
208 SEG64 150 863 262 SEG118 -3090 863
209 SEG65 90 863 263 SEG119 -3150 863
210 SEG66 30 863 264 SEG120 -3210 863
211 SEG67 -30 863 265 SEG121 -3270 863
212 SEG68 -90 863 266 SEG122 -3330 863
213 SEG69 -150 863 267 SEG123 -3390 863
214 SEG70 -210 863 268 SEG124 -3450 863
215 SEG71 -270 863 269 SEG125 -3510 863
216 SEG72 -330 863 270 SEG126 -3570 863
Table 3. Power Supply Pin Description according to the state of LCD Bias. Table 4. LCD Driver Supply Pin Description It is valid only when on-chip resistors are not used (INTRS = “L”) .
Table 5. System Control Pin Description The following table depends on the MS status. This pin is used together with the M pin. This pin selects the resistors for adjusting V0 voltage level. − INTRS = "H": use the internal resistors. − INTRS = "L": use the external resistors. V0 voltage is controlled with VR pin and external resistive divider. This pin is valid in master operation.
Table 5. System Control Pin Description (Continued)
Table 6. Microprocessor Interface Pin Description When RESETB is “L”, initialization is executed. DB5 are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”. Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”. When chip select is non-active, DB0 to DB7 may be high impedance.
Table 6. Microprocessor Interface Pin Description (Continued) the falling edge of the E signal. When /RD is “L”, DB0 to DB7 are in an output status. When chip select is not active, DB0 to DB7 may be high impedance.
Table 7. LCD Driver Outputs Pin Description The display data and the M signal control the output voltage of segment driver. The internal scanning data and M signal control the output voltage of common driver. The output signals of two pins are same. When not used, these pins should be left open. NOTE: DUMMY - These pins should be opened (floated).
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD FUNCTIONAL DESCRIPTION MICROPROCESSOR INTERFACE Chip Select Input There are CS1B and CS2 pins for C hip S election. The S6B0721 can interface with an MPU only when CS1B is “L” and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface S6B0721 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 8. Table 8 . Parallel / Serial Interface Mode PS Type CS1B CS2 MI Interface mode H 6800-series MPU mode H Parallel CS1B CS2 L 8080-series MPU mode L Serial CS1B CS2 * × Serial-mode * × : Don't care Parallel Interface (PS = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by MI as shown in table 9 . The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table10 . Table 9 . Microprocessor Selection for Parallel Interface MI CS1B CS2 RS E_RD RW_WR DB0 to DB7 MPU bus H CS1B CS2 RS E RW DB0 to DB7 6800-series L CS1B CS2 RS /RD /WR DB0 to DB7 8080-series Table 10 . Parallel Data Transfer Common 6800-series 8080-series RS E_RD (E) RW_WR (RW) E_RD (/RD) RW_WR (/WR)
Description
H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to internal register (instruction)
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 Serial Interface (PS = "L") When the S6B0721 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high and control data when RS is low. Since the clock signal ( DB6) is easy to be affected by the external noise caused by the line length, the operation check on the actual machine is recommended. CS1B CS2 SID SCLK RS DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7 Figure 3 . Serial Interface Timing Busy Flag The B usy F lag indicates whether the S6B0721 is operating or not. When DB7 is “H” in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance.
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD Data Transfer The S6B0721 uses bus holder and internal data bus for D ata T ransfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4 . And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5 . This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. T herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the second read of data. RS /WR DB0 to DB7 N D(N) D(N+1) D(N+2) D(N+3) Internal signals MPU signals /WR BUS HOLDER COLUMN ADDRESS N N+1 N+2 N+3 N D(N) D(N+1) D(N+2) D(N+3) Figure 4 . Write Timing
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 RS /WR B /RD B DB0 to DB7 N MPU signals Dummy D(N) D(N+1) Internal signals /WR B /RD B BUS HOLDER COLUMN ADDRESS N D(N) D(N+1) D(N+2) N N+1 N+2 N+3 D(N+2) Figure 5 . Read Timing
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD DISPLAY DATA RAM (DDRAM) The Display Data RAM stores pixel data for the LCD. It is 65 -row by 1 32 -column addressable array. Each pixel can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and the 9 th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as shown in Figure 6 . The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker. COM 1 - - COM 2 - - COM 3 - - COM 4 - - COM 5 - - DB0 0 0 1 - - 0 DB1 1 0 0 - - 1 DB2 0 1 1 - - 0 DB3 1 0 1 - - 0 DB4 0 0 0 - - 1 Display Data RAM LCD Display Figure 6 . RAM-to-LCD Data Transfer Page Address Circuit This circuit is for providing a P age A ddress to D isplay Data RAM shown in figure 8 . It incorporates 4-bit P age A ddress register changed by only the “Set Page” instruction. Page A ddress 8 (DB3 is “H”, but DB2, DB1 and DB0 are “L”) is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is impossible to access to on-chip RAM. Line Address Circuit This circuit assigns DDRAM a L ine A ddress corresponding to the first line (COM 1 ) of the display. Therefore, by setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 8 . It incorporates 6 -bit line address register changed by only the initial display line instruction and 6 -bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the L ine A ddress for transferring the 1 32 -bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU can not access L ine Ad dress of icons.
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 Column Address Circuit Column address circuit has a 8 -bit preset counter that provides column address to the Display Data RAM as shown in figure 8 . When set Column Address MSB / LSB instruction is issued, 8 -bit [Y 7 :Y0] is updated. And, since this address is increased by 1 each a Read or Write Data instruction, microprocessor can access the display data continuously. However, the counter is not incre as ed and locked if a non-existing address above 84 H. It is unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the C olumn A ddress counter is independent of page address register. ADC s elect instruction makes it possible to invert the relationship between the C olumn A ddress and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC s elect instruction. Refer to the following figure 7 . SEG output SEG SEG SEG SEG 129 SEG 130 SEG 131 SEG 132 Display data 1 0 1 0 1 1 0 0 LCD panel display ( ADC = 0 ) LCD panel display Figure 7 . The Relationship b etween t he Column Address a nd t he Segment Outputs Segment Control Circuit This circuit controls the display data by the Display ON / OFF, Reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM.
in the voltage converter and display timing generation circuit. Figure 9. V DD vs. f OSC waveform and internal timing signal are shown in figure 9 . shows the M, CL, and DISP status.
Instruction specifies the scanning direction of the common output pins . Table 12. The Relationship between Duty Ratio and Common Output
0 COM[1:16] *NC COM[17:32]1/33 1 COM[32:17] *NC COM[16:1] COMS
0 COM[1:24] *NC COM[25:48]1/49 1 COM[48:25] *NC COM[24:1] COMS
0 COM[1:64]1/65 1 COM[64:1] COMS
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 LCD DRIVER CIRCUIT This driver circuit is configured by 66-c hannel common drivers (including 2 COMS channels) and 1 32 -channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal. COM 1 COM2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 COM 10 COM1 1 COM1 2 COM1 3 COM1 4 COM1 5 COM 16 S E G S E G S E G S E G S E G
1 SEG 3
M V SS V SS V SS V SS V SS V SS V DD V SS Figure 11 . Segment and Common Timing
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD POWER SUPPLY CIRCUITS The P ower S upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For details, refers to "Instruction Description". Table 13 shows the referenced combinations in using power supply circuits. Table 13 . Recommended Power Supply Combinations User setup Power control (VC VR VF) V/C circuits V/R circuits V/F circuits VOUT V0 V1 to V4 Only the internal power supply circuits are used 1 1 1 ON ON ON Open Open Open Only the voltage regulator circuits and voltage follower circuits are used 0 1 1 OFF ON ON External input Open Open Only the voltage follower circuits are used 0 0 1 OFF OFF ON Open External input Open Only the external power supply circuits are used 0 0 0 OFF OFF OFF Open External input External input
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD Voltage Regulator Circuits The function of the internal V oltage R egulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in figure 16 , it is necessary to be applied internally or externally. For the Eq. 1, we determine V0 by Ra, Rb and V EV . The Ra and Rb are connected internally or externally by INTRS pin. And V EV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. V REF voltage at Ta = 25 °C is shown in table 14-1 . Rb Ra (63 - α) 3 00 Table 14-1. V REF Voltage at Ta = 25 °°C TEMPS Temp. coefficient V REF [V] L -0.05% / °C 2.0 H -0. 2 % / °C 2.0 Table 14-2. Reference Voltage Parameter s ( αα) S V5 S V4 S V3 S V2 S V1 S V0 Reference voltage p arameter ( αα) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 62 1 1 1 1 1 1 63
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 V EV GND Ra Rb V SS VR VOUT Figure 16 . Internal V oltage R egulator C ircuit
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD In Case of Using Internal Resistors, Ra and Rb (INTRS = "H") When INTRS pin is “H”, resistor Ra is connected internally between VR pin and V SS , and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 15 . Internal Rb / Ra Ratio depending on 3-bit Data (R2 R1 R0) 3-bit data settings (R2 R1 R0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 The following figure shows V0 voltage measured by adjusting internal regulator re s ist o r ratio ( Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 °C. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 0 8 16 24 32 40 48 56 Electronic volume level [V] (1 1 1) (1 1 0) (1 0 1) (1 0 0) (0 1 1) (0 1 0) (0 0 1) (0 0 0) Figure 17 . Electronic Volume Level
- LCD driver voltage, V0 = 10V
- 6-bit reference voltage register = (1, 0, 0, 0, 0, 0)
- M aximum current flowing Ra, Rb = 1 uA
The following table shows the range of V0 depending on the above requirements. Table 16. V0 D epending on Electronic Volume L evel
between V1 to V4 level and each duty ratio. Table 17. The Relationship between V1 to V4 level and Duty Ratio
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 RESET CIRCUIT Setting RESETB to “L” or Reset instruction can initialize internal function. When RESETB becomes “L”, following procedure is occurred. Display ON / OFF: OFF Entire display ON / OFF: OFF (normal) ADC select: OFF (normal) Reverse display ON / OFF: OFF (normal) Power control register (VC, VR, VF) = (0, 0, 0) LCD bias ratio: 1/ 7 (1/65 d uty), 1/6 (1/49 d uty), 1/5 (1/33 d uty) R ead -m odify -write : OFF SHL select: OFF (normal) Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) D isplay start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Reference voltage set: OFF Reference voltage control register: ( S V5, S V4, S V3, S V2, S V1, S V0) = (1, 0, 0, 0, 0, 0) When RESET instruction is issued, following procedure is occurred. R ead -m odify- write : OFF Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) SHL select: 0 D isplay start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Reference voltage set: OFF Reference voltage control register: ( S V5, S V4, S V3, S V2, S V1, S V0) = (1, 0, 0, 0, 0, 0) While RESETB is “L” or Reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used.
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD INSTRUCTION DESCRIPTION Table 18 . Instruction Table × : Don’t care Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Read display data 1 1 Read data Read data from DDRAM Write display data 1 0 Write data Write data into DDRAM Read status 0 1 BUSY ADC ON /OFF RES ETB 0 0 0 0 Read the internal status Display ON / OFF 0 0 1 0 1 0 1 1 1 D ON Turn on/off LCD panel When D ON = 0: display OFF When D ON = 1: display ON Initial display line 0 0 0 1 S T 5 S T 4 S T 3 S T 2 S T 1 S T 0 Specify DDRAM line for COM1 Set r eference v oltage m ode 0 0 1 0 0 0 0 0 0 1 Set r eference v oltage Mode Set r eference v oltage r egister 0 0 × × S V5 S V4 S V3 S V2 S V1 S V0 Set r eference v oltage r egister Set page address 0 0 1 0 1 1 P3 P2 P1 P0 Set page address Set column address MSB 0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set column address MSB Set column address LSB 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Set column address LSB ADC select 0 0 1 0 1 0 0 0 0 ADC Select SEG output direction When ADC = 0 : normal direction (SEG1 → SEG132) When A DC = 1 : reverse direction (SEG132 → SEG1) Reverse display ON / OFF 0 0 1 0 1 0 0 1 1 REV Select normal / reverse display When REV = 0 : normal display When REV = 1 : reverse display Entire display ON / OFF 0 0 1 0 1 0 0 1 0 EON Select normal / entire display ON When EON = 0 : normal display. When EON = 1 : entire display ON LCD bias select 0 0 1 0 1 0 0 0 1 BIAS Select LCD bias Set modify-read 0 0 1 1 1 0 0 0 0 0 Set modify-read mode Reset modify-read 0 0 1 1 1 0 1 1 1 0 Release modify-read mode Reset 0 0 1 1 1 0 0 0 1 0 Initialize the internal functions SHL select 0 0 1 1 0 0 SHL × × × Select COM output direction When SHL = 0 : normal direction (COM1 → COM64) When SHL = 1: reverse direction (COM64 → COM1) Power control 0 0 0 0 1 0 1 VC VR VF Control power circuit operation Regulator resistor select 0 0 0 0 1 0 0 R2 R1 R0 Select internal resistance ratio of the regulator resistor Set static indicator mode 0 0 1 0 1 0 1 1 0 SM Set static indicator mode Set static indicator register 0 0 × × × × × × S1 S0 Set static indicator register Power s ave - - - - - - - - - - Compound instruction of display OFF and entire display ON Test instruction 0 0 1 1 1 1 × × × × Don't use this instruction.
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 Read Display Data 8-bit data from D isplay D ata RAM specified by the column address and page address can be read by this instruction. As the column address is incre as ed by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display D ata cannot be read through the serial interface. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 Read data Write Display Data 8-bit data of D isplay D ata from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is incre as ed by 1 automatically so that the microprocessor can continuously write data to the addressed page. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 Write data Data Write Set Column Address Set Page Address Optional Status Column = Column + 1 NO YESData Write Continue ? Dummy Data Read Set Column Address Set Page Address Optional Status Column = Column + 1 NO YESData Read Continue ? Data Read Column = Column + 1 Figure 22 . Sequence for Writing Display Data Figure 23 . Sequence for Reading Display Data
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD Read Stat u s Indicates the internal status of the S6B0721. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY ADC ON / OFF RES ETB 0 0 0 0 Flag Description BUSY The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy. ADC Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG 132 → SEG 1 ), 1: normal direction (SEG 1 → SEG 132 ) ON / OFF Indicates display ON / OFF status 0: display ON, 1: display OFF RES ETB Indicates the initialization is in progress by RESETB signal. 0: chip is active, 1: chip is being reset. Display ON / OFF Turns the display ON or OFF RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 1 D ON D ON = 1: display ON D ON = 0: display OFF Initial Display Line Sets the line address of display RAM to determine the Initial D isplay L ine . The RAM display data is displayed at the top row (COM 1 when SHL = L, COM64 when SHL = H ) of LCD panel. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 S T 5 S T 4 S T 3 S T 2 S T 1 S T 0 S T 5 S T 4 S T 3 S T 2 S T 1 S T 0 L ine address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 R eference Voltage Select Consists of 2-byte instruction The 1 st instruction sets reference voltage mode , the 2 nd one updates the contents of reference vol tage register. After second instruction, reference voltage m ode is released. The 1 st Instruction : Set Reference Voltage Select M ode RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 0 0 0 0 1 The 2 nd Instruction : Set Reference Voltage R egister RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 × × SV5 S V4 S V3 S V2 S V1 S V0 S V5 S V4 S V3 S V2 S V1 S V0 Reference voltage pa rameter ( αα) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 62 1 1 1 1 1 1 63 2 nd Instruction for Register Setting Setting R eference V oltage End 1 st Instruction for Mode Setting Setting R eference V oltage Start Figure 24 . Sequence for Setting the R eference V oltage
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD S et Page Address Sets the P age A ddress of display data RAM from the microprocessor into the P age A ddress register. Any RAM data bit can be accessed when its P age A ddress and column address are specified. Along with the column address, the P age A ddress defines the address of the display RAM to write or read display data. Changing the P age A ddress doesn't effect to the display status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 P3 P2 P1 P0 P3 P2 P1 P0 P age 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8 Set Column Address Sets the C olumn A ddress of display RAM from the microprocessor into the C olumn A ddress register. Along with the C olumn A ddress, the C olumn A ddress defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, column addresses are automatically incre as ed. Set Column Address MSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set Column Address LSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 C olumn address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : : 1 0 0 0 0 0 1 0 130 1 0 0 0 0 0 1 1 131
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 ADC Select Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins can be reversed by software. This makes IC layout flexible in LCD module assembly. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 0 ADC ADC = 0: normal direction (SEG 1 → SEG 132 ) ADC = 1: reverse direction (SEG 132 → SEG 1 ) Reverse Display ON / OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 1 REV REV RAM bit data = “1” RAM bit data = “0” 0 (normal) LCD pixel is illuminated LCD pixel is not illuminated 1 (reverse) LCD pixel is not illuminated LCD pixel is illuminated Entire Display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the reverse display ON / OFF instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 0 EON EON = 0: normal di splay EON = 1: e ntire di splay O N Select LCD Bias Selects LCD bias ratio of the voltage required for driving the LCD. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 1 B ias LCD biasD uty r atio D UTY 1 D UTY0 B ias = 0 Bias = 1 1/33 0 0 1/ 5 1/6 1/49 0 1 1/ 6 1/8 1/65 1 0 /1 1/ 7 1/9
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD Set Modify-Read This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-read instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 0 0 Reset Modify-Read This instruction cancels the Modify-read mode, and makes the column address return to its initial value just before the set Modify - read instruction is started. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 1 1 1 0 Set Modify- R ead Reset Modify- R ead Set Page Address Data P rocess NO YES Change C omplete ? Set Column Address (N) Dummy R ead Data R ead Data W rite Return C olumn A ddress (N) Figure 25 . Sequence for Cursor Display
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 Reset This instruction resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply which is initialized by the RESETB pin. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 0 SHL Select COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 SHL × × × × : Don ’t care SHL = 0: normal direction (COM 1 → COM 64 ) SHL = 1: reverse direction (COM 64 → COM 1 ) Power control Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 VC VR VF VC VR VF Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD Regulator Resistor Select Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. R efer to the table 15 . RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 R2 R1 R0 R2 R1 R0 1 + ( Rb / Ra ) 0 0 0 1.9 0 0 0 1 2.19 0 1 0 2.55 0 1 1 3.02 1 0 0 3.61 1 0 1 4.35 1 1 0 5.29 1 1 1 6.48 Set Static Indicator State Consists of two bytes instruction. The first byte instruction (set Static Indicator mode) enables the second byte instruction (set Static Indicator r egister) to be valid. The first byte sets the static indicator ON / OFF. When it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this static indicator state is released after setting the data of indicator register. The 1 st Instruction: Set Static Indicator Mode (ON / OFF) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 0 SM SM = 0: static indicator OFF SM = 1: static indicator ON The 2 nd Instruction: Set Static Indicator Register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S1 S0 Status of static indicator output 0 0 OFF 0 1 ON (about 1 second blinking) 1 0 ON (about 0.5 second blinking ) 1 1 ON (always ON)
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 Power Save ( C ompound Instruction) If the entire display ON / OFF instruction is issued during the display OFF state, S6B0721 enters the P ower S ave status to reduce the power consumption to the static power consumption value. According to the status of static indicator mode, power save is entered to one of two modes (sleep and standby mode). When s tatic indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power Save mode is released by the display ON and entire display OFF instruction. Release Standby Mode Power Save OFF (Compound Instruction) [Entire Display OFF] [Display ON] Release Sleep Mode Power Save OFF (Compound Instruction) [Entire Display OFF] [Static Indicator ON] [Display ON] Power Save (Compound Instruction) [Display OFF] [Entire Display ON] Static Indicator OFF Static Indicator O N Sleep Mode [Oscillator C ircuit: OFF] [LCD Power S upply C ircuit: OFF] [All COM / SEG O utputs: V SS ] [Consumption C urrent: < 2 µA] Standby Mode [Oscillator C ircuit: ON] [LCD Power S upply C ircuit: OFF] [All COM/SEG O utputs: V SS ] [Consumption C urrent: < 10 µA] Figure 26 . Power Save Routine
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD Referential Instruction S etup F low (1) End of Initialization Waiting for Stabilizing the LCD Power Levels User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select] Start of Initialization RESETB Pin = “ H ” Waiting for Stabilizing the Power Power O N (V DD - V SS ) Keeping the RESETB Pin = “ L ” User System Setup by External Pins User LCD P ower Setup by Internal Instructions [Voltage Converter ON] User LCD P ower Setup by Internal Instructions [Voltage Regulator ON] User LCD P ower Setup by Internal Instructions [Voltage Follower ON] User LCD P ower Setup by Internal Instructions [Regulator R esistor S elect] [Reference Voltage R egister S et] Waiting for ≥ 1ms Waiting for ≥ 1ms Figure 27 . Initializing with the B uilt-in P ower S upply C ircuits
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 Referential Instruction S etup F low (2) User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select] Start of initialization RESETB pin = “ H ” Waiting for stabilizing the power Power On ( V DD - V SS ) keeping the RESETB pin = “ L ” User System Setup by External pins Set Power Save Release Power Save User LCD P ower Setup by Internal Instructions [Regulator R esistor S elect] [Reference Voltage R egister S et] Waiting for Stabilizing the LCD Power Levels End of Initialization Figure 28 . Initializing without the B uilt-in P ower S upply C ircuits
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD Referential Instruction S etup F low (3) End of Initialization Write Display ON / OFF by Instruction [Display O N / OFF] Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address] End of Data Display Turn Display ON / OFF by Instruction [Display O N / O FF ] Figure 29 . Data D isplaying
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 Referential Instruction S etup F low (4) Turn Display ON / OFF by Instruction [Display O FF ] Optional Status Power OFF (V DD - V SS ) User LCD Power Setup by Internal Instructions [Voltage Follower O FF ] User LCD Power Setup by Internal Instructions [Voltage Regulator O FF ] User LCD Power Setup by Internal Instructions [Voltage Converter O FF ] Waiting for ≥ 50ms Waiting for ≥ 1ms Waiting for ≥ 1ms Figure 30 . Power O FF
Table 19. Absolute Maximum Ratings
- VDD and VLCD are based on V SS = 0V.
- Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied. (VLCD = V0 – VSS)
- If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.
Table 20. DC Characteristics
S6B0721 PRELIMINARY SPEC. VER. 0.1 132 SEG / 6 5 COM DRIVER & CONTROLLER FOR STN LCD Dynamic Current Consumption (1) when the B uilt-in Power C ircuit is OFF (At O perate M ode) ( Ta = 25 °C ) Item Symbol Condition Min. Typ. Max. Unit Pin used Dynamic current consumption (1) IDD1 V DD = 3.0V V0 – V SS = 11.0V 1/65 du ty ratio Display p attern OFF - - 20 µΑ *11 Dynamic Current Consumption (2) when t he built-in power circuit is ON (At operate mode) ( Ta = 25 °C ) Item Symbol Condition Min. Typ. Max. Unit Pin used V DD = 3.0V, quad boosting, V0 – V SS = 11.0V, 1/65 duty ratio, Display pattern OFF, Normal power mode - 70 100 µΑ *1 2 Dynamic current consumption (2) IDD2 V DD = 3.0V, quad boosting, V0 – V SS = 11.0V, 1/65 duty ratio, Display pattern checker, Normal power mode - 95 160 µΑ *1 2 Current Consumption During Power Save M ode ( Ta = 25 °C ) Item Symbol Condition Min. Typ. Max. Unit Pin used Sleep mode current IDDS1 During s leep - - 2.0 µA Standby mode current IDD S 2 During st andby - - 10.0 µA
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD PRELIMINARY SPEC. VER. 0.1 S6B0721 Table 21 . The Relationship between Oscillation Frequency and Frame Frequency Duty Ratio Item F CL F M On-chip oscillator circuit is used F OSC F OSC 2 × 8 × 65 On-chip oscillator circuit is not used External input ( f CL ) F OSC 2 × 65 On-chip oscillator circuit is used F OSC F OSC 2 × 10 × 49 On-chip oscillator circuit is not used External input ( f CL ) F OSC 2 × 49 On-chip oscillator circuit is used F OSC F OSC 2 × 15 × 33 On-chip oscillator circuit is not used External input ( f CL ) F OSC 2 × 33 ( f OSC : oscillation frequency, f CL : display clock frequency, f M : LCD AC signal frequency ) [* Remark Solves] *1 . Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2 . In case of external power supply is applied. *3 . CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, MI , PS, INTRS, HPM, DCDC5B, CLS, CL, M, DISP pins . *4 . DB0 to DB7, M , FRS, DISP, CL pins . *5 . CS1B, CS2, RS, DB [7:0], E_RD, RW_WR, RESETB, MS, MI, PS, INTRS, HPM, DCDC5B, CLS, CL, M, DISP pins. *6 . Applies when the DB [7:0], M, DISP, and CL pins are in high impedance. *7 . Resistance value when ± 0.1[ mA] is applied during the ON status of the output pin SEGn or COMn. RON= ΔV / 0.1 [k Ω ] ( ΔV: voltage change when ± 0.1[ mA] is applied in the ON status.) *8 . See table 21 for the relationship between oscillation frequency and frame frequency. *9 . The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range *10 . On-chip reference voltage source of the voltage regulator circuit to adjust V0. *11,12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON or OFF. The current flowing through voltage regulation resistors ( Ra and Rb) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc.
Figure 31. Display Pattern is O FF
Figure 34. Read / Write Characteristics (8080-series MPU)
Figure 35. Read/Write Characteristics (6800-series Microprocessor)
Figure 36. Serial Interface Characteristics
Figure 56. 130COM ( 1 28COM + 2COMS) ×× 132SEG
Figure 57. TCP Pin Layout