S6B0717X01-XXX0

S6B0717 SAMSUNG | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 65

Technical content

55 COM / 1 00 SEG DRIVER & CONTROLLER FOR STN LCD

January .2000 Ver. 1 .0 Prepared by: Yong - Jin, Jeon Yjjeon@samsung.co.kr Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.

55 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD S6 B0717

S6B0717 Specification Re vision History Version Content Date 0 .0 Apr.1999

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD CO NTENTS

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD INTRODUCTION The S6B0717 is a driver & controller LSI for graphic dot - matrix liquid crystal display systems. It contains 5 5 common and 1 00 segment driver circuits. This chip is connected directly to a microprocessor, accepts serial or 8 - bit parallel display data and stores in an on - chip display data RAM of 65 x 1 00 bits. It provides a high - flexible display section due to 1 - to - 1 correspondence between on - chi p display data RAM bits and LCD panel pixels. And it performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.

FEATURES

− 5 5 common outputs / 1 00 segment outputs On - chip Display Data RAM − Capacity: 65 x 1 00 = 6 ,50 0 bits − Bit data "1": a dot of display is illuminated . − Bit da ta "0": a dot of display is not illuminated . Multi - chip O peration ( M aster, S lave) A vailable Applicable Duty Ratios D uty ratio Applicable LCD bias Maximum display area 1/ 5 5 1/ 8 or 1/ 6 5 5 × 1 00 1/34 1/6 or 1/5 34 × 100 Microprocessor Interface − 8 - bit par allel bi - directional interface with 6800 - series or 8080 - series − Serial interface (only write operation) available On - Chip Low Power A nalog C ircuit − On - chip oscillator circuit − Voltage converter (x2 , x3, x4, x5) − Voltage regulator (temperature coefficie nt: - 0.05%/ °C or external input ) − Voltage follower (LCD b ias: 1/5, 1/6 or 1/8) − E lectronic contrast control function (64 steps) Operating Voltage Range − Supply voltage (V DD ): 2.4 to 3 .6 V − LCD driving voltage (V LCD = V0 - V SS ): 4.0 to 1 5 .0 V Wide O pera ting T emperature R ange − Ta = - 40 °C to 85 °C Low Power Consumption − 100 µΑ Max . (V DD = 3V, x 4 boosting, V0 = 1 1 V, internal power supply ON) − 10 µΑ M ax. (during power save [standby] mode) Package Type − Gold bumped chip or TCP

Product c ode Temp. c oefficient Package Chip t hickness S6B0717X01 - B0CZ 670 µm S6B0717X01 - B0CY COG 470 µm S6B0717X01 - xxX0 670 µm S6B0717X01 - xxXN - 0.05% / °C TCP 470 µm * xx: TCP ordering number

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD BLOCK DIAGRAM MS CL M FRS DISP DUTY V DD V SS HPMB VR INTRS VEXT REF VOUT C1- C1+ C2- C2+ C3 - C 3+ DCDC5B V / C CIRCUIT V / R CIRCUIT V / F CIRCUIT MPU INTERFACE (PARALLEL & SERIAL) INSTRUCTION DECODERBUS HOLDER COLUMN ADDRESS CIRCUIT LINE ADDRESS CIRCUIT PAGE ADDRESS CIRCUIT DISPLAY DATA RAM

65 X 1 00 = 6 ,50 0 Bits

DB6(SCLK) DB7(SID) C68 RESETB PS RW_WR E_RD RS CS2 CS1B OSCILLATOR I/O BUFFER STATUS REGISTER INSTRUCTION REGISTER CLS

56 COMMON

Figure 1 . Block Diagram

ððð ððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððð ððð Y 1 172 28 1 162 29 87258 86 1 S 6B 071 7(TOP VIEW) (0,0) X ðððððððððððððððððððððð - - - - - - - - - - ððððððððððððððððððððððð ðððð - - - - ðððð ðððð - - - - ðððð Figure 2 . S6B0717 Chip Configuration Table 1 . S6B0717 Pad Dimensions Size Item Pad No. X Y Unit Chip size - 9000 2 35 0 1 to 86 90 Pa d pitch 87 to 258 7 0 1 to 86 5 6 11 4 87 to 1 16 108 50 1 17 to 2 28 50 108 Bumped pad size 2 29 to 258 108 50 Bumped pad height 1 to 258 1 7 (Typ.) µm COG Align Key Coordinate ILB Align Key Coordinate 30 µm 30 µm 30 µm (-3855, -500) 30 µm 30 µm 30 µm (+3815, -548) 30µm30µm30µm 60µm30µm 42 µm 108 µm 42µm108µm 42µm108µm 42 µm108 µm

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD PAD CENTER COORDINAT ES Table 2 . P ad Center Coordinates [Unit: µm] No. Name X Y No. Name X Y No. Name X Y

1 DUMMY -3825 -1051 51 C3- 675 -1051 101 COM13 4341 -35

2 FRS -3735 -1051 52 C1- 765 -1051 102 COM12 4341 35

3 M -3645 -1051 53 C1- 855 -1051 103 COM11 4341 105

4 CL -3555 -1051 54 C1+ 945 -1051 104 COM10 4341 175

5 DISP -3465 -1051 55 C1+ 1035 -1051 105 COM9 4341 245

6 VSS -3375 -1051 56 C1+ 1125 -1051 106 COM8 4341 315

7 CS1B -3285 -1051 57 C2+ 1215 -1051 107 COM7 4341 385

8 CS2 -3195 -1051 58 C2+ 1305 -1051 108 COM6 4341 455

9 VDD -3105 -1051 59 C2- 1395 -1051 109 COM5 4341 525

10 E_RD -3015 -1051 60 C2- 1485 -1051 110 COM4 4341 595

11 RESETB -2925 -1051 61 C2- 1575 -1051 111 COM3 4341 665

12 VSS -2835 -1051 62 VDD 1665 -1051 112 COM2 4341 735

13 RS -2745 -1051 63 VEXT 1755 -1051 113 COM1 4341 805

14 RW_WR -2655 -1051 64 REF 1845 -1051 114 COM0 4341 875

15 DB0 -2565 -1051 65 VSS 1935 -1051 115 COMS 4341 945

16 DB1 -2475 -1051 66 V1 2025 -1051 116 DUMMY 4341 1015

17 DB2 -2385 -1051 67 V1 2115 -1051 117 DUMMY 3885 1016

18 DB3 -2295 -1051 68 V2 2205 -1051 118 DUMMY 3815 1016

19 DB4 -2205 -1051 69 V2 2295 -1051 119 DUMMY 3745 1016

20 DB5 -2115 -1051 70 V3 2385 -1051 120 DUMMY 3675 1016

21 DB6 -2025 -1051 71 V3 2475 -1051 121 DUMMY 3605 1016

22 DB7 -1935 -1051 72 V4 2565 -1051 122 DUMMY 3535 1016

23 VSS -1845 -1051 73 V4 2655 -1051 123 SEG0 3465 1016

24 MS -1755 -1051 74 V0 2745 -1051 124 SEG1 3395 1016

25 CLS -1665 -1051 75 V0 2835 -1051 125 SEG2 3325 1016

26 VDD -1575 -1051 76 VR 2925 -1051 126 SEG3 3255 1016

27 DCDC5B -1485 -1051 77 VR 3015 -1051 127 SEG4 3185 1016

28 C68 -1395 -1051 78 VSS 3105 -1051 128 SEG5 3115 1016

29 VSS -1305 -1051 79 VSS 3195 -1051 129 SEG6 3045 1016

30 VSS -1215 -1051 80 PS 3285 -1051 130 SEG7 2975 1016

31 VSS -1125 -1051 81 HPMB 3375 -1051 131 SEG8 2905 1016

32 VSS -1035 -1051 82 VDD 3465 -1051 132 SEG9 2835 1016

33 VSS -945 -1051 83 INTRS 3555 -1051 133 SEG10 2765 1016

34 VSS -855 -1051 84 TEMPS 3645 -1051 134 SEG11 2695 1016

35 VSS -765 -1051 85 VSS 3735 -1051 135 SEG12 2625 1016

36 DUTY -675 -1051 86 DUMMY 3825 -1051 136 SEG13 2555 1016

37 VDD -585 -1051 87 DUMMY 4341 -1015 137 SEG14 2485 1016

38 VDD -495 -1051 88 COM26 4341 -945 138 SEG15 2415 1016

39 VDD -405 -1051 89 COM25 4341 -875 139 SEG16 2345 1016

40 VDD -315 -1051 90 COM24 4341 -805 140 SEG17 2275 1016

41 VDD -225 -1051 91 COM23 4341 -735 141 SEG18 2205 1016

42 VDD -135 -1051 92 COM22 4341 -665 142 SEG19 2135 1016

43 VDD -45 -1051 93 COM21 4341 -595 143 SEG20 2065 1016

44 VOUT 45 -1051 94 COM20 4341 -525 144 SEG21 1995 1016

45 VOUT 135 -1051 95 COM19 4341 -455 145 SEG22 1925 1016

46 VOUT 225 -1051 96 COM18 4341 -385 146 SEG23 1855 1016

47 C3+ 315 -1051 97 COM17 4341 -315 147 SEG24 1785 1016

48 C3+ 405 -1051 98 COM16 4341 -245 148 SEG25 1715 1016

49 C3- 495 -1051 99 COM15 4341 -175 149 SEG26 1645 1016

50 C3- 585 -1051 100 COM14 4341 -105 150 SEG27 1575 1016

Table 2 . P ad Center Coordinates (Continued) [Unit: µm] No. Name X Y No. Name X Y No. Name X Y

151 SEG28 1505 1016 201 SEG78 -1995 1016 251 COM48 -4341 -525

152 SEG29 1435 1016 202 SEG79 -2065 1016 252 COM49 -4341 -595

153 SEG30 1365 1016 203 SEG80 -2135 1016 253 COM50 -4341 -665

154 SEG31 1295 1016 204 SEG81 -2205 1016 254 COM51 -4341 -735

155 SEG32 1225 1016 205 SEG82 -2275 1016 255 COM52 -4341 -805

156 SEG33 1155 1016 206 SEG83 -2345 1016 256 COM53 -4341 -875

157 SEG34 1085 1016 207 SEG84 -2415 1016 257 COMS -4341 -945

158 SEG35 1015 1016 208 SEG85 -2485 1016 258 DUMMY -4341 -1015

159 SEG36 945 1016 209 SEG86 -2555 1016

160 SEG37 875 1016 210 SEG87 -2625 1016

161 SEG38 805 1016 211 SEG88 -2695 1016

162 SEG39 735 1016 212 SEG89 -2765 1016

163 SEG40 665 1016 213 SEG90 -2835 1016

164 SEG41 595 1016 214 SEG91 -2905 1016

165 SEG42 525 1016 215 SEG92 -2975 1016

166 SEG43 455 1016 216 SEG93 -3045 1016

167 SEG44 385 1016 217 SEG94 -3115 1016

168 SEG45 315 1016 218 SEG95 -3185 1016

169 SEG46 245 1016 219 SEG96 -3255 1016

170 SEG47 175 1016 220 SEG97 -3325 1016

171 SEG48 105 1016 221 SEG98 -3395 1016

172 SEG49 35 1016 222 SEG99 -3465 1016

173 SEG50 -35 1016 223 DUMMY -3535 1016

174 SEG51 -105 1016 224 DUMMY -3605 1016

175 SEG52 -175 1016 225 DUMMY -3675 1016

176 SEG53 -245 1016 226 DUMMY -3745 1016

177 SEG54 -315 1016 227 DUMMY -3815 1016

178 SEG55 -385 1016 228 DUMMY -3885 1016

179 SEG56 -455 1016 229 DUMMY -4341 1015

180 SEG57 -525 1016 230 COM27 -4341 945

181 SEG58 -595 1016 231 COM28 -4341 875

182 SEG59 -665 1016 232 COM29 -4341 805

183 SEG60 -735 1016 233 COM30 -4341 735

184 SEG61 -805 1016 234 COM31 -4341 665

185 SEG62 -875 1016 235 COM32 -4341 595

186 SEG63 -945 1016 236 COM33 -4341 525

187 SEG64 -1015 1016 237 COM34 -4341 455

188 SEG65 -1085 1016 238 COM35 -4341 385

189 SEG66 -1155 1016 239 COM36 -4341 315

190 SEG67 -1225 1016 240 COM37 -4341 245

191 SEG68 -1295 1016 241 COM38 -4341 175

192 SEG69 -1365 1016 242 COM39 -4341 105

193 SEG70 -1435 1016 243 COM40 -4341 35

194 SEG71 -1505 1016 244 COM41 -4341 -35

195 SEG72 -1575 1016 245 COM42 -4341 -105

196 SEG73 -1645 1016 246 COM43 -4341 -175

197 SEG74 -1715 1016 247 COM44 -4341 -245

198 SEG75 -1785 1016 248 COM45 -4341 -315

199 SEG76 -1855 1016 249 COM46 -4341 -385

200 SEG77 -1925 1016 250 COM47 -4341 -455

Table 3. Power Su pply P ins Description according to the state of LCD bias. Table 4. LCD D river S upply P ins Description

Table 5. System C ontrol P ins Description The following table depends on the MS status. This pin is used together with the M pin. (multi - chip), the DISP pins must be connected each other. This pin selects the resistors for adjusting V0 voltage level. V0 voltage is controlled by VR pin and external resisti ve divider. This pin is fixed to High or Low.

Table 6. System C ontrol P ins Des cription (Continued) NOTE: DUMMY – These pins should be opend (floated).

Table 7. Microprocessor Interface P ins Description When RESETB is “L”, initialization is executed. DB5 are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”. select is no n - active, DB0 to DB7 may be high impedance.

Table 8. Microprocessor Interface P ins Description (Continued) the falling edge of the E signal. When /RD is “L”, DB0 to DB7 are in an output status. When chip select is not active, DB0 to DB7 may be high impedance.

Table 9. LCD D river O utputs Pin s Description The display data and the M signal control the output voltage of segment driver. The internal scanning data and M signal control the output voltage of common driver.

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD FUNCTIONAL DESCRIPTI ON MICROPROCESSOR INTER FACE Chip Select Input There are CS1B and CS2 pins for chip selection. The S6B0717 can interface with an MPU only when CS1B is “L” and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface S6B0717 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in t able 10 . Table 10 . Parallel / Serial Interface Mode PS Type CS1B CS2 C68 Interface mode H 6800 - series MPU m ode H Parallel CS1B CS2 L 8080 - series MPU mode L Serial CS1B CS2 * × Serial - mode * × : Don't care Parallel Interface (PS = "H") The 8 - bit bi - directional data bus is used in P arallel Interface and the type of MPU is selected by C68 as shown in table 11 . The type of data tr ansfer is determined by signals at RS, E_RD and RW_WR as shown in table 12 . Table 11 . Microprocessor Selection for Parallel Interface C68 CS1B CS2 RS E_RD RW_WR DB0 to DB7 MPU bus H CS1B CS2 RS E RW DB0 to DB7 6800 - series L CS1B CS2 RS /RD /WR DB0 to DB 7 8080 - series Table 12 . Parallel Data Transfer Common 6800 - series 8080 - series RS E_RD (E) RW_WR (RW) E_RD (/RD) RW_WR (/WR)

Description

H H H L H Display data read out H H L H L Display data write L H H L H Register status read L H L H L Writes to i nternal register (instruction)

Serial Interface (PS = "L") When the S6B0717 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8 - bit shift register and the 3 - bit counter are reset. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8 - bit parallel data on the eighth serial clock. Serial data input is display data when RS is high and control data when RS is low. Since the clock signal ( DB6) is easy to be affected by th e external noise caused by the line length, the operation check on the actual machine is recommended. CS1B CS2 SID SCLK RS DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7 Figure 3 . Serial Interface Timing Busy Flag The B usy F lag indicates whether the S6B0717 is operating or not. When DB7 is “H” in r ead s tatus operation, this device is in busy status and will accept only r ead s tatus instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU perf ormance.

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD Data Transfer The S6B0717 uses bus holder and internal data bus for D ata T ransfer with the MPU. When writing data from the MPU to on - chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4 . And when reading data from on - chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. T herefore, the data of the specified address cannot be output with the r ead d isplay d ata instruction right after the address sets, but can be output at the second read of data. RS /WR DB0 to DB7 N D(N) D(N+1) D(N+2) D(N+3) Internal signals MPU signals /WR BUS HOLDER COLUMN ADDRESS N N+1 N+2 N+3 N D(N) D(N+1) D(N+2) D(N+3) Figure 4 . Write Timing

/WR /RD DB0 to DB7 N MPU signals Dummy D(N) D(N+1) Internal signals /WR /RD BUS HOLDER COLUMN ADDRESS N D(N) D(N+1) D(N+2) N N+1 N+2 N+3 Figure 5 . Read Timing

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD DISPLAY DATA RAM (DD RAM) The Display Data RAM stores pixel data for the LCD. It is 65 - row by 1 00 - column addressable arr ay. Each pixel can be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and the 9 th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through DB0 t o DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as shown in figure 6 . The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be wr itten into RAM at the same time as data is being displayed without causing the LCD flicker. COM 0 - - COM 1 - - COM 2 - - COM 3 - - COM 4 - - DB0 0 0 1 - - 0 DB1 1 0 0 - - 1 DB2 0 1 1 - - 0 DB3 1 0 1 - - 0 DB4 0 0 0 - - 1 Display Data RAM LCD Display Figure 6 . RAM - to - LCD Data Transfer Page Address Circuit This circuit is for providing a P age A ddress to D isplay Data RAM shown in figure 8 . It incorporates 4 - bit P age A ddress register changed by only the “Set Page” instruction. Page A ddress 8 (DB3 is “H”, but DB2, DB1 and DB0 are “L”) is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is impossible to access to on - chip RAM. Line Address Circuit This circuit assigns DDRAM a L ine A ddress corresponding to the first line (COM 0 ) of the display. Therefore, by setting line address repeatedly, it is possible to realize t he screen scrolling and page switching without changing the contents of on - chip RAM as shown in figure 8 . It incorporates 6 - bit L ine A ddress register changed by only the Initial Display Line instruction and 6 - bit counter circuit. At the beginning of each L CD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 1 00 - bit RAM data to the display data latch circuit. However, display data of icons are not scrolled becaus e the MPU can not access L ine A ddress of icons.

Column A ddress circuit has a 7 - bit preset counter that provides column address to the Display Data RAM as shown in figure 8 . When set Column Address MSB / LSB instruction is issued, 7 - bit [Y 6 :Y0] is updated. And, since this address is increased by 1 each a r ead or w rite data instruction, microprocessor can access the display data continuously. However, the counter is not incre as ed and locked if a non - existing address above 63 H. It is un locked if a column address is set again by set Column Address MSB / LSB instruction. And the column address counter is independent of page address register. ADC Select instruction makes it possible to invert the relationship between the column address and the segment outputs. It is necessary to rewrite the display data on built - in RAM after issuing ADC Select instruction. Refer to the following figure 7 . SEG output SEG SEG SEG SEG SEG SEG SEG Display data 1 0 1 0 1 1 0 0 LCD panel display LCD panel display ( ADC = 1 ) Figure 7 . The Relationship b etween t he Column Address a nd t he Segment O utputs Segment Control Circuit This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM.

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD Page0 Page2 Page1 Page4 Page3 Page6 Page5 Page7 Page8 Line Address COM Output Page Address DB3 DB0DB1DB2 Data - - - - - - - - - - SEG99 SEG0 SEG1 SEG2 SEG3 SEG4 - - - - - ADC=1 ADC=0Column Address LCD Output DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 00H 08H 07H 06H 05H 04H 03H 02H 01H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 18H 17H 16H 15H 14H 13H 12H 11H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 28H 27H 26H 25H 24H 23H 22H 21H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 38H 37H 36H 35H 34H 33H 32H 31H 39H 3AH 3BH 3CH 3DH 3EH 3FH COM0 COM9 COM8 COM7 COM6 COM5 COM3 COM4 COM2 COM1 COM10 COM19 COM18 COM17 COM16 COM15 COM13 COM14 COM12 COM11 COM20 COM29 COM28 COM27 COM26 COM25 COM23 COM24 COM22 COM21 COM30 COM39 COM38 COM37 COM36 COM35 COM33 COM34 COM32 COM31 COM40 COM49 COM48 COM47 COM46 COM45 COM43 COM44 COM42 COM41 COM50 COM53 COM52 COM51 COMS 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 Start Duty Duty SEG5 SEG98 SEG97 SEG96 SEG95 SEG94 63 62 61 5F60 5E 00 - 02 0403 05 05 04 03 0102 00 5E 5F 60 6261 6301 When the initial display line address is 1C[HEX] Figure 8 . Display Data RAM Map

the voltage converter and display timing generation circuit . Figure 9. V DD vs. f OSC internal timing signal are shown in figure 10 .

Instruction specifies the scanning direction of the common output pins . Table 14. The Relationship between Duty Ratio and Common Output

0 COM[0:16] *NC COM[17:32] 1/34

1 COM[32:16] *NC COM[15:0]

0 COM[0:53] 1/55

1 COM[53:0]

This driver circuit is configured by 56 - c h annel (including 2 COMS channel) common driver and 1 00 - channel segment driver. This LCD panel driver voltage depends on the combination of display data and M signal. COM 0 COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 COM1 0 COM1 1 COM1 2 COM1 3 COM1 4 COM 15 S E G S E G S E G S E G S E G

0 SEG 2

M V SS V SS V SS V SS V SS V SS V DD V SS Figure 11 . Segment and Common Timing

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD POWER SUPPLY CIRCUIT S Th e P ower S upply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. The y are valid only in master operation and controlled by p ower c ontrol instruction. For details, refers to "Instruction Description". Table 13 shows the referenced combinations in using P ower S upply circuits. Table 13 . Recommended Power Supply Combinations U ser Setup Power control (VC VR VF) V/C circuits V/R circuits V/F circuits VOUT V0 V1 to V4 Only the internal power supply circuits are used 1 1 1 ON ON ON Open Open Open Only the voltage regulator circuits and voltage follower circuits are used 0 1 1 OF F ON ON External input Open Open Only the voltage follower circuits are used 0 0 1 OFF OFF ON Open External input Open Only the external power supply circuits are used 0 0 0 OFF OFF OFF Open External input External input

Voltage Converter Circuits The se circuits boost up the electric potential between V DD and V SS to 2, 3, 4 or 5 times toward positive side and boosted voltage is outputted from VOUT pin. [C1 = 1.0 to 4.7 mF] VOUT = 2 × V DD VOUT C3+ C3 - C2+ C2 - C1+ C1 - DCDC5B V DD V DD V SS V DD GND V SS V DD VOUT = 3 × V DD V DD V SS V DD V DD GND V SS V DD VOUT C3+ C3 - C2+ C2 - C1+ C1 - DCDC5B Figure 12 . Two Times Boosting Circu it Figure 13 . Three Times Boosting Circuit VOUT = 4 × V DD V DD V DD V SS + C1 GND V SS V DDV DD V DD V DD V SS + C1 GND V SS V DD VOUT = 5 × V DD GND VOUT C3+ C3 - C2+ C2 - C1+ C1 - DCDC5B VOUT C3+ C3 - C2+ C2 - C1+ C1 - DCDC5B Figure 14 . Four Times Boosting Circuit Figure 15 . Five Times Boosting Circuit

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD Voltage Regulator Circuits The function of the internal V ol tage R egulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational - amplifier circuits shown in figure 16 , it is necessary to be applied internally or externally. For the Eq. 1, we determine V0 by Ra, Rb and V EV . The Ra and Rb are connected internally or externally by INTRS pin. And V EV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is t he value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. V REF voltage at Ta = 25 °C is shown in table 14 - 1 . Rb Ra (63 - α) 162 Table 14 - 1. V REF voltage at Ta = 25 °C REF V REF [V] H (internal) 2. 1 L (external) VEXT Table 14 - 2. Reference Voltage Parameter ( a) S V5 S V4 S V3 S V2 S V1 S V0 Reference voltage p arameter ( a) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 62 1 1 1 1 1 1 63

Figure 16 . Internal V oltage R egulator C ircuit

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD In Case of Using Internal Resistors, Ra and Rb (INTRS = " H") When INTRS pin is “H”, resistor Ra is connected internally between VR pin and V SS , and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 15 . Internal Rb / Ra Ratio de pending on 3 - bit Data (R2 R1 R0) 3 - bit data settings (R2 R1 R0) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 The following figure shows V0 voltage measured by adjusting internal regulator register ratio (Rb / Ra) and 6 - bit electronic volume registers for each temperature coefficient at Ta = 25 °C. 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00 0 8 16 24 32 40 48 56 Electronic volume level [V] (1 1 1) (1 1 0) (1 0 1) (1 0 0) (0 1 1) (0 1 0) (0 0 1) (0 0 0) Figure 17 . Electronic V olume L evel

1. LCD driver voltage, V0 = 10V
2. 6 - bit reference voltage register = (1, 0, 0, 0, 0, 0)
3. M aximum current flowing Ra, Rb = 1 uA

The following table shows the range of V0 depending on the above requirements. Table 16. V0 depending on Electronic Volume Level

between V1 to V4 level and each duty ratio. Table 17. T he Relationship between V1 to V4 level and Duty R atio

Figure 18. When Using all LCD Power Circuits (4 - t ime V/C: O N , V/R: O N , V/F: O N ) Figure 19. When Using s ome LCD Power Circuits (V/C: O FF , V/R: O N , V/F: O N )

Setting RESETB to “L” or Reset instruction can initialize internal function. When RESETB becomes “L”, following procedure is occurred. Display ON / OFF: OFF Entire display ON / OFF: OFF (normal) ADC select: OFF (normal) Reverse display ON / OFF: OFF (normal) Power control register (VC, VR, VF) = (0, 0, 0) LCD bias ratio: 1/ 8(1/55 d uty) , 1/6(1/34 d uty) R ead - m odify - write : OFF SHL select: OFF (normal) Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) D isplay start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = ( 1 , 0, 0) Reference voltage set: OFF Reference voltage control register: ( S V5, S V4, S V3, S V2, S V1, S V0) = (1, 0, 0, 0, 0, 0) When RESET instruction is issued, following procedure is occurred. R ead - m odify - write : OFF Static indicator mode: OFF Static indicator register: (S1, S0) = (0, 0) SHL select: 0 D isplay start line: 0 (first) Column address: 0 Page address: 0 Regulator resistor select register: (R2, R1, R0) = ( 1 , 0, 0) Reference voltage set: OFF Reference voltage control register: ( S V5, S V4, S V3, S V2, S V1, S V0) = (1, 0, 0, 0, 0, 0) While RESETB is “L” or r eset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used.

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD INSTRUCTION DESCRIPT ION Table 18 . Instruction Table × : Don’t care Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Read display data 1 1 Read data Read data from DDRAM Write display data 1 0 Write data Write data into DDRAM Read status 0 1 BUSY ADC ON /OFF RES ETB 0 0 0 0 Read the internal status Display ON / OFF 0 0 1 0 1 0 1 1 1 D ON Turn ON / OFF LCD panel When D ON = 0: display OFF When D ON = 1: display ON Initial display line 0 0 0 1 S T 5 S T 4 S T 3 S T 2 S T 1 S T 0 Specify DDRAM line for COM0 Set r eference v oltage m ode 0 0 1 0 0 0 0 0 0 1 Set r eference v oltage m ode Set r eference v oltage r egister 0 0 × × S V5 S V4 S V3 S V2 S V1 S V0 Set r eference v oltage r egister Set page address 0 0 1 0 1 1 P3 P2 P1 P0 Set page address Set column address MSB 0 0 0 0 0 1 0 Y6 Y5 Y4 Set column address MSB Set column address LSB 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Set column address LSB ADC select 0 0 1 0 1 0 0 0 0 ADC Select SEG output direction When ADC = 0 : normal direction (SEG0 → SEG99) When A DC = 1 : reverse direction (SEG99 → SEG0) Reverse display ON / OFF 0 0 1 0 1 0 0 1 1 REV Select normal / reverse display When REV = 0 : normal display When RE V = 1 : reverse display Entire display ON / OFF 0 0 1 0 1 0 0 1 0 EON Select normal entire display ON When EON = 0 : normal display. When EON = 1 : entire display ON LCD bias select 0 0 1 0 1 0 0 0 1 BIAS Select LCD bias Set modify - read 0 0 1 1 1 0 0 0 0 0 Set modify - read mode Reset modify - read 0 0 1 1 1 0 1 1 1 0 release modify - read mode Reset 0 0 1 1 1 0 0 0 1 0 Initialize the internal functions SHL select 0 0 1 1 0 0 SHL × × × Select COM output direction When SHL = 0 : normal direction (COM0 → COM 53) When SHL = 1: reverse direction (COM53 → COM0) Power control 0 0 0 0 1 0 1 VC VR VF Control power circuit operation Regulator resistor select 0 0 0 0 1 0 0 R2 R1 R0 Select internal resistance ratio of the regulator resistor Set static indicator mode 0 0 1 0 1 0 1 1 0 SM Set static indicator mode Set static indicator register 0 0 × × × × × × S1 S0 Set static indicator register Power s ave - - - - - - - - - - Compound instruction of display OFF and entire display ON Test instruction 0 0 1 1 1 1 × × × × Don't use this instruction.

8 - bit data from D isplay D ata RAM specified by the column address and page address can be read by this instruction. As the column address is incre as ed by 1 automatically after each this instruction, th e micro p rocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display data cannot be read through the serial interface. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 Re ad data Write Display Data 8 - bit data of d isplay d ata from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is incre as ed by 1 automatically so that the microprocessor can continuous ly write data to the addressed page. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 Write data Data write Set Column Address Set Page Address Optional Status Column = Column + 1 NO YESData Write Continue ? Dummy Data Read Set Column Address Set Page Address Optional Status Column = Column + 1 NO YESData Read Continue ? Data Read Column = Column + 1 Figure 22 . Sequence for Writing Display Data Figure 23 . Sequence for Reading Display Data

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD Read Status Indicates t he internal status of the S6B0717 RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BUSY ADC ON / OFF RES ETB 0 0 0 0 Flag Description BUSY The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is acti ve, 1: chip is being busy ADC Indicates the relationship between RAM column address and segment driver. 0: reverse direction (SEG 99 → SEG 0 ), 1: normal direction (SEG 0 → SEG 99 ) ON / OFF Indicates display ON / OFF status 0: display ON, 1: display OFF RES E TB Indicates the initialization is in progress by RESETB signal 0: chip is active, 1: chip is being reset Display ON / OFF Turns the d isplay ON or OFF RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 1 D ON D ON = 1: display ON D ON = 0: display OFF Initial Display Line Sets the line address of display RAM to determine the initial display line . The RAM display data is displayed at the top row (COM 0 ) of LCD panel. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 S T 5 S T 4 S T 3 S T 2 S T 1 S T 0 S T 5 S T 4 S T 3 S T 2 S T 1 S T 0 Line address 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : 1 1 1 1 1 0 62 1 1 1 1 1 1 63

Consists of 2 - byte instruction The 1 st instruction sets reference voltage mode , the 2 nd one updates the contents of reference vol tage register. After second instruction, reference voltage m ode is released. The 1 st Instruction : Set Reference Voltage Select M ode RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 0 0 0 0 0 1 The 2 nd Instruction : Set Reference Voltage R egister RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 × × SV5 S V4 S V3 S V2 S V1 S V0 S V5 S V4 S V3 S V2 S V1 S V0 Reference voltage p arameter ( a) 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 62 1 1 1 1 1 1 63 2 nd Instruction for Register Setting Setting R eference V oltage End 1 st Instruction for Mode Setting Setting R eference V oltage Start Figure 24 . Se quence for Setting the R eference V oltage

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD Set Page Address Sets the P age A ddress of display data RAM from the microprocessor into the P age A ddress register. Any RAM data bit can be accessed when its P age A ddress and column address are specified. Along with the column address, the P age A ddress defines the address of the display RAM to write or read display data. Changing the P age A ddress doesn't effect to the display status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 1 P3 P2 P1 P0 P3 P2 P1 P0 P age 0 0 0 0 0 0 0 0 1 1 : : : : : 0 1 1 1 7 1 0 0 0 8 Set Column Address Sets the C olumn A ddress of display RAM from the microprocessor into the column address register. Along with the C olumn A ddress, the C olumn A ddress defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, column addresses are automatically incre as ed. Set Column Address MSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 Y6 Y5 Y4 Set Column A ddress LSB RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Y6 Y5 Y4 Y3 Y2 Y1 Y0 C olumn address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : : : : : : : 1 1 0 0 0 1 0 98 1 1 0 0 0 1 1 99

Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins can be reversed by software. This makes IC layout flexible in LCD module assembly. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 0 ADC ADC = 0: normal direction (SEG 0 → SEG 99 ) ADC = 1: reverse direction (SEG 99 → SEG 0 ) Reverse Display ON / OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 1 REV REV RAM bit data = “1” RAM bit data = “0” 0 (normal) LCD pixel is illuminated LCD pixel is not illuminated 1 (reverse) LCD pixel is not illuminated LCD pixel is illuminated Entire Display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the displ ay data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the reverse display ON / OFF instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 1 0 EON EON = 0: normal di splay EON = 1: e ntire d isplay O N Select LCD Bias Selects LCD bias ratio of the voltage required for driving the LCD RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 0 0 1 B ias LCD bias D uty r atio D UTY B ias = 0 B ias = 1 1/55 1 1/8 1/6 1/ 34 0 1/6 1/5

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD Set Modify - Read T his instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify - read instruction. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 0 0 Reset Modify - Read This instruction cancels the Modify - read mode, and makes the column address return to its initial value just before the Set Modify - r ead instruction is started. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 1 1 1 0 Set Modify- R ead Reset Modify- R ead Set Page Address Data P rocess NO YES Change C omplete ? Set Column Address (N) Dummy R ead Data R ead Data W rite Return C olumn A ddress (N) Figure 25 . Sequence for Cursor Display

This instruction resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply , which is initialized by the R ESETB pin. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 1 0 0 0 1 0 SHL Select COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 1 0 0 SHL × × × × : Don ’ t care SHL = 0: normal direction (COM 0 → COM 53 ) SHL = 1: reverse direction (COM 53 → COM 0 ) Power Control Selects one of eight power circuit functions by using 3 - bit reg ister. An external power supply and part of internal power supply functions can be used simultaneously. RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 1 VC VR VF VC VR VF Status of internal power supply circuits

1 Internal voltage converter circ uit is OFF

Internal voltage converter circuit is ON

1 Internal voltage regulator circuit is OFF

Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD Regulator Resistor Sele ct Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the table 1 5 . RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 R2 R1 R0 R2 R1 R0 1 + ( Rb / Ra ) 0 0 0 3.0 0 0 1 3.5 0 1 0 4.0 0 1 1 4.5 1 0 0 5.0 1 0 1 5.4 1 1 0 5.9 1 1 1 6.4 Set Static Indicator State Consists of two bytes instruction. The first byte instruction ( s et Static Indicator Mode) enables the second byte instruction ( s et Static Indicator Register) to be valid. The first byte sets the S tatic Indicator ON / OFF . When it is on, the second byte updates the contents of static indicator register without issuing any other instruction and this static indicator state is released after se tting the data of indicator register. The 1 st Instruction: Set Static Indicator Mode (ON / OFF) RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 1 0 1 0 1 1 0 SM SM = 0: static indicator OFF SM = 1: static indicator ON The 2 nd Instruction: Set Static Indicat or Register RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S1 S0 Status of static indicator output 0 0 OFF 0 1 ON (about 1 second blinking) 1 0 ON (about 0.5 second blinking ) 1 1 ON (always ON)

Power Save ( Compound Instruction ) If the entire display ON / OFF instruction is issued during the display OFF state, S6B0717 enters the P ower S ave status to reduce the power consumption to the static power consumption value. According to the status of static indicator mode, P ower S ave is ente red to one of two modes (sleep and standby mode). When s tatic indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power Save mode is released by the display ON & entire display OFF instruction. Release Standby Mode Power Save OFF (Compound Instruction) [Entire Display OFF] Release Sleep Mode Power Save OFF (Compound Instruction) [Entire Display OFF] [Static Indicator ON] Power Save (Compound Instruction) [Display OFF] [Entire Display ON] Static Indicator OFF Static Indicator O N Sleep Mode [Oscillator C ircuit: OFF] [LCD Power S upply C ircuit: OFF] [All COM / SEG O utputs: V SS ] [Consumption C urrent: < 2 µA] Standby Mode [Oscillator C ircuit: ON] [LCD Power S upply C ircuit: OFF] [All COM / SEG O utputs: V SS ] [Consumption C urrent: < 10 µA] Figure 2 6 . Power Save Routine

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD R eferential Instruction Setup Flow (1) End of Initialization Waiting for Stabilizing the LCD Power Levels User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select] Start of Initialization RESETB Pin = “ H ” Waiting for Stabilizing the Power Power O N (V DD - V SS ) Keeping the RESETB Pin = “ L ” User System Setup by External Pins User LCD P ower Setup by Internal Instructions [Voltage Converter ON] User LCD P ower Setup by Internal Instructions [Voltage Regulator ON] User LCD P ower Setup by Internal Instructions [Voltage Follower ON] User LCD P ower Setup by Internal Instructions [Regulator R esistor S elect] [Reference Voltage R egister S et] Waiting for ≥ 1ms Waiting for ≥ 1ms Figure 27 . Initializing with the B uilt - in P ower S upply C ircuits

R eferential Instruction Setup Flow (2) User Application Setup by Internal Instructions [ADC Select] [SHL Select] [LCD Bias Select] Start of Initialization RESETB Pin = “ H ” Waiting for Stabilizing the Power Power O N (V DD - V SS ) Keeping the RESETB Pin = “ L ” User System Setup by External Pins Set Power Save Release Power Save User LCD P ower Setup by Internal Instructions [Regulator R esistor S elect] [Reference Voltage R egister S et] Waiting for Stabilizing the LCD Power Levels End of Initialization Figure 28 . Initializing without the B uilt - in P ower S upply C ircuits

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD R eferential Instruction Setup Flow (3) End of initialization Write Display ON / OFF by Instruction [Display O N / OFF] Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address] End of Data Display Turn Display ON / OFF by Instruction [Display O N / OFF] Figure 29 . Data D isplaying

R eferential Instruction Setup Flow (4) Turn Display ON / OFF by Instruction [Display O FF ] Optional Status Power OFF (V DD -V SS ) User LCD Power Setup by Internal Instructions [Voltage Follower O FF ] User LCD Power Setup by Internal Instructions [Voltage Regulator O FF ] User LCD Power Setup by Internal Instructions [Voltage Converter O FF ] Waiting for ≥ 50ms Waiting for ≥ 1ms Waiting for ≥ 1ms Figure 30 . Power O FF

Table 19. Absolute Maximum Ratings

1. VDD and VLCD are based on V SS = 0V.
2. Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied .(VLCD = V0 – VSS)
3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.

I t is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result.

Table 20. DC Characteristics

S6B0717 5 5 COM / 1 00 SEG DRIVER & CONTRO LLER FOR STN LCD Dynamic Current Consumption (1) when the B uilt - in Power C ircuit is OFF (At O perate M ode) (Ta = 25 °C ) Item Symbol Condition Min. Typ. Max. Unit Pin used Dynamic current consumption (1) IDD1 V DD = 3.0V V0 – V SS = 11.0V 1/55 d uty ratio Display p attern OFF - - 50 µΑ *11 Dynamic Current Consumption (2) when t he B uilt - in P ower C ircuit is ON (At O perate M ode) (Ta = 25 °C ) Item Symbol Condition Min. Typ. Max. Unit Pin used V DD = 3.0V, quad boosting, V0 – V SS = 11.0V, 1/ 55 duty ratio, Display pattern OFF, Normal power mode - - 100 µΑ *1 2 Dynamic current consumption (2) IDD2 V DD = 3.0V, quad boosting, V0 – V SS = 11 .0V, 1/ 5 5 duty ratio, Display pattern checker, Normal power mode - - 160 µΑ *1 2 Current Consumption during Power Save mode (Ta = 25 °C ) Item Symbol Condition Min. Typ. Max. Unit Pin used Sleep mode current IDDS1 During s leep - - 2.0 µA Standby mode cu rrent IDD S 2 During s tandby - - 10.0 µA

Table 21 . The Relationship between Oscillation Frequency and Frame Frequency Duty ratio Item f CL f M On - chip oscillator circuit is used f OSC     f OSC     6 × 55 1/ 55 On - chip oscillator circuit is not us ed External input (f CL ) f OSC     2 × 55 On - chip oscillator circuit is used f OSC     f OSC     10 × 34 1/34 On - chip oscillator circuit is not used External input (f CL ) f OSC     2 × 34 (f OSC : oscillation frequency, f CL : display clock freque ncy, f M : LCD AC signal frequency ) [* Remark Solves] *1 . Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2 . In case of external power supply is applied. *3 . CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, C68 , PS, INTRS, HPM B , REF , DCDC5B, CLS, CL, M, DISP pins . *4 . DB0 to DB7, M , FRS, DISP, CL pins . *5 . CS1B, CS2, RS, DB[7:0], E_RD, RW_WR, RESETB, MS, C68 , PS, INTRS, HPM B , REF, DCDC5B, CLS, CL, M, DISP pins. *6 . Applies when the DB[7:0], M, DISP, and CL pins are in high impedance. *7 . Resistance value when ± 0.1[mA] is applied during the On status of the output pin SEGn or COMn. RON = ΔV / 0.1 [k Ω ] ( ΔV: voltage change when ± 0.1[mA] is ap plied in the ON status.) *8 . See table 21 for the relationship between oscillation frequency and frame frequency. *9 . The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range *10 . On - chip reference voltage source of the voltage regulator circuit to adjust V0. *11,12. Applies to the case where the on - chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built - in power supply circuit is on or off. The current flowing through voltage regulation resistors (Ra and Rb) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc

Figure 31. Display Pattern is O FF

Figure 32. Display Pattern is OFF Figure 33. Display Pattern is Checker

Figure 34. Read / Write C haracteristics (8080 - series MPU)

Figure 35. Read / Write C haracteristics (6800 - series Microprocessor)

Figure 36. Serial Interface Characteristics

Figure 37. Reset Input Timing

CONNECTIONS BETWEEN S6B0717 AND LCD PANE L Single Chip Configuration (1/ 5 5 Duty Configuratio ns) COM 26 COM 0 COMS COMS COM 53 COM 27 S 6B 071 7 ( Bottom View) COM 26 COM 0 COMS COMS COM 53 COM 27 S 6B 071 7 ( Top View) 54 × 1 00 pixels 54 × 1 00 pixels Figure 42 . SHL = 0, ADC = 1 Figure 43 . SHL = 0, ADC = 0 CO M S COM 0 CO M26 CO M27 COM 53 COM S S 6B 071 7 ( Top View) 54 × 1 00 pixels COM 27 COM 53 COMS COMS COM 0 COM26 S 6B 071 7 ( Bottom View) 54 × 1 00 pixels Figure 44 . SHL = 1, ADC = 0 Figure 45 . SHL = 1, ADC = 1

Mu lti ple C hip Configuration - 55COM (54COM + 1COMS) ´ 200SEG (100SEG ´ 2) COM 26 COM 0 COMS COMS COM 53 COM 27 S 6B 071 7 ( Bottom View ) ( Master ) COM 26 COM 0 COMS COMS COM 53 COM 27 S 6B 071 7 ( Bottom View ) ( Slave ) 54 × 2 00 pixels Figure 50 . SHL = 0, ADC = 1 ♦ Connect the following pins of two chips each other - Display clock pins: CL, M - Display c ontrol pin: DISP - LCD power pins: V0, V1, V2, V3, V4 54 × 2 00 pixels COM 27 COM 53 COMS COMS COM 0 COM 26 S 6B 071 7 ( Bottom View ) ( Master ) COM 27 COM 53 COMS COMS COM 0 COM 26 S 6B 071 7 ( Bottom View ) ( Slave ) Figure 51 . SHL = 1, ADC = 0 ♦ Connect the following pins of two chips each other - Display clock pins: CL, M - Display c ontrol pin: DISP - LCD power pins: V0, V1, V2, V3, V4

Figure 56. 110COM (108COM + 2CO MS) ´ 100SEG