S6B0086

S6B0086 SAMSUNG | Alldatasheet

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80 CH SEGMENT / COMMON DRIVER FOR DOT MATRIX LCD

June . 2000 . Ver. 0. 0 S 6B 00 86 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD INTRODUCTION The S6B0086 is an LCD driver LSI which is fabricated by low power CMOS high voltage process technology. In segment driver mode, it can be interfaced in 1-bit serial or 4-bit parallel method by the controller. In common driver mode, dual type mode is applicable. And in seg ment mode application, the power down function reduces power consumption.

FEATURES

• Power supply v oltage: + 5V ± 10 %, + 3V ± 10%
• Supply voltage for display: 6 to 28V (V DD -V EE )
• 4-bit parallel / 1-bit serial data processing (in segment mode)
• Single mode operation / dual mode operation (in common mode)
• Power down function (in segment mode)
• Applicable LCD duty: 1/64 – 1/256
• Interface DRIVERS COM (cascade) SEG (cascade) S6B0086 S6B0086
• High voltage CMOS process
• B are die or TCP available

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 TCP N C N C N C S C S C S C S C S C S C S C S C S C S C S C S C S C S C N C N C N C S6B0086 E R B V E E V V V V C S M D I S P F F B V D D S H L V S S D D R D D M D D L D S I D C L A M S C L E L B #1 #20 * Package Type = 100-TCP-35mm * Input Lead Pitch = 0.80mm * Output Lead Pitch = 0.22mm

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD PAD DIAGRAM (S6B0086 / S6B0086 TCP) SC29 SC28 SC27 SC26 SC25 SC24 SC23 SC22 SC21 SC20 SC19 SC18 SC17 SC16 SC15 SC14 SC13 SC12 SC11 SC10 SC9 SC8 SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC52 SC53 SC54 SC55 SC56 SC57 SC58 SC59 SC60 SC61 SC62 SC63 SC64 SC65 SC66 SC67 SC68 SC69 SC70 SC71 SC72 SC73 SC74 SC75 SC76 SC77 SC78 SC79 SC80 100 SC51 SC50 SC49 SC48 SC47 SC46 SC45 SC44 SC43 SC42 SC41 SC40 SC39 SC38 SC37 SC36 SC35 SC34 SC33 SC32 SC31 SC30 ERB VEE V43 V12 CS M DISPOFFB VDD SHL VSS D4_DR D3_DM D2_DL D1_SID CL2 AMS CL1 ELB S6B0086 Chip size: 4530 × 4390 Pad size: 98 × 98 Unit: µm (0, 0) X Y

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 PAD CENTER COORDINATES (S6B0086 / S6B0086TCP) Coordinates Coordinates CoordinatesPad No. Pad Name X Y Pad No. Pad Name X Y Pad No. Pad Name X Y

1 SC51 -1690 1959 35 V12 -900 -1959 69 SC19 2029 544

2 SC52 -2029 1884 36 V0 -775 -1959 70 SC20 2029 678

3 SC53 -2029 1750 37 VS -600 -1959 71 SC21 2029 812

4 SC54 -2029 1616 38 M -475 -1959 72 SC22 2029 946

5 SC55 -2029 1482 39 DISP0FFB -350 -1959 73 SC23 2029 1080

6 SC56 -2029 1348 40 VDD -225 -1959 74 SC24 2029 1214

7 SC57 -2029 1214 41 SHL -100 -1959 75 SC25 2029 1348

8 SC58 -2029 1080 42 VSS 25 -1959 76 SC26 2029 1482

9 SC59 -2029 946 43 D4_DR 266 -1959 77 SC27 2029 1616

10 SC60 -2029 812 44 D3_DM 470 -1959 78 SC28 2029 1750

11 SC61 -2029 678 45 D2_DL 711 -1959 79 SC29 2029 1884

12 SC62 -2029 544 46 D1_SID 915 -1959 80 SC30 1690 1959

13 SC63 -2029 410 47 CL2 1040 -1959 81 SC31 1529 1959

14 SC64 -2029 276 48 ELB 1165 -1959 82 SC32 1368 1959

15 SC65 -2029 142 49 CL1 1290 -1959 83 SC33 1207 1959

16 SC66 -2029 8 50 ELB 1496 -1959 84 SC34 1046 1959

17 SC67 -2029 -126 51 SC1 2029 -1884 85 SC35 885 1959

18 SC68 -2029 -260 52 SC2 2029 -1735 86 SC36 724 1959

19 SC69 -2029 -394 53 SC3 2029 -1601 87 SC37 563 1959

20 SC70 -2029 -528 54 SC4 2029 -1467 88 SC38 402 1959

21 SC71 -2029 -662 55 SC5 2029 -1333 89 SC39 241 1959

22 SC72 -2029 -797 56 SC6 2029 -1199 90 SC40 80 1959

23 SC73 -2029 -931 57 SC7 2029 -1065 91 SC41 -80 1959

24 SC74 -2029 -1065 58 SC8 2029 -931 92 SC42 -241 1959

25 SC75 -2029 -1199 59 SC9 2029 -797 93 SC43 -402 1959

26 SC76 -2029 -1333 60 SC10 2029 -662 94 SC44 -563 1959

27 SC77 -2029 -1467 61 SC11 2029 -528 95 SC45 -724 1959

28 SC78 -2029 -1601 62 SC12 2029 -394 96 SC46 -885 1959

29 SC79 -2029 -1735 63 SC13 2029 -260 97 SC47 -1046 1959

30 SC80 -2029 -1884 64 SC14 2029 -126 98 SC48 -1207 1959

31 ERB -1479 -1959 65 SC15 2029 8 99 SC49 -1368 1959

32 VEE -1275 -1959 66 SC16 2029 142 100 SC50 -1529 1959

33 V5 -1150 -1959 67 SC17 2029 276

34 V43 -1025 -1959 68 SC18 2029 410

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD BLOCK DIAGRAM V12 V43 VEE M DISP0FFB 80-bit 4-level Driver Output Level Selector 80-bit Driver 80-bit Data Latch/ Common Data bi-directional shift register 20 x 4-bit Segment Data bi-directional Shift Register Clock Control Power Down Function SC1 SC2 SC3 SC78 SC79 SC80 CL1 CL2 CS ELB ERB VSS D4_DR D3_DM D2_DL D1_SID AMS Data Latch Control SCK LCK VDD

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 BLOCK DESCRIPTION Name Function COM / SEG Clock control Generates latch clock (LCK), shift clock (SCK) and control clock timing according to the input of CL1, CL2 and con trol inputs (CS, AMS). In commo n driver application mode, this block generates the shift clock (LCK) for the com mon data Bi-directional shift register. COM / SEG Data latch control Determines the direction of segment data shift, and input data of each Bi-directional shift register. In 4-bit segment data parallel transfer mode, data is shifted by a 4-bit unit. In common driver application mode, data is transferred to the common data shift register directly, which disables this block. SEG Power down function Controls the clock enable state of the current driver according to the input value of enable pin (ELB or ERB). If enable input value is “ Low ” , every clock of the current driver is enabled and the clock control block works. But if enable input is “ High ” , current driver is disabled and the input data value has no effect on the output level. So power consumption can be lowered. SEG Output level selector Controls the output voltage level according to the input control pin (M and DISPOFFB) (refer to PIN DESCRIP TION). COM / SEG 20x4-bit segment data I-directional shift register Stores output data value by shifting the input values. In 1-bit serial interface mode application, all 80 shift clocks (SCK) are needed to store all the display data. But in 4-bit parallel transfer mode application, only 20 clocks are needed. In common driver application mode, this block does not work. SEG 80-bit data latch / common data I-directional shift register In segment driver application mode, the data from the 20x4-bit segment data shift register are latched for segment driver output. In single-type common driver application ,1-bit input data (from DL or DR pin) is shifted and latched by the direction according to the SHL signal input. In dual-type common application mode, 80-bit registers are divided by two blocks and controlled independently (refer to NOTE 3). COM / SEG 80-bit level shifter Voltage level shifter block for high voltage part. The inputs of this block are of logical voltage level and the outputs of this block are at high voltage level value. These values are input in to the driver. SEG 80-bit 4-level driver Selects the output voltage level according to M and latched data value. If the data value is "High" the driver output is at selected voltage level (V0 or V5), and in the reverse case the driver output value is at the non-selected level (V12 or V43). In segment driver application mode, non-selected output value is V2 or V3. and when in common driver application, this value becomes V1 or V4. SEG

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD PIN DESCRIPTION Pin I / O Name Function Interface VDD Logical "High" input port (+5V ± 10%, +3V ± 10%) VSS 0V (GND) VEE Power supply Logical "Low" for high voltage part Power V0, V12, V43, V5 I LCD driver output voltage level Bias supply voltage input to drive the LCD. Bias voltage divided by the resistance is usually used as a supply voltage source (refer to NOTE 2). Power SC1 - SC80 O LCD driver output Display data output pin which corresponds to the respective latch contents. One of V0, V12, V34 and V5 is selected as a display driving voltage source according to the combination of the latched data level and M signal (refer to NOTE 1). LCD CL2 I Data shift clock Clock pulse input for the bi-directional shift register. – In segment driver application mode, the data is shifted to 20 x 4-bit segment data shift The clock pulse, which was input when the enable bit (ELB/ERB) is in not active condition, is invalid. – In common driver application mode, the data is shifted to 80- bit common data bi-directional shift register by the CL1 clock. Hence, this clock pin is not used (Open or connect this pin to VDD). Controller M I AC signal for LCD driver output Alternate signal input pin for LCD driving. Normal frame inversion signal is input in to this pin. Controller CL1 I Data latch clock – In segment driver application mode, this signal is used for latching the shift register contents at the falling edge of this clock pulse. CL1 pulse "High" level initializes power-down function block. – In common driver application mode, CL1 is used as a shifting clock of common output data. Controller DISPOFFB I Display OFF control Control input pin to fix the driver output (SC1~SC80) to V0 level, during "Low" value input. LCD becomes non-selected by V0 level output from every output of segment drivers and every output of common drivers. Controller CS I COM / SEG mode control When CS = "Low", S6B0086 is used as an 80-bit segment driver. When CS = "High", S6B0086 is set to an 80-bit common driver VDD / VSS

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 mode select According to the input value of the AMS and the CS pin, application mode of S6B0086 is differs as shown below. VDD / VSS PIN DESCRIPTION (CONTINUED) Pin I / O Name Function Interface D1_SID, D2_DL, D3_DM, D4_DR I / O Display data input / serial input data / left, right data input output In segment driver application mode, these pins are used as 4-bit data input pin (when 4-bit parallel interface mode : AMS = "Low"), or D1_SID is used as serial data input pin and other pins are not used (connect these to VDD) (when 1-bit serial inter face mode : AMS = "High"). – In common driver application mode, the data is shifted from D2_ DL(D4_DR) to D4_DR(D2_DL), when in single type interface mode (AMS = "Low"). In dual- type application case, the data are shifted from D2_DL and D3_DM (D4_DR and D3_DM) to D4_ DR(D2_DL). In each case the direction of the data shift and the connection of data pins are determined by SHL input (refer to NOTE 3, NOTE 4). Controller SHL Input Shift direction control When SHL = "Low", data is shifted from left to right. When SHL = "High", the direction is reversed. (refer to NOTE3) VDD/VSS ELB, ERB I / O Enable data input/output – In segment driver application mode , the internal operation is enabled only when enable input (ELB or ERB) is “ Low ” (power down function). When several drivers are serially connected, the enable state of each driver is shifted according to the SHL input. Connect these pins as below. - In common driver application mode, power down function is not used. Open these pins. Segment Driver ELB ERB L Output (open) Input (VSS) H Input (VSS) Output (open) 0 0 4-bit parallel interface mode 0 1 1-bit serial interface mode 1 0 Single type application mode 1 1 Dual type application mode COM

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD NOTE 1. Output Level Control Output level (SC1 – SC80) M Latched data DISPOFFB SEG Mode COM Mode L L H V12 (V2) V12 (V1) L H H V0 V5 H L H V43 (V3) V43 (V4) H H H V5 V0 X X L V0 V0

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 NOTE 2. LCD Driving Voltage Application Circuit (1) Segment driver application (CS = “ Low ” ) S6B0086V12 V43 V5 VSS VDD to COM Driver to COM Driver VDD C V0 VEE R R (n-4)R R R SEG1- SEG80 to LCD Panel V0, V5 V2, V3 Selection Level Non-selection Level * n = 9 (when 1/64 duty) to 17 (when 1/256 duty) (2) Common driver application (CS = “ High ” ) S6B0086 V12 V43 V5 VSS VDD to SEG DriverV3 VDD C V0 VEE R R (n-4)R R R COM1- COM80 to LCD Panel V0, V5 V1, V4 Selection Level Non-selection Level * n = 9 (when 1/64 duty) to 17 (when 1/256 duty) VDD

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD NOTE 3. Data Shift Direction according to Control Signals (1) When CS = “ Low ” (segment driver application) mode Data Direction Input Pin first datalast data Shift Direction D1_SID, D2_DL, D3_DM D4_DR 4-Bit Parallel Data Transfer Mode (SEG) L L S C S C S C S C S C S C S C S C S C S C S C S C D D D D D D D D D D D D S C S C S C S C S C S C S C S C S C S C S C S C S C S C S C S C D D D D D D D D first data Shift Direction D1 last data H D D D D S C Last data (D1_SID) first data Shift Direction S C S C S C S C S C S C S C S C S C S C S C S C S C S C S C S C S C S C S C first data Last dataShift Direction 1-Bit Serial Data Transfer Mode (SEG) L H H D1_SID

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 (2) When CS = “ High ” (common driver application) mode Data Direction Input Pin Shift Direction Single-type Application Mode (COM) L L H Dual-type Application Mode (COM) L H H Shift Direction Input Data (D2_DL) S C S C S C S C S C S C S C S C S C S C S C S C Output Data (D4_DR) Input Data (D2_DR) S C S C S C S C S C S C S C S C S C S C S C S C Output Data (D2_DL) Input Data 1 (D2_DL) S C S C S C S C S C S C S C S C S C S C S C S C Output Data (D4_DR) Shift Direction Input Data 2 (D3_DM) Input Data 1 (D4_DR) S C S C S C S C S C S C S C S C S C S C S C S C Output Data (D2_DL) Input Data 2 (D3_DM) Shift Direction D2_DL D4_DR D2_DL, D3_DM D4_DR, D3_DM

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD NOTE 4. Usage of Data Pins Data interface pinCOM / SEG (CS pin) Application mode (AMS pin) SHL D1_SID D2_DL D3_DM D4_DR 4-bit parallel interface mode (AMS = “ Low ” ) X D1 (input) D2 (input2) D3 (input3) D4 (input4) SEG (CS =”Low”) 1-bit serial interface mode (AMS = “ High ” ) X SID (input) Connect to VDD L DL (input) DR (output)single-type application mode (AMS = “ Low ” ) H open DL (output) Open DR (input) L DL (input1) DM (input2) DR (output2) COM (CS = “ High ” ) dual-type application mode (AMS = “ High ” ) H open DL (output2) DM (input2) DR (input1) MAXIMUM ABSOLUTE LIMIT Characteristic Symbol Value Unit Power supply voltage V DD -0.3 – +7.0 Driver supply voltage VLCD 0 – +30 Input voltage VIN -0.3 – V DD + 0.3 V Operating temperature Topr -30 – +85 Storage temperature Tstg -55 – +150 * NOTE: Voltage greater than above may do damage to the circuit.

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086

ELECTRICAL CHARACTERISTICS

(1) Segment Driver Application Characteristic Symbol Test Condition Min. Typ. Max. Unit V DD - 2.7 - 5.5Operating Voltage1 V LCD V IN = V DD - V EE 6 - 28 V IH - 0.8V DD - V DD Input voltage (1) V IL - 0 - 0.2V DD V V OH IOH = -0.4mA V DD -0.4 - - Output voltage (2) V OL IOL = 0.4mA - - 0.4 V Input leakage current 1 (1) IIL1 V IN = V DD to V SS -10 - 10 Input leakage current 2 (3) IIL2 V IN = V DD to V EE -25 - 25 µA On resistance (4) R ON ION = 100 µA - 2 4 k Ω ISTBY f CL1 = 32kHz M = V SS V SS pin - - 100 µA V DD = 5V - - 5 IDD V DD = 3V - - 2 mASupply current (5) IEE f CL1 = 32kHz f M = 80Hz V DD = 5V - - 500 µA NOTES: 1. Applied to CL1, CL2, ELB, ERB, D1_SID - D4_DR, SHL, DISPOFFB, M, CS, AMS pin 2. ELB, ERB pin 3. V0, V12, V43, V5 pin 4. V LCD = V DD - V EE , V0 = V DD = 5V, V5= V EE = -23 V V12 = V DD -2/n(V LCD ), V43 = V EE +2/n(V LCD ), n = 17 (1/256 duty, 1/17 bias) 5. V0 = V DD , V12 = 1.71V(V DD = 5V) or -0.06V (V DD = 3V), V43 = -19.71 V(V DD = 5V) or -19.94V (V DD = 3V), V5 = V EE = -23V, no-load condition (1/256 duty, 1/17 bias) 4-bit parallel interface mode ISTBY : V DD = 5V, f CL2 = 5.12MHz, SHL = V SS , DISPOFFB = V DD , M = V SS , display data pattern = 0000 IDD : V DD = 3V, f CL2 = 4MHz, display data pattern = 0101 V DD = 5 V, f CL2 = 5.12MHz, display data pattern = 0101 IEE : V DD = 5V, f CL2 = 5.12MHz, display data pattern = 0101, V EE pin

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD DC CHARACTERISTICS (CONTINUED) (2) Common Driver Application Characteristic Symbol Test Condition Min. Typ. Max. Unit V DD - 2.7 - 5.5Operating voltage V LCD V IN = V DD - V EE 6 - 28 V IH - 0.8V DD - V DD Input voltage (1) V IL - 0 - 0.2V DD V V OH IOH = -0.4mA V DD -0.4 - -Output voltage (3) V OL IOL = 0.4mA - - 0.4 V Input leakage current 1 (1) IIL1 V IN = V DD to V SS -10 - 10 Input leakage current 2 (2) IIL2 V IN = 0V, V DD = 5V (PULL UP) -50 -125 -250 Input leakage current 3 (4) IIL3 V IN = V DD to V EE -25 - 25 µA On resistance(5) R ON ION = 100 µA - 2 4 k Ω ISTBY f CL1 = 32kHz V SS pin - - 100 V DD = 5V - - 200 IDD V DD = 3V - - 120 Supply current (6) IEE f CL1 = 32kHz f M = 80Hz V DD = 5V - - 150 µA NOTES: 1. Applied to CL1, D2_DL (SHL = LOW), D4_DR (SHL = HIGH), SHL, DISPOFFB, M, CS, AMS pin 2. Pull-up input pins : CL2, D1_SID, D3_DM (AMS = HIGH), ELB (SHL = LOW), ERB (SHL = HIGH) 3. D2_DL (SHL = HIGH ) , D4_DR (SHL = LOW) pin 4. V0, V12, V43, V5 pin 5. V LCD = V DD -V EE , V0 = V DD = 5V, V5 = V EE = -23V V12 = V DD -1/ n(V LCD ), V43 = V EE +1/n(V LCD ), n = 17(1/256 duty, 1/17 bias) 6. V0 = V DD , V12 = 3.35V (V DD = 5V) or 1.47V (V DD = 3V), V43 = -21.35V (V DD = 5 V) or -21.47V (V DD = 3 V), V5 = V EE = -23 V, no-load condition (1/256 duty, 1/17 bias) single-type mode operation : AMS = V SS , SHL = V SS , DISPOFFB = V DD D1_SID = D3_DM = V DD , D4_DR = OPEN, ELB = ERB = OPEN, ISTBY : V DD = 5V, M = V SS , D2_DL = V SS IDD : fM = 80Hz, D2_DL = V DD IEE : fM = 80Hz, D2_DL = V DD

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 AC CHARACTERISTICS (1) Segment Driver Application Characteristic Symbol Test Unit Clock cycle time tCY Duty = 50% 125 - - 250 - - Clock pulse width tWCK - 45 - - 95 - - Clock rise / fall time tR /tF - - - - - - 30 Data set-up time tDS - 30 - - 65 - - Data hold time tDH - 30 - - 65 - - Clock set-up time tCS - 80 - - 120 - - Clock hold time tCH - 80 - - 120 - - ELB Output 60 125 Propagation delay time tPHL ERB Output - - - - 125 ELB Input 30 65 ELB,ERB set-up time tPSU ERB Input 30 - - - - ns DISPOFFB low pulse width tWDL - 1.2 - - 1.2 - - µs DISPOFFB clear time tCD - 100 - - 100 - ns M - OUT propagation delay time tPD1 - - 1.0 - - 1.2 CL1 - OUT propagation delay time tPD2 - - 1.0 - - 1.2 DISPOFFB - OUT propagation delay time tPD3 C L = 15pF - - 1.0 - - - µs

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD AC CHARACTERISTICS (CONTINUED) (2) Common Driver Application Characteristic Symbol Test Unit Clock cycle time tCY Duty = 50% 250 - - 500 - - Clock pulse width tWCK - 45 - - 95 - - Clock rise / fall time tR /tF - - - 50 - - 50 Data set-up time tDS - 30 - - 65 - - Data hold time tDH - 30 - - 65 - - ns DISPOFFB low pulse width tWDL - 1.2 - - 1.2 - - µs DISPOFFB clear time tCD - 100 - - 100 - - Output delay time tDL - - 200 - - 250 ns M – OUT propagation delay time tPD1 - - 1.0 - - 1.2 CL1 - OUT propagation delay time tPD2 - - 1.0 - - 1.2 DISPOFFB - OUT propagation delay time tPD3 C L = 15pF - - 1.0 - - 1.2 µs

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 AC CHARACTERISTICS (CONTINUED) (3) Segment Driver Application Timing CL1 1 2 3 19 20 0.2VDD 0.8VDD tPHL 0.2VDD 0.2VDD tPSU CL2 ELB, ERB (Output 1) ELB, ERB (Input 2) M CL1 0.8VDD 0.2VDD 0.8VDD 0.2VDDtWCK tCH 0.8VDD 0.2VDD tCS tWCK 0.2VDD 0.8VDD0.8VDD 0.2VDD tWCK tF tCY tDS tDH 0.8VDD 0.2VDD tCDtWDL CL2 D1_SID - D4_DR DISP0FFB 0.2VDD 0.8VDD tPD1 0.2VDD tPD2 0.2VDD 0.8VDD tPD3 CL1 DISPOFFB SC1 - SC80 (Latched Data) tR

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD AC CHARACTERISTICS (CONTINUED) (4) Common Driver Application Timing M CL1 0.8VDD 0.2VDD tCY (*1) DI (*1) DO DISP0FFB 0.2VDD 0.8VDD tPD1 0.2VDD tPD2 0.2VDD 0.8VDD tPD3 CL1 DISPOFFB SC1 - SC80 (Latched Data 0.8VDD 0.2VDD tFtF tDH tDS tDWCKH tR 0.8VDD 0.2VDD 0.8VDD 0.2VDD tDL 0.8VDD 0.2VDD tCDtWDL (*1) When in single-type interface mode DI => D2_DL (SHL = L), D4_DR (SHL = H) DO => D4_DR (SHL = L ), D2_DL (SHL = H) When in dual-type interface mode DI => D2_DL and D3_DM (SHL = L), D4_DR and D3_DM (SHL = H) DO => D4_DR (SHL = L), D2_DL (SHL = H)

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 POWER DOWN FUNCTION In the case of cascade connection of segment mode drivers, S6B0086 has a "power down function" In order to reduce the power consumption. SHL Enable input Enable output Current driver status The other drivers status L ERB ELB While ERB ="Low", current driver is enabled. Disabled H ELB ERB While ELB ="Low", current driver is enabled. Disabled * In the case of common driver application, power down function does not work. 1 2 n-1 n 1 2 n-1 n 1 2 n-1 n 1 2 n-1 n 1 2 n-1 NOTES: 1. SHL = High (EBL = Input, ERB = Output) Current S6A0086's ERB must be connected to the next S6A0086's ELB. 2. When in 4-bit parallel interface mode: n = 20 When in 1-bit serial interface mode: n = 80 CL1 CL2 ELB1(input1) ERB1/ELB2 (Output1/Input2) ERB2/ELB3 (Output2/Input3) ERB3/ELB4 (Output3/Input4) ELB4 (Output4)

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD OPERATION TIMING DIAGRAM (1) 4-bit Parallel Mode Interface Segment Driver

• When SHL = "Low" 19 20 1 2 3 SC5 SC1 SC77 SC69SC73 19 20 1 2 SC5 SC1 SC77 SC73 CL2 D1_SID ELB (Input) ERB (Output) CL1 SC1 - SC80 D2_DL SC7 SC3 SC79 SC71SC75 SC7 SC3 SC79 SC75D3_DM SC6 SC2 SC78 SC70SC74 SC6 SC2 SC78 SC74 SC8 SC4 SC80 SC72SC76 SC8 SC4 SC80 SC76D4_DR
• When SHL = “ High ” 19 20 1 2 3 SC76 SC80 SC4 SC12SC8 19 20 1 2 SC76 SC80 SC4 SC8 CL2 D1_SID ERB (Input) ELB (Output) CL1 SC1 - SC80 D2_DL SC74 SC78 SC2 SC10SC6 SC74 SC78 SC2 SC6D3_DM SC75 SC79 SC3 SC11SC7 SC75 SC79 SC3 SC7 SC73 SC77 SC1 SC9SC5 SC73 SC77 SC1 SC5D4_DR

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 (2) 1-bit Serial Mode Interface Segment Driver

• When SHL = “ Low ” 79 80 1 2 3 SC2 SC1 SC80 SC78SC79 79 80 1 2 SC2 SC1 SC80 SC79 CL2 D1_SID ELB (Input) ERB (Output) CL1 SC1 - SC80
• When SHL = “ High ” 79 80 1 2 3 SC79 SC80 SC1 SC3SC2 79 80 1 2 SC79 SC80 SC1 SC2 CL2 D1_SID ERB (Input) ELB (Output) CL1 SC1 - SC80

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD (3) Single-type Interface Mode Common Driver

• When SHL = “ Low ” 79 80 1 2 CL1 79 80 1 2 Current Driver's COMMON area D4_DR COM_DATA1 COM_DATA2 COM_DATA3 COM_DATA79 COM_DATA80 D2_DL
• When SHL = “ High ” 79 80 1 2 CL1 D4_DR D2_DL COM_DATA1 79 80 1 2 COM_DATA3 COM_DATA79 Current Driver's COMMON area COM_DATA80 COM_DATA2

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 (4) DUAL-type Interface Mode Common Driver

• When SHL = “ Low ” CL1 D3_DM D2_DL COM_DATA1 COM_DATA3 COM_DATA39 COM_DATA40 COM_DATA2 1 2 3 39 40 1 2 3 39 40 COM_DATA41 COM_DATA42 COM_DATA43 COM_DATA79 COM_DATA80 D4_DR
• When SHL = “ High ” CL1 D3_DM D2_DL COM_DATA1 COM_DATA3 COM_DATA39 COM_DATA40 COM_DATA2 1 2 3 39 40 1 2 3 39 40 COM_DATA41 COM_DATA42 COM_DATA43 COM_DATA79 COM_DATA80 D4_DR

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD (5) Common / Segment Driver Timing (1/200 DUTY) CL1 M Latched Data (SEG) COM_DATA199 COM_DATA200 199 200 1 199 200 COM_DATA1 200 1 199 200 1 21 18 2019 1 COM1 COM199 COM200 SEG_DATA1 SEG1 CL2 CL1 D1 - D4 Latched_Data M Enable Out

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086

APPLICATION INFORMATION

1-bit Serial Interface Mode (80-C h. Segment Driver) a) Lower View (SHL = L, AMS = H ) S1 S80 S81 S160 SC80 SC1 ERB CS AMS SHL ELB D1_SID LCD PANEL Sn Sn+80 SC80 SC1 ERB CS AMS SHL ELB D1_SID SC80 SC1 ERB CS AMS SHL ELB D1_SID 1-bit serial data input D2_DL- D4_DR D2_DL- D4_DR D2_DL- D4_DR b) Upper View (SHL = H, AMS = H) SHL ELB SC1 AMS LCD PANEL ELB SC1 SC80 ELB CS AMS ERB 1-bit serial data input SC80 D2_DL- D4_DR D1_SID ERB CS D1_SID SHL AMS CS ERB SC80SC1 D1_SID SHL Sn Sn+80S160S81S1 S80 D2_DL- D4_DR D2_DL- D4_DR

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD 4-Bit Parallel Interface Mode (80 C h. Segment Driver) a) Lower View (SHL = L, AMS = L ) S1 S80 S81 S160 SC80 SC1 ERB CS AMS SHL ELB D1_SID-D4_DR LCD PANEL Sn Sn+80 SC80 SC1 ERB CS AMS SHL ELB SC80 SC1 ERB CS AMS SHL ELB 4-bit serial data input 4 D1_SID-D4_DR D1_SID-D4_DR 4 4 b) Upper View (SHL = H, AMS = L) SHL ELB SC1 AMS LCD PANEL ELB SC1 SC80 ELB CS AMS ERB 4-bit serial data input SC80 D1_SID-D4_DR ERB CS D1_SID-D4_DR SHL AMS CS ERB SC80SC1 D1_SID-D4_DR SHL Sn Sn+80S160S81S1 S80 4 44

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 Single-type Interface Mode (80 Ch. Common Driver) LCD PANEL input data 1 SC80 SC1 CS AMS SHL D4_DR D2_DL C80 CS AMS SHL D4_DR D2_DL SC80 SC1 C81 C160 CS AMS SHL D4_DR D2_DL SC1 SC1 C161 C240

S6B0086 80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD Dual-type Interface Mode (40 Ch. + 40 Ch. Common Driver) LCD PANEL (1/2) input data 1 SC80 SC1 CS AMS SHL D4_DR D2_DL CS AMS SHL D4_DR D2_DL SC80 SC1 CS AMS SHL D4_DR D2_DL SC80 SC1 CS AMS SHL D4_DR D2_DL SC80 SC1 CS AMS SHL D4_DR D2_DL D3_DMinput data 2 SC40 SC41 SC80 SC1 C81 C160 C80 C161 C200 C201 C240 C241 C320 C321 C400 LCD PANEL (2/2) NOTE: Using this application mode (dual-type common mode), the duty ratio can be reduced to half. In case , 1/200 duty can be used to drive the 400 common LCD panel.

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD S6B0086 APPLICATION CIRCUIT EXAMPLE S1 S80 V0-V5 DISPOFFB M ELB AMS CS SHL SC1 SC80 D1_SID - D4_DR CL1 CL2 ERB SEG - SEG80 V0-V5 DISPOFFB M ELB AMS CS SHL SC1 SC80 D1_SID - D4_DR CL1 CL2 ERB SEG - SEG80 V0-V5 DISPOFFB M ELB AMS CS SHL SC1 SC80 D1_SID - D4_DR CL1 CL2 ERB SEG - SEG80 S6B0086S6B0086 S6B0086 S81 S160 S161 S240 V0-V5 DISPOFFB M CL1 AMS CS SHL SC1 SC80 D4_DR S6B0086 D2_DL COM1 - COM80 V0-V5 DISPOFFB M CL1 AMS CS SHL SC1 SC80 D4_DR S6B0086 D2_DL COM1 - COM80 V0-V5 DISPOFFB M CL1 AMS CS SHL SC1 SC80 D4_DR S6B0086 D2_DL COM1 - COM80 C80 C81 C161 C161 C240 Controller DISPOFFB FRAME(M) COM_DATA D1 - D4 CL1 CL2 COM /SEG COM SEG SEG COM COM /SEG 4 4 44 4 4 VDD R VEE VSS R (n-4)R R R 240 x 240 LCD MODULE