S6A0065 SAMSUNG | Alldatasheet

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40 CH SEGMENT/COMMON DRIVER FOR DOT MA TRIX LCD S6A0065

The S6A0065 is a LCD driver IC which is fabricated by low power CMOS technology. Basically this IC consists of 20 x 2 bit bi - directional shift register, 20 x 2 bit data latch and 20 x 2 bit driver. (refer to Fig 1) This IC can be used as commo n or segment driver. FUNCTION

  • Dot matrix LCD driver with 40 channel output.
  • Selects function to use common/segment drivers simultaneously.
  • Input / Output signa l - Output: 20 x 2 channel waveform for LCD driving - Input: Serial display data and control signal from the controller LSI. Bias voltage (V 1 - V 6 )

FEATURES

  • Display driving bias: static - 1/5
  • Power supply voltage: 2.7 - 5.5V
  • Supply voltage for display: 3.0 - 13.0V (V LCD = V DD - V EE )
  • Interface Driver (cascade connection) Controller Other S6A0065, S6A2067 S6A0069 S6A0070 S6A00 73
  • CMOS Process
  • 64QFP or bare chip available

Figure 1. S6A0065 Functional Block Diagram

Figure 2. 60 QFP Top View

S6A0065 40 CH SEGMEN T/COMMON DRIVER FOR DOT MATRIX LCD PAD DIAGRAM S6A0065 X Chip size: 2700 × 2190 Pad size: 100 × 100 Unit: µm (0, 0) Y NOTE: (0,0) is center in the chip .

Unit: um PAD PAD COORDINATE PAD PAD COORDINATE NUMBER NAME X Y NUMBER NAME X Y 1 VEE - 1120.2 - 642.5 31 SC28 1117.5 865.2 2 CL1 - 1062.5 - 865.2 32 SC27 992.5 865.2 3 CL2 - 937.5 - 865.2 33 SC26 867.5 865.2 4 VSS - 812.5 - 865.2 34 SC25 742.5 865.2 5 DL1 - 687.5 - 865.2 35 SC24 617.5 865.2 6 DR1 - 562.5 - 865.2 36 SC23 492.5 865.2 7 DL2 - 437.5 - 865.2 37 SC22 367.5 865.2 8 DR2 - 312.5 - 865.2 38 SC21 242.5 865.2 9 M - 187.5 - 865.2 39 SC20 117.5 865.2 10 SHL1 - 62.5 - 865.2 40 S C19 - 7.5 865.2 11 SHL2 62.5 - 865.2 41 SC18 - 132.5 865.2 12 FCS 187.5 - 865.2 42 SC17 - 257.5 865.2 13 V1 332.5 - 865.2 43 SC16 - 382.5 865.2 14 V2 457.5 - 865.2 44 SC15 - 507.5 865.2 15 V3 582.5 - 865.2 45 SC14 - 632.5 865.2 16 V4 707.5 - 865.2 46 SC13 - 757.5 865.2 17 V5 832.5 - 865.2 47 SC12 - 882.5 865.2 18 V6 957.5 - 865.2 48 SC9 - 1120.2 857.2 19 SC40 1082.5 - 865.2 49 SC10 - 1120.2 732.5 20 SC39 1120.2 - 627.5 50 SC11 - 1120.2 607.5 21 SC38 1120.2 - 502.5 51 SC8 - 1120.2 482.5 22 SC37 1120.2 - 377.5 52 SC7 - 11 20.2 357.5 23 SC36 1120.2 - 252.5 53 VDD - 1120.2 232.5 24 SC35 1120.2 - 127.5 54 SC6 - 1120.2 107.5 25 SC30 1120.2 - 2.5 55 SC5 - 1120.2 - 17.5 26 SC31 1120.2 122.5 56 SC4 - 1120.2 - 142.5 27 SC32 1120.2 247.5 57 SC3 - 1120.2 - 267.5 28 SC33 1120.2 372.5 58 SC 2 - 1120.2 - 392.5 29 SC34 1120.2 497.5 59 SC1 - 1120.2 - 517.5 30 SC29 1120.2 622.5

S6A0065 40 CH SEGMEN T/COMMON DRIVER FOR DOT MATRIX LCD PIN DESCRIPTION Pin (No.) I/O Name Description Interface V DD (24) Operating Voltage For logical circuit (2.7 - 5.5V) Power GND(34) Power 0V (GND) Supply V EE ( 31) Negative Supply Voltage For LCD driver circuit V1, V2 (44,45) I Bias Voltage Bias voltage level for LCD drive (select level) Power SC 1 - SC 20 O LCD driver LCD driver output LCD V3, V4 (46, 47) I Part 1 Bias Voltage Bias voltage level for LCD drive (non - select level) Power SHL1(41) I Data interface Selection of the shift direction of Part 1 shift register V DD or V SS DL1, DR1 (35, 36) I/O Data input/output of Part 1 shift register Controller or S6A0065 SC 21 - SC 40 O LCD driver LCD driver output V5, V6 (48, 49) I Part 2 Bias Voltage Bias voltage level for LCD drive (non - select level) Power SHL2(42) I Data interface Selection of the shift direction of Part 2 shift register V DD or V SS DL2,DR2 (37, 38) I/O Data input/output of Part 2 shift register Controller or S6A0065 M (40) I Alternated signal for LCD driver output Controller CL1,CL2 (32,33) I Data shift /latch clock FCS(43) I Mode selection Shift/latch clock of display data and polarity of M signal are changed by FCS signal. By setting FCS to V DD level, user can select the function that use Part 1 as segment driver and Part 2 as common driver simultaneously. NC(39) No connection pin NC SHL2 DL2 DR2 V DD out in V SS in out M latch clock shift clock latch clock shift clock PART FCS M polarttyCL2 V SS CL1 V DD V SS V DD M SHL1 DL1 DR1 V DD out in V SS in out

MAXIMUM ABSOLUTE LIM IT (Ta = 25 °C) Characteristic Symbol Value Unit Operating Voltage V DD - 0.3 to + 7.0 V Driver Supply Voltage V LCD V DD - 15.0 to V DD + 0.3 V Input Voltage 1 V IN1 - 0.3 to V DD + 0.3 V Input Voltage 2 (V 1 - V 6 ) V IN2 V DD + 0. 3 to V EE - 0.3 V Operating Temperature T OPR - 30 to + 85 °C Storage Temperature T SRG - 55 to + 125 °C * Voltage greater than above may damage the circuit * V EE : connect a protection resistor (220 Ω ± 5%) ELECTRICAL CHARACTER ISTICS DC Characteristics (V DD = 2.7 - 5.5V, V DD - V EE = 3 - 13V, V SS = 0V, Ta = - 30 - +85 °C) Characteristic Symbol Test condition Min Max Unit Applicable pin Operating Current * IDD f CL2 = 400kHz - 1 mA - Supply Current * IEE f CL1 = 1kHz - 10 µA Input High Voltage V IH - 0.7V DD V DD V CL1, CL2, DL1, DL2 Input Low Voltage V IL 0 0.3V DD DR1, DR2, S HL1, SHL2 Input Leakage Current ILKG V IN = 0 - V DD - 5 5 µA M, F CS Output High Voltage V OH IOH = - 0.4mA V DD - 0.4 - DL1, DL2, DR1, DR2 Output Low Voltage V OL lOL = +0.4mA - 0.4 V Voltage Descending V D1 ION = 0.1mA for one of SC1 - SC40 - 1.1 V(V1 - V6) - SC(SC1 - SC40) V D2 ION = 0.05mA for each SC1 - SC40 - 1.5 Leaka ge Current IV V IN = V DD  V EE (Output SC1 - SC40 : floating) - 10 10 µA V1 - V6

S6A0065 40 CH SEGMEN T/COMMON DRIVER FOR DOT MATRIX LCD AC Characteristics (V DD = 2.7 to 5.5V, V DD - V EE = 3 to 13V, V SS = 0V, Ta = - 30 to +85 °C) Characteristic Symbol Test condition Min Max Unit Applicable pin Data Shift Frequency f CL - - 400 kHz CL2 Clock High Level Width tWCKH - 800 - CL1, CL2 Clock Low Level Width tWCKL - 800 - CL2 Clock Set - up Time tSL from CL2 to CL1 500 - ns tLS from CL1 to CL2 500 - CL1, CL2 Clock Rise/Fall Time tR /t F - - 200 Data Set - up Time tSU - 300 - DL1, DL2, DR1, DR2, FL M Data Hold Time tDH - 300 - Data Delay Time tD C L = 15pF - 500 DL1, DL2, DR1, DR2 * Input/Output current is excluded; When input is at the intermediate level with CMOS, excessive current flows through the input circuit to the power supply, To avoi d this, input level must be fixed at "H" or "L".

Figure 3. AC characteristics Figure 4. Segment Data Waveform

1) Segment Driver COM1 COM16 S6A0069 (Controller) M LCD common signal segment signal CLK2 CLK1 D SHL1 SHL2 FCS DL1 DR1 DL2 S6A0065 (seg driver) DR2 SC 1 - SC 40 CL1 CL2 M SHL1 SHL2 FCS DL1 DR1 DL2 S6A0065 (seg driver) DR2 SC 1 - SC 40 CL1 CL2 M open 2) Common Driver Controller LCD Common Signal Segment Signal CL2 CL1 FLM FCS SHL1 SHL2 DR1 DL2 S6A0065 (Com Driver) SC1-SC40 CL1 CL2 S6A0065 (Seg Driver) SC 1 -SC 40 S6A0065 (Seg Driver) SC 1 -SC 40 DL1

S6A0065 40 CH SEGMEN T/COMMON DRIVER FOR DOT MATRIX LCD 3) Segment / Common Driver Controller M LCD common signal segment signal CL1 CL2 FLM D SHL1 SHL2 FCS DL1 DR1 DL2 S6A0065 (seg/com driver) SC 2 1 - SC 40 CL1 CL2 M SC 1 - SC 20 SHL1 SHL2 FCS DL1 DR1 S6A0065 (seg driver) DR2 CL1CL2 M SC 1 - SC 40 DL2 open VDD