S6A0031

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8 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

June. 1999. Ver. 0. 5 Prepared by: Tae - Kwang, Park parktk@samsung.co.kr S 6A 003 1 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.

S 6A 003 1 Specification Revision History Ve rsion Content Date 0.0 Original Feb. 1999

0.1 ECKON pad added

Mar.1999 0.2 Page 6: E_RD signal description is changed E_RD: Active low signal for writing command in 6800 mode or high enable signal for reading command in 8 080 mode. → E_RD: Active low signal for writing command or high enable signal for reading command in 6800 mode, low enable signal for reading command in 8080 mode. Apr.1999 0.3 Page 6: LCD DRIVER OUTPUT added Page 18: Power O N / OFF timing added Page 29: IDD1 (V DD = 2.4~3.6V): 150 µA → 50 µA Page 30: IDD1 (V DD = 3.6~5.5V): 250 µA → 80 µA May.1999 0. 4 Page 1, 2, 11 : CGROM character size is changed from 256 to 254. Jun .1999 0.5 Page 6: RW_WR active low - > active high Page 6: RW _WR active low - > low enable Page 20: Wait for more than 1.2us or Busy Check - > delete “ or Busy Check ” Page 21: Wait for more than 1.2us or Busy Check - > delete “ or Busy Check ” Jun .1999

S6A0031 PRELIMINARY S PEC. VER. 0. 5 8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N LCD CO NTENTS

8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N L CD PRELIMINARY S PEC. VER. 0. 5 S6A0031 INTRODUCTION This character driver and controller LSI for liquid crystal do t matrix display systems can display 1 - line of 16 characters with the 5 x 8 dot s format. It is capable of interfacing various microprocessors, supporting the 4 - bit or 8 - bit parallel mode. Voltage follower and bias circuit is built in the IC.

FEATURES

− 8 common outputs / 80 segment outputs Applicable Duty Ratio Font size Display size Duty Contents of outputs 5 x 8 1 - line x 16 characters 1/ 8 1 x 16 characters On - chip Display Data RAM − Character Generator ROM (CGROM): 10,160 bits (254 characters x 5 x 8 dots) − Character Generator RAM (CGRAM): 80 bits (2 characters x 5 x 8 dots) − Display Data RAM (DDRAM): 256 bits (16 characters x 1 - line + 16 extended characters) Microprocessor Interface − 8 - bit parallel interface with 6800 - series or 8080 - s eries MPU − 4 - bit parallel interface with 6800 - series or 8080 - series MPU Function Set − Simple instruction set − COM / SEG bi - directional (4 types LCD application available) − Hardware reset (RESETB) On - chip Analog Circuit − Internal RC oscillator circuit − Voltage fo llower & bias circuit − Automatic p ower o n r eset c ircuit Operating Voltage Range − Supply voltage (V DD ): 2.4 to 5.5 V − LCD driving voltage (V LCD = V0 - V SS ): 6.0V Max. Low Power Consumption Package Type − Gold bumped chip

S6A0031 PRELIMINARY S PEC. VER. 0. 5 8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N LCD BLOCK DIAGRAM Input Buffer Parallel Interface 4 bit/8 bit (6800/8080 -series) Instruction Register (IR)

8 Instruction

(DDRAM) 256 bitsData Register (DR) Character Generator RAM (CGRAM) 80 bits Character Generator ROM (CGROM) 10,160 bits Cursor and Blink Controller Common Driver 8 bits Shift Register Segment Driver 80 bits Latch Circuit 80 bits Shift Register LCD Driving Voltage Selector Segment Data Conversion Voltage Follower & Bias Resistor Timing GeneratorOscillator SEG1 to SEG80 CSB RS RW _WR E _RD DB7 to DB4 DB3 to DB0 RESETB V0 V1 V2 V3 V4DIRS DIRCCK COM1 to COM 8 V DD GND 5 5 8Data Output Register (OR) MI Power On Reset (POR) ECKON Figure 1 . Block Diagram

8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N L CD PRELIMINARY S PEC. VER. 0. 5 S6A0031 PAD CONFIGURATION z X Y (0,0) PAD DUMMY_PAD 130 144 129 136 137 S6A0031 Figure 2 . S6A0031 Chip Configuration Table 1 . S6A0031 Pad Dimensions Size Item Pad No. X Y Unit Chip siz e - 5430 1410 1 to 44 90 Pad pitch 45 to 144 70 1 to 44 5 2 9 2 45 to 59 92 42 60 to 129 4 2 92 Bumped pad size 130 to 144 92 42 Bumped pad height 1 to 144 1 7 (Typ.) µm COG Align Key Coordinate 30 µm 30 µm 30 µm (+2600, +590) 30 µm 30 µm 30 µm (-2600, +605) 30µm30µm30µm 60µm 30µm

S6A0031 PRELIMINARY S PEC. VER. 0. 5 8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N LCD PAD CENTER CO ORDINATES Table 2 . Pad Center Coordinates [Unit: µm] No. Name X Y No. Name X Y No. Name X Y

1 DUMMY -1935 -595 51 COM7 2605 -135 101 SEG47 -455 595

2 VSS -1845 -595 52 COM8 2605 -65 102 SEG48 -525 595

3 VSS -1755 -595 53 SEG1 2605 5 103 SEG49 -595 595

4 VSS -1665 -595 54 SEG2 2605 75 104 SEG50 -665 595

5 ECKON -1575 -595 55 SEG3 2605 145 105 SEG51 -735 595

6 VDD -1485 -595 56 SEG4 2605 215 106 SEG52 -805 595

7 V4 -1395 -595 57 SEG5 2605 285 107 SEG53 -875 595

8 V3 -1305 -595 58 SEG6 2605 355 108 SEG54 -945 595

9 V2 -1215 -595 59 DUMMY 2605 425 109 SEG55 -1015 595

10 V1 -1125 -595 60 DUMMY 2415 595 110 SEG56 -1085 595

11 CK -1035 -595 61 SEG7 2345 595 111 SEG57 -1155 595

12 VDD -945 -595 62 SEG8 2275 595 112 SEG58 -1225 595

13 VDD -855 -595 63 SEG9 2205 595 113 SEG59 -1295 595

14 VDD -765 -595 64 SEG10 2135 595 114 SEG60 -1365 595

15 V0 -675 -595 65 SEG11 2065 595 115 SEG61 -1435 595

16 V0 -585 -595 66 SEG12 1995 595 116 SEG62 -1505 595

17 VDD -495 -595 67 SEG13 1925 595 117 SEG63 -1575 595

18 VDD -405 -595 68 SEG14 1855 595 118 SEG64 -1645 595

19 VDD -315 -595 69 SEG15 1785 595 119 SEG65 -1715 595

20 RESETB -225 -595 70 SEG16 1715 595 120 SEG66 -1785 595

21 RS -135 -595 71 SEG17 1645 595 121 SEG67 -1855 595

22 RW_WR -45 -595 72 SEG18 1575 595 122 SEG68 -1925 595

23 VSS 45 -595 73 SEG19 1505 595 123 SEG69 -1995 595

24 E_RD 135 -595 74 SEG20 1435 595 124 SEG70 -2065 595

25 VDD 225 -595 75 SEG21 1365 595 125 SEG71 -2135 595

26 DB0 315 -595 76 SEG22 1295 595 126 SEG72 -2205 595

27 DB1 405 -595 77 SEG23 1225 595 127 SEG73 -2275 595

28 DB2 495 -595 78 SEG24 1155 595 128 SEG74 -2345 595

29 DB3 585 -595 79 SEG25 1085 595 129 DUMMY -2415 595

30 DB4 675 -595 80 SEG26 1015 595 130 DUMMY -2605 425

31 DB5 765 -595 81 SEG27 945 595 131 SEG75 -2605 355

32 DB6 855 -595 82 SEG28 875 595 132 SEG76 -2605 285

33 DB7 945 -595 83 SEG29 805 595 133 SEG77 -2605 215

34 CSB 1035 -595 84 SEG30 735 595 134 SEG78 -2605 145

35 VSS 1125 -595 85 SEG31 665 595 135 SEG79 -2605 75

36 MI 1215 -595 86 SEG32 595 595 136 SEG80 -2605 5

37 VDD 1305 -595 87 SEG33 525 595 137 DUMMY -2605 -65

38 TEST 1395 -595 88 SEG34 455 595 138 DUMMY -2605 -135

39 VSS 1485 -595 89 SEG35 385 595 139 DUMMY -2605 -205

40 DIRC 1575 -595 90 SEG36 315 595 140 DUMMY -2605 -275

41 VDD 1665 -595 91 SEG37 245 595 141 DUMMY -2605 -345

42 DIRS 1755 -595 92 SEG38 175 595 142 DUMMY -2605 -415

43 VSS 1845 -595 93 SEG39 105 595 143 DUMMY -2605 -485

44 DUMMY 1935 -595 94 SEG40 35 595 144 DUMMY -2605 -555

45 COM1 2605 -555 95 SEG41 -35 595 145

46 COM2 2605 -485 96 SEG42 -105 595 146

47 COM3 2605 -415 97 SEG43 -175 595 147

48 COM4 2605 -345 98 SEG44 -245 595 148

49 COM5 2605 -275 99 SEG45 -315 595 149

50 COM6 2605 -205 100 SEG46 -385 595 150

LCD driving voltage outputs. T hese voltages are generated as following table. Table 3. Pin Description (Continued) oscillator circuit is turne d OFF . When ECKON = " Low " , internal oscillator is used.

Initialization is performed by "Low" level sensing of the RESET B signal. S6A0031 is selected while CSB is "Low". In 6800 - series MPU interface mode, this pin is connected to R/W pin of MPU. read or write command according to RW_WR signal. don ’ t care (connect to " High " , " Low " or open). This pin is not used for normal operation and should be connect to " Low " . *NOTE: DUMMY – These pins should be opened (floated).

DL bit in the instruction register, and 6800 - ser ies MPU or 8080 - series MPU is selected by MI pin. Table 4. Various Kinds of MPU Interface according to MI and DL Bit RW_WR: Read / Write indicating signal in 6800 mode , active high signal for w riting command in 8080 mode. low enable signal for reading command in 8080 mode. transferred from MPU. To select DR or IR register, RS input pin is used. the 3rd reading in 4 - bit bus mode). The dummy cycle make s the address counter (AC) indicate the correct address . internal operation is being processed (Busy Flag). transaction. The DB0 to DB3 pins are floated in this 4 - bit bus mode.

S6A0031 PRELIMINARY S PEC. VER. 0. 5 8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N LCD ADDRESS COUNTER (AC) Ad dress Counter (AC) in S6A0031 stores DDRAM / CGRAM address. After writing into or reading from DDRAM / CGRAM, AC is automatically increased or decreased by 1 according to the entry mode. DISPLAY DATA RAM (DD RAM) DDRAM stores display data of maximum 32 x 8 bits ( 16 characters + 16 extended characters ). DDRAM address is set in the address counter (AC) as a hexadecimal number. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F (a) Display shift is not performed 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 1 0 (b) Display shift left is performed 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1 F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E

(c) Display shift right is performed COM1 COM8 COM1 COM8 COM1 COM8 Figure 7 . DDRAM Address

CGROM has 5 x 8 - dot 254 characters. The CGROM char acter code 00h and 01h are CGRAM character data area. Table 5. CGROM Character Code ( 00 )

CGRAM has up to 5 x 8 - dot 2 characters. By writing font data to CGRAM, user defined character can be used. Table 6. Relationship bet ween Character Code (DDRAM) and Character Pattern (CGRAM)

8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N L CD PRELIMINARY S PEC. VER. 0. 5 S6A0031 LCD DRIVER CIRCUIT LCD Driver circuit has 8 common and 80 segment signals for driving LCD. Data from CGRAM / CGROM are transferred to 80 - bit segment register serially, and then they are stored to 80 - bit shift latch. COM1 to COM 8 have 1/ 8 duty ratio. SEG bi - directional function is selected by DIRS input, and COM shift direction is selected by DIRC input. Table 7 . SEG Data Shift Direction DI RS pin SEG data shift direction Low SEG1 → SEG2 → SEG3 → - - - - - - - → SEG78 → SEG79 → SEG80 High SEG80 → SEG79 → SEG78 → - - - - - - - → SEG3 → SEG2 → SEG1 Table 8 . COM Data Shift Direction DIRC pin COM data shift direction Low COM1 → COM2 → COM3 → - - - - - - - - → COM 6 → COM 7 → COM 8 High COM 8 → COM 7 → COM 6 → - - - - - - - - → COM3 → COM2 → COM1

S6A0031 PRELIMINARY S PEC. VER. 0. 5 8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N LCD INSTRUCTION DESCRIPT ION Table 9 . Instruction Table Instruction RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description * Clear display 0 0 0 0 0 0 0 0 0 1 Write "20H" to DDRAM and set DDRAM address to "00H" from AC Return home 0 0 0 0 0 0 0 0 1 - DDRAM address is set to 00h from AC and the cursor returns to 00h position. The contents of DDRAM are not changed. Entry mode set 0 0 0 0 0 0 0 1 I/D SH Assign cursor moving direction and enable the shift of entire display Display ON / OFF control 0 0 0 0 0 0 1 D C B Set display (D), cursor (C), and blinking of cursor (B) ON / OFF control Cursor or display shift 0 0 0 0 0 1 S/C R/L - - Set cur sor moving and display shift control bit, and the direction, without changing of DDRAM data Function set 0 0 0 0 1 DL - - - - Set interface data length (DL: 4 - bit / 8 - bit) instruction CGRAM address set 0 0 0 1 0 0 A3 A2 A1 A0 Set CGRAM address in address counter. DDRAM address set 0 0 1 0 0 A4 A3 A2 A1 A0 Set DDRAM address in address counter. Read busy flag and address 0 1 BF - - A4 A3 A2 A1 A0 Whether in internal operation or not can be known by reading BF, The contents of address counter can also be r ead Write data 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write data into DDRAM / CGRAM Read data 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data from DDRAM / CGRAM (" - ": Don’t care) NOTES 1. Instruction execution time depends on the internal process time of S6A0031, therefore it is necessary to provide a time larger than one MPU interface cycle time (tc) between execution of two successive instructions. 2. "Clear Display" instruction has 850 µs execution time (when fosc = 4 0.0 kHz), so check the Busy flag or wait for more than 850 µs after using "Clear Display" instruction.

8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N L CD PRELIMINARY S PEC. VER. 0. 5 S6A0031 Clear Display RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 1 Clear all the display data by writing "20H" (space code of CGROM) to all the DDRAM address, and set the DDRAM address to "00H" into AC (address counter). For this instruction, the CGROM address "20H" have to set space code. If the display position has shifted then it return s to the original positions. Namely, when display data is shifted and cursor or blinking is displayed, bring the cursor to the left edge on first line of the display. It makes entry mode to increment (I/D = " High " ) . Return Home RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 - Return Home instruction field makes cursor return home. DDRAM address is set to 00h from AC and the cursor returns to 00h position. The contents of DDRAM are not changed. Entry Mode Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 1 I/D SH Set the moving direction of cursor and display after data writing or readi ng instruction . I/D: Increment / Decrement of DDRAM / CGRAM Address (Cursor or Blink) After DDRAM / CGRAM data write/read operation, DDRAM / CGRAM address is increased (I/D = " High " ) or decreased (I/D = " Low " ) by1. So in case of DDRAM data transfer operat ion and cursor or blink is turned on, cursor or blink moves to right (I/D = " High " ) or left (I/D = " Low " ), but in CGRAM data transfer operation, cursor or blink does not move. SH: Shift of Entire Display When DDRAM read (CGRAM read / write) operation or SH = "Low", entire display is not shift. Only w hen SH = "High" and DDRAM write operation, entire display is shift according to I/D value (I/D = "1": shift left, I/D = "0": shift right). Display O N / O FF Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 D C B Control display / cursor / blink ON / OFF 1 bit register. D: Display ON / OFF Control Bit When D = "High", entire display is turned ON. When D = "Low", entire display is turned OFF, but display data is remained in DDRAM. C: Cursor ON / OFF Control Bit When C = "High", cursor is turned ON. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. B: Cursor Blink ON / OFF Control Bit When B = "High", c ursor blink is ON, that performs alternate between all hig h data (black pattern) and display character at the cursor position. When B = "Low", bl ink is OFF.

correct or search display data (refer to table 10) . Note that display shift is performed simultaneously in all the line. contents of address counter are not changed. Table 10. Shift Patterns According to S/C and R/L Bits When DL = "High", it means 8 - bit bus mode with MPU. When DL = "Low", it means 4 - bit bus mode with MPU. When 4 - bit bus mode, it needs to transfer 4 - bit data by two times. (when I/D = "Low"). The address ranges are 00h to 1Fh.

8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N L CD PRELIMINARY S PEC. VER. 0. 5 S6A0031 Read Busy Flag and Address RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 1 BF - - A4 A3 A2 A1 A0 This instruction shows whether S6A0031 is in internal operation or not. If the resultant BF is "High", it means the internal operation is in progress and you have to wait until BF to be "Low", and then the next instruction can be performed. In this instruction you can read also the value of address counter. Write Data RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Write binary 8 - / 5 - bit data to DDRAM / CGRAM The selection of RAM from DDRAM / CGRAM is set by the previous address set instruction (DDRAM address set, CGRAM address set). After write operation, the address is au tomatically increased / decreased by 1, according to the entry mode. Read Data RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Read binary 8 - / 5 - bit data from DDRAM / CGRAM The selection of RAM is set by the previous address set ins truction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read ope ration, you can get correct RAM data from the second, and the first data would be incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instructio n: it also transfer s RAM data to output data register. After read operation address counter is automatically increased / decreased by 1 according to the entry mode. After CGRAM read operation, display shift may not be executed correctly. * In case of RAM write operation, after this operation, AC is increased / decreased by 1 like read operation. In this time, AC indicates the next address position, but you can read only the previous data by read instruction. RAM address is dummy data, so the correct RAM data come from the second read transaction. After reading operation, the address is increased by 1 automatically.

S6A0031 PRELIMINARY S PEC. VER. 0. 5 8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N LCD INITIALIZING HARDWARE RESET When the power is turned on , S6A0031 is initialized automatically by the p ower on reset circuit ( r efer to figure 8). In case of RESETB pin becomes "Low" and durable the state for more than 1 .2 µs (VDD = 3V), S6A0031 can be initialized too. During the initialization, the following instructions are executed, and BF (Busy Flag) is kept "High" (busy state) to the end of initialization. Display Clear All the DDRAM data is set to "20H" Return Home Address counter = "00H" Entry Mode Set Instruction I/D = 1: A ddress counter is set to increment mode . SH = 0: E ntire display shift is disabled . Display ON / OFF Control Instructi on C = 0: cursor OFF B = 0: blink OFF D = 0: display OFF Function Set Instruction DL = 1 : 8 - bit interface mode CGRAM / DDRAM Address RAM address counter is set to "00H" . tOFF V DD tR DD 0.1V DD 0.9V DD 0.1V DD 0.1V DD V DD Rising Time tR DD ≤ 1 ms Power Off Time tOFF ≥ 1 m s Note: If the upper power conditions are not satisfied in power on/off sequence, the internal power on reset (POR) circuit will not op erates normally. Figure 8 . Power O N / OFF Timing

8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N L CD PRELIMINARY S PEC. VER. 0. 5 S6A0031 Reset Pulse Width tRW 1. 2 µs Reset Time tR 850 µs Note: tRW indicates the minimum RESETB duration for activate internal reset signal tR indicates reset completion time of internal circuit from the start of the internal reset signal (when fosc = 40.0kHz) . tRtRW RESETB Internal R eset T ime Figure 9 . RESET Timing

S6A0031 PRELIMINARY S PEC. VER. 0. 5 8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N LCD INSTRUCTION INITIALI ZING WITH RESET 8 - b it Interface Mode (fosc = 4 0 .0 kHz) RAM Address Set RAM Data Write End of Initialization Command Input Function Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 DL (1) - - - - Entry Mode Set 0 0 0 0 0 0 0 1 I/D SH Display ON / OFF Control 0 0 0 0 0 0 1 D C B Wait until Power is Stable Set Reset (RESETB Pin = "Low") V DD -V SS Power ON Wait for more than 1.2 µs Release Reset (RESETB Pin = "High") Wait for more than 1m s Wait for more than 20ms after V DD rises to 0.9 V DD When just U sing Internal P ower On R eset C ircuit When U sing RESETB Input for Initializing

8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N L CD PRELIMINARY S PEC. VER. 0. 5 S6A0031 4 - b it Interface Mode (fosc = 4 0 .0 kHz) RAM Address Set RAM Data Write End of Initialization Command Input Function Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 DL (0) - - - - Entry Mode Set 0 0 0 0 0 0 - - - - 0 0 0 1 I/D SH - - - - Display ON / OFF Control 0 0 0 0 0 0 - - - - 0 0 1 D C B - - - - Wait until Power is Stable Set Reset (RESETB Pin = "Low") V DD -V SS Power ON Wait for more than 1.2 µs Release Reset (RESETB Pin = "High") Wait for more than 1m s Wait for more than 20ms after V DD rises to 0.9 V DD When just U sing Internal P ower O n R eset C ircuit When U sing RESETB Input for Initializing

S6A0031 PRELIMINARY S PEC. VER. 0. 5 8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N LCD LCD DRIVING POWER SU PPLY CIRCUIT The Power Supply circuit pro duces LCD panel driving voltage at low power consumption. The LCD d riving Power Supply circuit consists of external voltage input and v oltage follower. V DD S 6B 003 1 V SS GND V DD External Power Supply * Recommended Capacitance value is 0. 1 to 4.7 µF O P E N Figure 10 . LCD Driving Power Connection

S6A0031 PRELIMINARY S PEC. VER. 0. 5 8 COM / 80 SEG DRIVER & CONTROLLER FOR ST N LCD FRAME FREQUENCY 1-line Selection Period = 16 Clock Pulses x 4 D ivision One Frame = 64 x 8 x 25 .0 µs = 1 2 .8ms (1 Clock = 2 5 .0 µs at fosc = 4 0 .0 kHz) Frame Frequency = 1 / 1 2 .8ms = 78 Hz V SS COM1

1 FRAME

Figure 1 7 . Frame Frequency

Table 11. Maximum Absolute Rate NOTE : 1 . All the voltage levels are based on V SS = 0V. 2 . Voltage greater than above may damage the circuit.

Table 12. DC Characteristics

Table 12. DC Characteristics (Continued)

Table 13. AC Characteristics (6800 - series Write Instruction)

Table 14. AC Characteristics (8080 - series Write Instruction)

Table 15. AC Characteristics (6800 - series Read Instruction)

Table 16. AC Characteristics (8080 - series read instruction)