S5T8555 SAMSUNG | Alldatasheet
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Technical content
TIME SLOT ASSIGNMENT CIRCUIT S5T8555 INTRODUCTION The S5T8555 is a per channel Time Slot Assignment Circuit (TSAC) that produces 8-bit receive and transmit time slots for four 1 CHIP CODEC. Each frame synchronization pulse may be independently assigned to a time slot in a frame of up to 64 time slots
FEATURES
- Single, 5V operation
- Low power consumption: 5mW
- Controls four 1 CHIP CODEC
- Independent transmit and receive frame syncs
- channel unidirectional mode
- Up to 64 time slots per frame
- Compatible with S5T8554B/7B CODECs
- TTL and CMOS compatible
ORDERING INFORMATION
Device Package Operating Temperature S5T8555X01-L0B0 20 −CERDIP −20 °C to 125 °C 20-CERDIP
S5T8555 TIME SLOT ASSIGNMENT CIRCUIT PIN CONFIGURATION GND FS X 3 CH0 CH1 RSY C /CH2 XSY C BCLK FS X 1 FS R 1 FS X 0 FS R 0 TS X D C CLK C CS 1110 KT8555 V CC FS R 2 FS X 2 FS R 3 MODE S5T8555
TIME SLOT ASSIGNMENT CIRCUIT S5T8555 PIN DISCRIPTION Pin No Symbol Description FS X 0 FS X 1 FS X 2 FS X 3 A Transmit frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid transmit time slot assignment is made. FS R 0 FS R 1 FS R 2 FS R 3 A Receive frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid receive time slot assignment is made. 5 TS X This pin pulls low during any active transmit time slot. (N-channel open drain) 6 D C The input for an 8 bit serial control word. X is the first bit clocked in. 7 CLK C The clock input for the control interface. 8 CS The active-low chip select for the control interface.
9 MODE Mode 1 = Open or V CC
Mode 2 = Gnd
10 GND Ground
11 BCLK The bit clock input (2.048 MHz) 12 XSY C The transmit Time Slot Output sync pulse input. Must be synchronous with BCLK. 13 RSY C /CH2 The receive time slot sync pulse input. Must be synchronous with BCLK. In mode 1 this input is the receive time slot 0 sync pulse, RSY C , which must be synchronous with BCLK. In mode 2 this is the CH2 input for the MSB of the channel select word. 14 CH1 The input for the NSB (next significant bit) of the channel select word.
15 CH0 The input for the LSB (last significant bit) of the channel select word, which defines
the frame sync output affected by the following control word. 20 V CC Power supply pin. 5V ± 5%
S5T8555 TIME SLOT ASSIGNMENT CIRCUIT ABSOLUTE MAXIMUM RATING (T a = 25 °C) Characteristic Symbol Value Unit Positive Supply Voltage V CC 70. V Input Voltage V I V CC + 0.3 ~ −0.3 V Output Voltage V O V CC + 0.3 ~ −0.3 V Operating Temperature Range T OPR − 25 ~ 125 °C Storage Temperature Range T STG − 65 ~ 150 °C Lead Temperature (Soldering, 10 secs) T LEAD 300 °C
TIME SLOT ASSIGNMENT CIRCUIT S5T8555
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted; V CC = 5.0V ± 5%, Ta = 0 °C to 70 °C) Characteristic Symbol Test Conditions Min. Typ. Max. Unit Operating Current ICC BCLK = 2.048MHz, all output open − 1 1.5 mA Input Voltage High V IH − 2.0 − − V Input Voltage Low V IL − − − 0.7 V Input Current 1 II1 All Inputs Except Mode, V IL ≤V IN ≤V IH −1 − 1 µA Input Current 2 II2 Mode, V IN = 0V −100 − − µA Output Voltage High V OH FS X and FS R Outputs, IOH = 3mA 2.4 − − V Output Voltage Low FS X and FS R Outputs, IOH = 3mA − − 0.4 V TS X output, I OL =3mA − − 0.4 V Rise and Fall Time of Clock tR (CK) tF (CK) BCLK, CLK C − − 50 nS Delay to TS X Low tD (TSXL) C L =50pF − − 140 nS Delay to TS X High tD (TSXH) R L =1k Ω 30 − 100 nS Hold Time BCLK to Frame Sync tH (BFS) − 50 − − nS Set-Up Time from Frame Sync BCLK tH (FSB) − 30 − − nS Delay Time from BLCK Low to FS X/R 0-3 High or Low tD C L = 50pF − − 50 nS Hold Time from Channel Select to CLK tH (CSC) − 50 − − nS Set-Up Time from Channel Select to CLK tSU (CSC) − 30 − − nS Period of Clock tCK BCLK, CLK C 240 − − nS Width of Clock High tW (CKH) BCLK, CLK 50 − − nS Width of Clock Low tW (CKL) BCLK, CLK 50 − − nS Set-Up Time from D C to CLK tSU (DCC) − 30 − − nS Hold Time from CLK to D C tH (CDC) − 50 − − nS Set-Up Time from CS to CLK tSU (CC) − 30 − − nS Hold Time from CLK to CS tH (CC) − 100 − − nS
S5T8555 TIME SLOT ASSIGNMENT CIRCUIT TIMING DIAGRAM Figure 1.
APPLICATION INFORMATION
The S5T8555 is a control interface which requires an 8 bit serial control word. Either one of the frame sync output group, FS X 0 to FX X 3 or FS R 0 to FS R 3, affected by the control word is defined by the two bits, X and R. Time slot selected from 0 to 63 is specified. A frame sync output is highly active for one time slot which is equivalent to 8 cycles of BCLK. Up to 64 time slots are allowed to form a frame. There are two operational mode. In mode 1, each channel of transmit and receive direction has different time slot assigned. This mode can be selected by either leaving pin 9 (MODE) opened or connecting it with V CC . In such a case, pin 13 is RSYC input defining the start of each receive frame while four out-put, FS R 0 to FS R 3, are assigned with respect to RSYC. On the other hand, start of each transmit frame is defined by XSYC input by which output FS X 0 to FS X 3, are assigned. XSYC and RSYC can be phase related. Channels from 0-3 are selected by the input CH0 and CH1 (refer to the table 1). X R T5 T4 T3 T2 T1 T0 CH1 CH0 Channel Selected X is the first bit clocked into D C input 0 Assign to FS X 0 and/or FS R 0 Assign to FS X 1 and/or FS R 1 Assign to FS X 2 and/or FS R 2 Assign to FS X 3 and/or FS R 3 1 2 3 4 5 6 7 8 1 2 CLK C CS CH0, CH1 AND CH2 D C BCLK XSYC OR RSY C FS X OR FS R TS X tHCD tH(CC) t SU(CC) tW(CKH) tW(CKL) t R(CK) tF(CK) tH(CC) tSU(CC) tSU(CSC) tH(CSC) tD tSU(DcC) tSU(FSB) tDT(SxL) tWCH t H(BFS) t FSt RS tF(CK) t W(CKL) t R(CK) 3 4 5 6 7 8 tD(TSxH) MIN tD(TSxH) MAX tD OUTPUT CONTROL INTERFACE
In mode 2, all 8 frame sync outputs can be assigned with respect to XSYC input. time slot assigned. For instance, FS X and FSR input of 1 CHIP CODEC are hard wired together. The channel assigned has its channel selected by CH0, CH1 and CH2 (refer to table 2). Table 1. OPERATING CONTROL MODE 1
Figure 4. Digital Interface on a Typical Subscriber Linecard
1 CHIP CODEC #1
1 CHIP CODEC #2
1 CHIP CODEC #3
1 CHIP CODEC #4
1 CHIP CODEC #5
1 CHIP CODEC #6
1 CHIP CODEC #7
1 CHIP CODEC # 0
S5T8555 TIME SLOT ASSIGNMENT CIRCUIT NOTES