S5P4418

Samsung semiconductor

Application Processor

Manufacturer: Samsung semiconductor

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Samsung Electronics Co. Ltd. ( "Samsung") reserves the right to make changes to the information in this publication at any time without prior notice. All information provided is for reference purpose only. Samsung assumes no responsibility for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. This publication on its own does not convey any license , either express or implied, relating to any Samsung and/or third-party products, under the intellectual property rights of Samsung and/or any third parties. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability a rising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. Customers are responsible for their own products and applications. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could reasonably be expected to create a situation where personal injury or death may occur. Customers acknowledge and agree t hat they are solely responsible to meet all other legal and regulatory requirements regarding their applications using Samsung products notwithstanding any information provided in this publication. Customer shall indemnify and hold Samsung and its officers , employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim (including but not limited to personal injury or death ) that may be associated with such unintended , unauthorized and/or illegal use. WARNING No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung. This publication is intended for use by designated recipients only . This publication contains confidential information (including trade secrets) of Samsung protected by Competition Law, Trade Sec rets Protection Act and other related laws, and therefore may not be, in part or in whole, directly or indirectly publicized, distributed, photocopied or used (including in a posting on the Internet where unspecified access i s possible ) by any unauthorized third party. Samsung reserves its right to take any and all measures both in equity and law available to it and claim full damages against any party that misappropriates Samsung 's trade secrets and/or confidential information. 警告本文件仅向经韩国三星电子株式会社授权的人员提供，其内容含有商业秘密保护相关法规规定并受其保护的三星电子株式会社商业秘密，任何直接或间接非法向第三人披露、传播、复制或允许第三人使用该文件全部或部分内容的行为（包括在互联网等公开媒介刊登该商业秘密而可能导致不特定第三人获取相关信息的行为）皆为法律严格禁止。此等违法行为一经发现，三星电子株式会社有权根据相关法规对其采取法律措施，包括但不限于提出损害赔偿请求。 Copyright  2014 Samsung Electronics Co., Ltd. Samsung Electronics Co., Lt. 1-1, Samsungjeonja-ro, Hwaseong-si, Gyeonggi-do, Korea 445-330 Contact Us: mobilesol.cs@samsung.com Home Page: http://www.samsungsemi.com cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

All brand names, trademarks and registered trademarks belong to their respective owners.  Exynos, Exynos 5410, FlexOneNAND, and OneNAND are trademarks of Samsung Electronics.  ARM, Jazelle, TrustZone, and Thumb are registered trademarks of ARM Limited. Cort ex, ETM, ETB, Coresight, ISA, and Neon are trademarks of ARM Limited.  Java is a trademark of Sun Microsystems, Inc.  SD is a registered trademark of Toshiba Corporation.  MMC and eMMC are trademarks of MultiMediaCard Association.  JTAG is a registered trademark of JTAG Technologies, Inc.  Synopsys is a registered trademark of Synopsys, Inc.  I2S is a trademark of Phillips Electronics.  I2C is a trademark of Phillips Semiconductor Corp.  MIPI and Slimbus are registered trademarks of the Mobile Industry Processor Interface (MIPI) Alliance. All other trademarks used in this publication are the property of their respective owners. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

Precaution against Electrostatic Discharge When using semiconductor devices, ensure that the environment is protected against static electricity: 1. Wear antistatic clothes and use earth band. 2. All objects that are in direct contact with devices must be made up of materials that do not produce static electricity. 3. Ensure that the equipment and work table are earthed. 4. Use ionizer to remove electron charge. Contamination Do not use semiconductor products in an environment exposed to dust or dirt adhesion. Temperature/Humidity Semiconductor devices are sensitive to:  Environment  Temperature  Humidity High temperature or humidity deteriorates the characteristics of semiconductor devices. Therefore, do not store or use semiconductor devices in such conditions. Mechanical Shock Do not to apply excessive mechanical shock or force on semiconductor devices. Chemical Do not expose semiconductor devices to chemicals because exposure to chemicals leads to reactions that deteriorate the characteristics of the devices. Light Protection In non- Epoxy Molding Compound (EMC) package, do not expose semiconductor IC to bright light. Exposure to bright light causes malfunctioning of the devices. However, a few special products that utilize light or with security functions are exempted from this guide. Radioactive, Cosmic and X-ray Radioactive substances, cosmic ray, or X-ray may influence semiconductor devices. These substances or rays may cause a soft error during a device operation. Therefore, ensure to shield the semiconductor devices under environment that may be exposed to radioactive substances, cosmic ray, or X-ray. EMS (Electromagnetic Susceptibility) Strong electromagnetic wave or magnetic field may affect the characteristic of semiconductor devices during the operation under insufficient PCB circuit design for Electromagnetic Susceptibility (EMS). cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

Revision History

Revision No. Date Description Author(s) 0.00 Oct. 01, 2014  First draft Chongkun Lee 0.10 Oct. 22, 2014  2nd draft Chongkun Lee cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

Register RW Access Type Conventions Type Definition Description R Read Only The application has permission to read the Register field. Writes to read-only fields have no effect. W Write Only The application has permission to write in the Register field. RW Read & Write The application has permission to read and writes in the Register field. The application sets this field by writing 1'b1 and clears it by writing 1'b0. Register Value Conventions Expression Description x Undefined bit X Undefined multiple bits ? Undefined, but depends on the device or pin status Device dependent The value depends on the device Pin value The value depends on the pin status Reset Value Conventions Expression Description

0 Clears the register field

1 Sets the register field

x Don't care condition Warning: Some bits of control registers are driven by hardware or write operation only. As a result the indicated reset value and the read value after reset might be different. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

Abbreviations/Acronyms Expanded Form ADC Analog Digital Converter DMAC Direct Memory Access Controller ethernet MAC ethernet Media Access Control HDMI High Definition Multimedia Interface I2C Inter-Integrated Circuit I2S Inter-IC Sound JTAG Joint Test Action Group LVDS Low Voltage Differential Signaling MFC Multi Format Codec MPEG-TS Moving Picture Experts Group-Transport Stream NFCON Nand Flash Controller PDM Pulse Density Modulation PPM Pulse Period Measurement for IR remote receiver PWM Pulse Width Modulation RTC Real Time Clock SPDIF Sony Philips Digital Interconnect Format SPI Serial Peripheral Interface SSP Synchronous Serial Port UART Universal Asynchronous Receiver And Transmitter VIP Video Input Processor cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1 Product Overview

1.1 Introduction

S5P4418 is a system-on-a-chip (SoC) based on the 32-bit RISC processor for tablets and cell-phones. Designed with the 28 nm low power process, features of S5P4418 include:  Cortex-A9 Quad core CPU  Highest memory bandwidth  Full HD display  1080p 60 frame video decoding and 1080p 30 frame encoding hardware  3D graphics hardware  High-speed interfaces such as eMMC4.5 and USB 2.0 S5P4418 uses the Cortex-A9 quad core, which is 50 % overall performance higher than Cortex-A8 core. It provides 6.4 GB/s memory bandwidth for heavy traffic operations such as 1080p video encoding and decoding, 3D graphics display and high resolution image signal processing with Full HD display. The application processor supports dynamic virtual address mapping, which helps software engineers to ful ly utilize the memory resources with ease. S5P4418 provides the best 3D graphics performance with wide range of APIs, such as OpenGL ES 1.1, 2.0.Superior 3D performance fully supports Full HD display. The native dual display, in particular, supports Full HD resolution of a main LCD display and 1080p 60 frame HDTV display throughout HDMI, simultaneously. Separate post processing pipeline enables S5P4418 to make a real display scenario. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1.2 Features

 28 nm, HKMG (High-K Metal Gate) Process Technology  513 pin FCBGA Package, 0.65mm Ball Pitch, 17  17 mm Body size  Cortex-A9 Quad Core CPU  High Performance 3D Graphic Accelerator  Full-HD Multi Format Video Codec  Supports various memory: x32 LPDDR2/3, LVDDR3(Low Voltage DDR3), DDR3 up to 800MHz  Supports MLC/SLC NAND Flash with Hardwired ECC algorithm (4/8/12/16/24/40/60-bit)  Supports Dual Display up to 2048x1280, TFT-LCD, LVDS, HDMI 1.4a, MIPI-DSI output  Supports 3ch ITUR.BT 656 Parallel Video Interface and MIPI-CSI  Supports10/100/1000M-bit Ethernet MAC  Supports 3ch SD/MMC, 5ch UARTs,32ch DMAs, 4ch Timer, Interrupt Controller, RTC  Supports 3ch I2S, SPDIF Rx/Tx, 3ch I2C, 3ch SPI, 8ch 12bit ADC, 3ch PWM and GPIOs, 1ch PPM  Supports MPEG-TS Serial/Parallel Interface and MPEG-TS HW Parser  Supports 1ch USB 2.0 Host, 1ch USB 2.0 OTG, 1ch USB HSIC Host  Supports Security functions (AES, DES/TDES, SHA-1, MD5 and PRNG) and Secure JTAG  Supports various Power Mode (Normal, Sleep, Deep-Sleep, Stop)  Supports various boot modes including NAND (with ECC detection and correction), SPI Flash/EEPROM, NOR, USB and UART cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1.3 Block Diagram

cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1.4 Brief Functional Specification

1.4.1 CPU

 Cortex-A9 Quad Core  L1 Cache  32 Kbyte I-Cache, 32 Kbyte D-Cache  L2 Cache  1 Mbyte Shared Cache  Co-Processor  VFP (Vector Floating Point Processor), Neon Processor

1.4.2 Clock &Power Management

 4 Spread-Spectrum PLLs  External Crystal: 24 MHz (for PLL), 32.768 kHz (for RTC)  Supports for various power mode  Normal, Idle, Stop  Suspend to RAM (Sleep, Deep Sleep)

1.4.3 DMA

 32-ch DMAs  Operation Mode  Memory-to-Memory Transfer  Memory to IO Transfer, IO to Memory Transfer

1.4.4 Interrupt Controller

 Vectored Interrupt Controller  Supports 64-ch Interrupt Sources  Supports following features  fixed hardware interrupt priority levels  programmable interrupt priority levels  hardware interrupt priority level masking  programmable interrupt priority level masking  IRQ and FIQ generation  software interrupt generation  test registers  raw interrupt status  interrupt request status cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1.4.5 Timer & Watchdog Timer

 4-ch Timer with Watchdog Timer  Normal interval timer mode with interrupt request  Internal reset signal is activated when the timer count value reaches 0 (time -out)  Level-triggered interrupt mechanism

1.4.6 RTC

 32-bit Counter  Support Alarm Interrupt

1.4.7 Memory Controller

 System Memory Controller  Supports LPDDR2/LPDDR3/LVDDR3(Low Voltage DDR3)/DDR3 SDRAM up to 2 Gbytes  Supports 1.2 V to 1.5 V power  Max Operation Frequency: 800 MHz  Data Bus width: 32-bit  Static Memory Controller  Multiplexed Address: up to 24-bit  SRAM, ROM and NAND Flash  Burst Read/Write  NAND Flash Controller  Supports SLC/MLC NAND Flash  Supports MLC NAND Boot  Hardwired ECC Algorithm  4/8/12/16/24/40/60-bit BCH Error Correction

1.4.8 GPIO Controller

 Various GPIO Interrupt Modes  Rising Edge, Falling Edge, High Level, Low Level Detection  Individual Interrupt Generation cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1.4.9 Ethernet MAC Controller

 Standard Compliance  IEEE 802.3az-2010, for Energy Efficient Ethernet (EEE)  RGMII specification version 2.6 from HP/Marvell  MAC supports the following features  10, 100, and 1000 Mbps data transfer rates with the following PHY interfaces: o RGMII interface to communicate with an external gigabit PHY  Full-duplex operation: o IEEE 802.3x flow control automatic transmission of zero-quanta Pause frame on flow control input de- assertion o Optional forwarding of received Pause frames to the user application  Half-duplex operation: o CSMA/CD Protocol support o Flow control using backpressure support (based on implementation-specific white papers and UNH Ethernet Clause 4 MAC Test Suite - Annex D) o Frame bursting and frame extension in 1000 Mbps half-duplex operation  Preamble and start of frame data (SFD) insertion in Transmit path  Preamble and SFD deletion in the Receive path  Automatic CRC and pad generation controllable on a per-frame basis  Automatic Pad and CRC Stripping options for receive frames  Flexible address filtering modes, such as: o Up to 31 additional 48-bit perfect (DA) address filters with masks for each byte o Up to 96 additional 48-bit perfect (DA) address filters that can be selected in blocks of 32 and 64registers o Up to 31 48-bit SA address comparison check with masks for each byte o 64-bit, 128-bit, or 256-bit Hash filter (optional) for multicast and unicast (DA) addresses o Option to pass all multicast addressed frames o Promiscuous mode to pass all frames without any filtering for network monitoring o Pass all incoming packets (as per filter) with a status report  Programmable frame length to support Standard or Jumbo Ethernet frames with up to 16 KB of size  Programmable Interframe Gap (IFG) (40-96 bit times in steps of 8)  Option to transmit frames with reduced preamble size  Separate 32-bit status for transmit and receive packets  IEEE 802.1Q VLAN tag detection for reception frames  Additional frame filtering: o VLAN tag-based: Perfect match and Hash-based (optional) filtering o Layer 3 and Layer 4-based: TCP or UDP over IPv4 or IPv6  Separate transmission, reception, and control interfaces to the application  MDIO master interface (optional) for PHY device configuration and management  Standard IEEE 802.3az-2010 for Energy Efficient Ethernet  CRC replacement, Source Address field insertion or replacement, and VLAN insertion, replacement, an d deletion in transmitted frames with per-frame control cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  Programmable watchdog timeout limit in the receive path

1.4.10 SD/MMC Controller

 3 Independent SD/MMC Controller and Ports  Secure Digital Memory (SD mem- version 3.0)  Secure Digital I/O (SDIO - version 3.0)  Consumer Electronics Advanced Transport Architecture (CE-ATA - version 1.1)  Multimedia Cards (MMC - version 4.41, eMMC 4.5)  Supports following features of MMC4.41  Support following features of eMMC4.5  Support clock speed up to 50 MHz  Support PIO and DMA mode data transfer  Support 1/4-bit data bus widths  Overlay SPI signals to same GIOs from SSP/SPI controller

1.4.11 PPM

 Pulse Period Measurement for IR remote receiver

1.4.12 PWM

 3-ch PWM Controller  Five 32-bit Timers  Two 8-bit Clock Prescalers providing first level of division for the PCLK, Five Clock Dividers and Multiplexers providing second level of division for the Prescaler clock and Two External Clocks  Programmable Clock Select Logic for individual PWM Channels  Four Independent PWM Channels with Programmable Duty Control and Polarity  Static Configuration: PWM is stopped  Dynamic Configuration: PWM is running  Supports Auto-Reload Mode and One-Shot Pulse Mode  Supports for two external inputs to start PWM  Dead Zone Generator on two PWM Outputs  Supports DMA Transfers  Optional Pulse or Level Interrupt Generation  The PWM has two operation modes:  Auto-Reload Mode o Continuous PWM pulses are generated based on programmed duty cycle and polarity  One-Shot Pulse Mode o Only one PWM pulse is generated based on programmed duty cycle and polarity cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1.4.13 ADC

 8-ch analog input port  Supports following features  Resolution: 12-bit  Conversion rate: 1 MSPS  Input range: 0 to AVDD18  Input frequency: up to 100 kHz  Digital output: CMOS Level (0 to AVDD10)

1.4.14 I2C

 3-ch I2C bus controller  Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; master can operate as master-transmitter or as master-receiver  Serial, 8-bit oriented, bi-directional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode  The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance of 400 pF  Repeated START and early termination function are not support  High speed mode, combined format, 10bit address are not supported

1.4.15 SPI/SSP

 3-ch SPI Controller  Master or slave operation.  Programmable clock bit rate and prescale.  Separate transmit and receive first-in, first-out memory buffers, 16 bits wide, 8 locations deep.  Programmable choice of interface operation, SPI, Microwire, or TI synchronous serial.  SPI Protocol, SSP Protocol, Microwire Protocol  DMA request servicing of the transmit and receive FIFO  Inform the system that a receive FIFO over-run has occurred  Inform the system that data is present in the receive FIFO after an idle period has expired  Only support DMA burst length 4  Maximum SSP CLKGEN's frequency is 100 MHz  SSP Receive Timeout Period: 64 cycle of SSP CLKGEN's clock  Max Operation Frequency  Master Mode: 50 MHz (Receive Data is 20 MHz)  Slave Mode: 8 MHz cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1.4.16 MPEG-TS

 Supports Serial & Parallel MPEG-TS Interface  Supports Hardwired MPEG2-TS parser for Set-top and IPTV

1.4.17 UART& ISO7816 Sim Card Interface

 5-ch UART controller  Programmable use of UART or IrDA SIR input/output.  Separate 32 × 8 transmit and 3 2 ×12 receive First-In, First-Out (FIFO) memory buffers to reduce CPU interrupts.  Programmable FIFO disabling for 1-byte depth.  Programmable baud rate generator. This enables division of the reference clock by (1 × 16) to (65535 × 16) and generates an internal × 16 clock. The divisor can be a fractional number enabling you to use any clock with a frequency >3.6864 MHzas the reference clock.  Standard asynchronous communication bits (start, stop and parity). These are added prior to transmission and removed on reception.  Independent masking of transmit FIFO, receive FIFO, receive timeout, modem status, and error condition interrupts.  Support for Direct Memory Access (DMA).  False start bit detection.  Line break generation and detection.  Support of the modem control functions CTS, DCD, DSR, RTS, DTR, and RI.  Programmable hardware flow control.  Fully-programmable serial interface characteristics:  data can be 5, 6, 7, or 8 bits  even, odd, stick, or no-parity bit generation and detection  1 or 2 stop bit generation  baud rate generation, dc up to UARTCLK/16  IrDA SIR ENDEC block providing:  programmable use of IrDA SIR or UART input/output  support of IrDA SIR ENDEC functions for data rates up to 115200 bps half-duplex  support of normal 3/16 and low-power (1.41-2.23 s) bit durations  programmable division of the UARTCLK reference clock to generate the appropriate bit duration for low - power IrDA mode.  Identification registers that uniquely identify the UART. These can be used by an operating system to automatically configure itself. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1.4.18 USB

 1-ch USB 2.0 Host and 1-ch USB2.0 HSIC Host  fully compliant with the Universal Serial Bus Specification, Revision 1.1, Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 2.0, and the openHCI: Open Host Controller Interface Specification for USB, Release 1.0a. The controller supports high-speed, 480-Mbps transfers (40 times faster than USB 1.1 full-speed mode) using an EHCI Host Controller, as well as full and low speeds through one or more integrated OHCI Host Controllers.  At the USB 2.0 physical interface, the controller provides the following:  UTMI: UTMI+ Level 3, Revision 1.0  High-Speed Inter-Chip (HSIC), Version 1.0  Supports ping and split transactions  UTMI/UTMI+ PHY interface clock supports 30-MHz operation for a 16-bit interface or 60-MHz operation for an 8-bit interface  Heterogeneous selection of UTMI+ or HSIC interfaces per port using strap pins. In Heterogeneous mode, only the 8-bit interface (60 MHz) is supported.  1-ch USB 2.0 OTG Controller  supports both device and host functions and complies fully with the On-The-Go Supplement to the USB 2.0 Specification, Revision 1.3a and Revision 2.0. It can also be configured as a host -only or device-only controller, fully compliant with the USB 2.0 Specification.  Complies with the On-The-Go Supplement to the USB 2.0 Specification (Revision 1.3)  Complies with the On-The-Go Supplement to the USB 2.0 Specification (Revision 2.0)  Software configurable to OTG1.3 and OTG2.0 modes of operation  Support for the following speeds: o High-Speed (HS, 480-Mbps), o Full-Speed (FS, 12-Mbps) and o Low-Speed (LS, 1.5-Mbps) modes  Multiple options available for low power operations  Multiple DMA/non DMA mode access support on the application side  Multiple Interface support on the MAC-Phy  Supports 16 bidirectional endpoints, including control endpoint 0.  Supports Session Request Protocol (SRP)  Supports Host Negotiation Protocol (HNP)  Supports up to 16 host channels. In Host mode, when the number of device endpoints to be supported is more than the number of host channels, software can reprogram the channels to support up to 127 devices, each having 32 endpoints (IN + OUT), for a maximum of 4,064 endpoints.  Includes automatic ping capabilities cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1.4.19 I2S

 3-ch I2S Controller for 5.1-ch Audio output  16-bit/24-bit Master & Slave Mode  Supports various interface mode  I2S, Left-justified, Right-Justified, DSP mode  Supports TDM mode for Digital MIC interface  Supports SPDIF Rx/Tx

1.4.20 AC97

 1-Ch AC97  Independent channels for stereo PCM In, stereo PCM Out, mono MIC In  DMA-based operation and interrupt based operation  All of the channels support only 16-bit samples  Variable sampling rate AC97 Codec interface (48 kHz and below)  16-bit, 16 entry FIFOs per channel  Only primary Codec support

1.4.21 SPDIF Tx, Rx

 SPDIF Tx  Supports linear PCM up to 24-bit per sample  Supports Non-linear PCM formats such as AC3, MPEG1 and MPEG2  2x24-bit buffers which is alternately filled with data  SPDIF Rx  Serial, unidirectional, self-clocking interface  Single wire-single signal interface  Easy to work because it is polarity independent cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1.4.22 PDM

 Supports receiving 2 channel audio data with 1 data pin  1 output clock pin  2 data pins (total 4 channel accepts available)  Fixed output clock frequency  Supports select of the timing of data capture  Supports DMA interface  Supports a user configuration of Coefficient. (Butterworth Low-pass Filter)

1.4.23 Display Controller

 Supports Dual Display  Supports 3 Layers, Gamma Correction and Color Control (Brightness, Contrast, Hue and Saturation)  Supports various Pixel Format  RGB/BGR 444,555,565,888 with/without Alpha channel  Resolution  Up to 2048 x 1280 @60 Hz  Supports various LCD  I80 Interface, RGB, Serial RGB, LVDS output  Supports MIPI-DSI 4 data lanes  HDMI Interface  HDMI 1.4a, HDCP 1.4 Complaint  Supports Video format: o 480p @59.94 Hz/60 Hz, 576p@50 Hz o 720p @50 Hz/59.94 Hz/60 Hz o 1080p @50 Hz/59.94 Hz/60 Hz o Primary 3D Video Formats o Other various formats up to148 MHz Pixel Clock  Supports Color Format: 4:4:4 RGB/YCbCr , 4:2:2 YCbCr  Pixel Repetition: Up to x4  Supports Bit Per Color: 8-bit, 10-bit ,12-bit (NOTE: 16-bit not supported)  Dedicated block for CEC function  Supports: Linear-PCM, Non-linear PCM and high-bitrate audio formats (Audio Sample packets and HBR packets for audio transmission)  Integrated HDCP Encryption Engine for Video/Audio content protection (Authentication procedure are controlled by S/W, not by H/W)  A dedicated CEC module (Separated for power/clock domain separation)  SPDIF Interface and I2S interface for Audio Input  Supports level-triggered Interrupt and SFR for HPD  Supports AES KEY Decryption Function for external HDCP Key management cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  LVDS Interface  Output clock range: 30M to 90 MHz  35:7 data channel compression up to 630Mbps on each LVDS channel  Power down mode  Up to 393.75 Mbytes/sec bandwidth  Falling clock edge data strobe  Narrow bus reduces cable size and cost  PLL requires no external component  6 LVDS output channels (5 data channels, 1 clock channel)  MIPI-DSI  Complies to MIPI DSI Standard Specification V1.01r11 o Maximum resolution ranges up to WUXGA (1920 x 1200) o Supports 1, 2, 3, or 4 data lanes o Supports pixel format: 16 bpp, 18 bpp packed, 18 bpp loosely packed (3 byte format), and 24 bpp  Interfaces o Complies with Protocol-to-PHY Interface (PPI) in 1.5 Gbps MIPI D-PHY o Supports RGB Interface for Video Image Input from display controller o Supports I80 Interface for Command Mode Image input from display controller o Supports PMS control interface for PLL to configure byte clock frequency o Supports Prescaler to generate escape clock from byte clock

1.4.24 Video Post Processor

 3D De-interlace Controller  Fine Scalar for video: Poly-phase filter cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1.4.25 Video Input Processor

 Max. 8192 x 8192 resolution support  Supportsx2 8-bit BT656, 601 format  Supports MIPI-CSI  General Features o Support primary and secondary Image format - YUV420, YUV420(Legacy),YUV420(CSPS), YUV422 of 8-bits and 10-bits - RGB565, RGB666, RGB888 - RAW6, RAW7, RAW8, RAW10, RAW12, RAW14 - Compressed format: 10-6-10, 10-7-10, 10-8-10 - All of User defined Byte-based Data packet o Support embedded byte-based non Image data packet and generic short packets. o Compatible to PPI(Protocol-to-PHY Interface) in MIPI D-PHY Specification o Support 4 channel virtual channel or data interleave  Standard Compliance  Compliant to MIPI CSI2 Standard Specification V1.01r06  D-phy standard specification V1.0

1.4.26 Multi Format MPEG codec

 Decoder  H.264 o BP, MP, HP profile, Level 4.2 up to 1920  1080, 50 Mbps  MPEG4 ASP o Advanced Simple Profile up to 1920  1080, 40 Mbps  H.263 o Profile3 up to 1920  1080, 20 Mbps  VC-1 o SP/MP/AP profile, Level 3 up to 1920  1080, 2048  1024, 45 Mbps  MPEG-1/2 o Main Profile, High Level up to 1920  1080, 80 Mbps  VP8 o up to 1920  1080, 20 Mbps  Theora o up to 1280  720, 20 Mbps  AVS o Jizhun Profile, Level 6.2 up to 1920  1080, 40 Mbps  RV8/9/10 o up to 1920  1080, 40 Mbps  MJPEG o Baseline profile up to 8192  8192 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  Encoder  H.264 o Baseline Profile, Level 4.0 up to 1080p, 20 Mbps  MPEG4 o Simple Profile, Level 5.6 up to 1080p, 20 Mbps  H.263 o Profile3, Level 70 up to 1080p, 20 Mbps  MJPEG o Baseline Profile up to 81928192 1.4.27 3D Graphic Controller  Supports OpenGL|ES 1.0 and 2.0  Supports OpenVG 1.1  GPU is a hardware accelerator for 2D and 3D graphics systems.  The GPU consists of:  one to four Pixel Processors (PPs)  a Geometry Processor (GP)  a Level 2 Cache Controller (L2)  a Memory Management Unit (MMU) for each GP and PP included in the GPU  a Power Management Unit (PMU).  Pixel processor features  each pixel processor used processes a different tile, enabling a faster turnaround  programmable fragment shader  alpha blending  complete non-power-of-2 texture support  cube mapping  fast dynamic branching  fast trigonometric functions, including arctangent  full floating-point arithmetic  frame buffer blend with destination Alpha  indexable texture samplers  line, quad, triangle and point sprites  no limit on program length  perspective correct texturing  point sampling, bilinear, and trilinear filtering  programmable mipmap level-of-detail biasing and replacement  stencil buffering, 8-bit  two-sided stencil  unlimited dependent texture reads cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  4-level hierarchical Z and stencil operations  Up to 512 times Full Scene Anti-Aliasing (FSAA). 4x multisampling times 128xsupersampling  4-bit per texel compressed texture format.  Geometry processor features  programmable vertex shader  flexible input and output formats  autonomous operation tile list generation  indexed and non-indexed geometry input  primitive constructions with points, lines, triangles and quads.  Level 2 cache controller features  sizes of 32 KB  4-way set-associative  supports up to 32 outstanding AXI transactions  implements a standard pseudo-LRU algorithm  cache line and line fill burst size is 64 bytes  supports eight to 64 bytes uncached read bursts and write bursts  128-bit interface to memory sub-system  support for hit-under-miss and miss-under-miss with the only limitation of AXI ordering rules.  MMU features  accesses control registers through the bus infrastructure to configure the memory system.  each processor has its own MMU to control and translate memory accesses that the GPU initiates.  PMU features  programmable power management  powers up and down each GP, PP and Level 2 cache controller separately  controls the clock, isolation and power of each device  provides an interrupt when all requested devices are powered up

1.4.28 Security IP

 On-chip secure boot ROM/RAM  Hardware Crypto Accelerator  DES/TDES, AES, SHA-1, MD5 and PRNG  Supports Secure JTAG cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 1 Product Overview 1-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

1.4.29 Unique Chip ID

 Supports 128-bit Unique Chip ID register

1.4.30 Operating Conditions

 Operation Voltage  Core: 1.0 V  CPU: 1.0 V to 1.3 V  DDR Memory: 1.2 to 1.5 V  I/O: 3.3 V  Operation Temperature  T.B.D

1.4.31 Package

 513 pin FCBGA  Ball Pitch: 0.65 mm  Body Size: 17  17 mm cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2 Mechanical Dimension and I/O Pin Description

2.1 Mechanical Dimension

Figure 2-1 Mechanical Dimension - Bottom View cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.2 FCBGA Ball Map

Figure 2-4 FCBGA Ball Map (Top View) cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Figure 2-5 FCBGA Ball Map (Top View) - Upper Left Side cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Figure 2-6 FCBGA Ball Map (Top View) - Upper Right Side cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Figure 2-7 FCBGA Ball Map (Top View) - Lower Left Side cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Figure 2-8 FCBGA Ball Map (Top View) - Lower Right Side cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3 I/O Function Description

2.3.1 Ball List Table

Table 2-1 Ball Function Table Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 A1 MIPICSI_DNCL K S IO N MIPICSI_DNCL K – – – A2 MIPICSI_DN0 S IO N MIPICSI_DN0 – – – A3 MIPICSI_DN1 S IO N MIPICSI_DN1 – – – A4 MIPICSI_DN2 S IO N MIPICSI_DN2 – – – A5 MIPICSI_DN3 S IO N MIPICSI_DN3 – – – A7 MIPIDSI_DNCL K S IO N MIPIDSI_DNCL K – – – A8 MIPIDSI_DN0 S IO N MIPIDSI_DN0 – – – A9 MIPIDSI_DN1 S IO N MIPIDSI_DN1 – – – A10 MIPIDSI_DN2 S IO N MIPIDSI_DN2 – – – A11 MIPIDSI_DN3 S IO N MIPIDSI_DN3 – – – A12 GMAC_GTXCLK S IO N GPIOE24 GMAC_GTXCLK – – A14 LVDS_TN1 S IO N LVDS_TN1 – – – A15 LVDS_TN2 S IO N LVDS_TN2 – – – A16 LVDS_TNCLK S IO N LVDS_TNCLK – – – A17 LVDS_TN3 S IO N LVDS_TN3 – – – A18 LVDS_TN4 S IO N LVDS_TN4 – – – A20 PLLXTI S I N PLLXTI – – – A22 HDMI_TXN2 S O N HDMI_TXN2 – – – A23 HDMI_TXN1 S O N HDMI_TXN1 – – – A24 HDMI_TXN0 S O N HDMI_TXN0 – – – A25 HDMI_TXNCLK S O N HDMI_TXNCLK – – – B1 MIPICSI_DPCL K S IO N MIPICSI_DPCL K – – – B2 MIPICSI_DP0 S IO N MIPICSI_DP0 – – – B3 MIPICSI_DP1 S IO N MIPICSI_DP1 – – – B4 MIPICSI_DP2 S IO N MIPICSI_DP2 – – – B5 MIPICSI_DP3 S IO N MIPICSI_DP3 – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 B7 MIPIDSI_DPCL K S IO N MIPIDSI_DPCL K – – – B8 MIPIDSI_DP0 S IO N MIPIDSI_DP0 – – – B9 MIPIDSI_DP1 S IO N MIPIDSI_DP1 – – – B10 MIPIDSI_DP2 S IO N MIPIDSI_DP2 – – – B11 MIPIDSI_DP3 S IO N MIPIDSI_DP3 – – – B12 GMAC_CRS S IO N GPIOE23 GMAC_CRS – – B14 LVDS_TP1 S IO N LVDS_TP1 – – – B15 LVDS_TP2 S IO N LVDS_TP2 – – – B16 LVDS_TPCLK S IO N LVDS_TPCLK – – – B17 LVDS_TP3 S IO N LVDS_TP3 – – – B18 LVDS_TP4 S IO N LVDS_TP4 – – – B20 PLLXTO S O N PLLXTO – – – B21 HDMI_REXT S – N HDMI_REXT – – – B22 HDMI_TXP2 S O N HDMI_TXP2 – – – B23 HDMI_TXP1 S O N HDMI_TXP1 – – – B24 HDMI_TXP0 S O N HDMI_TXP0 – – – B25 HDMI_TXPCLK S O N HDMI_TXPCLK – – – C1 AD21 S IO N AD21 – – – C2 AD23 S IO N AD23 – – – C7 MIPIDSI_VREG _0P4V S – N MIPIDSI_VREG _0P4V – – – C11 GMAC_TXD1 S IO N GPIOE8 GMAC_TXD1 – – C12 GMAC_TXD3 S IO N GPIOE10 GMAC_TXD3 – – C14 LVDS_TN0 S IO N LVDS_TN0 – – – C15 LVDS_TP0 S IO N LVDS_TP0 – – – C17 GMAC_RXD1 S IO N GPIOE15 GMAC_RXD1 SPIFRM1 – C18 GMAC_RXD3 S IO N GPIOE17 GMAC_RXD3 – – C19 LVDS_ROUT S N LVDS_ROUT – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 D1 AD19 S IO N AD19 – – – D2 AD17 S IO N AD17 – – – D3 PADQS0 S IO N PADQS0 – – – D11 GMAC_TXD0 S IO N GPIOE7 GMAC_TXD0 VIVSYNC1 – D12 GMAC_TXD2 S IO N GPIOE9 GMAC_TXD2 – – D14 GMAC_MDIO S IO N GPIOE21 GMAC_MDIO – – D15 GMAC_MDC S IO N GPIOE20 GMAC_MDC – – D17 GMAC_RXD0 S IO N GPIOE14 GMAC_RXD0 SPICLK1 – D18 GMAC_RXD2 S IO N GPIOE16 GMAC_RXD2 – – E1 ADQM2 S O N ADQM2 – – – E2 PADQS2 S IO N PADQS2 – – – E3 AD2 S IO N AD2 – – – E4 NADQS0 S IO N NADQS0 – – – E11 GMAC_TXER S – N GPIOE12 GMAC_TXER – – E12 GMAC_TXEN S IO N GPIOE11 GMAC_TXEN – – E14 GMAC_COL S IO N GPIOE13 GMAC_COL VIHSYNC1 – E15 GMAC_RXER S IO N GPIOE22 GMAC_RXER – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 E17 GMAC_RXDV S IO N GPIOE19 GMAC_RXDV SPITXD1 – E18 GMAC_RXCLK S IO N GPIOE18 GMAC_RXCLK SPIRXD1 – E22 VDD18_USBHO F1 NADQS2 S IO N NADQS2 – – – F2 AD20 S IO N AD20 – – – F3 ADQM0 S O N ADQM0 – – – F4 AD6 S IO N AD6 – – – F5 AD0 S IO N AD0 – – – F19 VDD10_HM_PL F21 DISD5 S IO N GPIOA6 DISD5 – – G1 AD16 S IO N AD16 – – – G2 AD22 S IO N AD22 – – – G3 AD3 S IO N AD3 – – – G4 AD4 S IO N AD4 – – – G5 AD1 S IO N AD1 – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 G21 DISD1 S IO N GPIOA2 DISD1 – – G22 DISD13 S IO N GPIOA14 DISD13 – – H1 AD18 S IO N AD18 – – – H2 ACKE0 S O N ACKE0 – – – H3 AD5 S IO N AD5 – – – H4 AD7 S IO N AD7 – – – H5 AA4 S O N AA4 – – – H20 DISD3 S IO N GPIOA4 DISD3 – – H21 DISD2 S IO N GPIOA3 DISD2 – – H22 DISDE S IO N GPIOA27 DISDE – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 OST0 H24 USB2.0OTG_VB US S IO N USB2.0OTG_VB US – – – H25 USB2.0OTG_ID S IO N USB2.0OTG_ID – – – J1 AA8 S O N AA8 – – – J2 AA6 S O N AA6 – – – J3 ABA1 S O N ABA1 – – – J4 AA1 S O N AA1 – – – J5 ANWE S O N ANWE – – – J6 AA0 S O N AA0 – – – J19 DISD7 S IO N GPIOA8 DISD7 – – J20 DISHSYNC S IO N GPIOA26 DISHSYNC – – J21 DISVSYNC S IO N GPIOA25 DISVSYNC – – J22 DISD8 S IO N GPIOA9 DISD8 – – J23 DISD0 S IO N GPIOA1 DISD0 – – J24 USB2.0OTG_D M S IO N USB2.0OTG_D M – – – J25 USB2.0OTG_DP S IO N USB2.0OTG_D P – – – K1 AA14 S O N AA14 – – – K2 AA11 S O N AA11 – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 K19 DISD12 S IO N GPIOA13 DISD12 – – K25 USB2.0OTG_RK ELVIN S IO N USB2.0OTG_R KELVIN – – – L1 ACKB S O N ACKB – – – L2 ACK S O N ACK – – – L3 AA12 S O N AA12 – – – L4 AA10 S O N AA10 – – – L5 ABA2 S O N ABA2 – – – L19 DISD4 S IO N GPIOA5 DISD4 – – L20 DISD6 S IO N GPIOA7 DISD6 – – L21 DISD11 S IO N GPIOA12 DISD11 – – L22 DISD10 S IO N GPIOA11 DISD10 – – L23 DISD15 S IO N GPIOA16 DISD15 – – L24 USB2.0HOST_D M S IO N USB2.0HOST_D M – – – L25 USB2.0HOST_D P S IO N USB2.0HOST_D P – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 M1 AA7 S O N AA7 – – – M2 AA5 S O N AA5 – – – M3 AA3 S O N AA3 – – – M4 AA9 S O N AA9 – – – M5 AA13 S O N AA13 – – – M19 DISD9 S IO N GPIOA10 DISD9 – – M20 DISD22 S IO N GPIOA23 DISD22 – – M21 DISD16 S IO N GPIOA17 DISD16 – – M22 DISD14 S IO N GPIOA15 DISD14 – – M24 VDD33_USBHO M25 USB2.0HOST_R KELVIN S IO N USB2.0HOST_R KELVIN – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 N19 VID1_0 S IO N GPIOA30 VID1_0 SDEX0 I2SBCLK1 P1 ANCS0 S O N ANCS0 – – – P2 ANCAS S O N ANCAS – – – P3 ABA0 S O N ABA0 – – – P4 AA15 S O N AA15 – – – P5 AODT1 S O N AODT1 – – – P19 VID1_2 S IO N GPIOB2 VID1_2 SDEX2 I2SBCLK2 P20 VID1_1 S IO N GPIOB0 VID1_1 SDEX1 I2SLRCLK1 P21 DISD19 S IO N GPIOA20 DISD19 – – P22 DISD17 S IO N GPIOA18 DISD17 – – P24 USBHSIC_STR OBE S IO N USBHSIC_STR OBE – – – P25 USBHSIC_DAT A S IO N USBHSIC_DAT A – – – R1 AODT0 S O N AODT0 – – – R2 ANRAS S O N ANRAS – – – R3 AA2 S O N AA2 – – – R4 ARST S O N ARST – – – R5 ACKE1 S O N ACKE1 – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 R19 VID1_4 S IO N GPIOB6 VID1_4 SDEX4 I2SDOUT1 R20 VID1_3 S IO N GPIOB4 VID1_3 SDEX3 I2SLRCLK2 R21 DISD21 S IO N GPIOA22 DISD21 – – R22 DISD23 S IO N GPIOA24 DISD23 – – R23 DISD18 S IO N GPIOA19 DISD18 – – R24 DISD20 S IO N GPIOA21 DISD20 – – R25 DISCLK S IO N GPIOA0 DISCLK – – T1 AREF1 P IO N AREF1 – – – T2 AREF2 P IO N AREF2 – – – T19 USB2.0OTG_US BVBUS S I N USB2.0OTG_U SBVBUS – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 T24 SDCLK0 S IO N GPIOA29 SDCLK0 – – T25 SDDAT0_0 S IO N GPIOB1 SDDAT0_0 – – U1 AD8 S IO N AD8 – – – U2 AD10 S IO N AD10 – – – U3 AD27 S IO N AD27 – – – U4 AD25 S IO N AD25 – – – U5 ANCS1 S O N ANCS1 – – – U6 ADC6 S IO N ADC6 – – – U7 ADC7 S IO N ADC7 – – – U19 HDMI_HOT5V S I N HDMI_HOT5V – – – U20 VID1_6 S IO N GPIOB9 VID1_6 SDEX6 I2SDIN1 U21 VICLK1 S IO N GPIOA28 VICLK1 I2SMCLK2 I2SMCLK1 U22 SD7 S IO N SD7 GPIOB23 – – U23 SDCMD0 S IO N GPIOA31 SDCMD0 – – U24 SDDAT0_1 S IO N GPIOB3 SDDAT0_1 – – U25 SDDAT0_2 S IO N GPIOB5 SDDAT0_2 – – V1 AD14 S IO N AD14 – – – V2 AD12 S IO N AD12 – – – V3 AD24 S IO N AD24 – – – V4 AD26 S IO N AD26 – – – V5 ZQ S – N ZQ – – – V6 NTRST S IO PU NTRST GPIOE25 – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 V16 DVDD_VID2_SD V17 DVDD_VID2_SD V19 VID1_7 S IO N GPIOB10 VID1_7 SDEX7 I2SDIN2 V20 VID1_5 S IO N GPIOB8 VID1_5 SDEX5 I2SDOUT2 V21 SD6 S IO N SD6 GPIOB22 – – V22 SD4 S IO N SD4 GPIOB20 – – V23 SD3 S IO N SD3 GPIOB19 – – V24 SDDAT0_3 S IO N GPIOB7 SDDAT0_3 – – V25 NNFWE0 S IO N NNFWE0 nNFWE1 GPIOB18 – W1 ADQM1 S O N ADQM1 – – – W2 PADQS1 S IO N PADQS1 – – – W3 PADQS3 S IO N PADQS3 – – – W4 NADQS3 S IO N NADQS3 – – – W5 TDI S IO PU TDI GPIOE27 – – W9 ADC5 S IO N ADC5 – – – W10 ALIVEGPIO3 S IO N ALIVEGPIO3 – – – W11 ALIVEGPIO5 S IO N ALIVEGPIO5 – – – W13 SA13 S IO N SA13 GPIOC13 PWM1 SDnINT2 W14 SA11 S IO N SA11 GPIOC11 SPIRXD2 USB2.0OT G_DrvVBU S W15 SA12 S IO N SA12 GPIOC12 SPITXD2 SDnRST2 W16 SA10 S IO PU SA10 GPIOC10 SPIFRM2 – W17 UARTTXD3 S IO N GPIOD21 UARTTXD3 – SDnCD1 W18 SA3 S IO N SA3 GPIOC3 HDMI_CEC SDnRST0 W21 SD5 S IO N SD5 GPIOB21 – – W22 SD2 S IO N SD2 GPIOB17 – – W23 SD1 S IO N SD1 GPIOB15 – – W24 ALE0 S IO N ALE0 ALE1 GPIOB12 – W25 CLE0 S IO N CLE0 CLE1 GPIOB11 – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 Y1 NADQS1 S IO N NADQS1 – – – Y2 AD9 S IO N AD9 – – – Y3 ADQM3 S O N ADQM3 – – – Y4 AD29 S IO N AD29 – – – Y5 TMS S IO PU TMS GPIOE26 – – Y7 TDO S IO N TDO GPIOE29 – – Y8 ALIVEGPIO4 S IO N ALIVEGPIO4 – – – Y9 ADC4 S IO N ADC4 – – – Y12 PPM S IO N GPIOD8 PPM – – Y14 SDDAT1_3 S IO N GPIOD27 SDDAT1_3 – – Y15 SDDAT1_2 S IO N GPIOD26 SDDAT1_2 – – Y17 UARTRXD3 S IO N GPIOD17 UARTRXD3 – – Y18 UARTTXD2 S IO N GPIOD20 UARTTXD2 – SDWP1 Y19 UARTRXD2 S IO N GPIOD16 UARTRXD2 – – Y22 NNFOE0 S IO N NNFOE0 NNFOE1 GPIOB16 – Y23 SD0 S IO N SD0 GPIOB13 – – Y24 NNCS1 S O PU NNCS1 – – – Y25 NNCS0 S O N NNCS0 – – – AA1 AD11 S IO N AD11 – – – AA2 AD13 S IO N AD13 – – – AA3 AD31 S IO N AD31 – – – AA4 AD28 S IO N AD28 – – – AA6 TCLK S IO PD TCLK GPIOE28 – – AA7 ALIVEGPIO2 S IO N ALIVEGPIO2 – – – AA8 ALIVEGPIO1 S IO N ALIVEGPIO1 – – – AA9 VID0_0 S IO N GPIOD28 VID0_0 TSIDATA1_0 SA24 AA11 VIHSYNC0 S IO N GPIOE5 VIHSYNC0 TSISYNC1 – AA12 SA21 S IO N SA21 GPIOC21 SDDAT2_1 VID2_4 AA14 SA17 S IO N SA17 GPIOC17 TSIDP0 VID2_0 AA15 I2SMCLK0 S IO N GPIOD13 I2SMCLK0 AC97_nRST – AA17 SDDAT1_1 S IO N GPIOD25 SDDAT1_1 – – AA18 SDDAT1_0 S IO N GPIOD24 SDDAT1_0 – – AA19 SDCMD1 S IO N GPIOD23 SDCMD1 – – AA20 SDCLK1 S IO N GPIOD22 SDCLK1 – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 AA22 SA2 S IO N SA2 GPIOC2 – – AA23 RNB0 S IO N RnB0 RnB1 GPIOB14 – AA24 NSDQM S IO PU NSDQM GPIOC27 PDMDATA1 – AA25 SD8 S IO N SD8 GPIOB24 TSIDATA0_0 – AB1 AD15 S IO N AD15 – – – AB2 NBATF S I N NBATF – – – AB3 AD30 S IO N AD30 – – – AB5 ADC1 S IO N ADC1 – – – AB6 VDDPWRON S O N VDDPWRON – – – AB7 NGRESETOUT S O N NGRESETOUT – – – AB8 ALIVEGPIO0 S IO N ALIVEGPIO0 – – – AB9 VID0_4 S IO N GPIOE0 VID0_4 TSIDATA1_4 – AB11 SA20 S IO N SA20 GPIOC20 SDDAT2_0 VID2_3 AB12 SA18 S IO N SA18 GPIOC18 SDCLK2 VID2_1 AB14 SA19 S IO N SA19 GPIOC19 SDCMD2 VID2_2 AB15 I2SBCLK0 S IO N GPIOD10 I2SBCLK0 AC97_BCLK – AB17 SCL1 S IO N GPIOD4 SCL1 – – AB18 SDA1 S IO N GPIOD5 SDA1 – – AB19 SDA2 S IO N GPIOD7 SDA2 – – AB20 NSWE S IO PU NSWE GPIOE31 – – AB21 NSCS1 S IO PU GPIOC28 NSCS1 UARTnRI1 – AB23 RDNWR S IO PU RDNWR GPIOC26 PDMDATA0 – AB24 SA9 S IO N SA9 GPIOC9 SPICLK2 PDMStrobe AB25 SD9 S IO N SD9 GPIOB25 TSIDATA0_1 – AC2 ADCREF P IO N – – – – AC5 AVDD18_ADC P IO N – – – – AC6 VDDPWRON_D DR S O N VDDPWRON_D DR – – – AC8 VDDI10_ALIVE P – N – – – – AC9 VID0_1 S IO N GPIOD29 VID0_1 TSIDATA1_1 – AC11 VID0_3 S IO N GPIOD31 VID0_3 TSIDATA1_3 – AC12 SA23 S IO N SA23 GPIOC23 SDDAT2_3 VID2_6 AC14 SA22 S IO N SA22 GPIOC22 SDDAT2_2 VID2_5 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 AC15 I2SDIN0 S IO N GPIOD11 I2SDIN0 AC97_DIN – AC17 I2SLRCLK0 S IO N GPIOD12 I2SLRCLK0 AC97_SYNC – AC18 SCL2 S IO N GPIOD6 SCL2 – – AC19 SDA0 S IO N GPIOD3 SDA0 ISO7816 – AC20 SCL0 S IO N GPIOD2 SCL0 ISO7816 – AC21 NSWAIT S IO PU NSWAIT GPIOC25 SPDIFTX – AC22 SA4 S IO N SA4 GPIOC4 UARTnDCD1 SDnINT0 AC24 SD15 S IO N SD15 GPIOB31 TSIDATA0_7 – AC25 SD10 S IO N SD10 GPIOB26 TSIDATA0_2 – AD2 ADC0 S IO N ADC0 – – – AD3 ADC2 S IO N ADC2 – – – AD4 RTCXTO S O N RTCXTO – – – AD6 ADC3 S IO N ADC3 – – – AD7 EFUSE_FSOUR CE S – N EFUSE_FSOUR CE – – – AD8 WIRE0 S I N WIRE0 – – – AD9 VID0_2 S IO N GPIOD30 VID0_2 TSIDATA1_2 – AD10 VID0_6 S IO N GPIOE2 VID0_6 TSIDATA1_6 – AD11 VIVSYNC0 S IO N GPIOE6 VIVSYNC0 TSIDP1 – AD12 SA14 S IO N SA14 GPIOC14 PWM2 VICLK2 AD14 SA15 S IO N SA15 GPIOC15 TSICLK0 VIHSYNC2 AD15 I2SDOUT0 S IO N GPIOD9 I2SDOUT0 AC97_DOUT – AD16 SPIRXD0 S IO N GPIOD0 SPIRXD0 PWM3 – AD17 SPIFRM0 S IO N GPIOC30 SPIFRM0 – – AD18 UARTTXD1 S IO N GPIOD19 UARTTXD1 ISO7816 SDnCD2 AD19 UARTTXD0 S IO N GPIOD18 UARTTXD0 ISO7816 SDWP2 AD20 NSCS0 S O N NSCS0 – – – AD21 SA8 S IO N SA8 GPIOC8 UARTnDTR1 SDnINT1 AD22 SA5 S IO N SA5 GPIOC5 UARTnCTS1 SDWP0 AD23 SA0 S IO N SA0 GPIOC0 TSERR0 – AD24 SD14 S IO N SD14 GPIOB30 TSIDATA0_6 – AD25 SD11 S IO N SD11 GPIOB27 TSIDATA0_3 – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type I/O PU/PD Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 AE3 NRESET S I N NRESET – – – AE4 RTCXTI S I N RTCXTI – – – AE5 ADCREFGND G – N – – – – AE6 NVDDPWRTOG GLE S I PU NVDDPWRTOG GLE – – – AE7 TEST_EN S I N TEST_EN – – – AE8 WIRE1 S – N WIRE1 – – – AE9 VID0_5 S IO N GPIOE1 VID0_5 TSIDATA1_5 – AE10 VICLK0 S IO N GPIOE4 VICLK0 TSICLK1 – AE11 VID0_7 S IO N GPIOE3 VID0_7 TSIDATA1_7 – AE12 LATADDR S IO N LATADDR GPIOC24 SPDIFRX VID2_7 AE14 SA16 S IO N SA16 GPIOC16 TSISYNC0 VIVSYNC2 AE15 PWM0 S IO N GPIOD1 PWM0 SA25 – AE16 SPITXD0 S IO N GPIOC31 SPITXD0 – – AE17 SPICLK0 S IO N GPIOC29 SPICLK0 – – AE18 UARTRXD1 S IO N GPIOD15 UARTRXD1 ISO7816 – AE19 UARTRXD0 S IO N GPIOD14 UARTRXD0 ISO7816 – AE20 NSOE S IO PU NSOE GPIOE30 – – AE21 SA7 S IO N SA7 GPIOC7 UARTnDSR1 SDnRST1 AE22 SA6 S IO N SA6 GPIOC6 UARTnRTS1 SDnCD0 AE23 SA1 S IO N SA1 GPIOC1 TSERR1 – AE24 SD13 S IO N SD13 GPIOB29 TSIDATA0_5 UARTTXD4 AE25 SD12 S IO N SD12 GPIOB28 TSIDATA0_4 UARTRXD4 NOTE: 1. Type definition - S: Signal ball, P: Power ball, G: GND ball 2. IO pad type definition - I: Input, O: Output, IO: Input/Output 3. Internal Pull Up/Down definition - PU: Pull Up, PD: Pull Down, N: no Pull Up/Down cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2 Ball List Table: Sorted by Function

2.3.2.1 MCU-A

F 5 AD0 S AD0 – – – G 5 AD1 S AD1 – – – E 3 AD2 S AD2 – – – G 3 AD3 S AD3 – – – G 4 AD4 S AD4 – – – H 3 AD5 S AD5 – – – F 4 AD6 S AD6 – – – H 4 AD7 S AD7 – – – U 1 AD8 S AD8 – – – Y 2 AD9 S AD9 – – – U 2 AD10 S AD10 – – – AA 1 AD11 S AD11 – – – V 2 AD12 S AD12 – – – AA 2 AD13 S AD13 – – – V 1 AD14 S AD14 – – – AB 1 AD15 S AD15 – – – G 1 AD16 S AD16 – – – D 2 AD17 S AD17 – – – H 1 AD18 S AD18 – – – D 1 AD19 S AD19 – – – F 2 AD20 S AD20 – – – C 1 AD21 S AD21 – – – G 2 AD22 S AD22 – – – C 2 AD23 S AD23 – – – V 3 AD24 S AD24 – – – U 4 AD25 S AD25 – – – V 4 AD26 S AD26 – – – U 3 AD27 S AD27 – – – AA 4 AD28 S AD28 – – – Y 4 AD29 S AD29 – – – AB 3 AD30 S AD30 – – – AA 3 AD31 S AD31 – – – J 6 AA0 S AA0 – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 J 4 AA1 S AA1 – – – R 3 AA2 S AA2 – – – M 3 AA3 S AA3 – – – H 5 AA4 S AA4 – – – M 2 AA5 S AA5 – – – J 2 AA6 S AA6 – – – M 1 AA7 S AA7 – – – J 1 AA8 S AA8 – – – M 4 AA9 S AA9 – – – L 4 AA10 S AA10 – – – K 2 AA11 S AA11 – – – L 3 AA12 S AA12 – – – M 5 AA13 S AA13 – – – K 1 AA14 S AA14 – – – P 4 AA15 S AA15 – – – P 3 ABA0 S ABA0 – – – J 3 ABA1 S ABA1 – – – L 5 ABA2 S ABA2 – – – D 3 PADQS0 S PADQS0 – – – W 2 PADQS1 S PADQS1 – – – E 2 PADQS2 S PADQS2 – – – W 3 PADQS3 S PADQS3 – – – E 4 NADQS0 S NADQS0 – – – Y 1 NADQS1 S NADQS1 – – – F 1 NADQS2 S NADQS2 – – – W 4 NADQS3 S NADQS3 – – – F 3 ADQM0 S ADQM0 – – – W 1 ADQM1 S ADQM1 – – – E 1 ADQM2 S ADQM2 – – – Y 3 ADQM3 S ADQM3 – – – R 2 ANRAS S ANRAS – – – P 2 ANCAS S ANCAS – – – P 1 ANCS0 S ANCS0 – – – U 5 ANCS1 S ANCS1 – – – L 2 ACK S ACK – – – L 1 ACKB S ACKB – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-26 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 H 2 ACKE0 S ACKE0 – – – R 5 ACKE1 S ACKE1 – – – J 5 ANWE S ANWE – – – R 4 ARST S ARST – – – R 1 AODT0 S AODT0 – – – P 5 AODT1 S AODT1 – – – T 1 AREF1 P AREF1 – – – T 2 AREF2 P AREF2 – – – V 5 ZQ S ZQ – – –

2.3.2.2 MCU-S

Y 23 SD0 S SD0 GPIOB13 – – W 23 SD1 S SD1 GPIOB15 – – W 22 SD2 S SD2 GPIOB17 – – V 23 SD3 S SD3 GPIOB19 – – V 22 SD4 S SD4 GPIOB20 – – W21 SD5 S SD5 GPIOB21 – – V21 SD6 S SD6 GPIOB22 – – U 22 SD7 S SD7 GPIOB23 – – AA 25 SD8 S SD8 GPIOB24 TSIDATA0_0 – AB 25 SD9 S SD9 GPIOB25 TSIDATA0_1 – AC 25 SD10 S SD10 GPIOB26 TSIDATA0_2 – AD 25 SD11 S SD11 GPIOB27 TSIDATA0_3 – AE 25 SD12 S SD12 GPIOB28 TSIDATA0_4 UARTRXD4 AE 24 SD13 S SD13 GPIOB29 TSIDATA0_5 UARTTXD4 AD 24 SD14 S SD14 GPIOB30 TSIDATA0_6 – AC 24 SD15 S SD15 GPIOB31 TSIDATA0_7 – N19 SDEX0 S GPIOA30 VID1_0 SDEX0 I2SBCLK1 P20 SDEX1 S GPIOB0 VID1_1 SDEX1 I2SLRCLK1 P19 SDEX2 S GPIOB2 VID1_2 SDEX2 I2SBCLK2 R20 SDEX3 S GPIOB4 VID1_3 SDEX3 I2SLRCLK2 R19 SDEX4 S GPIOB6 VID1_4 SDEX4 I2SDOUT1 V20 SDEX5 S GPIOB8 VID1_5 SDEX5 I2SDOUT2 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 U20 SDEX6 S GPIOB9 VID1_6 SDEX6 I2SDIN1 V19 SDEX7 S GPIOB10 VID1_7 SDEX7 I2SDIN2 AD 23 SA0 S SA0 GPIOC0 TSERR0 – AE 23 SA1 S SA1 GPIOC1 TSERR1 – AA 22 SA2 S SA2 GPIOC2 – – W18 SA3 S SA3 GPIOC3 HDMI_CEC SDnRST0 AC 22 SA4 S SA4 GPIOC4 UARTnDCD1 SDnINT0 AD 22 SA5 S SA5 GPIOC5 UARTnCTS1 SDWP0 AE 22 SA6 S SA6 GPIOC6 UARTnRTS1 SDnCD0 AE 21 SA7 S SA7 GPIOC7 UARTnDSR1 SDnRST1 AD 21 SA8 S SA8 GPIOC8 UARTnDTR1 SDnINT1 AB 24 SA9 S SA9 GPIOC9 SPICLK2 PDMStrobe W16 SA10 S SA10 GPIOC10 SPIFRM2 – W 14 SA11 S SA11 GPIOC11 SPIRXD2 USB2.0OTG_Dr vVBUS W15 SA12 S SA12 GPIOC12 SPITXD2 SDnRST2 W13 SA13 S SA13 GPIOC13 PWM1 SDnINT2 AD 12 SA14 S SA14 GPIOC14 PWM2 VICLK2 AD 14 SA15 S SA15 GPIOC15 TSICLK0 VIHSYNC2 AE 14 SA16 S SA16 GPIOC16 TSISYNC0 VIVSYNC2 AA 14 SA17 S SA17 GPIOC17 TSIDP0 VID2_0 AB 12 SA18 S SA18 GPIOC18 SDCLK2 VID2_1 AB 14 SA19 S SA19 GPIOC19 SDCMD2 VID2_2 AB 11 SA20 S SA20 GPIOC20 SDDAT2_0 VID2_3 AA12 SA21 S SA21 GPIOC21 SDDAT2_1 VID2_4 AC 14 SA22 S SA22 GPIOC22 SDDAT2_2 VID2_5 AC 12 SA23 S SA23 GPIOC23 SDDAT2_3 VID2_6 AA 9 SA24 S GPIOD28 VID0_0 TSIDATA1_0 SA24 AE 15 SA25 S GPIOD1 PWM0 SA25 – AD 20 NSCS0 S NSCS0 – – – AB 21 NSCS1 S GPIOC28 NSCS1 UARTnRI1 – AB 20 NSWE S NSWE GPIOE31 – – AE 20 NSOE S NSOE GPIOE30 – – AB 23 RDNWR S RDNWR GPIOC26 PDMDATA0 – AA 24 NSDQM S NSDQM GPIOC27 PDMDATA1 – AC 21 NSWAIT S NSWAIT GPIOC25 SPDIFTX – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-28 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 AE 12 LATADDR S LATADDR GPIOC24 SPDIFRX VID2_7 W 25 CLE0 S CLE0 CLE1 GPIOB11 – W 24 ALE0 S ALE0 ALE1 GPIOB12 – AA 23 RNB0 S RnB0 RnB1 GPIOB14 – Y 22 NNFOE0 S NNFOE0 NNFOE1 GPIOB16 – V 25 NNFWE0 S NNFWE0 nNFWE1 GPIOB18 – Y 25 NNCS0 S NNCS0 – – – Y 24 NNCS1 S NNCS1 – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-29 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2.3 Digital RGB

J23 DISD0 S GPIOA1 DISD0 – – G21 DISD1 S GPIOA2 DISD1 – – H21 DISD2 S GPIOA3 DISD2 – – H20 DISD3 S GPIOA4 DISD3 – – L19 DISD4 S GPIOA5 DISD4 – – F21 DISD5 S GPIOA6 DISD5 – – L20 DISD6 S GPIOA7 DISD6 – – J19 DISD7 S GPIOA8 DISD7 – – J22 DISD8 S GPIOA9 DISD8 – – M19 DISD9 S GPIOA10 DISD9 – – L22 DISD10 S GPIOA11 DISD10 – – L21 DISD11 S GPIOA12 DISD11 – – K19 DISD12 S GPIOA13 DISD12 – – G22 DISD13 S GPIOA14 DISD13 – – M22 DISD14 S GPIOA15 DISD14 – – L23 DISD15 S GPIOA16 DISD15 – – M21 DISD16 S GPIOA17 DISD16 – – P22 DISD17 S GPIOA18 DISD17 – – R23 DISD18 S GPIOA19 DISD18 – – P21 DISD19 S GPIOA20 DISD19 – – R24 DISD20 S GPIOA21 DISD20 – – R21 DISD21 S GPIOA22 DISD21 – – M20 DISD22 S GPIOA23 DISD22 – – R22 DISD23 S GPIOA24 DISD23 – – R25 DISCLK S GPIOA0 DISCLK – – J21 DISVSYNC S GPIOA25 DISVSYNC – – J20 DISHSYNC S GPIOA26 DISHSYNC – – H22 DISDE S GPIOA27 DISDE – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-30 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2.4 HDMI

B 24 HDMI_TXP0 S HDMI_TXP0 – – – A 24 HDMI_TXN0 S HDMI_TXN0 – – – B 23 HDMI_TXP1 S HDMI_TXP1 – – – A 23 HDMI_TXN1 S HDMI_TXN1 – – – B 22 HDMI_TXP2 S HDMI_TXP2 – – – A 22 HDMI_TXN2 S HDMI_TXN2 – – – B 25 HDMI_TXPCLK S HDMI_TXPCLK – – – A 25 HDMI_TXNCLK S HDMI_TXNCLK – – – Y 21 HDMI_CEC S SA3 GPIOC3 HDMI_CEC SDnRST0 A 21 HDMI_HOT5V S HDMI_HOT5V – – – B 21 HDMI_REXT S HDMI_REXT – – –

2.3.2.5 LVDS

C 15 LVDS_TP0 S LVDS_TP0 – – – C 14 LVDS_TN0 S LVDS_TN0 – – – B 14 LVDS_TP1 S LVDS_TP1 – – – A 14 LVDS_TN1 S LVDS_TN1 – – – B 15 LVDS_TP2 S LVDS_TP2 – – – A 15 LVDS_TN2 S LVDS_TN2 – – – B 17 LVDS_TP3 S LVDS_TP3 – – – A 17 LVDS_TN3 S LVDS_TN3 – – – B 18 LVDS_TP4 S LVDS_TP4 – – – A 18 LVDS_TN4 S LVDS_TN4 – – – B 16 LVDS_TPCLK S LVDS_TPCLK – – – A 16 LVDS_TNCLK S LVDS_TNCLK – – – C 19 LVDS_ROUT S LVDS_ROUT – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-31 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2.6 MIPI DSI

Ball Name Type Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 B 8 MIPIDSI_DP0 S MIPIDSI_DP0 – – – A 8 MIPIDSI_DN0 S MIPIDSI_DN0 – – – B 9 MIPIDSI_DP1 S MIPIDSI_DP1 – – – A 9 MIPIDSI_DN1 S MIPIDSI_DN1 – – – B 10 MIPIDSI_DP2 S MIPIDSI_DP2 – – – A 10 MIPIDSI_DN2 S MIPIDSI_DN2 – – – B 11 MIPIDSI_DP3 S MIPIDSI_DP3 – – – A 11 MIPIDSI_DN3 S MIPIDSI_DN3 – – – B 7 MIPIDSI_DPCLK S MIPIDSI_DPCLK – – – A 7 MIPIDSI_DNCLK S MIPIDSI_DNCLK – – – C 7 MIPIDSI_VREG_ 0P4V S MIPIDSI_VREG_0P4V – – –

2.3.2.7 MIPI CSI

Ball Name Type Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 B 2 MIPICSI_DP0 S MIPICSI_DP0 – – – A 2 MIPICSI_DN0 S MIPICSI_DN0 – – – B 3 MIPICSI_DP1 S MIPICSI_DP1 – – – A 3 MIPICSI_DN1 S MIPICSI_DN1 – – – B 4 MIPICSI_DP2 S MIPICSI_DP2 – – – A 4 MIPICSI_DN2 S MIPICSI_DN2 – – – B 5 MIPICSI_DP3 S MIPICSI_DP3 – – – A 5 MIPICSI_DN3 S MIPICSI_DN3 – – – B1 MIPICSI_DPCLK S MIPICSI_DPCLK – – – A1 MIPICSI_DNCLK S MIPICSI_DNCLK – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-32 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2.8 VIP

AA 9 VID0_0 S GPIOD28 VID0_0 TSIDATA1_0 SA24 AC 9 VID0_1 S GPIOD29 VID0_1 TSIDATA1_1 – AD 9 VID0_2 S GPIOD30 VID0_2 TSIDATA1_2 – AC 11 VID0_3 S GPIOD31 VID0_3 TSIDATA1_3 – AB 9 VID0_4 S GPIOE0 VID0_4 TSIDATA1_4 – AE 9 VID0_5 S GPIOE1 VID0_5 TSIDATA1_5 – AE 10 VID0_6 S GPIOE2 VID0_6 TSIDATA1_6 – AE 11 VID0_7 S GPIOE3 VID0_7 TSIDATA1_7 – AD 10 VICLK0 S GPIOE4 VICLK0 TSICLK1 – AA 11 VIHSYNC0 S GPIOE5 VIHSYNC0 TSISYNC1 – AD 11 VIVSYNC0 S GPIOE6 VIVSYNC0 TSIDP1 – J 21 VID1_0 S GPIOA30 VID1_0 SDEX0 I2SBCLK1 L 20 VID1_1 S GPIOB0 VID1_1 SDEX1 I2SLRCLK1 M 20 VID1_2 S GPIOB2 VID1_2 SDEX2 I2SBCLK2 P 20 VID1_3 S GPIOB4 VID1_3 SDEX3 I2SLRCLK2 R 20 VID1_4 S GPIOB6 VID1_4 SDEX4 I2SDOUT1 U 20 VID1_5 S GPIOB8 VID1_5 SDEX5 I2SDOUT2 V 20 VID1_6 S GPIOB9 VID1_6 SDEX6 I2SDIN1 W 21 VID1_7 S GPIOB10 VID1_7 SDEX7 I2SDIN2 J 20 VICLK1 S GPIOA28 VICLK1 I2SMCLK2 I2SMCLK1 E 14 VIHSYNC1 S GPIOE13 GMAC_COL VIHSYNC1 – D 11 VIVSYNC1 S GPIOE7 GMAC_TXD0 VIVSYNC1 – AA 14 VID2_0 S SA17 GPIOC17 TSIDP0 VID2_0 AB 12 VID2_1 S SA18 GPIOC18 SDCLK2 VID2_1 AB 14 VID2_2 S SA19 GPIOC19 SDCMD2 VID2_2 AB 11 VID2_3 S SA20 GPIOC20 SDDAT2_0 VID2_3 Y 11 VID2_4 S SA21 GPIOC21 SDDAT2_1 VID2_4 AC 14 VID2_5 S SA22 GPIOC22 SDDAT2_2 VID2_5 AC 12 VID2_6 S SA23 GPIOC23 SDDAT2_3 VID2_6 AE 12 VID2_7 S LATADDR GPIOC24 SPDIFRX VID2_7 AD 12 VICLK2 S SA14 GPIOC14 PWM2 VICLK2 AD 14 VIHSYNC2 S SA15 GPIOC15 TSICLK0 VIHSYNC2 AE 14 VIVSYNC2 S SA16 GPIOC16 TSISYNC0 VIVSYNC2 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-33 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2.9 Ethernet MAC

D 11 GMAC_TXD0 S GPIOE7 GMAC_TXD0 VIVSYNC1 – C 11 GMAC_TXD1 S GPIOE8 GMAC_TXD1 – – C 12 GMAC_TXD2 S GPIOE9 GMAC_TXD2 – – D 12 GMAC_TXD3 S GPIOE10 GMAC_TXD3 – – E 12 GMAC_TXEN S GPIOE11 GMAC_TXEN – – E 11 GMAC_TXER S GPIOE12 GMAC_TXER – – E 14 GMAC_COL S GPIOE13 GMAC_COL VIHSYNC1 – D 17 GMAC_RXD0 S GPIOE14 GMAC_RXD0 SPICLK1 – C 17 GMAC_RXD1 S GPIOE15 GMAC_RXD1 SPIFRM1 – D 18 GMAC_RXD2 S GPIOE16 GMAC_RXD2 – – C 18 GMAC_RXD3 S GPIOE17 GMAC_RXD3 – – E 18 GMAC_RXCLK S GPIOE18 GMAC_RXCLK SPIRXD1 – E 17 GMAC_RXDV S GPIOE19 GMAC_RXDV SPITXD1 – D 15 GMAC_MDC S GPIOE20 GMAC_MDC – – D 14 GMAC_MDIO S GPIOE21 GMAC_MDIO – – E 15 GMAC_RXER S GPIOE22 GMAC_RXER – – B 12 GMAC_CRS S GPIOE23 GMAC_CRS – – A 12 GMAC_GTXCLK S GPIOE24 GMAC_GTXCLK – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-34 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2.10 MPEG-TS Interface

AA 25 TSIDATA0_0 S SD8 GPIOB24 TSIDATA0_0 – AB 25 TSIDATA0_1 S SD9 GPIOB25 TSIDATA0_1 – AC 25 TSIDATA0_2 S SD10 GPIOB26 TSIDATA0_2 – AD 25 TSIDATA0_3 S SD11 GPIOB27 TSIDATA0_3 – AE 25 TSIDATA0_4 S SD12 GPIOB28 TSIDATA0_4 UARTRXD4 AE 24 TSIDATA0_5 S SD13 GPIOB29 TSIDATA0_5 UARTTXD4 AD 24 TSIDATA0_6 S SD14 GPIOB30 TSIDATA0_6 – AC 24 TSIDATA0_7 S SD15 GPIOB31 TSIDATA0_7 – AD 14 TSICLK0 S SA15 GPIOC15 TSICLK0 VIHSYNC2 AE 14 TSISYNC0 S SA16 GPIOC16 TSISYNC0 VIVSYNC2 AA 14 TSIDP0 S SA17 GPIOC17 TSIDP0 VID2_0 AA 9 TSIDATA1_0 S GPIOD28 VID0_0 TSIDATA1_0 SA24 AC 9 TSIDATA1_1 S GPIOD29 VID0_1 TSIDATA1_1 – AD 9 TSIDATA1_2 S GPIOD30 VID0_2 TSIDATA1_2 – AC 11 TSIDATA1_3 S GPIOD31 VID0_3 TSIDATA1_3 – AB 9 TSIDATA1_4 S GPIOE0 VID0_4 TSIDATA1_4 – AE 9 TSIDATA1_5 S GPIOE1 VID0_5 TSIDATA1_5 – AE 10 TSIDATA1_6 S GPIOE2 VID0_6 TSIDATA1_6 – AE 11 TSIDATA1_7 S GPIOE3 VID0_7 TSIDATA1_7 – AD 10 TSICLK1 S GPIOE4 VICLK0 TSICLK1 – AA 11 TSISYNC1 S GPIOE5 VIHSYNC0 TSISYNC1 – AD 11 TSIDP1 S GPIOE6 VIVSYNC0 TSIDP1 – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-35 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2.11 UART_ISO7816

AD 19 UARTTXD0 S GPIOD18 UARTTXD0 ISO7816 SDWP2 AE 19 UARTRXD0 S GPIOD14 UARTRXD0 ISO7816 – AD 18 UARTTXD1 S GPIOD19 UARTTXD1 ISO7816 SDnCD2 AE 18 UARTRXD1 S GPIOD15 UARTRXD1 ISO7816 – AC 22 UARTnDCD1 S SA4 GPIOC4 UARTnDCD1 SDnINT0 AD 22 UARTnCTS1 S SA5 GPIOC5 UARTnCTS1 SDWP0 AE 22 UARTnRTS1 S SA6 GPIOC6 UARTnRTS1 SDnCD0 AE 21 UARTnDSR1 S SA7 GPIOC7 UARTnDSR1 SDnRST1 AD 21 UARTnDTR1 S SA8 GPIOC8 UARTnDTR1 SDnINT1 AB 21 UARTnRI1 S GPIOC28 NSCS1 UARTnRI1 – Y 18 UARTTXD2 S GPIOD20 UARTTXD2 – SDWP1 Y 19 UARTRXD2 S GPIOD16 UARTRXD2 – – W 17 UARTTXD3 S GPIOD21 UARTTXD3 – SDnCD1 Y 17 UARTRXD3 S GPIOD17 UARTRXD3 – – AE 24 UARTTXD4 S SD13 GPIOB29 TSIDATA0_5 UARTTXD4 AE 25 UARTRXD4 S SD12 GPIOB28 TSIDATA0_4 UARTRXD4

2.3.2.12 I2C

AC 19 SDA0 S GPIOD3 SDA0 ISO7816 – AC 20 SCL0 S GPIOD2 SCL0 ISO7816 – AB 18 SDA1 S GPIOD5 SDA1 – – AB 17 SCL1 S GPIOD4 SCL1 – – AB 19 SDA2 S GPIOD7 SDA2 – – AC 18 SCL2 S GPIOD6 SCL2 – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-36 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2.13 SPI/SSP

AE 16 SPITXD0 S GPIOC31 SPITXD0 – – AD 16 SPIRXD0 S GPIOD0 SPIRXD0 PWM3 – AE 17 SPICLK0 S GPIOC29 SPICLK0 – – AD 17 SPIFRM0 S GPIOC30 SPIFRM0 – – E 17 SPITXD1 S GPIOE19 GMAC_RXDV SPITXD1 – E 18 SPIRXD1 S GPIOE18 GMAC_RXCLK SPIRXD1 – D 17 SPICLK1 S GPIOE14 GMAC_RXD0 SPICLK1 – C 17 SPIFRM1 S GPIOE15 GMAC_RXD1 SPIFRM1 – V 15 SPITXD2 S SA12 GPIOC12 SPITXD2 SDnRST2 W 14 SPIRXD2 S SA11 GPIOC11 SPIRXD2 USB2.0OTG_Dr vVBUS AB 24 SPICLK2 S SA9 GPIOC9 SPICLK2 PDMStrobe V 19 SPIFRM2 S SA10 GPIOC10 SPIFRM2 –

2.3.2.14 PWM

AE 15 PWM0 S GPIOD1 PWM0 SA25 – V 14 PWM1 S SA13 GPIOC13 PWM1 SDnINT2 AD 12 PWM2 S SA14 GPIOC14 PWM2 VICLK2 AD 16 PWM3 S GPIOD0 SPIRXD0 PWM3 –

2.3.2.15 PPM

Y 12 PPM S GPIOD8 PPM – –

2.3.2.16 PDM

AB 23 PDMDATA0 S RDNWR GPIOC26 PDMDATA0 – AA 24 PDMDATA1 S NSDQM GPIOC27 PDMDATA1 – AB 24 PDMStrobe S SA9 GPIOC9 SPICLK2 PDMStrobe cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-37 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2.17 SPDIF

AC 21 SPDIFTX S NSWAIT GPIOC25 SPDIFTX – AE 12 SPDIFRX S LATADDR GPIOC24 SPDIFRX VID2_7

2.3.2.18 SD/MMC

T 25 SDDAT0_0 S GPIOB1 SDDAT0_0 – – U 24 SDDAT0_1 S GPIOB3 SDDAT0_1 – – U 25 SDDAT0_2 S GPIOB5 SDDAT0_2 – – V 24 SDDAT0_3 S GPIOB7 SDDAT0_3 – – T 24 SDCLK0 S GPIOA29 SDCLK0 – – U 23 SDCMD0 S GPIOA31 SDCMD0 – – AD 22 SDWP0 S SA5 GPIOC5 UARTnCTS1 SDWP0 AE 22 SDnCD0 S SA6 GPIOC6 UARTnRTS1 SDnCD0 Y 21 SDnRST0 S SA3 GPIOC3 HDMI_CEC SDnRST0 AC 22 SDnINT0 S SA4 GPIOC4 UARTnDCD1 SDnINT0 AA 18 SDDAT1_0 S GPIOD24 SDDAT1_0 – – AA 17 SDDAT1_1 S GPIOD25 SDDAT1_1 – – Y 15 SDDAT1_2 S GPIOD26 SDDAT1_2 – – Y 14 SDDAT1_3 S GPIOD27 SDDAT1_3 – – AA 20 SDCLK1 S GPIOD22 SDCLK1 – – AA 19 SDCMD1 S GPIOD23 SDCMD1 – – Y 18 SDWP1 S GPIOD20 UARTTXD2 – SDWP1 W 17 SDnCD1 S GPIOD21 UARTTXD3 – SDnCD1 AE 21 SDnRST1 S SA7 GPIOC7 UARTnDSR1 SDnRST1 AD 21 SDnINT1 S SA8 GPIOC8 UARTnDTR1 SDnINT1 AB 11 SDDAT2_0 S SA20 GPIOC20 SDDAT2_0 VID2_3 Y 11 SDDAT2_1 S SA21 GPIOC21 SDDAT2_1 VID2_4 AC 14 SDDAT2_2 S SA22 GPIOC22 SDDAT2_2 VID2_5 AC 12 SDDAT2_3 S SA23 GPIOC23 SDDAT2_3 VID2_6 AB 12 SDCLK2 S SA18 GPIOC18 SDCLK2 VID2_1 AB 14 SDCMD2 S SA19 GPIOC19 SDCMD2 VID2_2 AD 19 SDWP2 S GPIOD18 UARTTXD0 ISO7816 SDWP2 AD 18 SDnCD2 S GPIOD19 UARTTXD1 ISO7816 SDnCD2 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-38 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 V 15 SDnRST2 S SA12 GPIOC12 SPITXD2 SDnRST2 V 14 SDnINT2 S SA13 GPIOC13 PWM1 SDnINT2 2.3.2.19 USB2.0 HOST Ball Name Type Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 F 25 USB2.0HOST_DP S USB2.0HOST_DP – – – F 24 USB2.0HOST_DM S USB2.0HOST_DM – – – G 25 USB2.0HOST_RK ELVIN S USB2.0HOST_RK ELVIN – – – 2.3.2.20 USB2.0 HSIC HOST Ball Name Type Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 H 24 USBHSIC_DATA S USBHSIC_DATA – – – H 25 USBHSIC_STROB E S USBHSIC_STROB E – – – 2.3.2.21 USB2.0 OTG Ball Name Type Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 D 25 USB2.0OTG_DP S USB2.0OTG_DP – – – D 24 USB2.0OTG_DM S USB2.0OTG_DM – – – E 25 USB2.0OTG_RKE LVIN S USB2.0OTG_RKE LVIN – – – C 25 USB2.0OTG_ID S USB2.0OTG_ID – – – C 24 USB2.0OTG_VBU S S USB2.0OTG_VBU S – – – W 14 USB2.0OTG_DrvV BUS S SA11 GPIOC11 SPIRXD2 USB2.0OTG_ DrvVBUS E 24 USB2.0OTG_USB VBUS S USB2.0OTG_USB VBUS – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-39 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2.22 I2S& AC97

AD 15 I2SDOUT0 S GPIOD9 I2SDOUT0 AC97_DOUT – AC 15 I2SDIN0 S GPIOD11 I2SDIN0 AC97_DIN – AB 15 I2SBCLK0 S GPIOD10 I2SBCLK0 AC97_BCLK – AA 15 I2SMCLK0 S GPIOD13 I2SMCLK0 AC97_nRST – AC 17 I2SLRCLK0 S GPIOD12 I2SLRCLK0 AC97_SYNC – R 20 I2SDOUT1 S GPIOB6 VID1_4 SDEX4 I2SDOUT1 V 20 I2SDIN1 S GPIOB9 VID1_6 SDEX6 I2SDIN1 J 21 I2SBCLK1 S GPIOA30 VID1_0 SDEX0 I2SBCLK1 J 20 I2SMCLK1 S GPIOA28 VICLK1 I2SMCLK2 I2SMCLK1 L 20 I2SLRCLK1 S GPIOB0 VID1_1 SDEX1 I2SLRCLK1 U 20 I2SDOUT2 S GPIOB8 VID1_5 SDEX5 I2SDOUT2 W 21 I2SDIN2 S GPIOB10 VID1_7 SDEX7 I2SDIN2 M 20 I2SBCLK2 S GPIOB2 VID1_2 SDEX2 I2SBCLK2 J 20 I2SMCLK2 S GPIOA28 VICLK1 I2SMCLK2 I2SMCLK1 P 20 I2SLRCLK2 S GPIOB4 VID1_3 SDEX3 I2SLRCLK2

2.3.2.23 ADC

AE 3 ADC0 S ADC0 – – – AB 5 ADC1 S ADC1 – – – AD 3 ADC2 S ADC2 – – – AE 2 ADC3 S ADC3 – – – AC1 ADC4 S ADC4 – – – AD1 ADC5 S ADC5 – – – AD 2 ADC6 S ADC6 – – – AD 6 ADC7 S ADC7 – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-40 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2.24 ALIVE GPIO

AB 8 ALIVEGPIO0 S ALIVEGPIO0 – – – AA 8 ALIVEGPIO1 S ALIVEGPIO1 – – – AA 7 ALIVEGPIO2 S ALIVEGPIO2 – – – Y 9 ALIVEGPIO3 S ALIVEGPIO3 – – – Y 8 ALIVEGPIO4 S ALIVEGPIO4 – – – W 9 ALIVEGPIO5 S ALIVEGPIO5 – – –

2.3.2.25 JTAG

V 6 NTRST S NTRST GPIOE25 – – Y 5 TMS S TMS GPIOE26 – – W 5 TDI S TDI GPIOE27 – – AA 6 TCLK S TCLK GPIOE28 – – Y 7 TDO S TDO GPIOE29 – –

2.3.2.26 Crystal PLL & RTC

A 20 PLLXTI S PLLXTI – – – B 20 PLLXTO S PLLXTO – – – AE 4 RTCXTI S RTCXTI – – – AD 4 RTCXTO S RTCXTO – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-41 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

2.3.2.27 Miscellaneous

Ball Name Type Alternate Function 0 Alternate Function 1 Alternate Function 2 Alternate Function 3 AE1 NRESET S NRESET – – – AB 7 NGRESETOUT S NGRESETOUT – – – AB 6 VDDPWRON S VDDPWRON – – – AC 6 VDDPWRON_DDR S VDDPWRON_DDR – – – AE 6 NVDDPWRTOGGL E S NVDDPWRTOGGLE – – – AB 2 NBATF S NBATF – – – AE 7 TEST_EN S TEST_EN – – – AD 8 WIRE0 S WIRE0 – – – AE 8 WIRE1 S WIRE1 – – – AD 7 EFUSE_FSOURCE S EFUSE_FSOURCE – – –

2.3.2.28 Power: VDD

Ball Name Type Description D5, D6, E6, E7, E8, G11, J12, J14, K11, K13, K15, L12, L14, L16, L17, M11, M13, M15, N12, P11, R12, T11, U12, V11, V12, W11, W12 VDDI P 1.0 V for CORE N14, N16, P13, P15, P16, R14, R15, R16, T14, T15, T16, U14, U15 VDDI_ARM P 1.0 V to 1.3 V for CPU. K9, K10, L9, L10, M9, M10, N9, N10, P9, P10, R9, R10, T9, T10 VDDQ P 1.5 V for DDR3 IO U10, U11, V9 VDDP18 P 1.8 V for Internal IO L19, M19, P19, R18, R19, U18, U19, V17 DVDD33_IO P 3.3 V for IO E23 DVDD10_USB0 P 1.0 V for USB G23 DVDD10_USBHOST0 P 1.0 V for USB HOST F23 VDD18_USB0 P 1.8 V for USB F21 VDD18_USBHOST P 1.8 V for USB HOST E22 VDD33_USB0 P 3.3 V for USB G24 VDD33_USBHOST P 3.3 V for USB HOST H23 DVDD12_HSIC P 1.2 V for USB HSIC HOST AC8 VDDI10_ALIVE P 1.0 V for ALIVE V7 VDDP18_ALIVE P 1.8 V for Internal IO ALIVE W8 VDD33_ALIVE P 3.3 V for ALIVE AC4, AC7 VDD18_RTC P 1.8 V for RTC cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 2 Mechanical Dimension and I/O Pin Description 2-42 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Ball Name Type Description D20 VDD18_OSC P 1.8 V for Crystal G14 AVDD10_LV P 1.0 V for LVDS F15 AVDD18_LV P 1.8 V for LVDS C22 AVDD10_HM P 1.0 V for HDMI F19 VDD10_HM_PLL P 1.0 V for HDMI PLL D23 VDD18_HM P 1.8 V for HDMI C8 M_VDD10_PLL P 1.0 V for MIPI PLL C4, C5, D7, D8 M_VDD10 P 1.0 V for MIPI C6 M_VDD18 P 1.8 V for MIPI AC5 AVDD18_ADC P 1.8 V for ADC AC2 ADCREF P 1.8 V for ADC reference VDD C21, D19, D21, E20 AVDD18_PLL P 1.8 V for PLL T13, U13 DVDD_VID2_SD2 P 2.8 V for VID2/SD2 AA12 DVDD_VID0 P 2.8 V for VID0 F14 DVDD_GMAC P 2.8 V for Ethernet MAC

2.3.2.29 Power: GND

Ball Name Type Description A6, A19, B6, B19, C9, D9, E9, F7, F8, F9, F22, G8, G9, G12, G17, G21, G22, H6, H7, H9, H11, H12, H14, H15, H17, H19, H20, J7, J8, J10, J11, J13, J15, J16, J18, J19, K12, K14, K16, K17, L6, L7, L8, L11, L13, L15, L18, M6, M7, M8, M12, 14, M16, M17, M18, N11, N13, N15, N17, P6, P7, P8, P12, P14, P17, P18, R6, R7, R8, R11, R13, R17, T12, T17, U6, U7, U8, U16, W15, W18 VSSI G Digital GND C20 VSS18_OSC G GND for 1.8 V Crystal VDD G15 AVSS10_LV G GND for 1.0 V LVDS VDD F11, F12 AVSS18_LV G GND for 1.8 V LVDS VDD AD5 AVSS18_ADC G GND for 1.8 V ADC VDD E19, F17, F18, G18 AVSS18_PLL G GND for 1.8 V PLL VDD cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

3 System Boot

3.1 Overview

S5P4418 supports various system boot modes. Boot Mode is determined by System Configuration when boot reset off.  External Static Memory Boot  Internal ROM Boot  NAND boot with Error Correction  SD/MMC/eMMC boot  SPI Serial EEPROM boot  UART boot  USB boot cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

3.2 Functional Description

3.2.1 System Configuration

Table 3-1 System Configuration by RST_CFG Pins Pins RST_CFG Static Memory SDFS(TBD) UART Serial Flash SD MMC USB Device Nand SD0 RST_CFG0 0 1 1 0 1 0 1 SD1 RST_CFG1 0 0 1 0 0 1 1 SD2 RST_CFG2 0 0 0 1 1 1 1 SD3 RST_CFG3 - Port_Num0 Port_Num0 Port_Num0 Port_Num0 - SELCS SD4 RST_CFG4 ADDRWIDTH0 eMMCBOOTMODE SD5 RST_CFG5 ADDRWIDTH1 PARTITION SD6 RST_CFG6 BAUD SPEED eMMCBOOT SD7 RST_CFG7 DISD0 RST_CFG8 LATADDR LATADDR LATADDR LATADDR LATADDR LATADDR LATADDR DISD1 RST_CFG9 BUSWIDTH 0 0 0 0 0 0 DISD2 RST_CFG10 NANDPAGE1 DISD3 RST_CFG11 NANDTYPE0 DISD4 RST_CFG12 NANDTYPE1 DISD5 RST_CFG13 NANDPAGE0 DISD6 RST_CFG14 DECRYPT DECRYPT DECRYPT DECRYPT DECRYPT DECRYPT DISD7 RST_CFG15 I-Cache I-Cache I-Cache I-Cache I-Cache I-Cache VID1[0] RST_CFG16 Next Try Next Try Next Try Next Try VID1[1] RST_CFG17 SEL_VBUS VID1[2] RST_CFG18 Next Port Next Port Next Port Next Port VID1[3] RST_CFG19 Port_Num1 Port_Num1 Port_Num1 Port_Num1 VID1[4] RST_CFG20 USE_FS USE_FS(TBD) USE_FS(TBD) VID1[5] RST_CFG21 VID1[6] RST_CFG22 VID1[7] RST_CFG23 CORE_VOLTAGE CORE_VOLTAGE CORE_VOLTAGE CORE_VOLTAGE CORE_ VOLTAGE CORE_ VOLTAGE cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Table 3-2 System Configuration by Function Name Pin RST_CFG Note NANDTYPE[1:0] DISD[4:3] RST_CFG[12:11] NAND flash Memory Type on SD Bus 0: Small Block 3 Address 1: Small block 4 Address 2: Large 4 Address 3: Large 5 Address NANDPAGE [1:0] DISD5 RST_CFG13 Pagesize of Large NAND Flash on SD Bus 0: 2K 1: 4K or above SELCS DISD2 RST_CFG10 NAND Chip Select When SD bus  0:nNCS0 1:nNCS1 When SDEX bus  nNCS1. (Not selectable) DECRYPT DISD6 RST_CFG14 AES ECB mode decrypt 0: not decrypt 1: decrypt I-Cache DISD7 RST_CFG15 I-Cache Enable 0: Disable 1: Enable eMMC Boot Mode SD4 RST_CFG4 SD / eMMC Boot Selection 0: Normal SD Boot 1: eMMC Boot PARTITION SD5 RST_CFG5 Boot Parition on eMMC 0: Default Partition 1: Boot Partition (Partition#1) ADDRWIDTH[1:0] SD[5:4] RST_CFG[5:4] Serial Flash Address width 0: 16-bit 1: 24-bit 2: 32-bit eMMCBOOT SD6 RST_CFG6 Alternative / Normal Boot Selection 0: Alternative Boot 1: Normal Boot BAUD SD6 RST_CFG6 UART Baudrate 0: 19200bps 1: 115200bps SPEED SD6 RST_CFG6 Serial Flash Speed 0: 1 MHz 1: 16 MHz LATADDR DISD0 RST_CFG8 Static Latched Address 0: None 1: Latched BootMode[2:0] SD[2:0] RST_CFG[2:0] Boot Mode Select 0: Static Memory 3: UART 4: SPI 5: SDMMC 6: USB 7: NAND Port Num[1:0] Core Voltage Vbus_Level VID1[1] RST_CFG17 Vbus Detect Host Voltage Level 0: 5 V 1: 3.3 V Boot Scenario cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Table 3-3 Boot Scenario NextTry USE_FS (TBD) NextPort Port SEL1 Port SEL0 BOOT MODE Boot Scenario x x x x x 6 USB 0 x x SPI0  USB

1 SPI1  USB

1 SPI2  USB

1 SPI0hs  USB

0 SPI0  SDs0  USB

1 SPI1  SDs1  USB

0 SPI2  SDs0  USB

1 SPI0hs  SDs1  USB

0 SPI0  SDs1  USB

1 SPI1  SDs0  USB

0 SPI2  SDs1  USB

1 SPI0hs  SDs0  USB

1, 5 SD0  USB

1 SD1  USB

0 SD2  USB

1 SD2hs  USB

0 SD0  SDs2  USB

1 SD1  SDs0  USB

0 SD2  SDs1  USB

1 SD2hs  SDs1  USB

0 SD0  SDs1  USB

1 SD1  SDs2  USB

0 SD2  SDs0  USB

1 SD2hs  SDs0  USB

NAND0  USB

1 NAND1  USB

0 NAND0  SDs0  USB

1 NAND1  SDs1  USB

0 NAND0  SDs2  USB

1 NAND1  SDs2hs 

0 NAND0  SDs1 USB

1 NAND1  SDs0  USB

1 0 NAND0  SDs2hs  cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. NextTry USE_FS (TBD) NextPort Port SEL1 Port SEL0 BOOT MODE Boot Scenario USB

1 NAND1  SDs2 USB

cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

3.3 External Static Memory Boot

CPU executes External Static Memory Access without CPU Hold.

3.3.1 External Static Memory Boot Features

Supports 16/8-bit Static Memory

3.3.2 External Static Memory Boot System Configuration

Table 3-4 External Static Memory not System Configuration Setting Description Pin Name Function Name Description RST_CFG[7:0] – Don't care RST_CFG8 CfgSTLATADD Static Latched Address (user select) 0 = None 1 = Latched RST_CFG[10:9] – Don't care RST_CFG11 CfgSTBUSWidth Static Bus Width (user select) 0 = 8-bit 1 = 16-bit RST_CFG[14:12] BOOTMODE[2:0] Pull-down RST_CFG[24:16] – Don't care

3.3.3 External Static Memory Boot Operation

In case of External Static Memory Boot, nSCS[0] is set to Address 0x00000000 by reset configuration and CPU can access Static Memory through MCU-S. Figure 3-1 External Static Memory Boot MCU-Static External Static Memory 0x00000000 CPU nSCS[0] cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

3.4 Internal ROM Boot

The chip has built-in 20 KB ROM. It is possible to set Internal ROM address to 0th address by setting CfgBOOTMODE of System Configuration to "3 to 7". After Reset, CPU executes instruction fetched from 0th address of the Internal ROM. Internal ROM has a code supporting various Booting methods. This ROM code executes User Bootcode by reading it through various media and loading it to specific memory. This Booting method is defined as internal ROM Booting (which is, from now on, called iROMBOOT). iROMBOOT uses internal SRAM for storing stack or data. Therefore it is possible for the content of internal SRAM to change after iROMBOOT is executed.

3.4.1 Features

 Supports five booting modes: SPI Serial EEPROM BOOT, UART BOOT, USBBOOT, SDHCBOOT and NANDBOOT with Error Correction  Supports CPU Exception Vector Redirection for OS systems without using MMU.  Supports Fast Power Control: Set VDDPWRON and VDDPWRON_DDR as High.

3.4.2 System Configuration for the Internal ROM booting

iROMBOOT supports 5 Booting modes such as USBBOOT, UART BOOT, SPI Serial EEPRO M BOOT, SDHCBOOT, and NANDBOOT with Error Correction. Every Booting mode supports various booting methods by referring to Reset states from SD[15:0] and SDEX[7: 0]. Table 3-5 shows System configuration for each Booting mode. Table 3-5 iROMBOOT System Configuration Pins iROMBOOT UART SPI Serial Flash SDMMC USB Device NANDBOOT with Error Correction RST_CFG[1:0]/ RST_CFG[17:16] Don't care NANDTYPE[1:0] RST_CFG[2,18] PAGESIZE RST_CFG[3] SELCS RST_CFG[4,20] DECRYPT RST_CFG[5 21] I-CACHE RST_CFG[6] Don't care OTG Session Check Don't care RST_CFG[7] Don't care eMMC Boot Mode Don't care RST_CFG[8] LATADDR RST_CFG[9] Don't care ADDRWIDTH0 PARTITION Don't care RST_CFG[10] ADDRWIDTH1 eMMCBOOT RST_CFG[11] BUSWIDTH = 0 RST_CFG[14:12] BOOTMODE = 3 BOOTMODE = 4 BOOTMODE = 5 BOOTMODE = 6 BOOTMODE = 7 RST_CFG[15] Don't care SEL SDEX cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

3.4.3 USB BOOT

iROMBOOT can load User Boot code via USB to memory and execute this code, which Booting method is called USBBOOT.

3.4.3.1 Features

 Supports Full speed or High Speed USB connection.  Uses the USB Bulk transfer.  Supports 64 bytes for Full speed and 512 bytes for High speed as Max packet size.

3.4.3.2 Operation

Figure 3-2 USBBOOT Operation USB Host Program should transfer User boot code by using bulk transfer through EP2 of USB Dev ice. The max packet size is changeable according to USB connection speed at Endpoint. In Full speed connection, USB Host Program can transfer the maximum 64 bytes as one packet and, in High speed connection, the maximum 512 bytes as one packet. USB Host Program should transfer the data packet of even size even though it can transfer the same packet as the max size or the packet smaller than the max size. USBBOOT writes User Boot code from USB Host Program and USBBOOT executes User Boot code by changing PC to 0xFFFF0000 after it receives User Boot code size of 16 KB. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

3.4.3.3 USB Descriptors

USB Host Program can get Descriptor of USBBOOT by using Get_Descriptor Request. Table 3-6 shows Descriptor of USBBOOT. USBBOOT has one configuration, one interface, and two additional Endpoints except Control Endpoint. However, Endpoint 1 exists only for compatibility. Then USBBOOT only receives data by using Endpoint2 only. Table 3-6 USBBOOT Description Offset Field Size USBBOOT Value

Description

0 bLength 1 18 Size of this descriptor in bytes 1 bDescriptorType 1 01h DEVICE descriptor type 2 bcdUSB 2 0110h 0200h USB spec release number in BCD 4 bDeviceClass 1 FFh Class code 5 bDeviceSubClass 1 FFh Subclass code 6 bDeviceProtocol 1 FFh Protocol code 7 bMaxPacketSize0 1 64 Maximum packet size for EP0 8 idVender 2 04E8h Vender ID 10 idProduct 2 1234h Product ID 12 bcdDevice 2 0000h Device release number in BCD 14 iManufacturer 1 0 Index of string descriptor describing manufacturer 15 iProduct 1 0 Index of string descriptor describing product 16 iSerialNumber 1 0 Index of string descriptor describing the device's serial number 17 bNumConfiguration 1 1 Number of possible configuration Configuration Descriptor 0 bLength 1 9 Size of this descriptor in bytes 1 bDescriptorType 1 02h CONFIGURATION descriptor type 2 wTotalLength 2 32 Total length of data returned for this con figuration 4 bNumInterfaces 1 1 Number of interfaces 5 bConfigurationValue 1 1 Value to use as an argument to the Set Configuration 6 iConfiguration 1 0 Index of string descriptor describing this con figuration 7 bmAttribute 1 80h Configuration characteristics 8 bMaxPower 1 25 Maximum power consumption Interface Descriptor 0 bLength 1 9 Size of this descriptor in bytes cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Offset Field Size USBBOOT Value 1 bDescriptorType 1 04h INTERFACE descriptor type 2 bInterfaceNumber 1 0 Number of this interface 3 bAlternateSetting 1 0 Value used to select this alternate setting 4 bNumEndpoints 1 2 Value used to select this alternate setting for the interface 5 bInterfaceClass 1 FFh Class code 6 bInterfaceSubClass 1 FFh Subclass code 7 bInterfaceProtocol 1 FFh Protocol code 8 iInterface 1 0 Index of string descriptor describing this interface Endpoint Descriptor for EP1 0 bLength 1 7 Size of this descriptor in bytes 1 bDescriptorType 1 05h ENDPOINT descriptor type 2 bEndpointAddress 1 81h The address of the endpoint 3 bmAttributes 1 02h the endpoint's attributes 4 wMaxPacketSize 2 64 512 Maximum packet size 6 bInterval 1 0 Interval for polling endpoint for data transfers Endpoint Descriptor for EP2 0 bLength 1 7 Size of this descriptor in bytes 1 bDescriptorType 1 05h ENDPOINT descriptor type 2 bEndpointAddress 1 02h The address of the endpoint 3 bmAttributes 1 02h the endpoint's attributes 4 wMaxPacketSize 2 64 512 Maximum packet size 6 bInterval 1 0 Interval for polling endpoint for data transfers cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

3.4.4 SDHCBOOT

iROMBOOT can execute User Boot code by reading it from SD memory card, MMC memory card, and eMMC and loading it to memory by using SDHC module. This method is called SDHCBOOT.

3.4.4.1 Features

 Supports SD/MMC memory card, and eMMC  Supports High Capacity SD/MMC memory card  Supports eMMC Booting  Supports Normal Booting and Alternate Booting  Supports only 4-bit data bus  Doesn't support BOOT_ACK  Outputs 400 kHz SDCLK for Identification and 22.9 MHz SDCLK for Data Transfer

3.4.4.2 Operation

Figure 3-3 SDHCBOOT Operation SDHCBOOT uses SDHC #0 module. The pins SDHC #0 module uses are GPIO A[29, 31] and GPIO B[1, 3, 5, 7]. SDHCBOOT provides various Booting methods according to CFG pins, in which the specification of each method is recommended to refer to Table 3-1. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. User Boot code should be written as Table 3-7 to Storage Device for the use of SDHCBOOT. Table 3-7 Boot Data Format for SDHCBOOT Sector Name Description

0 RESERVED

SDHCBOOT don't care data in 0^ th^ Sector. Therefore it is possible to use 0^ th^ Sector for storing MBR (Master Boot record), and to include User Boot code along with File System into one Physical Partition. 1 to 32 User Boot code Boot code User made has 16 KB size from 2nd Sector to 32st Sector The SDHCBOOT Booting process is as follows.  eMMC Booting: SDHCBOOT executes eMMC Booting in case that CfgSDHCBM is 1.  When CfgEMMCBM is "1", Normal eMMC Booting is executed, and when CfgEMMCBM is "0", Alternate eMMC Booting is executed.  For eMMC Booting, SDHCBOOT always uses 4-bit data bus. Therefore BOOT_BUS_WIDTH of EXT_CSD should be set to "1." And BOOT_ACK of EXT_CSD should be set to "0" because BOOT_ACK is not available for eMMCBooting.  Normal SDMMC Booting is processed when no Data is transferred from Card in 1 second.  512 bytes first transferred from Card are not used.  512 bytes secondly transferred from Card are used.  User Boot code transferred from Card is loaded to internal SRAM to be executed. Figure 3-4 eMMC Boot  Normal SDMMC Booting is executed when CfgSDHCBM is "0", or eMMC Booting fails.  Go idle state  SDHCBOOT identifies the type of Card and initializes.  The state of Card changes to Data Transfer Mode.  SDHCBOOT selects partition according to CfgPARTITION.  SDHCBOOT reads User Boot code from Sector #1, and load it to internal SRAM to be executed. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

3.4.5 NANDBOOT with Error Correction

iROMBOOT provides the booting method which can correct any error in User Boot code stored in NAND Flash memory. This Booting method is described as NANDBOOT with Error Corre ction (which is abbreviated to NANDBOOTEC).

3.4.5.1 Features

 Supports Error Correction for up to 24-bit errors per 551 bytes: User Boot code 512 bytes + parity 39 bytes and 60-bit errors per 1129 bytes: User Boot code 1024 bytes + parity 105 bytes.  Supports 512B, 2 KB, 4 KB, and above as the page size of the NAND flash memory.  Supports NAND flash memories required RESET command to initialize them.  Doesn't support the bad block management.

3.4.5.2 Operation

Figure 3-5 NANDBOOTEC Operation NANDBOOTEC can correct the errors which occur in User Boot code stored in NAND flash memory. Whenever NANDBOOTEC reads User Boot code from NAND flash memory by 512 bytes or 1024 bytes, it gets to know whether any error of Data exists or not by using Error detection function of H/W BCH decoder included in MCU-S. In case of any error in Data, the maximum 24 or 60 errors can be corrected through H/W Error Correction. If Error Correction fails, Booting with USB Boot mode. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

3.4.5.3 How to Store User Boot code into the NAND Flash Memory

Table 3-8 shows the written form of User Boot code into NAND flash memory. NANDBOOTEC uses the main memory of NAND flash memory and doesn't use the spared area of it. Table 3-8 NAND Flash Memory Format for NANDBOOTEC Sector Data Page Size ECC #n 64 bytes  8 = 512 bytes 512B – LSB (312-bit) MSB (200-bit)

0 ECC #0 page #0 LSB 39

1 Bin #0 page #1 – Parity for sector # (n  8 + 1) Reserved

2 Bin #1 page #2 – Parity for sector # (n  8 + 2) Reserved

3 Bin #2 page #3 – Parity for sector # (n  8 + 3) Reserved

4 Bin #3 page #4 – Parity for sector # (n  8 + 4) Reserved

5 Bin #4 page #5 – Parity for sector # (n  8 + 5) Reserved

6 Bin #5 page #6 – Parity for sector # (n  8 + 6) Reserved

7 Bin #6 page #7 MSB 39

bytes Parity for sector # (n  8 + 7) Reserved

12 Bin #10 page #12 – – –

13 Bin #11 page #13 – – –

14 Bin #12 page #14 – – –

15 Bin #13 page #15 – – –

17 Bin #14 page #17 – – –

18 Bin #15 page #18 – – –

19 Bin #16 page #19 – – –

20 Bin #17 page #20 – – –

21 Bin #18 page #21 – – –

22 Bin #19 page #22 – – –

23 Bin #20 page #23 – – –

25 Bin #21 page #25 – – –

26 Bin #22 page #26 – – –

27 Bin #23 page #27 – – –

28 Bin #24 page #28 – – –

29 Bin #25 page #29 – – –

cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Sector Data Page Size ECC #n 64 bytes  8 = 512 bytes 512B – LSB (312-bit) MSB (200-bit)

30 Bin #26 page #30 – – –

31 Bin #27 page #31 – – –

33 Bin #28 page #33 – – –

34 Bin #29 Page #34 – – –

34 Bin #30 page #35 – – –

35 Bin #31 page # 36 – – –

Page Size ECC #n 128 bytes  8 = 1024 bytes

2 KB 4 KB 8K – LSB (840-bit) MSB (184-bit)

0 ECC #0 page #0

page #0 page #0 LSB 105 bytes Reserved

1 Bin #0 page #1 – Parity for sector

# (n  8 + 1) Reserved

2 Bin #1 page #2

page #1 – Parity for sector # (n  8 + 2) Reserved

3 Bin #2 page #3 Parity for sector

# (n  8 + 3) Reserved –

4 Bin #3 page #4

page #2 page #1 – Parity for sector # (n  8 + 4) Reserved

5 Bin #4 page #5 – Parity for sector

# (n  8 + 5) Reserved

6 Bin #5 page #6

page #3 – Parity for sector # (n  8 + 6) Reserved

7 Bin #6 page #7 Parity for sector

# (n  8 + 7) Reserved –

8 ECC #1 page #8

page #4 page #2 – – –

10 Bin #8 page #10

page #5 – – –

12 Bin #10 page #12

page #6 page #3 – – –

14 Bin #12 page #14

page #7 – – –

16 ECC #1 page #16

page #8 page #4 – – –

18 Bin #15 page #18

page #9 – – – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

3.4.6 Additional Information

3.4.6.1 ALIVE POWER Control

iROMBOOT changes VDDPWRON and VDDPWRON_DDR pins to High state after Reset in order to supports the fast response to nVDDPWRTOGGLE button. Table 3-9 shows ALIVE module states after iROMBOOT Execution. Table 3-9 ALIVE Power Control Function State Description VDDPWRON High Enable Core Power VDDPWRON_DDR High Enable DDR Memory Power nPADHOLD[2:0] High Disable PAD Retention nPADHOLDEnb[2:0] Low

3.4.6.2 Exception Vector Redirection

Exception Handler of ARM CPU should exist from 0th address by 4 byte one after the other. User generally places the routine jumping to User's Exception Handler to the Exception Handler existing from 0th address. However, in case of iROMBOOT, User's Exception Handler is impossible to set at 0th address because ROM exists at 0thaddress. CPU Exception can be processed by mapping the arbitrary memory to 0th address when MMU is being used. However iROMBOOT provides the function redirecting Exception Handler for the System not using MMU. iROMBOOT uses 32 bytes from the lowest address of internal SRAM as User Exception Vector Table. When Exception occurs, ROM Exception Handler in iROMBOOT lets PC jump to the address of User Exception Handler taken from User Exception Vector Table. Therefore Exception can be processed even at Ph ysical address system by User's setting the address of User Exception Handler to User Exception Vector Table present in internal SRAM and that is equal to High Vector Address. #define BASEADDR_SRAM 0xFFFF0000 Example 3-1 iROMBOOT Exception Handlers //; Vectors .global Vectors Vectors: LDR pc, ResetV //; 00 - Reset LDR pc, UndefV //; 04 - Undefined instructions LDR pc, SWIV //; 08 - SWI instructions LDR pc, PAbortV //; 0C - Instruction fetch aborts LDR pc, DAbortV //; 10 - Data access aborts LDR pc, UnusedV //; 14 - Reserved (was address exception) LDR pc, IRQV //; 18 - IRQ interrupts LDR pc, FIQV //; 1C - FIQ interrupts ResetV: .word Reset_Handler UndefV: cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. .word (BASEADDR_SRAM + 0x04) //; 04 - undef SWIV: .word (BASEADDR_SRAM + 0x08) //; 08 - software interrupt PAbortV: .word (BASEADDR_SRAM + 0x0C) //; 0C - prefetch abort DAbortV: .word (BASEADDR_SRAM + 0x10) //; 10 - data abort UnusedV: .word 0 //; 14 - will reset if called... IRQV: .word (BASEADDR_SRAM + 0x18) //; 18 - IRQ FIQV: .word (BASEADDR_SRAM + 0x1C) //; 1C - FIQ //; Imports .global iROMBOOT //; Reset Handler - Generic initialization, run by all CPUs Reset_Handler:

3.4.6.3 Parity Generation for Error Correction

NANDBOOTEC can correct the maximum 24 errors in User Boot code 512 bytes and Parity 39 bytes or maximum 60 errors in User Boot code 1024 bytes and Parity 105 bytes. Therefore, by generating Parity 39 bytes at every 512 bytes of User Boot code, User should write the parity information to ECC Sector. For NANDBOOTEC, the number of Parity information varies according to the size of User Boot code. It is recommended to refer to the description of NANDBOOTEC about the site in which Parity information should be located. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 3 System Boot 3-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

3.4.6.4 CRC32 Error Check

UART and SPI Boot check 16368 (16384 - 16) bytes with CRC32 and if adding CRC32 fcs data to last of transfer of payload then CRC32 fcs will checking will success. CRC32 fcs generator function. #define POLY 0x04C11DB7L unsigned int get_fcs(unsigned int fcs, unsigned char data) register int i; fcs ^= (unsigned int)data; for(i=0; i<8; i++) if(fcs & 0x01) fcs ^= POLY; fcs >>= 1; return fcs; #define POLY 0x04C11DB7L unsigned int get_fcs(unsigned int fcs, unsigned char data) register int i; fcs ^= (unsigned int)data; for(i=0; i<8; i++) if(fcs & 0x01) fcs ^= POLY; fcs >>= 1; return fcs;

3.4.6.5 Data Decryption with AES128 ECB Mode to Use Hidden Key

All boot mode data will decrypted with AES128 ECB mode to use hidden key by option. Boot mode sd[4], sdex[4] can select weather data will decrypt or not decrypt. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4 System Control

4.1 Overview

The clock of the S5P4418 is roughly divided into FCLK, HCLK, MCLK, BCLK and PCLK are used for the ARM CPU core, AXI bus peripherals and APB bus peripherals, respectively. In addition, BCLK is the clock for the S5P4418 system bus. MCLK is the clock for SDRAM memory. The 2-PLL of the S5P4418 is called PLL0 and PLL1, respectively. The 2-PLL and EXTCLK are used to generate the above clocks (i.e. FCLK, HCLK, PCLK, BCLK, MCLK). All PLLs are designed to operate with an X-TAL input of 24MHz.

4.2 Features

 Embedded 4-PLL operating independently  Output Frequency Range  PLL0: 40M to 2.5 GHz (non-dithered PLL)  PLL1: 40M to 2.5 GHz (non-dithered PLL)  PLL2: 35M to 2.2 GHz (dithered PLL)  PLL3: 35M to 2.2 GHz (dithered PLL)  Frequency is changed by Programmable Divider (PDIV, MDIV, SDIV)  Clock generation for all blocks in the chip  The PLLs can be switched into Power Down mode by using the program.  32.768 kHz supported for Power Management  Various Power Down Modes  IDLE mode and STOP mode  Various Wake Up sources cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.3 Block Diagram

The above figure shows a diagram for the clock manager in the S5P4418. As shown in the above figure, the S5P4418 has four PLLs. The S5P4418 receives the output of PLLs and generates all system clocks, the memory clock and the CPU clock with the output frequency selected among many PLLs. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.4 Functional Description

4.4.1 PLL (Phase Locked Loop)

4.4.1.1 PMS Value

Figure 4-2 Block Diagram of PLL For the aspect of PLL structure, Figure 4-2 shows the block diagram for one PLL. Fin and Fout indicate input frequency and output frequency respectively. The S5P4418 has PLLs and can generate various programmable clocks by using each PLL. If the Pre Divider receives a Fin input of 24 MHz, it divides the Fin with "P". After that, Phase Frequency Detector (PFD) compares the difference between Fin/P (Reference Clock) and Fvco/M (Feedback Clock). The amplitude of the voltage varies depending on the difference of the values compared between Fin/P and Fvco/M. If the reference clock is faster feed back block, the Voltage Controlled Oscillator (VCO) increases in proportion to the difference. If the reference clock is delayed than the feed clock, VCO is decreased, and it generates an Fvco clock. That is because VCO is a voltage value and plays the role of controlling the clock speed to be faster or slower. At this point, the voltage value is determined by the difference of the values compared between the reference clock and the feedback clock. If the Fvco is not a desired clock, the feedback is recreated through the Main Divider and compared in PFD. These steps are repeated until the reference clock and the feedback clock become equal. If proper FVCO is out, the final Fout clock is created as the divide value(s) of a Post Scaler. Finally, the desired clock frequency is determined by the p, m and s values. As described above, Fout can be variously set by Fin and p/m/s values and the equation to specify p/m/s values is as follows: (Note that all PLL0/1/2/3 indicate Fout. Equation may vary for each case.)  PLL x = ( m x Fin)/(p x 2s)  (x = 0,1,2,3, m = MDIV, p = PDIV, s = SDIV = 0, 1, 2, 3)  The range of the MDIV and PDIV values for PLL x are as follows:  Range of MDIV Value: 64 ≤ MDIV ≤ 1023  Range of PDIV Value: 1 ≤ PDIV ≤ 63 Fin Pre DIVIDER (p) P[5..0] Phase Frequency Detector Voltage Controlled Oscillator Post Scaler (s) Fout Main DIVIDER (m) FvcoFin/P M[7..0] S[1..0] Fvco/M cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. The PDIV and the MDIV values should be selected by considering the VCO value and S5P4418's stable operation. The S5P4418 has PLLs and each PLL has different default values and operation ranges. The basic frequencies for the S5P4418 are listed in the table below: Table 4-1 Initial PDIV/MDIV/SDIV Value PLL INITIAL FREQUENCY RECOMMENDED FREQUENCY (Fvco) RECOMMENDED FREQUENCY (Fout) INITIAL PDIV/MDIV/SDIV VALUE PDIV MDIV SDIV PLL0 550.000000 MHz 1250 to 2500 MHz 40 to 2500 MHz 6 550 2 PLL1 147.456 MHz 1250 to 2500 MHz 40 to 2500 MHz 6 590 4 PLL2 96 MHz 40 to 2200 MHz 1100 to 2200 MHZ 3 192 4 PLL3 125 MHz 40 to 2200 MHz 1100 to 2200 MHz 3 250 4 For all blocks except for CPU, the operation status (Run/Stop) of the memory controller should be checked before changing the PLL output frequency. In addition, the PLL change bit (PWRMODE.CHGPLL) should be set as "1" after PLL change (PLLSETREG0, PLLSETREG1). Setting guide of PMSK  p, m, s and k are decimal values of P[5:0], M[8:0], S[2:0] and K[15:0], respectively.  FFVCO and FFOUT are calculated by the following equation.  FFVCO = ((m+k/65536)  FFIN)/p  FFOUT = ((m+k/65536)  FFIN)/(p  2s)  While range of registers P[5:0], M[8:0] and S[2:0] are unsigned integers, K[15:0] is a two 's complement integer.  6'b00 0001 ≤ P[5:0] ≤ 6'b11 1111 and 2MHz ≤ FFREF(FFIN/p) ≤ 30 MHz  9'b0 0100 0000 ≤ M[8:0] ≤ 9'b1 1111 1111  16'b1000 0000 0000 0000 ≤ K[15:0] ≤ 16'b0111 1111 1111 1111  Setting P[5:0] or M[8:0] to all zeros is strictly prohibited while RESETB is logic high. (6 'b00 0000/9'b0 0000 0000)  The division ratio of scaler is controlled by S[2:0] as summarized in Table 4-2.  Setting S[2:0] to the values in the gray rows in Table 4-2 is strictly prohibited. Table 4-2 Division Ratio of Scaler S[2:0] Division Ratio 000 20 = 1 001 21 = 2 010 22 = 4 011 23 = 8 100 24 = 16 101 25 = 32 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. S[2:0] Division Ratio

110 Prohibited

111 Prohibited

4.4.1.2 Setting Guide of SSCG_EN, SEL_PF, MFR and MRR

 When SSCG_EN is set to logic high, the spread spectrum mode is enabled.  sel_pf, mfr and mrr are decimal values of SEL_PF[1:0], MFR[7:0] and MRR[5:0], respectively.  sel_pf = SEL_PF[1:0], mfr = MFR[7:0], mrr = MRR[5:0]  Modulation frequency, MF, is determined by the following equation.  MF = FFIN/p/mfr/25[Hz]  Modulation rate (pk-pk), MR, is determined by the following equation.  MR = mfr  mrr/m/26  100 [%]  Modulation mode is determined by sel_pf.  00 = down spread 01 = up spread 1x = center spread  Range of registers.  8'b0000 0000 ≤ MFR[7:0] ≤ 8'b1111 1111  6'b00 0001 ≤ MRR[5:0] ≤ 6'b11 1111  0 ≤ mrr  mfr ≤ 512 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.4.1.3 PDIV/MDIV/SDIV Values for PLL0, PLL1

Table 4-3 PDIV/MDIV/SDIV Value for PLL0 Input Frequency Output Frequency (MHz) PDIV/MDIV/SDIV Value Remark PDIV MDIV SDIV 24 MHz 2000.000000 6 500 0 Maximum Available Frequency 24 MHz 1900.000000 6 475 0 – 24 MHz 1800.000000 4 300 0 – 24 MHz 1700.000000 6 425 0 – 24 MHz 1600.000000 6 400 0 – 24 MHz 1500.000000 4 250 0 – 24 MHz 1400.000000 6 350 0 – 24 MHz 1300.000000 6 325 0 – 24 MHz 1200.000000 4 400 1 – 24 MHz 1100.000000 6 550 1 – 24 MHz 1000.000000 6 500 1 – 24 MHz 900.000000 4 300 1 – 24 MHz 800.000000 6 400 1 Maximum Available Frequency 24 MHz 780.000000 4 260 1 – 24 MHz 760.000000 6 380 1 – 24 MHz 740.000000 6 370 1 – 24 MHz 720.000000 4 240 1 – 24 MHz 562.000000 6 562 2 – 24 MHz 533.000000 6 533 2 – 24 MHz 490.000000 6 490 2 – 24 MHz 470.000000 6 470 2 – 24 MHz 460.000000 6 460 2 – 24 MHz 450.000000 4 300 2 – 24 MHz 440.000000 6 440 2 – 24 MHz 430.000000 6 430 2 – 24 MHz 420.000000 4 280 2 – 24 MHz 410.000000 6 410 2 – 24 MHz 400.000000 6 400 2 – 24 MHz 399.000000 4 266 2 – 24 MHz 390.000000 4 260 2 – 24 MHz 384.000000 4 256 2 – 24 MHz 350.000000 6 350 2 – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Input Frequency Output Frequency (MHz) PDIV/MDIV/SDIV Value Remark PDIV MDIV SDIV 24 MHz 330.000000 4 220 2 – 24 MHz 300.000000 4 400 3 – 24 MHz 266.000000 6 532 3 – 24 MHz 250.000000 6 500 3 – 24 MHz 220.000000 6 440 3 – 24 MHz 200.000000 6 400 3 – 24 MHz 166.000000 6 332 3 – 24 MHz 147.45600 6 590 4 147.5 MHz (0.03% error 24 MHz 133.000000 6 532 4 – 24 MHz 125.000000 6 500 4 – 24 MHz 100.000000 6 400 4 – 24 MHz 96.000000 4 256 4 – 24 MHz 48.000000 3 96 4 –

4.4.1.4 PDIV/MDIV/SDIV Values for PLL2, PLL3

Table 4-4 PDIV/MDIV/SDIV Value for PLL1 Input Frequency Output Frequency (MHz) PDIV/MDIV/SDIV Value Remark PDIV MDIV SDIV 24 MHz 2000.000000 3 250 0 Maximum Available Frequency 24 MHz 1900.000000 3 238 0 – 24 MHz 1800.000000 3 225 0 – 24 MHz 1700.000000 3 213 0 – 24 MHz 1600.000000 3 200 0 – 24 MHz 1500.000000 4 250 0 – 24 MHz 1400.000000 3 175 0 – 24 MHz 1300.000000 3 163 0 – 24 MHz 1200.000000 3 150 0 – 24 MHz 1100.000000 3 275 1 – 24 MHz 1000.000000 3 250 1 – 24 MHz 900.000000 3 225 1 – 24 MHz 800.000000 3 200 1 Maximum Available Frequency 24 MHz 780.000000 3 195 1 – 24 MHz 760.000000 3 190 1 – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Input Frequency Output Frequency (MHz) PDIV/MDIV/SDIV Value Remark PDIV MDIV SDIV 24 MHz 740.000000 3 185 1 – 24 MHz 720.000000 3 180 1 – 24 MHz 562.000000 3 141 1 – 24 MHz 533.000000 3 267 2 – 24 MHz 490.000000 3 245 2 – 24 MHz 470.000000 3 235 2 – 24 MHz 460.000000 3 230 2 – 24 MHz 450.000000 3 225 2 – 24 MHz 440.000000 3 220 2 – 24 MHz 430.000000 3 215 2 – 24 MHz 420.000000 3 210 2 – 24 MHz 410.000000 3 205 2 – 24 MHz 400.000000 3 200 2 – 24 MHz 399.000000 4 266 2 – 24 MHz 390.000000 3 195 2 – 24 MHz 384.000000 3 192 2 – 24 MHz 350.000000 3 175 2 – 24 MHz 330.000000 3 165 2 – 24 MHz 300.000000 3 150 2 – 24 MHz 266.000000 3 266 3 – 24 MHz 250.000000 3 250 3 – 24 MHz 220.000000 3 220 3 – 24 MHz 200.000000 3 200 3 – 24 MHz 166.000000 3 166 3 – 24 MHz 147.45600 3 147 3 – 24 MHz 133.000000 3 266 4 – 24 MHz 125.000000 3 250 4 – 24 MHz 100.000000 3 200 4 – 24 MHz 96.000000 3 192 4 – 24 MHz 48.000000 3 96 4 – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.4.1.5 PLL Power Down

The S5P4418 supports PLL Power Down mode to minimize power consumption. For example, if all system clocks are generated with PLL0 and PLL1 does not need to be used. Therefore, power does not need to be supplied to the PLL1. In such a case, the S5P4418 switches PLL1 into power down mode to reduce the power consumption. However, PLL0 cannot enter to the power down mode. PLL0 power down can be achieved by writing "1" to the CLKMODEREG0.PLLPWDN1.

4.4.2 Change PLL Value

When CPU want to change the PLL divider value, The PLL Change Bit (PWRMODE.CHGPLL bit) must be set to 1 after setting the PLL Setting Reset (PLLSETREG0, PLLSETREG1) to appropriate value. Power management and Clock Controller blocks up the clock supplied to internal controllers because PLLs are unstable when PLL divider value is changed. After locking time, these blocks supply clock. CPU must check whether the blocks run or stop such as STOP mode. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.4.3 Clock Generator

4.4.3.1 Clocks Summary

The 5 clocks created in the S5P4418 and the maximum frequencies for each clock are listed in the table below. The minimum frequency is not limited within the clock frequency limit creatable in PLL. Table 4-5 S5P4418 Clock Summary Clock Name Min Frequency Max Frequency (MHz) Description FCLKCPU0 – 800/1000 (1) CPU CLOCK HCLKCPU0 – 250 CPU BUS CLOCK MDCLK – 800 Memory DLL clock. MCLK (NOTE) 800 Memory clock. NOTE: Minimum frequency of MCLK is determined by SDRAM specification. MBCLK – 400 Memory BUS CLOCK(MCU CLOCK) MPCLK – 200 Memory Peripheral clock. BCLK – 333 MHz SYSTEM BUS CLOCK (CORE CLOCK) CORE blocks operates on the basis of BCLK. (MPEG, DMA, etc…) PCLK – 166 MHz PERIPHERAL BUS CLOCK CPU accesses a block register via I/O with PCLK. GR3DBCLK – 333 GPU clock GR3DPCLK – – Not used. MPEGBCLK – 300 MFC clock. (BUS and CODEC) MPEGPCLK – 150 MFC clock (Peripheral clock) NOTE: In, note that the size of PCLK should be the half size of the BCLK when the maximum/minimum frequency values are specified. 1. CPU frequency is 800 MHz at 1.0 V and 1000 MHz at 1.1 V cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.4.3.2 CPU0 Clock

Figure 4-3 shows a block diagram that creates the clock supplied to FCLKCPU0, which is the main CPU of the S5P4418.CLKMODEREG0 selects a desired PLL output from among PLLs. With the clock created from t he selected PLL, the CLKDIV_FCLKCPU0 register and CLKDIV_HCLKCPU0 generates FCLKCPU0 to be supplied to the core block of CPU and HCLKCPU to be supplied to the AXI bus clock. Be careful not to set HCLKCPU over maximum speed. The frequency of FCLKCPU and HCLKCPU cannot be the same. Any PLL can be used to generate the CPU clock, but it is recommended to use the PLL0 Recommended clock frequency as follows: Table 4-6 Recommended Clock Frequency for CPU CPU Operation Voltage FCLKCPU0 (MHz) HCLKC'P'U0 (MHz)

1.0 V 800 200

1.1 V 1000 250

cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.4.3.3 System Bus Clock (Core clock)

Figure 4-4 System BUS Clock System bus clock (BCLK) is used as Core clock. The system bus clock is called [BCLK] and the half clock of BCLK is called [PCLK]. BCLK is the clock for all SOC Core operations. PCLK is used when the CPU accesses each block register via I/O. Therefore, PCLK should not be applied to the block s not being used. Every block has PCLK enable/disable Register. The blocks that PCLK is applied to have (refer to each Section). These registers decide if PCLK is applied to a block only when the CPU accesses the corresponding block register or when it is always applied. Clock frequency ratio should be as follows.  BCLK:PCLK = 2:1 Recommended clock frequency as follows: Table 4-7 Recommended clock Frequency for System BUS Mode BCLK (MHz) PCLK (MHz) max operation. 333 166 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.4.3.4 Memory Bus Clock (MCU Clock)

Figure 4-5 Memory BUS Clock Memory bus clock (MCLK) is used as SDRAM, MCU Core clock. MDCLK is the clock for DLL of Memory Control Unit (MCU). MCLK is the DDR interface clock. MBCLK is bus clock of MCU. MPCLK is peripheral bus clock of MCU. The MCLK frequency should be the double that of the MBCLK frequency. (BCLK to MCLK is a 1:2 ratio) Recommended clock frequency ratio is as follows.  MDCLK:MCLK:MBCLK:MPCLK = 4:4:2:1 Recommended clock frequency as follows: Table 4-8 Recommended clock Frequency for Memory BUS Mode MDCLK (MHz) MCLK (MHz) MBCLK (MHz) MPCLK (MHz) Fast 800 (NOTE) 800 400 200 Slow 800 200 100 50 NOTE: MDCLK should be divided by 2, i.e. CLKDIV_MDCLK should be 1. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.4.3.5 GPU (Graphic Processing Unit) clock

Figure 4-6 System BUS Clock GPU clock (GR3DBCLK) is used as GPU core clock. GR3DPCLK is not used (reserved). Recommended clock frequency as follows: Table 4-9 Recommended clock Frequency for GPU Mode GR3DBCLK (MHz) GR3DPCLK (MHz) Max operation. 333 166 (not used)

4.4.3.6 MFC (Multi-Function Codec) clock

Figure 4-7 System BUS Clock MFC clock (MPEGBCLK) is used as Multi-function codec clock. MPEGPCLK is used peripheral bus clock for MFC unit. Recommended clock frequency as follows: Table 4-10 Recommended clock Frequency for MFC Mode MPEGBCLK (MHz) MPEGPCLK (MHz) Max operation. 300 150 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.5 Power Manager

4.5.1 Power Manager Overview

The power manager of the S5P4418 provides the following functions to operate the system stably and reduce the power consumption.  Power Up Sequence  Reset Generation  Power Management  Change PLL Value The key functions of the power manager are to control the Power up Sequence to make the S5P4418 stable after the power is supplied to the system and to manage the power effectively. Apart from this, it controls the reset configuration in initial operation. In addition, this block generates various reset signals, such as External Reset Output (nRSTOUT), AliveGPIO Reset and Soft Reset.  The S5P4418 provides various Power Down modes to reduce the system power consumption. The three Power modes provided by the S5P4418 are as follows: Normal Mode  IDLE Mode  STOP Mode  SLEEP Mode (See the "ALIVE'' Section for SLEEP Mode) cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.5.2 Power Down Mode Operation

Figure 4-8 shows the state diagram for the Power Management Block. The figure indicates the entry conditions for each Power Down mode and all Wake Up conditions. Figure 4-8 Power Management Sequence POR Stable PLL0 & PLL1 Hold1 Normal StopStable X-tal Stable PLL0 & PLL1 ~nBATF nBATF CPU Request Wakeup ~nBATF 60ms ~nBATF 600us 600us cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  S5P4418 State  POR: Power On Reset State  Stable PLL: Wait for PLL locking time  NORMAL: Normal Operation State  STOP: Stop Operation Mode  Stable X-tal: Wait for Crystal's stable oscillation  Hold: Wait for nBATF = High.  Wake Up Source  SWRST: Software Reset  SWRSTENB: Software Reset Enable  ALIVEGPIO Event: ALIVE GPIO Wake Up Event  CPUIRQ: Interrupt from CPU(IDLE Mode)  RTCIRQ: Interrupt from RTC  BAFT: Battery Fault  VDDPWRTOGGLE: VDDPWRTOGGLE Switch Push Button  WRST: Watchdog Reset

4.5.2.1 IDLE Mode

In the IDLE mode, since the power and clocks are supplied to all blocks except for the CPU clock, power consumption can be reduced a bit. To enter to IDLE mode, the PWRMODE.IDLE Register should be set as "1". In IDLE Mode, the CPU clock is not supplied, but the power is normally supplied and PLLs operate normally. Wake-Up Source can use all the S5P4418 interrupts that can be generated by the Interrupt controller: GPIO Interrupt, Alive GPIO Interrupt, External Interrupt and RTC Interrupt. The interrupt for the Wake -Up Source should be enabled before entering to the IDLE Mode. The CPU returns to the previous status immediately after it is woken up in IDLE Mode. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.5.2.2 STOP Mode

In STOP mode, the clock is not supplied to all bocks including the ARM Core, because the PLL al so does not operate in the clock controller if the clock is not supplied to all blocks. However, the S5P4418 converts DRAM into Self Refresh mode to protect memory data before entering to STOP mode. Like IDLE m ode, the PWRMODE.STOP should be set as "1" to enter to STOP mode. The Wake Up source is slightly limited in STOP mode. The available Wake Up sources are RTC Interrupt, Alive GPIO Interrupt, etc. The Wake Up source is limited because the clock is not suppli ed to all the other blocks except for the power manager and RTC block. Since the RTC block uses a separate power and clock, only interrupts by the RTC clock can be used as a Wake Up source. Unlike with IDLE mode, all PLLs stop when the system is woken up in STOP mode so that the system cannot return to the previous status, immediately. Therefore, the Wake Up time is about 70 ms longer than that of IDLE mode to stabilize the internal PLLs. Table 4-11 Wake Up Condition and Power Down Mode Status Power Down Mode Power Supply CPU Clock Supply Other Clock Supply SDRAM Mode Wake Up Condition IDLE MODE ON OFF ON NORMAL RTC Interrupt, AliveGPIO Interrupt, All Interrupt to Interrupt Controller, External IRQ STOP MODE ON OFF OFF Self Refresh RTC Interrupt, AliveGPIO Interrupt cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.5.2.3 SLEEP Mode 1, SLEEP Mode 2

See the "ALIVE" Section for SLEEP Mode1 and SLEEP Mode2. Figure 4-9 Power Down Mode Sequence Figure 4-9 shows the sequence to enter the Power Down mode and the Wake Up procedure. First, the Wake Up source selects a desired event (interrupt) and specifies the attribute of the event. If the Wake up Source is GPIO, the setting is changed into Input and the Pending Clear is performed. In addition, the status to detect that an event (interrupt) is specified and Software Reset Enb is set as False for the worst case (If the Software Reset Enb switch is not implemented in terms of Hardware, False does not need to be specified). Finally, the system enables the relevant interrupt (if an interrupt is used) and enters a Power Down mode. In this Power Down mode, the S5P4418 a waits a Wake Up event (interrupt). If the Wake Up event (Interrupt) occurs, the S5P4418 returns to normal mode and clears the relevant interrupt pending in terms of Software. Wait for Wake Up Event Normal Mode Wake Up from IDLE/ Stop Mode Pending Clear GPIO Setting I/O : Input GPIO Wake Up Pending Clear (GPIOINTPEND REG) Detect Event Register Enable (GPIOWAKEUPRISEENB or GPIOWAKEUPFALLENB REG) GPIO Reset Enb = False (GPIORSTENB REG) Wake Up Event Enable (GPIOWAKEUPENB REG) RTC Setting RTC Wake Up Pending Clear (INTPEND REG) Wake Up Event Enable (RTCWAKEUPENB REG) RTC Wake up Enable (RTCWKENB REG) Enter Power Down Mode (PWRMODE) Interrupt Enable (INTENB REG) cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.5.2.4 GPIO as a Wake up Source

GPIO is available for all Power Down modes. However, since the internal power and the clock status are not equal for each power modes, the operation status is a little different at each power mode. Figure 4-10 Wake Up Block Diagram As shown in Figure 4-10, Power Manager use different clock. Since RTC-clock is always supplied to Power Manager Block, the PADs can be used as a Wake Up Source. The description of the Wake Up procedures in Power Down mode is as follows:  Wake Up in IDLE Mode During IDLE mode, clock and the power for the other blocks are supplied normally except CPU clock. Therefore, the input received in GPIO is applied to the interrupt controller and wakes up the CPU.  Wake Up in STOP Mode In STOP mode, all clocks except for the RTC clock are not supplied (PLL and XTI are included). The interrupt controller does not operate in STOP mode. At this time, if a signal is entered to Power Manager, the power manager wakes up the clock manager, first. As a result of this Wake Up, all clocks, such as the PLL and PCLK, BCLK, MCLK and FCLK, are enabled and supplied to the CPU and the whole system. In other words, the system is woken up. The Wake Up time is about 70 ms longer than that of IDLE mode to stabilize the PLLs. GPIO BGPIO Interrupt Controller CPU Power Manager RTC-Clocked Block GPIO PLL-clocked Block Clock Manager Clock Active VDDPWRTOGGLE RTC RTC clock AliveGPIO BATF RTCIRQ cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.6 Reset Generation

4.6.1 Power on Reset Sequence

Power management block has the reset generation block. The reset generation block uses the nPORST which is sampled at RTC clock (32.768 kHz). And the RTC clock is used as main clock for power management. So Even if the RTC Function is not used, the RTC clock must be supplied. Figure 4-11 shows the clock and reset behavior during the power-on reset sequence. Figure 4-11 Power-On Reset Sequence Table 4-12 Power-On Reset Timing Parameters Symbol Min (MSEC) Max (MSEC) Description tALIVE –50 Infinity RTC to VDDI10_ALIVE tALIVEIO 0 50 VDDI10_ALIVE to ALIVE IO power tCORE 0 Infinity VDDP18_ALIVE/VDD33_ALIVE to VDDI tARM 0 50 VDDI to VDDI_ARM tDDR 0 150 VDDI_ARM to VDDQ (DDR IO power) tIO 0 150 VDDI_ARM to DVDD33_IO (normal IO power) tALL 0 150 VDDI_ARM to DVDD33_IO (normal IO power) tRESETIN 0 Infinity All power on to assert nRESET tRESETOUT 200 200 NRESET to NGRESETOUT NOTE: Other VDD: this mean all other powers like analog power. VDD18_RTC VDDI10_ALIVE VDDP18_ALIVE VDD33_ALIVE VDDI (CORE) VDDI_ARM VDDQ (DDR) **OTHER VDD NRESET (input) NGRESETOUT (output) tRESETOUT tDDR tRESETIN tALL tARM tCORE tALIVE tALIVEIO tALIVEIO VDDP18 DVDD33_IO tIO tIO cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.6.2 Sleep Mode Wakeup Sequence

All ALIVE and RTC power should be powered on before asserting sleep mode wakeup sequence. Figure 4-12 Power On Sequence for Wakeup Table 4-13 Wakeup Timing Parameters Symbol Min (MSEC) Max (MSEC) Description tARM 0 50 VDDI to VDDI_ARM tDDR 0 150 VDDI_ARM to VDDQ (DDR IO power) tIO 0 150 VDDI_ARM to DVDD33_IO (normal IO power) tALL 0 150 VDDI_ARM to DVDD33_IO (normal IO power) tRESETIN 0 Infinity All power on to assert nRESET tRESETOUT 200 200 NRESET to NGRESETOUT NOTE: Other VDD: this mean all other powers like analog power. VDDI (CORE) VDDI_ARM VDDQ (DDR) **OTHER VDD NRESET (input) NGRESETOUT (output) tRESETOUT tDDR tRESETIN tALL tARM VDDP18 DVDD33_IO tIO tIO cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.6.3 Power off Sequence

Figure 4-13 Power Off Sequence Table 4-14 Power off Timing Parameters Symbol Min (MSEC) Max (MSEC) Description tALIVE_OFF –50 Infinity ALIVE IO power to ALIVE CORE tALIVEIO_OFF 0 50 ALIVE IO power to ALIVE core power tCORE_OFF 0 Infinity VDDI to ALIVE power tARM_OFF 0 Infinity VDDI_ARM to ALIVE power tDDR_OFF 0 50 VDDQ (DDR IO power) to VDDI tIO_OFF 0 50 DVDD33_IO (normal IO power) to VDDI tALL_OFF 0 50 Other VDD power to VDDI NOTE: Other VDD: this mean all other powers like analog power. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.6.4 Software Reset and GPIO Reset

S5P4418 supports Software Reset that CPU can reset itself with Software reset. To generate Software Reset, SWRSTENB bit must be set to 1 before setting PWRMODE.SWRST bit. Software Reset mode does not need the time for stabilization clock because the software reset is requested in stable state differently from power on reset. S5P4418 supports user defined GPIO Reset. The Power management block generates reset when the AliveGPIO pad defined as GPIO Reset source is asserted or de-asserted. The AliveGPIO pad is used as GPIO Reset source are defined at Wakeup Source Register. The GPIORSTENB bit set to 1 enables the AliveGPIO Reset source feature.

4.6.5 Watchdog Reset

The Watchdog timer block is used to resume the controller operation whenever it is disturbed by malfunctions such as system error, etc. When power management block detects the event from watchdog time r, it generates exactly the same reset as power on reset because the watchdog reset event occurs in malfunctions and unknown state. 4.6.5.1 nPORST, Software Reset, Watchdog Reset and GPIO Reset S5P4418 has four reset states as below. Table 4-15 Reset State Blocks Power On Reset Watchdog Reset GPIO Reset (Software Reset) Wake Up (Idle, Stop) Clock Manager Reset Reset Reset X All Core (CPU and etc…) Reset Reset Reset X GPIO Reset Reset Reset X Power Manager (Except LASTPWRMODE Register) Reset Reset Reset X LASTPWRMODE Register Reset X X X RTC Registers (Except RTCCNTREAD Register) Reset Reset Reset X RTCCNTREAD Register X X X X nGRESETOUT (Output to PAD) Reset Reset Reset X

4.7 Tie Off

Tieoff block is a set of registers that includes special registers which don't need to be set in normal mode operation. Tieoff block includes special function registers for ARM, HDMI, DRAM controller, UART, USB2.0 HOST controller/Phy, USB2.0 OTG controller/Phy, Ethernet controller, AXI buses and the internal SRAM timing margin controls. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.8 AXI BUS

ARM PL301 (AXI3 BUS interconnect) provides programmable function for AXI BUS and which includes QoS and Programmable Round-Robin.

4.8.1 Programmable Quality of Service (ProgQoS)

The QoS scheme works by tracking the number of outstanding transactions, and when a specified number is reached, only permits transactions from particular, specified masters. The QoS scheme only provides support for slaves that have a combined acceptance capability, such as the PrimeCell Dynamic Memory Controller (PL340). The QoS scheme has no effect until the AXI bus matrix calculates that, at a particular MI, there are a number of outstanding transactions equal to the value stored in the QoS tidemark Register. It then accepts transactions only from slave ports specified in the QoS access control Register. This restriction remains until the number of outstanding transactions is again less than the value stored in the QoS tidemark Register. It is recommended that you assign low MI numbers to MIs that require QoS support. This approach aligns well with the cyclic priority scheme because MIs that require QoS support are typically those that can be considered high-ranking slaves. See the PrimeCell High-Performance Matrix (PL301) Technical Reference Manual. Below Figure shows the implementation for an interconnection that supports two masters and one slave. Figure 4-14 Example Implementation of ProgQoS Control Registers for 2×1 Interconnect cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-26 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.8.2 Arbitration scheme

You can configure each MI separately to have an arbitration scheme that is a programmable or fixed Round -robin (RR) scheme. The AW and AR channels have separate arbiters and can be programmed, if applicable, and interrogated separately through the APB programming interface, but both AW and AR channels are configured identically. Because the AW and AR channels are arbitrated separately, an MI can permit simultaneous read and write transactions from different SIs. The arbitration mechanism registers the arbitration decision for use in the subsequent cycle. An arbitration decision taken in the current cycle does not affect the current cycle. If no SIs are active, the arbiter adopts default arbitration, that is, the highest priority SI. If this occurs and then the highest priority interface becomes active in the same cycle as, or before any other SI, then this does not constitute a grant to an active SI and the arbitration scheme does not change its state as a result of that transfer. If a QoS provision is enabled and active, only a subset of SIs are permitted to win arbitration, and it cannot be guaranteed that the default arbitration is among these. In these circumstances, no transaction is permitted to use the default arbitration, and arbitration must occur when there is an active SI.

4.8.2.1 RR schemes

In these schemes, you can choose, at design time:  the number of slots that are used  the SI to which they are allocated  their order. There must be at least one slot per connected SI and there can be up to 32 slots. By allocating multiple slots for an SI, you can allocate access to the slave, on average, in proportion to the number of slots. If the slots are appropriately ordered, this can also reduce the maximum time before a grant is guaranteed. The SI associated with a slot can be interrogated from the APB programming interface and can be changed if the pr ogrammable RR scheme is chosen. Whenever arbitration is granted to an active SI, the slots are rotated so that the slot currently in the highest priority position becomes the lowest, and all other slots move to a higher priority but maintain their relative order. This means that if an SI is the highest priority active SI, but is not the highest priority interface, then it continues to win the arbitration until it becomes the highest priority interface, and then the lowest priority interface subsequently. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Because the arbitration value is registered, the arbitration decision made in this cycle is used in the next cycle. This means that if the SI that currently holds the arbitration is still the highest priority active SI in th is cycle, wins the arbitration again regardless of whether or not it is active in the next cycle as shown by the status of M3 in stages A, B, and C of below Figure 4-15. Figure 4-15 Example Operation of RR Arbitration Scheme cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-28 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9 Register Description

4.9.1 Register Map Summary

4.9.1.1 Clock/Power Manager/Boot

 Base Address: 0xC001_0000 Register Offset Description Reset Value CLKMODEREG0 0000h Clock Mode Register 0 0x0000_0000 CLKMODEREG1 0004h CLOCK MODE REGISTER1 0x0000_0000 PLLSETREG0 0008h PLL0 SETTING REGISTER 0x101A_2602 PLLSETREG1 000Ch PLL1 SETTING REGISTER 0x101A_4E04 PLLSETREG2 0010h PLL2 SETTING REGISTER 0x100C_C004 PLLSETREG3 0014h PLL3 SETTING REGISTER 0x100C_0FA4 RSVD 0018h to 001Fh Reserved 0x0000_0000 CLKDIVREG0 0020h FCLKCPU0 SETTING REGISTER 0x0000_8208 CLKDIVREG1 0024h BCLK SETTING REGISTER 0x0000_8208 CLKDIVREG2 0028h CLKDIVREG2 0x0020_8000 CLKDIVREG3 002Ch GR3DBCLK SETTING REGISTER 0x0000_8208 CLKDIVREG4 0030h MPEGBCLK SETTING REGISTER 0x0000_8208 RSVD 0034h to 003Fh Reserved 0x0000_0000 0040h to 0047h 0x0000_0000 PLLSETREG0_SSCG 0048h PLL0 SETTING REGISTER FOR SPREAD SPECTRUM 0x0000_0000 PLLSETREG1_SSCG 004Ch PLL1 SETTING REGISTER FOR SPREAD SPECTRUM 0x0000_0000 PLLSETREG2_SSCG 0050h PLL2 SETTING REGISTER FOR SPREAD SPECTRUM 0x0000_0000 PLLSETREG3_SSCG 0054h PLL3 SETTING REGISTER FOR SPREAD SPECTRUM 0x0000_0000 GPIOWAKEUPRISEENB 0200h RISING EDGE DETECT ENABLE REGISTER 0x0000_0003 GPIOWAKEUPFALLENB 0204h FALLING EDGE DETECT ENABLE REGISTER 0x0000_0003 GPIORSTENB 0208h GPIO RESET ENABLE REGISTER 0x0000_0003 GPIOWKENB 020Ch GPIO WAKEUP ENABLE REGISTER 0x0000_0003 INTENB 0210h GPIO INTERRUPT ENABLE REGISTER 0x0000_0003 GPIOINTPEND 0214h GPIO INTERRUPT PENDING REGISTER 0x0000_0000 RESETSTATUS 0218h RESET STATUS REGISTER 0x0000_0001 INTENABLE 021Ch INTERRUPT ENABLE REGISTER 0x0000_0000 INTPEND 0220h INTERRUPT PENDING REGISTER 0x0000_0000 PWRCONT 0224h POWER MANGEMENT CONTROL REGISTER 0x0000_FF00 PWRMODE 0228h POWER MANGEMENT MODE REGISTER 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-29 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value RSVD 022Ch Reserved 0x0000_0000 PADSTRENGTHGPIOAL 0230h to 0238h SCRATCH REGISTER 0x0000_0000 SYSRSTCONFIG 023Ch SYSTEM RESET COFIGURATION REGISTER 0x0000_0000 RSVD 0240h to 03FFh Reserved 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-30 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.1 CLKMODEREG0

 Base Address: 0xC001_0000  Address = Base Address + 0000h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value WAIT_UPDATE_PLL [31] RW Wait flag updating-PLL for several RTC (32768 Hz) clocks 1 = In-process 0 = Done 1'b0 RSVD [30:4] – reserved 1'b0 UPDATE_PLL[3] [3] RW Update P,M,S values for PLL[3] 1 = Update 0 = None 1'b0 UPDATE_PLL[2] [2] RW Update P,M,S values for PLL[2] 1 = Update 0 = None 1'b0 UPDATE_PLL[1] [1] RW Update P,M,S values for PLL[1] 1 = Update 0 = None 1'b0 UPDATE_PLL[0] [0] RW Update P,M,S values for PLL[0] 1 = Update 0 = None 1'b0 NOTE: The PMS values of PLL[n] is applied when UPDATE_PLL[n] is set to \`1'.

4.9.1.1.2 CLKMODEREG1

 Base Address: 0xC001_0000  Address = Base Address + 0004h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:0] – Reserved 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-31 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.3 PLLSETREG0

 Base Address: 0xC001_0000  Address = Base Address + 0008h, Reset Value = 0x101A_2602 Name Bit Type Description Reset Value RSVD [31] – Reserved 1'b0 SSCG_EN [30] RW PLL spread spectrum enable. This register is ignored for non-dithered PLL 1 = Enable 0 = Disable 1'b0 PD [29] RW PLL Power down 1 = Power down 0 = Power on. 1'b0 nPLLBYPASS [28] RW This register bypass PLL outputs. 1 = Normal PLL output 0 = X-tal clock (PLL input) is selected as PLL output. 1'b1 PLLOUTDIV [27:24] RW PLL output for peripheral is divided by this register. PLL output for system clock is not affected by this register. 0 = Divide by one 1 = Divide by two N-1 = divide by N 4'b0 PDIV [23:18] RW Pre Divider Value. Divider initially dividing 12 MHz to make PLL0 1 ≤ PDIV ≤ 63 6'd6 MDIV [17:8] RW Main Divider Value. If the value of Fvco is not a desired clock, the value is divided into MDIV again after feedback. (This loop is continuously circulated until a desired clock frequency is made.) 64≤ MDIV ≤ 1023 10'd550 SDIV [7:0] RW Post Scale Divider. Divide the value of Fvco by SDIV to obtain the desired PLL0 value finally. 0 ≤ SDIV ≤ 5 8'd2 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-32 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.4 PLLSETREG1

 Base Address: 0xC001_0000  Address = Base Address + 000Ch, Reset Value = 0x101A_4E04 Name Bit Type Description Reset Value RSVD [31] – Reserved 1'b0 SSCG_EN [30] RW PLL spread spectrum enable. This register is ignored for non-dithered PLL 0 = Disable 1 = Enable 1'b0 PD [29] RW PLL Power down 0 = Power on 1 = Power down 1'b0 nPLLBYPASS [28] RW This register bypass PLL outputs. 0 = X-tal clock (PLL input) is selected as PLL output 1 = Normal PLL output 1'b1 PLLOUTDIV [27:24] RW PLL output for peripheral is divided by this register. PLL output for system clock is not affected by this register. 0 = Divide by one 1 = Divide by two N-1 = Divide by N 4'b0 PDIV [23:18] RW Pre Divider Value. Divider initially dividing 12 MHz to make PLL0 1 ≤ PDIV ≤ 63 6'd6 MDIV [17:8] RW Main Divider Value. If the value of Fvco is not a desired clock, the value is divided into MDIV again after feedback. (This loop is continuously circulated until a desired clock frequency is made.) 64≤ MDIV ≤ 1023 10'd590 SDIV [7:0] RW Post Scale Divider. Divide the value of Fvco by SDIV to obtain the desired PLL0 value finally. 0 ≤ SDIV ≤ 5 8'd4 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-33 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.5 PLLSETREG2

 Base Address: 0xC001_0000  Address = Base Address + 0010h, Reset Value = 0x100C_C004 Name Bit Type Description Reset Value RSVD [31] – Reserved 1'b0 SSCG_EN [30] RW PLL spread spectrum enable. This register is ignored for non-dithered PLL 0 = Disable 1 = Enable 1'b0 PD [29] RW PLL Power down 0 = Power on 1 = Power down 1'b0 nPLLBYPASS [28] RW This register bypass PLL outputs. 0 = X-tal clock (PLL input) is selected as PLL output 1 = Normal PLL output 1'b1 PLLOUTDIV [27:24] RW PLL output for peripheral is divided by this register. PLL output for system clock is not affected by this register. 0 = Divide by one 1 = Divide by two N-1 = Divide by N 4'b0 PDIV [23:18] RW Pre Divider Value. Divider initially dividing 12 MHz to make PLL0 1 ≤ PDIV ≤ 63 6'd3 MDIV [17:8] RW Main Divider Value. If the value of Fvco is not a desired clock, the value is divided into MDIV again after feedback. (This loop is continuously circulated until a desired clock frequency is made.) 64 ≤ MDIV ≤ 1023 10'd192 SDIV [7:0] RW Post Scale Divider. Divide the value of Fvco by SDIV to obtain the desired PLL0 value finally. 0 ≤ SDIV ≤ 5 8'd4 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-34 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.6 PLLSETREG3

 Base Address: 0xC001_0000  Address = Base Address + 0014h, Reset Value = 0x100C_0FA4 Name Bit Type Description Reset Value RSVD [31] – Reserved 1'b0 SSCG_EN [30] RW PLL spread spectrum enable. This register is ignored for non-dithered PLL 0 = Disable 1 = Enable 1'b0 PD [29] RW PLL Power down 0 = Power on 1 = Power down 1'b0 nPLLBYPASS [28] RW This register bypass PLL outputs. 0 = X-tal clock (PLL input) is selected as PLL output 1 = Normal PLL output 1'b1 PLLOUTDIV [27:24] RW PLL output for peripheral is divided by this register. PLL output for system clock is not affected by this register. 0 = Divide by one 1 = Divide by two N-1 = Divide by N 4'b0 PDIV [23:18] RW Pre Divider Value. Divider initially dividing 12 MHz to make PLL0 1 ≤ PDIV ≤ 63 6'd3 MDIV [17:8] RW Main Divider Value. If the value of Fvco is not a desired clock, the value is divided into MDIV again after feedback. (This loop is continuously circulated until a desired clock frequency is made.) 64≤ MDIV ≤ 1023 10'd250 SDIV [7:0] RW Post Scale Divider. Divide the value of Fvco by SDIV to obtain the desired PLL0 value finally. 0 ≤ SDIV ≤ 5 8'd4 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-35 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.7 CLKDIVREG0

 Base Address: 0xC001_0000  Address = Base Address + 0020h, Reset Value = 0x0000_8208 Name Bit Type Description Reset Value RSVD [31:27] RW Reserved 4'b0 RSVD [26:21] RW Reserved 6'b0 RSVD [20:15] RW Reserved 6'b1 CLKDIV_HCLKCPU0 [14:9] RW Divide value to create the clock of HCLKCPU0. For "N" clock divide, enter an [N-1] value. Register Set value 000001 to 111111  actual Divide Value = 2 to 64 Ex) For eight clock divide, set this register to 000111b Ex) For three clock divide, set this register to 000010b 6'b1 CLKDIV_FCLKCPU0 [8:3] RW Divide value to create the clock of FCLKCPU0. For "N" clock divide, enter an [N-1] value. Register Set value 000001 to 111111  actual Divide Value = 2 to 64 Ex) For eight clock divide, set this register to 000111b For three clock divide, set this register to 000010b 6'b1 CLKSEL_FCLKCPU0 [2:0] RW Select a clock source. If this bits is N, then PLL[N] is selected as clock source. 3'b0

4.9.1.1.8 CLKDIVREG1

 Base Address: 0xC001_0000  Address = Base Address + 0024h, Reset Value = 0x0000_8208 Name Bit Type Description Reset Value RSVD [31:27] RW Reserved 4'b0 RSVD [26:21] RW Reserved 6'b0 RSVD [20:15] RW Reserved 6'b1 CLKDIV_PCLK [14:9] RW Divide value to create the clock of PCLK. For "N" clock divide, enter an [N-1] value. Register Set value 000001 to 111111  actual Divide Value = 2 to 64 Ex) For eight clock divide, set this register to 000111b For three clock divide, set this register to 000010b 6'b1 CLKDIV_BCLK [8:3] RW Divide value to create the clock of BCLK. For "N" clock divide, enter an [N-1] value. Register Set value 000001 to 111111  actual Divide Value = 2 to 64 Ex) For eight clock divide, set this register to 000111b 6'b1 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-36 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Ex) For three clock divide, set this register to 000010b CLKSEL_BCLK [2:0] RW Select a clock source. If this bits is N, then PLL[N] is selected as clock source. 3'b0

4.9.1.1.9 CLKDIVREG2

 Base Address: 0xC001_0000  Address = Base Address + 0028h, Reset Value = 0x0020_8000 Name Bit Type Description Reset Value RSVD [31:27] RW Reserved 4'b0 CLKDIV_MPCLK [26:21] RW Divide value to create the clock of MPCLK. For "N" clock divide, enter an [N-1] value. Register Set value 000001 to 111111  actual Divide Value = 2 to 64 Ex) For eight clock divide, set this register to 000111b For three clock divide, set this register to 000010b 6'b1 CLKDIV_MBCLK [20:15] RW Divide value to create the clock of MBCLK. For "N" clock divide, enter an [N-1] value. Register Set value 000001 to 111111  actual Divide Value = 2 to 64 Ex) For eight clock divide, set this register to 000111b For three clock divide, set this register to 000010b 6'b1 CLKDIV_MCLK [14:9] RW Divide value to create the clock of MCLK. For "N" clock divide, enter an [N-1] value. Register Set value 000001 to 111111  actual Divide Value = 2 to 64 Ex) For eight clock divide, set this register to 000111b For three clock divide, set this register to 000010b 6'b0 CLKDIV_MDCLK [8:3] RW Divide value to create the clock of MDCLK. For "N" clock divide, enter an [N-1] value. Register Set value 000001 to 111111  actual Divide Value = 2 to 64 Ex) For eight clock divide, set this register to 000111b For three clock divide, set this register to 000010b 6'b0 CLKSEL_MDCLK [2:0] RW Select a clock source. If this bits is N, then PLL[N] is selected as clock source. 3'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-37 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.10 CLKDIVREG3

 Base Address: 0xC001_0000  Address = Base Address + 002Ch, Reset Value = 0x0000_8208 Name Bit Type Description Reset Value RSVD [31:27] RW Reserved 4'b0 RSVD [26:21] RW Reserved 6'b0 RSVD [20:15] RW Reserved 6'b1 CLKDIV_GR3DPCLK [14:9] RW Divide value to create the clock of GR3DPCLK. For "N"' clock divide, enter an [N-1] value. Register Set value 000001 to 111111  actual Divide Value = 2 to 64 Ex) For eight clock divide, set this register to 000111b For three clock divide, set this register to 000010b 6'b1 CLKDIV_GR3DBCLK [8:3] RW Divide value to create the clock of GR3DBCLK. For "N" clock divide, enter an [N-1] value. Register Set value 000001 to 111111  actual Divide Value = 2 to 64 Ex) For eight clock divide, set this register to 000111b For three clock divide, set this register to 000010b 6'b1 CLKSEL_GR3DBCLK [2:0] RW Select a clock source. If this bits is N, then PLL[N] is selected as clock source. 3'b0

4.9.1.1.11 CLKDIVREG4

 Base Address: 0xC001_0000  Address = Base Address + 0030h, Reset Value = 0x0000_8208 Name Bit Type Description Reset Value RSVD [31:27] RW Reserved 4'b0 RSVD [26:21] RW Reserved 6'b0 RSVD [20:15] RW Reserved 6'b1 CLKDIV_MPEGPCLK [14:9] RW Divide value to create the clock of HC MPEGPCLK. For "N" clock divide, enter an [N-1] value. Register Set value 000001 to 111111  actual Divide Value = 2 to 64 Ex) For eight clock divide, set this register to 000111b For three clock divide, set this register to 000010b 6'b1 CLKDIV_MPEGBCLK [8:3] RW Divide value to create the clock of MPEGBCLK. For "N" clock divide, enter an [N-1] value. Register Set value 000001 to 111111  actual Divide Value = 2 to 64 Ex) For eight clock divide, set this register to 000111b For three clock divide, set this register to 000010b 6'b1 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-38 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value CLKSEL_MPEGBCLK [2:0] RW Select a clock source. If this bits is N, then PLL[N] is selected as clock source. 3'b0

4.9.1.1.12 PLLSETREG0_SSCG

 Base Address: 0xC001_0000  Address = Base Address + 0048h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value K [31: 16] RW Value of 16-bit DSM. 16'b0 MFR [15:8] RW Modulation frequency control 8'b0 MRR [7:2] RW Modulation rate control 6'b0 SEL_PF [1:0] RW Modulation method 00 = Down spread 01 = Up spread 1x = Center spread 2'b0 NOTE: This register is applied only for dithered-type PLL.

4.9.1.1.13 PLLSETREG1_SSCG

 Base Address: 0xC001_0000  Address = Base Address + 004Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value K [31: 16] RW Value of 16-bit DSM. 16'b0 MFR [15:8] RW Modulation frequency control 8'b0 MRR [7:2] RW Modulation rate control 6'b0 SEL_PF [1:0] RW Modulation method 00 = Down spread 01 = Up spread 1x = Center spread 2'b0 NOTE: This register is applied only for dithered-type PLL. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-39 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.14 PLLSETREG2_SSCG

 Base Address: 0xC001_0000  Address = Base Address + 0050h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value K [31: 16] RW Value of 16-bit DSM. 16'b0 MFR [15:8] RW Modulation frequency control 8'b0 MRR [7:2] RW Modulation rate control 6'b0 SEL_PF [1:0] RW Modulation method 00 = Down spread 01 = Up spread 1x = Center spread 2'b0 NOTE: This register is applied only for dithered-type PLL.

4.9.1.1.15 PLLSETREG3_SSCG

 Base Address: 0xC001_0000  Address = Base Address + 0054h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value K [31: 16] RW Value of 16-bit DSM. 16'b0 MFR [15:8] RW Modulation frequency control 8'b0 MRR [7:2] RW Modulation rate control 6'b0 SEL_PF [1:0] RW Modulation method 00 = Down spread 01 = Up spread 1x = Center spread 2'b0 NOTE: This register is applied only for dithered-type PLL. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-40 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.16 GPIOWAKEUPRISEENB

 Base Address: 0xC001_0000  Address = Base Address + 0200h, Reset Value = 0x0000_0003 Name Bit Type Description Reset Value RSVD [31: 15] – Reserved 17'b0 RISEWKSRC14 [14] RW Wakeup source (USB20OTG.SUSPEND) Rising Edge Detect Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 RISEWKSRC13 [13] RW Wakeup source (USB20OTG.SLEEP) Rising Edge Detect Enable This bit enables wakeup form power down modes, when USB2.0 OTG's Sleep pin toggles. 0 = Disable 1 = Enable 1'b0 RISEWKSRC12 [12] RW Reserved. This bit must be set to "1'b0" 1'b0 RISEWKSRC11 [11] RW Reserved. This bit must be set to "1'b0" 1'b0 RISEWKSRC10 [10] RW Wakeup source (UART[3].RX) Rising Edge Detect Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 RISEWKSRC9 [9] RW Wakeup source (UART[2].RX) Rising Edge Detect Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 RISEWKSRC8 [8] RW Wakeup source (UART[1].RX) Rising Edge Detect Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 RISEWKSRC7 [7] RW Wakeup source (UART[0].RX) Rising Edge Detect Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-41 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value RISEWKSRC6 [6] RW Wakeup source (VDDPWRTOGGLE) Rising Edge Detect Enable This bit enables wakeup form power down modes, when user pushed VDDPWRTOGGLE PAD. 0 = Disable 1 = Enable 1'b0 RISEWKSRC5 [5] RW Wakeup Source (ALIVEGPIO5) Rising Edge Detect Enable 0 = Disable 1 = Enable 1'b 0 RISEWKSRC4 [4] RW Wakeup Source (ALIVEGPIO4) Rising Edge Detect Enable 0 = Disable 1 = Enable 1'b 0 RISEWKSRC3 [3] RW Wakeup Source (ALIVEGPIO3) Rising Edge Detect Enable 0 = Disable 1 = Enable 1'b 0 RISEWKSRC2 [2] RW Wakeup Source (ALIVEGPIO2) Rising Edge Detect Enable 0 = Disable 1 = Enable 1'b 0 RISEWKSRC1 [1] RW Wakeup Source (ALIVEGPIO1) Rising Edge Detect Enable 0 = Disable 1 = Enable 1'b 1 RISEWKSRC0 [0] RW Wakeup Source (ALIVEGPIO0) Rising Edge Detect Enable 0 = Disable 1 = Enable 1'b 1 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-42 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.17 GPIOWAKEUPFALLENB

 Base Address: 0xC001_0000  Address = Base Address + 0204h, Reset Value = 0x0000_0003 Name Bit Type Description Reset Value RSVD [31 :15] – Reserved 17'b0 FALLWKSRC14 [14] RW Wakeup source (USB20OTG.SUSPEND)Falling Edge Detect Enable This bit enables wakeup form power down modes, when UART RX pin pin toggles. 0 = Disable 1 = Enable 1'b0 FALLWKSRC13 [13] RW Wakeup source (USB20OTG.SLEEP)Falling Edge Detect Enable This bit enables wakeup form power down modes, when USB2.0 OTG's Sleep pin toggles. 0 = Disable 1 = Enable 1'b0 FALLWKSRC12 [12] RW Reserved. This bit must be set to \1'b0' 1'b0 FALLWKSRC11 [11] RW Reserved. This bit must be set to \1'b0' 1'b0 FALLWKSRC10 [10] R/W Wakeup source (UART[3].RX)Falling Edge Detect Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 FALLWKSRC9 [9] R/W Wakeup source (UART[2].RX)Falling Edge Detect Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 FALLWKSRC8 [8] R/W Wakeup source (UART[1].RX)Falling Edge Detect Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 FALLWKSRC7 [7] R/W Wakeup source (UART[0].RX)Falling Edge Detect Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-43 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value FALLWKSRC6 [6] RW Wakeup source (VDDPWRTOGGLE) Falling Edge Detect Enable 0 = Disable 1 = Enable 1'b0 FALLWKSRC5 [5] RW Wakeup Source (ALIVEGPIO5) Falling Edge Detect Enable 0 = Disable 1 = Enable 1'b 0 FALLWKSRC4 [4] RW Wakeup Source (ALIVEGPIO4) Falling Edge Detect Enable 0 = Disable 1 = Enable 1'b 0 FALLWKSRC3 [3] RW Wakeup Source (ALIVEGPIO3) Falling Edge Detect Enable 0 = Disable 1 = Enable 1'b 0 FALLWKSRC2 [2] RW Wakeup Source (ALIVEGPIO2) Falling Edge Detect Enable 0 = Disable 1 = Enable 1'b 0 FALLWKSRC1 [1] RW Wakeup Source (ALIVEGPIO1) Falling Edge Detect Enable 0 = Disable 1 = Enable 1'b 1 FALLWKSRC0 [0] RW Wakeup Source (ALIVEGPIO0) Falling Edge Detect Enable 0 = Disable 1 = Enable 1'b 1 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-44 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.18 GPIORSTENB

 Base Address: 0xC001_0000  Address = Base Address + 0208h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31: 15] RW Reserved (These bits should always be "0") 17'b0 RSVD [14:6] RW Reserved (These bits should always be "0") 1'b0 GPIO5RSTENB [5] RW ALIVEGPIO5 Reset Source Enable 0 = Disable 1 = Enable 1'b0 GPIO4RSTENB [4] RW ALIVEGPIO4 Reset Source Enable 0 = Disable 1 = Enable 1'b0 GPIO3RSTENB [3] RW ALIVEGPIO3 Reset Source Enable 0 = Disable 1 = Enable 1'b0 GPIO2RSTENB [2] RW ALIVEGPIO2 Reset Source Enable 0 = Disable 1 = Enable 1'b0 GPIO1RSTENB [1] RW ALIVEGPIO1 Reset Source Enable 0 = Disable 1 = Enable 1'b0 GPIO0RSTENB [0] RW ALIVEGPIO0 Reset Source Enable 0 = Disable 1 = Enable 1'b0 NOTE: Wake-up and Reset Enable are not allowed at the same time for the same ALIVEGPIO. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-45 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.19 GPIOWKENB

 Base Address: 0xC001_0000  Address = Base Address + 020Ch, Reset Value = 0x0000_0003 Name Bit Type Description Reset Value RSVD [31: 15] RW Reserved 17'b0 GPIO14WKENB [14] RW Wakeup source (USB20OTG.SUSPEND) Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO13WKENB [13] RW Wakeup source (USB20OTG.SLEEP) Enable This bit enables wakeup form power down modes, when USB2.0 OTG's Sleep pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO12WKENB [12] RW Reserved. This bit must be set to "1'b0" 1'b0 GPIO11WKENB [11] RW Reserved. This bit must be set to "1'b0" 1'b0 GPIO10WKENB [10] RW Wakeup source (UART[3].RX) Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO9WKENB [9] RW Wakeup source (UART[2].RX) Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO8WKENB [8] RW Wakeup source (UART[1].RX) Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO7WKENB [7] RW Wakeup source (UART[0].RX) Enable This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 VDDTOGGLEWKENB [6] RW VDDPWRTOGGLE Wakeup Source Enable 0 = Disable 1 = Enable 1'b0 GPIO5WKENB [5] RW ALIVEGPIO5 Wakeup Source Enable 0 = Disable 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-46 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 1 = Enable GPIO4WKENB [4] RW ALIVEGPIO4 Wakeup Source Enable 0 = Disable 1 = Enable 1'b0 GPIO3WKENB [3] RW ALIVEGPIO3 Wakeup Source Enable 0 = Disable 1 = Enable 1'b0 GPIO2WKENB [2] RW ALIVEGPIO2 Wakeup Source Enable 0 = Disable 1 = Enable 1'b0 GPIO1WKENB [1] RW ALIVEGPIO1 Wakeup Source Enable 0 = Disable 1 = Enable 1'b1 GPIO0WKENB [0] RW ALIVEGPIO0 Wakeup Source Enable 0 = Disable 1 = Enable 1'b1 NOTE: Wake-up and Reset Enable are not allowed at the same time for the same ALIVEGPIO.

4.9.1.1.20 INTENB

 Base Address: 0xC001_0000  Address = Base Address + 0210h, Reset Value = 0x0000_0003 Name Bit Type Description Reset Value RSVD [31: 15] – Reserved 17'b0 GPIO14 [14] RW Wakeup source (USB20OTG.SUSPEND) Event Interrupt Enable This bit enables wakeup form power down modes, when UART RX pin pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO13 [13] RW Wakeup source (USB20OTG.SLEEP) Event Interrupt Enable This bit enables wakeup form power down modes, when USB2.0 OTG's Sleep pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO12 [12] RW Reserved. This bit must be set to "1'b0" 1'b0 GPIO11 [11] RW Reserved. This bit must be set to "1'b0" 1'b0 GPIO10 [10] RW Wakeup source (UART[3].RX) Event Interrupt Enable This bit enables wakeup form power down modes, 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-47 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value when UART RX pin pin toggles. 0 = Disable 1 = Enable GPIO9 [9] RW Wakeup source (UART[2].RX) Event Interrupt Enable This bit enables wakeup form power down modes, when UART RX pin pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO8 [8] RW Wakeup source (UART[1].RX) Event Interrupt Enable This bit enables wakeup form power down modes, when UART RX pin pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO7 [7] RW Wakeup source (UART[0].RX) Event Interrupt Enable This bit enables wakeup form power down modes, when UART RX pin pin toggles. 0 = Disable 1 = Enable 1'b0 vddtoggle [6] RW VDDPWRTOGGLE Event Interrupt Enable 0 = Disable 1 = Enable 1'b0 GPIO5 [5] RW ALIVEGPIO5 Event Interrupt Enable 0 = Disable 1 = Enable 1'b0 GPIO4 [4] RW ALIVEGPIO4 Event Interrupt Enable 0 = Disable 1 = Enable 1'b0 GPIO3 [3] RW ALIVEGPIO3 Event Interrupt Enable 0 = Disable 1 = Enable 1'b0 GPIO2 [2] RW ALIVEGPIO2 Event Interrupt Enable 0 = Disable 1 = Enable 1'b0 GPIO1 [1] RW ALIVEGPIO1 Event Interrupt Enable 0 = Disable 1 = Enable 1'b1 GPIO0 [0] RW ALIVEGPIO0 Event Interrupt Enable 0 = Disable 1 = Enable 1'b1 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-48 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.21 GPIOINTPEND

 Base Address: 0xC001_0000  Address = Base Address + 0214h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:15] R Reserved 17'b0 GPIO14PEND [14] RW This bit is set as "1" when (USB20OTG. SUSPEND) Event occurs. And this bit is cleared by setting as "1" This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO13PEND [13] RW This bit is set as "1" when (USB20OTG.SLEEP) Event occurs. And this bit is cleared by setting as "1" This bit enables wakeup form power down modes, when USB2.0 OTG's Sleep pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO12PEND [12] RW Reserved. This bit must be set to "1'b0" 1'b0 GPIO11PEND [11] RW Reserved. This bit must be set to "1'b0" 1'b0 GPIO10PEND [10] RW This bit is set as "1" when (UART[3].RX) Event occurs. And this bit is cleared by setting as "1" This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO9PEND [9] RW This bit is set as "1" when (UART[2].RX) Event occurs. And this bit is cleared by setting as "1" This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO8PEND [8] RW This bit is set as "1" when (UART[1].RX) Event occurs. And this bit is cleared by setting as "1" This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 GPIO7PEND [7] RW This bit is set as "1" when (UART[0].RX) Event occurs. And this bit is cleared by setting as "1" This bit enables wakeup form power down modes, when UART RX pin toggles. 0 = Disable 1 = Enable 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-49 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value VDDTOGGLEPEND [6] RW This bit is set as "1" when VDDPWRTOGGLE Event occurs. And this bit is cleared by setting as "1" Read 0 = None 1 = Interrupt Pended Write 0 = Not Clear 1 = Clear 1'b0 GPIO5PEND [5] RW This bit is set as "1" when ALIVEGPIO5 Event occurs. And this bit is cleared by setting as "1" Read 0 = None 1 = Interrupt Pended Write 0 = Not Clear 1 = Clear 1'b0 GPIO4PEND [4] RW This bit is set as "1" when ALIVEGPIO4 Event occurs. And this bit is cleared by setting as "1" Read 0 = None 1 = Interrupt Pended Write 0 = Not Clear 1 = Clear 1'b0 GPIO3PEND [3] RW This bit is set as "1" when ALIVEGPIO3 Event occurs. And this bit is cleared by setting as "1" Read 0 = None 1 = Interrupt Pended Write 0 = Not Clear 1 = Clear 1'b0 GPIO2PEND [2] RW This bit is set as "1" when ALIVEGPIO2 Event occurs. And this bit is cleared by setting as "1" Read 0 = None 1 = Interrupt Pended Write 0 = Not Clear 1 = Clear 1'b0 GPIO1PEND [1] RW This bit is set as "1" when ALIVEGPIO1 Event occurs. And this bit is cleared by setting as "1" Read 0 = None 1 = Interrupt Pended Write 0 = Not Clear 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-50 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 1 = Clear GPIO0PEND [0] RW This bit is set as "1" when ALIVEGPIO0 Event occurs. And this bit is cleared by setting as "1" Read 0 = None 1 = Interrupt Pended Write 0 = Not Clear 1 = Clear 1'b0

4.9.1.1.22 RESETSTATUS

 Base Address: 0xC001_0000  Address = Base Address + 0218h, Reset Value = 0x0000_0001 Name Bit Type Description Reset Value RSVD [31: 4] – Reserved 28'b0 SOFTWARERESET [3] R Software Reset Status. This bit is cleared when other Reset occurs 0 = No Effect 1 = Software Reset 1'b0 WATCHDOGRESET [2] R Watchdog Reset Status. This bit is cleared when other Reset occurs 0 = No Effect 1 = Watchdog Reset 1'b0 GPIORESET [1] R GPIO Reset Status. This bit is cleared when other Reset occurs 0 = No Effect 1 = GPIO Reset 1'b0 POR [0] R Power On Reset Status. This bit is cleared when other Reset occurs 0 = No Effect 1 = Power On Reset 1'b1 NOTE: The priority of Reset - POR > GPIO > Watchdog > Software cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-51 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.23 INTENABLE

 Base Address: 0xC001_0000  Address = Base Address + 021Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31: 2] – Reserved 30'b0 BATF [1] RW BATF(Battery Fault) Event Interrupt Enable Interrupt occurs when BATF is low level. 0 = Disable 1 = Enable 1'b0 RTC [0] RW RTC Event Interrupt Enable Interrupt occurs when BATF is low level. 0 = Disable 1 = Enable 1'b0

4.9.1.1.24 INTPEND

 Base Address: 0xC001_0000  Address = Base Address + 0220h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31: 2] R- Reserved 30'b0 BATFWAKEUP [1] RW This bit is set as "1" when BATF (Battery Fault) Event occurs. And this bit is cleared by setting as "1" Read 0 = None 1 = Interrupt Pended Write 0 = Not Clear 1 = Clear 1'b0 RTCWAKEUP [0] RW This bit is set as "1" when RTC Wakeup Event occurs. And this bit is cleared by setting as "1" Read 0 = None 1 = Interrupt Pended Write 0 = Not Clear 1 = Clear 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-52 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.1.25 PWRCONT

 Base Address: 0xC001_0000  Address = Base Address + 0224h, Reset Value = 0x0000_FF00 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 USE_WFI [15:12] RW Use STANDBYWFI[n] signal as indicating signal to go into stop mode. 4'b1111 USE_WFE [11:8] RW Use STANDBYWFE[n] signal as indicating signal to go into stop mode. 4'b1111 XTAL_PWRDN [4] RW Xrystal power down mode selection This controls the power down of Xrystal-PAD in stop- mode. 0 = XTAL is powered down instop mode 1 = XTAL is not powered down in stop mode 1'b0 SWRSTENB [3] RW Software Reset Enable. 0 = Disable 1 = Enable 1'b0 RESERVED [2] RW Reserved (This bit always should be "0") 1'b0 RTCWKENB [1] RW RTC Wake-up enable 0 = Disable 1 = Enable 1'b0 RESERVED [0] RW Reserved (This bit always should be "0") 1'b0

4.9.1.1.26 PWRMODE

 Base Address: 0xC001_0000  Address = Base Address + 0228h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Reserved 16'b0 chgpll [15] RW Change PLL Value with new value defined in PLL Setting Register (PLL0set, PLL1set) in clock Controller. Read 0 = Stable 1 = PLL is Unstable Write 0 = None 1 = PLL Value Change 1'b0 RSVD [14:13] Reserved 2'b0 swrst [12] W This bit is cleared after Software Reset 0 = Do Not Reset 1 = Go to Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-53 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value RSVD [11:6] R Reserved 6'b0 LASTPWRSTOP [5] R Indicates that the chip has been in STOP Mode before in Normal state.(This bit is cleared in case of Reset in Normal state) 0 = None 1 = Stop mode 1'b0 LASTPWRIDLE [4] R Indicates that the chip has been in STOP Mode before in Normal state.(This bit is cleared in case of Reset in Normal state) 0 = None 1 = Idle mode 1'b0 RSVD [3] RW Reserved 1'b0 RSVD [2] RW Reserved (This bit always should be \`0') 1'b0 STOP [1] RW Set New Power Mode STOP. The chip wakes up to be in Normal mode when RTC, GPIO occurs in STOP mode, and this bit is cleared. Read 0 = Normal 1 = Stop mode Write 0 = None 1 = go to stop mode 1'b0 IDLE [0] RW Set New Power Mode IDLE. The chip wakes up to be in Normal mode when RTC, GPIO, Watchdog reset, and CPU interrupt occurs in STOP mode, and this bit is cleared. Read 0 = Normal 1 = Idle mode Write 0 = None 1 = go to Idle mode 1'b0

4.9.1.1.27 PADSTRENGTHGPIOAL

 Base Address : 0xC001_0000  Address = Base Address + 0230h, 0234h, 0238h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value SCRATCH [31:0] RW Register is initialized only in case of CORE Power On Reset. (size: 8 byte) 0x0000_0000

4.9.1.1.28 SYSRSTCONFIG

 Base Address : 0xC001_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-54 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  Address = Base Address + 023Ch, Reset Value = Undefined Name Bit Type Description Reset Value SCRATCH [31:22] R Reserved - CfgICACHE [21] R Indicates L1 Cache enable when (CfgBootMode ! = 4'hF) In the case of internal rom boot, use this register for CPU Instruction cache enable 0 = Disable

1 Enable

VID1_5 CfgDecrypt [20] R Indicates AES ECB mode decrypt when (CfgBootMode ! = 4'hF) 0 = Not decrypt 1 = Decrypt VID1_4 RSVD [19] R Reserved VID1_3 CfgNANDPage [18] R Indicates External nand page size when (CfgBootMode == 4'h7). 0 = 2K or below 1 = 4K or above VID1_2 CfgNANDType [17:16] R Indicates External nand type when (CfgBootMode == 4'hF). 0 = Small Block 3 Address 1 = Small block 4 Address 2 = Large 4 Address 3 = Large 5 Address 2'b{VID1_1, VID1_0} CfgBootMode [15:12] R System boot mode. 4'bx000: Nor boot 4'bx011: Internal ROM UART boot 4'bx100: Internal ROM Serial flash boot 4'bx101: Internal ROM SD boot 4'bx110: Internal ROM USB boot 4'b0111: Internal ROM NAND boot 4'b1111: Internal ROM NANDEX boot 4'b{ DISD7, DISD6, DISD5, DISD4} CfgSTBUSWIDTH [11] R Static Memory BUS bit. Internal ROM boot fixed 0. 0 = 8-bit 1 = 16-bit DISD3 CfgAlternative [10] R Indicates eMMC Alternative Boot mode when (CfgBootMode == 4'bx101). 0 = Alternative Boot 1 = Normal Boot Indicates [1] bit of Serial flash memory address when (CfgBootMode == 4'bx100). Indicates UART Baudrate when (CfgBootMode == 4'bx011) 0 = 19200 bps 1 = 115200 bps Indicates Serial flash memory address width when DISD2 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-55 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value (CfgBootMode == 4'bx100). (CfgAlternative, CfgPARTITION) == 2'b00:16-bit address (CfgAlternative, CfgPARTITION) == 2'b01:24-bit address (CfgAlternative, CfgPARTITION) == 2'b10:25-bit address CfgPARTITION [9] R Indicates Boot Partition on eMMC when (CfgBootMode == 4'bx101) 0 = Default Partition 1 = Boot Partition (Partition#1) Used for [0] bit of Serial flash memory address when (CfgBootMode == 4'bx100). DISD1 CfgLATADDR [8] R Static Memory Latched Address. 0 = None 1 = Latched DISD0 CfgeMMCBootMode [7] R Indicates eMMC Boot mode when (CfgBootMode == 4'bx101). 0 = Normal SD Boot 1 = eMMC Boot SD7 CfgOTGSessionCheck [6] R Indicates USB OTG Session Check when (CfgBootMode == 4'bx110). 0 = not check 1 = check SD6 CfgICACHE [5] R Indicates L1 Cache enable when (CfgBootMode ! = F). Used for CPU Instruction cache enable in the case of internal rom boot. 0 = Disable 1 = Enable SD5 CfgDecrypt [4] R Indicates AES ECB mode decrypt when (CfgBootMode ! = F) 0 = Not decrypt 1 = Decrypt SD4 CfgNANDSELCS [3] R Select nand chip 0 or 1 when (CfgBootMode == 7). 0 = nNCS[0] 1 = nNCS[1] In the case of (CfgBootMode == 4'hF), CfgNANDSELCS is ignored and nNCS[1] can be used only SD3 CfgNANDPage [2] R Indicates External nand page size when (CfgBootMode == 7). 0 = 2K or below 1 = 4K or above SD2 CfgNANDType [1:0] R Indicates External nand type when (CfgBootMode == 2'b{SD1, SD0} cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-56 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 7). 0 = Small Block 3 Address 1 = Small block 4 Address 2 = Large 4 Address 3 = Large 5 Address cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-57 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2 Tie Off

 Base Address: 0xC001_0000 Register Offset Description Reset Value TIEOFFREG00 1000 CPU Configuration 0 Register 0x00C0_0000 TIEOFFREG01 1004 CPU Configuration 1 Register 0x1E0D_800C TIEOFFREG02 1008 DISPLAY Configuration 0 Register 0xFDB6_C78F TIEOFFREG03 100C DISPLAY Configuration 1/ MCU Configuration 0 Register 0x98C1_B6C6 TIEOFFREG04 1010 MCU Configuration 1/ UART Configuration 0 Register 0x0001_FFB7 TIEOFFREG05 1014 UART Configuration 1/ USBHOST Configuration 0 Register 0x0400_83C0 TIEOFFREG06 1018 USBHOST Configuration 1 Register 0x0000_0000 TIEOFFREG07 101C USBHOST Configuration 2 Register 0x0000_0000 TIEOFFREG08 1020 USBHOST Configuration 3 Register 0xAC00_6D00 TIEOFFREG09 1024 USBHOST Configuration 4 Register 0x3E38_0200 TIEOFFREG10 1028 USBHOST Configuration 5 Register 0x3240_0153 TIEOFFREG11 102C USBHOST Configuration 6 Register 0x0F3A_202B TIEOFFREG12 1030 USBOTG Configuration 0 Register 0x0000_0001 TIEOFFREG13 1034 USBOTG Configuration 1 Register 0xA000_6D00 TIEOFFREG14 1038 USBOTG Configuration 2 Register 0x3E38_0200 TIEOFFREG15 103C USBOTG Configuration 3 Register 0x3FC0_0153 TIEOFFREG16 1040 CODA Configuration 0 Register 0x00FF_FFFF TIEOFFREG17 1044 CODA Configuration 1 Register 0x3FFF_FFFF TIEOFFREG18 1048 CODA Configuration 2 Register 0xFFFF_FFFF TIEOFFREG19 104C CODA Configuration 3 Register 0x0FFF_FFFF TIEOFFREG20 1050 CODA Configuration 4 Register 0x1B6D_BFFF TIEOFFREG21 1054 CODA Configuration 5 Register 0x6C86_306C TIEOFFREG22 1058 GPU Configuration 0 Register 0xFFFE_18DB TIEOFFREG23 105C GPU Configuration 1 Register 0x001F_FFFF TIEOFFREG24 1060 GPU Configuration 2 Register 0x0000_0000 TIEOFFREG25 1064 GPU Configuration 3 Register 0xFFFF_FFFF TIEOFFREG26 1068 GPU Configuration 4 Register 0x0000_0000 TIEOFFREG27 106C GPU Configuration 5 Register 0xFFFF_FFFF TIEOFFREG28 1070 GPU Configuration 6 Register 0x0000_0000 TIEOFFREG29 1074 GPU Configuration 7 Register 0xFFFF_FFFF TIEOFFREG30 1078 GPU Configuration 8 Register 0xFFFF_FFFF TIEOFFREG31 107C GPU Configuration 9 Register 0xFFFF_FFFF TIEOFFREG32 1080 BUS Configuration 0 Register 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-58 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. NOTE: SRAM EMA signals are for chip test only. Users don't need to control those registers for normal functions. SRAM EMA: Extra Margin Adjustment EMA: SRAM read/write margin EMAW: SRAM write margin EMAS: SRAM S/A pulse width cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-59 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.1 TIEOFFREG00

 Base Address: 0xC001_0000  Address = Base Address + 1000, Reset Value = 0x00C0_0000 Name Bit Type Description Reset Value RSVD [31] – Reserved 0 CA9_L1EMAW [30:29] RW Cortex-A9 L1 Cache EMAW value 0 CA9_TEINIT [28:25] RW Individual Cortex-A9 Processor out-of-reset default exception handling state. When set to: 0 = ARM 1 = Thumb. This pin is only sampled during reset of the processor. It sets the initial value of SCTLR.TE. CA9_L2EMA [24:22] RW Cortex-A9 L2 Cache EMA value 3 CA9_VINITHI [21:18] RW Individual Cortex-A9 Processor control of the location of the exception vectors at reset: 0 = Exception vectors start at address 0x00000000 1 = Exception vectors start at address 0xFFFF0000. This pin is only sampled during reset of the processor. It sets the initial value of SCTLR.V. CA9_CLAMPL2_1 [17] RW Enables L2 cache way 8 to 15 memory clamp cells 0 CA9_CLAMPL2_0 [16] RW Enables L2 cache way 0~7 memory clamp cells 0 CA9_L2PGEN_1 [15] RW Power Down Enable for L2 cache way 8 to 15 0 CA9_L2PGEN_0 [14] RW Power Down Enable for L2 cache way 0 to 7 0 CA9_L2RET1N_1 [13] RW Retention mode enable1 for L2 cache way 8 to 15 0 CA9_L2RET1N_0 [12] RW Retention mode enable1 for L2 cache way 0 to 7 0 CA9_L1EMAS [11] RW Cortex-A9 L1 Cache EMAS value 0 CA9_L2_CFGENDIAN [10] RW For L2 cache controller, big-endian mode for accessing configuration registers out of reset 0 CA9_CPU3PWRDOWN [9] RW Activates CPU3 power gating cells 0 = CPU3 Active 1 = CPU3 Power Down CA9_CPU2PWRDOWN [8] RW Activates CPU2 power gating cells 0 = CPU2 Active 1 = CPU2 Power Down CA9_CPU1PWRDOWN [7] RW Activates CPU1 power gating cells 0 = CPU1 Active 1 = CPU1 Power Down CA9_CPU0PWRDOWN [6] RW Activates CPU0 power gating cells 0 = CPU0 Active 1 = CPU0 Power Down CA9_COREPWRDOWN [5] RW Activates Cortex-A9 QAUD power gating cells 0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-60 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 0 = Cortex-A9 Quad Active 1 = Cortex-A9 Quad Power Down CA9_CLAMPCPU3 [4] RW Enables CPU3 output port clamp cells 0 CA9_CLAMPCPU2 [3] RW Enables CPU3 output port clamp cells 0 CA9_CLAMPCPU1 [2] RW Enables CPU3 output port clamp cells 0 CA9_CLAMPCPU0 [1] RW Enables CPU3 output port clamp cells 0 CA9_CLAMPCOREOUT [0] RW Enables the Cortex-A9 QAUD output port clamp cells 0

4.9.1.2.2 TIEOFFREG01

 Base Address: 0xC001_0000  Address = Base Address + 1004, Reset Value = 0x1E0D_800C Name Bit Type Description Reset Value RSVD [31:30] RW Reserved 0 RSVD [29:27] RW Reserved 3 AXISRAM_NSLEEP [26] RW AXISRAM SRAM retention (low active) 1 AXISRAM_NPOWERDO WN [25] RW Reserved 1 AXISRAM_RA2W_EMA WB [24:23] RW AXISRAM EMAWB value 0 AXISRAM_RA2W_EMA WA [22:21] RW AXISRAM EMAWA value 0 AXISRAM_RA2W_EMAB [20:18] RW AXISRAM EMAB value 3 AXISRAM_RA2W_EMAA [17:15] RW AXISRAM EMAA value 3 CA9_PWRCTLI2 [14:13] RW Reset value for CPU2 status register [3:2] 0 CA9_PWRCTLI1 [12:11] RW Reset value for CPU1 status register [3:2] 0 CA9_PWRCTLI0 [10:9] RW Reset value for CPU0 status register [1:0] 0 CA9_CPUCLKOFF [8:5] RW Activates individual processor clock gating cells 0 = Clock is enabled 1 = Clock is stopped CA9_L1EMA [4:2] RW Cortex-A9 L1 Cache EMA value 3 CA9_L2EMAW [1:0] RW Cortex-A9 L2 Cache EMAW value 0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-61 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.3 TIEOFFREG02

 Base Address: 0xC001_0000  Address = Base Address + 1008, Reset Value = 0xFDB6_C78F Name Bit Type Description Reset Value HDMI_NSLEEP [31:30] RW HDMI SRAM retention (low active) 3 RESERVED [29:28] RW 3 RESCONV_NSLEEP [27] RW Resolution Converter SRAM retention (low active) 1 RESERVED [26] RW 1 DEINTER_RF2W_EMAB [25:23] RW De-Interlacer RF2W SRAM EMAB value 3 DEINTER_RF2W_EMAA [22:20] RW De-Interlacer RF2W SRAM EMAA value 3 DEINTER_RF2_EMAB [19:17] RW De-Interlacer RF2 SRAM EMAB value 3 DEINTER_RF2_EMAA [16:14] RW De-Interlacer RF2 SRAM EMAA value 3 DEINTER_RF1_EMAW [13:12] RW De-Interlacer RF1 SRAM EMAW value 0 DEINTER_RF1_EMA [11:9] RW De-Interlacer RF1 SRAM EMA value 3 RESERVED [8] RW 1 RESERVED [7] RW 1 RESERVED [6:5] RW 0 RESERVED [4:2] RW 3 RESERVED [1] RW 1 RESERVED [0] RW 1

4.9.1.2.4 TIEOFFREG03

 Base Address: 0xC001_0000  Address = Base Address + 100C, Reset Value = 0x98C1_B6C6 Name Bit Type Description Reset Value DREX_DFI_RESET_N_P0 [31] RW DFI reset signal. Reset value for dfi_reset_n_pN[1:0] are 1. These signals areonly required for DDR3 support. dfi_reset_n_p0/p1 is connected to io_reset_out. DREX_CTRL_HCKE [30] RW This signal decides the reset value of CKE and some signals. If this bit is set, reset value of io_cke_out is 1. Otherwise, reset value of them is 0. DREX_PEREV_TRIGGER [29] RW DERX Performance Event Trigger Enable bit 0x0 = disables all counters including CCNT 0x1 = enables all counters including CCNT When you read it, 1 means it's counting and 0 means it's idle(stop counting). You can write it only when the start mode is set to be 0(PPMU is started by CPU). At this time, you can write this bit by 1 to start counting cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-62 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value and write it by 0 to stop the counting. When the start mode is set to be 1(PPMU is started by SYSCON), you only can read it and get the status of the PPMU. At this time PPMU is controlled by external trigger. When external trigger is 1, counting starts, and when external trigger is 0, counting stops. DREX_PAUSE_REQ [28] RW DREX-1 supports pause feature through external ports called "PAUSE_REQ" and "PAUSE_ACK". When PAUSE_ACK is set to low, DREX-1 guarantees that there will be no requests issued to the DRAM until the external port PAUSE_REQ is driven to high. This feature is used for switching the clock frequency of the memory interface. Clock frequency change of memory can be applied through this pause feature like below procedures. Pause request setting PAUSE_REQ to low. DREX-1 sets AxREADY to low. DREX-1 finishes memory access until queue empty. DREX-1 sets PAUSE_ACK to low. Clock frequency changes. Release pause request setting PAUSE_REQ to high. DREX-1 sets AxREADY and PAUSE_ACK to high. Master side of this protocol should not change PAUSE_REQ value before finishing previous handshaking. It means that PAUSE_REQ should be waiting for the PAUSE_ACK before change its value. DREX_CSYSREQ [27] RW AXI Low power interface Request signal. 1 DREX_CA_SWAP [26] RW DREX-1 has an input signal named ca_swap. If this signal is driven to 1, the DFI interface's address signals will have its bit locations reversed. (addr[9] and addr[0] will be swapped, addr[8] and addr[1] will be swapped, etc) The purpose of this signal is for supporting different packaging solutions, so that the system level designer can choose among one of the modes depending on the routing requirement of the packaging or the PCB using the SoC with DREX-1. Please take care since driving the wrong ca_swap value may render the whole SoC unusable! The ca_swap feature is only valid on LPDDR2/LPDDR3 modes, and has no effect on DDR3 modes. DREX_CKE_INIT [25] RW DREX CKE signal initialization. It sets the state of CKE[MEMORY_CHIPS-1:0] when resetn is de-asserted. The default value is set by the state of cke_init, when resetn goes HIGH. VROM_EMA [24:22] RW ROM EMA value 3 DISPLAY_DPSRAM_EMA [21:20] RW DISPLAY SRAM EMAWB value 0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-63 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value WB DISPLAY_DPSRAM_EMA WA [19:18] RW DISPLAY SRAM EMAWA value 0 DISPLAY_DPSRAM_EMA B [17:15] RW DISPLAY SRAM EMAB value 3 DISPLAY_DPSRAM_EMA A [14:12] RW DISPLAY SRAM EMAA value 3 DISPLAY_DPSRAM_1R1 W_EMAB [11:9] RW DISPLAY SRAM EMAB value 3 DISPLAY_DPSRAM_1R1 W_EMAA [8:6] RW DISPLAY SRAM EMAA value 3 DISPLAY_SPSRAM_EMA W [5:4] RW DISPLAY SRAM EMAW value 0 DISPLAY_SPSRAM_EMA [3:1] RW DISPLAY SRAM EMA value 3 HDMI_PHY_REFCLK_SE L [0] RW Reference Clock Selection. REFCLK_SEL is used for PHY reference clock selection. REFCLK_SEL = 1'b0: CLKI REFCLK_SEL = 1'b1: INT_CLK cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-64 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.5 TIEOFFREG04

 Base Address: 0xC001_0000  Address = Base Address + 1010, Reset Value = 0x0001_FFB7 Name Bit Type Description Reset Value UART3_SMCRXENB [31] RW SmartCard Interface RX mode enable 0 UART3_SMCTXENB [30] RW SmartCard Interface TX mode enable 0 UART3_USESMC [29] RW Use UART for SmartCard Interface 0 UART2_SMCRXENB [28] RW SmartCard Interface RX mode enable 0 UART2_SMCTXENB [27] RW SmartCard Interface TX mode enable 0 UART2_USESMC [26] RW Use UART for SmartCard Interface 0 UART1_SMCRXENB [25] RW SmartCard Interface RX mode enable 0 UART1_SMCTXENB [24] RW SmartCard Interface TX mode enable 0 UART1_USESMC [23] RW Use UART for SmartCard Interface 0 UART0_SMCRXENB [22] RW SmartCard Interface RX mode enable 0 UART0_SMCTXENB [21] RW SmartCard Interface TX mode enable 0 UART0_USESMC [20] RW Use UART for SmartCard Interface 0 SCALER_EMAW [19:18] RW SCALER SRAM EMAW value 0 SCALER_EMA [17:15] RW SCALER SRAM EMA value 3 MIPI_NSLEEP [14:11] RW MIPI SRAM retention (low active) F RESERVED [10:7] RW F MIPI_DPSRAM_1R1W_ EMAB [6:4] RW MIPI SRAM EMAB value 3 MIPI_DPSRAM_1R1W_ EMAA [3:1] RW MIPI SRAM EMAA value 3 DREX_DFI_RESET_N_P 1 [0] RW DFI reset signal. Reset value for dfi_reset_n_pN[1:0] are 1. These signals are only required for DDR3 support. dfi_reset_n_p0/p1 is connected to io_reset_out. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-65 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.6 TIEOFFREG05

 Base Address: 0xC001_0000  Address = Base Address + 1014, Reset Value = – Name Bit Type Description Reset Value HOST_phy_vstatus_0 [31:29] RW Vendor Status 0 HOST_SS_RESUME_UT MI_PLS_DIS [28] RW Resume Disable Function: This signal is valid only if ss_utmi_backward_enb_i is tied low. ss_resume_utmi_pls_dis_i controls the Resume termination sequence. If ss_resume_utmi_pls_dis_i is tied low, then the EHCI simultaneously switches term_sel[1:0] to 2'b00 and xver_sel to 1'b0. This transition occurs if either of the following two conditions is satisfied: SE0 is detected online_state or 255 PHY clocks elapse after tx valid is de-asserted. Ifss_resume_utmi_pls_dis_i is tied high, at the end of resume, tx valid is de-asserted and term_sel[1:0] is switched simultaneously to 2'b00. At this point, xver_sel is still high. After line_state is SE0 or if 255 PHY clocks elapse after tx valid is de-asserted, xver_sel switches to 1'b0. NOTE: For interfacing with ULPI PHY or UTMI+ PHY set ss_resume_utmipls_dis_i == 0 Active State: High HOST_SS_UTMI_BACK WARD_ENB [27] RW UTMI Backward Enable Function: This signal controls the Resume termination sequence as follows: When this signal is tied high, term_sel is switched to high-speed when tx valid is de-asserted. Before the xver_sel signal is switched to high speed, one of the following two conditions should to be met: 2 us of SE0 is detected on line_state

255 PHY clocks elapse after txvalid is de-asserted

When this signal is tied low, then it is used together with the strap signal ss_resume_utmi_pls_dis_i and the behavior of USB 2.0 Host is described in detail under strap signal ss_resume_utmi_pls_dis_i. The switching of term_sel is done first followed by xver_sel to create EOP as part of resume sequence. Since the term_sel which is xver_sel forUTMI+ PHY is switched during the last byte of transmit data (for sending resume, data is transmitted with bit stuff and NRZ disable) is coming on USB as garbage data and the device does not see a clean EOP for the resume sequence. NOTE: This signal is valid only if the USB 2.0 Host controller is interfaced to Synopsys PHY. If you use any third party PHY, then this signal needs to be tied cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-66 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value low. NOTE: For interfacing with ULPI PHY or UTMI+ PHY, set ss_utmi_backward_enb_i == 0 Active State: High HOST_SS_WORD_IF [26] RW Word Interface Function: Selects the data width of the UTMI/UTMI+ PHY interface. 1'b1: 16 -bit interface 1'b0: 8-bit interface Note: In ULPI mode, unless the 16-bit ULPI adapter is selected, you cannot set ss_word_if_i interface to 16- bit mode. In 8-bit ULPI mode, ss_word_if_i must be tied to 0. In 16-bit ULPI mode, the ss_word_if_i must reflect same value asulpi_mode16_en_i on page 97. When ulpi_mode16_en_i is tied to 0, then ss_word_if_i must also be tied to 0. In 16-bit ULPI mode, when ulpi_mode16_en_i is tied to 1, then ss_word_if_i must also be tied to 1. Active State: High HOST_SS_WORD_IF_E NB [25] RW Use Tieoff register value instead of controller value 0 HOST_HSIC_480M_FR OM_OTG_PHY [24] RW Select HSIC PHY 480M clock 0 : PLL clock 1 : HOST PHY output clock 0 HOST_HSIC_FREE_CL OCK_ENB [23] RW Select free clock of HSIC LINK. 0 : HOST PHY free clock 1 : HSIC PHY free clock 0 HOST_NHOSTHSICRES ETSYNC [22] RW Reset off HSIC LINK 0 HOST_NHOSTUTMIRES ETSYNC [21] RW Reset off UTMI clock of HOST LINK 0 HOST_NHOSTPHYRES ETSYNC [20] RW Reset off PHY clock of HOST LINK 0 HOST_NAUXWELLRES ETSYNC [19] RW Reset off Aux Well of HOST LINK 0 HOST_NRESETSYNC_ OHCI [18] RW Reset off OHCI of HOST LINK 0 HOST_NRESETSYNC [17] RW Sleep off OTG RAM 0 HOST_HSIC_EN [16:14] RW Description: HSIC into UTMI+ Interface Enable Function: This input pin exists only if the HSIC feature is enabled during core Consultant configuration. The width of this pin is 'UHC2_N_PORTS, the number of EHCI PHY ports in the host controller. Each pin is associated with its port number. 0 = When this pin is tied low, it indicates that the cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-67 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value associated port does not support HSIC. 1 = When this pin is tied high, it indicates that the associated port supports HSIC. The pin has to be tied to a valid value. This pin helps maintain backward compatibility of the controller for the HSIC feature per port. This pin is quasi static, that is, it doesn't change during a session and has to be tied to stable value (preferably) from power-on. If this pin is external to the core through registers, it must be stable before the enumeration of the port begins (before the AHB reset). This signal is implemented in one of two ways.  If heterogeneous ports is not selected during core Consultant configuration, this bussed input port should be driven to the same value homogeneously externally to the controller.  If heterogeneous ports is selected during core Consultant configuration, its width is still UHC2_N_PORTS, each bit is associated to a port in contiguous order, and each strap pin can independently and asynchronously enable HSIC per port. NOTE: This pin will be constrained as a false path from this input. It will be constrained from the AHB clock domain and end up being used in the UTMI+ clock domain. However, since the use model is quasi- static, this should not be an issue related to clock domain crossing. Active State: High HOST_SYS_INTERRUP T [13] RW System Interrupt, system error indication to host controller only for non-AHB errors. Function: DWC_h20ahb detects an error condition on the AHB and takes the appropriate action. In addition to AHB error conditions, this signal is active when any fatal error occurs during a host system access involving the controller. In order for the host to detect this signal, the minimum signal duration is at least one AHB clock pulse (hclk_i). In PCI-based design, fatal (not recoverable) PCI bus errors are: Target Abort Address Parity Error Master Abort NOTE: That when the EHCI and OHCI Host Controllers sample this signal asserted, the controllers are halted to prevent further execution of the scheduled descriptors and send a host System Error cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-68 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value interrupt. The EHCI and OHCI Host Controllers do not process any lists until the corresponding Host Controller Driver clears the corresponding error Active State: High HOST_NX_RF1_EMAW [12:11] RW USB2.0 HOST SRAM EMAW value 0 HOST_NX_RF1_EMA [10:8] RW USB2.0 HOST SRAM EMA value 3 HOST_NSLEEP [7] RW USB2.0 HOST SRAM retention (low active) 1 HOST_NPOWERDOWN [6] RW Power Down off OTG RAM 1 RESERVED [5] RW 0 RESERVED [4] RW 0 RESERVED [3] RW 0 UART4_SMCRXENB [2] RW SmartCard Interface RX mode enable 0 UART4_SMCTXENB [1] RW SmartCard Interface TX mode enable 0 UART4_USESMC [0] RW Use UART for SmartCard Interface 0

4.9.1.2.7 TIEOFFREG06

 Base Address: 0xC001_0000  Address = Base Address + 1018, Reset Value = – Name Bit Type Description Reset Value RSVD [31] – Reserved 0 HOST_SS_SIMULATION _MODE [30] RW Simulation Mode Function: When set to 1'b1, this bit sets the PHY in a non-driving mode so the EHCI can detect device connection. This signal is used only for simulation. Active State: High HOST_APP_PRT_OVRC UR [29:27] RW Port Over current Indication From Application Function: When asserted by the application, the corresponding port enters Disable state. This signal controls both EHCI and OHCI controller port state machines. Depending on ownership of the port, the corresponding EHCI or OHCI controller generates an Over current Detect interrupt. NOTE: That you must implement over current detection logic and provide input to the host. When an over current condition exists, port power remains on. Use the over current condition to control the port power. Active State: High HOST_SS_NEXT_POW ER_STATE [26:25] RW Next Power Management State Function: Power management for the next state output from PCI. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-69 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Active State: High HOST_SS_POWER_ST ATE [24:23] RW Power Management Function: Power management for the current state output from PCI. Active State: High HOST_SS_NXT_POWE R_STATE_VALID [22] RW Next Power Management State Valid Function: Due to the difference between the host AHB and the PCI clocks, the ss_next_power_state_i may not be in the correct state when input to the host controller. Therefore, ss_nxt_power_state_valid_i is used (as asynchronization signal) to validate the ss_next_power_state_i signal. When this signal is asserted, the ss_next_power_state_i input is valid. Active State: High HOST_SS_POWER_ST ATE_VALID [21] RW Power State Valid Function: Active high input qualifier signal for ss_power_state_i. Active State: High HOST_phy_vstatus_7 [20:18] RW Vendor Status 0 HOST_phy_vstatus_6 [17:15] RW Vendor Status 0 HOST_phy_vstatus_5 [14:12] RW Vendor Status 0 HOST_phy_vstatus_4 [11:9] RW Vendor Status 0 HOST_phy_vstatus_3 [8:6] RW Vendor Status 0 HOST_phy_vstatus_2 [5:3] RW Vendor Status 0 HOST_phy_vstatus_1 [2:0] RW Vendor Status 0

4.9.1.2.8 TIEOFFREG07

 Base Address: 0xC001_0000  Address = Base Address + 101C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value HOST_OHCI_0_APP_IR Q12 [31] RW External Interrupt 12 Function: This external keyboard controller interrupt 12 causes an emulation interrupt. Active State: High HOST_OHCI_0_APP_IR Q1 [30] RW External Interrupt 1 Function: This external keyboard controller interrupt 1 causes an emulation interrupt. Active State: High HOST_OHCI_0_CNTSE L_N [29] RW Count Select Function: Selects the counter value for simulation or real time for 1ms. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-70 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 1'b0: Count full 1 ms 1'b1: Simulation time Active State: Low HOST_SS_ENA_INCRX _ALIGN [28] RW Burst Alignment Enable Function: Forces AHB master to start INCR4/8/16 busts only on burst boundaries. AHB requires that double word width burst be addressed aligned only to the double-word boundary. 1'b1: Start INCRX burst only on burst x-aligned addresses 1'b0: Normal AHB operation; start bursts on any double word boundary NOTE: When this function is enabled, the burst are started only when the lowest bits of haddr are:  INCR4: haddr[3:0] == 4'b0000  INCR8: haddr[4:0] == 5'b00000  INCR16: haddr[5:0] == 6'b000000 Active State: High HOST_SS_ENA_INCR4 [27] RW AHB Burst Type INCR4 Enable Function: Enables the AHB master interface to utilize burst INCR8 when appropriate. 1'b1: Use INCR4 when appropriate 1'b0: Do not use INCR4; use other enabled INCRX bursts or un specified length burst INCR NOTE: The AHB INCRX enhancement must be enabled (during configuration) to utilize INCR4. If not, then this strap has no effect. The OHCI part of the controller only supports INCR4 or SINGLE. Active State: High HOST_SS_ENA_INCR8 [26] RW AHB Burst Type INCR8 Enable Function: Enables the AHB master interface to utilize burst INCR8 when appropriate. 1'b1: Use INCR8 when appropriate 1'b0: Do not use INCR8; use other enabled INCRX bursts or un specified length burst INCR NOTE: The AHB INCRX enhancement must be enabled (during configuration) to utilize INCR8. If not, then this strap has no effect. The OHCI does not support INCR8. Active State: High HOST_ss_ena_incr16 [25] RW AHB Burst Type INCR16 Enable Function: Enables the AHB master interface to utilize burst INCR16 when appropriate. 1'b1: Use INCR16 when appropriate 1'b0: Do not use INCR16; use other enabled INCRX bursts or unspecified length burst INCR cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-71 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Note: The AHB INCRX enhancement must be enabled (during configuration) to utilize INCR16. If not, then this strap has no effect. The OHCI does not support INCR16. Active State: High HOST_SS_AUTOPPD_O N_OVERCUR_EN [24] RW Auto Port Power Disable on Over current Function: This strap signal enables automatic port power disable in the host controller. When this signal is active, if an over-current condition is detected on a powered port and PPC is 1, the PP bit in each affected port is automatically transitioned by the host controller from a 1 to 0, removing power from the port. NOTE: If this strap signal is not high, then the software needs to disable port power when an over current condition occurs. Active State: High HOST_SS_FLADJ_VAL_ 0 [23:21] RW Frame Length Adjustment Register for Port 0 Function: This feature adjusts the frame length of the micro frame per port. This value must be the same as that of ss_fladj_val_host_i, or the EHCI yields undefined results. See ss_fladj_val_host_i for the adjustment value. Active State: High HOST_SS_FLADJ_VAL _1 [20:18] RW Frame Length Adjustment Register for Port 1 Function: This feature adjusts the frame length of the micro frame per port. This value must be the same as that of ss_fladj_val_host_i, or the EHCI yields undefined results. See ss_fladj_val_host_i for the adjustment value. Active State: High HOST_SS_FLADJ_VAL _2 [17:15] RW Frame Length Adjustment Register for Port 2 Function: This feature adjusts the frame length of the micro frame per port. This value must be the same as that of ss_fladj_val_host_i, or the EHCI yields undefined results. See ss_fladj_val_host_i for the adjustment value. Active State: High HOST_SS_FLADJ_VAL _3 [14:12] RW Frame Length Adjustment Register for Port 3 Function: This feature adjusts the frame length of the micro frame per port. This value must be the same as that of ss_fladj_val_host_i, or the EHCI yields undefined results. See ss_fladj_val_host_i for the adjustment value. Active State: High HOST_SS_FLADJ_VAL _4 [11:9] RW Frame Length Adjustment Register for Port 4 Function: This feature adjusts the frame length of the micro frame per port. This value must be the same as cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-72 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value that of ss_fladj_val_host_i, or the EHCI yields undefined results. See ss_fladj_val_host_i for the adjustment value. Active State: High HOST_SS_FLADJ_VAL _5 [8:6] RW Frame Length Adjustment Register for Port 5 Function: This feature adjusts the frame length of the micro frame per port. This value must be the same as that of ss_fladj_val_host_i, or the EHCI yields undefined results. See ss_fladj_val_host_i for the adjustment value. Active State: High HOST_SS_FLADJ_VAL_ HOST [5:0] RW Frame Length Adjustment Register Function: This feature adjusts any offset from the clock source that drives the μSOF counter. The μSOF cycle time (number of μSOF counter clock periods to generate a μSOF micro frame length) is equal to 59,488 plus this value. The default value is decimal 32 (0x20), which gives an SOF cycle time of 60,000 (each micro frame has 60,000 bit times). Frame Length (decimal) FLADJ Value (decimal) 59488 0 (0x00) 59504 1 (0x01) 59520 2 (0x02) … … 59984 31 (0x1F) 60000 32 (0x20) … … 60496 63 (0x3F) NOTE: That this register must be modified only when the HC Halted bit in the USBSTS register is set to 1; otherwise, the EHCI yields undefined results. The register must not be reprogrammed by the USB system software unless the default or BIOS programmed values are incorrect, or the system is restoring the register while returning from a suspended state. Connect this signal to value 0x20 (32 decimal) for no offset. Active State: High cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-73 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.9 TIEOFFREG08

 Base Address: 0xC001_0000  Address = Base Address + 1020, Reset Value = 0xAC00_6D00 Name Bit Type Description Reset Value HOST_SLEEPM [31] RW Sleep Assertion Function: Asserting this signal places the USB 2.0 picoPHY in Sleep mode according to the USB 2.0 Link Power Management (LPM) addendum to the USB2.0 specification. In Sleep Mode, the transmitter is tri- stated and the USB 2.0picoPHY circuits are powered down except for the XO block If the reference clock isa crystal, the XO block remains powered when the USB 2.0 picoPHY is placed in Sleep mode. 0 = Sleep mode 1 = Normal operating mode If SUSPENDM0 is set to 1'b0, the USB 2.0 picoPHY will remain in Suspend mode irrespective of the SLEEPM0 setting. If the LPM function is not required, SLEEPM0 must be tied to DVDD. USB 2.0picoPHY Sleep mode can be overridden using the test interface. Voltage Range: 0 V-DVDD Active State: Low HOST_SLEEPM_ENB [30] RW Use Tieoff register value instead of controller value 0 HOST_SUSPENDM [29] RW Suspend Assertion Function: Asserting this signal suspends the USB 2.0 picoPHY by tri-stating the transmitter and powering down the USB 2.0 picoPHY circuits. 0 = Suspend mode 1 = Normal operating mode USB 2.0 picoPHY power-down behavior can be overridden using the test interface. Voltage Range: 0 V-DVDD Active State: Low HOST_SUSPENDM_EN B [28] RW Use Tieoff register value instead of controller value 0 HOST_DMPULLDOWN [27] RW D- Pull-Down Resistor Enable Function: This controller signal controls the pull-down resistance on the D- line. 0 = The pull-down resistance on D- is disabled 1 = The pull-down resistance on D- is enabled When an A/B device is acting as a host (downstream- facing port), DPPULLDOWN0 and DMPULLDOWN0 are enabled. NOTE: UTMI+/OTG-compliant controllers are not allowed to toggleDPPULLDOWN0 and cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-74 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value DMPULLDOWN0 during normal operation. Voltage Range: 0 V-DVDD Active State: High HOST_DPPULLDOWN [26] RW D+ Pull-Down Resistor Enable Function: This controller signal controls the pull-down resistance on the D+ line. 0 = The pull-down resistance on D+ is disabled 1 = The pull-down resistance on D+ is enabled When an A/B device is acting as a host (downstream- facing port),DPPULLDOWN0 and DMPULLDOWN0 are enabled. Note: UTMI+/OTG-compliant controllers are not allowed to toggleDPPULLDOWN0 and DMPULLDOWN0 during normal operation. Voltage Range: 0 V-DVDD Active State: High HOST_VBUSVLDEXTSE L [25] RW External VBUS Valid Select Function: This signal selects either the VBUSVLDEXT0 input or the internal Session Valid comparator to generate the OTGSESSVLD0 output. To avoid potential glitches in DP0, VBUSVLDEXTSEL0 must be static prior to a power- on reset and remain static during normal operation. The OTGSESSVLD0 signal, in conjunction with XCVRSEL0[1:0],OPMODE0[1:0], TERMSEL0, DPPULLDOWN0, and DMPULLDOWN0,control the DP0 pull-up resistor. If VBUSVLDEXT0 and the internal Session Valid comparator output are asserted, and VBUSEXTSEL0changes, it is possible for OTGSESSVLD0 to glitch low, causing the DP0resistor to be temporarily disabled. 0 = The internal Session Valid comparator is used to generateOTGSESSVLD0 and assert the DP0 pull-up resistor. 1 = The VBUSVLDEXT0 input is used to generate OTGSESSVLD0 and assert the DP0 pull-up resistor This signal is not critical for STA, and any other timings or loading limits for the pin are specified in the .lib timing model included in the product deliverables. Voltage Range: 0 V-DVDD Active State: High HOST_VBUSVLDEXT [24] RW External VBUS Valid Indicator Function: This signal is valid in Device mode and only when theVBUSVLDEXTSEL0 signal is set to 1'b1. VBUSVLDEXT0 indicates whether the VBUS signal on the USB cable is valid. In addition, VBUSVLDEXT0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-75 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value enables the pull-up resistor on the D+ line. 0 = The VBUS signal is not valid, and the pull-up resistor on D+ is disabled. 1 = The VBUS signal is valid, and the pull-up resistor on D+ is enabled In Host mode, this input is not used and can be tied to 1'b0. Voltage Range: 0 V-DVDD Active State: N/A HOST_ADPPRBENB [23] RW ADP Probe Enable Function: Enables/disables the ADP Probe comparator. 0 = ADP Probe comparator is disabled 1 = ADP Probe comparator is enabled If this signal is not used, tie it to 1'b0. Voltage Range: 0 V-DVDD Active State: High HOST_ADPDISCHRG [22] RW VBUS Input ADP Discharge Enable Function: Controls discharging the VBUS input during ADP. 0 = Disables discharging VBUS during ADP. 1 = Enables discharging VBUS during ADP. If this signal is not used, tie it to 1'b0. Voltage Range: 0 V-DVDD Active State: High HOST_ADPCHRG [21] RW VBUS Input ADP Charge Enable Function: Controls charging the VBUS input during ADP. 0 = Disables charging VBUS during ADP. 1 = Enables charging VBUS during ADP. If this signal is not used, tie it to 1'b0. Voltage Range: 0 V-DVDD Active State: High HOST_DRVVBUS [20] RW Drive VBUS Function: This controller signal controls the VBUS Valid comparator. Thissignal drives 5 V on VBUS through an external charge pump. When OTGDISABLE0 is set to 1'b0 and DRVVBUS0 is asserted, theBandgap circuitry and VBUS Valid comparator are powered, even inSuspend or Sleep mode. 0 = The VBUS Valid comparator is disabled. 1 = The VBUS Valid comparator is enabled. Voltage Range: 0 V-DVDD Active State: High cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-76 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value HOST_IDPULLUP [19] RW Analog ID Input Sample Enable Function: This controller signal controls ID line sampling. 0 = ID pin sampling is disabled, and the IDDIG0 output is not valid. 1 = ID pin sampling is enabled, and the IDDIG0 output is valid. Voltage Range: 0 V-DVDD Active State: High HOST_LOOPBACKENB [18] RW Loopback Test Enable Function: This signal places the USB 2.0 picoPHY in Loopback mode, which enables the receive and transmit logic concurrently. 0 = During data transmission, the receive logic is disabled. 1 = During data transmission, the receive logic is enabled. NOTE: Loopback mode is for test purposes only; it cannot be used for normal operation. In normal operation, tie this signal low. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High HOST_OTGDISABLE [17] RW OTG Block Disable Function: This signal powers down the VBUS Valid comparator, but not the Session Valid comparator, ADP probe and sense comparators, nor the ID detection circuitry. To save power, if the application does not use the OTG function, this input can be set high. 0 = The OTG block is powered up. 1 = The OTG block is powered down. Voltage Range: 0 V-DVDD Active State: High HOST_PORTRESET [16] RW Per-Port Reset Function: When asserted, this signal resets the corresponding port's transmit and receive logic without disabling the clocks within the USB 2.0 picoPHY. 0 = The transmit and receive FSMs are operational, and the line_state logic becomes sequential after 11 PHYCLOCK0 cycles. 1 = The transmit and receive finite state machines (FSMs) are reset, and the line_state logic combinatorially reflects the state of the single-ended receivers. Asserting PORTRESET0 does not override any USB 2.0 picoPHY inputs that normally control the USB cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-77 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value state, nor does it cause any transient, illegal USB states. Within 100 ns of asserting PORTRESET0, the controller must set the inputs that control the USB to values that cause a safe state. A safe state for Host and Device modes is defined as follows:  Host mode: Non-driving (OPMODE0[1:0] = 2'b01) with the 15 k pull-down resistors enabled (DPPULLDOWN0 and DMPULLDOWN0 = 1'b1)  Device mode: Non-driving (OPMODE0[1:0] = 2'b01) with the 1.5 k pull-up resistor disabled Voltage Range: 0 V-DVDD Active State: High HOST_RESREQIN [15] RW Reserved Function: Reserved. Tie this pin to 1'b0. Voltage Range: 0 V-DVDD HOST_COMMONONN [14] RW Common Block Power-Down Control Function: This signal controls the power-down signals in the XO, Bias, and PLL blocks when the USB 2.0 picoPHY is in Suspend, or Sleep mode. 0 = In Suspend mode, the XO, Bias, and PLL blocks remain powered in Suspend mode. In Sleep mode, if the reference clock is a crystal, the XO block remains powered. 1 = In Suspend mode, the XO, Bias, and PLL blocks are powered down. In Sleep mode, the Bias and PLL blocks are powered down. This signal is a strapping option that must be set prior to a power-on reset and remain static during normal operation. Strapping options are not critical for STA, and any other timings or loading limits for the pin are specified in the .lib timing model included in the product deliverables. NOTE: 1. If COMMONONN is set low, CLK48MOHCI and CLK480M remain available in Suspend or UART/Auto resume mode. 2. If the reference clock source is a crystal, CLK12MOHCI remains available in Suspend or UART/Auto resume mode, only if COMMONONN is set to 1'b0. 3. If the reference clock source is either an external clock (connected to XO) or CLKCORE, CLK12MOHCI will continue to pulse in Suspend or UART/Auto resume mode, even when COMMONONN is set to 1'b1. 4. In Sleep mode, CLK48MOHCI and CLK12MOHCI cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-78 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value are always available, irrespective of COMMONONN. Voltage Range: 0 V-DVDD Active State: Low HOST_FSEL [13:11] RW Reference Clock Frequency Select Function: Selects the USB 2.0 picoPHY reference clock frequency. 000 = 9.6 MHz 001 = 10 MHz 010 = 12 MHz 011 = 19.2 MHz 100 = 20 MHz 101 = 24 MHz 110 = Reserved 111 = 50 MHz Voltage Range: 0 V-DVDD Active State: N/A HOST_REFCLKSEL [10:9] RW Reference Clock Select for PLL Block Function: This signal selects the reference clock source for the PLL block. 00 = The XO block uses the clock from a crystal. 01 = The XO block uses an external, 1.8-V clock supplied on the XO pin. 10 = The PLL uses CLKCORE as reference. 11 = Reserved This bus is a strapping option that must be set prior to a power-on reset and remain static during normal operation. Strapping options are not critical for STA, and any other timings or loading limits for the pin are specified in the .lib timing model included in the product deliverables. Voltage Range: 0 V-DVDD Active State: N/A HOST_POR [8] RW Power-On Reset Function: This signal resets all test registers and state machines in the USB 2.0picoPHY. The POR signal must be asserted for a minimum of 10 μs. Voltage Range: 0 V-DVDD Active State: High HOST_POR_ENB [7] RW Use Tieoff register value instead of controller value 0 HOST_VATESTENB [6:5] RW Analog Test Pin Select Function: Enables analog test voltages to be placed on either the ANALOGTEST or ID0 pin. 00 = Analog test voltages cannot be viewed or applied on either ANALOGTEST or ID0. 01 = Analog test voltages can be viewed or applied on cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-79 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value ID0. 10 = Analog test voltages can be viewed or applied on ANALOGTEST. 11 = Reserved. Invalid setting. If this bus is not used, tie these inputs low. Voltage Range: 0 V-DVDD Active State: N/A HOST_SIDDQ [4] RW IDDQ Test Enable Function: This test signal enables you to perform IDDQ testing by powering downall analog blocks. Before asserting SIDDQ, ensure that VDATSRCENB0, VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0, and TESTBURNIN are set to 1'b0. 0 = The analog blocks are powered up. 1 = The analog blocks are powered down. If this signal is not used, tie it low. Voltage Range: 0 V-DVDD Active State: High HOST_OHCI_SUSP_LG CY [3] RW OHCI Clock control signal Function: This is a static strap signal.  When tied HIGH and the USB port is owned by OHCI, the signal utmi_suspend_o_n reflects the status of the USB port: (suspended or not suspended).  When tied LOW and the USB port is owned by OHCI, then utmi_suspend_o_n asserts (0) if all the OHCI ports are suspended, or if the OHCI is in global suspend state (HCFS = USBSUSOPEND). utmi_suspend_o_n de-asserts (1) if any of the OHCI ports are not suspended and OHCI is not in global suspend. Note: This strap must be tied low if the OHCI 48/12 MHz clocks must be suspended when the EHCI and OHCI controllers are not active. Active State: NA HOST_APP_START_CL K [2] RW OHCI Clock control signal Function: This is an asynchronous primary input to the host core. When the OHCI clocks are suspended, the system has to assert this signal to start the clocks (12 and 48 MHz). This should be de-asserted after the clocks are started and before the host is suspended again. (Host is suspended means HCFS = SUSPEND or all the OHCI ports are suspended). Active State: High cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-80 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value HOST_SS_HUBSETUP_ MIN [1] RW Hub setup time control signal Function: This is static strap signal. Some FS devices down the hub do not recover properly after a pre-amble packet, directed at other LS device, if the hub setup time is four FS clocks. Four FS clocks just meet the specification. By adding one extra clock, these FS devices are made to work better. This strap selects four or five FS clocks as hub setup time for interoperability with the various devices. It is recommended to tie low, that is, for five FS clocks.  When tied HIGH, four FS clocks of hub setup time is used.  When tied LOW, five FS clocks of hub setup time is used. Active State: NA HOST_OHCI_0_APP_IO _HIT [0] RW Application I/O Hit Function: This signal indicates a PCI I/O cycle strobe. (This signal is relevant only when using a PCI controller.) Active State: High

4.9.1.2.10 TIEOFFREG09

 Base Address: 0xC001_0000  Address = Base Address + 1024, Reset Value = 0x3E38_0200 Name Bit Type Description Reset Value HOST_TXFSLSTUNE [31:28] RW FS/LS Source Impedance Adjustment Function: This bus adjusts the low- and full-speed single-ended source impedance while driving high. The following adjustment values are based on nominal process, voltage, and temperature. 0000 = + 5 % 0001 = + 2.5 % 0011 = Design default 0111 = – 2.5 % 1111 = – 5 % All other bit settings are reserved. Voltage Range: 0 V-DVDD Active State: N/A HOST_TXHSXVTUNE [27:26] RW Transmitter High-Speed Crossover Adjustment Function: This bus adjusts the voltage at which the DP0 and DM0 signals cross while transmitting in HS mode. 00 = Reserved 01 = – 15 mV 10 = + 15 mV cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-81 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 11 = Default setting Voltage Range: 0 V-DVDD Active State: N/A HOST_OTGTUNE [25:23] RW VBUS Valid Threshold Adjustment Function: This bus adjusts the voltage level for the VBUS Valid threshold. 000: – 12 % 001: – 9 % 010: – 6 % 011: – 3 % 100: Design default 101: + 3 % 110: + 6 % 111: + 9 % If this bus is not used, leave it at the default setting. Voltage Range: 0 V-DVDD Active State: N/A HOST_SQRXTUNE [22:20] RW Squelch Threshold Adjustment Function: This bus adjusts the voltage level for the threshold used to detect valid high-speed data. 000: + 15 % 001: + 10 % 010: + 5 % 011: Design default 100: – 5 % 101: – 10 % 110: – 15 % 111: – 20 % Voltage Range: 0 V-DVDD Active State: N/A HOST_COMPDISTUNE [19:17] RW Disconnect Threshold Adjustment Function: This bus adjusts the voltage level for the threshold used to detect a disconnect event at the host. 000: – 6 % 001: – 4.5 % 010: – 3 % 011: – 1.5 % 100: Design default 101: + 1.5 % 110: + 3 % 111: + 4.5 % If this bus is not used, leave it at the default setting. Voltage Range: 0 V-DVDD Active State: N/A HOST_BYPASSSEL [16] RW Transmitter Digital Bypass Select Function: Enables/disables Transmitter Digital Bypass cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-82 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value mode. 0 = Transmitter Digital Bypass mode is disabled. 1 = Transmitter Digital Bypass mode is enabled. If Transmitter Digital Bypass mode is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High HOST_BYPASSDMEN [15] RW DM0 Transmitter Digital Bypass Enable Function: Enables/disables the DM0 FS/LS driver in Transmitter Digital Bypass mode. 0 = DM0 FS/LS driver is disabled in Transmitter Digital Bypass mode. 1 = DM0 FS/LS driver is enabled and driven with the BYPASSDPDATA0 signal. If Transmitter Digital Bypass mode is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High HOST_BYPASSDPEN [14] RW DP0 Transmitter Digital Bypass Enable Function: Enables/disables the DP0 FS/LS driver in Transmitter Digital Bypass mode. 0 = DP0 FS/LS driver is disabled in Transmitter Digital Bypass mode. 1 = DP0 FS/LS driver is enabled and driven with the BYPASSDPDATA0 signal. If Transmitter Digital Bypass mode is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High HOST_BYPASSDMDAT A [13] RW Data for DM0 Transmitter Digital Bypass Function: In Transmitter Digital Bypass mode, this signal provides the data that is transmitted on DM0. 0 = DM0 FS/LS driver drives to a low state. 1 = DM0 FS/LS driver drives to a high state. If Transmitter Digital Bypass mode is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: N/A HOST_BYPASSDPDATA [12] RW Data for DP0 Transmitter Digital Bypass Function: In Transmitter Digital Bypass mode, this signal provides the data that is transmitted on DP0. 0 = DP0 FS/LS driver drives to a low state. 1 = DP0 FS/LS driver drives to a high state. If Transmitter Digital Bypass mode is not used, tie this input to 1'b0. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-83 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Voltage Range: 0 V-DVDD Active State: N/A HOST_TXBITSTUFFEN H [11] RW High-Byte Transmit Bit-Stuffing Enable Function: This controller signal controls bit stuffing on DATAINH0[7:0] whenOPMODE0[1:0] = 2'b11. 0 = Bit stuffing is disabled. 1 = Bit stuffing is enabled. Voltage Range: 0 V-DVDD Active State: High HOST_TXBITSTUFFEN [10] RW Low-Byte Transmit Bit-Stuffing Enable Function: This controller signal controls bit stuffing on DATAIN0[7:0] whenOPMODE0[1:0] = 2'b11. 0 = Bit stuffing is disabled. 1 = Bit stuffing is enabled. Voltage Range: 0 V-DVDD Active State: High HOST_WORDINTERFA CE [9] RW UTMI+ Data Bus Width and Clock Select Function: This controller signal selects the data bus width of the UTMI+ data buses. 0 = 8-bit data interface (PHYCLOCK0 frequency is 60 MHz) 1 = 16-bit data interface (PHYCLOCK0 frequency is

30 MHz)

The USB 2.0 picoPHY supports 8/16-bit data interfaces for all valid USB 2.0picoPHY speed modes. This signal is a strapping option that must be set prior to a power-on reset and remain static during normal operation. Strapping options are not critical for STA, and any other timings or loading limits for the pin are specified in the .lib timing model included in the product deliverables. Voltage Range: 0 V-DVDD Active State: N/A HOST_WORDINTERFA CE_ENB [8] RW Use Tieoff WORDINTERFACE instead of using USB2.0 HOST Controller signal 0 HOST_XCVRSEL [7:6] RW Transceiver Select Function: This controller bus selects the HS, FS, or LS Transceiver. 00 = HS Transceiver 01 = FS Transceiver 10 = LS Transceiver 11 = Sends an LS packet on an FS bus or receives an LS packet. NOTE: Due to the power-up time required by the HS Transmitter, the controller must not transmit a high- speed packet within 1.6 μs after switching cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-84 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value XCVRSEL0[1:0] to HS Transceiver (from any other setting). Voltage Range: 0 V-DVDD Active State: N/A HOST_XCVRSEL_ENB [5] RW Use Tieoff register value instead of controller value 0 HOST_TERMSEL [4] RW USB Termination Select Function: This controller signal sets the USB 2.0 picoPHY's terminations to FS or HS. 0 = High-speed terminations are enabled. 1 = Full-speed terminations are enabled. NOTE: Four PHYCLOCK0 cycles are required for internal synchronous reset generation, and an additional six cycles are required to enable HS terminations inthe digital core. Therefore, the controller must not transmit a high-speed packet within 10 PHYCLOCK0 cycles after switching TERMSEL0 to 1'b0. Voltage Range: 0 V-DVDD Active State: N/A HOST_TERMSEL_ENB [3] RW Use Tieoff register value instead of controller value 0 HOST_OPMODE [2:1] RW UTMI+ Operational Mode Function: This controller bus selects the UTMI+ operational mode. 00 = Normal 01 = Non-Driving 10 = Disable bit stuffing and NRZI encoding 11 = Normal operation without SYNC or EOP generation. If the XCVRSEL0[1:0]bus is not set to 2'b00 while OPMODE0[1:0] is set to 2'b11, USB 2.0 picoPHY behavior is undefined. NOTE: To perform battery charging, the USB 2.0 picoPHY must be placed in Non-Driving mode. Voltage Range: 0 V-DVDD Active State: N/A HOST_OPMODE_ENB [0] RW Use Tieoff register value instead of controller value 0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-85 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.11 TIEOFFREG10

 Base Address: 0xC001_0000  Address = Base Address + 1028, Reset Value = 0x3240_0153 Name Bit Type Description Reset Value HOST_HSIC_LOOPBACK ENB [31] RW Loopback Test Enable Function: This signal places the USB 2.0 pico PHY in Loopback mode, which enables the receive and transmit logic concurrently. 0 = During data transmission, the receive logic is disabled. 1 = During data transmission, the receive logic is enabled. NOTE: Loopback mode is for test purposes only; it cannot be used for normal operation. In normal operation, tie this signal low. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High HOST_HSIC_PORTRESE T [30] RW Per-Port Reset Function: When asserted, this signal resets the corresponding port's transmit and receive logic without disabling the clocks within the USB 2.0 picoPHY. 0 = The transmit and receive FSMs are operational, and the line_state logic becomes sequential after 11 PHYCLOCK0 cycles. 1 = The transmit and receive finite state machines (FSMs) are reset, and the line_state logic combinatorially reflects the state of the single-ended receivers. Asserting PORTRESET0 does not override any USB 2.0 picoPHY inputs that normally control the USB state, nor does it cause any transient, illegal USB states. Within 100 ns of asserting PORTRESET0, the controller must set the inputs that control the USB to values that cause a safe state. A safe state for Host and Device modes is defined as follows:  Host mode: Non-driving (OPMODE0[1:0] = 2'b01) with the 15 k pull-down resistors enabled (DPPULLDOWN0 and DMPULLDOWN0 = 1'b1)  Device mode: Non-driving (OPMODE0[1:0] = 2'b01) with the 1.5 k pull-up resistor disabled Voltage Range: 0 V-DVDD Active State: High HOST_HSIC_COMMONO NN [29] RW Common Block Power-Down Control Function: This signal controls the power-down signals in the XO, Bias, and PLL blocks when the USB 2.0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-86 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value picoPHY is in Suspend, or Sleep mode. 0 = In Suspend mode, the XO, Bias, and PLL blocks remain powered in Suspend mode. In Sleep mode, if the reference clock is a crystal, the XO block remains powered. 1 = In Suspend mode, the XO, Bias, and PLL blocks are powered down. In Sleep mode, the Bias and PLL blocks are powered down. This signal is a strapping option that must be set prior to a power-on reset and remain static during normal operation. Strapping options are not critical for STA, and any other timings or loading limits for the pin are specified in the .lib timing model included in the product deliverables. NOTE: 1. If COMMONONN is set low, CLK48MOHCI and CLK480M remain available in Suspend or UART/Auto resume mode. 2. If the reference clock source is a crystal, CLK12MOHCI remains available in Suspend or UART/Auto resume mode, only if COMMONONN is set to 1'b0. 3. If the reference clock source is either an external clock (connected to XO) or CLKCORE, CLK12MOHCI will continue to pulse in Suspend or UART/Auto resume mode, even when COMMONONN is set to 1'b1. 4. In Sleep mode, CLK48MOHCI and CLK12MOHCI are always available, irrespective of COMMONONN. Voltage Range: 0 V-DVDD Active State: Low HOST_HSIC_REFCLKSE L [28:27] RW Reference Clock Select for PLL Block Function: This signal selects the reference clock source for the PLL block. 00 = The XO block uses the clock from a crystal. 01 = The XO block uses an external, 1.8-V clock supplied on the XO pin. 10 = The PLL uses CLKCORE as reference. 11 = Reserved This bus is a strapping option that must be set prior to a power-on reset and remain static during normal operation. Strapping options are not critical for STA, and any other timings or loading limits for the pin are specified in the .lib timing model included in the product deliverables. Voltage Range: 0 V-DVDD Active State: N/A cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-87 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value HOST_HSIC_REFCLKDIV [26:20] RW 0x24 HOST_HSIC_POR [19] RW Power-On Reset Function: This signal resets all test registers and state machines in the USB 2.0picoPHY. The POR signal must be asserted for a minimum of 10 μs. Voltage Range: 0 V-DVDD Active State: High HOST_HSIC_POR_ENB [18] RW Use Tieoff register value instead of controller value 0 HOST_HSIC_SIDDQ [17] RW IDDQ Test Enable Function: This test signal enables you to perform IDDQ testing by powering down all analog blocks. Before asserting SIDDQ, ensure that VDATSRCENB0,VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0, and TESTBURNIN are set to 1'b0. 0 = The analog blocks are powered up. 1 = The analog blocks are powered down. If this signal is not used, tie it low. Voltage Range: 0 V-DVDD Active State: High HOST_HSIC_MSTRXCVR [16] RW 0 HOST_ACAENB [15] RW ACA ID_OTG Pin Resistance Detection Enable Function: Enables detection of resistance on the ID_OTG pin of an ACA. 0 = Disables detection of resistance on the ID_OTG pin of an ACA. 1 = Enables detection of resistance on the ID_OTG pin of an ACA. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High HOST_DCDENB [14] RW Data Contact Detection Enable Function: Enables current sourcing on the D+ line and pull-down resistance on the D- line for Data Contact Detect (DCD). 0 = IDP_SRC current is disabled, pull-down resistance on DM0 is disabled. 1 = IDP_SRC current is sourced onto DP0, pull-down resistance on DM0 is enabled. NOTE: During USB 2.0 picoPHY normal operation, set this signal low. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-88 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value HOST_VDATSRCENB [13] RW Battery Charging Sourcing Select Function: Enables or disables sourcing for battery charging. 0 = Data source voltage (VDAT_SRC) is disabled. 1 = Data source voltage (VDAT_SRC) is enabled. During USB 2.0 picoPHY normal operation, set this signal low. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High HOST_VDATDETENB [12] RW Battery Charging Attach/Connect Detection Enable Function: Enables or disables attach/connect detection. 0 = Data detect voltage (CHG_DET) is disabled. 1 = Data detect voltage (CHG_DET) is enabled. During USB 2.0 picoPHY normal operation, set this signal low. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High HOST_CHRGSEL [11] RW Battery Charging Source Select Function: Determines whether current is sourced onto or sunk from DP0 or DM0. 0 = Data source voltage (VDAT_SRC) is sourced onto DP0 and sunk from DM0. 1 = Data source voltage (VDAT_SRC) is sourced onto DM0 and sunk from DP0. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: N/A HOST_TXPREEMPPULS ETUNE [10] RW HS Transmitter Pre-Emphasis Duration Control Function: This signal controls the duration for which the HS pre-emphasis current is sourced onto DP0 or DM0. The HS Transmitter pre-emphasis duration is defined in terms of unit amounts. One unit of pre- emphasis duration is approximately 580 ps and is defined as 1X pre-emphasis duration. This signal is valid only if either TXPREEMPAMPTUNE0[1] orTXPREEMPAMPTUNE0[0] is set to 1'b1. 0 (design default) = 2X, long pre-emphasis current duration 1 = 1X, short pre-emphasis current duration If TXPREEMPPULSETUNE0 is not used, set it to 1'b0. Voltage Range: 0 V-DVDD Active State: N/A cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-89 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value HOST_TXPREEMPAMPT UNE [9:8] RW HS Transmitter Pre-Emphasis Current Control Function: This signal controls the amount of current sourced to DP0 andDM0 after a J-to-K or K-to-J transition. The HS Transmitter pre-emphasis current is defined in terms of unit amounts. One unit amount is approximately 600 μA and is defined as 1X pre- emphasis current. 00 = HS Transmitter pre-emphasis is disabled. 01 (design default) = HS Transmitter pre-emphasis circuit sources 1Xpre-emphasis current. 10 = HS Transmitter pre-emphasis circuit sources 2X pre-emphasis current. 11 = HS Transmitter pre-emphasis circuit sources 3X pre-emphasis current. If these signals are not used, set them to 2'b00. Voltage Range: 0 V-DVDD Active State: N/A HOST_TXRESTUNE [7:6] RW USB Source Impedance Adjustment Function: In some applications, there can be significant series resistance on the D+ and D- paths between the transceiver and cable. This bus adjusts the driver source impedance to compensate for added series resistance on the USB. NOTE: Any setting other than the default can result in source impedance variation across process, voltage, and temperature conditions that does not meet USB 2.0 specification limits. 00 = Source impedance is increased by approximately 1.5 . 01 = Design default 10 = Source impedance is decreased by approximately 2 . 11 = Source impedance is decreased by approximately 4 . If this bus is not used, leave it at the default setting. Voltage Range: 0 V-DVDD Active State: N/A HOST_TXRISETUNE [5:4] RW HS Transmitter Rise/Fall Time Adjustment Function: This bus adjusts the rise/fall times of the high-speed waveform. 00 = – 10% 01 = – Design default 10 = + 15 11 = + 20% If this bus is not used, leave it at the default setting. Voltage Range: 0 V-DVDD cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-90 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Active State: N/A HOST_TXVREFTUNE [3:0] RW HS DC Voltage Level Adjustment Function: This bus adjusts the high-speed DC level voltage. 0000: – 6 % 0001: – 4 % 0010: – 2 % 0011: Design default 0100: + 2 % 0101: + 4 % 0101: + 4 % 0110: + 6 % 0111: + 8 % 1000: + 10 % 1001: + 12 % 1010: + 14 % 1011: + 16 % 1100: + 18 % 1101: + 20 % 1110: + 22 % 1111: + 24 % Voltage Range: 0 V-DVDD Active State: N/A

4.9.1.2.12 TIEOFFREG11

 Base Address: 0xC001_0000  Address = Base Address + 102C, Reset Value = 0x0F3A_202B Name Bit Type Description Reset Value RSVD [31] – Reserved 0 OTG_NX_RF1_EMAW [30:29] RW USB2.0 OTG SRAM EMAW value 0 OTG_NX_RF1_EMA [28:26] RW USB2.0 OTG SRAM EMAW value 3 OTG_NSLEEP [25] RW Sleep off OTG RAM 1 OTG_NPOWERDOWN [24] RW Power down off OTG RAM 1 HOST_HSIC_TXSRTUN E [23:20] RW TXSRTUNE value of HSIC PHY 3 HOST_HSIC_TXRPDTU NE [19:18] RW TXRPDTUNE value of HSIC PHY 2 HOST_HSIC_TXRPUTU NE [17:16] RW TXRPUTUNE value of HSIC PHY 2 HOST_HSIC_TXBITSTU FFENH [15] RW High-Byte Transmit Bit-Stuffing Enable Function: This controller signal controls bit stuffing on DATAINH0[7:0] whenOPMODE0[1:0] = 2'b11. 0 = Bit stuffing is disabled. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-91 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 1 = Bit stuffing is enabled. Voltage Range: 0 V-DVDD Active State: High HOST_HSIC_TXBITSTU FFEN [14] RW Low-Byte Transmit Bit-Stuffing Enable Function: This controller signal controls bit stuffing on DATAIN0[7:0] whenOPMODE0[1:0] = 2'b11. 0 = Bit stuffing is disabled. 1 = Bit stuffing is enabled. Voltage Range: 0 V-DVDD Active State: High HOST_HSIC_WORDINT ERFACE [13] RW UTMI+ Data Bus Width and Clock Select Function: This controller signal selects the data bus width of the UTMI+ data buses. 0 = 8-bit data interface (PHYCLOCK0 frequency is 60 MHz) 1 = 16-bit data interface (PHYCLOCK0 frequency is The USB 2.0 picoPHY supports 8/16-bit data interfaces for all valid USB 2.0picoPHY speed modes. This signal is a strapping option that must be set prior to a power-on reset and remain static during normal operation. Strapping options are not critical for STA, and any other timings or loading limits for the pin are specified in the .lib timing model included in the product deliverables. Voltage Range: 0 V-DVDD Active State: N/A HOST_HSIC_WORDINT ERFACE_ENB [12] RW Use Tieoff register value instead of controller value 0 HOST_HSIC_XCVRSEL ECT [11] RW XCVRSELECT value of HSIC PHY 0 HOST_HSIC_XCVRSEL ECT_ENB [10] RW Enable HOST_HSIC_XCVRSELECT register 0 HOST_HSIC_OPMODE [9:8] RW UTMI+ Operational Mode Function: This controller bus selects the UTMI+ operational mode. 00 = Normal 01 = Non-Driving 10 = Disable bit stuffing and NRZI encoding 11 = Normal operation without SYNC or EOP generation. If the XCVRSEL0[1:0]bus is not set to 2'b00 while OPMODE0[1:0] is set to 2'b11, USB 2.0 picoPHY behavior is undefined. NOTE: To perform battery charging, the USB 2.0 picoPHY must be placed in Non-Driving mode. Voltage Range: 0 V-DVDD cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-92 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Active State: N/A HOST_HSIC_OPMODE_ ENB [7] RW Use Tieoff register value instead of controller value 0 HOST_HSIC_MSTRXOP U [6] RW MSTRXOPU value of HSIC PHY 0 HOST_HSIC_SLEEPM [5] RW Sleep Assertion Function: Asserting this signal places the USB 2.0 picoPHY in Sleep mode according to the USB 2.0 Link Power Management (LPM) addendum to the USB2.0 specification. In Sleep Mode, the transmitter is tri- stated and the USB 2.0picoPHY circuits are powered down except for the XO block If the reference clock is a crystal, the XO block remains powered when the USB 2.0 picoPHY is placed in Sleep mode. 0 = Sleep mode 1 = Normal operating mode If SUSPENDM0 is set to 1'b0, the USB 2.0 picoPHY will remain in Suspend mode irrespective of the SLEEPM0 setting. If the LPM function is not required, SLEEPM0 must be tied to DVDD. USB 2.0picoPHY Sleep mode can be overridden using the test interface. Voltage Range: 0 V-DVDD Active State: Low HOST_HSIC_SLEEPM_ ENB [4] RW Use Tieoff register value instead of controller value 0 HOST_HSIC_SUSPEND M [3] RW Suspend Assertion Function: Asserting this signal suspends the USB 2.0 picoPHY by tri-stating the transmitter and powering down the USB 2.0 picoPHY circuits. 0 = Suspend mode 1 = Normal operating mode USB 2.0 picoPHY power-down behavior can be overridden using the test interface. Voltage Range: 0 V-DVDD Active State: Low HOST_HSIC_SUSPEND M_ENB [2] RW Use Tieoff register value instead of controller value 0 HOST_HSIC_DMPULLD OWN [1] RW D- Pull-Down Resistor Enable Function: This controller signal controls the pull-down resistance on the D- line. 0 = The pull-down resistance on D- is disabled. 1 = The pull-down resistance on D- is enabled. When an A/B device is acting as a host (downstream- facing port),DPPULLDOWN0 and DMPULLDOWN0 are enabled. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-93 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value NOTE: UTMI+/OTG-compliant controllers are not allowed to toggleDPPULLDOWN0 and DMPULLDOWN0 during normal operation. Voltage Range: 0 V-DVDD Active State: High HOST_HSIC_DPPULLD OWN [0] RW D+ Pull-Down Resistor Enable Function: This controller signal controls the pull-down resistance on the D+ line. 0 = The pull-down resistance on D+ is disabled. 1 = The pull-down resistance on D+ is enabled. When an A/B device is acting as a host (downstream- facing port),DPPULLDOWN0 and DMPULLDOWN0 are enabled. NOTE: UTMI+/OTG-compliant controllers are not allowed to toggleDPPULLDOWN0 and DMPULLDOWN0 during normal operation. Voltage Range: 0 V-DVDD Active State: High

4.9.1.2.13 TIEOFFREG12

 Base Address: 0xC001_0000  Address = Base Address + 1030, Reset Value = 0x0000_0001 Name Bit Type Description Reset Value OTG_SOF_COUNT [31:18] RW SOF Input Count Function: Wireless USB Wire Adapter (DWA) application Values:  Wireless USB Device Wire Adapter (DWA) application: Input value to be loaded into Host Frame Number/Frame Time Remaining Register (HFNUM) field FrNum.  Non-Wireless USB application: Must be tied to 0. This signal is not present when parameter OTG_RM_OPT_FEATURES = Yes. Active State: High OTG_GP_IN [17:2] RW General Purpose Input Port Function: Can be used as general purpose inputs. This bus is not present when parameter OTG_RM_OPT_FEATURES = Yes. Active State: High OTG_SS_SCALEDOWN _MODE [1:0] RW Scale-Down Mode Function:  When this signal is enabled during simulation, the cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-94 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value core uses scaled-down timing values, resulting in faster simulations.  When it is disabled, actual timing values are used. NOTE: This signal must be disabled during synthesis. This strap signal is tied to one static value. Values: 2'b00: Disables all scale-downs. Actual timing values are used. Required for synthesis. 2'b01: Enables scale-down of all timing values except Device mode suspend and resume. These include: Speed enumeration. HNP/SRP. Host mode suspend and resume. 2'b10: Enables scale-down of Device mode suspend and resume timing values only. 2'b11: Enables bit 0 and bit 1 scale-down timing values. Active State: N/A

4.9.1.2.14 TIEOFFREG13

 Base Address: 0xC001_0000  Address = Base Address + 1034, Reset Value = 0xA000_6D00 Name Bit Type Description Reset Value OTG_SLEEPM [31] RW Sleep Assertion Function: Asserting this signal places the USB 2.0 picoPHY in Sleep mode according to the USB 2.0 Link Power Management (LPM) addendum to the USB2.0 specification. In Sleep Mode, the transmitter is tri- stated and the USB 2.0picoPHY circuits are powered down except for the XO block If the reference clock is a crystal, the XO block remains powered when the USB 2.0 picoPHY is placed in Sleep mode. 0 = Sleep mode 1 = Normal operating mode If SUSPENDM0 is set to 1'b0, the USB 2.0 picoPHY will remain in Suspend mode irrespective of the SLEEPM0 setting. If the LPM function is not required, SLEEPM0 must be tied to DVDD. USB 2.0picoPHY Sleep mode can be overridden using the test interface. Voltage Range: 0 V-DVDD Active State: Low OTG_SLEEPM_ENB [30] RW Use Tieoff register value instead of controller value 0 OTG_SUSPENDM [29] RW Suspend Assertion 1 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-95 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Function: Asserting this signal suspends the USB 2.0 picoPHY by tri-stating the transmitter and powering down the USB 2.0 picoPHY circuits. 0 = Suspend mode 1 = Normal operating mode USB 2.0 picoPHY power-down behavior can be overridden using the test interface. Voltage Range: 0 V-DVDD Active State: Low OTG_SUSPENDM_ENB [28] RW Use Tieoff register value instead of controller value 0 OTG_DMPULLDOWN [27] RW D- Pull-Down Resistor Enable Function: This controller signal controls the pull-down resistance on the D- line. 0 = The pull-down resistance on D- is disabled. 1 = The pull-down resistance on D- is enabled. When an A/B device is acting as a host (downstream- facing port), DPPULLDOWN0 and DMPULLDOWN0 are enabled. NOTE: UTMI+/OTG-compliant controllers are not allowed to toggleDPPULLDOWN0 and DMPULLDOWN0 during normal operation. Voltage Range: 0 V-DVDD Active State: High OTG_DPPULLDOWN [26] RW D+ Pull-Down Resistor Enable Function: This controller signal controls the pull-down resistance on the D+ line. 0 = The pull-down resistance on D+ is disabled. 1 = The pull-down resistance on D+ is enabled. When an A/B device is acting as a host (downstream- facing port), DPPULLDOWN0 and DMPULLDOWN0 are enabled. NOTE: UTMI+/OTG-compliant controllers are not allowed to toggleDPPULLDOWN0 and DMPULLDOWN0 during normal operation. Voltage Range: 0 V-DVDD Active State: High OTG_VBUSVLDEXTSEL [25] RW External VBUS Valid Select Function: This signal selects either the VBUSVLDEXT0 input or the internal Session Valid comparator to generate the OTGSESSVLD0 output. To avoid potential glitches in DP0, VBUSVLDEXTSEL0 must be static prior to a power- on reset and remain static during normal operation. The OTGSESSVLD0 signal, in conjunction with XCVRSEL0[1:0],OPMODE0[1:0], TERMSEL0, DPPULLDOWN0, and DMPULLDOWN0,control the DP0 pull-up resistor. If VBUSVLDEXT0 and the cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-96 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value internal Session Valid comparator output are asserted, and VBUSEXTSEL0changes, it is possible for OTGSESSVLD0 to glitch low, causing the DP0resistor to be temporarily disabled. 0 = The internal Session Valid comparator is used to generateOTGSESSVLD0 and assert the DP0 pull-up resistor. 1 = The VBUSVLDEXT0 input is used to generate OTGSESSVLD0 and assert the DP0 pull-up resistor. This signal is not critical for STA, and any other timings or loading limits for the pin are specified in the .lib timing model included in the product deliverables. Voltage Range: 0 V-DVDD Active State: High OTG_VBUSVLDEXT [24] RW External VBUS Valid Indicator Function: This signal is valid in Device mode and only when theVBUSVLDEXTSEL0 signal is set to 1'b1. VBUSVLDEXT0 indicates whether the VBUS signal on the USB cable is valid. In addition, VBUSVLDEXT0 enables the pull-up resistor on the D+ line. 0 = The VBUS signal is not valid, and the pull-up resistor on D+ is disabled. 1 = The VBUS signal is valid, and the pull-up resistor on D+ is enabled. In Host mode, this input is not used and can be tied to 1'b0. Voltage Range: 0 V-DVDD Active State: N/A OTG_ADPPRBENB [23] RW ADP Probe Enable Function: Enables/disables the ADP Probe comparator. 0 = ADP Probe comparator is disabled. 1 = ADP Probe comparator is enabled. If this signal is not used, tie it to 1'b0. Voltage Range: 0 V-DVDD Active State: High OTG_ADPDISCHRG [22] RW VBUS Input ADP Discharge Enable Function: Controls discharging the VBUS input during ADP. 0 = Disables discharging VBUS during ADP. 1 = Enables discharging VBUS during ADP. If this signal is not used, tie it to 1'b0. Voltage Range: 0 V-DVDD Active State: High OTG_ADPCHRG [21] RW VBUS Input ADP Charge Enable 0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-97 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Function: Controls charging the VBUS input during ADP. 0 = Disables charging VBUS during ADP. 1 = Enables charging VBUS during ADP. If this signal is not used, tie it to 1'b0. Voltage Range: 0 V-DVDD Active State: High OTG_DRVVBUS [20] RW Drive VBUS Function: This controller signal controls the VBUS Valid comparator. This signal drives 5 V on VBUS through an external charge pump. When OTGDISABLE0 is set to 1'b0 and DRVVBUS0 is asserted, the Band gap circuitry and VBUS Valid comparator are powered, even in Suspend or Sleep mode. 0 = The VBUS Valid comparator is disabled. 1 = The VBUS Valid comparator is enabled. Voltage Range: 0 V-DVDD Active State: High OTG_IDPULLUP [19] RW Analog ID Input Sample Enable Function: This controller signal controls ID line sampling. 0 = ID pin sampling is disabled, and the IDDIG0 output is not valid. 1 = ID pin sampling is enabled, and the IDDIG0 output is valid. Voltage Range: 0 V-DVDD Active State: High OTG_LOOPBACKENB [18] RW Loopback Test Enable Function: This signal places the USB 2.0 picoPHY in Loopback mode, which enables the receive and transmit logic concurrently. 0 = During data transmission, the receive logic is disabled. 1: During data transmission, the receive logic is enabled. NOTE: Loopback mode is for test purposes only; it cannot be used for normal operation. In normal operation, tie this signal low. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High OTG_OTGDISABLE [17] RW OTG Block Disable Function: This signal powers down the VBUS Valid comparator, but not the Session Valid comparator, ADP probe and sense comparators, nor the ID cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-98 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value detection circuitry. To save power, if the application does not use the OTG function, this input can be set high. 0 = The OTG block is powered up. 1 = The OTG block is powered down. Voltage Range: 0 V-DVDD Active State: High OTG_PORTRESET [16] RW Per-Port Reset Function: When asserted, this signal resets the corresponding port's transmit and receive logic without disabling the clocks within the USB 2.0 picoPHY. 0 = The transmit and receive FSMs are operational, and the line_state logic becomes sequential after 11 PHYCLOCK0 cycles. 1 = The transmit and receive finite state machines (FSMs) are reset, and the line_state logic combinatorially reflects the state of the single-ended receivers. Asserting PORTRESET0 does not override any USB 2.0 picoPHY inputs that normally control the USB state, nor does it cause any transient, illegal USB states. Within 100 ns of asserting PORTRESET0, the controller must set the inputs that control the USB to values that cause a safe state. A safe state for Host and Device modes is defined as follows:  Host mode: Non-driving (OPMODE0[1:0] = 2'b01) with the 15 k pull-down resistors enabled (DPPULLDOWN0 and DMPULLDOWN0 = 1'b1)  Device mode: Non-driving (OPMODE0[1:0] = 2'b01) with the 1.5 k pull-up resistor disabled Voltage Range: 0 V-DVDD Active State: High OTG_RESREQIN [15] RW Reserved Function: Reserved. Tie this pin to 1'b0. Voltage Range: 0 V-DVDD OTG_COMMONONN [14] RW Common Block Power-Down Control Function: This signal controls the power-down signals in the XO, Bias, and PLL blocks when the USB 2.0 picoPHY is in Suspend, or Sleep mode. 0 = In Suspend mode, the XO, Bias, and PLL blocks remain powered in Suspend mode. In Sleep mode, if the reference clock is a crystal, the XO block remains powered. 1 = In Suspend mode, the XO, Bias, and PLL blocks are powered down. In Sleep mode, the Bias and PLL cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-99 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value blocks are powered down. This signal is a strapping option that must be set prior to a power-on reset and remain static during normal operation. Strapping options are not critical for STA, and any other timings or loading limits for the pin are specified in the .lib timing model included in the product deliverables. NOTE: 1. If COMMONONN is set low, CLK48MOHCI and CLK480M remain available in Suspend or UART/Auto resume mode. 2. If the reference clock source is a crystal, CLK12MOHCI remains available in Suspend or UART/Auto resume mode, only if COMMONONN is set to 1'b0. 3. If the reference clock source is either an external clock (connected to XO) or CLKCORE, CLK12MOHCI will continue to pulse in Suspend or UART/Auto resume mode, even when COMMONONN is set to 1'b1. 4. In Sleep mode, CLK48MOHCI and CLK12MOHCI are always available, irrespective of COMMONONN. Voltage Range: 0 V-DVDD Active State: Low OTG_FSEL [13:11] RW Reference Clock Frequency Select Function: Selects the USB 2.0 picoPHY reference clock frequency. 000 = 9.6 MHz 001 = 10 MHz 010 = 12 MHz 011 = 19.2 MHz 100 = 20 MHz 101 = 24 MHz 110 = Reserved 111 = 50 MHz Voltage Range: 0 V-DVDD Active State: N/A OTG_REFCLKSEL [10:9] RW Reference Clock Select for PLL Block Function: This signal selects the reference clock source for the PLL block. 00 = The XO block uses the clock from a crystal. 01 = The XO block uses an external, 1.8-V clock supplied on the XO pin. 10 = The PLL uses CLKCORE as reference. 11 = Reserved This bus is a strapping option that must be set prior to a power-on reset and remain static during normal cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-100 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value operation. Strapping options are not critical for STA, and any other timings or loading limits for the pin are specified in the .lib timing model included in the product deliverables. Voltage Range: 0 V-DVDD Active State: N/A OTG_POR [8] RW Power-On Reset Function: This signal resets all test registers and state machines in the USB 2.0picoPHY. The POR signal must be asserted for a minimum of 10 μs. Voltage Range: 0 V-DVDD Active State: High OTG_POR_ENB [7] RW Use Tieoff register value instead of controller value 0 OTG_VATESTENB [6:5] RW Analog Test Pin Select Function: Enables analog test voltages to be placed on either the ANALOGTEST or ID0 pin. 00 = Analog test voltages cannot be viewed or applied on either ANALOGTEST or ID0. 01 = Analog test voltages can be viewed or applied on ID0. 10 = Analog test voltages can be viewed or applied on ANALOGTEST. 11 = Reserved. Invalid setting. If this bus is not used, tie these inputs low. Voltage Range: 0 V-DVDD Active State: N/A OTG_SIDDQ [4] RW IDDQ Test Enable Function: This test signal enables you to perform IDDQ testing by powering down all analog blocks. Before asserting SIDDQ, ensure that VDATSRCENB0, VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0, and TESTBURNIN are set to 1'b0. 0 = The analog blocks are powered up. 1 = The analog blocks are powered down. If this signal is not used, tie it low. Voltage Range: 0 V-DVDD Active State: High OTG_NUTMIRESETSYN C [3] RW Reset off utmi clock of OTG LINK 0 OTG_NRESETSYNC [2] RW Reset off OTG LINK 0 OTG_IF_SELECT_HSIC [1] RW HSIC Interface Select Function: Used to select the HSIC mode of operation. Indicates that the HSIC interface is selected. The core cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-101 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value starts to connect/operate in HSIC mode when the GLPMCFG. HSICCon is programmed to 1, if GLPMCFG. InvSelHsic = 0. Active State: High OTG_SYS_DMA_DONE [0] RW System DMA Done Function: This signal should be asserted when the DATA write is completed in the System Memory. It should be asserted for one AHB clock cycle synchronous to hclk. The signal is valid only when RMS is enabled. Values: 0 = Data write not complete. 1 = Data Write complete in the system memory for the current DMA write-transferfrom HS OTG Active State: High

4.9.1.2.15 TIEOFFREG14

 Base Address: 0xC001_0000  Address = Base Address + 1038, Reset Value = 0x3E38_0200 Name Bit Type Description Reset Value OTG_TXFSLSTUNE [31:28] RW FS/LS Source Impedance Adjustment Function: This bus adjusts the low- and full-speed single-ended source impedance while driving high. The following adjustment values are based on nominal process, voltage, and temperature. 0000 = +5 % 0001 = +2.5 % 0011 = Design default 0111 = –2.5 % 1111 = –5 % All other bit settings are reserved. Voltage Range: 0 V-DVDD Active State: N/A OTG_TXHSXVTUNE [27:26] RW Transmitter High-Speed Crossover Adjustment Function: This bus adjusts the voltage at which the DP0 and DM0 signals cross while transmitting in HS mode. 00 = Reserved 01 = –15 mV 10 = +15 mV 11 = Default setting Voltage Range: 0 V-DVDD Active State: N/A OTG_OTGTUNE [25:23] RW VBUS Valid Threshold Adjustment 4 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-102 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Function = This bus adjusts the voltage level for the VBUS Valid threshold. 000 = –12 % 001 = –9 % 010 = –6 % 011 = –3 % 100 = Design default 101 = +3 % 110 = +6 % If this bus is not used, leave it at the default setting. Voltage Range: 0 V-DVDD Active State: N/A OTG_SQRXTUNE [22:20] RW Squelch Threshold Adjustment Function = This bus adjusts the voltage level for the threshold used to detect valid high-speed data. 000 = +15 % 001 = +10 % 010 = +5 % 011 = Design default 100 = –5 % 101 = –10 % 110 = –15 % 111 = –20 % Voltage Range: 0 V-DVDD Active State: N/A OTG_COMPDISTUNE [19:17] RW Disconnect Threshold Adjustment Function = This bus adjusts the voltage level for the threshold used to detect a disconnect event at the host. 000 = –6 % 001 = –4.5 % 010 = –3 % 011 = –1.5 % 100 = Design default 101 = +1.5 % 110 = +3 % 111 = +4.5 % If this bus is not used, leave it at the default setting. Voltage Range: 0 V-DVDD Active State: N/A OTG_BYPASSSEL [16] RW Transmitter Digital Bypass Select Function: Enables/disables Transmitter Digital Bypass mode. 0 = Transmitter Digital Bypass mode is disabled. 1 = Transmitter Digital Bypass mode is enabled. If Transmitter Digital Bypass mode is not used, tie this input to 1'b0. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-103 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Voltage Range: 0 V-DVDD Active State: High OTG_BYPASSDMEN [15] RW DM0 Transmitter Digital Bypass Enable Function: Enables/disables the DM0 FS/LS driver in Transmitter Digital Bypass mode. 0 = DM0 FS/LS driver is disabled in Transmitter Digital Bypass mode. 1 = DM0 FS/LS driver is enabled and driven with the BYPASSDPDATA0 signal. If Transmitter Digital Bypass mode is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High OTG_BYPASSDPEN [14] RW DP0 Transmitter Digital Bypass Enable Function: Enables/disables the DP0 FS/LS driver in Transmitter Digital Bypass mode. 0 = DP0 FS/LS driver is disabled in Transmitter Digital Bypass mode. 1 = DP0 FS/LS driver is enabled and driven with the BYPASSDPDATA0 signal. If Transmitter Digital Bypass mode is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High OTG_BYPASSDMDATA [13] RW Data for DM0 Transmitter Digital Bypass Function: In Transmitter Digital Bypass mode, this signal provides the data that is transmitted on DM0. 0 = DM0 FS/LS driver drives to a low state. 1 = DM0 FS/LS driver drives to a high state. If Transmitter Digital Bypass mode is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: N/A OTG_BYPASSDPDATA [12] RW Data for DP0 Transmitter Digital Bypass Function: In Transmitter Digital Bypass mode, this signal provides the data that is transmitted on DP0. 0 = DP0 FS/LS driver drives to a low state. 1 = DP0 FS/LS driver drives to a high state. If Transmitter Digital Bypass mode is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: N/A OTG_TXBITSTUFFENH [11] RW High-Byte Transmit Bit-Stuffing Enable Function: This controller signal controls bit stuffing on DATAINH0[7:0] whenOPMODE0[1:0] = 2'b11. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-104 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 0 = Bit stuffing is disabled. 1 = Bit stuffing is enabled. Voltage Range: 0 V-DVDD Active State: High OTG_TXBITSTUFFEN [10] RW Low-Byte Transmit Bit-Stuffing Enable Function: This controller signal controls bit stuffing on DATAIN0[7:0] whenOPMODE0[1:0] = 2'b11. 0 = Bit stuffing is disabled. 1 = Bit stuffing is enabled. Voltage Range: 0 V-DVDD Active State: High OTG_WORDINTERFAC E [9] RW UTMI+ Data Bus Width and Clock Select Function: This controller signal selects the data bus width of the UTMI+ data buses. 0 = 8-bit data interface (PHYCLOCK0 frequency is 60 MHz) 1 = 16-bit data interface (PHYCLOCK0 frequency is The USB 2.0 picoPHY supports 8/16-bit data interfaces for all valid USB 2.0picoPHY speed modes. This signal is a strapping option that must be set prior to a power-on reset and remain static during normal operation. Strapping options are not critical for STA, and any other timings or loading limits for the pin are specified in the .lib timing model included in the product deliverables. Voltage Range: 0 V-DVDD Active State: N/A OTG_WORDINTERFAC E_ENB [8] RW Use Tieoff register value instead of controller value 0 OTG_XCVRSEL [7:6] RW Transceiver Select Function: This controller bus selects the HS, FS, or LS Transceiver. 00 = HS Transceiver 01 = FS Transceiver 10 = LS Transceiver 11 = Sends an LS packet on an FS bus or receives an LS packet. NOTE: Due to the power-up time required by the HS Transmitter, the controller must not transmit a high- speed packet within 1.6 μs after switching XCVRSEL0[1:0] to HS Transceiver (from any other setting). Voltage Range: 0 V-DVDD Active State: N/A OTG_XCVRSEL_ENB [5] RW Use Tieoff register value instead of controller value 0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-105 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value OTG_TERMSEL [4] RW USB Termination Select Function: This controller signal sets the USB 2.0 picoPHY's terminations to FS orHS. 0 = High-speed terminations are enabled. 1 = Full-speed terminations are enabled. NOTE: Four PHYCLOCK0 cycles are required for internal synchronous reset generation, and an additional six cycles are required to enable HS terminations in the digital core. Therefore, the controller must not transmit a high-speed packet within 10 PHYCLOCK0 cycles after switching TERMSEL0 to 1'b0. Voltage Range: 0 V-DVDD Active State: N/A OTG_TERMSEL_ENB [3] RW Use Tieoff register value instead of controller value 0 OTG_OPMODE [2:1] RW UTMI+ Operational Mode Function: This controller bus selects the UTMI+ operational mode. 00 = Normal 01 = Non-Driving 10 = Disable bit stuffing and NRZI encoding 11 = Normal operation without SYNC or EOP generation. If the XCVRSEL0[1:0]bus is not set to 2'b00 while OPMODE0[1:0] is set to 2'b11, USB 2.0 picoPHY behavior is undefined. NOTE: To perform battery charging, the USB 2.0 picoPHY must be placed in Non-Driving mode. Voltage Range: 0 V-DVDD Active State: N/A OTG_OPMODE_ENB [0] RW Use Tieoff register value instead of controller value 0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-106 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.16 TIEOFFREG15

 Base Address: 0xC001_0000  Address = Base Address + 103C, Reset Value = 0x3FC0_0153 Name Bit Type Description Reset Value RSVD [31:30] – Reserved 0 CODA960_NSLEEP00 [29:26] RW CODA960 SRAM group 0 retention (low active) F CODA960_NPWRDN00 [25:22] RW CODA960 SRAM group 0 Power Down F OTG_GLITCHLESSMUX CNTRL [21] RW Select glitch less mux of OTG suspend clock 0 OTG_LPMCLKMUXCNT RL [20] RW 0 OTG_DRVVBUS_ENB [19] RW Use Tieoff register value instead of controller value 0 OTG_DMPULLDOWN_E NB [18] RW Use Tieoff register value instead of controller value 0 OTG_DPPULLDOWN_E NB [17] RW Use Tieoff register value instead of controller value 0 OTG_IDPULLUP_ENB [16] RW Use Tieoff register value instead of controller value 0 OTG_ACAENB [15] RW ACA ID_OTG Pin Resistance Detection Enable Function: Enables detection of resistance on the ID_OTG pin of an ACA. 0 = Disables detection of resistance on the ID_OTG pin of an ACA. 1 = Enables detection of resistance on the ID_OTG pin of an ACA. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High OTG_DCDENB [14] RW Data Contact Detection Enable Function: Enables current sourcing on the D+ line and pull-down resistance on the D- line for Data Contact Detect (DCD). 0 = IDP_SRC current is disabled, pull-down resistance on DM0 is disabled. 1 = IDP_SRC current is sourced onto DP0, pull-down resistance on DM0 is enabled. NOTE: During USB 2.0 picoPHY normal operation, set this signal low. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High OTG_VDATSRCENB [13] RW Battery Charging Sourcing Select Function: Enables or disables sourcing for battery charging. 0 = Data source voltage (VDAT_SRC) is disabled. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-107 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 1 = Data source voltage (VDAT_SRC) is enabled. During USB 2.0 picoPHY normal operation, set this signal low. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High OTG_VDATDETENB [12] RW Battery Charging Attach/Connect Detection Enable Function: Enables or disables attach/connect detection. 0 = Data detect voltage (CHG_DET) is disabled. 1 = Data detect voltage (CHG_DET) is enabled. During USB 2.0 picoPHY normal operation, set this signal low. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: High OTG_CHRGSEL [11] RW Battery Charging Source Select Function: Determines whether current is sourced onto or sunk from DP0 or DM0. 0 = Data source voltage (VDAT_SRC) is sourced onto DP0 and sunk from DM0. 1 = Data source voltage (VDAT_SRC) is sourced onto DM0 and sunk from DP0. If this signal is not used, tie this input to 1'b0. Voltage Range: 0 V-DVDD Active State: N/A OTG_TXPREEMPPULS ETUNE [10] RW HS Transmitter Pre-Emphasis Duration Control Function: This signal controls the duration for which the HS pre-emphasis current is sourced onto DP0 or DM0. The HS Transmitter pre-emphasis duration is defined in terms of unit amounts. One unit of pre- emphasis duration is approximately 580 ps and is defined as 1X pre-emphasis duration. This signal is valid only if either TXPREEMPAMPTUNE0[1] orTXPREEMPAMPTUNE0[0] is set to 1'b1. 0 (design default) = 2X, long pre-emphasis current duration 1 = 1X, short pre-emphasis current duration If TXPREEMPPULSETUNE0 is not used, set it to 1'b0. Voltage Range: 0 V-DVDD Active State: N/A OTG_TXPREEMPAMPT UNE [9:8] RW HS Transmitter Pre-Emphasis Current Control Function: This signal controls the amount of current sourced to DP0 andDM0 after a J-to-K or K-to-J transition. The HS Transmitter pre-emphasis current is cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-108 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value defined in terms of unit amounts. One unit amount is approximately 600μA and is defined as 1X pre- emphasis current. 00 = HS Transmitter pre-emphasis is disabled. 01 (design default) = HS Transmitter pre-emphasis circuit sources 1Xpre-emphasis current. 10 = HS Transmitter pre-emphasis circuit sources 2X pre-emphasis current. 11 = HS Transmitter pre-emphasis circuit sources 3X pre-emphasis current. If these signals are not used, set them to 2'b00. Voltage Range: 0 V-DVDD Active State: N/A OTG_TXRESTUNE [7:6] RW USB Source Impedance Adjustment Function: In some applications, there can be significant series resistance on the D+ and D- paths between the transceiver and cable. This bus adjusts the driver source impedance to compensate for added series resistance on the USB. Note: Any setting other than the default can result in source impedance variation across process, voltage, and temperature conditions that does not meet USB 2.0 specification limits. 00 = Source impedance is increased by approximately 1.5 . 01 = Design default 10 = Source impedance is decreased by approximately 2 . 11 =: Source impedance is decreased by approximately 4 . If this bus is not used, leave it at the default setting. Voltage Range: 0 V-DVDD Active State: N/A OTG_TXRISETUNE [5:4] RW HS Transmitter Rise/Fall Time Adjustment Function: This bus adjusts the rise/fall times of the high-speed waveform. 00 = –10 % 01 = –Design default 10 = + 15 % 11 = + 20 % If this bus is not used, leave it at the default setting. Voltage Range: 0 V-DVDD Active State: N/A OTG_TXVREFTUNE [3:0] RW HS DC Voltage Level Adjustment Function: This bus adjusts the high-speed DC level voltage. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-109 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 0000 = –6 % 0001 = –4 % 0010 = –2 % 0011 = Design default 0100 = +2 % 0101 = +4 % 0110 = +6 % 0111 = +8 % 1000 = +10 % 1001 = +12 % 1010 = +14 % 1011 = +16 % 1100 = +18 % 1101 = +20 % 1110 = +22 % 1111 = +24 % Voltage Range: 0 V-DVDD Active State: N/A

4.9.1.2.17 TIEOFFREG16

 Base Address: 0xC001_0000  Address = Base Address + 0x1040, Reset Value = 0x00FF_FFFF Name Bit Type Description Reset Value RSGVD [31:26] – Reserved 0 CODA960_nPWRDN02 [25:16] RW CODA960 SRAM group2 Power down(low active) FF CODA960_nSLEEP01 [15:8] RW CODA960 SRAM group 1 retention (low active) FF CODA960_nPWRDN01 [7:0] RW CODA960 SRAM group 1 power down(low active) FF

4.9.1.2.18 TIEOFFREG17

 Base Address: 0xC001_0000  Address = Base Address + 0x1044, Reset Value = 0x3FFF_FFFF Name Bit Type Description Reset Value RSVD [31:30] – Rserved 0 CODA960_nSLEEP04 [29:23] RW CODA960 SRAM group 4 retention (low active) FF CODA960_nPWRDN04 [21:14] RW CODA960 SRAM group 4 Power down(low active) FF CODA960_nSLEEP03 [13:12] RW CODA960 SRAM group 3 retention (low active) 3 CODA960_nPWRDN03 [11:10] RW CODA960 SRAM group 3 Power down(low active) 3 CODA960_nSLEEP02 [9:0] RW CODA960 SRAM group 2 retention (low active) 3FF cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-110 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.19 TIEOFFREG18

 Base Address: 0xC001_0000  Address = Base Address + 0x1048, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value CODA960_nPWRDN07 [31:20] RW CODA960 SRAM group 7 power down(low active) FFF CODA960_nSLEEP06 [19:13] RW CODA960 SRAM group 6 retention (low active) 7F CODA960_nPWRDN06 [12:6] RW CODA960 SRAM group 6 power down(low active) 7F CODA960_nSLEEP05 [5:3] RW CODA960 SRAM group 5 retention (low active) 7 CODA960_nPWRDN05 [2:0] RW CODA960 SRAM group 5 power down(low active) 7

4.9.1.2.20 TIEOFFREG19

 Base Address: 0xC001_0000  Address = Base Address + 0x104C, Reset Value = 0x0FFF_FFFF Name Bit Type Description Reset Value RSVD [31:28] – 0 CODA960_nPWRDN10 [27:18] RW CODA960 SRAM group 10 power down (low active) 3FF CODA960_nSLEEP09 [17:16] RW CODA960 SRAM group 9 retention (low active) 3 CODA960_nPWRDN09 [15:14] RW CODA960 SRAM group 9 power down (low active) 3 CODA960_nSLEEP08 [13] RW CODA960 SRAM group 8 retention (low active) 1 CODA960_nPWRDN08 [12] RW CODA960 SRAM group 8 power down (low active) 1 CODA960_nSLEEP07 [11:0] RW CODA960 SRAM group 7 retention (low active) FFF

4.9.1.2.21 TIEOFFREG20

 Base Address: 0xC001_0000  Address = Base Address + 0x1050, Reset Value = 0x1B6D_BFFF Name Bit Type Description Reset Value CODA960_ra2_EMAWA [31:30] RW CODA960 SRAM EMAW value 0 CODA960_ra2_EMAB [29:27] RW CODA960 SRAM EMAB value 3 CODA960_ra2_EMAA [26:24] RW CODA960 SRAM EMAA value 3 CODA960_rf2w_EMAB [23:21] RW CODA960 SRAM EMAB value 3 CODA960_rf2w_EMAA [20:18] RW CODA960 SRAM EMAA value 3 CODA960_rf2_EMAB [17:15] RW CODA960 SRAM EMAB value 3 CODA960_rf2_EMAA [14:12] RW CODA960 SRAM EMAA value 3 CODA960_nSLEEP11 [11] RW CODA960 SRAM group 11 retention (low active) 1 CODA960_nPWRDN11 [10] RW CODA960 SRAM group 11 power down (low active) 1 CODA960_nSLEEP10 [9:0] RW CODA960 SRAM group 10 retention (low active) 3FF cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-111 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.22 TIEOFFREG21

 Base Address: 0xC001_0000  Address = Base Address + 0x1054, Reset Value = 0x6C86_306C Name Bit Type Description Reset Value GMAC_RF2_EMAB [31:29] RW GMAC SRAM EMAB value 3 GMAC_RF2_EMAA [28:26] RW GMAC SRAM EMAA value 3 GMAC_PHY_INIF_SEL [25:23] RW PHY Interface Select Function: These pins select on of the multiple PHY interface of MAC. This is sampled only during reset assertion and ignored after that. - 000 : GMII or MII - 001 : RGMII - 010 : SGMII - 011 : TBI - 100 : RMII - 101 : RTBL - 110 : SMLL - 111 : RevVII Synchronous to : CSR clock Caution : This chip supports only RGBMII GMAC_SBD_FLOWCTL [22] RW Side band Flow Control Function : When set high, instructs the MAC to transmit Pause frames in Full-Duplex mode, In half- duplex mode, the MAC enables the backpressure function until this signal is made low again Active State: High Registered: Yes Synchronous t0: Asynchronous CODA960_rf1w_EMAW [21:20] RW CODA960 SRAM EMAW value 0 CODA960_rf1w_EMA [19:17] RW CODA960 SRAM EMA value 3 CODA960_rf1_EMAW [16:15] RW CODA960 SRAM EMAW value 0 CODA960_rf1_EMA [14:12] RW CODA960 SRAM EMA value 3 CODA960_ra2w_EMAWB [11:10] RW CODA960 SRAM EMAWB value 0 CODA960_ra2w_EMAWA [9:8] RW CODA960 SRAM EMAWA value 0 CODA960_ra2w_EMAB [7:5] RW CODA960 SRAM EMAB value 3 CODA960_ra2w_EMAA [4:2] RW CODA960 SRAM EMAA value 3 CODA960_ra2_EMAWB [1:0] RW CODA960 SRAM EMAWB value 0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-112 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.23 TIEOFFREG22

 Base Address: 0xC001_0000  Address = Base Address + 0x1058, Reset Value = 0xFFFE_18DB Name Bit Type Description Reset Value RSVD [31:17] RW Reserved 7FFF RSVD [16] RW Reserved 0 GPU_SPSRAM_BW_EMA W [15:14] RW 3D GPU SRAM EMAW value 0 GPU_SPSRAM_BW_EMA [13:11] RW 3D GPU SRAM EMA value 3 3D GPU_SPSRAM_EMAW [10:9] RW 3D GPU SRAM EMAW value 0 3D GPU_SPSRAM_EMA [8:6] RW 3D GPU SRAM EMA value 3 GPU_DPSRAM_1R1W_EM AB [5:3] RW 3D GPU SRAM EMAB value 3 GPU_DPSRAM_1R1W_EM AA [2:0] RW 3D GPU SRAM EMAA value 3 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-113 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.24 TIEOFFREG23

 Base Address: 0xC001_0000  Address = Base Address + 105C, Reset Value = Reset Value = 0x001F_FFFF Name Bit Type Description Reset Value RSVD [31:21] – Reserved 0 3D GPU_L2_NSLEEP [20:18] RW 3D GPU L2 Cache SRAM retention (low active) 7 RSVD [17:15] RW Reserved 7 3D GPU_GP_NSLEEP [14:0] RW 3D GPU GP SRAM retention (low active) 7FFF

4.9.1.2.25 TIEOFFREG24

 Base Address: 0xC001_0000  Address = Base Address + 1060, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Reserved 0 ARQOS1 [15:12] RW DREX slave interface port 1 read channel QoS 0 AWQOS1 [11:8] RW DREX slave interface port 1 write channel QoS 0 ARQOS0 [7:4] RW DREX slave interface port 0 read channel QoS 0 AWQOS0 [3:0] RW DREX slave interface port 0 write channel QoS 0

4.9.1.2.26 TIEOFFREG25

 Base Address: 0xC001_0000  Address = Base Address + 1064, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value 3D GPU_PP0_NSLEEP [31:0] RW 3D GPU PP0 SRAM retention (low active) FFFFFFFF cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-114 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.27 TIEOFFREG26

 Base Address: 0xC001_0000  Address = Base Address + 1068, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value TZPCDECPROT0m3 [31:24] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT1m3 [23:16] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure RSVD [15:14] RW Reserved 0 TZPCDECPROT0m7 [13] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT1m7 [12] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT0m8 [11] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT1m8 [10] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT0m10 [9] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT1m10 [8] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT0m12 [7] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT1m12 [6] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT0m13 [5] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT1m13 [4] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT0m14 [3] RW Secure Transaction (Peri BUS) 0 = Secure cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-115 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 1 = Non-Secure TZPCDECPROT1m14 [2] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT0m16 [1] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure TZPCDECPROT1m16 [0] RW Secure Transaction (Peri BUS) 0 = Secure 1 = Non-Secure

4.9.1.2.28 TIEOFFREG27

 Base Address: 0xC001_0000  Address = Base Address + 106C, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value 3D GPU_PP1_NSLEEP [31:0] RW 3D GPU PP1 SRAM retention (low active) FFFFFFFF

4.9.1.2.29 TIEOFFREG28

 Base Address: 0xC001_0000  Address = Base Address + 1070, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ACPARUSER_0 [31] RW ACP AR channel user value 0 ACPAWUSER_0 [30] RW ACP AW channel user value 0 RSVD [29:26] – Reserved 0 CA9_PWRCTLI3 [25:24] RW Reset value for CPU3 status register [3:2] 0 MPEGTS_HPROT_3 [23] RW AXI Cacheable 0 MPEGTS_HPROT_2 [22] RW AXI Bufferable 0 SDMMC_HPROT_3 [21] RW AXI Cacheable 0 SDMMC_HPROT_2 [20] RW AXI Bufferable 0 TB0_AWCACHE1_VALU E [19] RW TOP BUS m0 AWCACHE[1] value 0 TB0_ARCACHE1_VALU E [18] RW TOP BUS m0 ARCACHE[1] value 0 TB0_AWCACHE1_CTRL EN [17] RW TOP BUS m0 AWCACHE[1] control enable 0 = AWCACHE[1] bit control disable 1 = AWCACHE[1] bit control enable TB0_ARCACHE1_CTRL EN [16] RW TOP BUS m0 ARCACHE[1] control enable 0 = ARCACHE[1] bit control disble cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-116 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 1 = ARCACHE[1] bit control enable HOST_HPROT_3 [15] RW AXI Cacheable 0 HOST_HPROT_2 [14] RW AXI Bufferable 0 EHCI_HPROT_3 [13] RW AXI Cacheable 0 EHCI_HPROT_2 [12] RW AXI Bufferable 0 OTG_HPROT_3 [11] RW AXI Cacheable 0 OTG_HPROT_2 [10] RW AXI Bufferable 0 ACP_AxPROT [9] RW Secure Transaction (AxPROT[1] between TOP bus <- > ARM) 0 = Secure 1 = Non-Secure GMAC_AxPROT [8] RW Secure Transaction (AxPROT[1] between GMAC <-> AXI) 0 = Secure 1 = Non-Secure DISP_ARPROT [7] RW Secure Transaction (Display0 & 1) 0 = Secure 1 = Non-Secure VIP_AWPROT [6] RW Secure Transaction (VIP0 & 1) 0 = Secure 1 = Non-Secure SCALER_AxPROT [5] RW Secure Transaction 0 = Secure 1 = Non-Secure CODAS_AxPROT [4] RW Secure Transaction 0 = Secure 1 = Non-Secure CODAP_AxPROT [3] RW Secure Transaction 0 = Secure 1 = Non-Secure DEINT _AxPROT [2] RW Secure Transaction 0 = Secure 1 = Non-Secure T2B_AxPROT [1] RW Secure Transaction 0 = Secure 1 = Non-Secure MALI_AxPROT [0] RW Secure Transaction1 0 = Secure 1 = Non-Secure cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-117 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.30 TIEOFFREG29

 Base Address: 0xC001_0000  Address = Base Address + 1074, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value 3D GPU_PP2_NSLEEP [31:0] RW 3D GPU PP2 SRAM retention (low active) FFFFFFFF

4.9.1.2.31 TIEOFFREG30

 Base Address: 0xC001_0000  Address = Base Address + 1078, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value RSVD [31:24] RW Reserved FF TZPROT_T_M1 [23] RW TrustZone Protection (TOP BUS) 0 = Secure 1 = Non-Secure TZPROT_T_M0 [22] RW TrustZone Protection (TOP BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M16 [21] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M15 [20] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M14 [19] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M13 [18] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M12 [17] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M11 [16] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M10 [15] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M9 [14] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-118 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value TZPROT_P_M8 [13] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M7 [12] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M6 [11] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M5 [10] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M4 [9] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M3 [8] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M2 [7] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M1 [6] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_P_M0 [5] RW TrustZone Protection (PERI BUS) 0 = Secure 1 = Non-Secure TZPROT_D_DREX [4] RW TrustZone Protection (DISPLAY BUS) 0 = Secure 1 = Non-Secure TZPROT_B_AXISRAM [3] RW TrustZone Protection (BOTTOM BUS) 0 = Secure 1 = Non-Secure TZPROT_B_PBUS [2] RW TrustZone Protection (BOTTOM BUS) 0 = Secure 1 = Non-Secure TZPROT_B_DREX [1] RW TrustZone Protection (BOTTOM BUS) 0 = Secure 1 = Non-Secure TZPROT_B_MCUS [0] RW TrustZone Protection (BOTTOM BUS) 0 = Secure 1 = Non-Secure cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-119 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.2.32 TIEOFFREG31

 Base Address: 0xC001_0000  Address = Base Address + 0x107C, Reset Value = 0xFFFF_FFFF Name Bit Type Description Reset Value 3D GPU_PP3_NSLEEP [31:0] RW 3D GPU PP3 SRAM retention (low active) FFFFFFFF

4.9.1.2.33 TIEOFFREG32

 Base Address: 0xC001_0000  Address = Base Address + 0x1080, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value AXI_MASTER_BUS_RE MAP [4:3] RW TOP AXI BUS Remap Master Interface - 0 port: Bottom AXI BUS0 0x0000_0000 ~ 0x3FFF_FFFF 0xC000_0000 ~ 0xCFFF_FFFF 0xFFFF_0000 ~ 0xFFFF_FFFF AXI_MASTER_BUS_REMAP[3] 0 = 0x4000_0000 ~ 0xBFFF_FFFF 1 = 0xD000_0000 ~ 0xDFFF_FFFF Master Interface - 1 port: ARM Cortex-A9 ACP Port AXI_MASTER_BUS_REMAP[4] 0 = 0xD000_0000 ~ 0xDFFF_FFFF 1 = 0x4000_0000 ~ 0xBFFF_FFFF AXI_PERI_BUS_SYNCM ODEREQm16 [2] RW DREX & DDRPHY APB Interface clock synchronizer request 0 AXI_PERI_BUS_SYNCM ODEREQm10 [1] RW CODA APB Interface clock synchronizer request 0 AXI_PERI_BUS_SYNCM ODEREQm9 [0] RW 3D GPU AXI (Peripheral interface) Interface clock synchronizer request 0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-120 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.3 IP Reset

 Base Address: 0xC001_2000 Register Offset Description Reset Value IP RESET REGISTER 0 000h 0x0000_0000 IP RESET REGISTER 1 004h 0x0000_0000 IP RESET REGISTER 2 008h 0x0000_0000

4.9.1.3.1 IP RESET REGISTER 0

 Base Address: 0xC001_0000  Address = Base Address + 2000h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value MIPITOP_i_PHY_S_RES ETN [31] RW MIPI D-PHY Slave channel Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 MIPITOP_i_CSI_I_PRES ETn [30] RW MIPI CSI SlaveReset (Active Low) 0 = Reset 1 = No Reset 1'b0 MIPITOP_i_DSI_I_PRES ETn [29] RW MIPI DSI MasterReset (Active Low) 0 = Reset 1 = No Reset 1'b0 MIPITOP_i_nRST [28] RW MIPI Register InterfaceReset (Active Low) 0 = Reset 1 = No Reset 1'b0 MCUYZTOP_nPRST [27] RW Memory Controller Core Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 MCUYZTOP_ARESETn [26] RW Memory Controller AXI Interface Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 MCUYZTOP_CRESETn [25] RW Memory Controller APB Interface Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 I2S2_PRESETn [24] RW I2S2 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 I2S1_PRESETn [23] RW I2S1 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 I2S0_PRESETn [22] RW I2S0 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-121 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value I2C2_PRESETn [21] RW I2C2 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 I2C1_PRESETn [20] RW I2C1 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 I2C0_PRESETn [19] RW I2C0 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 DisplayTop_i_LVDS_nR ST [18] RW LVDS PHY Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 DisplayTop_i_HDMI_PH Y_nRST [17] RW HDMI PHY Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 DisplayTop_i_HDMI_TM DS_nRST [16] RW HDMI LINK TMDS Block Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 DisplayTop_i_HDMI_SP DIF_nRST [15] RW HDMI LINK SPDIF Block Reset (Active Low) 0: Reset 1: No Reset0 = Reset 1 = No Reset 1'b0 DisplayTop_i_HDMI_VID EO_nRST [14] RW HDMI LINK VIDEO Block Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 DisplayTop_i_HDMI_nRS T [13] RW HDMI LINK & CEC Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 RSVD [12] RW Caution: This bit should be set to 1 1'b0 RSVD [11] RW Caution: This bit should be set to 1 1'b0 DisplayTop_i_DualDispla y_nRST [10] RW Dual Display(MLC & DPC) Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 DisplayTop_i_Top_nRST [9] RW Display Block Total Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 DEINTERLACE_i_nRST [8] RW Deinterlace Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 Crypto_i_nRST [7] RW Crypto Engine Reset (Active Low) 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-122 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 0 = Reset 1 = No Reset ARMTOP_nWDRESET3 [6] RW Watch Dog Timer 3 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 ARMTOP_nWDRESET2 [5] RW Watch Dog Timer 2 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 ARMTOP_nWDRESET1 [4] RW Watch Dog Timer 1 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 ARMTOP_nCPURESET3 [3] RW CPU Core 3 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 ARMTOP_nCPURESET2 [2] RW CPU Core 2 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 ARMTOP_nCPURESET1 [1] RW CPU Core 1 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 AC970_PRESETn [0] RW AC97 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0

4.9.1.3.2 IP RESET REGISTER 1

 Base Address: 0xC001_0000  Address = Base Address + 2004h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value gmac0_aresetn_i [31] RW GMAC Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 coda960_i_creset_n [30] RW Multi-Format Video Codec CoreReset (Active Low) 0 = Reset 1 = No Reset 1'b0 coda960_i_preset_n [29] RW Multi-Format Video Codec APB Interface Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 coda960_i_areset_n [28] RW Multi-Format Video Codec AXI Interface Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-123 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value adc_nRST [27] RW ADC Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 WDT00_nPOR [26] RW nRSTOUT Initialization by POReset (Active Low) 0 = Reset 1 = No Reset 1'b0 WDT00_PRESETn [25] RW WDT APB Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 USB20OTG0_i_nRST [24] RW USB2.0 OTG Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 USB20HOST0_i_nRST [23] RW USB2.0 Host Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 RSVD [22] RW Reserved 1'b0 UART04_nUARTRST [21] RW UART4 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 UART03_nUARTRST [20] RW UART3 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 UART02_nUARTRST [19] RW UART2 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 UART01_nUARTRST [18] RW UART1 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 UART00_nUARTRST [17] RW UART0 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 SSP2_nSSPRST [16] RW SSP2 Core Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 SSP2_PRESETn [15] RW SSP2 APB Interface Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 SSP1_nSSPRST [14] RW SSP1 Core Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 SSP1_PRESETn [13] RW SSP1 APB Interface Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-124 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value SSP0_nSSPRST [12] RW SSP0 Core Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 SSP0_PRESETn [11] RW SSP0 APB Interface Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 SPDIFTX00_PRESETn [10] RW SPDIFTX Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 SPDIFRX00_PRESETn [9] RW SPDIFRX Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 SDMMC2_i_nRST [8] RW SDMMC Controller 2 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 SDMMC1_i_nRST [7] RW SDMMC Controller 1 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 SDMMC0_i_nRST [6] RW SDMMC Controller 0 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 SCALER_i_nRST [5] RW Scaller Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 PWMTIMER1_PRESETn [4] RW PWMTIMER1 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 PWMTIMER0_PRESETn [3] RW PWMTIMER0 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 PDM_i_nRST [2] RW PDM Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 MPEGTSI00_i_nRST [1] RW MPEG-TSI Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 MIPITOP_i_PHY_M_RE SETN [0] RW MIPI D-PHY Master Channel Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-125 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.3.3 IP RESET REGISTER 2

 Base Address: 0xC001_0000  Address = Base Address + 2008h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:4] – Reserved 28'b0 vip001_i_nRST [3] RW VIP Controller 1 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 vip000_i_nRST [2] RW VIP Controller 0 Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 ppm_i_nRST [1] RW PPM Reset (Active Low) 0 = Reset 1 = No Reset 1'b0 3D GPU_nRST [0] RW 3D GPUReset (Active Low) 0 = Reset 1 = No Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-126 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.4 AXI BUS

 Bottom AXI BUS base address: 0xC0050000  TOP AXI BUS base address: 0xC0052000  DISPLAY AXI BUS base address: 0xC005E000 Offset Type Name Description Reset Value 0x400a RW QoS_tidemark_MI0 QoS tidemark for MI 0 0x00000000 0x404b RW QoS_control_MI0 QoS access control for MI 0 0x00000000 0x408c RW AR_arbitration_MI0 AR channel arbitration value for MI 0 Configured 0x40Cd RW AW_arbitration_MI0 AW channel arbitration value for MI 0 Configured 1. Address allocation for QoS tidemark Register is 0x400 + 0x20×N, where N is the number of the relevant MI. 2. Address allocation for QoS access control Register is 0x404 + 0x20×N, where N is the number of the relevant MI. 3. Address allocation for AR channel arbitration control registers is 0x408 + 0x20×N, where N is the number of the relevant MI. 4. Address allocation for AW channel arbitration control registers is 0x40C + 0x20×N, where N is the number of the relevant MI. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-127 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.4.1 Programmable Quality of Service (ProgQoS)

 Address map The register space for the MIs starts at 0x400 and extends to 0x7FC. Each MI that is configured to support QoS filtering contains the registers at the following offsets:  0x0: QoS tidemark Register  0x4: QoS access control Register. When more than one MI with QoS support is included then the MI number controls the register address offset for that MI.  Qos tidemark Register You can program this with the number of outstanding transactions that are permitted before the QoS scheme becomes active. If a value is written to this register that is larger than the combined acceptance capability of the attached slave, then the QoS scheme never becomes active for this MI. If a value of 0 is written to this register, then the QoS scheme is turned off for this MI. This behavior ensures that it is impossible to block all transactions completely by accidental mis-programming. If you access a QoS tidemark Register for an MI that has not been configured to support QoS then the HPM ignores writes and reads are undefined.  Qos access control Register A 1 in any bit of this register indicates that the SI corresponding to the bit p osition is permitted to use the reserved slots of the connected combined acceptance capability of the slaves. The maximum value that you can write to this register is 2^<total number of SIs>^ -1. NOTE: If you attempt to write a value containing 1s in positions that do not correspond to SIs, then these bits are ignored and are not set in the register. Changes to these values occur on the first possible arbitration time after they are written. If you access a QoS access control Register for an MI that has not been configured to support QoS then the HPM ignores writes and reads are undefined. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 4-128 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

4.9.1.4.2 Arbitration control

The arbitration schemes for the AR channel and AW channel are set when you configure the HPM, and they control the arbitration scheme for these channels when the HPM exits from reset. However, the HPM enables you to change the AR channel and AW channel arbitration schemes by using the APB SI on the HPM to write to the arbitration control registers. The HPM provides two arbitration control registers per MI, one for the AR channel and one for the AW channel. They operate and are programmed in the same way. As the address map does not have sufficient space for each value to be addressable separately, some addressing information is encoded in the write data when updating values. When reading registers the extra addressing information is supplied by a preliminary write command before the read command. NOTE: When a master interface has connections to only one slave interface its operation is much simpler and as a result the arbitration mechanism is removed. If you attempt to configure or interrogate the arbitration mechanism for such a master interface, all writes are ignored, and each read returns zero.  Programmable RR arbitration scheme The following sections describe how to program and read the values for the programmable RR arbitration scheme:  Writing configuration values  Reading configuration values Writing configuration values When the programmable RR scheme is selected for a master interface then each of its arbitration slots can have the slave interface associated with it changed. Table 4-16 Bit Assignment for Writing Master Interface Channel Arbitration Values Bit Name Description [31:24] slot_number Arbitration slot number [23:8] reserved Set to 0x0000 [7:0] slave_interface_num Slave interface number NOTE: No protection is imposed when you program the slots in the programmable RR arbitration scheme. So it is possible for you to remove a slave interface from all the slots which would make that slave interface inaccessible. However, if the mechanism for programming the configuration registers uses the interconnect, it is possible to make the configuration mechanism itself inaccessible. Reading configuration values You must perform a write followed by a read operation to the same address. The write transfer sets the slot number to be read for that master interface. The following read operation returns the slave interface that is associated with that slot number. Table 4-17 lists the bit assignments of the preliminary write operation. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 4 System Control 129 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Table 4-17 Preliminary write Bit Assignment for an Arbitration Register Read Operation Bit Name Description [31:24] reserved Set to 0xFF [23:8] reserved Set to 0x0000 [7:0] slot_number These bits set the slot number for the following read operation The format of the read data returned has the slave interface number associated with the addressed slot in bits [7:0]. All other bits are set to zero. Table 4-18 lists the bit assignments of the arbitration read operation. Table 4-18 Bit Assignment for an Arbitration Register Read Operation Bit Name Description [31:8] reserved These bits read as zero [7:0] interface_number Slave interface number associated with the addressed slot number cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5 Clock Generator

5.1 IP Clock Generator Overview

The IP Clock Generator can generate divided clock. Each IP have clocking scheme which requires several different division ratio simultaneously. Therefore, each of IP Clock Generator supplies required clock to each IP. These IP Clock Generators uses the PLL from SYSCTRL or External Clock from PAD. And it can divide required clock of each IP by 2-n divider. Figure 5-1 Interconnection Example of Clock Generator cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.1 Clock Generator Level 0

Clock Generator Level 0 does not have clock divider. It can only do clock gating. It uses PCLK or BCLK Gating.  Following peripherals use Level 0 Clock Generator:  CODA960  Crypto  I2C  3D GPU  MPEGTSI  PDM  SCALLER  DEINTERLACE  MLC

5.1.1.1 Block Diagram

Figure 5-2 Block Diagram of Clock Generator Level 0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.1.2 Register Map Summary

Register Offset Description Reset Value  Base Address: 0xC00C_0000 CODA960CLKENB 0x7000 Clock Generator for CODA960 Enable Register 0x0000_0000 CRYPTOCLKENB 0x6000 Clock Generator for CRYPTO Enable Register 0x0000_0000  Base Address: 0xC00A_0000  Base Address: 0xC00B_0000 I2CCLKENB 0xE000, 0xF000 Clock Generator for I2C ch0/1 Enable Register 0x0000_0000 0x0000 Clock Generator for I2C ch2 Enable Register 0x0000_0000  Base Address: 0xC00C_0000 3D GPUCLKENB 0x3000 Clock Generator for 3D GPU Enable Register 0x0000_0000 MPEGTSICLKENB 0xB700 Clock Generator for MPEG-TS Enable Register 0x0000_0000 PDMCLKENB 0xB000 Clock Generator for PDM Enable Register 0x0000_0000  Base Address: 0xC00B_0000 SCALERCLKENB 0x6000 Clock Generator for SCALER Enable Register 0x0000_0000 DEINTERLACECLKENB 0x5000 Clock Generator for DEINTERLACE Enable Register 0x0000_0000  Base Address: 0xC010_0000 MLCCLKENB 0x23C0, 0x27C0 Clock Generator for MLC Enable Register 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.1.2.1 CODA960CLKENB

 Base Address: 0xC00C_7000  Address = Base Address + 0x00, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:4] R Reserved 28'b0 PCLKMODE [3] RW Specifies PCLK operating mode. 0 = PCLK is only enabled when CPU accesses this module 1 = PCLK is always enabled 1'b0 BCLKENB [2:0] R BCLK Enable 0 = Disable 1 = Reserved 2 = Reserved 3 = Always 2'b0

5.1.1.2.2 CRYPTOCLKENB

 Base Address: 0xC00C_6000  Address = Base Address + 0x00, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:4] R Reserved 28'b0 PCLKMODE [3] RW Specifies PCLK operating mode. 0 = PCLK is only enabled when CPU accesses this module 1 = PCLK is always enabled 1'b0 RSVD [2:0] R Reserved 2'b0

5.1.1.2.3 I2CCLKENB

 Base Address: 0xC00A_E000, 0xC00A_F000 Address = Base Address + 0x00, 0x00, Reset Value = 0x0000_0000  Base Address: 0xC00B_0000 Address = Base Address + 0x00, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:4] R Reserved 28'b0 PCLKMODE [3] RW Specifies PCLK operating mode. 0 = PCLK is only enabled when CPU accesses this module 1 = PCLK is always enabled 1'b0 RSVD [3:0] R Reserved 3'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 5.1.1.2.4 3D GPUCLKENB  Base Address: 0xC00C_3000  Address = Base Address + 0x00, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:2] R Reserved 30'b0 BCLKENB [1:0] R BCLK Enable 0 = Disable 1 = Reserved 2 = Reserved 3 = Always 2'b0

5.1.1.2.5 MPEGTSICLKENB

 Base Address: 0xC00C_B000  Address = Base Address + 0x700, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:2] R Reserved 30'b0 BCLKENB [1:0] R BCLK Enable 0 = Disable 1 = Reserved 2 = Reserved 3 = Always 2'b0

5.1.1.2.6 PDMCLKENB

 Base Address: 0xC00C_B000  Address = Base Address + 0x00, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value Reserved [31:4] R Reserved 28'b0 PCLKMODE [3] RW Specifies PCLK operating mode. 0 = PCLK is only enabled when CPU accesses this module 1 = PCLK is always enabled 1'b0 BCLKENB [2:0] R BCLK Enable 0 = Disable 1 = Reserved 2 = Reserved 3 = Always 3'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.1.2.7 SCALERCLKENB

 Base Address: 0xC00B_6000  Address = Base Address + 0x00, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:2] R Reserved 30'b0 BCLKENB [1:0] R BCLK Enable 0 = Disable 1 = Reserved 2 = Reserved 3 = Always 2'b0

5.1.1.2.8 DEINTERLACECLKENB

 Base Address: 0xC00B_5000  Address = Base Address + 0x00, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:2] R Reserved 30'b0 BCLKENB [1:0] R BCLK Enable 0 = Disable 1 = Reserved 2 = Reserved 3 = Always 2'b0

5.1.1.2.9 MLCCLKENB

 Base Address: 0xC010_2000  Address = Base Address + 0x3C0, 0x7C0, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:4] R Reserved 28'b0 PCLKMODE [3] RW Specifies PCLK operating mode. 0 = PCLK is only enabled when CPU accesses this module 1 = PCLK is always enabled 1'b0 RSVD [2] R Reserved 1'b0 BCLKENB [1:0] R BCLK Enable 0 = Disable 1 = Reserved 2 = Reserved 3 = Always 2'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.2 Clock Generator Level 1

The Clock Generator Level-1 has one clock divider. Clock Divider has 8-bit divide registers. Divide registers can reach to 256 levels and it can divide up to 256 levels.  Following peripherals use Level 1 Clock Generator:  MIPICSI  PPM  PWMTIMER  SDMMC  SPDIFTX  SSP  UART  VIP

5.1.2.1 Block Diagram

Figure 5-3 Block Diagram of Clock Generator Level 1 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.2.2 Register Map Summary

Register Offset Description Reset Value  Base Address: 0xC00C_0000 MIPICSICLKENB 0xA000 Clock Generator Enable Register for MIPI CSI 0x0000_0000 MIPICSICLKGEN0L 0xA004 Clock Generator Control 0 Low Register for MIPI CSI 0x0000_0000 PPMCLKENB 0x4000 Clock Generator Enable Register for PPM 0x0000_0000 PPMCLKGEN0L 0x4004 Clock Generator Control 0 Low Register for PPM 0x0000_0000  Base Address: 0xC00B_0000 (PWM, TIMER)  Base Address: 0xC00C_0000 (PWM) PWMTIMERCLKENB (PWM) 0xA000, 0xE000, 0xF000 Clock Generator Enable Register for PWM 0x0000_0000 0xC00C _0000 PWMTIMERCLKENB (TIMER) 0x9000, 0xB000, 0xC000, 0xD000 Clock Generator Enable Register for TIMER 0x0000_0000 PWMTIMERCLKGEN0L (PWM) 0xA004, 0xE004, 0xF004 Clock Generator Control 0 Low Register for PWM 0x0000_0000 0xC00C _0004 PWMTIMERCLKGEN0L (TIMER) 0x9004, 0xB004, 0xC004, 0xD004 Clock Generator Control 0 Low Register for TIMER 0x0000_0000  Base Address: 0xC00C_0000 SDMMCCLKENB 0x5000, 0xC000, 0xD000 Clock Generator Control 0 Low Register for SDMMC 0x0000_0000 SDMMCCLKGEN0L 0x5004, 0xC004, 0xD004 Clock Generator Control 0 Low Register for SDMMC 0x0000_0000  Base Address: 0xC00B_0000 SPDIFTXCLKENB 0x8000 Clock Generator Control 0 Low Register for SPDIF 0x0000_0000 SPDIFTXCLKGEN0L 0x8004 Clock Generator Control 0 Low Register for SPDIF 0x0000_0000  Base Address: 0xC00A_0000 SSPCLKENB 0xC000, 0xD000, 0x7000 Clock Generator Control 0 Low Register for SSP 0x0000_0000 SSPCLKGEN0L 0xC004, 0xD004, Clock Generator Control 0 Low Register for SSP 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value 0x7004  Base Address: 0xC00A_0000  Base Address: 0xC006_0000  Base Address: 0xC008_0000 UARTCLKENB 0x9000, 0x8000, 0xA000, 0xB000 Clock Generator Control 0 Low Register for UART 0x0000_0000 0xE000 0x4000 UARTCLKGEN0L 0x9004, 0x8004, 0xA004, 0xB004 Clock Generator Control 0 Low Register for UART 0x0000_0000 0xE004 0x4004  Base Address: 0xC00C_0000 VIPCLKENB 0x1000, 0x2000, Clock Generator Control 0 Low Register for VIP 0x0000_0000 VIPCLKGEN0L 0x1004, 0x2004, Clock Generator Control 0 Low Register for VIP 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.2.2.1 MIPICSICLKENB

 Base Address: 0xC00C_0000  Address = Base Address + 0xA000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] R Reserved 29'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0

5.1.2.2.2 MIPICSICLKGEN0L

 Base Address: 0xC00C_0000  Address = Base Address + 0xA004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable(Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to "0") 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.2.2.3 PPMCLKENB

 Base Address: 0xC00C_0000  Address = Base Address + 0x4000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] R Reserved 29'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0

5.1.2.2.4 PPMCLKGEN0L

 Base Address: 0xC00C_0000  Address = Base Address + 0x4004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable(Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to "0") 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.2.2.5 PWMTIMERCLKENB

 Base Address: 0xC00B_0000 (PWM, TIMER)  Base Address: 0xC00C_0000 (PWM)  Address = Base Address + 0xA000, 0xE000, 0xF000, 0xC00C_0000 (PWM), Reset Value = 0x0000_0000  Address = Base Address + 0x9000, 0xB000, 0xC000, 0xD000 (TIMER), Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] R Reserved 29'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0

5.1.2.2.6 PWMTIMERCLKGEN0L

 Base Address: 0xC00B_0000 (PWM, TIMER)  Base Address: 0xC00C_0000 (PWM)  Address = Base Address + 0xA004, 0xE004, 0xF004, 0xC00C_0004 (PWM), Reset Value = 0x0000_0000  Address = Base Address + 0x9004, 0xB004, 0xC004, 0xD004 (TIMER), Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable(Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to \`0') 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.2.2.7 SDMMCCLKENB

 Base Address: 0xC00C_0000  Address = Base Address + 0x5000, 0xC000, 0xD000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] R Reserved 29'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0

5.1.2.2.8 SDMMCCLKGEN0L

 Base Address: 0xC00C_0000  Address = Base Address + 0x5004, 0xC004, 0xD004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable(Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to \`0') 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.2.2.9 SPDIFTXCLKENB

 Base Address: 0xC00B_0000  Address = Base Address + 0x8000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] R Reserved 29'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0

5.1.2.2.10 SPDIFTXCLKGEN0L

 Base Address: 0xC00B_0000  Address = Base Address + 0x8004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable(Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to \`0') 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.2.2.11 SSPCLKENB

 Base Address: 0xC00A_0000  Address = Base Address + 0xC000, 0xD000, 0x7000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] R Reserved 29'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0

5.1.2.2.12 SSPCLKGEN0L

 Base Address: 0xC00A_0000  Address = Base Address + 0xC004, 0xD004, 0x7004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable(Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to \`0') 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.2.2.13 UARTCLKENB

 Base Address: 0xC00A_0000 Address = Base Address + 0x9000, 0x8000, 0xA000, 0xB000, Reset Value = 0x0000_0000  Base Address: 0xC006_0000 Address = Base Address + 0xE000, Reset Value = 0x0000_0000  Base Address: 0xC008_0000 Address = Base Address + 0x4000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] R Reserved 29'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0

5.1.2.2.14 UARTCLKGEN0L

 Base Address: 0xC00A_0000 Address = Base Address + 0x9004, 0x8004, 0xA004, 0xB004, Reset Value = 0x0000_0000  Base Address: 0xC006_0000 Address = Base Address + 0xE004, Reset Value = 0x0000_0000  Base Address: 0xC008_0000 Address = Base Address + 0x4004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable(Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to \`0') 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.2.2.15 VIPCLKENB

 Base Address: 0xC00C_0000  Address = Base Address + 0x1000, 0x2000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] R Reserved 29'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 BCLKENB [1:0] RW BCLK Enable 0 = Disable 1 = Reserved 2 = Reserved 3 = Always 2'b0

5.1.2.2.16 VIPCLKGEN0L

 Base Address: 0xC00C_0000  Address = Base Address + 0x1004, 0x2004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable(Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = PLL[3] 4 = CIS External Clock 0 5 = CIS External Clock 1 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to \`0') 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.3 Clock Generator Level 2

The Clock Generator Level2 has two clock dividers. Clock Divider has 8-bit divide registers. And each divide registers can reach to 256 levels and it can divide up to 256 levels. The two clock divider is serialized. Therefore Clock Generator Level-2 can divide up to 65,536.  Following peripherals use Level 2 Clock Generator:  GMAC  I2S  USBHOSTOTG  DPC  LVDS  HDMI  MIPIDSI

5.1.3.1 Block Diagram

Figure 5-4 Block Diagram of Clock Generator Level 2 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.3.2 Register Map Summary

Register Offset Description Reset Value  Base Address: 0xC00C_0000 GMACCLKENB 0x8000 Clock Generator Enable Register for GMAC 0x0000_0000 GMACCLKGEN0L 0x8004 Clock Generator Control 0 Low Register for GMAC 0x0000_0000 RSVD 0x8008 Reserved 0x0000_0000 GMACCLKGEN1L 0x800C Clock Generator Control 1 Low Register for GMAC 0x0000_0000  Base Address: 0xC00B_0000 I2SCLKENB 0x2000, 0x3000, 0x4000, Clock Generator Enable Register for I2S 0x0000_0000 I2SCLKGEN0L 0x2004, 0x3004, 0x4004, Clock Generator Control 0 Low Register for I2S 0x0000_0000 RSVD 0x2008, 0x3008, 0x4008, Reserved 0x0000_0000 I2SCLKGEN1L 0x200C, 0x300C, 0x400C, Clock Generator Control 1 Low Register for I2S 0x0000_0000  Base Address: 0xC006_0000 USBHOSTOTGCLKENB 0xB000 Clock Generator Enable Register for USBHOSTOTG 0x0000_0000 USBHOSTOTGCLKGEN0L 0xB004 Clock Generator Control 0 Low Register for USBHOSTOTG 0x0000_0000 RSVD 0xB008 0x0000_0000 USBHOSTOTGCLKGEN1L 0xB00C Clock Generator Control 1 Low Register for USBHOSTOTG 0x0000_0000  Base Address: 0xC010_0000 DPCCLKENB 0x2BC0, 0x2FC0 Clock Generator Enable Register for DPC 0x0000_0000 DPCCLKGEN0L 0x2BC4, 0x2FC4 Clock Generator Control 0 Low Register for DPC 0x0000_0000 RSVD 0x2BC8, 0x2FC8 Reserved 0x0000_0000 DPCCLKGEN1L 0x2BCC, 0x2FCC Clock Generator Control 1 Low Register for DPC 0x0000_0000 LVDSCLKENB 0x8000 Clock Generator Enable Register for LVDS 0x0000_0000 LVDSCLKGEN0L 0x8004 Clock Generator Control 0 Low Register for LVDS 0x0000_0000 RSVD 0x8008 Reserved 0x0000_0000 LVDSCLKGEN1L 0x800C Clock Generator Control 1 Low Register for LVDS 0x0000_0000 HDMICLKENB 0x9000 Clock Generator Enable Register for HDMI 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value HDMICLKGEN0L 0x9004 Clock Generator Control 0 Low Register for HDMI 0x0000_0000 RSVD 0x9008 Reserved 0x0000_0000 HDMICLKGEN1L 0x900C Clock Generator Control 1 Low Register for HDMI 0x0000_0000 MIPIDSICLKENB 0x5000 Clock Generator Enable Register for MIPI 0x0000_0000 MIPIDSICLKGEN0L 0x5004 Clock Generator Control 0 Low Register for MIPI 0x0000_0000 RSVD 0x5008 Reserved 0x0000_0000 MIPIDSICLKGEN1L 0x500C Clock Generator Control 1 Low Register for MIPI 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.3.2.1 GMACCLKENB

 Base Address: 0xC00C_0000  Address = Base Address + 0x8000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] R Reserved 29'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0

5.1.3.2.2 GMACCLKGEN0L

 Base Address: 0xC00C_0000  Address = Base Address + 0x8004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable(Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = PLL[3] 4 = External RX Clock 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to "0") 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.3.2.3 GMACCLKGEN1L

 Base Address: 0xC00C_0000  Address = Base Address + 0x800C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:13] R Reserved 19'b0 CLKDIV1 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL1 [4:2] RW 0 = Reserved 1 = Reserved 2 = Reserved 3 = Reserved 4 = Reserved 5 = Reserved 6 = Reserved 7 = Divided Clock from Divider 0 3'b0 OUTCLKINV1 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 OUTCLKSEL [0] RW 1/2 ns delay is applied to Out clock from source clock Can be used only in case of division by even number 0; Bypass 1 source clock/2 ns 1'b0

5.1.3.2.4 I2SCLKENB

 Base Address: 0xC00B_0000  Address = Base Address + 0x2000, 0x3000, 0x4000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] R Reserved 29'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.3.2.5 I2SCLKGEN0L

 Base Address: 0xC00B_0000  Address = Base Address + 0x2004, 0x3004, 0x4004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable(Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = PLL[3] 4 = External I2S Codec Clock 2 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to \`0') 1'b0

5.1.3.2.6 I2SCLKGEN1L

 Base Address: 0xC00B_0000  Address = Base Address + 0x200C, 0x300C, 0x400C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:13] R Reserved 19'b0 CLKDIV1 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL1 [4:2] RW 0 = Reserved 1 = Reserved 2 = Reserved 3 = Reserved 4 = Reserved 5 = Reserved 6 = Reserved 7 = Divided Clock from Divider 0 3'b0 OUTCLKINV1 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 OUTCLKSEL [0] RW 1/2 ns delay is applied to Out clock from source clock Can be used only in case of division by even number 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 0; Bypass 1 source clock/2 ns

5.1.3.2.7 USBHOSTOTGCLKENB

 Base Address: 0xC006_0000  Address = Base Address + 0xB000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] R Reserved 29'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0

5.1.3.2.8 USBHOSTOTGCLKGEN0L

 Base Address: 0xC006_0000  Address = Base Address + 0xB004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable(Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = PLL[3] 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to "0") 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.3.2.9 USBHOSTOTGCLKGEN1L

 Base Address: 0xC006_0000  Address = Base Address + 0xB00C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:13] R Reserved 19'b0 CLKDIV1 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL1 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = PLL[3] 4 = External XTI 5 = Reserved 6 = Reserved 7 = Divided Clock from Divider 0 3'b0 OUTCLKINV1 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 OUTCLKSEL [0] RW 1/2 ns delay is applied to Out clock from source clock Can be used only in case of division by even number 0; Bypass 1 source clock/2 ns 1'b0

5.1.3.2.10 DPCCLKENB

 Base Address: 0xC010_0000  Address = Base Address + 0x2BC0, 0x2FC0, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value Reserved [31:4] R Reserved 28'b0 PCLKMODE [3] RW Specifies PCLK operating mode. 0 = PCLK is only enabled when CPU accesses this module 1 = PCLK is always enabled 1'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 Reserved [1:0] R Reserved 2'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-26 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.3.2.11 DPCCLKGEN0L

 Base Address: 0xC010_0000  Address = Base Address + 0x2BC4, 0x2FC4, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable (Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = Reserved 4 = HDMI PLL Clock 5 = Reserved 6 = PLL[3] 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to "0") 1'b0

5.1.3.2.12 DPCCLKGEN1L

 Base Address: 0xC010_0000  Address = Base Address + 0x2BCC, 0x2FCC, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:13] R Reserved 19'b0 CLKDIV1 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL1 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = Reserved 4 = HDMI PLL Clock 5 = Reserved 6 = PLL[3] 7 = Divided Clock from Divider 0 3'b0 OUTCLKINV1 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value OUTCLKSEL [0] RW 1/2 ns delay is applied to Out clock from source clock Can be used only in case of division by even number 0; Bypass 1 source clock/2 ns 1'b0

5.1.3.2.13 LVDSCLKENB

 Base Address: 0xC010_0000  Address = Base Address + 0x8000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:4] R Reserved 28'b0 PCLKMODE [3] RW Specifies PCLK operating mode. 0 = PCLK is only enabled when CPU accesses this module 1 = PCLK is always enabled 1'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0

5.1.3.2.14 LVDSCLKGEN0L

 Base Address: 0xC010_0000  Address = Base Address + 0x8004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable (Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = PLL[3] 4 = HDMI PLL Clock 5 = Reserved 6 = Reserved 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-28 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value RSVD [0] RW Reserved (This bit should be set to "0") 1'b0

5.1.3.2.15 LVDSCLKGEN1L

 Base Address: 0xC010_0000  Address = Base Address + 0x800C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value Reserved [31:13] R Reserved 19'b0 CLKDIV1 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL1 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = PLL[3] 4 = HDMI PLL Clock 5 = Reserved 6 = Reserved 7 = Divided Clock from Divider 0 3'b0 OUTCLKINV1 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 OUTCLKSEL [0] RW 1/2 ns delay is applied to Out clock from source clock Can be used only in case of division by even number 0; Bypass 1 source clock/2 ns 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-29 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.3.2.16 HDMICLKENB

 Base Address: 0xC010_0000  Address = Base Address + 0x9000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:4] R Reserved 28'b0 PCLKMODE [3] RW Specifies PCLK operating mode. 0 = PCLK is only enabled when CPU accesses this module 1 = PCLK is always enabled 1'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0

5.1.3.2.17 HDMICLKGEN0L

 Base Address: 0xC010_0000  Address = Base Address + 0x9004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable (Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = PLL[3] 4 = Reserved 5 = Reserved 6 = Reserved 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to "0") 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-30 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.3.2.18 HDMICLKGEN1L

 Base Address: 0xC010_0000  Address = Base Address + 0x900C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:13] R Reserved 19'b0 CLKDIV1 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL1 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = PLL[3] 4 = Reserved 5 = Reserved 6 = Reserved 7 = Divided Clock from Divider 0 3'b0 OUTCLKINV1 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 OUTCLKSEL [0] RW 1/2 ns delay is applied to Out clock from source clock Can be used only in case of division by even number 0; Bypass 1 source clock/2 ns 1'b0

5.1.3.2.19 MIPIDSICLKENB

 Base Address: 0xC010_0000  Address = Base Address + 0x5000, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] R Reserved 29'b0 CLKGENENB [2] RW Enable/Disable to generate a clock. 0 = Disable 1 = Enable 1'b0 RSVD [1:0] R Reserved 2'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator 5-31 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

5.1.3.2.20 MIPIDSICLKGEN0L

 Base Address: 0xC010_0000  Address = Base Address + 0x5004, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] R Reserved 16'b0 OUTCLKENB [15] RW Specifies the direction of the PADVCLK pad. This bit should be set when CLKSRCSEL0/1 is 3 or 4. 0 = Enable(Output) 1 = Reserved 1'b0 RSVD [14:13] R Reserved 2'b0 CLKDIV0 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL0 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = PLL[3] 4 = HDMI PLL Clock 5 = Reserved 6 = Reserved 3'b0 OUTCLKINV0 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 RSVD [0] RW Reserved (This bit should be set to "0") 1'b0

5.1.3.2.21 MIPIDSICLKGEN1L

 Base Address: 0xC010_0000  Address = Base Address + 0x500C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:13] R Reserved 19'b0 CLKDIV1 [12:5] RW Specifies divider value of the source clock. Divider value = CLKDIV0 + 1 8'b0 CLKSRCSEL1 [4:2] RW 0 = PLL[0] 1 = PLL[1] 2 = PLL[2] 3 = PLL[3] 4 = HDMI PLL Clock 5 = Reserved 6 = Reserved 7 = Divided Clock from Divider 0 3'b0 OUTCLKINV1 [1] RW Specifies whether to invert the clock output. 0 = Normal (Falling Edge) 1 = Invert (Rising Edge) 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 5 Clock Generator Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value OUTCLKSEL [0] RW 1/2 ns delay is applied to Out clock from source clock Can be used only in case of division by even number 0; Bypass 1 source clock/2 ns 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6 System L2 Cache (PL-310 L2C)

6.1 Overview

The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a recognized method of improving the performance of ARM-based systems when significant memory traffic is generated by the processor. By definition a secondary cache assumes the presence of a Level 1 or primary cache, closely coupled or internal to the processor. Memory access is fastest to L1 cache, followed closely by L2 cache. Memory access is typically significantly slower with L3 main memory. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.2 Features

The cache controller features:  Slave and master AMBA AXI interfaces designed for high performance systems.  Lockdown format C supported, for data and instructions.  Lockdown by line supported.  Lockdown by master ID supported.  L2 cache available size can be 16 KB to 8 MB, depending on configuration and the use of the lockdown registers.  Fixed line length of 32 bytes, eight words or 256 bits.  Interface to data RAM is byte writable.  Supports all of the AXI cache modes:  Write-through and write-back  Read allocate, write allocate, read and write allocate.  Force write allocate option to always have cacheable writes allocated to L2 cache, for processors not supporting this mode.  Normal memory non-cacheable shared reads are treated as cacheable non-allocatable. Normal memory non- cacheable shared writes are treated as cacheable write-through no write-allocate. There is an option, Shared Override, to override this behavior.  Critical word first line fill supported.  Pseudo-Random, or round-robin victim selection policy. You can make this deterministic with use of lockdown registers.  Four 256-bit Line Fill Buffers (LFBs), shared by the master ports. These buffers capture line fill data from main memory, waiting for a complete line before writing to L2 cache memory.  Two 256-bit Line Read Buffers (LRBs) for each slave port. These buffers hold a line from the L2 memory for a cache hit.  Three 256-bit Eviction Buffers (EBs). These buffers hold evicted lines from the L2 cache, to be written back to main memory.  Three 256-bit Store Buffers (STBs). These buffers hold bufferable writes before their draining to main memory, or the L2 cache. They enable multiple writes to the same line to be merged.  Software option to enable exclusive cache configuration.  Configuration registers accessible using address decoding in the slave ports.  Address filtering in the master ports enabling redirection of a certain address range to one master port while all other addresses are redirected to the other one. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.3 Block Diagram

Figure 6-1 System L2 Cache Block Diagram System BUS CACHE RAM Processor Cache Controller Instruction And/or data (RW) Instruction And/or data (RW) AXI Slave0 (RW) AXI Slave1 (RW) AXI Master0 (RW) AXI Master1 (RW) Internal registers cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.4 Functional Description

6.4.1 L2 Cache User Configure

 System L2 Cache Base Address: Base Address: 0xCF000000  Turn off and Turn on L2C:  Turn off offset 0x100 (Base Address + 0x100) set to 0  Turn on offset 0x100 (Base Address + 0x100) set to 1  Early Write Response: The AXI protocol specifies that the write response can only be sent back to an AXI master when the last write data has been accepted. This optimization enables the L2C-310 to send the write response of certain write transactions as soon as the store buffer accepts the write address. This behavior is not compatible with the AXI protocol and is disabled by default. You enable this optimization by sett ing the Early BRESP Enable bit in the Auxiliary Control Register, bit[30]. The L2C-310 slave ports then send an early write response only if the input signal AWUSERSx[11], x = 0 or 1, is set to 1'b1 for the corresponding write transaction.

6.4.2 Initialization Sequence

As an example, a typical cache controller start-up programming sequence consists of the following register operations: 1. Write to the Auxiliary, Tag RAM Latency, Data RAM Latency, Pre-fetch, and Power Control registers using a read-modify-write to set up global configurations:  Associativity, Way Size  latencies for RAM accesses  allocation policy  Pre-fetch and power capabilities. 2. Secure write to the Invalidate by Way, offset 0x77C, to invalidate all entries in cache:  Write 0xFFFF to 0x77C  Poll cache maintenance register until invalidate operation is complete. 3. Write to the Lockdown D and Lockdown I Register 9 if required. 4. Write to interrupt clear register to clear any residual raw interrupts set. 5. Write to the Interrupt Mask Register if you want to enable interrupts. 6. Write to Control Register 1 with the LSB set to 1 to enable the cache. If you write to the Auxiliary, Tag RAM Latency, or Data RAM Latency Control Register with the L2 cache enabled, this results in a SLVERR. You must disable the L2 cache by writing to the Control Register 1 before Writing to the Auxiliary, Tag RAM Latency, or Data RAM Latency Control Register. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.5 Register Description

The base address of the Cache controller is 0xCF000000.

6.5.1.1 Register Map Summary

 Base Address: 0xCF00_0000 Register Offset Description Reset Value REG0_CACHE_ID 0000h Cache ID and type Register 0x4100_C4C8 REG0_CACHE_TYPE 0004h CACHE Type register 0x1A34_0340 REG1_CONTROL 0100h control register 0x0000_0000 AUX_CONTROL 0104h aux control register 0x0207_0000 REG1_TAG_RAM_CON TROL/ REG1_DATA_RAM_CO NTROL 0108h to 010Ch tag and data ram control register 0x0000_0777 REG2_EV_COUNTER_C TRL 0200h event counter control register 0x0000_0000 REG2_EV_COUNTER1_ CFG/ REG2_EV_COUNTER0_ CFG 0204h to 0208h event counter configuration register 1, 0 0x0000_0000 REG2_EV_COUNTER1/ REG2_EV_COUNTER0 020Ch to 0210h event counter registers 1, 0 0x0000_0000 REG2_INT_MASK 0214h Interrupt mask register 0x0000_0000 REG2_INT_MASK_STAT US 0218h Interrupt mask STATUS register 0x0000_0000 REG2_INT_RAW_STAT US 021Ch Interrupt RAW STATUS register 0x0000_0000 REG2_INT_CLEAR 0220h Interrupt CLEAR register 0x0000_0000 REG7_CACHE_SYNC 0730h CACHE SYNC 0x0000_0000 REG7_INV_PA 0770h INVALIDATE line by pa 0x0000_0000 REG7_INV_WAY 077Ch invalidate by way 0x0000_0000 REG7_CLEAN_PA 07B0h clean line by pa 0x0000_0000 REG7_CLEAN_INDEX 07B8h clean line by set/way 0x0000_0000 REG7_CLEAN_WAY 07BCh clean by way 0x0000_0000 REG7_CLEAN_INV_PA 07F0h clean and invalidate line by pa 0x0000_0000 REG7_CLEAN_INV_IND EX 07F8h clean and 07F8h line by set/way 0x0000_0000 REG7_CLEAN_INV_WA Y 07FCh clean and invalidate by way 0x0000_0000 REG9_D_LOCKDOWN0 0900h, 0908h, 0910h, 0918h, 0920h, 0928h, DATA Lockdown 0 to 7 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value 0930h, 0938h REG9_I_LOCKDOWN0~ 0904h, 090Ch, 0914h, 091Ch, 0924h, 092Ch, 0934h, 093Ch Instruction Lockdown 0 to 7 0x0000_0000 REG9_LOCK_LINE_EN 0950h lock down by line enable 0x0000_0000 REG9_UNLOCK_WAY 0954h Unlock lines by way 0x0000_0000 REG12_ADDR_FILTERI NG_START 0C00h address filtering start 0x0000_0000 REG12_ADDR_FILTERI NG_END 0C04h address filtering end 0x0000_0000 REG15_DEBUG_CTRL 0F40h debug ctrl 0x0000_0000 REG15_PREFETCH_CT RL 0F60h prefetch ctrl 0x0000_0004 REG15_POWER_CTRL 0F80h power ctrl 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.5.1.1.1 REG0_CACHE_ID

 Base Address: 0xCF00_0000  Address = Base Address + 0x0000h, Reset Value = 0x4100_C4C8 Name Bit Type Description Reset Value Implementer [31:24] R ARM 0x4100_C4C8 RSVD [23:16] R Reserved CACHE ID [15:10] R Cache Controller ID Partnum [9:6] R Part number 0x3 denotes Core Link Level 2 Cache Controller L2C-310 RTL RELEASE [5:0] R RTL release 0x8 denotes r3p2 code of the cache controller.

6.5.1.1.2 REG0_CACHE_TYPE

 Base Address: 0xCF00_0000  Address = Base Address + 0x0004h, Reset Value = 0x1A34_0340 Name Bit Type Description Reset Value data bank [31] R 0 = Data banking not implemented 1 = Data banking implemented 0x1A34_0340 RSVD [30:29] R Reserved ctype [28:25] R 4'b11xy x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0 y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0 H [24] R 0 = unified 1 = Havard dsize [23:19] R [23] SBZ/RAZ [19] SBZ/RAZ L2 associativity [18] R Read from Auxiliary Control Register[16] RSVD [17:14] R Reserved L2 cache line length [13:12] R 00 to 32 bytes isize [11:7] R [11] SBZ/RAZ [7] SBZ/RAZ l2 associativity [6] R Read from Auxiliary Control Register[16] reserved [5:2] R Reserved L2 cache line length [1:0] R 00 to 32 bytes cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.5.1.1.3 REG1_CONTROL

 Base Address: 0xCF00_0000  Address = Base Address + 0x0100h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:1] R Reserved 0x0000_0000 Enb [0] RW 0 = L2 Cache disabled. Default 1 = L2 Cache Enabled

6.5.1.1.4 AUX_CONTROL

 Base Address: 0xCF00_0000  Address = Base Address + 0x0104h, Reset Value = 0x0207_0000B Name Bit Type Description Reset Value RSVD [31] RW Reserved 0x0207_0000B early bresp [30] RW 0 = Early BRESP disabled. This is the default. 1 = Early BRESP enabled. instruction prefetch enable [29] RW 0 = Instruction pre-fetching disabled. This is the default. 1 = Instruction pre-fetching enabled. data prefetch enable [28] RW 0 = Data pre-fetching disabled. This is the default. 1 = Data pre-fetching enabled. ns interrupt access control [27] RW 0 = Interrupt Clear, 0x220, and Interrupt Mask, 0x214, can only be modified or read with secure accesses. This is the default. 1 = Interrupt Clear, 0x220, and Interrupt Mask, 0x214, can be modified or read with secure or non-secure accesses. ns lockdown [26] RW 0 = Lockdown registers cannot be modified using non- secure. This is the default. 1 = Non-secure accesses can write to the lockdown registers. cache replacement policy [25] RW 0 = Pseudo-random replacement using lfsr. 1 = Round-robin replacement. This is the default. force write allocate [24:23] RW 0b00 = Use AWCACHE attributes for WA. This is the default. 0b01 = Force no allocate, set WA bit always 0. 0b10 = Override *AWCACHE *attributes, set WA bit always 1, all cacheable write misses become write allocated. 0b11 = Internally mapped to 00. shared attribute override enable [22] RW 0 = Treats shared accesses. This is the default. 1 = Shared attribute internally ignored. parity enable [21] RW 0 = Disabled. This is the default. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 1 = Enabled. event monitor bus enable [20] RW 0 = Disabled. This is the default. 1 = Enabled. way-size [19:17] RW 0b000 = Reserved, internally mapped to 16 KB 0b001 = 16 KB 0b010 = 32 KB 0b011 = 64 KB 0b100 = 128 KB 0b101 = 256 KB 0b110 = 512 KB 0b111 = Reserved, internally mapped to 512 KB associativity [16] RW 0 = 8-way 1 = 16-way. RSVD [15:14] RW SBZ/RAZ shared attribute invalidate enable [13] RW 0 = Shared invalidate behavior disabled. This is the default. 1 = Shared invalidate behavior enabled, if Shared Attribute Override Enable bit not set. exclusive cache configuration [12] RW 0 = Disabled. This is the default. 1 = Enabled. store buffer device limitation enable [11] RW 0 = Store buffer device limitation disabled. Device writes can take all slots in store buffer. This is the default. 1 = Store buffer device limitation enabled. Device writes cannot take all slots in store buffer when connected to the Cortex-A9 MPCore There is always one available slot to service Normal Memory. high priority for so and dev reads enable [10] RW 0 = Strongly Ordered and Device reads have lower priority than cacheable accesses when arbitrated in the L2CC L2C-310 master This is the default. 1 = Strongly Ordered and Device reads get the highest priority when arbitrated in the L2C-310 master ports. RSVD [9:1] RW SBZ/RAZ full line of zero enable [0] RW 0 = Full line of write zero behavior disabled. This is the default. 1 = Full line of write zero behavior Enabled. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.5.1.1.5 REG1_TAG_RAM_CONTROL/ REG1_DATA_RAM_CONTROL

 Base Address: 0xCF00_0000  Address = Base Address + 0x0108h, 0x010Ch, Reset Value = 0x0000_0777 Name Bit Type Description Reset Value RSVD [31:11] RW Reserved 0x0000_0777 ram write access latency [10:8] RW Default value depends on the value of pl310_TAG_WRITE_LAT for reg1_tag_ram_control or pl310_DATA_WRITE_LAT for reg1_data_ram_control. 0b000 = 1 cycle of latency, there is no additional latency 0b001 = 2 cycles of latency 0b010 = 3 cycles of latency 0b011 = 4 cycles of latency 0b100 = 5 cycles of latency 0b101 = 6 cycles of latency 0b110 = 7 cycles of latency 0b111 = 8 cycles of latency RSVD [7] RW Reserved ram read access latency [6:4] RW 0b000 = 1 cycle of latency, there is no additional latency 0b001 = 2 cycles of latency 0b010 = 3 cycles of latency 0b011 = 4 cycles of latency 0b100 = 5 cycles of latency 0b101 = 6 cycles of latency 0b110 = 7 cycles of latency 0b111 = 8 cycles of latency RSVD [3] RW SBZ/RAZ ram setup latency [2:0] RW 0b000 = 1 cycle of latency, there is no additional latency 0b001 = 2 cycles of latency 0b010 = 3 cycles of latency 0b011 = 4 cycles of latency 0b100 = 5 cycles of latency 0b101 = 6 cycles of latency 0b110 = 7 cycles of latency 0b111 = 8 cycles of latency cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.5.1.1.6 REG2_EV_COUNTER_CTRL

 Base Address: 0xCF00_0000  Address = Base Address + 0x0200h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] RW SBZ/RAZ 0x0000_0000 counter reset [2:1] RW Always Read as zero. The following counters are reset when a 1 is written to the following bits: bit[2] = Event Counter1 reset bit[1] = Event Counter0 reset. event counter enable [0] RW 0 = Event Counting Disable. This is the default. 1 = Event Counting Enable.

6.5.1.1.7 REG2_EV_COUNTER1_CFG/ REG2_EV_COUNTER0_CFG

 Base Address: 0xCF00_0000  Address = Base Address + 0x0204h, 0x0208h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:6] RW Reserved 26'b0 counter event source [5:2] RW Event Encoding Counter Disabled: 0b'0000 CO: 0b'0001 DRHIT: 0b'0010 DRREQ: 0b'0011 DWHIT: 0b'0100 DWREQ: 0b'0101 DWTREQ: 0b'0110 IRHIT: 0b'0111 IRREQ: 0b'1000 WA: 0b'1001 IPFALLOC: 0b'1010 EPFHIT: 0b'1011 EPFALLOC: 0b'1100 SRRCVD: 0b'1101 SRCONF: 0b'1110 EPFRCVD: 0b'1111 4'b0 event counter interrupt generation [1:0] RW 0b00 = Disabled. This is the default. 0b01 = Enabled: Increment condition. 0b10 = Enabled: Overflow condition. 0b11 = Interrupt generation is disabled. 2'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.5.1.1.8 REG2_EV_COUNTER1/ REG2_EV_COUNTER0

 Base Address: 0xCF00_0000  Address = Base Address + 020Ch, 0x0210h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value Counter [31:0] RW Total of the event selected. If a counter reaches its maximum value, it saturates at that value until it is reset. 0x0000_0000

6.5.1.1.9 REG2_INT_MASK

 Base Address: 0xCF00_0000  Address = Base Address + 0x0214h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:9] RW Reserved 0x0000_0000 DECERR [8] RW DECERR from L3 0 = Masked, Default 1 = Enabled. SLVERR [7] RW SLVERR from L3 0 = Masked, Default 1 = Enabled. ERRRD [6] RW Error on L2 data RAM, Read 0 = Masked, Default 1 = Enabled. ERRRT [5] RW Error on L2 tag RAM, Read 0 = Masked, Default 1 = Enabled. ERRWD [4] RW Error on L2 data RAM, Write 0 = Masked, Default 1 = Enabled. ERRWT [3] RW Error on L2 tag RAM, Write 0 = Masked, Default 1 = Enabled. PARRD [2] RW Parity Error on L2 data RAM, Read 0 = Masked, Default 1 = Enabled. PARRT [1] RW Parity Error on L2 tag RAM, Read 0 = Masked, Default 1 = Enabled. ECNTR [0] RW Even Counter1 and Event Counter 0 Overflow Increment 0 = Masked, Default 1 = Enabled. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.5.1.1.10 REG2_INT_MASK_STATUS

 Base Address: 0xCF00_0000  Address = Base Address + 0x0218h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:9] R Reserved 0x0000_0000 DECERR [8] R DECERR from L3 HIGH: If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW: If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. SLVERR [7] R SLVERR from L3 HIGH: If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW: If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. ERRRD [6] R Error on L2 data RAM, Read HIGH: If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW: If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. ERRRT [5] R Error on L2 tag RAM, Read HIGH: If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW: If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. ERRWD [4] R Error on L2 data RAM, Write HIGH: If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW: If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. ERRWT [3] R Error on L2 tag RAM, Write HIGH: If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW: If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. PARRD [2] R Parity Error on L2 data RAM, Read HIGH: If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW: If the bits read LOW, either no interrupt has been generated, or the interrupt is masked. PARRT [1] R Parity Error on L2 tag RAM, Read HIGH: If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW: If the bits read LOW, either no interrupt has cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value been generated, or the interrupt is masked. ECNTR [0] R Even Counter1 and Event Counter 0 Overflow Increment HIGH: If the bits read HIGH, they reflect the status of the input lines triggering an interrupt. LOW: If the bits read LOW, either no interrupt has been generated, or the interrupt is masked.

6.5.1.1.11 REG2_INT_RAW_STATUS

 Base Address: 0xCF00_0000  Address = Base Address + 0x021Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:9] R Reserved 0x0000_0000 DECERR [8] R DECERR from L3 HIGH: If the bits read HIGH, they reflect the status of the input lines riggering an interrupt. LOW: If the bits read LOW, no interrupt has been generated. SLVERR [7] R SLVERR from L3 HIGH: If the bits read HIGH, they reflect the status of the input lines riggering an interrupt. LOW: If the bits read LOW, no interrupt has been generated. ERRRD [6] R Error on L2 data RAM, Read HIGH: If the bits read HIGH, they reflect the status of the input lines riggering an interrupt. LOW: If the bits read LOW, no interrupt has been generated. ERRRT [5] R Error on L2 tag RAM, Read HIGH: If the bits read HIGH, they reflect the status of the input lines riggering an interrupt. LOW: If the bits read LOW, no interrupt has been generated. ERRWD [4] R Error on L2 data RAM, Write HIGH: If the bits read HIGH, they reflect the status of the input lines riggering an interrupt. LOW: If the bits read LOW, no interrupt has been generated. ERRWT [3] R Error on L2 tag RAM, Write HIGH: If the bits read HIGH, they reflect the status of the input lines riggering an interrupt. LOW: If the bits read LOW, no interrupt has been generated. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value PARRD [2] R Parity Error on L2 data RAM, Read HIGH: If the bits read HIGH, they reflect the status of the input lines riggering an interrupt. LOW: If the bits read LOW, no interrupt has been generated. PARRT [1] R Parity Error on L2 tag RAM, Read HIGH: If the bits read HIGH, they reflect the status of the input lines riggering an interrupt. LOW: If the bits read LOW, no interrupt has been generated. ECNTR [0] R Even Counter1 and Event Counter 0 Overflow Increment HIGH: If the bits read HIGH, they reflect the status of the input lines riggering an interrupt. LOW: If the bits read LOW, no interrupt has been generated.

6.5.1.1.12 REG2_INT_CLEAR

 Base Address: 0xCF00_0000  Address = Base Address + 0x0220h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:9] W Reserved 0x0000_0000 DECERR [8] W DECERR from L3 When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. SLVERR [7] W SLVERR from L3 When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. ERRRD [6] W Error on L2 data RAM, Read When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. ERRRT [5] W Error on L2 tag RAM, Read When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. ERRWD [4] W Error on L2 data RAM, Write When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. ERRWT [3] W Error on L2 tag RAM, Write cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. PARRD [2] W Parity Error on L2 data RAM, Read When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. PARRT [1] W Parity Error on L2 tag RAM, Read When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect. ECNTR [0] W Even Counter1 and Event Counter 0 Overflow Increment When a bit is written as 1, it clears the corresponding bit in the Raw Interrupt Status Register. When a bit is written as 0, it has no effect.

6.5.1.1.13 REG7_CACHE_SYNC

 Base Address: 0xCF00_0000  Address = Base Address + 0x0730h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:1] RW Reserved 0x0000_0000 cachesync [0] RW Cache SYNC cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.5.1.1.14 REG7_INV_PA

 Base Address: 0xCF00_0000  Address = Base Address + 0x0770h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value TAG [31:12] RW Tag 0x0000_0000 INDEX [11:5] RW Index RSVD [4:1] RW Reserved Clean [0] RW Invalidate 0 = Idle 1 = Enable Invalidate

6.5.1.1.15 REG7_INV_WAY

 Base Address: 0xCF00_0000  Address = Base Address + 0x077Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value way [31:28] RW Way 0x0000_0000 RSVD [27:12] RW Reserved INDEX [11:5] RW Index RSVD [4:1] RW Reserved Clean [0] RW Invalidate 0 = Idle 1 = Enable Invalidate

6.5.1.1.16 REG7_CLEAN_PA

 Base Address: 0xCF00_0000  Address = Base Address + 0x07B0h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value TAG [31:12] RW Tag 0x0000_0000 INDEX [11:5] RW Index RSVD [4:1] RW Reserved Clean [0] RW Invalidate 0 = Idle 1 = Enable Invalidate cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.5.1.1.17 REG7_CLEAN_INDEX

 Base Address: 0xCF00_0000  Address = Base Address + 0x07B8h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value way [31:28] RW Way 0x0000_0000 RSVD [27:12] RW Reserved INDEX [11:5] RW Index reserved [4:1] RW Reserved

6.5.1.1.18 REG7_CLEAN_WAY

 Base Address: 0xCF00_0000  Address = Base Address + 0x07BCh, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Reserved 0x0000_0000 WAY Bits [15:0] RW Way Bits 8WAY: 0xFF 16WAY: 0xFFFF

6.5.1.1.19 REG7_CLEAN_INV_PA

 Base Address: 0xCF00_0000  Address = Base Address + 0x07F0h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value TAG [31:12] RW Tag 0x0000_0000 INDEX [11:5] RW Index RSVD [4:1] RW Reserved Clean [0] RW Invalidate 0 = Idle 1 = Enable Invalidate cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.5.1.1.20 REG7_CLEAN_INV_INDEX

 Base Address: 0xCF00_0000  Address = Base Address + 0x07F8h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value way [31:28] RW Way 0x0000_0000 RSVD [27:12] RW Reserved INDEX [11:5] RW Index RSVD [4:1] RW Reserved

6.5.1.1.21 REG7_CLEAN_INV_WAY

 Base Address: 0xCF00_0000  Address = Base Address + 0x07FCh, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Reserved 0x0000_0000 WAY Bits [15:0] RW Way Bits 8WAY: 0xFF 16WAY: 0xFFFF

6.5.1.1.22 REG9_D_LOCKDOWN 0~7

 Base Address: 0xCF00_0000  Address = Base Address + 0x0900h, 0x0908h, 0x0910h, 0x0918h, 0x0920h, 0x0928h, 0x0930h, 0x0938h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Reserved 0x0000_0000 DATALOCK [15:0] RW Way Bits 8WAY: 0xFF 16WAY: 0xFFFF cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.5.1.1.23 REG9_I_LOCKDOWN 0~7

 Base Address: 0xCF00_0000  Address = Base Address + 0x0904h, 0x090Ch, 0x0914h, 0x091Ch, 0x0924h, 0x092Ch, 0x0934h, 0x093Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Reserved 0x0000_0000 INSTRLOCK [15:0] RW Way Bits 8WAY: 0xFF 16WAY: 0xFFFF

6.5.1.1.24 REG9_LOCK_LINE_EN

 Base Address: 0xCF00_0000  Address = Base Address + 0x0950h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSCD [31:1] RW Reserved 0x0000_0000 LOCKDOWN by LINE ENB [0] RW 0 = Lockdown by line disabled. This is default 1 = Lockdown by line enabled

6.5.1.1.25 REG9_UNLOCK_WAY

 Base Address: 0xCF00_0000  Address = Base Address + 0x0954h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Reserved 0x0000_0000 UNlock all lines by way [15:0] RW For all bits: 0 = Unlock all lines disabled. This is the default 1 = Unlock all lines operation in progress for the corresponding way

6.5.1.1.26 REG12_ADDR_FILTERING_START

 Base Address: 0xCF00_0000  Address = Base Address + 0x0C00h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value filtering start [31:20] RW Address filtering start address for bits[31:20] of the filtering address 0x0000_0000 RSVD [19:1] RW SBZ/RAZ filter enb [0] RW Address filter enable cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

6.5.1.1.27 REG12_ADDR_FILTERING_END

 Base Address: 0xCF00_0000  Address = Base Address + 0x0C04h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value filtering start [31:20] RW Address filtering start address for bits[31:20] of the filtering address 0x0000_0000 RSVD [19:0] RW SBZ/RAZ

6.5.1.1.28 REG15_DEBUG_CTRL

 Base Address: 0xCF00_0000  Address = Base Address + 0x0F40h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] RW Reserved 0x0000_0000 SPNIDEN [2] RW Reads value of SPNIDEN Input. DWB [1] RW Disable Write-back force WT 0 = Enable write-back behavior. This is the default. 1 = Force write-through behavior DCL [0] RW Disable cache line fill 0 = Enable cache line fills. This is the default 1 = Disable cache line fills

6.5.1.1.29 REG15_PREFETCH_CTRL

 Base Address: 0xCF00_0000  Address = Base Address + 0x0F60h, Reset Value = 0x0000_0004 Name Bit Type Description Reset Value RSVD [31] RW Reserved 0x0000_0004 Double line fill enable [30] RW You can set the following options for this register bit: 0 = The L2CC always issues 4x64-bit read bursts to L3 on reads that miss in the L2cache. This is the default. 1 = The L2CC issues 8x64-bit read bursts to L3 on reads that miss in the L2 cache. Instruction prefetch enable [29] RW You can set the following options for this register bit: 0 =: Instruction pre-fetching disabled. This is the default. 1 =: Instruction pre-fetching enabled. Data prefetch enable [28] RW You can set the following options for this register bit: 0 = Data pre-fetching disabled. This is the default. 1 = Data pre-fetching enabled. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 6 System L2 Cache (PL-310 L2C) 6-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Double line fill on wrap read disable [27] RW You can set the following options for this register bit: 0 = Double line fill on WRAP read enabled. This is the default. 1 = Double line fill on wrap read disabled. RSVD [26:25] RW SBZ/RAZ prefetch drop enable [24] RW You can set the following options for this register bit: 0 = The L2CC does not discard pre-fetch reads issued to L3. This is default 1 = The L2CC discards pre-fetch reads issued to L3 when there is a resource conflict with explicit reads. incr double linefill enable [23] RW 0 = The L2CC does not issue INCR 8x64-bit read bursts to L3 on reads that miss in the L2 cache. This is the default. 1 = The L2CC can issue INCR 8x64-bit read bursts to L3 on reads that miss in the L2cache. RSVD [22] RW SBZ/RAZ Not same ID on exclusive sequence enable [21] RW You can set following options for this register bit: 0 = Read and write portions of a non cacheable exclusive sequence have the same AXI ID when issued to L3. This is the default. 1 = Read and write portions of a non cacheable exclusive sequence do not have the same AXI ID when issued to L3. RSVD [20:5] RW SBZ/RAZ prefetch offset [4:0] RW Default value = 0b00000 You must only use the pre-fetch offset values of 0-7, 15, 23, and 31 for these bits. The L2C-310 does not support the other values.

6.5.1.1.30 REG15_POWER_CTRL

 Base Address: 0xCF00_0000  Address = Base Address + 0x0F80h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:2] RW Reserved 0x0000_0000 dynamic_clk_gating [1] RW Dynamic Clock gating Enable. 0 = Disabled. This is the default 1 = Enabled stanby mode en [0] RW Standby mode enable. 0 = Disabled. This is the default 1 = Enabled cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 7 Secure JTAG 7-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

7 Secure JTAG

7.1 Overview

The Secure JTAG consists of an Authentication & Authorization module an Access Provider. Secure JTAG Device support protection by user password can be unlocked by providing the correct password. Secure JTAG Connected with CoreSight at AHB AP. To activate the password unlock mechanism, the password exchange request must be applied to the AHB AP of CoreSight.

7.2 Features

The Secure JTAG features: Authentication & Authorization Debug Module. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 7 Secure JTAG 7-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

7.3 Block Diagram

Figure 7-1 Secure JTAG Block Diagram

7.4 Secure JTAG User Configure

System L2 Cache Base Address: JTAG AHB-AP BASE Address 0x00000000 Coresight JTAG DAP Secure JTAG CPU Password Write Debug Hashed Password Authentication Authorization Ext. JTAG cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8 DMA

8.1 Overview

The DMA Controller (DMAC) is an Advanced Microcontroller Bus Architecture (AMBA) block that connects to the Advanced High-performance Bus (AHB). There is an AHB slave interface for programming the DMAC and 2 AHB masters for data transfer. There are two DMAC in S5P4418 and each DMAC has eight channels, which can buffer up to 4 words each. Each channel can transfer data through either of the AHB Master interfaces with the programmed data width and endianness. The DMAC supports 16 DMA requestors, and generates individually maskable interrupts for Terminal count and transfer error for each channel. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.2 Features

 16 DMA channels. Each channel can support a unidirectional transfer.  16 DMA requests. The DMAC provides 16 peripheral DMA request lines.  Single DMA and burst DMA request signals. Each peripheral connected to the DMAC can assert either a burst DMA request or a single DMA request. You set the DMA burst size by programming the DMAC.  Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers.  Scatter or gather DMA support through the use of linked lists.  Hardware DMA channel priority. Each DMA channel has a specific hardware priority. DMA channel 0 has the highest priority and channel 7 has the lowest priority. If requests from two channels become active at the same time, the channel with the highest priority is serviced first.  AHB slave DMA programming interface. You program the DMAC by writing to the DMA control registers over the AHB slave interface.  Two AHB bus masters for transferring data. Use these interfaces to transfer data when a DMA request goes active.  Incrementing or non-incrementing addressing for source and destination.  Programmable DMA burst size. You can program the DMA burst size to transfer data more efficiently. The burst size is usually set to half the size of the FIFO in the peripheral.  Internal four word FIFO per channel.  Supports eight, 16, and 32-bit wide transactions.  Big-endian and little-endian support. The DMAC defaults to little-endian mode on reset.  Separate and combined DMA error and DMA count interrupt requests. You can generate an interrupt to the processor on a DMA error or when a DMA count has reached 0. This is usually used to indicate that a transfer has finished. There are three interrupt request signals to do this:  DMACINTTC signals when a transfer has completed.  DMACINTERR signals when an error has occurred.  DMACINTR combines both the DMACINTTC and DMACINTERR interrupt request signals. You can use the DMACINTR interrupt request in systems that have few interrupt controller request inputs.  Interrupt masking. You can mask the DMA error and DMA terminal count interrupt re quests.  Raw interrupt status. You can read the DMA error and DMA count raw interrupt status prior to masking.  Test registers for use in block and integration system level testing.  Identification registers that uniquely identify the DMAC. An operating system can use these to automatically configure itself. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.3 Block Diagram

Figure 8-1 DMAC Block Diagram cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.4 Functional Description

8.4.1 Software Considerations

You must take into account the following software considerations when programming the DMAC:  There must not be any write-operation to Channel registers in an active channel after the channel enable is made HIGH. If you must reprogram any DMAC channel parameters, you must reprogram after disabling the DMAC channel.  If the source width is less than the destination width, the TransferSize value multiplied by the source width must be an integral multiple of the destination width.  When the source peripheral is the flow controller and the source width is less than the destination width, the number of transfers that the source peripheral performs, before asserting a DMACLSREQ *or *DMACLBREQ, must be so that the number of transfers multiplied by the source width is an integral multiple of the destination width. If this case is violated, the data can get stuck and lost in the FIFO causing UNPREDICTABLE results. You can abort the transfer by disabling the relevant DMAC channel.  You must not program the SrcPeripheral and DestPeripheral bit fields in the DMACCxConfig Register with any value greater than 15. See Channel Configuration Registers.  The SWidth and DWidth bit fields in the DMACCxControl Register must not indicate more than a 32-bit wide peripheral. See Channel Control Registers.  After the software disables a channel by clearing the Channel Enable bit in the DMACCxConfig Register, see Channel Configuration Registers, it must re-enable the bit only after it has polled a 0 in the corresponding DMACEnbldChns Register bit, see 'Enabled Channel Register. This is because the actual disabling does not immediately happen with the clearing of Channel Enable bit. You must accommodate the latency of the on going AHBburst.  The LLI field in the DMACCxLLIReg Register must not indicate an address greater than 0xFFFFFFF0, otherwise the four-word LLI burst wraps over at 0x00000000 and the LLI data structure is not in contiguous memory locations. See Channel Linked List Item Registers.  When the transfer size programmed in the DMAC is greater than the depth of the FIFO in a source or destination peripheral, you must only program the DMAC for non-incrementing address generation.  A peripheral is expected to deassert any DMACSREQ, DMACBREQ, DMACLSREQ, or DMACLBREQ signals on receiving the DMACCLR signal irrespective of the request the DMACCLR was asserted in response to. This is because DMACCLR is not specific to a single-request signal, DMACSREQ, or burst-request signal, DMACSBEQ. The handshaking of DMACCLR is achieved with a logical OR of all the DMA requests in the DMAC. NOTE: It is illegal for a peripheral to give a new DMACSREQ or DMACBREQ signal while DMACCLR is HIGH. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  If you program the TransferSize field in the DMACCxControl Register, see Channel Control Registers, as zero, and the DMAC is the flow controller, the TransferSize field has no meaning in ot her flow-control modes, then the channel does not initiate any transfers. It is your responsibility to disable the channel by writing into the channel enable bit of the DMACCxConfig Register and reprogramming the channel again.  You must not run the normal read-write tests on the DMACCxControl Register, see Channel Control Registers, because the TransferSize field is not a typical write and read-back register field. While writing, the TransferSize bit-field is like a control register because it determines how many transfers the DMAC performs. However, during read-back, TransferSize behaves like a status register because it returns the number of remaining transfers in terms of source width. So when TransferSize is read back, it returns the number of destination-transfer-completed stored in a separate counter called TrfSizeDst multiplied by a factor. The same physical register is not being written into and read from, and normal write and read -back tests are not applicable.  In the destination flow control mode, with peripheral-to-peripheral transfer, if sufficient data is present in the channel FIFO to service a DMACLSREQ or DMACLBREQ request raised by a destination peripheral without requiring data to be fetched from the source peripheral, then the source periphe ral is issued a *DMACTC.  For destination flow controlled case, peripheral-to-peripheral transfer, with DWidth < SWidth, the number of data bytes requested by the destination peripheral must be an integral multiple of Swidth expressed in bytes. If you do not ensure this, then the DMAC might fetch more data from the source peripheral than is required. This can result in data loss.  At the end of accesses corresponding to low-priority channels, an IDLE cycle is inserted on the AHB bus to enable other masters to access the bus. This ensures that a low-priority channel does not monopolize the bus. It does, however, mean that the bus might be occupied by transactions corresponding to a low priority for up to 16 cycles in the worst case. This applies to all transfer configurations, including memory-to-memory transfers. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.4.2 Programmer's Model

8.4.2.1 About the programmer's Model

The DMAC enables the following types of transactions:  memory-to-memory  memory-to-peripheral  peripheral-to-memory  peripheral-to-peripheral. Each DMA stream is configured to provide unidirectional DMA transfers for a single source and destination. For example, a bidirectional serial port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and you can access them through the same AHB master, or one area by each master. The base address of the DMAC is not fixed, and can be different for any particular system implementation. However, the offset of any particular register from the base address is fixed. Register fields The following applies to the registers that the DMAC uses:  You must not access reserved or unused address locations because this can result in unpredictable behavior of the device.  You must write reserved or unused bits of registers as zero, and ignore them on read unless otherwise stated in the relevant text.  A system or power-on reset resets all register bits to logic 0 unless otherwise stated in the relevant text.  All registers support read and write accesses unless otherwise stated in the relevant text. A write updates the contents of a register, and a read returns the contents of the register.  You can only access registers defined in this document using word reads and word wri tes, unless otherwise stated in the relevant text. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.4.2.2 Programming the DMAC

Enable the DMAC by setting the DMA Enable, E, bit in the DMAC Configuration Register. See Configuration Register. Disabling DMAC To disable the DMAC: 1. Read the DMACEnbldChns Register and ensure that you have disabled all the DMA channels. If any channels are active, see disabling a DMA channel. 2. Disable the DMAC by writing 0 to the DMA Enable bit in the DMAC Configuration Register. See 'Configuration Register. Enabling a DMA channel Enable the DMA channel by setting the Channel Enable bit in the relevant DMA channel Configuration Register. See Channel Configuration Registers. NOTE: You must fully initialize the channel before you enable it. Additionally, you must set the Enable bit of the DMAC before you enable any channels. Disabling a DMA channel You can disable a DMA channel in the following ways: 1. Write directly to the Channel Enable bit. NOTE: You lose any outstanding data in the FIFOs if you use this method. 2. Use the Active and Halt bits in conjunction with the Channel Enable bit. 3. Wait until the transfer completes. The channel is then automatically disabled. Disabling a DMA channel and losing data in the FIFO Clear the relevant Channel Enable bit in the relevant channel Configuration Register. See Channel Configuration Registers. The current AHB transfer, if one is in progress, completes and the channel is disabled. NOTE: You lose any data in the FIFO. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Disabling a DMA channel without losing data in the FIFO To disable a DMA channel without losing data in the FIFO: 1. Set the Halt bit in the relevant channel Configuration Register. See Channel Configuration Registers. This causes any subsequent DMA requests to be ignored. 2. Poll the Active bit in the relevant channel Configuration Register until it reaches0. This bit indicates whether there is any data in the channel that has to be transferred. 3. Clear the Channel Enable bit in the relevant channel Configuration Register. Setting up a new DMA transfer To set up a new DMA transfer: 1. If the channel is not set aside for the DMA transaction:  Read the DMACEnbldChns Register and determine the channels that are inactive. See Enabled Channel Register.  Choose an inactive channel that has the necessary priority. 2. Program the DMAC. Halting a DMA channel Set the Halt bit in the relevant DMA channel Configuration Register. The current source request is serviced. Any subsequent source DMA requests are ignored until the Halt bitis cleared. Programming a DMA channel To program a DMA channel: 1. Choose a free DMA channel with the necessary priority. DMA channel 0 has the highest priority and DMA channel 7 has the lowest priority. 2. Clear any pending interrupts on the channel you want to use by writing to the DMAC IntTCClear and DMAC IntErrClr Registers. See Interrupt Terminal Count Clear Register and Interrupt Error Clear Register. The previous channel operation might have left interrupts active. 3. Write the source address into the DMACCxSrcAddr Register. See Channel Source Address Registers. 4. Write the destination address into the DMAC CxDestAddr Register. See Channel Destination Address Registers. 5. Write the address of the next LLI into the DMACCxLLI Register. See Channel Linked List Item Registers. If the transfer consists of a single packet of data, you must write 0 into this register. 6. Write the control information into the DMACCxControl Register. See ChannelControl Registers. 7. Write the channel configuration information into the DMACCxConfiguration Register. See 'Channel Configuration Registers. If the Enable bit is set, then the DMA channel is automatically enabled. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.4.2.3 Register Name Description

Table 8-1 DMAC0 Register Summary  Base Address: 0xC000_0000 Name Offset Description Reset value DMACIntStatus 0x0000 Interrupt Status Register 0x00 DMACIntTCStatus 0x0004 Interrupt Terminal Count Status Register 0x00 DMACIntTCClear 0x0008 Interrupt Terminal Count Clear Register – DMACIntErrorStatus 0x000C Interrupt Error Status Register 0x00 DMACIntErrClr 0x0010 Interrupt Error Clear Register – DMACRawIntTCStatus 0x0014 Raw Interrupt Terminal Count Status Register – DMACRawIntErrorStatus 0x0018 Raw Error Interrupt Status Register – DMACEnbldChns 0x001C Enabled Channel Register 0x00 DMACSoftBReq 0x0020 Software Burst Request Register 0x0000 DMACSoftSReq 0x0024 Software Single Request Register 0x0000 DMACSoftLBReq 0x0028 Software Last Burst Request Register 0x0000 DMACSoftLSReq 0x002C Software Last Single Request Register 0x0000 DMACConfiguration 0x0030 Configuration Register 0b000 DMACSync 0x0034 Synchronization Register 0x0000 DMACC0SrcAddr 0x0100 Channel Source Address Registers 0x00000000 DMACC0DestAddr 0x0104 Channel Destination Address Registers 0x00000000 DMACC0LLI 0x0108 Channel Linked List Item Registers 0x00000000 DMACC0Control 0x010C Channel Control Registers 0x00000000 DMACC0Configuration 0x0110 Channel Configuration Registers 0x0000 DMACC1SrcAddr 0x0120 Channel Source Address Registers 0x00000000 DMACC1DestAddr 0x0124 Channel Destination Address Registers 0x00000000 DMACC1LLI 0x0128 Channel Linked List Item Registers 0x00000000 DMACC1Control 0x012C Channel Control Registers 0x00000000 DMACC1Configuration 0x0130 Channel Configuration Registers 0x0000 DMACC2SrcAddr 0x0140 Channel Source Address Registers 0x00000000 DMACC2DestAddr 0x0144 Channel Destination Address Registers 0x00000000 DMACC2LLI 0x0148 Channel Linked List Item Registers 0x00000000 DMACC2Control 0x014C Channel Control Registers 0x00000000 DMACC2Configuration 0x0150 Channel Configuration Registers 0x0000 DMACC3SrcAddr 0x0160 Channel Source Address Registers 0x00000000 DMACC3DestAddr 0x0164 Channel Destination Address Registers 0x00000000 DMACC3LLI 0x0168 Channel Linked List Item Registers 0x00000000 DMACC3Control 0x016C Channel Control Registers 0x00000000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Offset Description Reset value DMACC3Configuration 0x0170 Channel Configuration Registers 0x0000 DMACC4SrcAddr 0x0180 Channel Source Address Registers 0x00000000 DMACC4DestAddr 0x0184 Channel Destination Address Registers 0x00000000 DMACC4LLI 0x0188 Channel Linked List Item Registers 0x00000000 DMACC4Control 0x018C Channel Control Registers 0x00000000 DMACC4Configuration 0x0190 Channel Configuration Registers 0x0000 DMACC5SrcAddr 0x01A0 Channel Source Address Registers 0x00000000 DMACC5DestAddr 0x01A4 Channel Destination Address Registers 0x00000000 DMACC5LLI 0x01A8 Channel Linked List Item Registers 0x00000000 DMACC5Control 0x01AC Channel Control Registers 0x00000000 DMACC5Configuration 0x01B0 Channel Configuration Registers 0x0000 DMACC6SrcAddr 0x01C0 Channel Source Address Registers 0x00000000 DMACC6DestAddr 0x01C4 Channel Destination Address Registers 0x00000000 DMACC6LLI 0x01C8 Channel Linked List Item Registers 0x00000000 DMACC6Control 0x01CC Channel Control Registers 0x00000000 DMACC6Configuration 0x01D0 Channel Configuration Registers 0x0000 DMACC7SrcAddr 0x01E0 Channel Source Address Registers 0x00000000 DMACC7DestAddr 0x01E4 Channel Destination Address Registers 0x00000000 DMACC7LLI 0x01E8 Channel Linked List Item Registers 0x00000000 DMACC7Control 0x01EC Channel Control Registers 0x00000000 DMACC7Configuration 0x01F0 Channel Configuration Registers 0x0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Table 8-2 DMAC1 Register Summary  Base Address: 0xC000_1000 Name Offset Description Reset value DMACIntStatus 0x0000 Interrupt Status Register 0x00 DMACIntTCStatus 0x0004 Interrupt Terminal Count Status Register 0x00 DMACIntTCClear 0x0008 Interrupt Terminal Count Clear Register – DMACIntErrorStatus 0x000C Interrupt Error Status Register 0x00 DMACIntErrClr 0x0010 Interrupt Error Clear Register – DMACRawIntTCStatus 0x0014 Raw Interrupt Terminal Count Status Register – DMACRawIntErrorStatus 0x0018 Raw Error Interrupt Status Register – DMACEnbldChns 0x001C Enabled Channel Register 0x00 DMACSoftBReq 0x0020 Software Burst Request Register 0x0000 DMACSoftSReq 0x0024 Software Single Request Register 0x0000 DMACSoftLBReq 0x0028 Software Last Burst Request Register 0x0000 DMACSoftLSReq 0x002C Software Last Single Request Register 0x0000 DMACConfiguration 0x0030 Configuration Register 0b000 DMACSync 0x0034 Synchronization Register 0x0000 DMACC0SrcAddr 0x0100 Channel Source Address Registers 0x00000000 DMACC0DestAddr 0x0104 Channel Destination Address Registers 0x00000000 DMACC0LLI 0x0108 Channel Linked List Item Registers 0x00000000 DMACC0Control 0x010C Channel Control Registers 0x00000000 DMACC0Configuration 0x0110 Channel Configuration Registers 0x0000 DMACC1SrcAddr 0x0120 Channel Source Address Registers 0x00000000 DMACC1DestAddr 0x0124 Channel Destination Address Registers 0x00000000 DMACC1LLI 0x0128 Channel Linked List Item Registers 0x00000000 DMACC1Control 0x012C Channel Control Registers 0x00000000 DMACC1Configuration 0x0130 Channel Configuration Registers 0x0000 DMACC2SrcAddr 0x0140 Channel Source Address Registers 0x00000000 DMACC2DestAddr 0x0144 Channel Destination Address Registers 0x00000000 DMACC2LLI 0x0148 Channel Linked List Item Registers 0x00000000 DMACC2Control 0x014C Channel Control Registers 0x00000000 DMACC2Configuration 0x0150 Channel Configuration Registers 0x0000 DMACC3SrcAddr 0x0160 Channel Source Address Registers 0x00000000 DMACC3DestAddr 0x0164 Channel Destination Address Registers 0x00000000 DMACC3LLI 0x0168 Channel Linked List Item Registers 0x00000000 DMACC3Control 0x016C Channel Control Registers 0x00000000 DMACC3Configuration 0x0170 Channel Configuration Registers 0x0000 DMACC4SrcAddr 0x0180 Channel Source Address Registers 0x00000000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Offset Description Reset value DMACC4DestAddr 0x0184 Channel Destination Address Registers 0x00000000 DMACC4LLI 0x0188 Channel Linked List Item Registers 0x00000000 DMACC4Control 0x018C Channel Control Registers 0x00000000 DMACC4Configuration 0x0190 Channel Configuration Registers 0x0000 DMACC5SrcAddr 0x01A0 Channel Source Address Registers 0x00000000 DMACC5DestAddr 0x01A4 Channel Destination Address Registers 0x00000000 DMACC5LLI 0x01A8 Channel Linked List Item Registers 0x00000000 DMACC5Control 0x01AC Channel Control Registers 0x00000000 DMACC5Configuration 0x01B0 Channel Configuration Registers 0x0000 DMACC6SrcAddr 0x01C0 Channel Source Address Registers 0x00000000 DMACC6DestAddr 0x01C4 Channel Destination Address Registers 0x00000000 DMACC6LLI 0x01C8 Channel Linked List Item Registers 0x00000000 DMACC6Control 0x01CC Channel Control Registers 0x00000000 DMACC6Configuration 0x01D0 Channel Configuration Registers 0x0000 DMACC7SrcAddr 0x01E0 Channel Source Address Registers 0x00000000 DMACC7DestAddr 0x01E4 Channel Destination Address Registers 0x00000000 DMACC7LLI 0x01E8 Channel Linked List Item Registers 0x00000000 DMACC7Control 0x01EC Channel Control Registers 0x00000000 DMACC7Configuration 0x01F0 Channel Configuration Registers 0x0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.4.2.4 Peripheral DMA Request ID

Table 8-3 Peripheral DMA Request ID Index Description Index Description

0 UART1 Tx 16 I2S2 Tx

1 UART1 Rx 17 I2S2 Rx

2 UART0 Tx 18 AC97 PCMOUT

3 UART0 Rx 19 AC97 PCMIN

4 UART2 Tx 20 AC97 MICIN

5 UART2 Rx 21 SPDIF RX

6 SSP0 Tx 22 SPDIF TX

7 SSP0 Rx 23 MPEGTSI0

8 SSP1 Tx 24 MPEGTSI1

9 SSP1 Rx 25 MPEGTSI2

10 SSP2 Tx 26 MPEGTSI4

11 SSP2 Rx 27 CRYPTO BR

12 I2S0 Tx 28 CRYPTO BW

13 I2S0 Rx 29 CRYPTO HR

14 I2S1 Tx 30 Reserved

15 I2S1 Rx 31 Reserved

8.4.2.5 Address Generation

Address generation can be either incrementing or non-incrementing. NOTE: Address wrapping is not supported. Bursts do not cross the 1 KB address boundary. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.4.2.6 Scatter/gather

Scatter/gather is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas in memory. You must set the DMACCxLLI Register to 0 if you do not require scatter/gather. For more information about scatter/gather DMA, see Appendix B DMA Interface. Linked list items An LLI consists of four words. These words are organized in the following order: 1. DMACCxSrcAddr 2. DMACCxDestAddr 3. DMACCxLLI 4. DMACCxControl NOTE: The DMACCx Configuration Channel Configuration Register is not part of the LLI. Programming the DMAC for scatter/gather DMA To program the DMAC for scatter/gather DMA: 1. Write the LLIs for the complete DMA transfer to memory. Each LLI contains four words:  source address  destination address  pointer to next LLI  control word. The last LLI has its linked list word pointer set to 0. 1. Choose a free DMA channel with the required priority. DMA channel 0 has the highest priority and DMA channel 7 the lowest priority. 2. Write the first LLI, previously written to memory, to the relevant channel in the DMAC. 3. Write the channel configuration information to the channel configuration register and set the Channel Enable bit. The DMAC then transfers the first and then subsequent packets of data as each LLI are loaded. 4. An interrupt can be generated at the end of each LLI depending on the Terminal Count bit in the DMACCxControl Register. If this bit is set, an interrupt is generated at the end of the relevant LLI. You must then service the interrupt request, and you must set the relevant bit in the DMACIntTCClear Register to clear the interrupt. If so, you must service this interrupt request and you must set the relevant IntTCClear bit in the DMACIntTCClr Register to clear the interrupt request interrupt. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. A chain of descriptors is built up, each one pointing to the next in the series. To initialize the DMA stream, the first LLI, 0x20000, is programmed into the DMAC. When the first packet of data has been transf erred, the next LLI is automatically loaded. The final LLI is stored at 0x20070 and contains:  source start address 0x11200  destination address set to the destination peripheral address  transfer width, word, 32-bit  transfer size, 3072 bytes, 0xC00  source and destination burst sizes, 16 transfers  next LLI address, 0x0. Because the next LLI address is set to zero, this is the last descriptor, and the DMA channel is disabled after transferring the last item of data. The channel is probably set to generate an in terrupt at this point to indicate to the ARM processor that the channel can be reprogrammed.

8.4.2.7 Interrupt requests

Interrupt requests can be generated when an AHB error is encountered, or at the end of a transfer, terminal count, after all the data corresponding to the current LLI has been transferred to the destination. The interrupts can be masked by programming the relevant bits on the relevant DMACCxControl and DMACCxConfiguration Channel Registers. Interrupt Status Registers are provided. They group the interrupt requests from all the DMA channels prior to interrupt masking, DMACRawIntTCStatus, DMACRawIntErrorStatus, and after interrupt masking, DMACIntTCStatus, DMACIntErrorStatus. The DMACIntStatus Register combines both the DMACIntTCStatus and DMACIntEr rorStatus requests into a single register to enable the source of an interrupt to be found quickly. Writing to the DMACIntTCClear or the DMACIntErrClr Registers with a bit set HIGH enables selective clearing of interrupts. The DMAC provides two interrupt request connection schemes. See Interrupt controller connectivity. The simplest connection scheme has a combined error and end of transfer complete interrupt request. To find the source of an interrupt, you must read both the DMACIntStatus and DMACIntTCStatus Registers. For faster interrupt response, you can use an alternate connection scheme. This scheme uses separate interrupt requests for the error and transfer complete requests. Read either the DMACIntTCStatus or DMACIntErrorStatus Registers to find the source of an interrupt. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Combined terminal count and error interrupt sequence flow When you use the *DMACINTR *interrupt request: 1. You must wait until the combined interrupt request from the DMAC goes active. Assuming the interrupt is enabled in the interrupt controller and in the processor, the processor branches to the interrupt vector address and enters the interrupt service routine. 2. You must read the interrupt controller Status Register and determine whether the so urce of the request was the DMAC. 3. You must read the DMACIntStatus Register to determine the channel that generated the interrupt. If more than one request is active, it is recommended that you check the highest priority channels first. 4. You must read the DMACIntTCStatus Register to determine whether the interrupt was generated because of the end of the transfer, terminal count, or because an error occurred. A HIGH bit indicates that the transfer completed. 5. You must read the DMACIntErrorStatus Register to determine whether the interrupt was generated because of the end of the transfer, terminal count, or because an error occurred. A HIGH bit indicates that an error occurred. 6. You must write a 1 to the relevant bit in the DMACIntTCClear, orDMACIntErrClr, Register to clear the interrupt request. Terminal count interrupt sequence flow When the separate, DMACINTTC and DMACINTERR, interrupt requests are used: 1. You must wait until the terminal count DMA interrupt request goes active. Assuming the interrupt is enabled in the interrupt controller and in the processor, the processor branches to the interrupt vector address and enters the interrupt service routine. 2. You must read the interrupt controller Status Register to determine if the source of the interrupt request was the DMAC asserting the DMACINTTC signal. 6. You must read the DMACIntTCStatus Register to determine the channel that generated the interrupt. If more than one request is active, it is recommended that you service the highest priority channel first. 4. You must service the interrupt request. 5. You must write a 1 to the relevant bit in the DMACIntTCClear Register to clear the interrupt request. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Error interrupt sequence flow When the separate interrupt requests, DMACINTTC and DMACINTERR, are used: 1. You must wait until the interrupt request goes active because of a DMA channel error. Assuming the interrupt is enabled in the interrupt controller and in the processor, the processor branches to th e interrupt vector address and enters the interrupt service routine. 2. You must read the Interrupt Controllers Status Register to determine if the source of the request was the DMAC asserting the DMACINTERR signal. 3. You must read the DMACIntErrorStatus Register to determine the channel that generated the interrupt. If more than one request is active it is recommended that you check the highest priority channels first. 4. You must service the interrupt request. 5. You must write a 1 to the relevant bit in the DMACIntErrClr Register to clear the interrupt request. Interrupt polling sequence flow The DMAC interrupt request signal is masked out, disabled in the interrupt controller, or disabled in the processor. When polling the DMAC, you must: 1. Read the DMACIntStatus Register. If none of the bits are HIGH repeat this step, otherwise, go to step 2. If more than one request is active, it is recommended that you check the highest priority channels first. 2. Read the DMACIntTCStatus Register to determine if the interrupt was generated because of the end of the transfer, terminal count, or because of error occurred. A HIGH bit indicates that the transfer completed. 3. Service the interrupt request. 4. For an error interrupt, write a 1 to the relevant bit of the DMACIntErrClr Register to clear the interrupt request. For a terminal count interrupt, write a 1 to the relevant bit of the DMACIntTCClrRegister. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.4.2.8 DMAC Data Flow

For a memory-to-memory DMA flow: 1. Program and enable the DMA channel. 2. Transfer data whenever the DMA channel has the highest pending priority and the DMAC gains bus master ship of the AHB bus. 3. If an error occurs while transferring the data, generate an error interrupt and disab le the DMA stream. 4. Decrement the transfer count. 5. If the count has reached zero:  Generate a terminal count interrupt. You can mask the interrupt.  If the DMACCxLLI Register is not 0, then reload the following registers and go to back to step 2: o DMACCxSrcAddr o DMACCxDestAddr o DMACCxLLI o DMACCxControl. o However, if DMACCxLLI is 0, the DMA stream is disabled and the flow sequence ends. Memory-to-peripheral, or peripheral-to-memory DMA flow For a peripheral-to-memory or memory-to-peripheral DMA flow: 1. Program and enable the DMA channel. 2. Wait for a DMA request. 3. The DMAC then starts transferring data when:  The DMA request goes active.  The DMA stream has the highest pending priority.  The DMAC is the bus master of the AHB bus. 4. If an error occurs while transferring the data, an error interrupt is generated and the DMA stream is disabled, and the flow sequence ends. 5. Decrement the transfer count if the DMAC is controlling the flow control. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 6. If the transfer has completed, indicated by the transfer count reaching 0 if the DMAC is performing flow control, or by the peripheral setting the DMACLBREQ or DMACLSREQ signals if the peripheral is performing flow control:  The DMAC asserts the DMACTC signal.  The terminal count interrupt is generated. You can mask this interrupt.  If the DMACCxLLI Register is not 0, then reload the following registers and go to back to step 2: o DMACCxSrcAddr o DMACCxDestAddr o DMACCxLLI o DMACCxControl. o However, if DMACCxLLI is 0, the DMA stream is disabled and the flow sequence ends. Peripheral-to-peripheral DMA flow For a peripheral-to-peripheral DMA flow: 1. Program and enable the DMA channel. 2. Wait for a source DMA request. 3. The DMAC then starts transferring data when:  The DMA request goes active.  The DMA stream has the highest pending priority.  The DMAC is the bus master of the AHB bus. 4. If an error occurs while transferring the data, an error interrupt is generated, then finishes. 5. Decrement the transfer count if the DMAC is controlling the flow control. 6. If the transfer has completed, indicated by the transfer count reaching 0 if the DMAC is performing flow control, or by the peripheral setting the DMACLBREQ or DMACLSREQ signals if the peripheral is performing flow control:  The DMAC asserts the DMACTC signal to the source peripheral.  Subsequent source DMA requests are ignored. 7. When the destination DMA request goes active and there is data in the DMACFIFO, transfer data into the destination peripheral. 8. If an error occurs while transferring the data, an error interrupt is generated and the DMA stream is disabled, and the flow sequence ends. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 9. If the transfer has completed, it is indicated by the transfer count reaching 0 if the DMAC is performing flow control, or by the peripheral setting the DMACLBREQ or DMACLSREQ signals if the peripheral is performing flow control. The following happens:  The DMAC asserts the DMACTC signal to the destination peripheral.  The terminal count interrupt is generated. You can mask this interrupt.  If the DMACCxLLI Register is not 0, then reload the following registers and go to back to step 2: o DMACCxSrcAddr o DMACCxDestAddr o DMACCxLLI o DMACCxControl. o However, if DMACCxLLI is 0, the DMA stream is disabled and the flow se quence ends. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.5 Register Description

8.5.1 Register Map Summary

This section describes the DMAC0/1 registers.  Base Address: 0xC000_0000  Base Address: 0xC000_1000 Register Offset Description Reset Value Interrupt Status Register 0x00 The read-only DMACIntStatus Register, with address offset of 0x000, shows the status of the interrupts after masking. A HIGH bit indicates that a specific DMA channel interrupt request is active. You can generate the request from either the error or terminal count interrupt requests. 0x0 Interrupt Terminal Count Status Register 0x04 The read-only DMACIntTCStatus Register, with address offset of 0x004, indicates the status of the terminal count after masking. You must use this register in conjunction with the DMACIntStatus Register if you use the combined interrupt request, DMACINTR, to request interrupts. If you use the DMACINTTC interrupt request, then you only have to read the DMACIntTCStatus Register to ascertain the source of the interrupt request. 0x0 Interrupt Terminal Count Clear Register 0x08 The write-only DMACIntTCClear Register, with address offset of 0x008, clears a terminal count interrupt request. When writing to this register, each data bit that is set HIGH causes the corresponding bit in the Status Register to be cleared. Data bits that are LOW have no effect on the corresponding bit in the register. Interrupt Error Status Register 0x0C The read-only DMACIntErrorStatus Register, with address offset of 0x00C, indicates the status of the error request after masking. You must use this register in conjunction with the DMACIntStatus Register if you use the combined interrupt request, DMACINTR, to request interrupts. If you use the DMACINTERR interrupt request, then only read the DMACIntErrorStatus Register. 0x0 Interrupt Error Clear Register 0x10 The write-only DMACIntErrClr Register, with address offset of 0x010, clears the error interrupt requests. When writing to this register, each data bit that is HIGH causes the corresponding bit in the Status Register to be cleared. Data bits that are LOW have no effect on the corresponding bit in the register. Raw Interrupt Terminal Count Status Register 0x14 The read-only DMACRawIntTCStatus Register, with address offset of 0x014, indicates the DMA channels that are requesting a transfer complete, terminal count interrupt, prior to masking. A HIGH bit indicates that the terminal count interrupt request is active prior to masking. Raw Error Interrupt Status Register 0x18 The read-only DMACRawIntErrorStatus Register, with address offset of 0x018, indicates the DMA channels that are requesting an error interrupt prior to masking. A HIGH cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value bit indicates that the error interrupt request is active prior to masking. Enabled Channel Register 0x1C The read-only DMACEnbldChns Register, with address offset of 0x01C, indicates the DMA channels that are enabled, as indicated by the Enable bit in the DMACCxConfiguration Register. A HIGH bit indicates that a DMA channel is enabled. A bit is cleared on completion of the DMA transfer. 0x0 Software Burst Request Register. 0x20 The read/write DMACSoftBReq Register, with address offset of 0x020, enables DMA burst requests to be generated by software. You can generate a DMA request for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Writing 0 to this register has no effect. Reading the register indicates the sources that are requesting DMA burst transfers. You can generate a request from either a peripheral or the software request register. 0x0 Software Single Request Register. 0x24 The read/write DMACSoftSReq Register, with address offset of 0x024, enables DMA single requests to be generated by software. You can generate a DMA request for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Writing 0 to this register has no effect. Reading the register indicates the sources that are requesting single DMA transfers. You can generate a request from either a peripheral or the software request register. 0x0 Software Last Burst Request Register 0x28 The read/write DMACSoftLBReq Register, with address offset of 0x028, enables software to generate DMA last burst requests. You can generate a DMA request for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Writing 0 to this register has no effect. Reading the register indicates the sources that are requesting last burst DMA transfers. You can generate a request from either a peripheral or the software request register. 0x0 Software Last Single Request Register 0x2C The read/write DMACSoftLSReq Register, with address offset of 0x02C, enables software to generate DMA last single requests. You can generate a DMA request for each source by writing a 1 to the corresponding register bit. A register bit is cleared when the transaction has completed. Writing 0 to this register has no effect. Reading the register indicates the sources that are requesting last single DMA transfers. You can generate a request from either a peripheral or the software request register. 0x0 Configuration Register 0x30 The read/write DMACConfiguration Register, with address offset of 0x030, configures the operation of the DMAC. You can alter the endianness of the individual AHB master interfaces by writing to the M1 and M2 bits of this register. The M1 bit enables you to alter the endianness of AHB 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value master interface 1. The M2 bit enables you to alter the endianness of AHB master interface 2. The AHB master interfaces are set to little-endian mode on reset. Synchronization Register 0x34 The read/write DMACSync Register, with address offset of 0x034, enables or disables synchronization logic for the DMA request signals. The DMA request signals consist of:

DMACBREQ[15:0]
DMACSREQ[15:0]
DMACLBREQ[15:0]
DMACLSREQ[15:0]. A bit set to 0 enables the synchronization logic for a particular group of DMA requests. A bit set to 1 disables the synchronization logic for a particular group of DMA requests. This register is reset to 0, and synchronization logic enabled. NOTE: It is illegal for a peripheral to give a new DMACSREQ or DMACBREQ signal while DMACCLR is HIGH. NOTE: You must use synchronization logic when the peripheral generating the DMA request runs on a different clock to the DMAC. For peripherals running on the same clock as the DMAC, disabling the synchronization logic improves the DMA request response time. If necessary, synchronize the DMA response signals, DMACCLR and DMACTC, in the peripheral. 0x0 Channel registers The channel registers are for programming a DMA channel. These registers consist of:  eight DMACCxSrcAddr Registers  eight DMACCxDestAddr Registers  eight DMACCxLLI Registers  eight DMACCxControl Registers  eight DMACCxConfiguration Registers. When performing scatter/gather DMA, the first four registers are automatically updated. NOTE: Unpredictable behavior can result if you update the channel registers when a transfer is taking place. If you want to change the channel configurations, you must disable the channel first and then reconfigure the relevant register. Channel Source Address Registers 0x100, 0x120, 0x140, 0x160, 0x180, 0x1A0, 0x1C0, 0x1E0 The eight read/write DMACCxSrcAddr Registers, with address offsets of 0x100, 0x120, 0x140, 0x160, 0x180, 0x1A0, 0x1C0, and 0x1E0 respectively, contain the current source address, byte-aligned, of the data to be transferred. Software programs each register directly before the appropriate channel is enabled. When the DMA channel is enabled, this register is updated:  as the source address is incremented  by following the linked list when a complete packet of 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value data has been transferred. Reading the register when the channel is active does not provide useful information. This is because by the time the software has processed the value read, the channel might have progressed. It is intended to be read-only when the channel has stopped, and in such case, it shows the source address of the last item read. NOTE: You must align source and destination addresses to the source and destination widths. Channel Destination Address Register 0x104, 0x124, 0x144, 0x164, 0x184, 0x1A4, 0x1C4, 0x1E4 Channel Destination Address Registers. The eight read/write DMACCxDestAddr Registers, with address offsets of 0x104, 0x124, 0x144, 0x164, 0x184, 0x1A4, 0x1C4, and 0x1E4 respectively, contain the current destination address, byte-aligned, of the data to be transferred. Software programs each register directly before the channel is enabled. When the DMA channel is enabled, the register is updated as the destination address is incremented and by following the linked list when a complete packet of data has been transferred. Reading the register when the channel is active does not provide useful information. This is because by the time the software has processed the value read, the channel might have progressed. It is intended to be read-only when a channel has stopped. In this case, it shows the destination address of the last item read. 0x0 Channel Linked List Item Registers 0x108, 0x128, 0x148, 0x168, 0x188, 0x1A8, 0x1C8, 0x1E8 Channel Linked List Item Register. The eight read/write DMACCxLLI Registers, with address offsets of 0x108, 0x128, 0x148, 0x168, 0x188, 0x1A8, 0x1C8, and 0x1E8 respectively, contain a word-aligned address of the next LLI. If the LLI is 0, then the current LLI is the last in the chain, and the DMA channel is disabled after all DMA transfers associated with it are completed. NOTE: 1. Programming this register when the DMA channel is enabled has unpredictable results. 2. To make loading the LLIs more efficient for some systems, you can make the LLI data structures 4-word aligned. 0x0 Channel Control Registers 0x10C, 0x12C, 0x14C, 0x16C, 0x18C, 0x1AC, 0x1CC, 0x1EC Refer to below description. The eight read/write DMACCxControl Registers, with address offsets of 0x010C, 0x12C, 0x14C, 0x16C, 0x18C, 0x1AC, 0x1CC, and 0x1EC respectively, contain DMA channel control information such as the transfer size, burst size, and transfer width. Software programs each register directly before the DMA channel is enabled. When the channel is enabled, the register is updated by 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-26 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value following the linked list when a complete packet of data has been transferred. Reading the register while the channel is active does not give useful information. This is because by the time that software has processed the value read, the channel might have progressed. It is intended to be read- only when a channel has stopped. Below Table lists the values of the DBSize or SBSsize bits and their corresponding burst sizes. Below Table Source or destination burst size Bit value of DBSize or SBSize Source or Destination Burst Transfer Request Size 0b000 1 0b001 4 0b010 8 0b011 16 0b100 32 0b101 64 0b110 128 0b111 256 Below Table lists the value of the SWidth or DWidth bits and their corresponding widths. Below Table lists the value of the SWidth or DWidth bits and their corresponding widths. Bit value of SWidth or DWidth Source or Destination Width 0b000 Byte, 8-bit 0b001 Halfword, 16-bit 0b010 Word, 32-bit 0b011 Reserved 0b100 Reserved 0b101 Reserved 0b110 Reserved 0b111 Reserved Protection and access information AHB access information is provided to the source and destination peripherals when a transfer occurs. The transfer information is provided by programming the DMA channel, the Prot bit of the DMACCxControl Register, and the Lock bit of the DMACCxConfiguration Register. Software programs these bits, and peripherals can use this cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value information if necessary. Three bits of information are provided. Below Table lists the purposes of the three protection bits. Below Table Protection bits Bit Descripti on Purpose [2] Cacheabl e or Non- cacheable Indicates whether or not the access can be cached: 0 = non-cacheable 1 = cacheable. This bit indicates whether or not the access is cacheable. For example, you can use this bit to indicate to an AMBA bridge that when it saw the first read of a burst of eight it can transfer the whole burst of eight reads on the destination bus, rather than pass the transactions through one at a time. This bit controls the AHB HPROT[3] signal. [1] Bufferable or Non- bufferable Indicates whether or not the access can be buffered: 0 = non-bufferable 1 = bufferable. This bit indicates whether or not the access is bufferable. For example, you can use this bit to indicate to an AMBA bridge that the read can complete in zero wait states on the source bus without waiting for it to arbitrate for the destination bus and for the slave to accept the data. This bit controls the AHB HPROT[2] signal. [0] Privileged or User Indicates whether the access is in User, or Privileged mode: 0 = user mode 1 = privileged mode. This bit controls the AHB HPROT[1] signal. Channel Configuration Registers 0x110, 0x130, 0x150, 0x170, 0x190, 0x1B0, 0x1D0, 0x1F0 The eight DMACCxConfiguration Registers, with address offsets of 0x110, 0x130, 0x150, 0x170, 0x190, 0x1B0, 0x1D0, and 0x1F0 respectively, are read/write and configure the DMA channel. The registers are not updated when a new LLI is requested. Below Table lists the bit values of the three flow control and transfer type bits. Below Table Flow control and transfer type bits 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-28 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.5.1.1 Interrupt Status Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x00, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value SesReqScs [31:8] R Read undefined 0x0 IntStatus [7:0] R Status of the DMA interrupts after masking 0x0

8.5.1.2 Interrupt Terminal Count Status Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x04, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] R Read undefined 0x0 IntTCStatus [7:0] R Interrupt terminal count request status 0x0

8.5.1.3 Interrupt Terminal Count Clear Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x08, Reset Value = x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] W Undefined. Write as zero. 0x0 IntTCClear [7:0] W Terminal count request clear. 0x0

8.5.1.4 Interrupt Error Status Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x0C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] R Read undefined 0x0 IntErrorStatus [7:0] R Interrupt error status 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-29 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.5.1.5 Interrupt Error Clear Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x10, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] W Undefined. Write as zero. 0x0 IntErrClr [7:0] W IntErrClr Interrupt error clear. 0x0

8.5.1.6 Raw Interrupt Terminal Count Status Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x14, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] R Read undefined 0x0 RawIntTCStatus [7:0] R Status of the terminal count interrupt prior to masking 0x0

8.5.1.7 Raw Error Interrupt Status Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x18, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] R Read undefined 0x0 RawIntErrorStatus [7:0] R Status of the error interrupt prior to masking 0x0

8.5.1.8 Enabled Channel Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x1C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] R Read undefined 0x0 EnabledChannels [7:0] R Channel enable status 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-30 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.5.1.9 Software Burst Request Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x20, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Read undefined. Write as zero. 0x0 SoftBReq [15:0] RW Software burst request. 0x0

8.5.1.10 Software Single Request Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x24, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Read undefined. Write as zero. 0x0 SoftSReq [15:0] RW Software single request. 0x0

8.5.1.11 Software Last Burst Request Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x28, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Read undefined. Write as zero. 0x0 SoftLBReq [15:0] RW Software last burst request. 0x0

8.5.1.12 Software Last Single Request Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x2C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Read undefined. Write as zero. 0x0 SoftLSReq [15:0] RW Software last single request. 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-31 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.5.1.13 Configuration Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x30, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] RW Read undefined. Write as zero. - M2 [2] RW AHB Master 2 endianness configuration: 0 = little-endian mode 1 = big-endian mode This bit is reset to 0. 1'b0 M1 [1] RW AHB Master 1 endianness configuration: 0 = little-endian mode 1 = big-endian mode This bit is reset to 0. 1'b0 E [0] RW DMAC enable: 0 = disabled 1 = enabled This bit is reset to 0. Disabling the DMAC reduces power consumption. 1'b0

8.5.1.14 Synchronization Register

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x34, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Read undefined. Write as zero. - DMACSync [15:0] RW DMA synchronization logic for DMA request signals enabled or disabled. A LOW bit indicates that the synchronization logic for the request signals is enabled. A HIGH bit indicates that the synchronization logic is disabled. 0x0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-32 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.5.1.15 Channel Source Address Registers_n (n = 0 to 7)

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x100, 0x120, 0x140, 0x160, 0x180, 0x1A0, 0x1C0, 0x1E0, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value SrcAddr [31:0] RW DMA source address 0x0000_0000

8.5.1.16 Channel Destination Address Registers_n (n = 0 to 7)

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x104, 0x124, 0x144, 0x164, 0x184, 0x1A4, 0x1C4, 0x1E4, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value DestAddr [31:0] RW DMA destination address 0x0000_0000

8.5.1.17 Channel Linked List Item Registers_n (n = 0 to 7)

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x108, 0x128, 0x148, 0x168, 0x188, 0x1A8, 0x1C8, 0x1E8, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value LLI [31:2] – Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0. 0x0000_0000 RSVD [1] RW Read undefined. Write as zero. 1'b0 LM [0] – AHB master select for loading the next LLI 0 = AHB Master 1 1 = AHB Master 2. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-33 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

8.5.1.18 Channel Control Registers_n (n = 0 to 7)

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x10C, 0x12C, 0x14C, 0x16C, 0x18C, 0x1AC, 0x1CC, 0x1EC, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value I [31] R "Terminal count" interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count interrupt. 1'b0 Prot [30:28] RW Protection. 3'b0 DI [27] R Destination increment. When set, the destination address is incremented after each transfer. 1'b0 SI [26] R Source increment. When set, the source address is incremented after each transfer. 1'b0 D [25] RW Destination AHB master select: 0 = AHB master 1 selected for the destination transfer 1 = AHB master 2 selected for the destination transfer 1'b0 S [24] RW Source AHB master select: 0 = AHB master 1 selected for the source transfer 1 = AHB master 2 selected for the source transfer 1'b0 DWidth [23:21] RW Destination transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data when required. 3'b0 SWidth [20:18] RW Source transfer width. Transfers wider than the AHB master bus width are illegal. The source and destination widths can be different from each other. The hardware automatically packs and unpacks the data when required. 3'b0 DBSize [17:15] RW Destination burst size. Indicates the number of transfers that make up a destination burst transfer request. You must set this value to the burst size of the destination peripheral, or if the destination is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACxBREQ signal goes active in the destination peripheral. The burst size is not related to the AHB HBURST signal. 3'b0 SBSize [14:12] RW Source burst size. Indicates the number of transfers that make up a source burst. You must set this value to the burst size of the source peripheral, or if the source is memory, to the memory boundary size. The burst size is the amount of data that is transferred when the DMACxBREQ signal goes active in the source peripheral. The burst size is not related to the 3'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-34 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value AHB HBURST signal. TransferSize [11:0] RW Transfer size. A write to this field sets the size of the transfer when the DMAC is the flow controller. This value counts down from the original value to zero, and so its value indicates the number of transfers left to complete. A read from this field provides the number of transfers still to be completed on the destination bus. Reading the register when the channel is active does not give useful information because by the time the software has processed the value read, the channel might have progressed. Only use it when a channel is enabled, and then disabled. Program the transfer size value to zero if the DMAC is not the flow controller. If you program the TransferSize to a non-zero value, the DMAC might attempt to use this value instead of ignoring the TransferSize. 11'b0

8.5.1.19 Channel Configuration Registers_n (n = 0 to 7)

 Base Address: 0xC000_0000  Base Address: 0xC000_1000  Address = Base Address + 0x110, 0x130, 0x150, 0x170, 0x190, 0x1B0, 0x1D0, 0x1F0, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:19] – Read undefined. Write as zero. - H [18] RW Halt: 0 = Enable DMA requests 1 = Ignore extra source DMA requests. The contents of the channels FIFO are drained. You can use this value with the Active and Channel Enable bits to cleanly disable a DMA channel. 1'b0 A [17] R Active: 0 = There is no data in the FIFO of the channel 1 = The FIFO of the channel has data. You can use this value with the Halt and Channel Enable bits to cleanly disable a DMA channel. 1'b0 L [16] RW Lock. When set, this bit enables locked transfers. 1'b0 ITC [15] RW Terminal count interrupt mask. When cleared, this bit masks out the terminal count interrupt of the relevant channel. 1'b0 IE [14] RW Interrupt error mask. When cleared, this bit masks out the error interrupt of the relevant channel. 1'b0 FlowCntrl [13:11] RW Flow control and transfer type. This value indicates the flow controller and transfer type. The flow controller can be the DMAC, the source peripheral, or 3'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 8 DMA 8-35 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value the destination peripheral. The transfer type can be memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral. RSVD [10] – Read undefined. Write as zero. 1'b0 DestPeripherala [9:6] RW Destination peripheral. This value selects the DMA destination request This field is ignored if the destination of the transfer is to memory. 4'b0 RSVD [5] – Read undefined. Write as zero. - SrcPeripherala [4:1] RW Source peripheral. This value selects the DMA source request peripheral. This field is ignored if the source of the transfer is from memory. 4'b0 E [0] RW Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = Channel disabled 1 = Channel enabled You can also determine the Channel Enable bit status by reading the DMACEnbldChns register. You enable a channel by setting this bit. You can disable a channel by clearing the Enable bit. This causes the current AHB transfer, if one is in progress, to complete, and the channel is then disabled. Any data in the channel's FIFO is lost. Restarting the channel by setting the Channel Enable bit has unpredictable effects and you must fully re- initialize the channel. The channel is also disabled, and the Channel Enable bit cleared, when the last LLI is reached, or if a channel error is encountered. If a channel has to be disabled without losing data in a channel's FIFO, you must set the Halt bit so that subsequent DMA requests are ignored. The Active bit must then be polled until it reaches 0, indicating that there is no data left in the channel's FIFO. Finally, you can clear the Channel Enable bit. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9 Interrupt Controller

9.1 Overview

64 interrupt sources from internal peripherals, including the DMA controller, UART, I2C and GPIO, etc. supply requests to an Interrupt Controller. An FIQ or an IRQ (interrupt requests) are signaled by the Interrupt Controller to CPU. After arbitrating multiple requests from internal peripherals and GPIO, the Controller requests an interrupt. The hardware arbitration logic decides the interrupt arbitration process and the results are recorded in the interrupt pending registers.

9.2 Features

The interrupt controller is responsible for:  support for 64 IRQ interrupts  2 channels, each channel processes 32 IRQ interrupts and has each AHB bus.  IRQ and FIQ generation  AHB mapped for faster interrupt response  software interrupt generation  raw interrupt status  interrupt request status cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.3 Block Diagram

The interrupt controller has two channels. Each channel has 32 interrupt sources. The interrupt request logic receives the interrupt requests from the peripheral and combines them with the software interr upt requests. It then masks out the interrupt requests which are not enabled, and routes the enabled interrupt requests to either IRQ Status or FIQ Status. Figure 9-1 shows a block diagram of the interrupt request logic in each channel. Figure 9-1 Interrupt Request Logic in 1 Channel The FIQ interrupt logic generates the FIQ interrupt signal by FIQ interrupt requests in the interrupt controller. Figure 9-2 shows a block diagram of the FIQ interrupt logic in each channel. Figure 9-2 FIQ Interrupt Logic in 1 Channel cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.4 Programming sequence

9.4.1 Interrupt Flow Sequence Using AHB

The following procedure shows the sequence for the IRQ interrupt flow:  An IRQ interrupt occurs.  The ARM processor branches to the IRQ interrupt vector  Stack the workspace so that IRQ interrupts can be re-enabled later.  Perform a dummy read to the VICADDRESS Register to set up priority status control in the VIC.  Read the VICIRQSTATUS Register and determine which interrupt sources have to be service.  Execute the ISR. At the beginning of the ISR, the interrupt of the processor can be re -enabled so that a higher priority interrupt can be serviced.  Clear the requesting interrupt in the peripheral, or write to the VICSOFTINTCLEAR Register if the request was generated by a software interrupt.  Disable the interrupt on the processor and restore the workspace.  Write to the VICADDRESS Register. This clears the respective interrupt in the internal interrupt priority hardware.  Return from the interrupt. This re-enables the interrupts.

9.4.2 FIQ Interrupt Flow Sequence

The following procedure shows the sequence for the FIQ interrupt flow.  An FIQ interrupt occurs.  The ARM processor branches to the FIQ interrupt vector.  Branch to the ISR.  Execute the ISR.  Clear the requesting interrupt in the peripheral, or write to the VICSOFTINTCLEAR Register if the request was generated by a software interrupt.  Disable the interrupts and restore the workspace.  Return from the interrupt. This re-enables the interrupts

9.4.3 Internal GIC

Cortex A9 MP Core has included internal Generic Interrupt Controller (GIC). Some interrupt signals are connected with this internal GIC. Internal GIC should be enable for using these interrupt. Refer to Cortex A9 MP Core Technical Reference Manual for how to use. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.5 Interrupt Source

Table 9-1 Interrupt Sources Description Table Interrupt Number Source Description

0 MCUSTOP MCUSTOP interrupt

1 DMA0 DMA0 interrupt

2 DMA1 DMA1 interrupt

3 CLKPWR0 CLKPWRPWR interrupt

4 CLKPWR1 CLKPWRALIVE interrupt

5 CLKPWR2 CLKPWRRTC interrupt

6 UART1 UART1 interrupt

7 UART0 UART0 interrupt

8 UART2 UART2 interrupt

9 UART3 UART3 interrupt

10 UART4 UART4 interrupt

11 RESERVED –

12 SSP0 SSP0 interrupt

13 SSP1 SSP1 interrupt

14 SSP2 SSP2 interrupt

15 I2C0 I2C0 interrupt

16 I2C1 I2C1 interrupt

17 I2C2 I2C2 interrupt

18 DEINTERLACE DEINTERLACE interrupt

19 SCALER SCALER interrupt

20 AC97 AC97 interrupt

21 SPDIFRX SPDIFRX interrupt

22 SPDIFTX SPDIFTX interrupt

23 TIMER0 TIMER0 interrupt

24 TIMER1 TIMER1 interrupt

25 TIMER2 TIMER2 interrupt

26 TIMER3 TIMER3 interrupt

27 PWM0 PWM0 interrupt

28 PWM1 PWM1 interrupt

29 PWM2 PWM2 interrupt

30 PWM3 PWM3 interrupt

31 WDT WDT interrupt

32 MPEGTSI MPEGTSI interrupt

33 DISPLAYTOP0 DISPLAYDUALDISPLAYPRIM interrupt

cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Interrupt Number Source Description

34 DISPLAYTOP1 DISPLAYDUALDISPLAYSECOND interrupt

35 DISPLAYTOP2 DISPLAYRESCONV interrupt

36 DISPLAYTOP3 DISPLAYHDMI interrupt

37 VIP0 VIP0 interrupt

38 VIP1 VIP1 interrupt

39 MIPI MIPI interrupt

40 3D GPU 3D GPU interrupt

41 ADC ADC interrupt

42 PPM PPM interrupt

43 SDMMC0 SDMMC0 interrupt

44 SDMMC1 SDMMC1 interrupt

45 SDMMC2 SDMMC2 interrupt

46 CODA9600 CODA960HOST interrupt

47 CODA9601 CODA960JPG interrupt

48 GMAC GMAC interrupt

49 USB20OTG USB20OTG interrupt

50 USB20HOST USB20HOST interrupt

51 N/A N/A

52 N/A N/A

53 GPIOA GPIOA interrupt

54 GPIOB GPIOB interrupt

55 GPIOC GPIOC interrupt

56 GPIOD GPIOD interrupt

57 GPIOE GPIOE interrupt

58 CRYPTO CRYPTO interrupt

59 PDM PDM interrupt

60 N/A N/A

61 N/A N/A

62 N/A N/A

63 N/A N/A

cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.6 Internal GIC Interrupt Source

Table 9-2 GIC Interrupt Sources Description Table Interrupt Number Source Description

0 CPU0 PMU CPU0 PMU interrupt

1 CPU1 PMU CPU1 PMU interrupt

2 CPU2 PMU CPU2 PMU interrupt

3 CPU3 PMU CPU3 PMU interrupt

4 L2CCINTR L2 cache interrupt

5 MCUINTR MCU interrupt

cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7 Register Summary

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Channel 0 programs 0 to 31 IRQ.  Channel 1 programs 32 to 63 IRQ. Register Offset Description Reset Value VICIRQSTATUS 0x00 (CH0) 0x00 (CH1) IRQ Status Register 0x0 VICFIQSTATUS 0x04 (CH0) 0x04 (CH1) FIQ Status Register 0x0 VICRAWINTR 0x08 (CH0) 0x08 (CH1) RAW Interrupt Status Register – VICINTSELECT 0x0C (CH0) 0x0C (CH1) Interrupt Select Register 0x0 VICINTENABLE 0x10 (CH0) 0x10 (CH1) Interrupt Enable Register 0x0 VICINTENCLEAR 0x14 (CH0) 0x14 (CH1) Interrupt Enable Clear Register – VICSOFTINT 0x18 (CH0) 0x18 (CH1) Software Interrupt Register 0x0 VICSOFTINTCLEAR 0x1C (CH0) 0x1C (CH1) Software Interrupt Clear Register – VICPROTECTION 0x20 (CH0) 0x20 (CH1) Protection Enable Register 0x0 VICSWPRIORITYMASK 0x24 (CH0) 0x24 (CH1) Software Priority Mask Register 16'hFFFF VICVECTPRIORITYDAISY 0x28 (CH0) 0x28 (CH1) Vector Priority Register For Daisy Chain 4'b1111 VICVECTADDR0 0x100 (CH0) 0x100 (CH1) Vector Address 0 Registers 0x0 VICVECTADDR1 0x104 (CH0) 0x104 (CH1) Vector Address 1 Registers 0x0 VICVECTADDR2 0x108 (CH0) 0x108 (CH1) Vector Address 2 Registers 0x0 VICVECTADDR3 0x10C (CH0) 0x10C (CH1) Vector Address 3 Registers 0x0 VICVECTADDR4 0x110 (CH0) 0x110 (CH1) Vector Address 4 Registers 0x0 VICVECTADDR5 0x114 (CH0) 0x114 (CH1) Vector Address 5 Registers 0x0 VICVECTADDR6 0x118 (CH0) 0x118 (CH1) Vector Address 6 Registers 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value VICVECTADDR7 0x11C (CH0) 0x11C (CH1) Vector Address 7 Registers 0x0 VICVECTADDR8 0x120 (CH0) 0x120 (CH1) Vector Address 8 Registers 0x0 VICVECTADDR9 0x124 (CH0) 0x124 (CH1) Vector Address 9 Registers 0x0 VICVECTADDR10 0x128 (CH0) 0x128 (CH1) Vector Address 10 Registers 0x0 VICVECTADDR11 0x12C (CH0) 0x12C (CH1) Vector Address 11 Registers 0x0 VICVECTADDR12 0x130 (CH0) 0x130 (CH1) Vector Address 12 Registers 0x0 VICVECTADDR13 0x134 (CH0) 0x134 (CH1) Vector Address 13 Registers 0x0 VICVECTADDR14 0x138 (CH0) 0x138 (CH1) Vector Address 14 Registers 0x0 VICVECTADDR15 0x13C (CH0) 0x13C (CH1) Vector Address 15 Registers 0x0 VICVECTADDR16 0x140 (CH0) 0x140 (CH1) Vector Address 16 Registers 0x0 VICVECTADDR17 0x144 (CH0) 0x144 (CH1) Vector Address 17 Registers 0x0 VICVECTADDR18 0x148 (CH0) 0x148 (CH1) Vector Address 18 Registers 0x0 VICVECTADDR19 0x14C (CH0) 0x14C (CH1) Vector Address 19 Registers 0x0 VICVECTADDR20 0x150 (CH0) 0x150 (CH1) Vector Address 20 Registers 0x0 VICVECTADDR21 0x154 (CH0) 0x154 (CH1) Vector Address 21 Registers 0x0 VICVECTADDR22 0x158 (CH0) 0x158 (CH1) Vector Address 22 Registers 0x0 VICVECTADDR23 0x15C (CH0) 0x15C (CH1) Vector Address 23 Registers 0x0 VICVECTADDR24 0x160 (CH0) 0x160 (CH1) Vector Address 24 Registers 0x0 VICVECTADDR25 0x164 (CH0) 0x164 (CH1) Vector Address 25 Registers 0x0 VICVECTADDR26 0x168 (CH0) 0x168 (CH1) Vector Address 26 Registers 0x0 VICVECTADDR27 0x16C (CH0) 0x16C (CH1) Vector Address 27 Registers 0x0 VICVECTADDR28 0x170 (CH0) Vector Address 28 Registers 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value 0x170 (CH1) VICVECTADDR29 0x174 (CH0) 0x174 (CH1) Vector Address 29 Registers 0x0 VICVECTADDR30 0x178 (CH0) 0x178 (CH1) Vector Address 30 Registers 0x0 VICVECTADDR31 0x17C (CH0) 0x17C (CH1) Vector Address 31 Registers 0x0 VICVECTPRIORITY0 0x200 (CH0) 0x200 (CH1) Vector Priority 0 register 4'b1111 VICVECTPRIORITY1 0x204 (CH0) 0x204 (CH1) Vector Priority 1 register 4'b1111 VICVECTPRIORITY2 0x208 (CH0) 0x208 (CH1) Vector Priority 2 register 4'b1111 VICVECTPRIORITY3 0x20C (CH0) 0x20C (CH1) Vector Priority 3 register 4'b1111 VICVECTPRIORITY4 0x210 (CH0) 0x210 (CH1) Vector Priority 4 register 4'b1111 VICVECTPRIORITY5 0x214 (CH0) 0x214 (CH1) Vector Priority 5 register 4'b1111 VICVECTPRIORITY6 0x218 (CH0) 0x218 (CH1) Vector Priority 6 register 4'b1111 VICVECTPRIORITY7 0x21C (CH0) 0x21C (CH1) Vector Priority 7 register 4'b1111 VICVECTPRIORITY8 0x220 (CH0) 0x220 (CH1) Vector Priority 8 register 4'b1111 VICVECTPRIORITY9 0x224 (CH0) 0x224 (CH1) Vector Priority 9 register 4'b1111 VICVECTPRIORITY10 0x228 (CH0) 0x228 (CH1) Vector Priority 10 register 4'b1111 VICVECTPRIORITY11 0x22C (CH0) 0x22C (CH1) Vector Priority 11 register 4'b1111 VICVECTPRIORITY12 0x230 (CH0) 0x230 (CH1) Vector Priority 12 register 4'b1111 VICVECTPRIORITY13 0x234 (CH0) 0x234 (CH1) Vector Priority 13 register 4'b1111 VICVECTPRIORITY14 0x238 (CH0) 0x238 (CH1) Vector Priority 14 register 4'b1111 VICVECTPRIORITY15 0x23C (CH0) 0x23C (CH1) Vector Priority 15 register 4'b1111 VICVECTPRIORITY16 0x240 (CH0) 0x240 (CH1) Vector Priority 16 register 4'b1111 VICVECTPRIORITY17 0x244 (CH0) 0x244 (CH1) Vector Priority 17 register 4'b1111 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value VICVECTPRIORITY18 0x248 (CH0) 0x248 (CH1) Vector Priority 18 register 4'b1111 VICVECTPRIORITY19 0x24C (CH0) 0x24C (CH1) Vector Priority 19 register 4'b1111 VICVECTPRIORITY20 0x250 (CH0) 0x250 (CH1) Vector Priority 20 register 4'b1111 VICVECTPRIORITY21 0x254 (CH0) 0x254 (CH1) Vector Priority 21 register 4'b1111 VICVECTPRIORITY22 0x258 (CH0) 0x258 (CH1) Vector Priority 22 register 4'b1111 VICVECTPRIORITY23 0x25C (CH0) 0x25C (CH1) Vector Priority 23 register 4'b1111 VICVECTPRIORITY24 0x260 (CH0) 0x260 (CH1) Vector Priority 24 register 4'b1111 VICVECTPRIORITY25 0x264 (CH0) 0x264 (CH1) Vector Priority 25 register 4'b1111 VICVECTPRIORITY26 0x268 (CH0) 0x268 (CH1) Vector Priority 26 register 4'b1111 VICVECTPRIORITY27 0x26C (CH0) 0x26C (CH1) Vector Priority 27 register 4'b1111 VICVECTPRIORITY28 0x270 (CH0) 0x270 (CH1) Vector Priority 28 register 4'b1111 VICVECTPRIORITY29 0x274 (CH0) 0x274 (CH1) Vector Priority 29 register 4'b1111 VICVECTPRIORITY30 0x278 (CH0) 0x278 (CH1) Vector Priority 30 register 4'b1111 VICVECTPRIORITY31 0x27C (CH0) 0x27C (CH1) Vector Priority 31 register 4'b1111 VICADDRESS 0xF00 (CH0) 0xF00 (CH1) Vector address register 0x0 VICPERIPHID0 0xFE0 (CH0) 0xFE0 (CH1) Peripheral Identification Register Bits 7:0 8'h92 VICPERIPHID1 0xFE4 (CH0) 0xFE4 (CH1) Peripheral Identification Register Bits 15:8 8'h11 VICPERIPHID2 0xFE8 (CH0) 0xFE8 (CH1) Peripheral Identification Register Bits 23:16 4'b0100 VICPERIPHID3 0xFEC (CH0) 0xFEC (CH1) Peripheral Identification Register Bits 31:24 0x0 VICPCELLID0 0xFF0 (CH0) 0xFF0 (CH1) Prime cell Identification Register Bits 7:0 8'h0D VICPCELLID1 0xFF4 (CH0) 0xFF4 (CH1) Prime cell Identification Register Bits 15:8 8'hF0 VICPCELLID2 0xFF8 (CH0) Prime cell Identification Register Bits 23:16 8'h05 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value 0xFF8 (CH1) VICPCELLID3 0xFFC (CH0) 0xFFC (CH1) Prime cell Identification Register Bits 31:24 8'hB1 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.1 VICIRQSTATUS

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x00 (CH0), 0x00 (CH1), Reset Value = 0x0000_0000 Name Bit Type Description Reset Value VICIRQSTATUS [31:0] R Shows the status of the interrupts after masking by the VICINTENABLE andVICINTSELECT Registers: 0 = Interrupt is inactive (reset) 1 = Interrupt is active There is one bit of the register for each interrupt source. 0x0000_0000

9.7.1.2 VICFIQSTATUS

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x04 (CH0), 0x04 (CH1), Reset Value = 0x0000_0000 Name Bit Type Description Reset Value VICFIQSTATUS [31:0] R Shows the status of the FIQ interrupts after masking by the VICINTENABLE and VICINTSELECT Registers: 0 = Interrupt is inactive (reset) 1 = Interrupt is active There is one bit of the register for each interrupt source. 0x0000_0000

9.7.1.3 VICRAWINTR

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x08 (CH0), 0x08 (CH1), Reset Value = Undefined Name Bit Type Description Reset Value VICRAWINTR [31:0] R Shows the status of the interrupts before masking by the Enable Registers: 0 = Interrupt is inactive before masking 1 = Interrupt is active before masking Because this register provides a direct view of the raw interrupt inputs, the reset value is unknown. There is one bit of the register for each interrupt source. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.4 VICINTSELECT

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x0C (CH0), 0x0C (CH1), Reset Value = 0x0000_0000 Name Bit Type Description Reset Value VICINTSELECT [31:0] RW Selects type of interrupt for interrupt request: 0 = IRQ interrupt (reset) 1 = FIQ interrupt. There is one bit of the register for each interrupt source 0x0000_0000

9.7.1.5 VICINTENABLE

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x10 (CH0), 0x10 (CH1), Reset Value = 0x0000_0000 Name Bit Type Description Reset Value VICINTENABLE [31:0] RW Enables the interrupt request lines, which allow the interrupts to reach the processor. Read: 0 = Interrupt disabled (reset) 1 = Interrupt enabled The interrupt enable can only be set using this register. The VICINTENCLEAR Register must be used to disable the interrupt enable. Write: 0 = No effect 1 = Interrupt enabled On reset, all interrupts are disabled. There is one bit of the register for each interrupt source. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.6 VICINTENCLEAR

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x14 (CH0), 0x14 (CH1), Reset Value = Undefined Name Bit Type Description Reset Value VICINTENCLEAR [31:0] W Clears corresponding bits in the VICINTENABLE Register: 0 = No effect 1 = Interrupt disabled in VICINTENABLE Register There is one bit of the register for each interrupt source

9.7.1.7 VICSOFTINT

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x18 (CH0), 0x18 (CH1), Reset Value = 0x0000_0000 Name Bit Type Description Reset Value VICSOFTINT [31:0] RW Setting a bit HIGH generates a software interrupt for the selected source before interrupt masking. Read: 0 = Software interrupt inactive (reset) 1 = Software interrupt active Write: 0 = No effect 1 = Software interrupt enabled There is one bit of the register for each interrupt source. 0x0000_0000

9.7.1.8 VICSOFTINTCLEAR

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x1C (CH0), 0x1C (CH1), Reset Value = Undefined Name Bit Type Description Reset Value VICSOFTINTCLEAR [31:0] W Clears corresponding bits in the VICSOFTINT Register: 0 = No effect 1 = Software interrupt disabled in the VICSOFTINT Register There is one bit of the register for each interrupt source. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.9 VICPROTECTION

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x20 (CH0), 0x20 (CH1), Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:1] – Reserved – VICPROTECTION [0] RW Enables or disables protected register access: 0 = Protection mode disabled (reset) 1 = Protection mode enabled When enabled, only privileged mode accesses (reads and writes) can access the interrupt controller registers, that is, when HPROT[1] is set HIGH for the current transfer. When disabled, both user mode and privileged mode can access the registers. This register can only be accessed in privileged mode, even when protection mode is disabled. 1'b0

9.7.1.10 VICSWPRIORITYMASK

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x24 (CH0), 0x24 (CH1), Reset Value = 0x0000_FFFF Name Bit Type Description Reset Value RSVD [31:16] – Reserved – VICSWPRIORITYMASK [15:0] RW Controls software masking of the 16 interrupt priority levels: 0 = Interrupt priority level is masked 1 = Interrupt priority level is not masked (reset) Each bit of the register is applied to each of the 16 interrupt priority levels. 0xFFFF cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.11 VICVECTPRIORITYDAISY

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x28 (CH0), 0x28 (CH1), Reset Value = 0x0000_000F Name Bit Type Description Reset Value RSVD [31:4] – Reserved - VECTPRIORITY [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 - 15. 15 is the lowest. 4'b1111

9.7.1.12 VICVECTADDR0

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x100 (CH0), 0x100 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR0 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.13 VICVECTADDR1

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x104 (CH0), 0x104 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR1 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.14 VICVECTADDR2

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x108 (CH0), 0x108 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR2 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.15 VICVECTADDR3

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x10C (CH0), 0x10C (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR3 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.16 VICVECTADDR4

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x110 (CH0), 0x110 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR4 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.17 VICVECTADDR5

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x114 (CH0), 0x114 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR5 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.18 VICVECTADDR6

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x118 (CH0), 0x118 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR6 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.19 VICVECTADDR7

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x11C (CH0), 0x11C (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR7 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.20 VICVECTADDR8

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x120 (CH0), 0x120 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR8 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.21 VICVECTADDR9

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x124 (CH0), 0x124 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR9 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.22 VICVECTADDR10

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x128 (CH0), 0x128 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR10 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.23 VICVECTADDR11

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x12C (CH0), 0x12C (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR11 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.24 VICVECTADDR12

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x130 (CH0), 0x130 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR12 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.25 VICVECTADDR13

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x134 (CH0), 0x134 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR13 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.26 VICVECTADDR14

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x138 (CH0), 0x138 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR14 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.27 VICVECTADDR15

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x13C (CH0), 0x13C (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR15 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.28 VICVECTADDR16

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x140 (CH0), 0x140 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR16 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.29 VICVECTADDR17

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x144 (CH0), 0x144 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR17 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.30 VICVECTADDR18

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x148 (CH0), 0x148 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR18 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-26 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.31 VICVECTADDR19

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x14C (CH0), 0x14C (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR19 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.32 VICVECTADDR20

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x150 (CH0), 0x150 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR20 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.33 VICVECTADDR21

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x154 (CH0), 0x154 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR21 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.34 VICVECTADDR22

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x158 (CH0), 0x158 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR22 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-28 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.35 VICVECTADDR23

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x15C (CH0), 0x15C (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR23 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.36 VICVECTADDR24

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x160 (CH0), 0x160 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR24 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-29 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.37 VICVECTADDR25

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x164 (CH0), 0x164 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR25 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.38 VICVECTADDR26

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x168 (CH0), 0x168 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR26 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-30 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.39 VICVECTADDR27

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x16C (CH0), 0x16C (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR27 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.40 VICVECTADDR28

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x170 (CH0), 0x170 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR28 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-31 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.41 VICVECTADDR29

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x174 (CH0), 0x174 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR29 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000

9.7.1.42 VICVECTADDR30

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x178 (CH0), 0x178 (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR30 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-32 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.43 VICVECTADDR31

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x17C (CH0), 0x17C (CH1), Reset Value = 32'h0000_0000 Name Bit Type Description Reset Value VICVECTADDR31 [31:0] RW Contains ISR vector addresses. This register can be accessed with one wait state. This register must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior. If the system does not support interrupt vector addresses, the VICVECTADDR registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined. 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-33 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.44 VICVECTPRIORITY0

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x200 (CH0), 0x200 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY0 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.45 VICVECTPRIORITY1

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x204 (CH0), 0x204 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY1 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.46 VICVECTPRIORITY2

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x208 (CH0), 0x208 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY2 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-34 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.47 VICVECTPRIORITY3

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x20C (CH0), 0x20C (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY3 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.48 VICVECTPRIORITY4

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x210 (CH0), 0x210 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY4 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.49 VICVECTPRIORITY5

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x214 (CH0), 0x214 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY5 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-35 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.50 VICVECTPRIORITY6

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x218 (CH0), 0x218 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY6 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.51 VICVECTPRIORITY7

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x21C (CH0), 0x21C (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY7 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.52 VICVECTPRIORITY8

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x220 (CH0), 0x220 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY8 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-36 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.53 VICVECTPRIORITY9

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x224 (CH0), 0x224 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY9 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.54 VICVECTPRIORITY10

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x228 (CH0), 0x228 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY10 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.55 VICVECTPRIORITY11

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x22C (CH0), 0x22C (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY11 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-37 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.56 VICVECTPRIORITY12

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x230 (CH0), 0x230 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY12 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.57 VICVECTPRIORITY13

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x234 (CH0), 0x234 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY13 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.58 VICVECTPRIORITY14

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x238 (CH0), 0x238 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY14 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-38 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.59 VICVECTPRIORITY15

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x23C (CH0), 0x23C (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY15 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.60 VICVECTPRIORITY16

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x240 (CH0), 0x240 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY16 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.61 VICVECTPRIORITY17

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x244 (CH0), 0x244 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY17 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-39 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.62 VICVECTPRIORITY18

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x248 (CH0), 0x248 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY18 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.63 VICVECTPRIORITY19

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x24C (CH0), 0x24C (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY19 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.64 VICVECTPRIORITY20

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x250 (CH0), 0x250 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY20 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-40 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.65 VICVECTPRIORITY21

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x254 (CH0), 0x254 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY21 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.66 VICVECTPRIORITY22

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x258 (CH0), 0x258 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY22 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.67 VICVECTPRIORITY23

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x25C (CH0), 0x25C (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY23 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-41 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.68 VICVECTPRIORITY24

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x260 (CH0), 0x260 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY24 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.69 VICVECTPRIORITY25

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x264 (CH0), 0x264 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY25 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.70 VICVECTPRIORITY26

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x268 (CH0), 0x268 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY26 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-42 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.71 VICVECTPRIORITY27

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x26C (CH0), 0x26C (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY27 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.72 VICVECTPRIORITY28

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x270 (CH0), 0x270 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY28 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.73 VICVECTPRIORITY29

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x274 (CH0), 0x274 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY29 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-43 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.74 VICVECTPRIORITY30

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x278 (CH0), 0x278 (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY30 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111

9.7.1.75 VICVECTPRIORITY31

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0x27C (CH0), 0x27C (CH1), Reset Value = 4'b1111 Name Bit Type Description Reset Value RSVD [31:4] – Reserved – VECTPRIORITY31 [3:0] RW Selects vectored interrupt priority level. User can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0 to 15. 15 is the lowest. 4'b1111 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-44 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.76 VICADDRESS

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0xF00 (CH0), 0xF00 (CH1), Reset Value = 0x0000_0000 Name Bit Type Description Reset Value vectaddr [31:0] RW Contains the address of the currently active ISR, with reset value 0x00000000. A read of this register returns the address of the ISR and sets the current interrupt as being serviced. A read must only be performed while there is an active interrupt. A write of any value to this register clears the current interrupt. A write must only be performed at the end of an interrupt service routine. 0x0000_0000

9.7.1.77 VICPERIPHID0

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0xFE0 (CH0), 0xFE0 (CH1), Reset Value = 0x0000_0092 Name Bit Type Description Reset Value RSVD [31:8] – Reserved – partnumber0 [7:0] R These bits read back as 0x92 8'h92

9.7.1.78 VICPERIPHID1

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0xFE4 (CH0), 0xFE4 (CH1), Reset Value = 0x0000_0011 Name Bit Type Description Reset Value RSVD [31:8] – Reserved – designer0 [7:4] R These bits read back as 0x1. 4'b0001 partnumber1 [3:0] R These bits read back as 0x1. 4'b0001 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-45 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.79 VICPERIPHID2

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0xFE8 (CH0), 0xFE8 (CH1), Reset Value = 0x0000_0004 Name Bit Type Description Reset Value RSVD [31:8] – Reserved – revision [7:4] R These bits read back as the revision number, which can be between 0 and 15. 4'b0000 designer1 [3:0] R These bits read back as 0x4. 4'b0100

9.7.1.80 VICPERIPHID3

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0xFEC (CH0), 0xFEC (CH1), Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved – configuration [7:2] R These bits read back as 0x0. 6'b000000 configuration [1:0] R Indicates the number of interrupts supported: 00 = 32 (default) 01 = 64 10 = 128 11 = 256 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 9 Interrupt Controller 9-46 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

9.7.1.81 VICPCELLID0

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0xFF0 (CH0), 0xFF0 (CH1), Reset Value = 0x0000_000D Name Bit Type Description Reset Value RSVD [31:8] – Reserved – VICPCELLID0 [7:0] R These bits read back as 0x0d 8'h0D

9.7.1.82 VICPCELLID1

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0xFF4 (CH0), 0xFF4 (CH1), Reset Value = 0x0000_00F0 Name Bit Type Description Reset Value RSVD [31:8] – Reserved – VICPCELLID1 [7:0] R These bits read back as 0xF0 8'hF0

9.7.1.83 VICPCELLID2

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0xFF8 (CH0), 0xFF8 (CH1), Reset Value = 0x0000_0005 Name Bit Type Description Reset Value RSVD [31:8] – Reserved – VICPCELLID2 [7:0] R These bits read back as 0x05 8'h05

9.7.1.84 VICPCELLID3

 Base Address: 0xC000_2000  Base Address: 0xC000_3000  Address = Base Address + 0xFFC (CH0), 0xFFC (CH1), Reset Value = 0x0000_00B1 Name Bit Type Description Reset Value RSVD [31:8] – Reserved – VICPCELLID3 [7:0] R These bits read back as 0xB1 8'hB1 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 10 Watch Dog Timer 10-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

10 Watch Dog Timer

10.1 Overview

Watchdog timer is used to resume the controller operation whenever it is disturbed by malfunction such as noise and system error. It can be used as normal 16bit interval timer to request interrupt service. The watchdog timer generates the reset signal. Difference in usage WDT compared with PWM timer is that WDT generates the reset signal.

10.2 Features

Features of WDT are:  Normal interval timer mode with interrupt request  Internal reset signal is activated when the timer count value reaches 0 (time -out).  Level-triggered interrupt mechanism cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 10 Watch Dog Timer 10-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

10.3 Functional Description

10.3.1 Watchdog Timer Operation

Figure 10-1 shows the functional block diagram of the watchdog timer. The watchdog timer uses only PCLK as its source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer c lock, and the resulting frequency is divided again. Figure 10-1 Watchdog Timer Block Diagram The prescaler value and the frequency division factor are specified in the watchdog timer control (WDTCON) register. Valid prescaler values range from 0 to 28-1. The frequency division factor can be selected as 16, 32, 64 or 128. Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle: t_watchdog = 1/(PCLK/(Prescaler value + 1)/Division_factor) cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 10 Watch Dog Timer 10-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

10.3.2 WTDAT & WTCNT

Once the watchdog timer is enabled, the value of watchdog timer data (WTDAT) register cannot be automatically reloaded into the timer counter (WTCNT). In this reason, an initial value must be written to the watchdog timer count (WTCNT) register, before the watchdog timer starts.

10.3.3 Consideration of Debugging Environment

When the MDIRAC-III is in debug mode Embedded ICE, the watchdog timer must not operate. The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal (DBGACK signal). Once the DBGACK signal is asserted, the reset output of the watchdog timer is not activated as the watchdog timer is expired.

10.3.4 Special Function Register

10.3.4.1 Memory map

Register Type Description Reset Value WTCON RW Watchdog timer control register 0x8021 WTDAT RW Watchdog timer data register 0x8000 WTCNT RW Watchdog timer count register 0x8000 WTCLRINT W Watchdog timer interrupt register –

10.3.4.2 Watchdog Timer Control (WTCON) Register

The WTCON register allows the user to enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output. The Watchdog timer is used to resume restart in mal-function after its power on, if controller restart is not desired, the Watchdog timer should be disabled. If the user wants to use the normal timer provided by the Watchdog timer, enable the interrupt and disable the Watchdog timer.

10.3.4.3 Watchdog Timer Data (WTDAT) Register

The WTDAT register is used to specify the time-out duration. The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation. However, using 0x8000(initial value) will drive the first time_out. In this case, the value of WTDAT will be automatically reloaded into WTCNT.

10.3.4.4 Watchdog Timer Count (WTCNT) Register

The WTCNT register contains the current count values for the watchdog timer during normal operation. Note that the content of WTDAT register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially, so the WTCNT register must be set to initial value before enabling it.

10.3.4.5 Watchdog Timer Interrupt (WTCLRINT) Register

The WTCLRINT register is used to clear the interrupt. Interrupt service routine is responsible for clearing the relevant interrupt after the interrupt service is completed. Writing any values on this register clears the interrupt. Reading this register is not allowed. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 10 Watch Dog Timer 10-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

10.4 Register Description

10.4.1 Register Map Summary

 Base Address: 0xC001_9000h Register Offset Description Reset Value WTCON 0x00h Watchdog Timer Control register 0x8021 WTDAT 0x04h Watchdog Timer Data register 0x8000 WTCNT 0x08h Watchdog Timer Count register 0x8000 WTCLRINT 0x0Ch Watchdog Timer Interrupt register –

10.4.1.1 WTCON

 Base Address: 0xC001_9000h  Address = Base Address + 0x00h, Reset Value = 0x0000_8021 Name Bit Type Description Reset Value RSVD [31:16] – Reserved – prescaler value [15:8] RW Prescaler value. The valid range is from 0 to (28-1). 0x80 RSVD [7:6] – Reserved – watchdog timer [5] RW Enable or disable bit of Watchdog timer. 0 = Disable 1 = Enable 1'b1 clock select [4:3] RW Determine the clock division factor. 00 = 16 01 = 32 10 = 64 11 = 128 2'b0 interrupt generation [2] RW Enable or disable bit of the interrupt. 0 = Disable 1 = Enable 1'b0 RSVD [1] – Reserved – Reset enable/disable [0] RW Enable or disable bit of Watchdog timer output for reset signal. 0 = Disable the reset function of the watchdog timer. 1 = Assert reset signal of the NXP4330Q at watchdog time-out. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 10 Watch Dog Timer 10-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

10.4.1.2 WTDAT

 Base Address: 0xC001_9000h  Address = Base Address + 0x04h, Reset Value = 0x0000_8000 Name Bit Type Description Reset Value RSVD [31:16] – Reserved – wtdat [15:0] RW Watchdog timer count value for reload. 0x8000

10.4.1.3 WTCNT

 Base Address: 0xC001_9000h  Address = Base Address + 0x08h, Reset Value = 0x0000_8000 Name Bit Type Description Reset Value RSVD [31:16] – Reserved – WTCNT [15:0] RW The current value of the watchdog timer 0x8000

10.4.1.4 WTCLRINT

 Base Address: 0xC001_9000h  Address = Base Address + 0x0Ch, Reset Value = Undefined Name Bit Type Description Reset Value WTCLRINT [31:0] W Write any values clears the interrupt – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 11 RTC 11-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

11 RTC

11.1 Overview

The Real Time Clock (RTC) block can be operated by the Backup Battery while the system power is off. The RTC block is composed of 32-bit free counter register and works with an external 32.768 kHz Crystal and also can perform the alarm function.

11.2 Features

 32-bit Counter  Alarm Function : Alarm Interrupt or Wake Up from Power Down Mode  Independent power pin (VDD_RTC)  Supports 1 Hz Time interrupt for Power Down Mode  Generates Power Management Reset signal cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 11 RTC 11-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

11.3 Block Diagram

Figure 11-1 RTC Block Diagram Figure 11-1 shows the RTC block diagram. The RTC block receives an external clo ck of 32.768 kHz and divides it into 1 Hz with 32.768 kHz. The RTC Counter operates depending on the external clock. NOTE: As shown in Figure 11-1, the left and right parts of the central dotted line use RTC Power and Normal Power, separately. The RTC Power Block uses a mercury battery, but the block actually using the mercury battery is the RTC Counter in the RTC Power Block. The battery life is about five years. In Figure 11-1, the output in point [A] is applied to the Power Manager or the Interrupt Controller. The output is applied to the Interrupt Controller in Normal mode and applied to the Power Manager in Power mode. NOTE: Even if RTC is not used, RTC power and RTC clock should be supplied. Fin/ 32768 Q Q SET CLR D RTC COUNTER RTCCNTWRITE RTCALARM Q Q SET CLR D RTCCNTWRITEENB bit RTC POWER BLOCK NORMAL POWER BLOCK Q Q SET CLR D ALARMINTENB bit RTCINTENB bit EXTERNAL INERNAL Rising Edge Detector 32.768KHz 1Hz Power Manager + 1 Yes Battery ==Fin Interrupt Controller A cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 11 RTC 11-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

11.4 Functional Description

11.4.1 Backup Battery Operation

As shown in Figure 11-1, since the RTC block uses a separate power source (Coin Battery), the RTC block operates even when the external power is turned off. The RTC Logic can be driven by the Backup Battery, which supplies the power through the VDD_ RTC pin into the RTC Block, even if the system power is off. When the system power is off, the interfaces of the CPU and RTC logic should be blocked and the backup battery only drives the oscillation circuit and the internal 32 -bit RTC counter to minimize power dissipation. In other words, the RTC block can be used as the Wake -Up Source when the S5P4418 is converted into Power Down mode. The use of the RTC block as a Wake-Up source requires that the RTCCTRL.ACCESSENB bit is set as "0" before the system enters Power Down mode. Setting it as "0" is performed to use the RTC as the Wake-Up source even when the system enters the Power Down Mode. (For detailed information on the Power Down Mode, refer to Section 4.) Even if the RTC block is not used, the RTC Clock must be connected to S5P4418 because the RTC clock is used as the clock for power management operation.

11.4.2 RTC Operation

The RTC generates an alarm signal at a specified time in the Power Down Mode or Normal Operation Mode. In Normal Operation Mode, the Alarm Interrupt is activated. In Power Down Mode, the Power Management Wake Up Signal is activated as well as the RTCALARM. The ALARM Time Set register (RTCALARM) de termines the condition of the alarm time setting and the RTCINTENB.ALARMINTENB bit determines the alarm enable/disable status. The procedure to generate an alarm interrupt is as follows: First, write a counter value to the RTCCNTWRITE register. (To this end, the busy status of the RTCCTRL.RTCCNTWAIT should be checked in advance. The written value is applied to the register after two 32.768 kHz clock cycles.) After that, write the value of the point at which you wish to generate an interrupt to the RTCALARM register. The RTC counter increases the counter value at intervals of 1 Hz. If the values of the two registers (RTCCNTWRITE and RTCAKARM registers) become equal when the RTCINTENB.ALARMINTENB bit is set as "1", an interrupt occurs. In a similar way, the RTC interrupt is detected in a rising edge of 1 Hz. In this case, the interrupt is generated by setting the RTCINTENB.RTCINTENB bit as "1". In addition, The RTCINTENB register contains the Pending Clear function and the Pending Clear is performed by writing "0". cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 11 RTC 11-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

11.4.3 Accessing the RTC Time Counter Setting/Read Register

To access RTC Time Count Read Register (RTCCNTREAD) and RTC Time Count Setting Register (RTCCNTWRITE), the RTCCTRL.RTCCNTWRITEENB bit is set to "1" before accessing these register. When the CPU completes to access these register, the CPU should set the RTCCTRL.RTCCNTWRITEENB bit to "0" to protect the content of RTC counter from unknown problem in abnormal state. The RTCCNTWRITEENB bit determines the reflection of the RCCNTWRITE register value to the RTC counter.

11.4.4 Interrupt Pending Register

Only the "READ" function is available for the RTCINTPND register of the S5P4418, but the current pending status can be read. Since the RTCINTPND register only has a "READ" function, the Pending Clear function is controlled by the RTCINTENB register. The Interrupt Pending status is cleared by disabling the relevant interrupt. Therefore, if the corresponding bit of the RTCINTENB register is set as "1", the relevant interrupt is enabled. If the corresponding bit is set as "0", the interrupt is disabled and the pending bit is also cleared.

11.4.5 Power Manager Reset Time Control

RTC controls the time when nPWRMANRST (Power Manager Reset) releases from CorePOR. Refer to RTCCORERSTIMESEL Register for setting the time when nPWRMANRST releases. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 11 RTC 11-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

11.5 Register Description

11.5.1 Register Map Description

 Base Address: 0xC001_0C00h Register Offset Description Reset Value RTCCNTWRITE 0x00h RTC time count setting register – RTCCNTREAD 0x04h RTC time count read register – RTCALARM 0x08h Alarm time count set register 0x0000_0000 RTCCTRL 0x0Ch RTC control register 0x0000_0000 RTCINTENB 0x10h RTC interrupt enable register 0x0000_0000 RTCINTPND 0x14h RTC interrupt pending register 0x0000_0000 RTCCORERSTIMESEL 0x18h RTC core por time select register 0x0000_0000 RTCSCRATCH 0x1Ch RTC scratch register 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 11 RTC 11-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

11.5.1.1 RTCCNTWRITE

 Base Address: 0xC001_0C00h  Address = Base Address + 0x00h, Reset Value = Undefined Name Bit Type Description Reset Value rtccntwrite [31:0] W Set RTC Counter Value. (Unit : 1Hz) The RTCCNTWAIT bit of the RTCCONTROL register should be checked before a value is written in this bit. If the RTCCNTWAIT bit is "1", this written value is not reflected. The written value is reflected to this register at least two cycles of 32768 Hz after it is changed to "0". To write a value to this register, the RTCCNTWRITEENB bit should be set as "1"'. NOTE: RTC reset to unknown values. If RTC power is first applied

11.5.1.2 RTCCNTREAD

 Base Address: 0xC001_0C00h  Address = Base Address + 0x04h, Reset Value = Undefined Name Bit Type Description Reset Value rtccntread [31 : 0] R Read Current RTC Counter Value. (Unit: 1 Hz) The value of the RTC counter is continuously changed.

11.5.1.3 RTCALARM

 Base Address: 0xC001_0C00h  Address = Base Address + 0x08h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value rtcalarm [31 : 0] RW ALARM Time Set Register. (Unit: 1 Hz) The ALARMCNTWAIT bit of the RTCCONTROL register should be checked before a value is written in this bit. If the RTCCNTWAIT bit is "1", this written value is not reflected. The written value is reflected to this register at least two cycles of 32768 Hz after it is changed to "0". 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 11 RTC 11-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

11.5.1.4 RTCCTRL

 Base Address: 0xC001_0C00h  Address = Base Address + 0x0Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31 : 5] - Reserved 27'b0 RTCCNTWAIT [4] R RTCCNTWAIT: Register to check if the previously requested "WRITE" is completed when writing a value to the RTCCNTWRITE register. The bit below indicates the status of the RTCCNTWRITE*register. 0 = IDLE 1 = Busy 1'b0 ALARMCNTWAIT [3] R ALARMCNTWAIT: Register to check if the previously requested "WRITE" is completed when writing a value to the RTCALARM*register. The bit below indicates the status of the RTCALARMWRITE*register 0 = IDLE 1 = Busy 1'b0 RSVD [2] - Reserved 1'b0 RSVD [1] - Reserved. However, \`0' should be written. 1'b0 RTCCNTWRITEENB [0] RW RTCCNTWRITEENB: Control Power isolation and connection of RTC block. This bit should be "0" before Power Down Mode for normal operation of RTC in Power Down Mode. 0 = Disable (Power Isolation) 1 = Enable (Power Connection) To access the RTCCNTREAD and RTCCNTWRITE registers, this bit should be set as "1". 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 11 RTC 11-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

11.5.1.5 RTCINTENB

 Base Address: 0xC001_0C00h  Address = Base Address + 0x10h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:2] – Reserved 30'b0 ALARMINTENB [1] RW ALARMINTENB: Set ALARM Interrupt On/Off and Pending Clear/Interrupt Enable READ 0 = Interrupt Disable 1 = Interrupt Enable WRITE 0 = Pending Clear & Interrupt Disable 1 = Interrupt Enable 1'b0 RTCINTENB [0] RW RTCINTENB : Set RTC (1 Hz Only) Interrupt On/Off and Pending Clear/Interrupt Enable READ 0 = Interrupt Disable 1 = Interrupt Enable WRITE 0 = Pending Clear & Interrupt Disable 1 = Interrupt Enable 1'b0

11.5.1.6 RTCINTPND

 Base Address: 0xC001_0C00h  Address = Base Address + 0x14h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:2] – Reserved 30'b0 ALARMINTPEND [1] R ALARMINTEPND: ALARM Interrupt Pending bit. 0 = None 1 = Interrupt Pended 1'b0 RTCINTPEND [0] R RTCINTPEND: Set RTC (1 Hz Only) Interrupt Pending bit. 0 = None 1 = Interrupt Pended 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 11 RTC 11-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

11.5.1.7 RTCCORERSTIMESEL

 Base Address: 0xC001_0C00h  Address = Base Address + 0x18h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31 : 2] – Reserved 30'b0 COREPORtimeSEL6 [6:0] RW CORE POR (Power On Reset) releases with the delay of about 186 ms after CORE VDD Power is turned on. 0 = None 1 = Select 1'b0 COREPORTimeSEL5 [5] RW CORE POR (Power On Reset) releases with the delay of about 155 ms after CORE VDD Power is turned on. 0 = None 1 = Select 1'b0 COREPORtimeSEL4 [4] RW CORE POR (Power On Reset) releases with the delay of about 124 ms after CORE VDD Power is turned on. 0 = None 1 = Select 1'b0 COREPORtimeSEL3 [3] RW CORE POR (Power On Reset) releases with the delay of about 93 ms after CORE VDD Power is turned on. 0 = None 1 = Select 1'b0 COREPORtimeSEL2 [2] RW CORE POR (Power On Reset) releases with the delay of about 62 ms after CORE VDD Power is turned on. 0 = None 1 = Select 1'b0 COREPORtimeSEL1 [1] RW CORE POR (Power On Reset) releases with the delay of about 31 ms after CORE VDD Power is turned on. 0 = None 1 = Select 1'b0 COREPORtimeSEL0 [0] RW CORE POR (Power On Reset) releases without delay after CORE VDD Power is turned on. 0 = None 1 = Select 1'b0 NOTE: CORE POR releases about 210 ms after CORE VDD Power is turned on when RTCCOREPORIMESEL[6:0] == 7'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 11 RTC 11-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

11.5.1.8 WTCON

 Base Address: 0xC001_0C00h  Address = Base Address + 0x1Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RTCscratch [31:0] RW RTC scratch register. 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12 Alive

12.1 Overview

In the status with eliminating core power supply of S5P4418, some PAD need power supply continuously and should keep driving PAD with certain value. For example a bit that controlling STN LCD should keep driving PAD with low in the status with eliminating core power supply. 32-bit value can be saved in Scratch Register and the saved value maintains in the case of core power off. User could on/off the system power by pressing toggle switch and ALIVE performs the necessary functions in these momentary power controls.

12.2 Features

Alive GPIO PADs are all in/output PAD.  The value of ALIVE Block maintains even in power off of Core Power.  Alive Block does not use clock. To change the control register value, need to program set/reset pin of SR - flipflop directly.  Chip sleep mode wake-up source (AliveGPIO, VDDToggle, RTCIRQ)  Power IC Enable.  Supports the PAD Hold function Scan chain is not inserted to Alive GPIO. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.3 Power Isolation

12.3.1 Core Power Off

In the case of power off of CoreVDD, Alive Registers maintains its value since Alive VDD keep supplied. Pull - down register connected to nPowerGating performs the function of maintaining control bit of Alive Registers securely in the interval of core power off or unstable.

12.3.2 Power Gating

The value of set/reset should be kept as low to maintains the value of Alive Registers securely in the case of power off of CoreVDD. Therefore, it's designed to maintain low value in the case of core power off since nPowerGating register is connected to pull-down register. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.4 Alive Registers

All of the Registers except nPowerGating/AliveDetectPending Register of Alive block maintains the value written in Register when Core power turns off, and are reset when Alive Power turns off. Alive Registers do not have their own Clock, and these can be read and written when nPowerGating register is "1" (nPowerGating = 1). And especially, in write mode, Alive Registers can be written by SET/RST (reset) Register. The following is the example of the Register function according to Register SET/RST. Alive Registers remains as the former state when Regiser_nameSET == 0, Regiser_nameRST=0 Alive Registers are written as "1" when Regiser_nameSET == 1, Regiser_nameRST=0 Alive Registers are written as "0" write "0" when Regiser_nameSET == 0, Regiser_nameRST=1 Alive Registers are written as "1" when Regiser_nameSET == 1, Regiser_nameRST=1

12.4.1 Alive GPIO Detect Registers

For Alive GPIO input, Alive GPIO Detect Registers can be used as Core Power on, Alive Interrupt, Sleep mode wakeup source in case of Asynchronous/synchronous detecting mode. And when those events are detected, ALIVEGPIODETECTPENDREG[n] Register is set to "1". The following are the operating examples according to Detecting modes. Ex1) Asynchronous Low Level Detecting Alive GPIO Detect Registers detect the event when ALIVEGPIOLOWASYNCDETECTMODEREADREG [n] = "1", ALIVEGPIODETECTENBREADREG[n] = "1", and AliveGPIO ==0 Ex2) Asynchronous High Level Detecting Alive GPIO Detect Registers detect the event when ALIVEGPIOHIGHASYNCDETECTMODEREADREG [n] = "1", ALIVEGPIODETECTENBREADREG[n] = "1", and AliveGPIO[n] == "1" Ex3) Synchronous Low Level Detecting Alive GPIO Detect Registers detect the event when ALIVEGPIOLOWSYNCDETECTMODEREADREG [n] = "1", ALIVEGPIODETECTENBREADREG[n] = "1", AliveGPIO[n] == "0" Ex4) Synchronous High Level Detecting Alive GPIO Detect Registers detect the event when ALIVEGPIOHIGHSYNCDETECTMODEREADREG [n] = "1", ALIVEGPIODETECTENBREADREG[n] = "1", AliveGPIO[n] == "1" Ex5) Synchronous Falling Edge Detecting Alive GPIO Detect Registers detect the event when ALIVEGPIOFALLDETECTMODEREADREG[n] = "1", ALIVEGPIODETECTENBREADREG[n] = "1", and AliveGPIO[n] bit changes from "1" to "0" Ex6) Synchronous Rising Edge Detecting Alive GPIO Detect Registers detect the event when ALIVEGPIORISEDETECTMODEREADREG [n] = "1", ALIVEGPIODETECTENBREADREG[n] = "1", and AliveGPIO[n] bit changes from "0" to "1" cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.4.2 Scratch Register

Programmer could save any 32bit value in Scratch Register. The value of Scratch Register maintains in the case of power off of CoreVDD.

12.4.3 Alive GPIO Control Registers

Alive GPIO is controlled through Alive Block regardless of GPIO block. Control Register has AliveGPIO in/out mode enable, pull-up, and AliveGPIOPADOut. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.5 Momentary Power Control

12.5.1 CoreVDD Powering On

The Core Power can be changed from off-state to on-state by the VDDPWRTOGGLE switch, AliveGPIO Detecting, RTC interrupt. And in case of Power on, VDDPWRTOGGLE switch, AliveGPIO Detecting, and RTC interrupt can be processed, after system booting, by setting VDDPWRON_DDR/VDDPWRON Bit. (Power On is not allowed when Battery Fault occurs.).

12.5.2 CoreVDD Powering Off

The Core Power can be changed from off-state to on-state by clearing VDDPWRON_DDR/VDDPWRON Bit. Core Block and Alive Block are connected through PowerGating Register, which makes it possible for Alive Registers to safely sustain their own values even after Core Power turns off with VDDPWRON_DDR/VDDPWRON Bit cleared. The following is the example of Chip Power sequence 1. Do not hold the initial Pad state. (nPadHold = 1) 2. Hold the Pad before you turn off the Power. (nPadHold Register = 0) 3. Turn off VDDPWRON 4. Non-Alive POR is set low after power turns off 5. Power starts to be supplied by pressing toggle switch 6. PAD releases from the hold state when internal POR turns on (which provides the stability for preventing pad hold from releasing after power turns on) 7. VDDPWRON and PadHold Register should be released simultaneously after system booting. 8. VDDPOWRON should be released. nPadHoldEnb Register should be set as "0" except Power On Reset. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.6 SLEEP Mode

S5P4418 supports two SLEEP Modes (SleepMode1, SleepMode2). Core power turns off in SLEEP Mode, and the Chip wakes up from SLEEP Mode by Wake-up sources such as AliveGPIO Detecting, RTC Interrupt, and nVDDPWRTOGGLE Switch push.(And, No wake-up is possible in case of battery fault)  Alive GPIO Detect Pending Register Clear  Hold the Pad before user turns off Power. (SleepMode1: nPadHold[2:1] = 2'b00, SleepMode2: nPadHold[2:0] == 3'b000)  VDDPWRON Register Clear  nPowerGating Register Clear  S5P4418 STOP Mode Set(Refer to Clock and Power management Section) cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.7 PMU (Power management Unit)

12.7.1 Overview

PMU is a block inside of ALIVE. It controls internal power switch of sub-blocks in chip. PMU can controls the power up and down of these blocks:  GPU (graphic processing unit)  MFC (multi function codec)

12.7.2 Power Mode Table

PD_RTC PD_ALIVE PD_TOP PD_DREX PD_CODEC PD_GR3D PD_CPU Num. Name

1 POWER ON RESET ON ON ON ON ON ON ON

2 NORMAL ON ON ON ON ON ON ON

3 SUB SLEEP - 0 ON ON ON ON OFF ON ON

4 SUB SLEEP - 1 ON ON ON ON ON OFF ON

5 SUB SLEEP - ALL ON ON ON ON OFF OFF ON

6 DEEP IDLE ON ON ON ON OFF OFF OFF

7 TOP SLEEP ON ON OFF OFF OFF OFF OFF

8 RTC ONLY ON OFF OFF OFF OFF OFF OFF

12.7.3 Power Switch Control Sequence

Figure 12-1 Power Switch Control Sequence cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8 Register Description

12.8.1 Register Map Summary

 Base Address:C001_0000h Register Offset Description Reset Value ALIVEPWRGATEREG 0800h Alive Power Gating Register 0x0000_0000 ALIVEGPIOASYNCDETECTMODE RSTREG0 0804h Alive GPIO ASync Detect Mode Reset Register 0 0x0000_0000 ALIVEGPIOASYNCDETECTMODE RSTREG1 0810h Alive GPIO ASync Detect Mode Reset Register 1 0x0000_0000 ALIVEGPIOASYNCDETECTMODE SETREG0 0808h Alive GPIO ASync Detect Mode Set Register 0 0x0000_0000 ALIVEGPIOASYNCDETECTMODE SETREG1 0814h Alive GPIO ASync Detect Mode Set Register 1 0x0000_0000 ALIVEGPIOLOWASYNCDETECTM ODEREADREG 080Ch Alive GPIO Low Level Async Detect Mode Read Register 0x0000_0000 ALIVEGPIOHIGHASYNCDETECT MODEREADREG 0818h Alive GPIO High Level Async Detect Mode Read Register 0x0000_0000 ALIVEGPIODETECTMODERSTRE G0 081Ch Alive GPIO Detect Mode Reset Register 0 0x0000_0000 ALIVEGPIODETECTMODERSTRE G1 0828h Alive GPIO Detect Mode Reset Register 1 0x0000_0000 ALIVEGPIODETECTMODERSTRE G2 0834h Alive GPIO Detect Mode Reset Register 2 0x0000_0000 ALIVEGPIODETECTMODERSTRE G3 0840h Alive GPIO Detect Mode Reset Register 3 0x0000_0000 ALIVEGPIODETECTMODESETRE G0 0820h Alive GPIO Detect Mode Set Register 0 0x0000_0000 ALIVEGPIODETECTMODESETRE G1 082Ch Alive GPIO Detect Mode Set Register 1 0x0000_0000 ALIVEGPIODETECTMODESETRE G2 0838h Alive GPIO Detect Mode Set Register 2 0x0000_0000 ALIVEGPIODETECTMODESETRE G3 0844h Alive GPIO Detect Mode Set Register 3 0x0000_0000 ALIVEGPIOFALLDETECTMODER EADREG 0824h Alive GPIO Falling Edge Detect Mode Read Register 0x0000_0000 ALIVEGPIORISEDETECTMODERE ADREG 0830h Alive GPIO Rising Edge Detect Mode Read Register 0x0000_0000 ALIVEGPIOLOWDETECTMODERE ADREG 083Ch Alive GPIO Low Level Detect Mode Read Register 0x0000_0000 ALIVEGPIOHIGHDETECTMODER EADREG 0848h Alive GPIO High Level Detect Mode Read Register 0x0000_0000 ALIVEGPIODETECTENBRSTREG 084Ch Alive GPIO Detect Enable Reset Register 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value ALIVEGPIODETECTENBSETREG 0850h Alive GPIO Detect Enable Set Register 0x0000_0000 ALIVEGPIODETECTENBREADRE G 0854h Alive GPIO Detect Enable Read Register 0x0000_0000 ALIVEGPIOINTENBRSTREG 0858h Alive GPIO Interrupt Enable Reset Register 0x0000_0000 ALIVEGPIODETECTENABLESETR EG 085Ch Alive GPIO Detect Enable Set Register 0x0000_0000 ALIVEGPIOINTENBREADREG 0860h Alive GPIO Interrupt Enable Read Register 0x0000_0000 ALIVEGPIODETECTPENDREG 0864h Alive GPIO Detect Pending Register 0x0000_0000 ALIVESCRATCHRSTREG 0868h Alive Scratch Reset Register 0x0000_0000 ALIVESCRATCHSETREG 086Ch Alive Scratch Set Register 0x0000_0000 ALIVESCRATCHREADREG 0870h Alive Scratch Read Register 0x0000_0000 ALIVEGPIOPADOUTENBRSTREG 0874h Alive GPIO PAD Out Enable Reset Register 0x0000_0000 ALIVEGPIOPADOUTENBSETREG 0878h Alive GPIO PAD Out Enable Set Register 0x0000_0000 ALIVEGPIOPADOUTENBREADRE G 087Ch Alive GPIO PAD Out Enable Read Register 0x0000_0000 ALIVEGPIOPADPULLUPRSTREG 0880h Alive GPIO PAD Pullup Reset Register 0x0000_0000 ALIVEGPIOPADPULLUPSETREG 0884h Alive GPIO PAD Pullup Set Register 0x0000_0000 ALIVEGPIOPADPULLUPREADRE G 0888h Alive GPIO PAD Pullup Read Register 0x0000_00FF ALIVEGPIOPADOUTRSTREG 088Ch Alive GPIO PAD Out Reset Register 0x0000_0000 ALIVEGPIOPADOUTSETREG 0890h Alive GPIO PAD Out Set Register 0x0000_0000 ALIVEGPIOPADOUTREADREG 0894h Alive GPIO PAD Out Read Register 0x0000_0000 VDDCTRLRSTREG 0898h VDD Control reset Register 0x0000_0000 VDDCTRLSETREG 089Ch VDD Control set Register 0x0000_0000 VDDCTRLREADREG 08A0h VDD Control Read Register 0x0000_03FF ALIVECLEARWAKEUPSTATUSRE GISTER 08A4h Alive Clear Wakeup Status Register 0x0000_0000 ALIVESLEEPWAKEUPSTATUSRE GISTER 08A8h Alive Sleep Wakeup Status Register 0x0000_0000 ALIVESCRATCHRSTREG1 08ACh Alive Scratch Reset Register1 0x0000_0000 ALIVESCRATCHRSTREG2 08B8h Alive Scratch Reset Register2 0x0000_0000 ALIVESCRATCHRSTREG3 08C4h Alive Scratch Reset Register3 0x0000_0000 ALIVESCRATCHRSTREG4 08D0h alive scratch reset register4 0x0000_0000 ALIVESCRATCHRSTREG5 08DCh Alive Scratch Reset Register5 0x0000_0000 ALIVESCRATCHRSTREG6 08E8h Alive Scratch Reset Register6 0x0000_0000 ALIVESCRATCHRSTREG7 08F4h Alive Scratch Reset Register7 0x0000_0000 ALIVESCRATCHRSTREG8 0900h Alive Scratch Reset Register8 0x0000_0000 ALIVESCRATCHSETREG1 08B0h Alive Scratch Set Register1 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value ALIVESCRATCHSETREG2 08BCh Alive Scratch Set Register2 0x0000_0000 ALIVESCRATCHSETREG3 08C8h Alive Scratch Set Register3 0x0000_0000 ALIVESCRATCHSETREG4 08D4h Alive Scratch Set Register4 0x0000_0000 ALIVESCRATCHSETREG5 08E0h Alive Scratch Set Register5 0x0000_0000 ALIVESCRATCHSETREG6 08ECh Alive Scratch Set Register6 0x0000_0000 ALIVESCRATCHSETREG7 08F8h Alive Scratch Set Register7 0x0000_0000 ALIVESCRATCHSETREG8 0904h Alive Scratch Set Register8 0x0000_0000 ALIVESCRATCHREADREG1 08B4h Alive Scratch Read Register1 0x0000_0000 ALIVESCRATCHREADREG2 08C0h Alive Scratch Read Register2 0x0000_0000 ALIVESCRATCHREADREG3 08CCh Alive Scratch Read Register3 0x0000_0000 ALIVESCRATCHREADREG4 08D8h Alive Scratch Read Register4 0x0000_0000 ALIVESCRATCHREADREG5 08E4h Alive Scratch Read Register5 0x0000_0000 ALIVESCRATCHREADREG6 08F0h Alive Scratch Read Register6 0x0000_0000 ALIVESCRATCHREADREG7 08FCh Alive Scratch Read Register7 0x0000_0000 ALIVESCRATCHREADREG8 0908h Alive Scratch Read Register8 0x0000_0000 VDDOFFDELAYRSTREGISTER 090Ch VDD Off Delay Reset Register 0x0000_0000 VDDOFFDELAYSETREGISTER 0910h VDD Off Delay Set Register 0x0000_0000 VDDOFFDELAYVALUEREGISTER 0914h VDD Off Delay Value Register 0x0000_0000 VDDOFFDELAYTIMEREGISTER 0918h VDD Off Delay Time Register 0x0000_0000 ALIVEGPIOINPUTVALUE 091Ch Alive GPIO Input Value Read Register 0x0000_0000 RSVD ~ 0BFFh Reserved - RTC 0C00h 0CFFh See RTC section - PMUNISOLATE 0D00h PMU nISOLATE Register 0x0000_0003 PMUNPWRUPPRE 0D04h PMU nPOWER Up Precharge Register 0x0000_0000 PMUNPWRUP 0D08h PMU nPOWER Up Register 0x0000_0000 PMUNPWRUPACK 0D0Ch PMU nPOWER Up ACK Register 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.1 ALIVEPWRGATEREG

 Base Address: C001_0000h  Address = Base Address + 0800h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:1] – Reserved 0 NPOWERGATING [0] RW nPowerGating (negative active Power Gating). The default value is 0, disabling writing to Alive Registers, in order to keep the values of Alive Registers when Core Power 1.0V is off. 0 = Disable writing data to Alive Register 1 = Enable writing data to Alive Register 1'b0

12.8.1.2 ALIVEGPIOASYNCDETECTMODERSTREG0

 Base Address: C001_0000h  Address = Base Address + 0804h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 ASyncdetectmoderST0_7 [7] RW Alive GPIO7 Low Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetectmoderST0_6 [6] RW Alive GPIO6 Low Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetectmoderST0_5 [5] RW Alive GPIO5 Low Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetectmoderST0_4 [4] RW Alive GPIO4 Low Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetectmoderST0_3 [3] RW Alive GPIO3 Low Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetectmoderST0_2 [2] RW Alive GPIO2 Low Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetectmoderST0_1 [1] RW Alive GPIO1 Low Level Async detect mode Register 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Reset. 0 = None 1 = Reset ASyncdetectmoderST0_0 [0] RW Alive GPIO0 Low Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0

12.8.1.3 ALIVEGPIOASYNCDETECTMODERSTREG1

 Base Address: C001_0000h  Address = Base Address + 0810h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 ASyncdetecTMODERST 1_7 [7] RW Alive GPIO7 High Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetecTMODERST 1_6 [6] RW Alive GPIO6 High Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetecTMODERST 1_5 [5] RW Alive GPIO5 High Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetecTMODERST 1_4 [4] RW Alive GPIO4 High Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetecTMODERST 1_3 [3] RW Alive GPIO3 High Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetecTMODERST 1_2 [2] RW Alive GPIO2 High Level Async detect enable Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetecTMODERST 1_1 [1] RW Alive GPIO1 High Level Async detect mode Register Reset. 0 = None 1 = Reset 1'b0 ASyncdetecTMODERST 1_0 [0] RW Alive GPIO0 High Level Async detect mode Register Reset. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 0 = None 1 = Reset

12.8.1.4 ALIVEGPIOASYNCDETECTMODESETREG0

 Base Address: C001_0000h  Address = Base Address + 0808h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 ASyncdetectMODEset0_7 [7] RW Alive GPIO7 Low Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectMODEset0_6 [6] RW Alive GPIO6 Low Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectMODEset0_5 [5] RW Alive GPIO5 Low Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectMODEset0_4 [4] RW Alive GPIO4 Low Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectMODEset0_3 [3] RW Alive GPIO3 Low Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectMODEset0_2 [2] RW Alive GPIO2 Low Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectMODEset0_1 [1] RW Alive GPIO1 Low Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectMODEset0_0 [0] RW Alive GPIO0 Low Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.5 ALIVEGPIOASYNCDETECTMODESETREG1

 Base Address: C001_0000h  Address = Base Address + 0814h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 ASyncdetectmodeset1_7 [7] RW Alive GPIO7 High Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectmodeset1_6 [6] RW Alive GPIO6 High Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectmodeset1_5 [5] RW Alive GPIO5 High Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectmodeset1_4 [4] RW Alive GPIO4 High Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectmodeset1_3 [3] RW Alive GPIO3 High Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetecenbset1_2 [2] RW Alive GPIO2 High Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectmodeset1_1 [1] RW Alive GPIO1 High Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 ASyncdetectmodeset1_0 [0] RW Alive GPIO0 High Level Async detect mode Register Set. 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.6 ALIVEGPIOLOWASYNCDETECTMODEREADREG

 Base Address: C001_0000h  Address = Base Address + 080Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 alivegpiolowasyncdetect MODE7 [7] R Alive GPIO7 Low level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpiolowasyncdetect MODE6 [6] R Alive GPIO6 Low level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpiolowasyncdetect MODE5 [5] R Alive GPIO5 Low level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpiolowasyncdetect MODE4 [4] R Alive GPIO4 Low level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpiolowasyncdetect MODE3 [3] R Alive GPIO3 Low level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpiolowasyncdetect MODE2 [2] R Alive GPIO2 Low level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpiolowasyncdetect MODE1 [1] R Alive GPIO1 Low level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpiolowasyncdetect MODE0 [0] R Alive GPIO0 Low level Async detect mode register 0 = Disable 1 = Enable 1'b0 NOTE: ALIVEGPIOLOWASYNCDETECTMODE(n) Register operates as follows It remains as the former state in case of {ASYNCDETECTENBRST0_(n), ASYNCDETECTENBSET0_(n)} = 2'b00 It is set as "1" in case of {ASYNCDETECTENBRST0_(n), ASYNCDETECTENBSET0_(n)} = 2'b01 It is set as "0" in case of {ASYNCDETECTENBRST0_(n), ASYNCDETECTENBSET0_(n)} = 2'b10 It is set as "1" in case of {ASYNCDETECTENBRST0_(n), ASYNCDETECTENBSET0_(n)} = 2'b11 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.7 ALIVEGPIOHIGHASYNCDETECTMODEREADREG

 Base Address: C001_0000h  Address = Base Address + 0818h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 alivegpiohighasyncdetect Mode7 [7] R Alive GPIO7 High level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHighasyncdetect mode6 [6] R Alive GPIO6 High level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHighasyncdetect mode5 [5] R Alive GPIO5 High level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHighasyncdetect mode4 [4] R Alive GPIO4 High level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHighasyncdetect mode3 [3] R Alive GPIO3 High level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHighasyncdetect mode2 [2] R Alive GPIO2 High level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHighasyncdetect mode1 [1] R Alive GPIO1 High level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHighasyncdetect mode0 [0] R Alive GPIO0 High level Async detect mode register 0 = Disable 1 = Enable 1'b0 NOTE: ALIVEGPIOHIGHASYNCDETECTMODE(n) Register operates as follows It remains as the former state in case of {ASYNCDETECTMODERST1_(n), ASYNCDETECTMODESET1_(n)} = 2'b00 It is set as "1" in case of {ASYNCDETECTMODERST1_(n), ASYNCDETECTMODESET1_(n)} = 2'b01 It is set as "0" in case of {ASYNCDETECTMODERST1_(n), ASYNCDETECTMODESET1_(n)} = 2'b10 It is set as "1" in case of {ASYNCDETECTMODERST1_(n), ASYNCDETECTMODESET1_(n)} = 2'b11 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.8 ALIVEGPIODETECTMODERSTREG0

 Base Address: C001_0000h  Address = Base Address + 081Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 detecTMODERST0_7 [7] RW Alive GPIO7 Falling Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST0_6 [6] RW Alive GPIO6 Falling Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST0_5 [5] RW Alive GPIO5 Falling Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST0_4 [4] RW Alive GPIO4 Falling Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST0_3 [3] RW Alive GPIO3 Falling Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST0_2 [2] RW Alive GPIO2 Falling Edge detect enable Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST0_1 [1] RW Alive GPIO1 Falling Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST0_0 [0] RW Alive GPIO0 Falling Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.9 ALIVEGPIODETECTMODERSTREG1

 Base Address: C001_0000h  Address = Base Address + 0828h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 detecTMODERST1_7 [7] RW Alive GPIO7 Rising Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST1_6 [6] RW Alive GPIO6 Rising Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST1_5 [5] RW Alive GPIO5 Rising Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST1_4 [4] RW Alive GPIO4 Rising Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST1_3 [3] RW Alive GPIO3 Rising Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST1_2 [2] RW Alive GPIO2 Rising Edge detect enable Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST1_1 [1] RW Alive GPIO1 Rising Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST1_0 [0] RW Alive GPIO0 Rising Edge detect mode Register Reset. 0 = None 1 = Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.10 ALIVEGPIODETECTMODERSTREG2

 Base Address: C001_0000h  Address = Base Address + 0834h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 detecTMODERST2_7 [7] RW Alive GPIO7 Low Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST2_6 [6] RW Alive GPIO6 Low Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST2_5 [5] RW Alive GPIO5 Low Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST2_4 [4] RW Alive GPIO4 Low Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST2_3 [3] RW Alive GPIO3 Low Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST2_2 [2] RW Alive GPIO2 Low Level detect enable Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST2_1 [1] RW Alive GPIO1 Low Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST2_0 [0] RW Alive GPIO0 Low Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.11 ALIVEGPIODETECTMODERSTREG3

 Base Address: C001_0000h  Address = Base Address + 0840h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 detecTMODERST3_7 [7] RW Alive GPIO7 High Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST3_6 [6] RW Alive GPIO6 High Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST3_5 [5] RW Alive GPIO5 High Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST3_4 [4] RW Alive GPIO4 High Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST3_3 [3] RW Alive GPIO3 High Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST3_2 [2] RW Alive GPIO2 High Level detect enable Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST3_1 [1] RW Alive GPIO1 High Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 detecTMODERST3_0 [0] RW Alive GPIO0 High Level detect mode Register Reset. 0 = None 1 = Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.12 ALIVEGPIODETECTMODESETREG0

 Base Address: C001_0000h  Address = Base Address + 0820h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 detectmodeset0_7 [7] RW Alive GPIO7 Falling Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detectmodeset0_6 [6] RW Alive GPIO6 Falling Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detectmodeset0_5 [5] RW Alive GPIO5 Falling Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detectmodeset0_4 [4] RW Alive GPIO4 Falling Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detectmodeset0_3 [3] RW Alive GPIO3 Falling Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detectmodeset0_2 [2] RW Alive GPIO2 Falling Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detectmodeset0_1 [1] RW Alive GPIO1 Falling Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detectmodeset0_0 [0] RW Alive GPIO0 Falling Edge detect mode Register Set. 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.13 ALIVEGPIODETECTMODESETREG1

 Base Address: C001_0000h  Address = Base Address + 082Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 detecTMODESET1_7 [7] RW Alive GPIO7 Rising Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET1_6 [6] RW Alive GPIO6 Rising Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET1_5 [5] RW Alive GPIO5 Rising Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET1_4 [4] RW Alive GPIO4 Rising Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET1_3 [3] RW Alive GPIO3 Rising Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET1_2 [2] RW Alive GPIO2 Rising Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET1_1 [1] RW Alive GPIO1 Rising Edge detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET1_0 [0] RW Alive GPIO0 Rising Edge detect mode Register Set. 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.14 ALIVEGPIODETECTMODESETREG2

 Base Address: C001_0000h  Address = Base Address + 0838h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 detecTMODESET2_7 [7] RW Alive GPIO7 Low Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET2_6 [6] RW Alive GPIO6 Low Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET2_5 [5] RW Alive GPIO5 Low Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET2_4 [4] RW Alive GPIO4 Low Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET2_3 [3] RW Alive GPIO3 Low Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET2_2 [2] RW Alive GPIO2 Low Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET2_1 [1] RW Alive GPIO1 Low Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET2_0 [0] RW Alive GPIO0 Low Level detect mode Register Set. 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.15 ALIVEGPIODETECTMODESETREG3

 Base Address: C001_0000h  Address = Base Address + 0844h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 detecTMODESET3_7 [7] RW Alive GPIO7 High Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET3_6 [6] RW Alive GPIO6 High Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET3_5 [5] RW Alive GPIO5 High Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET3_4 [4] RW Alive GPIO4 High Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET3_3 [3] RW Alive GPIO3 High Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET3_2 [2] RW Alive GPIO2 High Level detect mode Register Set. 0 = None 1 = Set 0 : none 1: Set 1'b0 detecTMODESET3_1 [1] RW Alive GPIO1 High Level detect mode Register Set. 0 = None 1 = Set 1'b0 detecTMODESET3_0 [0] RW Alive GPIO0 High Level detect mode Register Set. 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.16 ALIVEGPIOFALLDETECTMODEREADREG

 Base Address: C001_0000h  Address = Base Address + 0824h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 alivegpioFALLdetectMod e7 [7] R Alive GPIO7 Falling Edge detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioFALLdetectMod e6 [6] R Alive GPIO6 Falling Edge detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioFALLdetectMod e5 [5] R Alive GPIO5 Falling Edge detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioFALLdetectMod e4 [4] R Alive GPIO4 Falling Edge Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioFALLdetectMod e3 [3] R Alive GPIO3 Falling Edge detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioFALLdetectMod e2 [2] R Alive GPIO2 Falling Edge detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioFALLdetectMod e1 [1] R Alive GPIO1 Falling Edge detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioFALLdetectMod e0 [0] R Alive GPIO0 Falling Edge detect mode register 0 = Disable 1 = Enable 1'b0 NOTE: ALIVEGPIOFALLDETECTMODE(n) Register operates as follows It remains as the former state in case of {DETECTMODERST0_(n), DETECTMODESET0_(n)} = 2'b00 It is set as "1" in case of {DETECTMODERST0_(n), DETECTMODESET0_(n)} = 2'b01 It is set as "0" in case of {DETECTMODERST0_(n), DETECTMODESET0_(n)} = 2'b10 It is set as "1" in case of {DETECTMODERST0_(n), DETECTMODESET0_(n)} = 2'b11 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-26 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.17 ALIVEGPIORISEDETECTMODEREADREG

 Base Address: C001_0000h  Address = Base Address + 8030h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 alivegpioRISEdetectMod e7 [7] R Alive GPIO7 Rising Edge detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioRISEdetectMod e6 [6] R Alive GPIO6 Rising Edge detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioRISEdetectMod e5 [5] R Alive GPIO5 Rising Edge detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioRISEdetectMod e4 [4] R Alive GPIO4 Rising Edge Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioRISEdetectMod e3 [3] R Alive GPIO3 Rising Edge detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioRISEdetectMod e2 [2] R Alive GPIO2 Rising Edge detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioRISEdetectMod e1 [1] R Alive GPIO1 Rising Edge detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioRISEdetectMod e0 [0] R Alive GPIO0 Rising Edge detect mode register 0 = Disable 1 = Enable 1'b0 NOTE: ALIVEGPIORISEDETECTMODE(n) Register operates as follows It remains as the former state in case of {DETECTMODERST1_(n), DETECTMODESET1_(n)} = 2'b00 It is set as "1" in case of {DETECTMODERST1_(n), DETECTMODESET1_(n)} = 2'b01 It is set as "0" in case of {DETECTMODERST1_(n), DETECTMODESET1_(n)} = 2'b10 It is set as "1" in case of {DETECTMODERST1_(n), DETECTMODESET1_(n)} = 2'b11 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.18 ALIVEGPIOLOWDETECTMODEREADREG

 Base Address: C001_0000h  Address = Base Address + 083Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 alivegpioLOWdetectMod e7 [7] R Alive GPIO7 Low Level detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioLOWdetectMod e6 [6] R Alive GPIO6 Low Level detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioLOWdetectMod e5 [5] R Alive GPIO5 Low Level detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioLOWdetectMod e4 [4] R Alive GPIO4 Low Level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioLOWdetectMod e3 [3] R Alive GPIO3 Low Level detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioLOWdetectMod e2 [2] R Alive GPIO2 Low Level detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioLOWdetectMod e1 [1] R Alive GPIO1 Low Level detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioLOWdetectMod e0 [0] R Alive GPIO0 Low Level detect mode register 0 = Disable 1 = Enable 1'b0 NOTE: ALIVEGPIOLOWDETECTMODE(n) Register operates as follows It remains as the former state in case of {DETECTMODERST2_(n), DETECTMODESET2_(n)} = 2'b00 It is set as "1" in case of {DETECTMODERST2_(n), DETECTMODESET2_(n)} = 2'b01 It is set as "0" in case of {DETECTMODERST2_(n), DETECTMODESET2_(n)} = 2'b10 It is set as "1" in case of {DETECTMODERST2_(n), DETECTMODESET2_(n)} = 2'b11 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-28 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.19 ALIVEGPIOHIGHDETECTMODEREADREG

 Base Address: C001_0000h  Address = Base Address + 0848h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 alivegpioHIGHdetectMod e7 [7] R Alive GPIO7 High Level detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHIGHdetectMod e6 [6] R Alive GPIO6 High Level detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHIGHdetectMod e5 [5] R Alive GPIO5 High Level detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHIGHdetectMod e4 [4] R Alive GPIO4 High Level Async detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHIGHdetectMod e3 [3] R Alive GPIO3 High Level detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHIGHdetectMod e2 [2] R Alive GPIO2 High Level detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHIGHdetectMod e1 [1] R Alive GPIO1 High Level detect mode register 0 = Disable 1 = Enable 1'b0 alivegpioHIGHdetectMod e0 [0] R Alive GPIO0 High Level detect mode register 0 = Disable 1 = Enable 1'b0 NOTE: ALIVEGPIOHIGHTDETECTMODE(n) Register operates as follows It remains as the former state in case of {DETECTMODERST3_(n), DETECTMODESET3_(n)} = 2'b00 It is set as "1" in case of {DETECTMODERST3_(n), DETECTMODESET3_(n)} = 2'b01 It is set as "0" in case of {DETECTMODERST3_(n), DETECTMODESET3_(n)} = 2'b10 It is set as "1" in case of {DETECTMODERST3_(n), DETECTMODESET3_(n)} = 2'b11 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-29 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.20 ALIVEGPIODETECTENBRSTREG

 Base Address: C001_0000h  Address = Base Address + 084Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 detecTENBRST7 [7] RW Alive GPIO7 Detect Enable Register Reset. 0 = None 1 = Reset 1'b0 detecTENBRST6 [6] RW Alive GPIO6 Detect Enable Register Reset. 0 = None 1 = Reset 1'b0 detecTENBRST5 [5] RW Alive GPIO5 Detect Enable Register Reset. 0 = None 1 = Reset 1'b0 detecTENBRST4 [4] RW Alive GPIO4 Detect Enable Register Reset. 0 = None 1 = Reset 1'b0 detecTENBRST3 [3] RW Alive GPIO3 Detect Enable Register Reset. 0 = None 1 = Reset 1'b0 detecTENBRST2 [2] RW Alive GPIO2 Detect Enable Register Reset. 0 = None 1 = Reset 1'b0 detecTENBRST1 [1] RW Alive GPIO1 Detect Enable Register Reset. 0 = None 1 = Reset 1'b0 detecTENBRST0 [0] RW Alive GPIO0 Detect Enable Register Reset. 0 = None 1 = Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-30 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.21 ALIVEGPIODETECTENBSETREG

 Base Address: C001_0000h  Address = Base Address + 0850h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 detecTENBSET7 [7] RW Alive GPIO7 Detect Enable Register Set. 0 = None 1 = Set 1'b0 detecTenbSET6 [6] RW Alive GPIO6 Detect Enable Register Set. 0 = None 1 = Set 1'b0 detecTenbSET5 [5] RW Alive GPIO5 Detect Enable Register Set. 0 = None 1 = Set 1'b0 detecTenbSET4 [4] RW Alive GPIO4 Detect Enable Register Set. 0 = None 1 = Set 1'b0 detecTenbSET3 [3] RW Alive GPIO3 Detect Enable Register Set. 0 = None 1 = Set 1'b0 detecTenbSET2 [2] RW Alive GPIO2 Detect Enable Register Set. 0 = None 1 = Set 1'b0 detecTenbSET1 [1] RW Alive GPIO1 Detect Enable Register Set. 0 = None 1 = Set 1'b0 detecTenbSET0 [0] RW Alive GPIO0 Detect Enable Register Set. 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-31 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.22 ALIVEGPIODETECTENBREADREG

 Base Address: C001_0000h  Address = Base Address + 0854h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 alivegpiodetectENB7 [7] R Alive GPIO7 Detect Enable register 0 = Disable 1 = Enable 1'b0 alivegpiodetectENB6 [6] R Alive GPIO6 Detect Enable register 0 = Disable 1 = Enable 1'b0 alivegpiodetectENB5 [5] R Alive GPIO5 Detect Enable register 0 = Disable 1 = Enable 1'b0 alivegpiodetectENB4 [4] R Alive GPIO4 Detect Enable register 0 = Disable 1 = Enable 1'b0 alivegpiodetectENB3 [3] R Alive GPIO3 Detect Enable register 0 = Disable 1 = Enable 1'b0 alivegpiodetectENB2 [2] R Alive GPIO2 Detect Enable register 0 = Disable 1 = Enable 1'b0 alivegpiodetectENB1 [1] R Alive GPIO1 Detect Enable register 0 = Disable 1 = Enable 1'b0 alivegpiodetectENB0 [0] R Alive GPIO0 Detect Enable register 0 = Disable 1 = Enable 1'b0 NOTE: ALIVEGPIODETECTENB (n) Register operates as follows It remains as the former state in case of {DETECTENBRST(n), DETECTENBSET(n)} = 2'b00 It is set as "1" in case of {DETECTENBRST(n), DETECTENBSET(n)} = 2'b01 It is set as "0" in case of {DETECTENBRST(n), DETECTENBSET(n)} = 2'b10 It is set as "1" in case of {DETECTENBRST(n), DETECTENBSET(n)} = 2'b11 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-32 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.23 ALIVEGPIOINTENBRSTREG

 Base Address: C001_0000h  Address = Base Address + 0858h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 ALIVEGPIOINTENBRST 7 [7] RW Alive GPIO7 Interrupt Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOINTENBRST 6 [6] RW Alive GPIO6 Interrupt Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOINTENBRST 5 [5] RW Alive GPIO5 Interrupt Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOINTENBRST 4 [4] RW Alive GPIO4 Interrupt Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOINTENBRST 3 [3] RW Alive GPIO3 Interrupt Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOINTENBRST 2 [2] RW Alive GPIO2 Interrupt Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOINTENBRST 1 [1] RW Alive GPIO1 Interrupt Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOINTENBRST 0 [0] RW Alive GPIO0 Interrupt Enable Register Reset. 0 = None 1 = Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-33 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.24 ALIVEGPIODETECTENABLESETREG

 Base Address: C001_0000h  Address = Base Address + 085Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 ALIVEGPIOINTENBSET 7 [7] RW Alive GPIO7 Interrupt Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOINTENBSET 6 [6] RW Alive GPIO6 Interrupt Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOINTENBSET 5 [5] RW Alive GPIO5 Interrupt Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOINTENBSET 4 [4] RW Alive GPIO4 Interrupt Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOINTENBSET 3 [3] RW Alive GPIO3 Interrupt Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOINTENBSET 2 [2] RW Alive GPIO2 Interrupt Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOINTENBSET 1 [1] RW Alive GPIO1 Interrupt Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOINTENBSET 0 [0] RW Alive GPIO0 Interrupt Enable Register Set. 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-34 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.25 ALIVEGPIOINTENBREADREG

 Base Address: C001_0000h  Address = Base Address + 0860h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 alivegpioINTENB7 [7] R Alive GPIO7 Interrupt Enable register 0 = Disable 1 = Enable 1'b0 alivegpioINTENB6 [6] R Alive GPIO6 Interrupt Enable register 0 = Disable 1 = Enable 1'b0 alivegpioINTENB5 [5] R Alive GPIO5 Interrupt Enable register 0 = Disable 1 = Enable 1'b0 alivegpioINTENB4 [4] R Alive GPIO4 Interrupt Enable register 0 = Disable 1 = Enable 1'b0 alivegpioINTENB3 [3] R Alive GPIO3 Interrupt Enable register 0 = Disable 1 = Enable 1'b0 alivegpioINTENB2 [2] R Alive GPIO2 Interrupt Enable register 0 = Disable 1 = Enable 1'b0 alivegpioINTENB1 [1] R Alive GPIO1 Interrupt Enable register 0 = Disable 1 = Enable 1'b0 alivegpioINTENB0 [0] R Alive GPIO0 Interrupt Enable register 0 = Disable 1 = Enable 1'b0 NOTE: ALIVEGPIOINTENB (n) Register operates as follows It remains as the former state in case of {ALIVEGPIOENBRST(n), ALIVEGPIOENBSET(n)} = 2'b00 It is set as "1" in case of {ALIVEGPIOENBRST(n), ALIVEGPIOENBSET (n)} = 2'b01 It is set as "0" in case of {ALIVEGPIOENBRST(n), ALIVEGPIOENBSET (n)} = 2'b10 It is set as "1" in case of {ALIVEGPIOENBRST(n), ALIVEGPIOENBSET (n)} = 2'b11 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-35 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.26 ALIVEGPIODETECTPENDREG

 Base Address: C001_0000h  Address = Base Address + 0864h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 alivegpioDETECTPEND7 [7] R Alive GPIO7 Detect Pending Read 0 = None 1 = Interrupt Pending Write 0 = None 1 = Clear 1'b0 alivegpioDETECTPEND6 [6] R Alive GPIO6 Detect Pending Read 0 = None 1 = Interrupt Pending Write 0 = None 1 = Clear 1'b0 alivegpioDETECTPEND5 [5] R Alive GPIO5 Detect Pending Read 0 = None 1 = Interrupt Pending Write 0 = None 1 = Clear 1'b0 alivegpioDETECTPEND4 [4] R Alive GPIO4 Detect Pending Read 0 = None 1 = Interrupt Pending Write 0 = None 1 = Clear 1'b0 alivegpioDETECTPEND3 [3] R Alive GPIO3 Detect Pending Read 0 = None 1 = Interrupt Pending Write 0 = None 1 = Clear 1'b0 alivegpioDETECTPEND2 [2] R Alive GPIO2 Detect Pending Read 0 = None 1 = Interrupt Pending 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-36 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Write 0 = None 1 = Clear alivegpioDETECTPEND1 [1] R Alive GPIO1 Detect Pending Read 0 = None 1 = Interrupt Pending Write 0 = None 1 = Clear 1'b0 alivegpioDETECTPEND0 [0] R Alive GPIO0 Detect Pending Read 0 = None 1 = Interrupt Pending Write 0 = None 1 = Clear 1'b0

12.8.1.27 ALIVESCRATCHRSTREG

 Base Address: C001_0000h  Address = Base Address + 0868h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHRST [31:0] RW Reset Alive Scratch Register Each bit of ALIVESCRATCHRST drives Scratch Register's reset pin. 32'b0

12.8.1.28 ALIVESCRATCHSETREG

 Base Address: C001_0000h  Address = Base Address + 086Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHSET [31:0] RW Set Alive Scratch Register Each bit of ALIVESCRATCHSET drives Scratch Register's set pin 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-37 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.29 ALIVESCRATCHREADREG

 Base Address: C001_0000h  Address = Base Address + 0870h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHREAD [31:0] R Read Alive Scratch Register 32'b0

12.8.1.30 ALIVEGPIOPADOUTENBRSTREG

 Base Address: C001_0000h  Address = Base Address + 0874h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 ALIVEGPIOPADOUTEN BRST7 [7] RW Alive GPIO7 PAD Out Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTEN BRST6 [6] RW Alive GPIO6 PAD Out Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTEN BRST5 [5] RW Alive GPIO5 PAD Out Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTEN BRST4 [4] RW Alive GPIO4 PAD Out Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTEN BRST3 [3] RW Alive GPIO3 PAD Out Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTEN BRST2 [2] RW Alive GPIO2 PAD Out Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTEN BRST1 [1] RW Alive GPIO1 PAD Out Enable Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTEN BRST0 [0] RW Alive GPIO0 PAD Out Enable Register Reset. 0 = None 1 = Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-38 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.31 ALIVEGPIOPADOUTENBSETREG

 Base Address: C001_0000h  Address = Base Address + 0878h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 ALIVEGPIOPADOUTEN BSET7 [7] RW Alive GPIO7 PAD Out Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTEN BSET6 [6] RW Alive GPIO6 PAD Out Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTEN BSET5 [5] RW Alive GPIO5 PAD Out Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTEN BSET4 [4] RW Alive GPIO4 PAD Out Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTEN BSET3 [3] RW Alive GPIO3 PAD Out Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTEN BSET2 [2] RW Alive GPIO2 PAD Out Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTEN BSET1 [1] RW Alive GPIO1 PAD Out Enable Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTEN BSET0 [0] RW Alive GPIO0 PAD Out Enable Register Set. 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-39 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.32 ALIVEGPIOPADOUTENBREADREG

 Base Address: C001_0000h  Address = Base Address + 087Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 alivegpioPADOUTENB7 [7] R Alive GPIO7 PAD Out Enable register 0 = Disable 1 = Enable 1'b0 alivegpioPADOUTENB6 [6] R Alive GPIO6 PAD Out Enable register 0 = Disable 1 = Enable 1'b0 alivegpioPADOUTENB5 [5] R Alive GPIO5 PAD Out Enable register 0 = Disable 1 = Enable 1'b0 alivegpioPADOUTENB4 [4] R Alive GPIO4 PAD Out Enable register 0 = Disable 1 = Enable 1'b0 alivegpioPADOUTENB3 [3] R Alive GPIO3 PAD Out Enable register 0 = Disable 1 = Enable 1'b0 alivegpioPADOUTENB2 [2] R Alive GPIO2 PAD Out Enable register 0 = Disable 1 = Enable 1'b0 alivegpioPADOUTENB1 [1] R Alive GPIO1 PAD Out Enable register 0 = Disable 1 = Enable 1'b0 alivegpioPADOUTENB0 [0] R Alive GPIO0 PAD Out Enable register 0 = Disable 1 = Enable 1'b0 NOTE: ALIVEGPIOPADOUTENB(n) Register operates as follows It remains as the former state in case of {ALIVEGPIOPADOUTENBRST(n), ALIVEGPIOPADOUTENBSET(n)} = 2'b00 It is set as "1" in case of {ALIVEGPIOPADOUTENBRST(n), ALIVEGPIOPADOUTENBSET(n)} = 2'b01 It is set as "0" in case of {ALIVEGPIOPADOUTENBRST(n), ALIVEGPIOPADOUTENBSET(n)} = 2'b10 It is set as "1" in case of {ALIVEGPIOPADOUTENBRST(n), ALIVEGPIOPADOUTENBSET(n)} = 2'b11 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-40 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.33 ALIVEGPIOPADPULLUPRSTREG

 Base Address: C001_0000h  Address = Base Address + 0880h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 ALIVEGPIOPADPULLUP RST7 [7] RW Alive GPIO7 PAD Pullup Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADPULLUP RST6 [6] RW Alive GPIO6 PAD Pullup Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADPULLUP RST5 [5] RW Alive GPIO5 PAD Pullup Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADPULLUP RST4 [4] RW Alive GPIO4 PAD Pullup Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADPULLUP RST3 [3] RW Alive GPIO3 PAD Pullup Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADPULLUP RST2 [2] RW Alive GPIO2 PAD Pullup Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADPULLUP RST1 [1] RW Alive GPIO1 PAD Pullup Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADPULLUP RST0 [0] RW Alive GPIO0 PAD Pullup Register Reset. 0 = None 1 = Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-41 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.34 ALIVEGPIOPADPULLUPSETREG

 Base Address: C001_0000h  Address = Base Address + 0884h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 ALIVEGPIOPADPULLUP SET7 [7] RW Alive GPIO7 PAD Pullup Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADPULLUP SET6 [6] RW Alive GPIO6 PAD Pullup Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADPULLUP SET5 [5] RW Alive GPIO5 PAD Pullup Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADPULLUP SET4 [4] RW Alive GPIO4 PAD Pullup Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADPULLUP SET3 [3] RW Alive GPIO3 PAD Pullup Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADPULLUP SET2 [2] RW Alive GPIO2 PAD Pullup Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADPULLUP SET1 [1] RW Alive GPIO1 PAD Pullup Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADPULLUP SET0 [0] RW Alive GPIO0 PAD Pullup Register Set. 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-42 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.35 ALIVEGPIOPADPULLUPREADREG

 Base Address: C001_0000h  Address = Base Address + 0888h, Reset Value = 0x0000_00FF Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 alivegpioPADPULLUP7 [7] R Alive GPIO7 PAD Pullup register 0 = Pull-down 1 = Pull-up 1'b1 alivegpioPADPULLUP6 [6] R Alive GPIO6 PAD Pullup register 0 = Pull-down 1 = Pull-up 1'b1 alivegpioPADPULLUP5 [5] R Alive GPIO5 PAD Pullup register 0 = Pull-down 1 = Pull-up 1'b1 alivegpioPADPULLUP4 [4] R Alive GPIO4 PAD Pullup register 0 = Pull-down 1 = Pull-up 1'b1 alivegpioPADPULLUP3 [3] R Alive GPIO3 PAD Pullup register 0 = Pull-down 1 = Pull-up 1'b1 alivegpioPADPULLUP2 [2] R Alive GPIO2 PAD Pullup register 0 = Pull-down 1 = Pull-up 1'b1 alivegpioPADPULLUP1 [1] R Alive GPIO1 PAD Pullup register 0 = Pull-down 1 = Pull-up 1'b1 alivegpioPADPULLUP0 [0] R Alive GPIO0 PAD Pullup register 0 = Pull-down 1 = Pull-up 1'b1 NOTE: ALIVEGPIOPADPULLUP (n) Register operates as follows It remains as the former state in case of {ALIVEGPIOPADPULLUPRST(n), ALIVEGPIOPADPULLUPSET(n)} = 2'b00 It is set as "1" in case of {ALIVEGPIOPADOPULLUPRST(n), ALIVEGPIOPADPULLUPSET(n)} = 2'b01 It is set as "0" in case of {ALIVEGPIOPADOPULLUPRST(n), ALIVEGPIOPADPULLUPSET(n)} = 2'b10 It is set as "1" in case of {ALIVEGPIOPADOPULLUPRST(n), ALIVEGPIOPADPULLUPSET(n)} = 2'b11 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-43 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.36 ALIVEGPIOPADOUTRSTREG

 Base Address: C001_0000h  Address = Base Address + 088Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 ALIVEGPIOPADOUTRS T7 [7] RW Alive GPIO7 PAD Out Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTRS T6 [6] RW Alive GPIO6 PAD Out Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTRS T5 [5] RW Alive GPIO5 PAD Out Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTRS T4 [4] RW Alive GPIO4 PAD Out Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTRS T3 [3] RW Alive GPIO3 PAD Out Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTRS T2 [2] RW Alive GPIO2 PAD Out Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTRS T1 [1] RW Alive GPIO1 PAD Out Register Reset. 0 = None 1 = Reset 1'b0 ALIVEGPIOPADOUTRS T0 [0] RW Alive GPIO0 PAD Out Register Reset. 0 = None 1 = Reset 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-44 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.37 ALIVEGPIOPADOUTSETREG

 Base Address: C001_0000h  Address = Base Address + 0890h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 ALIVEGPIOPADOUTSE T7 [7] RW Alive GPIO7 PAD Out Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTSE T6 [6] RW Alive GPIO6 PAD Out Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTSE T5 [5] RW Alive GPIO5 PAD Out Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTSE T4 [4] RW Alive GPIO4 PAD Out Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTSE T3 [3] RW Alive GPIO3 PAD Out Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTSE T2 [2] RW Alive GPIO2 PAD Out Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTSE T1 [1] RW Alive GPIO1 PAD Out Register Set. 0 = None 1 = Set 1'b0 ALIVEGPIOPADOUTSE T0 [0] RW Alive GPIO0 PAD Out Register Set. 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-45 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.38 ALIVEGPIOPADOUTREADREG

 Base Address: C001_0000h  Address = Base Address + 0894h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved 0 alivegpioPADOUT7 [7] R Alive GPIO7 PAD Out register 1'b0 alivegpioPADOUT6 [6] R Alive GPIO6 PAD Out register 1'b0 alivegpioPADOUT5 [5] R Alive GPIO5 PAD Out register 1'b0 alivegpioPADOUT4 [4] R Alive GPIO4 PAD Out register 1'b0 alivegpioPADOUT3 [3] R Alive GPIO3 PAD Out register 1'b0 alivegpioPADOUT2 [2] R Alive GPIO2 PAD Out register 1'b0 alivegpioPADOUT1 [1] R Alive GPIO1 PAD Out register 1'b0 alivegpioPADOUT0 [0] R Alive GPIO0 PAD Out register 1'b0 NOTE: ALIVEGPIOPADOUT(n) Register operates as follows It remains as the former state in case of {ALIVEGPIOPADOUTRST(n), ALIVEGPIOPADOUTSET(n)} = 2'b00 It is set as "1" in case of {ALIVEGPIOPADOUTRST(n), ALIVEGPIOPADOUTSET(n)} = 2'b01 It is set as "0" in case of {ALIVEGPIOPADOUTRST(n), ALIVEGPIOPADOUTSET(n)} = 2'b10 It is set as "1" in case of {ALIVEGPIOPADOUTRST(n), ALIVEGPIOPADOUTSET(n)} = 2'b11 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-46 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.39 VDDCTRLRSTREG

 Base Address: C001_0000h  Address = Base Address + 0898h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:10] – Reserved 0 padholdENBrst3 [9] RW nPADHOLDENB3 Reset This register is not used in current version. Write to this register does not affect anything. 0 = None 1 = Set 1'b0 padholdENBrst2 [8] RW nPADHOLDENB2 Reset 0 = None 1 = Set 1'b0 padholdENBrst1 [7] RW nPADHOLDENB1 Reset 0 = None 1 = Set 1'b0 padholdENBrst0 [6] RW nPADHOLDENB0 Reset 0 = None 1 = Set 1'b0 padholdrst3 [5] RW nPADHOLD3 Reset This register is not used in current version. Write to this register does not affect anything. 0 = None 1 = Set 1'b0 padholdrst2 [4] RW nPADHOLD2 Reset 0 = None 1 = Set 1'b0 padholdrst1 [3] RW nPADHOLD1 Reset 0 = None 1 = Set 1'b0 padholdRST0 [2] RW nPADHOLD0 Reset 0 = None 1 = Set 1'b0 vddPWRONRST_DDR [1] RW DRAM VDD Power ON Reset 0 = None 1 = Set 1'b0 vddPWRONRST [0] RW Core VDD Power ON Reset 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-47 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.40 VDDCTRLSETREG

 Base Address: C001_0000h  Address = Base Address + 089Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:9] – Reserved 0 padholdENBset3 [9] RW nPADHOLDENB3 Set This register is not used in current version. Write to this register does not affect anything. 0 = None 1 = Set 1'b0 padholdENBset2 [8] RW nPADHOLDENB2 Set 0 = None 1 = Set 1'b0 padholdENBset1 [7] RW nPADHOLDENB1 Set 0 = None 1 = Set 1'b0 padholdENBset0 [6] RW nPADHOLDENB0 Set 0 = None 1 = Set 1'b0 padholdset3 [5] RW nPADHOLD3 Set This register is not used in current version. Write to this register does not affect anything. 0 = None 1 = Set 1'b0 padholdset2 [4] RW nPADHOLD2 Set 0 = None 1 = Set 1'b0 padholdset1 [3] RW nPADHOLD1 Set 0 = None 1 = Set 1'b0 padholdset0 [2] RW nPADHOLD0 Set 0 = None 1 = Set 1'b0 vddPWRonset_DDr [1] RW DRAM VDD Power ON Set 0 = None 1 = Set 1'b0 vddpwronset [0] RW Core VDD Power ON Set 0 = None 1 = Set 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-48 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.41 VDDCTRLREADREG

 Base Address: C001_0000h  Address = Base Address + 08A0h, Reset Value = 0x0000_03FF Name Bit Type Description Reset Value RSVD [31:11] – Reserved 0 VDDPWRTOGGLE [10] R Read VDDPWRTOGGLE PAD status 0 = User does not pushed VDDPWRTOGGLE PAD 1 = User pushed VDDPWRTOGGLE PAD npadholdENB3 [9] R Read nPADHOLDENB3 Register 0 = Pad Retention Enable 1 = Pad Retention Disable 1'b1 npadholdENB2 [8] R Read nPADHOLDENB2 Register 0 = Pad Retention Enable 1 = Pad Retention Disable 1'b1 npadholdENB1 [7] R Read nPADHOLDENB1 Register 0 = Pad Retention Enable 1 = Pad Retention Disable 1'b1 npadholdENB0 [6] R Read nPADHOLDENB0 Register 0 = Pad Retention Enable 1 = Pad Retention Disable 1'b1 npadhold2 [5] R Read nPADHOLD3 Register 0 = Pad Retention Enable 1 = Pad Retention Disable 1'b1 npadhold2 [4] R Read nPADHOLD2 Register 0 = Pad Retention Enable 1 = Pad Retention Disable 1'b1 npadhold1 [3] R Read nPADHOLD1 Register 0 = Pad Retention Enable 1 = Pad Retention Disable 1'b1 npadhold0 [2] R Read nPADHOLD0 Register 0 = Pad Retention Enable 1 = Pad Retention Disable 1'b1 vddpwron_ddr [1] R Read DRAM Vdd Power On Register 0 = DRAM Power Off 1 = CORE DRAM On 1'b1 vddpwron [0] R Read CORE Vdd Power On Register 0 = CORE Power Off 1 = CORE Power On 1'b1 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-49 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. NOTE: 1. Each bit of VDDCTRLREADREG is set or reset by each bit of VDDCTRLSETREG/VDDCTRLRSTREG 2. The Pad Retention of nPadHod and nPadHoldEnb operate as follows. Pad Retention Disable if nPadHod == "1", nPadHoldEnb == "1" when Core Power turns off Pad Retention Disable if nPadHod == "0", nPadHoldEnb == "1" when Core Power turns off Pad Retention Enable if nPadHod == "1", nPadHoldEnb == "0" when Core Power turns off Pad Retention Enable if nPadHod == "0", nPadHoldEnb == "0" when Core Power turns off Pad Retention Disable if nPadHod == "1", nPadHoldEnb == "1" when Core Power turns on Pad Retention Disable if nPadHod == "0", nPadHoldEnb == "1" when Core Power turns on Pad Retention Disable if nPadHod == "1", nPadHoldEnb == "0" when Core Power turns on Pad Retention Enable if nPadHod == "0", nPadHoldEnb == "0" when Core Power turns on

12.8.1.42 ALIVECLEARWAKEUPSTATUSREGISTER

 Base Address: C001_0000h  Address = Base Address + 08A4h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:1] R reserved 31'h0 CLRWAKEUP [0] W Clear is wakeup status register 0 = None 1 = Clear 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-50 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.43 ALIVESLEEPWAKEUPSTATUSREGISTER

 Base Address: C001_0000h  Address = Base Address + 08A8h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:10] R reserved 22'b0 alivegpio7 [9] R 0 = none 1 = wkeup is ALIVEGPIO[7] 1'b0 alivegpio6 [8] R 0 = none 1 = wkeup is ALIVEGPIO[6] 1'b0 alivegpio5 [7] R 0 = none 1 = wkeup is ALIVEGPIO[5] 1'b0 alivegpio4 [6] R 0 = none 1 = wkeup is ALIVEGPIO[4] 1'b0 alivegpio3 [5] R 0 = none 1 = wkeup is ALIVEGPIO[3] 1'b0 alivegpio2 [4] R 0 = none 1 = wkeup is ALIVEGPIO[2] 1'b0 alivegpio1 [3] R 0 = none 1 = wkeup is ALIVEGPIO[1] 1'b0 alivegpio0 [2] R 0 = none 1 = wkeup is ALIVEGPIO[0] 1'b0 rtcinterrupt [1] R 0 = none 1 = wkeup is rtc interrupt 1'b0 nVDDpwrtoggle [0] R 0 = none 1 = wkeup is vddpwrtoggle 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-51 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.44 ALIVESCRATCHRSTREG1

 Base Address: C001_0000h  Address = Base Address + 08ACh, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHRST1 [31:0] RW Reset Alive Scratch Register Each bit of ALIVESCRATCHRST1 drives Scratch Register's reset pin. 32'b0

12.8.1.45 ALIVESCRATCHRSTREG2

 Base Address: C001_0000h  Address = Base Address + 08B8h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHRST2 [31:0] RW Reset Alive Scratch Register Each bit of ALIVESCRATCHRST2 drives Scratch Register's reset pin. 32'b0

12.8.1.46 ALIVESCRATCHRSTREG3

 Base Address: C001_0000h  Address = Base Address + 08C4h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHRST3 [31:0] RW Reset Alive Scratch Register Each bit of ALIVESCRATCHRST3 drives Scratch Register's reset pin. 32'b0

12.8.1.47 ALIVESCRATCHRSTREG4

 Base Address: C001_0000h  Address = Base Address + 08D0h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHRST4 [31:0] RW Reset Alive Scratch Register Each bit of ALIVESCRATCHRST4 drives Scratch Register's reset pin. 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-52 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.48 ALIVESCRATCHRSTREG5

 Base Address: C001_0000h  Address = Base Address + 08DCh, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHRST5 [31:0] RW Reset Alive Scratch Register Each bit of ALIVESCRATCHRST5 drives Scratch Register's reset pin. 32'b0

12.8.1.49 ALIVESCRATCHRSTREG6

 Base Address: C001_0000h  Address = Base Address + 08E8h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHRST6 [31:0] RW Reset Alive Scratch Register Each bit of ALIVESCRATCHRST6 drives Scratch Register's reset pin. 32'b0

12.8.1.50 ALIVESCRATCHRSTREG7

 Base Address: C001_0000h  Address = Base Address + 08F4h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHRST7 [31:0] RW Reset Alive Scratch Register Each bit of ALIVESCRATCHRST7 drives Scratch Register's reset pin. 32'b0

12.8.1.51 ALIVESCRATCHRSTREG8

 Base Address: C001_0000h  Address = Base Address + 0900h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHRST8 [31:0] RW Reset Alive Scratch Register Each bit of ALIVESCRATCHRST3 drives Scratch Register's reset pin. 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-53 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.52 ALIVESCRATCHSETREG1

 Base Address: C001_0000h  Address = Base Address + 08B0h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHSET1 [31:0] RW Set Alive Scratch Register Each bit of ALIVESCRATCHSET1 drives Scratch Register's set pin. 32'b0

12.8.1.53 ALIVESCRATCHSETREG2

 Base Address: C001_0000h  Address = Base Address + 08BCh, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHSET2 [31:0] RW Set Alive Scratch Register Each bit of ALIVESCRATCHSET2 drives Scratch Register's set pin. 32'b0

12.8.1.54 ALIVESCRATCHSETREG3

 Base Address: C001_0000h  Address = Base Address + 08C8h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHSET3 [31:0] RW Set Alive Scratch Register Each bit of ALIVESCRATCHSET3 drives Scratch Register's set pin. 32'b0

12.8.1.55 ALIVESCRATCHSETREG4

 Base Address: C001_0000h  Address = Base Address + 08D4h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHSET4 [31:0] RW Set Alive Scratch Register Each bit of ALIVESCRATCHSET4 drives Scratch Register's set pin. 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-54 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.56 ALIVESCRATCHSETREG5

 Base Address: C001_0000h  Address = Base Address + 08E0h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHSET5 [31:0] RW Set Alive Scratch Register Each bit of ALIVESCRATCHSET5 drives Scratch Register's set pin. 32'b0

12.8.1.57 ALIVESCRATCHSETREG6

 Base Address: C001_0000h  Address = Base Address + 08ECh, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHSET6 [31:0] RW Set Alive Scratch Register Each bit of ALIVESCRATCHSET6 drives Scratch Register's set pin. 32'b0

12.8.1.58 ALIVESCRATCHSETREG7

 Base Address: C001_0000h  Address = Base Address + 08F8h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHSET7 [31:0] RW Set Alive Scratch Register Each bit of ALIVESCRATCHSET7 drives Scratch Register's set pin. 32'b0

12.8.1.59 ALIVESCRATCHSETREG8

 Base Address: C001_0000h  Address = Base Address + 0904h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHSET8 [31:0] RW Set Alive Scratch Register Each bit of ALIVESCRATCHSET8 drives Scratch Register's set pin. 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-55 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.60 ALIVESCRATCHREADREG1

 Base Address: C001_0000h  Address = Base Address + 08B4h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHREAD1 [31:0] R Read Alive Scratch Register 32'b0

12.8.1.61 ALIVESCRATCHREADREG2

 Base Address: C001_0000h  Address = Base Address + 08C0h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHREAD2 [31:0] R Read Alive Scratch Register 32'b0

12.8.1.62 ALIVESCRATCHREADREG3

 Base Address: C001_0000h  Address = Base Address + 08CCh, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHREAD3 [31:0] R Read Alive Scratch Register 32'b0

12.8.1.63 ALIVESCRATCHREADREG4

 Base Address: C001_0000h  Address = Base Address + 08D8h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHREAD4 [31:0] R Read Alive Scratch Register 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-56 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.64 ALIVESCRATCHREADREG5

 Base Address: C001_0000h  Address = Base Address + 08E4h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHREAD5 [31:0] R Read Alive Scratch Register 32'b0

12.8.1.65 ALIVESCRATCHREADREG6

 Base Address: C001_0000h  Address = Base Address + 08F0h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHREAD6 [31:0] R Read Alive Scratch Register 32'b0

12.8.1.66 ALIVESCRATCHREADREG7

 Base Address: C001_0000h  Address = Base Address + 08FCh, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHREAD7 [31:0] R Read Alive Scratch Register 32'b0

12.8.1.67 ALIVESCRATCHREADREG8

 Base Address: C001_0000h  Address = Base Address + 0908h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVESCRATCHREAD8 [31:0] R Read Alive Scratch Register 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-57 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.68 VDDOFFDELAYRSTREGISTER

 Base Address: C001_0000h  Address = Base Address + 090Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value VDDOFFDELAYRST [31:0] RW ResetVDD Off delay value register Each bit of vddoffdelayrst drives Vdd off delay value Register's reset pin. 32'b0

12.8.1.69 VDDOFFDELAYSETREGISTER

 Base Address: C001_0000h  Address = Base Address + 0910h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value VDDOFFDELAYSET [31:0] RW SetVDD Off delay value register Each bit of vddoffdelayset drives Vdd off delay value Register's set pin. 32'b0

12.8.1.70 VDDOFFDELAYVALUEREGISTER

 Base Address: C001_0000h  Address = Base Address + 0914h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value VDDOFFDELAYVALUE [31:0] R VDD OFF DELAY VALUE (unit: RTC clock) 32'b0

12.8.1.71 VDDOFFDELAYTIMEREGISTER

 Base Address: C001_0000h  Address = Base Address + 0918h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value VDDOFFDELAYTIME [31:0] R VDD OFF DELAY TIME (unit: RTC clock) clear is vddoffdelayrst/set register write 32'b0

12.8.1.72 ALIVEGPIOINPUTVALUE

 Base Address: C001_0000h  Address = Base Address + 091Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ALIVEGPIOINPUTVALU E [31:0] R Nth bit of this register show the value of AliveGPIO[N]. 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-58 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.73 PMUNISOLATE

 Base Address: C001_0000h  Address = Base Address + 0D00h, Reset Value = 0x0000_0003 Name Bit Type Description Reset Value RSVD [31:2] – Reserved 0 NISOLATE_MFC [1] RW Power isolation (low active Power Isolation) for MFC block The default value is 1 (all blocks are connected normally) Sub-block must be isolatioted in order to power off the sub-block 0 = Isolate (ready-to-power-off) 1 = normal mode 0x1 NISOLATE_GPU [0] RW Power isolation (low active Power Isolation) for GPU block The default value is 1 (all blocks are connected normally) Sub-block must be isolatioted in order to power off the sub-blocks 0 = Isolate (ready-to-power-off) 1 = normal mode 0x1

12.8.1.74 PMUNPWRUPPRE

 Base Address: C001_0000h  Address = Base Address + 0D04h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:2] – Reserved 0 nPWRUPPRE_MFC [1] RW Power up precharge for MFC block Sub-block must be precharged before powering up all power switches. 0 = Power up precharge 1 = Power down precharge 0x0 nPWRUPPRE_GPU [0] RW Power up precharge for GPU block Sub-block must be precharged before powering up all power switches. 0 = Power up precharge 1 = Power down precharge 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 12 Alive 12-59 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

12.8.1.75 PMUNPWRUP

 Base Address: C001_0000h  Address = Base Address + 0D08h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:2] – Reserved 0 nPWRUP_MFC [1] RW Power up for MFC block Sub-blocks must be powered up all switches before normal operation. 0 = Power up 1 = Power down 0x0 nPWRUP_GPU [0] RW Power up for GPU block Sub-blocks must be powered up all switches before normal operation. 0 = Power up 1 = Power down 0x0

12.8.1.76 PMUNPWRUPACK

 Base Address: C001_0000h  Address = Base Address + 0D0Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:2] – Reserved 0 nPWRUPACK_MFC [1] R Power up acknowledge for MFC block This register must be checked after NPWRUP_MFC register is set to power up. 0 = Power On (Powering Up Sequence is finished) 1 = Power Off nPWRUPACK_GPU [0] R Power up acknowledge for GPU block This register must be checked after NPWRUP_GPU register is set to power up. 0 = Power On (Powering Up Sequence is finished) 1 = Power Off cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13 ID Register

13.1 Overview

ECID module of the S5P4418 stores the 128-bit DIEID information on a e-fuse ROM. Each Chip will have its own DIEID to identify it.

13.2 Features

 Support 128-bit Die ID  Support 128-bit Secure Boot ID  Support 128-bit Secure JTAG ID  Support 128-bit Backdoor JTAG ID  Programmable Secure Boot ID, Secure JTAG ID, Backdoor JTAG ID cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13.3 Functional Description

13.3.1 AC Timing

Table 13-1 AC Timing Table [Unit: ns] Symbol Description Symbol Description Program Mode tPCS CS to PROG setup time (setup rising, rist constraint) tPCH CS to PROG hold time (hold falling, fall constraint) tFSRCS FSOURCE to PROG setup time (setup rising, rise constraint) tFSRCH FSOURCE to PROG hold time (hold falling, fall constraint) tPRW PROG pulse width high (rising edge) tSCW SCK pulse width high (rising edge) tPSS SCK to PROG setup time (setup rising, fall constraint) tPSH SCK to PROG hold time (hold falling, rise constraint) tSIS SDI to SCK setup time (setup falling, rise/fall constraint) tSIH SDI to SCK hold time (hold falling, rise/fall constraint) tSAS SDI to A0 setup time (setup rising, rise constraint) tSAH SDI to A0 hold time (hold falling, fall constraint) tAAS A2, A1 to A0 setup time (setup rising, rising constraint) tAAH A2, A1 to A0 hold time (hold falling, fall constraint) tAWH A0 pulse width high tAWL A0 pulse width low tPAS A0 to PROG setup time (setup rising, fall constraint) tPAH A0 to PROG hold time (hold falling, rise constraint) Sense Mode tSCS CS to FSET setup time (setup rising, rise constraint) tSCH CS to FSET hold time (hold falling, fall constraint) tAS ADDR[] to FSET setup time (setup rising, rise/fall constraint) tAH ADDR[] to PRCHG hold time (hold falling, rise/fall constraint) tPRS PRCHG to FSET setup time (setup rising, rise constraint) tPRH PRCHG to SIGDEV hold time (hold rising, rise constraint) PRCHG to SIGDEV hold time (hold falling, fall constraint) tSDS SIGDEV to FSET setup time (setup rising, rise constraint) tSDH SIGDEV to FSET hold time (hold rising, fall constraint) tACC DOUT[] access time after SIGDEV fall (falling edge) tFSH FSET to PRCHG hold time (hold falling, fall constraint) Scan Mode tDCS CS to SCK setup time (setup rising, rise constraint) tDCH CS to SCK hold time (hold falling, fall constraint) tPACC DOUT[] access time after SCK fall (falling edge) tSACC SDOUT access time after SCK rise (rising edge) cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  Blue : It will use each program mode and scan mode  Red : It will use each program mode and sense mode  tFSRCS, tFSRCH = 1000ns, All other timing arcs = 2ns  tPRW = 10000ns ± 100ns (Not allowed out of tPRW range. Must need approval from PTE/DT team if any change)

13.3.2 Sense Mode Timing

Figure 13-1 Sense Mode Timing  When SIGDEV is enabled ("H"), sensing current is occurred. So you should reduce SIGDEV pulse width high period for power saving.  CS should be set high (enable) and A2, A1, A0 states should be set properly before first SIGDEV rising in sense mode.  After sense operation, DOUT[] have "0" for un-blown fuse cell and "1" for blown fuse cell.  Sense (read) operation would be performed correctly with timing diagram above. The user who w ant to have different timing sequence must have a prior consultation with effuse designer. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13.3.3 Scan-latch Mode Timing

Figure 13-2 Scan-Latch Mode Timing  After sense mode, cell's data is shifted to SDOUT by SCK in Scan-latch mode  Scan-latch operation would be performed correctly with timing diagram above. The user who want to have different timing sequence must have a prior consultation with effuse designer.

13.3.4 Stand-by Mode Timing

 CS pin should be set to ground (=0.0v) to reduce unnecessary leakage current.  Other control pins: don't care. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13.3.5 Program Mode Timing

Figure 13-3 Fuse Programming Operation Using Single Macro Figure 13-4 Fuse Programming Operation Using Single Macro  Apply tFSRCS > 1 s because of prevention leakage current from FSORUCE to ESD protection diode.  Fuse program operation would be performed correctly with timing diagram above. The user who want to have different timing sequence must have a prior consultation with effuse designer. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13.4 Register Description

13.4.1 Register Map Summary

 Base Address: C006_7000h Register Offset Description Reset Value ECID0 0x00h 128-bit ECID Register 0 – ECID1 0x04h 128-bit ECID Register 1 – ECID2 0x08h 128-bit ECID Register 2 – ECID3 0x0Ch 128-bit ECID Register 3 – CHIP_NAME_03_00 0x10h Chip Name Register 03_00 – CHIP_NAME_07_04 0x14h Chip Name Register 07_04 – CHIP_NAME_11_08 0x18h Chip Name Register 11_08 – CHIP_NAME_15_12 0x1Ch Chip Name Register 15_12 – CHIP_NAME_19_16 0x20h Chip Name Register 19_16 – CHIP_NAME_23_20 0x24h Chip Name Register 23_20 – CHIP_NAME_27_24 0x28h Chip Name Register 27_24 – CHIP_NAME_31_28 0x2Ch Chip Name Register 31_28 – CHIP_NAME_35_32 0x30h Chip Name Register 35_32 – CHIP_NAME_39_36 0x34h Chip Name Register 39_36 – CHIP_NAME_43_40 0x38h Chip Name Register 43_40 – CHIP_NAME_47_44 0x3Ch Chip Name Register 47_44 – RSVD 0x40h Reserved – GUID0 0x44h GUID0 – GUID1_2 0x48h GUID1_2 – GUID3_0 0x4Ch GUID3_0 – GUID3_1 0x50h GUID3_1 – EC0 0x54h ECID Control Register 0 0x0000_0000 EC1 0x58h ECID Control Register 1 0x0000_0000 EC2 0x5Ch ECID Control Register 2 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13.4.1.1 ECID0

 Base Address: C006_7000h  Address = Base Address + 0x00h, Reset Value = Undefined Name Bit Type Description Reset Value ECID0 [31:0] R 128-bit ECID Register [31:0] –

13.4.1.2 ECID1

 Base Address: C006_7000h  Address = Base Address + 0x04h, Reset Value = Undefined Name Bit Type Description Reset Value ECID1 [31:0] R 128-bit ECID Register [63:32] –

13.4.1.3 ECID2

 Base Address: C006_7000h  Address = Base Address + 0x08h, Reset Value = Undefined Name Bit Type Description Reset Value ECID2 [31:0] R 128-bit ECID Register [95:64] –

13.4.1.4 ECID3

 Base Address: C006_7000h  Address = Base Address + 0x0Ch, Reset Value = Undefined Name Bit Type Description Reset Value ECID3 [31:0] R 128-bit ECID Register [127:96] – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13.4.1.5 CHIP_NAME_03_00

 Base Address: C006_7000h  Address = Base Address + 0x10h, Reset Value = Undefined Name Bit Type Description Reset Value chip_name_3 [31:24] R Chip name character 3 – chip_name_2 [23:16] R Chip name character 2 – chip_name_1 [15:8] R Chip name character 1 – chip_name_0 [7:0] R Chip name character 0 –

13.4.1.6 CHIP_NAME_07_04

 Base Address: C006_7000h  Address = Base Address + 0x14h, Reset Value = Undefined Name Bit Type Description Reset Value chip_name_7 [31:24] R Chip name character 7 – chip_name_6 [23:16] R Chip name character 6 – chip_name_5 [15:8] R Chip name character 5 – chip_name_4 [7:0] R Chip name character 4 –

13.4.1.7 CHIP_NAME_11_08

 Base Address: C006_7000h  Address = Base Address + 0x18h, Reset Value = Undefined Name Bit Type Description Reset Value chip_name_11 [31:24] R Chip name character 11 – chip_name_10 [23:16] R Chip name character 10 – chip_name_9 [15:8] R Chip name character 9 – chip_name_8 [7:0] R Chip name character 8 – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13.4.1.8 CHIP_NAME_15_12

 Base Address: C006_7000h  Address = Base Address + 0x1Ch, Reset Value = Undefined Name Bit Type Description Reset Value chip_name_15 [31:24] R Chip name character 15 – chip_name_14 [23:16] R Chip name character 14 – chip_name_13 [15:8] R Chip name character 13 – chip_name_12 [7:0] R Chip name character 12 –

13.4.1.9 CHIP_NAME_19_16

 Base Address: C006_7000h  Address = Base Address + 0x20h, Reset Value = Undefined Name Bit Type Description Reset Value chip_name_19 [31:24] R Chip name character 19 – chip_name_18 [23:16] R Chip name character 18 – chip_name_17 [15:8] R Chip name character 17 – chip_name_16 [7:0] R Chip name character 16 –

13.4.1.10 CHIP_NAME_23_20

 Base Address: C006_7000h  Address = Base Address + 0x24h, Reset Value = Undefined Name Bit Type Description Reset Value chip_name_23 [31:24] R Chip name character 23 – chip_name_22 [23:16] R Chip name character 22 – chip_name_21 [15:8] R Chip name character 21 – chip_name_20 [7:0] R Chip name character 20 – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13.4.1.11 CHIP_NAME_27_24

 Base Address: C006_7000h  Address = Base Address + 0x28h, Reset Value = Undefined Name Bit Type Description Reset Value chip_name_27 [31:24] R Chip name character 27 – chip_name_26 [23:16] R Chip name character 26 – chip_name_25 [15:8] R Chip name character 25 – chip_name_24 [7:0] R Chip name character 24 –

13.4.1.12 CHIP_NAME_31_28

 Base Address: C006_7000h  Address = Base Address + 0x2Ch, Reset Value = Undefined Name Bit Type Description Reset Value chip_name_31 [31:24] R Chip name character 31 – chip_name_30 [23:16] R Chip name character 30 – chip_name_29 [15:8] R Chip name character 29 – chip_name_28 [7:0] R Chip name character 28 –

13.4.1.13 CHIP_NAME_35_32

 Base Address: C006_7000h  Address = Base Address + 0x30h, Reset Value = Undefined Name Bit Type Description Reset Value chip_name_35 [31:24] R Chip name character 35 – chip_name_34 [23:16] R Chip name character 34 – chip_name_33 [15:8] R Chip name character 33 – chip_name_32 [7:0] R Chip name character 32 – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13.4.1.14 CHIP_NAME_39_36

 Base Address: C006_7000h  Address = Base Address + 0x34h, Reset Value = Undefined Name Bit Type Description Reset Value chip_name_39 [31:24] R Chip name character 39 – chip_name_38 [23:16] R Chip name character 38 – chip_name_37 [15:8] R Chip name character 37 – chip_name_36 [7:0] R Chip name character 36 –

13.4.1.15 CHIP_NAME_43_40

 Base Address: C006_7000h  Address = Base Address + 0x38h, Reset Value = Undefined Name Bit Type Description Reset Value chip_name_43 [31:24] R Chip name character 43 – chip_name_42 [23:16] R Chip name character 42 – chip_name_41 [15:8] R Chip name character 41 – chip_name_40 [7:0] R Chip name character 40 –

13.4.1.16 CHIP_NAME_47_44

 Base Address: C006_7000h  Address = Base Address + 0x3Ch, Reset Value = Undefined Name Bit Type Description Reset Value chip_name_47 [31:24] R Chip name character 47 – chip_name_46 [23:16] R Chip name character 46 – chip_name_45 [15:8] R Chip name character 45 – chip_name_44 [7:0] R Chip name character 44 – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13.4.1.17 GUID0

 Base Address: C006_7000h  Address = Base Address + 0x44h, Reset Value = Undefined Name Bit Type Description Reset Value guid0 [31:0] R GUID 0 –

13.4.1.18 GUID1_2

 Base Address: C006_7000h  Address = Base Address +0x48h, Reset Value = Undefined Name Bit Type Description Reset Value guid2 [31:16] R GUID 2 – guid1 [15:0] R GUID 1 –

13.4.1.19 GUID3_0

 Base Address: C006_7000h  Address = Base Address + 0x4Ch, Reset Value = Undefined Name Bit Type Description Reset Value guid3_3 [31:24] R GUID 3_3 – guid3_2 [23:16] R GUID 3_2 – guid3_1 [15:8] R GUID 3_1 – guid3_0 [7:0] R GUID 3_0 –

13.4.1.20 GUID3_1

 Base Address: C006_7000h  Address = Base Address + 0x50h, Reset Value = Undefined Name Bit Type Description Reset Value guid3_7 [31:24] R GUID 3_7 – guid3_6 [23:16] R GUID 3_6 – guid3_5 [15:8] R GUID 3_5 – guid3_4 [7:0] R GUID 3_4 – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13.4.1.21 EC0

 Base Address: C006_7000h  Address = Base Address + 0x54h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:10] – Reserved – A_FF [9:7] RW Programmable A 3'b0 CS_FF [6] RW Programmable CS 1'b0 sigdev_ff [5] RW Programmable SIGDEV 1'b0 FSET_ff [4] RW Programmable FSET 1'b0 prchg_ff [3] RW Programmable PRCHG 1'b0 bonding_id [2:0] R Boinding ID –

13.4.1.22 EC1

 Base Address: C006_7000h  Address = Base Address + 0x58h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:3] – Reserved – prog_FF [2] RW Programmable PROG 1'b0 sck_FF [1] RW Programmable SCK 1'b0 sdi_ff [0] RW Programmable SDI 1'b0

13.4.1.23 EC2

 Base Address: C006_7000h  Address = Base Address + 0x5Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] – Reserved – hw_done [15] R ECID initialize done 1'b0 RSVD [14:5] – Reserved – hdcp_efuse_sel [4] RW HDCP Key select 0 = Secure Boot 1 = Secure JTAG 1'b0 RSVD [3:2] – Reserved – sel_bank [1:0] RW eFUSE select 0 = ECID 1 = Secure Boot 2 = Secure JTAG 3 = Backdoor JTAG 2'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 13 ID Register 13-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

13.5 Application Notes

 Permitting Over-the-cell routing. In chip-level layout, over-the-cell routing in EFROM_LP is permitted without any restrictions over Metal-4 layer.  Incomming power bus should be adjusted to guarantee NOT more than 5 % voltage drop at typical-case current levels.  Reduce resistance (<3 ) between PAD and FSOURCE pin of EFROM_LP.  Connect routing signal to all of the FSOURCE pins. When using two or more e-fuse sets, FSOURCE line can be shared among e-fuse sets, but program-mode operation should be applied sequentially. (For example, at first, operate e -fuse0 and then operate e-fuse1 for program-mode) It applies same during sense-mode, but there is a guideline for multi-sensing, only sense- mode.Keep the below rules. Refer to integration guide document for further information. Allowed maximum resistance can be obtained by 3 /# of 128-bit efuse box. If customer wants to run multi-sensing,  3 : 128-bit  1 ea, 1.5 : 128-bit  2 ea, 1 : 128-bit  3 ea, 0.5 : 128-bit  6 ea cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14 Memory Controller

14.1 Overview

The S5P4418 Memory Controller is based on a Unified Memory Architecture (UMA). This Controller consists of two control units: MCU-A, MCU-S. Each unit has dedicated control pins.

14.1.1 Unified Memory Architecture (UMA)

 Two Separate Memory Controller:  MCU-A: DDR3/LVDDR3(Low Voltage DDR3)/LPDDR3/LPDDR2  MCU-S: Static Memory  MCU-A features:  MCU-A is organized DREX and DDRPHY  Supports DDR3/LVDDR3(Low Voltage DDR3)/LPDDR3/LPDDR2 memory  Supports 8/16/32-bit SDRAM of 2GByte  Single Bank of Memory (32-bit data bus width)  Supports Power down mode  Supports Self Refresh mode  MCU-S features:  Static memory  Two Static Memory Chip Selects  NAND Flash Interface  23-bit address supports using latch address  SLC NAND, MLC NAND with ECC (Supports BCH-algorithm)  Static Memory Map Shadow cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.2 Block Diagram

Figure 14-1 Memory Controller Block Diagram cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3 Functional Description

The memory controller area of the S5P4418 is divided into an MCU-A and MCU-S bank. The MCU-A bank is connected to DDR3/LVDDR3 (Low Voltage DDR3)/LPDDR3/LPDDR2 which is the main memory of the S5P4418 and 32-bit data bus width. The MCU-S bank is the static bank and can be connected to Static Memory/Device, NAND (Refer to Figure 14-2)

14.3.1 MCU-A Bank Feature

 Compatible with JEDEC standard LPDDR2-S4/LPDDR3/LVDDR3(Low Voltage DDR3)/DDR3 SDRAMs  Supports 1:2 synchronous operation between bus clock and Memory clock  Supports up to two memory ranks (chip selects) and 4/8 banks per memory chips  Supports 512Mb, 1Gb, 2Gb, 4Gb, 8Gbit and 16Gbit density per a chip select  Supports outstanding exclusive accesses  Supports bank selective pre-charge policy  DREX Clock: MBCLK (400 MHz)  DDRPHY Clock: MCLK (800 MHz), MDCLK (800 MHz)  MBCLK: MCLK = 1: MBCLKx2  MDCLK: MDCLK 0° phase Master DLL clock (400 to 800 MHz). This clock should be the same frequency clock with clk2x in normal mode and generated from the same PLL which MCLK is using. But Master DLL is not able to lock under 400MHz. if MCLK is under 400 MHz, the double frequency of clk2x can be used for locking Master DLL for the low frequency operation cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.2 MCU-S Bank Feature

 Latched Addressing The number of pins that are connected to the outside is ADDR[18:0]. Since, however, the total address of the MCU-S Bank is 26-bit. ADDR[8:2] and ADDR[25:19] are allotted to the same pin, the system has a structure in which addresses are output two times. If the system uses ADDR[19] or more, the setting of higher address (ADDR[25:19]) is possible via System Configuration Pin (CfgSTLATADD). In this event, ADDR[25:19] which is configured by using external Latch IC first should be latched.  16-bit data bus width Static memory register except NAND flash (8 bits) has bus width select registers  Static memory Controller Normal static memory (SRAM and ROM) or static devices are connected. Up to two Static Chip Select signals exist.  NAND Flash Controller It supports both the small and large block NAND flash memories. Up to two NAND flash memories can be connected. Supports both SLC and MLC NAND flash memories. Up to 4/8/16/24/40/60-bit error correction/(1024 or 512 byte) using Binary-BCH coding cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.3 Memory Map

The memory map is roughly divided into one SDRAM Bank (MCU-A) and one static bank (MCU-S). The static bank consists of NAND Flash controller, Static Memory controller. The MCU-A bank consist of a Linear Array area and Display Array area. NAND Static #1 Static #0 0x0000_0000 0x0400_0000 0x0800_0000 MCU- A (2GB) DDR MCU-S STATIC Normal I/O Reserved 0x0000_0000 0x4000_0000 0xC000_0000 0xE000_0000 Reserved 0x2C00_0000 0x3000_0000 Internal ROM 0x3400_0000 Reserved Reserved 0xFFFF_0000 Internal SRAM cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.4 MCU-A Address Mapping

DREX modifies the address of the AXI transaction coming from the AXI slave port into a memory address - chip select, bank address, row address, column address and memory data width. To map chip select of memory device to a specific area of the address map, the chip_base and chip_mask bit - fields of the MemConfig0 register needs to be set (Refer to Register Descriptions). If chip1 of the mem ory device exists, the MemConfig1 register must also be set. Then, the AXI address requested by AXI Masters is divided into the AXI base address and AXI offset address. The AXI base address activates the appropriate memory chip select and the AXI offset address is mapped to a memory address according to the bank, row, column number, and data width set by the MemConfig0/1 and MemControl register. mapping

14.3.4.1 Linear Mapping

As shown in Figure 14-3 the linear mapping method maps the AXI address in the order of bank, row, column and width. Since the bank address does not change for at least one bank size, applications that use linear address mapping have a high possibility to access the same bank. Figure 14-3 Linear Address Mapping

14.3.4.2 Interleaved Mapping

As shown in Figure 14-4 the interleaved mapping method maps the AXI address in the order of row, bank, column and width. The difference between above two methods is that the bank and row order is different. For accesses beyond a row size, interleaved mapping accesses a different bank. Therefore, applications that use interleaved mapping access numerous banks. It causes better performance but more power consumption Command Arbiter. Command Arbiter re-arbitrates with the result of Fast Arbiter and Slow Arbiter. In this case, Fast Arbiter is always processed ahead with fixed method. Figure 14-4 Linear Address Mapping cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.5 Low Power Operation

The controller executes a low power memory operation in five ways as described below. Each feature is independent of each other and executed at the same time.

14.3.5.1 AXI Low Power Channel

The controller has an AXI low power channel interface to communicate with low power management units such as the system controller, which makes the memory device go into self refresh mode.

14.3.5.2 Dynamic Power Down

An SDRAM device has an active/pre-charge power down mode. This mode is triggered by de-asserting CKE to LOW. When any of the banks is open, it enters active power down mode. Otherwise, it enters pre -charge power down mode. When the request buffers remain empty for certain number of cycles (PwrdnConfig.dpwrdn_cyc register), DREX-1 changes the memory devices state to active/pre-charge power down automatically. The memory device enters Active/pre-charge power down mode or Forced pre-charge power down mode according to the SFR setting. The description of the two power down modes are as follows: 1. Active/pre-charge power down mode: Enter power down w/o considering whether there is a row open or not. 2. Forced pre-charge power down mode: Enter power down after closing all banks. When DREX-1 receives a new AXI transaction while memory device is in power down mode, it automatically wakes up the memory device from power down state and executes in a normal operation state.

14.3.5.3 Dynamic Self Refresh

Similarly to the dynamic power down feature, if the request buffers remain empty for certain number of cycles (PwrdnConfig.dsref_cyc register), DREX-1 changes the memory device's state to self-refresh mode. Since exiting power down mode requires many cycles, a longer idle cycle threshold is recommended for dynam ic self-refresh entry than the threshold for dynamic power down.

14.3.5.4 Clock Stop

To reduce the I/O power of the memory device and the controller, it is possible to stop the clock if the LPDDR / LPDDR2-S4 is in idle mode, or self refresh mode and DDR3 is in self refresh mode. If this feature is enabled, the controller automatically executes the clock stop feature. In DDR3, clock stop feature must be turn -on and off considering tCKSRX/tCKSRE/tCKESR timing by software.

14.3.5.5 Direct Command

Use the direct command feature to send a memory command directly to the memory device through the APB3 port. This way, it is possible to force the memory device to enter active/pre-charge power down, self-refresh or deep power down mode cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.6 MCU-A APPLICATION NOTE

14.3.6.1 DREX Initialization

14.3.6.1.1 LPDDR2/3

The following sequence should be used to initialize LPDDR2 devices. Unless specified otherwise, these steps are mandatory. 1. To provide stable power for memory device, DREX-1 must assert and hold CKE to a logic low level. Then apply stable clock. 2. Set the right value to PHY control register0 for LPDDR2/3 operation mode. If read leveling is needed, check LPDDR2/3 IO calibration MRR data and match it to PHY control register1's ctrl_rlvl_rdata_adj field. (Refer to PHY manual) 3. Set the PHY for dqs pull down mode. (Refer to PHY manual, PHY control register 14) 4. Set the ConControl. At this moment, assert the dfi_init_start field to high but the aref_en field should be off. 5. Wait for the PhyStatus0.dfi_init_complete field to change to [1[. 6. Set the ConControl. At this moment, de-assert the dfi_init_start field to low and the aref_en field should be off. 7. Set the PhyControl0.fp_resync bit-field to [1] to update DLL information for at least one MPCLK cycle. 8. Set the PhyControl0.fp_resync bit-field to [0]. 9. Set the MemControl and PhyControl0. At this moment, all power down modes including sl_dll_dyn_con should be off. 10. Set the MemBaseConfig0 register. If there are two external memory chips, set the MemBaseConfig1 register. 11. Set the MemConfig0 register. If there are two external memory chips, also set the MemConfig1 register. 12. Set the PrechConfig and PwrdnConfig registers. 13. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters. 14. If QoS scheme is required, set the QosControl0 to 15 and QosConfig0 to 15 registers. 15. Set the PHY for LPDDR2/3 initialization. LPDDR2/3 initialization clock period is 18ns to 100ns. If LPDDR2/3 initialization clock period is 20ns, then follow below steps 16 to 22(refer to PHY manual). 16. Set the PHY ctrl_offsetr0 to 3 and ctrl_offsetw0 to 3 value to 0x7F 17. Set the PHY ctrl_offsetd value to 0x7F. 18. Set the PHY ctrl_force value to 0x7F. 19. Set the PHY ctrl_dll_on to low. 20. Wait for 10 MPCLK cycles. 21. Set the PhyControl0.fp_resync bit-field to [1] to update DLL information. 22. Set the PhyControl0.fp_resync bit-field to [0]. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 23. Confirm that CKE has been as a logic low level at least 100ns after power on 24. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level. 25. Wait for minimum 200 us. 26. Issue a MRS command using the DirectCmd register to reset memory devices and program the operating parameters. 27. Wait for minimum 10 us. 28. Issue proper lpddr2 initialization commands according to specification such as IO calibration (MR #10), device feature1, 2 (MR #1, #2). Refer to LPDDR2/3 specification for details. 29. If there are two external memory chips, perform steps 24 to 28 for chip1 memory device. 30. Set the PHY ctrl_offsetr0 to 3 and ctrl_offsetw0 to 3 value to 0x0 31. Set the PHY ctrl_offsetd value to 0x0 32. Set the PHY ctrl_dll_on enable 33. Wait for 10 MPCLK cycles. 34. Set the PHY ctrl_start value to 0. 35. Set the PHY ctrl_start value to 1. 36. Wait for 10 MPCLK cycles. 37. Wait for the PhyStatus0.dfi_init_complete field to change to "1". 38. Set the PhyControl0.fp_resync bit-field to '1' to update DLL information. 39. Set the PhyControl0.fp_resync bit-field to '0'. 40. If any leveling/training is needed, disable ctrl_dll_on and set ctrl_force value. (Refer to PHY manual) 41. If write leveling for LPDDR3 is not needed, skip this procedure. If write leveling is needed, set LPDDR3 into write leveling mode using MRS command, set ODT pin high and tWLO using WRLVL_CONFIG0 register (offset = 0x120) and set the related PHY SFR fields through PHY APB Interface (Refer to PHY manual). To generate 1 cycle pulse of dfi_wrdata_en_p0, write 0x1 to WRLVL_CONFIG1 register (Offset addr = 0x124). To read the value of memory data, use CTRL_IO_RDATA (offset = 0x150). If write leveling is finished, then set ODT pin low and disable write leveling mode of LPDDR3 42. If CA calibration for LPDDR3 is not needed, skip this procedure. If CA calibration is needed, set the related PHY SFR fields through PHY APB Interface (Refer to PHY manual). Set LPDDR3 into CA calibration mode through MR41. For CKE assertion, de-assertion, CA value and tADDR setting, use CACAL_CONFIG0 (offset = 0x160). For Generation 1 cycle pulse of dfi_csn_p0, use CACAL_CONFIG1 (offset = 0x164). To read the value of memory data, use CTRL_IO_RDATA_CH0/CH1 (offset = 0x150, 0x154). Note that CKE pin should be asserted when MR41/48/42 command is issued and CKE pin should be de -asserted during CA calibration. Also note that because CA SDLL code updating needs some cycles to complete, 10 MPCLK cycles are needed before issuing next command. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 43. If read leveling is not needed, skip 44 to 48 and set proper value to PHY control register #2. If read leveling is needed, set the related PHY SFR fields through PHY APB Interface. The related register is PHY control register #1 and #2 (mpr value, ctrl_rdlvl_gate_en and ctrl_rdlvl_en register, refer to PHY manual). 44. Set the RdlvlConfig.ctrl_rdlvl_data_en bit-field to 1'b1. Gate training is not supported. 45. Wait for the PhyStatus0.read_level_complete field to change to [1]. 46. Disable the RdlvlConfig.ctrl_rdlvl_gate_en and ctrl_rdlvl_data_en. 47. Set the PhyControl0.fp_resync bit-field to [1] to update DLL information. 48. Set the PhyControl0.fp_resync bit-field to [0]. 49. If write training is not needed, skip 50 to 55. If write training is nedded, set the related PHY SFR fields through PHY APB Interface. The related register is PHY control register #2 and # 26, refer to PHY manual) 50. Set write latency of PHY control register #26. 51. Enable WrtraConfig.write_training_en to issue ACT command. Refer to this register definition for row and bank address. 52. Wait for 10 MPCLK cycles. 53. Enable write de-skewing of PHY control register #2. 54. Wait for the PhyStatus0.read_level_complete field to change to ?1?. 55. Disable write de-skewing of PHY control register #2. 56. After all leveling/training are completed, enable ctrl_dll_on. (Refer to PHY manual) 57. Set the PhyControl0.fp_resync bit-field to [1] to update DLL information. 58. Set the PhyControl0.fp_resync bit-field to [0]. 59. Disable PHY gating control through PHY APB Interface (ctrl_atgate, see PHY manual). 60. If power down modes are required, set the MemControl register. 61. Set the ConControl to turn on an auto refresh counter. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.6.1.2 DDR3

The following sequence should be used to initialize DDR3 devices. Unless specified otherwise, these steps are mandatory. 1. Apply power. RESET# pin of memory needs to be maintained for minimum 200 us with stable power. CKE is pulled "Low" any time before RESET# being de-asserted (Min. time 10ns) 2. Set the PHY for DDR3 operation mode. If read leveling is needed, check DDR3 MPR dat a and match it to PHY control register1's ctrl_rlvl_rdata_adj field. (Refer to PHY manual) 3. Set the PHY for dqs pull down mode. (Refer to PHY manual, PHY control register 14) 4. If on die termination is required, enable PhyControl0.mem_term_en, PhyControl0.phy_term_en. 5. Set the ConControl. At this moment, assert the dfi_init_start field to high but the aref_en field should be off. 6. Wait for the PhyStatus0.dfi_init_complete field to change to [1]. 7. Set the ConControl. At this moment, de-assert the dfi_init_start field to low and the aref_en field should be off. 8. Set the PhyControl0.fp_resync bit-field to [1] to update DLL information. 9. Set the PhyControl0.fp_resync bit-field to [0]. 10. Set the MemControl and PhyControl0. At this moment, all power down modes including sl_dll_dyn_con and periodic ZQ (pzq_en) should be off. 11. Set the MemBaseConfig0 register. If there are two external memory chips, set the MemBaseConfig1 register. 12. Set the MemConfig0 register. If there are two external memory chips, also set the MemConfig1 register. 13. Set the PrechConfig and PwrdnConfig registers. 14. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters. 15. If QoS scheme is required, set the QosControl0 to 15 and QosConfig0 to 15 registers. 16. Confirm that after RESET# is de-asserted, 500 us have passed before CKE becomes active. 17. Confirm that clocks (CK, CK#) need to be started and stabilized for at least 10 ns or 5 tCK (which is larger) before CKE goes active. 18. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level. 19. Wait for Txpr (Max. (5nCK,tRFC(min)+10ns)) or set tXP to tXPR value before step 17. If the system set tXP to tXPR, then the system must set tXP to proper value before normal memory operation. 20. Issue an EMRS2 command using the DirectCmd register to program the operating parameters. Dynamic ODT should be disabled. A10 and A9 should be low. 21. Issue an EMRS3 command using the DirectCmd register to program the operating parameters. 22. Issue an EMRS command using the DirectCmd register to enable the memory DLL. 23. Issue a MRS command using the DirectCmd register to reset the memory DLL. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 24. Issues a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL. 25. Issues a ZQINIT commands using the DirectCmd register. 26. If there are two external memory chips, perform steps 18 to 25 procedures for chip1 memory device. 27. If any leveling/training is needed, disable ctrl_dll_on and set ctrl_force value. (Refer to PHY manual) 28. If write leveling is not needed, skip this procedure. If write leveling is needed, set DDR3 into write leveling mode using MRS command, set ODT pin high and tWLO using WRLVL_CONFIG0 register (offset = 0x120) and set the related PHY SFR fields through PHY APB Interface (Refer to PHY manual). To generate 1 cycle pulse of dfi_wrdata_en_p0, write 0x1 to WRLVL_CONFIG1 register (Offset add r = 0x124). If write leveling is finished, then set ODT pin low and disable write leveling mode of DDR3 29. If gate leveling is not needed, skip 30 to 33. Gate leveling is only supported DDR3 over 667 MHz. If gate leveling is needed, set the related PHY SFR fields through PHY APB Interface. The related register is PHY control register #0, #1 and #2 (Refer to PHY manual) 30. Set the RdlvlConfig.ctrl_rdlvl_gate_en bit-field to 1'b1. 31. Wait for the PhyStatus0.read_level_complete field to change to [1]. 32. Disable DQS pull down mode. (Refer to PHY manual) 33. Disable the RdlvlConfig.ctrl_rdlvl_gate_en and ctrl_rdlvl_data_en. 34. If read leveling is not needed, skip 35 to 39 and set proper value to PHY control register #2. If read leveling is needed, set the related PHY SFR fields through PHY APB Interface. The related register is PHY control register #1 and #2 (mpr value, ctrl_rdlvl_gate_en and ctrl_rdlvl_en register, refer to PHY manual). 35. Set the ctrl_rdlvl_data_en bit-field to 1'b1. 36. Wait for the PhyStatus0.read_level_complete field to change to [1] 37. Disable the RdlvlConfig.ctrl_rdlvl_gate_en and ctrl_rdlvl_data_en. 38. Set the PhyControl0.fp_resync bit-field to [1] to update DLL information. 39. Set the PhyControl0.fp_resync bit-field to [0]. 40. If write training is not needed, skip 41 to 46. If write training is needed, set the related PHY SFR fields through PHY APB Interface. The related register is PHY control register #2 and #26, refer to PHY manual) 41. Set write latency of PHY control register #26. 42. Enable WrtraConfig.write_training_en to issue ACT command. Refer to this register definition for row and bank address. 43. Wait for 10 MPCLK cycles. 44. Enable write de-skewing of PHY control register #2. 45. Wait for the PhyStatus0.read_level_complete field to change to [1]. 46. Disable write de-skewing of PHY control register #2. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 47. After all leveling/training are completed, enable ctrl_dll_on. (Refer to PHY manual) 48. Set the PhyControl0.fp_resync bit-field to [1] to update DLL information. 49. Set the PhyControl0.fp_resync bit-field to [0]. 50. Disable PHY gating control through PHY APB Interface (ctrl_atgate, refer to PHY manual). 51. If power down modes or periodic ZQ (pzq_en) are required, set the MemControl register. 52. Set the ConControl to turn on an auto refresh counter. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.6.2 DDRPHY Initialization

After power-up and system PLL locking time, system reset (rst_n) is released. 1. Select Memory Type (=PHY_CON0[12:11]).  ctrl_ddr_mode = 2'b11 (LPDDR3)  ctrl_ddr_mode = 2'b10 (LDDR2)  ctrl_ddr_mode = 2'b01 (DDR3) NOTE: If ctrl_ddr_mode[1] = 1'b1, lpddr2_cmd = 14'h000E(=PHY_CON25[13:0]), cmd_default = 14'h000F(=PHY_CON26[13:0]) 2. ZQ Calibration (Please refer to "8.5 ZQ I/O CONTROL PROCEDURE" for more details)  Set Drive Strength (=zq_mode_dds or PHY_CON39[27:0]) properly (Please refer to p56, p63). - Please don't use default value (=0x0)  Enable and Disable "zq_clk_div_en" in PHY_CON16[18]  Enable "zq_manual_str" in PHY_CON16[1]  Wait until "zq_cal_done" (=PHY_CON17[0]) is enabled.  Disable "zq_manual_str" (=PHY_CON16[1]) 3. Memory Controller should assert "dfi_init_start" from LOW to HIGH. 4. Memory Controller should wait until "dfi_init_complete" is set  DLL lock will be processed.  If the frequency of "MDCLK" is changed during operation, "ctrl_start" should be clear and set to lock again. 5. Enable DQS pull down mode 6. Memory Controller should assert "dfi_ctrlupd_req" after "dfi_init_complete" is set. 7. Start Memory Initialization. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 8. Skip the following steps if Leveling and Training are not required.  Constraints during Leveling o Support BL=4 or 8 during Leveling. (Don't use BL=16) o Not support Memory ODT (On-Die-Termination) during Write DQ Calibration.  Enable "ctrl_atgate" in PHY_CON0[6].  Enable "p0_cmd_en" in PHY_CON0[14].  Enable "InitDeskewEn" in PHY_CON2[6].  Enable "byte_rdlvl_en" in PHY_CON0[13].  Set "rdlvl_pass_adj = 4'h6" in PHY_CON1[19:16].  Set "ddr3_cmd = 14'h105E" as default value (=PHY_CON25[29:16)  Set "lpddr2_cmd = 14'h107E" as default value (=PHY_CON25[13:0]) o Set "cmd_default = 16'h000F(LPDDR2, LPDDR3), 16'h107F(DDR2, DDR3)" as default value (=PHY_CON26[13:0])  Recommend that "rdlvl_incr_adj=7'h01" for the best margin. o Calibration time can be shorter by adjusting "rdlvl_incr_adj" in PHY_CON2[22:16].  Disable "ctrl_dll_on" in PHY_CON12[5] before Leveling. o Read "ctrl_lock_value[8:2]" in PHY_CON13[16:10]. o Update "ctrl_force[6:0]" in PHY_CON12[14:8] by the value of "ctrl_lock _value[9:2]".  Write Leveling (refer to 8.1.1)  CA Calibration (refer to 8.1.2)  Gate Leveling (refer to 8.1.3) o It should be used only for DDR3 (800 MHz). Please don't use under 800MHz.  Read DQ Calibration(=Read Leveling) (refer to 8.1.4)  After Read DQ Calibration, refer to "T_rddata_en" to know where "dfi_rddata_en_p0/p1" is enabled. o Read "T_rddata_en" timing parameters in PHY_CON18 after Read DQ Calibration.  Write DQ Calibration (refer to 8.1.5)  Enable "ctrl_dll_on" in PHY_CON12[5].  Disable "ctrl_atgate" in PHY_CON0[6] if controller controls "ctrl_gate_p0/p1" and "ctrl_read_p0/p1" directly.  Enable "DLLDeskewEn" (=PHY_CON2[12]) to compensate Voltage, Temperature variation during operation. 9. Controller should assert "dfi_ctrlupd_req" to make sure All SDLL is updated.  If "ca_swap_mode" is enabled, please don't use "ctrl_atgate=1" during normal operation. NOTE: The goal of data eye training (=Read, Write DQ Calibration) is to identify the delay at which the read DQS rising edge aligns with the beginning and end transitions of the associated DQ data eye. By identifying these delays, the system can calculate the midpoint between the delays and accurately center the read DQS within the DQ data eye. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.6.2.1 Write Leveling

Write Leveling compensates for the additional flight time skew delay introduced by the package, board and on - chip with respect to strobe (=DQS) and clock. The flight time skew between DQS and clock should be under 240ps to be compensated properly and suppose that the clock will be delayed than DQS 1. Memory Controller should configure Memory (DDR3, LPDDR3) in Write Level mode.  Memory Controller should assert "ODT[1:0]" signals(=dfi_odt_p0/p1) during Write Leveling. 2. Configure PHY in Write Level mode.  Enable "wrlvl_mode" in PHY_CON0[16].  "NOP" (CS HIGH at the clock rising edge N) should be used during "wrlvl_mode"=1 (Refer to p105). 3. To find out the optimal Write Level De-skew DLL code for the alignment between CK and DQS  Set each DLL code (PHY_CON30[6:0], PHY_CON[14:8], PHY_CON[23:17], PHY_CON[30:24]). (1) o The start code value should be 0x8. (0x8 to 0x38) o PHY_CON30[6:0] (= "DQS[0]" SDLL code ) o PHY_CON30[14:8] (= "DQS[1]" SDLL code ) o PHY_CON30[23:17] (= "DQS[2]" SDLL code ) o PHY_CON30[30:24] (= "DQS[3]" SDLL code )  Update SDLL code(PHY_CON30[16]). (2) o Enable "ctrl_wrlvl_resync" in PHY_CON30[16] o Disable " ctrl_wrlvl_resync" in PHY_CON30[16]  Memory Controller should generate 1 cycle pulse of "dfi_wrdata_en_p0". (3)  Memory Controller should read the value of "ctrl_io_rdata[0]" which is output of PHY. (4) o If it is zero, Increment "DQS[0]" SDLL code by "1" and then go to "2" to update "DQS[0]" SDLL code. o If it is one, the previous "DQS[0]" SDLL code ("The current SDLL code - 1") will be the optimal SDLL code.  Memory Controller should read the value of "ctrl_io_rdata[8]" which is output of PHY. (5) o If it is zero, Increment "DQS[1]" SDLL code by "1" and then go to "2" to update "DQS[1]" SDLL code. o If it is one, the previous "DQS[1]" SDLL code ("The current SDLL code - 1") will be the optimal SDLL code.  Memory Controller should read the value of "ctrl_io_rdata[16]" which is output of PHY. (6) o If it is zero, Increment "DQS[2]" SDLL code by "1" and then go to "2" to update "DQS[2]" SDLL code. o If it is one, the previous "DQS[2]" SDLL code ("The current SDLL code - 1") will be the optimal SDLL code.  Memory Controller should read the value of "ctrl_io_rdata[31]" which is output of PHY. (7) o If it is zero, Increment "DQS[3]" SDLL code by "1" and then go to "2" to update "DQS[3]" SDLL code. o If it is one, the previous "DQS[3]" SDLL code ("The current SDLL code - 1") will be the optimal SDLL code. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 4. Configure PHY in normal mode after 4 to 7 are finished. (8)  Disable "wrlvl_mode" in PHY_CON0[16]. 5. Memory Controller should configure Memory (DDR3, LPDDR3) in normal mode. (9) cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.6.2.2 CA Calibration

Controller should configure Memory (LPDDR3) in CA Calibration mode. 2. Configure PHY in CA Calibration mode.  Enable "wrlvl_mode" in PHY_CON0[16].  Enable "ca_cal_mode" in PHY_CON2[23]. 3. How to find the optimal CA SDLL code. (=PHY_CON10[7:0])  Change CA SDLL code in PHY_CON10[7:0]. (1) o The start code value should be 0x8.  Update CA SDLL code in PHY_CON10[7:0]. (2) o Enable "ctrl_resync" in PHY_CON10[24] o Disable " ctrl_resync" in PHY_CON10[24]  CA to DQ mapping change to calibrate CA[3:0], CA[8:5]. (3) o Mode Register Write to MR#41 by Controller. o Memory Controller should disable "dfi_cke_p0" and "dfi_cke_p1". (dfi_cke_p0/p1=0)  Memory Controller should generate 1 cycle pulse of "dfi_cs_n_p0" with "dfi_address_p0 = 20'h3FF.  Memory Controller should read and save the value of "ctrl_io_rddata[15:0]" which is output of PHY. o CA[3:0] at rising edge CK (=CA_L[3:0]) is equal to o CA[8:5] at rising edge CK (=CA_L[8:5]) is equal to {ctrl_io_rdata[14], ctrl_io_rdata[12], ctrl_io_rdata[10], ctrl_io_rdata[8]}. o CA[3:0] at falling edge CK (=CA_H[3:0]) is equal to {ctrl_io_rdata[7], ctrl_io_rdata[5], ctrl_io_rdata[3], ctrl_io_rdata[1]}. o CA[8:5] at falling edge CK (=CA_H[8:5]) is equal to {ctrl_io_rdata[15], ctrl_io_rdata[13], ctrl_io_rdata[11], ctrl_io_rdata[9]}.  CA to DQ mapping change to calibrate CA[4], CA[9]. (4) o Memory Controller should enable "dfi_cke_p0" and "dfi_cke_p1". (dfi_cke_p0/p1=1) o Mode Register Write to MR#48 by Controller. o Memory Controller should disable "dfi_cke_p0" and "dfi_cke_p1". (dfi_cke_p0/p1=0)  Memory Controller should generate 1 cycle pulse of "dfi_cs_n_p0" with "dfi_address_p0 = 20'h3FF.  Memory Controller read and save the value of "ctrl_io_rddata[1:0]" and "ctrl_io_rddata[8:9]" which is output of PHY. o CA[4] at rising edge CK (=CA_L[4]) is equal to "ctrl_io_rddata[0]" o CA[9] at rising edge CK (=CA_L[9]) is equal to "ctrl_io_rddata[8]" o CA[4] at falling edge CK (=CA_H[4]) is equal to "ctrl_io_rddata[1]" o CA[9] at falling edge CK (=CA_H[9]) is equal to "ctrl_io_rddata[9]" - Check if "CA_L = 10'h3FF" and "CA_H = 10'h000" or not. (5) cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  If not equaled, o Go to "6" until it searches for the leftmost code value. (7) o If it already saved the leftmost code value, save the current SDLL code by the rightmost code value (=VWMR). Go to "11". (10)  If equaled, o If it is matched for the first time, save the current SDLL code by the leftmost code value (=VWML). Go to "6". (8) o Go to "6" until it searches for the rightmost code value. (9)  Increment SDLL code by "1" and then go to "2" to update SDLL code. (6) 4. Calculate the optimal CA SDLL code (=PHY_CON10[7:0]). (11)  Calculate the optimal CA SDLL code (=VWMC) by the following formula.  VWMC = VWML + (VWMR - VWML)/2  Update CA SDLL code by using "VWMC". 5. Configure PHY in normal mode.  Disable "wrlvl_mode" in PHY_CON0[16]. 6. Memory Controller should configure Memory (LPDDR3) in normal mode. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.6.2.3 Gate Leveling

The goal of gate training is to locate the delay at which the initial read DQS rising edge aligns with the rising edge of the read DQS gate (=ctrl_gate_p0/p1). Once this point is identified, the read DQS gate can be adjusted prior to the DQS, to the approximate midpoint of the read DQS preamble. You can use "GATE Leveling" when using "DDR3 memory" over 800 MHz. 1. Controller should configure Memory (DDR3) in MPR mode. (Please refer to JEDEC Standard.) 2. Set "lpddr2_addr=20'h208" (=PHY_CON22[19:0]) to issue MR32 during GATE Leveling (LPDDR2/3)  In case of CA swap mode, lpddr2_addr=20'h041 to issue MR32 during GATE Leveling 3. Set Gate Leveling Mode.(1)  Enable "gate_cal_mode" in PHY_CON2[24]  Enable "ctrl_shgate" in PHY_CON0[8]  Set "ctrl_gateduradj[3:0] (=PHY_CON1[23:20]) in the following way. o 4'b0000" (DDR3, DDR2) o 4'b1011" (LPDDR3) o 4'b1001" (LPDDR2) 4. Memory Controller should assert "dfi_rdlvl_en" and "dfi_rdlvl_gate_en" to do read leveling. (2) 5. Memory Controller should wait until "dfi_rdlvl_resp" is set. (3)  The maximum waiting time will be 20 us. If the any command (the refresh or pre-charge command) is required within 20 us, please issue those commands before "(1)". 6. Memory Controller should deassert "dfi_rdlvl_en" and "dfi_rdlvl_gate_en" after "dfi_rdlvl_resp" is disabled. 7. Disable DQS pull down mode. (4) 8. Memory Controller should configure Memory (DDR3) in normal mode. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.6.2.4 Read DQ Calibration (=Read Leveling, Read De-skewing)

Read DQ Calibration adjusts for the delays introduced by the package, board and on-chip that impact the read cycle. 1. In case of using DDR3 Memory,  Memory Controller should configure Memory in MPR mode. (Please refer to JEDEC Standard)  Set "PHY_CON1[15:0]" by "0xFF00" if "Pre-defined Data Pattern" is "[0x0000_0000, 0x0101_0101, 0x0000_0000, 0x0101_0101]" (byte_rdlvl_en=1)  Set "PHY_CON1[15:0]" by "0x0100" if "Pre-defined Data Pattern" is "[0x0000_0000, 0xFFFF_FFFF, 0x0000_0000, 0xFFFF_FFFF]" in MPR mode. (byte_rdlvl_en=1) NOTE: Read DQ Calibration with "byte_rdlvl_en=0" should be done after Write DQ Calibration. Set "PHY_CON1[15:0]" by "0xFF00". "MPR Data Pattern" should be "[0x0000_0000, 0xFFFF_FFFF, 0x0000_0000, 0xFFFF_FFFF]". 2. In case of using LPDDR3 or LPDDR2 Memory,  Set "PHY_CON1[15:0]" by "0x00FF" if "MRR32 DQ Pattern" is "[0x0101_0101, 0x0000_0000, 0x0101_0101, 0x0000_0000]" (byte_rdlvl_en=1)  Set "PHY_CON1[15:0]" by "0x0001" if "MRR32 DQ Pattern" is "[0xFFFF_FFFF, 0x0000_0000, 0xFFFF_FFFF, 0x0000_0000]". (byte_rdlvl_en=1) NOTE: Read DQ Calibration with "byte_rdlvl_en=0" should be done after Write DQ Calibration. Set "PHY_CON1[15:0]" by "0x00FF". "MRR32 DQ Pattern" should be "[0xFFFF_FFFF, 0x0000_0000, 0xFFFF_FFFF, 0x0000_0000]". 3. Set "lpddr2_addr=20'h208"(=PHY_CON22[19:0]) to issue MR32 during Calibration (LPDDR2/3)  In case of CA swap mode, lpddr2_addr=20'h041 to issue MR32 during Calibration. o Set Read Leveling Mode.(1) 4. Enable "rd_cal_mode" in PHY_CON2[25]  Memory Controller should assert "dfi_rdlvl_en" to do read leveling. (2)  Memory Controller should wait until "dfi_rdlvl_resp" is set. (3) 5. The maximum waiting time will be 20 us. If the any command (the refresh or pre-charge command) is required within 20 us, please issue those commands before "(1)".  Memory Controller should deassert "dfi_rdlvl_en" after "dfi_rdlvl_resp" is enabled. (4)  Memory Controller should configure Memory (DDR3) in normal mode. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.6.2.5 Write DQ Calibration (=Write Deskewing)

Write DQ Calibration adjusts for the delays introduced by the package, board and on-chip that impact the write cycle. 1. Set Write Latency (WL) before Write Training(1)  Set "T_wrdata_en" by "WL" in PHY_CON26[20:16]. o WL is defined as clock cycles between the write command and the first valid rising edge of DQS 2. Memory Controller should issue "Active Command". 3. PHY will keep writing and reading the pattern in "PHY_CON1[15:0]" for Write DQ Calibration according to the following settings.(2)  The column address should be defined in "lpddr2_addr" in PHY_CON22[19:0](LPDDR2, LPDDR3). o "lpddr2_addr[9:0]" correspond to CA[9:0] at the rising edge of CK, and "lpddr2_addr[19:10]" to CA[19:10] at the falling edge of CK. o It should be the "READ" command. For example, lpddr2_addr = 20'h5 if the column address is 11'h0 and bank address is 3'b000. In case of CA swap mode, lpddr2_addr = 20'h204 if the column address is 11'h0 and bank address is 3'b000.  The column address should be defined in "ddr3_addr" in PHY_CON24[15:0] (DDR3) o For example, if the column address (=ddr3_addr) is "0x0", PHY will write and read the pre-defined pattern (=PHY_CON1[15:0]) at 0x0, 0x4, 0x8 and 0xC for DQ Calibration. (BL=4)  In case of using LPDDR2 or LPDDR3 memory, o Set "PHY_CON1[15:0] = 0x0001" and "byte_rdlvl_en = 1"(=PHY_CON0[13]) o Set "PHY_CON1[15:0] = 0x00FF" and "byte_rdlvl_en = 0"(=PHY_CON0[13]) for Deskewing.  In case of using DDR3 memory, o Set "PHY_CON1[15:0] = 0x0100" and "byte_rdlvl_en = 1"(=PHY_CON0[13]) o Set "PHY_CON1[15:0] = 0xFF00" and "byte_rdlvl_en = 0"(=PHY_CON0[13]) for Deskewing. 4. Enable "p0_cmd_en" in PHY_CON[14]. 5. Set Write Training Mode (3)  Enable "wr_cal_mode" in PHY_CON2[26]. 6. Enable "wr_cal_start" in PHY_CON2[27] to do Write DQ Calibration. (4) 7. Memory Controller should wait until "dfi_rdlvl_resp" is set. (5)  The maximum waiting time will be 50us. If the any command (the refresh or pre-charge command) is required within 50us, please issue those commands before "(3)". 8. Disable "wr_cal_start" in PHY_CON2[27] after "dfi_rdlvl_resp" is enabled. (6) cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.7 DLL Lock and ZQ I/O Calibration

DLL Lock and ZQ I/O calibration should be done prior to the initialization of MCUA Bank Memory following System Power on.

14.3.7.1 Static Memory Map Shadow

Figure 14-5 Static Memory is composed of Static#0 to #1 (External Static Memory), Static#13 (Internal ROM) and NAND as Figure. However, base address of internal ROM, and nSCS[0] is changed according to system boot mode. In internal ROM Boot Mode, base address of internal ROM is supposed to be exchanged with that of nSCS[0]. The previous Base Address remains in case of External Static Boot. Figure 14-5 Static Memory Map Shadow cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.7.2 Interface

32-bit Data bus width SDRAM Interface of MCU-A Bank MCU-A supports 32-bit data bus-width to CS[0] and CS[1] respectively. Figure 14-6 16-bit Data Bus width SDRAM Interface 16-bit Data bus width SDRAM Interface of MCU-A Bank 16-bit DDR3 SDRAM can add each two Memory to CS[0] and CS[1] respectively, which total four. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Figure 14-7 16-bit Data Bus width SDRAM Interface cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-26 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.3.8 NAND Overview

14.3.8.1 Normal Access Sequence

 Write NAND Flash Command at NFCMD Register.  Write Address to NFADDR Register with respect to NAND Flash Address Type. (Refer to NAND Flash data book)  Check IRQPEND bit.  Read ECC Data from NAND Flash Spare Array and Write ORGECC Register.  Read Data (512/1024 byte) from NAND Flash Main Array.  Check NFDecECCDone Register  Check NFCheckError Register Write Cycle  Write NAND Flash Command to NFCMD Register. (Refer to NAND Flash data book)  Access address of memory which tries to access to NFADDR Register by 3 to 5 time according to the sort of NAND Flash. (Refer to NAND Flash data book)  Write data (512/1024 byte) through NFDATA Register.  Check NFEncECCDone Register.  Read the result of ECC through NFECC Register. (Small block only)  Write NAND Flash Command to NFCMD Register. (Refer to NAND Flash data book)  Check whether NAND Flash is ready or not by reading NFCONTROL.IRQPEND bit. (For the e xact sequence of NAND Flash, Please refer to NAND Flash data book)

14.3.8.2 ECC (BCH)

 Hardware ECC generation, detection and indication (software correction) 4/8/16/24/40/60 bit error correction and detection  Error Detection Code/Error Correction Code (EDC/ECC) NAND-based MLC flash has error weakness therefore error handling method is required. S5P4418 can perform EDC (error detecting codes) and ECC (error correction codes) and both based on BCH (Bose- Chadhuri-Hocquenghem) algorithm.EDC is run by hardware to reduce CPU overload and increase the CPU performance. In contrast, ECC is run by software. Parity bit is calculated on every 512/1024 byte page. Syndrome is calculated when each data is read from NAND flash and the value is used in error correction operation.  Hardware ECC generation reset  This reset is asserted when NAND address or command register is written by any value.  This reset is also asserted when ECCRST bit (NFCONTROL register [11] bit) register is set to 1  This reset initializes NFECCL, NFECCH, NFCNT, NFECCSTATUS, NFSYNDRONE0 to 7 Registers. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4 Register Description

14.4.1 Register Map Summary

 Base Address: 0xC00E_0000 (DREX) Register Offset Description Reset Value DREX ConControl 0x0000 Controller control register 0x0FFF_1100 MemControl 0x0004 Memory control register 0x0020_2601 MemConfig0 0x0008 Memory chip0 configuration register 0x0000_1312 MemConfig1 0x000C Memory chip1 configuration register 0x0000_1312 DirectCmd 0x0010 Memory direct command register 0x0000_0000 PrechConfig 0x0014 Pre-charge policy configuration register 0xFF00_0000 PhyControl0 0x0018 PHY control0 register 0x0000_0000 RSVD 0x001C to 0x0024 Reserved 0x0000_0000 PwrdnConfig 0x0028 Dynamic power down configuration register oxFFFF_00FF TimingPZQ 0x002C AC timing register for periodic ZQ(ZQCS) of memory 0x0000_4084 TimingAref 0x0030 AC timing register for auto refresh of memory 0x0000_005D TimingRow 0x0034 AC timing register for the row of memory 0x1F23_3286 TimingData 0x0038 AC timing register for the data of memory 0x1230_360C TimingPower 0x003C AC timing register for the power modes of memory 0x381B_0422 PhyStatus 0x0040 PHY status register 0x0000_0000 RSVD 0x0044 Reserved 0x0000_0000 ChipStatus 0x0048 Memory chipstatus register 0x0000_0000 RSVD 0x004C to 0x0050 Reserved 0x0000_0000 MrStatus 0x0054 Memory mode registers status register 0x0000_0000 RSVD 0x0058 to 0x005C Reserved 0x0000_0000 QosControl n 0x0060 to 0x00D8 Quality of service control register n 0x0000_0FFF RSVD 0x00DC to 0x00F0 Reserved 0x0000_0000 WrTraConfig 0x00F4 Write training configuration register 0x0000_0000 RdlvlConfig 0x00F8 Read leveling configuration register 0x0000_0000 RSVD 0x00FC Reserved 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-28 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value BRBRSVCONTROL 0x0100 BRB reservation control register 0x0000_0000 BRBRSVCONFIG 0x0104 BRB reservation configuration register 0x8888_8888 BRBQOSCONFIG 0x0108 BRB QoS configuration register 0x0000_0010 MemBaseConfig0 0x010C Memory chip0 base configuration register 0x0020_07F8 MemBaseConfig1 0x0110 Memory chip1 base configuration register 0x0020_07F8 RSVD 0x0114 to 0x011C Reserved 0x0000_0000 WRLVLCONFIG0 0x0120 Write leveling configuration register0 0x0000_0010 WRLVLCONFIG1 0x0124 Write leveling configuration register1 0x0000_0000 WRLVLSTATUS 0x0128 Write leveling status register 0x0000_0000 RSVD 0x012C to 0x014C Reserved 0x0000_0000 CTRL_IO_RDATA 0x0150 CTRL_IO_RDATA register 0x0000_0000 RSVD 0x0154 to 0x015C Reserved 0x0000_0000 CACAL_CONFIG0 0x0160 CA calibration configuration register0 0x003F_F010 CACAL_CONFIG1 0x0164 CA calibration configuration register1 0x0000_0000 CACAL_STATUS 0x0168 CA calibration status register 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-29 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  Base Address: 0xC00E_1000 (DDRPHY) Register Offset Description Reset Value DDRPHY PHY_CON0 0x1000 PHY Control Register 0 0x1702_0240 PHY_CON1 0x1004 PHY Control Register 1 0x0921_0100 PHY_CON2 0x1008 PHY Control Register 2 0x0001_0000 PHY_CON3 0x100C GATE SDLL Code Control Register 0 0x0001_0842 PHY_CON4 0x1010 READ SDLL Code Control Register 0 0x0808_0808 PHY_CON5 0x1014 READ Mode Control Register 0x0000_0000 PHY_CON6 0x1018 WRITE SDLL Code Control Register 0 0x0808_0808 RSVD 0x101C Reserved 0x0000_0000 PHY_CON8 0x1020 GATE SDLL Code Control Register 1 0x0000_0000 PHY_CON9 0x1024 GATE SDLL Code Control Register 2 0x0000_0000 PHY_CON10 0x1028 CMD SDLL Code Control Register 0x0000_0008 RSVD 0x102C Reserved 0x0000_0000 PHY_CON12 0x1030 MDLL Control Register 0 0x1010_0070 PHY_CON13 0x1034 MDLL Control Register 1 - PHY_CON14 0x1038 Low Power Control Register 0x001F_0000 PHY_CON15 0x103C Feedback Test Control Register 0x0000_0000 PHY_CON16 0x1040 ZQ Control Register 0x0800_0304 PHY_CON17 0x1048 ZQ Status Register - PHY_CON18 0x104C Read Leveling Status Register 0 0x0055_5555 PHY_CON19 0x1050 Read Leveling Status Register 1 - PHY_CON20 0x1054 Read Leveling Status Register 2 - PHY_CON21 0x1058 Read Leveling Status Register 3 - PHY_CON22 0x105C Read Leveling Control Register 0 0x0000_0208 PHY_CON23 0x1060 Read Leveling Control Register 1 0x0000_03FF PHY_CON24 0x1064 Read Leveling Control Register 2 0x0000_0000 PHY_CON25 0x1068 Read Leveling Control Register 3 0x105E_107E PHY_CON26 0x106C Read Leveling Control Register 4 0x0008_107F PHY_CON27 0x1070 PHY Control Register 27 - PHY_CON28 0x1074 Read Leveling Status Register 4 - PHY_CON29 0x1078 Version Information Register 0x0501_0203 PHY_CON30 0x107C Write Leveling Control Register 0x0000_0000 PHY_CON31 0x1080 CA De-skew Control Register 0 0x0000_0000 PHY_CON32 0x1084 CA De-skew Control Register 1 0x0000_0000 PHY_CON33 0x1088 CA De-skew Control Register 2 0x0000_0000 PHY_CON34 0x108C CA De-skew Control Register 3 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-30 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value RSVD 0x1090 to 0x1094 Reserved 0x0000_0000 PHY_CON37 0x1098 CMD De-skew Control Register 1 0x0000_0000 RSVD 0x109C Reserved 0x0000_0000 PHY_CON39 0x10A0 Driver Strength Control Register 0x0000_0000 PHY_CON40 0x10A4 ZQ Divider Control Register 0x0000_0007 PHY_CON41 0x10A8 ZQ Timer Control Register 0x0000_00F0 PHY_CON42 0x10AC PHY Control Register 3 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-31 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  Base Address: 0xC005_1000 (MCUS_ADDR) Register Offset Description Reset Value MCUS_ADDR MEMBW 0x1000 Memory bus width register Note MEMTIMEACSL 0x1004 Memory timing for TACS low register Note MEMTIMEACSH 0x1008 Memory timing for TACS high register 0x0000_0000 MEMTIMECOSL 0x100C Memory timing for TCOS low register Note MEMTIMECOSH 0x1010 Memory timing for TCOS high register 0x0000_0000 MEMTIMEACC0 0x1014 Memory timing for TACC 0 register Note RSVD 0x1018 Reserved - RSVD 0x101C Reserved - MEMTIMEACC3 0x1020 Memory timing for TACC 3 register 0x0000_0000 MEMTIMESACC0 0x1024 Memory timing for TSACC 0 register 0x0000_0000 RSVD 0x1028 Reserved - RSVD 0x102C Reserved - MEMTIMESACC3 0x1030 Memory timing for TSACC 3 register 0x0000_0000 RSVD 0x1034 to 0x1040 Reserved 0x0000_0000 MEMTIMECOHL 0x1044 MEMORY TIMING FOR TCOH low register Note MEMTIMECOHH 0x1048 MEMORY timing for TCOH high register 0x0000_0000 MEMTIMECAHL 0x104C MEMORY timing for TCAH low register Note MEMTIMECAHH 0x1050 MEMORY timing for TCAH high register 0x0000_0000 MEMBURSTL 0x1054 MEMORY burst control low register 0x0000_0010 RSVD 0x1058 Reserved - MEMWAIT 0x105C Memory wait control register 0x0000_0000 RSVD 0x1060 to 0x1084 Reserved - NFCONTROL 0x1088 NAND flash control register Note NFECCTRL 0x108C NAND ECC control register 0x0000_0000 NFCNT 0x1090 NAND flash data count register 0x0000_0000 NFECCSTATUS 0x1094 NAND flash ECC status register 0x0000_0000 NFTIMEACS 0x1098 NAND timing for TACS register 0x0000_0007 NFTIMECOS 0x109C NAND timing for TCOS register 0x0000_0007 NFTIMEACC0 0x10A0 NAND timing for TACC0 register 0x0000_000F RSVD 0x10A4 Reserved - NFTIMEOCH 0x10A8 NAND timing for TOCH register 0x0000_0007 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-32 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value NFTIMECAH 0x10AC NAND timing for TCAH register 0x0000_0007 NFECC0 ~ NFECC26 0x10B0 to 0x1118 NAND flash ECC 0 ~ 26 register 0x0000_0000 NFORGECC0 ~ NFORGECC26 0x111C to 0x1184 NAND flash origin ECC 0~26 register 0x0000_0000 NFSYNDROME0 ~ NFSYNDROME29 0x1188 to 0x11FC NAND flash ECC syndrome value 0~29 register 0x0000_0000 NFELP0 ~ NFELP59 0x1200 to 0x1274 NAND flash ECC ELP value 0 ~ 59 register - NFERRORLOCATION0 NFERRORLOCATION59 0x1278 to 0x12EC NAND flash error location 0 ~ 59 register - AUTOSYND 0x12F0 AUTO SYNDROM REGISTER 0x0000_0000 NFWSYNDRONE0 ~ NFWSYNDRONE29 0x12F4 to 0x1368 NAND flash ECC write syndrome value 0~29 register 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-33 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  Base Address: 0x2C00_0000 (MCUS_ADDR) Register Offset Description Reset Value NFDATA 0x0000 NAND flash data register – NFCMD 0x0010 NAND flash command register – NFADDR 0x0018 NAND flash address register – cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-34 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1 DREX Register

14.4.1.1.1 ConControl

 Base Address: 0xC00E_0000  Address = Base Address + 0x0000, Reset Value = 0x0FFF_1100 Name Bit Type Description Reset Value RSVD [31:29] – Reserved (Should be zero) 0x0 dfi_init_start [28] RW DFI PHY initialization start This field is used to initialize DFI PHY. Set this field to 1 to initialize DFI PHY and set this field to 0 after received dfi_init_complete of PhyStatus register. 0x0 timeout_level0 [27:16] RW Default Timeout Cycles This counter prevents transactions in the AXI request FIFO from starvation. This counter starts if a new AXI transaction comes into the request FIFO. If the counter becomes zero, the corresponding FIFO has the highest priority during BRB arbitration. Refer to Section 1.7. Quality of Service for de-tailed information 0xFFF RSVD [15] – Reserved (Should be zero) 0x0 rd_fetch [14:12] RW Read Data Fetch Cycles 0xn = n MBCLK cycles (MBCLK : DREX-1 core clock) The recommended value of this field is 0x2 for LPDDR3 800 MHz memory clock and other cases are 0x1. This register is for the unpredictable latency of read data coming from memory devices by tDQSCK variation or the board flying time. The read fetch delay of PHY read FIFO must be controlled by this parameter. The controller will fetch read data from PHY after read_latency + n MBCLK cycles. Refer to Section 1.3 for detailed information. 0x1 RSVD [11:9] – Reserved (Should be zero) 0x0 empty [8] R Empty Status 0x0 = Not Empty, 0x1 = Empty There is no AXI transaction in memory controller. 0x1 RSVD [7:6] – Reserved (Should be zero) 0x0 aref_en [5] RW Auto Refresh Counter 0x0 = Disable, 0x1 = Enable Enable this to decrease the auto refresh counter by 1 at the rising edge of the MPCLK 0x0 RSVD [4] – Reserved (Should be zero) 0x0 io_pd_con [3] RW I/O Power down Control in Low Power Mode(through LPI) 0x0 : Use programmed ctrl_pd and pull down control 0x1 : Automatic control for ctrl_pd and pull down control 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-35 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value If this value is set to 0x1 and in low power mode through LPI, DREX-1 automatically sets power down enable for input buffer of I/O and pull down disable for dq and dqs in power down mode If this value is set to 0x0, DREX-1 only sends programmed ctrl_pd value and pull down control. clk_ratio [2:1] RW Clock Ratio of Bus Clock to Memory Clock 0x0 = freq.(MBCLK): freq.(MBCLK) = 1: 1, 0x1 to 0x3 = Reserved 0x0 RSVD [0] – Reserved (Should be zero) 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-36 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.2 MemControl

 Base Address: 0xC00E_0000  Address = Base Address + 0x0004, Reset Value = 0x00202601 Name Bit Type Description Reset Value RSVD [31:27] – Reserved (Should be zero) 0x0 mrr_byte [26:25] RW Mode Register Read byte lane location 0x0 = memory dq[7:0] 0x1 = memory dq[15:8] 0x2 = memory dq[23:16] 0x3 = memory dq[31:24] 0x0 pzq_en [24] RW DDR3 periodic ZQ (ZQCS) enable NOTE: That after exit from self refresh, ZQ function is required by the software. The controller does not support ZQ calibration command to be issued in parallel to DLL lock time when coming out of self refresh. Turn-on only when using DDR3. The periodic ZQ interval is defined by t_pzq in TIMINGPZQ register. 0x0 RSVD [23] – Reserved (Should be zero) 0x0 bl [22:20] RW Memory Burst Length 0x0 to 1 = Reserved, 0x2 = 4, 0x3 = 8, 0x4 to 0x7 = Reserved In case of LPDDR2-S4, the controller only supports burst length 4. In case of DDR3 and LPDDR3, the controller only supports burst length 8. 0x2 num_chip [19:16] RW Number of Memory Chips 0x0 = 1 chip, 0x1 = 2 chips, 0x2 to 0xf = Reserved 0x0 mem_width [15:12] RW Width of Memory Data Bus 0x0 to 0x1 = Reserved, 0x2 = 32-bit, 0x3 to 0xf= Reserved 0x2 mem_type [11:8] RW Type of Memory 0x0 to 0x4 = Reserved, 0x5 = LPDDR2-S4, 0x6 = DDR3, 0x7 = LPDDR3, 0x8 to 0xf = Reserved 0x6 add_lat_pall [7:6] RW Additional Latency for PALL in MBCLK cycle 0x0 = 0 cycle, 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-37 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 0x1 = 1 cycle 0x2 = 2 cycle, 0x3 = Reserved If all banks pre-charge command is issued, the latency of pre-charging will be tRP + add_lat_pall dsref_en [5] RW Dynamic Self Refresh 0x0 = Disable, 0x1 = Enable Refer to Section 1.5.2. Dynamic power down for detailed information. In DDR3, this feature is not supported. This feature must be turn-off when using DDR3. 0x0 tp_en [4] RW Timeout Pre-charge 0x0 = Disable, 0x1 = Enable If tp_en is enabled, it automatically pre-charges an open bank after a specified amount of mclk cycles (if no access has been made in between the cycles) in an open page policy. If Prech-Config.tp_cnt bit-field is set, it specifies the amount of mclk cycles to wait until timeout pre-charge pre- charges the open bank. Refer to Section 1.6.2. Timeout pre-charge for detailed information. 0x0 dpwrdn_type [3:2] RW Type of Dynamic Power Down 0x0 = Active/pre-charge power down, 0x1 = Forced pre-charge power down 0x2 to 0x3 = Reserved Refer to Section 1.5.2. Dynamic power down for detailed information. 0x0 dpwrdn_en [1] RW Dynamic Power Down 0x0 = Disable, 0x1 = Enable 0x0 clk_stop_en [0] RW Dynamic Clock Control 0x0 = Always running, 0x1 = Stops during idle periods This feature is only supported with LPDDR2/LPDDR3. Refer to Section 1.5.4. Clock stop for detailed information. 0x1 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-38 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.3 MemConfig0

 Base Address: 0xC00E_0000  Address = Base Address + 0x0008, Reset Value = 0x0000_1312 Name Bit Type Description Reset Value RSVD [31:16] – Reserved (Should be zero) 0x0 chip_map [15:12] RW Address Mapping Method (AXI to Memory) 0x0 = Linear ({bank, row, column, width}), 0x1 = Interleaved ({row, bank, column, width}), 0x2 to 0xf = Reserved 0x1 chip_col [11:8] RW Number of Column Address Bits 0x0 = Reserved, 0x1 = Reserved, 0x2 = 9 bits, 0x3 = 10 bits, 0x4 = Reserved, 0x5 to 0xf = Reserved 0x3 chip_row [7:4] RW Number of Row Address Bits 0x0 = 12 bits, 0x1 = 13 bits, 0x2 = 14 bits, 0x3 = 15 bits, 0x4 = 16 bits, 0x5 to 0xf = Reserved 0x1 chip_bank [3:0] RW Number of Banks 0x0 = Reserved, 0x1 = Reserved, 0x2 = 4 banks, 0x3 = 8 banks, 0x4 to 0xf = Reserved 0x2 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-39 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.4 MemConfig1

 Base Address: 0xC00E_0000  Address = Base Address + 0x000C, Reset Value = 0x0000_1312 Name Bit Type Description Reset Value RSVD [31:16] – Reserved (Should be zero) 0x0 chip_map [15:12] RW Address Mapping Method (AXI to Memory) 0x0 = Linear ({bank, row, column, width}), 0x1 = Interleaved ({row, bank, column, width}), 0x2 to 0xf = Reserved 0x1 chip_col [11:8] RW Number of Column Address Bits 0x0 = Reserved, 0x1 = Reserved, 0x2 = 9 bits, 0x3 = 10 bits, 0x4 = Reserved, 0x5 to 0xf = Reserved 0x3 chip_row [7:4] RW Number of Row Address Bits 0x0 = 12 bits, 0x1 = 13 bits, 0x2 = 14 bits, 0x3 = 15 bits, 0x4 = 16 bits, 0x5 to 0xf = Reserved 0x1 chip_bank [3:0] RW Number of Banks 0x0 = Reserved, 0x1 = Reserved, 0x2 = 4 banks, 0x3 = 8 banks, 0x4 to 0xf = Reserved 0x2 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-40 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.5 DirectCmd

 Base Address: 0xC00E_0000  Address = Base Address + 0x0010, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:28] – Reserved (Should be zero) 0x0 cmd_type [27:24] RW Type of Direct Command 0x0 = MRS/EMRS (mode register setting), 0x1 = PALL (all banks pre-charge), 0x2 = PRE (per bank pre-charge), 0x3 = DPD (deep power down), 0x4 = REFS (self refresh), 0x5 = REFA (auto refresh), 0x6 = CKEL (active/pre-charge power down), 0x7 = NOP (exit from active/pre-charge power down or deep power down, 0x8 = REFSX (exit from self refresh), 0x9 = MRR (mode register reading), 0xa = ZQINIT (ZQ calibration init.) 0xb = ZQOPER (ZQ calibration long) 0xc = ZQCS (ZQ calibration short) 0xd to 0xf = Reserved When a direct command is issued, AXI masters must not access memory. It is strongly recommended to check the command queue's state by ConControl.chip0/1_empty and the chip FSM in the ChipStatus register before issuing a direct command. The chip status must be checked before issuing a direct command. And clk_stop_en, dynamic power down, dynamic self refresh, force pre-charge function (MemControl register) and sl_dll_dyn_con (PhyControl0 register) must be disabled. MRS/EMRS or MRR commands should be issued if all banks are in idle state. If MRS/EMRS or MRR is issued to LPDDR2-S4/LPDDR3, the CA pins must be mapped as follows. MA[7:0] = {cmd_addr[1:0], cmd_bank[2:0], cmd_addr[12:10]}, OP[7:0] = cmd_addr[9:2] In DDR3, self refresh related timing such as tCKESR/tCKSRE/tCKSRX should be check by software. NOTE: That do not write reserved value to this field. 0x0 Reserved [23:21] – Reserved (Should be zero) 0x0 cmd_chip [20] RW Chip Number to send the direct command to 0 = Chip 0 1 = Chip 1 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-41 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value RSVD [19] – Reserved (Should be zero) 0x0 cmd_bank [18:16] RW Related Bank Address when issuing a direct command To send a direct command to a chip, additional information such as the bank address is required. This register is used in such situations 0x0 cmd_addr [15:0] RW Related Address value when issuing a direct command To send a direct command to a chip, additional information such as the address is required. This register is used in such situations. 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-42 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.6 PrechConfig

 Base Address: 0xC00E_0000  Address = Base Address + 0x0014, Reset Value = 0xFF00_0000 Name Bit Type Description Reset Value tp_cnt [31:24] RW Timeout Pre-charge Cycles 0xn = n MBCLK cycles, The minimum vlaue of this field is 0x2 If the timeout pre-charge function (MemControl.tp_en) is enabled and the timeout pre-charge counter becomes zero, the controller forces the activated memory bank into the pre-charged state. Refer to Section 1.6.2 .Timeout pre- charge for detailed information. 0xFF RSVD [23:16] – Reserved (Should be zero) 0x0 chip1_policy [15:8] RW Memory Chip1 Pre-charge Bank Selective Policy 0x0 = Open page policy, 0x1 = Close page (auto pre-charge) policy chip1_policy[n], n is the bank number of chip1. Open Page Policy: After a READ or WRITE, the row that was accessed is left open. Close Page (Auto Pre-charge) Policy: Right after a READ or WRITE command, memory devices automatically pre- charges the bank. This is a bank selective pre-charge policy. For example, if chip1_policy[2] is 0x0, bank2 of chip1 has an open page policy and if chip1_policy[6] is 0x1, bank6 of chip1 has a close page policy. Refer to Section 1.6.1. Bank Selective Pre-charge for detailed information. 0x0 chip0_policy [7:0] RW Memory Chip0 Pre-charge Bank Selective Policy 0x0 = Open page policy, 0x1 = Close page (auto pre-charge) policy Chip0_policy[n], n is the bank number of chip0. This is for memory chip0. 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-43 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.7 PhyControl0

 Base Address: 0xC00E_0000  Address = Base Address + 0x0018, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value mem_term_en [31] RW Termination Enable for Memory At high-speed memory operation, it can be necessary to turn on termination resistance in memory devices. This register control s an ODT pin of a memory device. 0x0 phy_term_en [30] RW Termination Enable for PHY At high-speed memory operation, it can be necessary to turn on termination resistance in the PHY. 0x0 ctrl_shgate [29] – Duration of DQS Gating Signal This field controls the gate control signal In LPDDR2-S4/LPDDRD3, this field should be 1‟b0 regard-less of clock frequency. In DDR3, according to memory clock, set the value like be-low. 1‟b0 = (gate signal length = “burst length / 2” (<= 200MHz)) 1‟b1 = (gate signal length = “burst length / 2” - 1 (> 200MHz)) 0x0 ctrl_pd [28:24] RW Input Gate for Power Down If this field is set, input buffer is off for power down. This field should be 0 for normal operation. Ctrl_pd[3:0] = for each data slice, Ctrl_pd[4] = for control slice. 0x0 RSVD [23:7] – Reserved (Should be zero) 0x0 dqs_delay [6:4] RW Delay Cycles for DQS Cleaning This register is to enable PHY to clean incoming DQS signals delayed by external circumstances. If DQS is coming with read latency plus n memory clock cycles, this registers must be set to n memory clock cycles. 0x0 fp_resync [3] RW Force DLL Re-synchronization 0x0 RSVD [2] – Reserved (Should be zero) 0x0 sl_dll_dyn_con [1] RW Turn On PHY Slave DLL Dynamically 0 = Disable, 1 = Enable 0x0 mem_term_chips [0] RW Memory termination between chips 0 = Disable, 1 = Enable This field is only valid when num_chip is 0x1(2 chips) in MemControl register and DDR3. 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-44 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.8 PwrdnConfig

 Base Address: 0xC00E_0000  Address = Base Address + 0x0028, Reset Value = 0xFFFF_00FF Name Bit Type Description Reset Value dsref_cyc [31:16] RW Number of Cycles for dynamic self refresh entry 0xn = n MBCLK cycles, The minimum value of this field is 0x2. If the command queue is empty for n+1 cycles, the controller forces memory devices into self refresh state. Refer to Section 1.5.3. Dynamic self refresh for detailed information. 0xFFFF RSVD [15:8] – Reserved (Should be zero) 0x0 dpwrdn_cyc [7:0] RW Number of Cycles for dynamic power down entry 0xn = n MBCLK cycles, The minimum value of this field is 0x2. If the command queue is empty for n+1 cycles, the controller forces the memory device into active/pre-charge power down state. Refer to Section 1.5.2. Dynamic power down for detailed information. 0xFF

14.4.1.1.9 TimingPZQ

 Base Address: 0xC00E_0000  Address = Base Address + 0x002C, Reset Value = 0x0000_4084 Name Bit Type Description Reset Value RSVD [31:24] – Reserved (Should be zero) 0x0 t_pzq [23:0] RW Average Periodic ZQ Interval(Only in DDR3) tREFI(t_refi T(MPCLK)) t_pzq should be less than or equal to the minimum value of memory periodic ZQ interval, for example, if MPCLK frequency is 12 MHz, t_refi is set to 93 and ZQ interval is 128ms then the following value should be programmed into it: 128 ms * 12 MHz / 93 = 16516 The minimum value is 2. 0x4084 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-45 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.10 TimingAref

 Base Address: 0xC00E_0000  Address = Base Address + 0x0030, Reset Value = 0x0000_005D Name Bit Type Description Reset Value RSVD [31:16] – Reserved (Should be zero) 0x0 t_refi [15:0] RW Average Periodic Refresh Interval t_refi * T(MPCLK) should be less than or equal to the minimum value of memory tREFI (all bank), for example, for the all bank refresh period of 7.8us, and an MPCLK frequency of 12 MHz, the following value should be programmed into it: 7.8 us * 12 MHz = 93 0x5D

14.4.1.1.11 TimingRow

 Base Address: 0xC00E_0000  Address = Base Address + 0x0034, Reset Value = 0x1F23_3286 Name Bit Type Description Reset Value t_rfc [31:24] RW Auto refresh to Active / Auto refresh command period, in MBCLK cycles t_rfc * T(MBCLK) should be greater than or equal to the minimum value of memory tRFC and the minimum value is 17 if PHY is running with dll on. In FPGA with low frequency and dll is off, the minimum value is 3. 0x1F t_rrd [23:20] RW Active bank A to Active bank B delay, in MBCLK cycles t_rrd * T(MBCLK) should be greater than or equal to the minimum value of memory tRRD. The minimum value is 2. 0x2 t_rp [19:16] RW Pre-charge command period, in MBCLK cycles t_rp * T(MBCLK) should be greater than or equal to the minimum value of memory tRP. The minimum value is 2. 0x3 t_rcd [15:12] RW Active to Read or Write delay, in MBCLK cycles t_rcd * T(MBCLK) should be greater than or equal to the minimum value of memory tRCD + T(MBCLK)/2. For example, tRCD in memory specification is 13.75ns and MBCLK is 3.0ns, t_rcd * 3ns >= 13.75ns + 1.5ns The right value for t_rcd is 6. The minimum value is 2. 0x3 t_rc [11:6] RW Active to Active period, in MBCLK cycles t_rc * T(MBCLK) should be greater than or equal to the minimum value of memory tRC. The minimum value is 2. 0xA cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-46 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value t_ras [5:0] RW Active to Pre-charge command period, in MBCLK cycles t_ras * T(MBCLK) should be greater than or equal to the minimum value of memory tRAS + T(MBCLK)/2. For example, tRAS in memory specification is 35ns and MBCLK is 3.0ns. t_ras * 3ns >= 35ns + 1.5ns The right value for t_ras is 13. The minimum value is 2. 0x6 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-47 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.12 TimingData

 Base Address: 0xC00E_0000  Address = Base Address + 0x0038, Reset Value = 0x1230_360C Name Bit Type Description Reset Value t_wtr [31:28] RW Internal write to Read command delay, in MBCLK cycles t_wtr * T(MBCLK) should be greater than or equal to the minimum value of memory tWTR In LPDDR2-S4/LPDDR3 t_wtr is max(2tCK, tWTR) andIn DDR3 t_wtr is max(4tCK, tWTR). And then this value should be changed in MBCLK cycles. The minimum value is 2. 0x1 t_wr [27:24] RW Write recovery time, in MBCLK cycles t_wr * T(MBCLK) should be greater than or equal to the minimum value of memory tWR. The minimum value is 2. 0x2 t_rtp [23:20] RW Internal read to Pre-charge command delay, in MBCLK cycles t_rtp * T(MBCLK) should be greater than or equal to the minimum value of memory tRTP. The minimum value is 2. 0x3 RSVD [19:17] RW Reserved (Should be zero) 0x0 t_w2w_c2c [16] RW Additional Write to Write delay in chip to chip case in MBCLK cycles. If mem_term_en of PhyControl0 register (offset addr = 0x18) is enabled, then this value will be set to 1 automatically. 0x0 t_r2r_c2c [15] RW Additional Read to Read delay in chip to chip case in MBCLK cycles. If mem_term_chips of PhyControl0 register (offset addr = 0x18) is enabled, then this value will be set to 1 automatically. 0x0 dqsck [14:12] – tDQSCK in memory clock cycles In DDR3, this field should set to 0. In LPDDR2/3, this field should be set to RU (tDQSCK max/tCK). tDQSCK max is 5.5ns in LPDDR2/3. 0x3 wl [11:8] RW Write data latency (for LPDDR2-S4/LPDDR3/DDR3), in memory clock cycles wl should be greater than or equal to the minimum value of memory WL. There is no restriction with LPDDR2-S4 but there is restriction with LPDDR3 and DDR3 like below. In LPDDR3, the minimum wl is 5 and in DDR3, the minimum wl is 6. 0x6 RSVD [7:4] – Reserved (Should be zero) 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-48 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value rl [3:0] RW Read data latency (for LPDDR2-S4/LPDDR3/DDR3), in memory clock cycles rl should be greater than or equal to the minimum value of memory RL 0xC cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-49 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.13 TimingPower

 Base Address: 0xC00E_0000  Address = Base Address + 0x003C, Reset Value = 0x381B_0422 Name Bit Type Description Reset Value t_faw [31:26] RW Four Active Window(for LPDDR2-S4/LPDDR3/DDR3) t_faw * T(MBCLK) should be greater than or equal to the minimum value of memory tFAW. The minimum value is 2. 0xE t_xsr [25:16] RW Self refresh exit power down to next valid command delay, in cycles t_xsr * T(MBCLK) should be greater than or equal to the minimum value of memory tXSR. In DDR3, this value should be set to tXSDLL. The minimum value is 2. 0x1B t_xp [15:8] RW Exit power down to next valid command delay, in cycles t_xp * T(MBCLK) should be greater than or equal to the minimum value of memory tXP In DDR3, this value should set to tXPDLL. In DDR3 even though “fast exit” is programmed in MRS, tXPDLL is applied. In DDR3, tXPDLL is likely Max. (10nCK, 24ns). So note that t_xp should set to Max. (5nMBCLK, 24ns/MBCLK period). The minimum value is 2. 0x4 t_cke [7:4] RW CKE minimum pulse width (minimum power down mode duration), in cycles t_cke should be greater than or equal to the minimum value of memory tCKE. The minimum value is 2. 0x2 t_mrd [3:0] RW Mode Register Set command period, in cycles t_mrd should be greater than or equal to the minimum value of memory tMRD In DDR3, this parameter should be set to tMOD value. The minimum value is 2. 0x2 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-50 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.14 PhyStatus

 Base Address: 0xC00E_0000  Address = Base Address + 0x0040, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:15] R Reserved (Should be zero) 0x0 rdlvl_complete [14] R Read Level Completion 0x0 RSVD [13:4] R Reserved (Should be zero) 0x0 dfi_init_complete [3] R DFI PHY initialization complete 0 = Initialization has not been finished 1 = Initialization has been finished 0x0 RSVD [2:0] R Reserved (Should be zero) 0x0

14.4.1.1.15 ChipStatus

 Base Address: 0xC00E_0000  Address = Base Address + 0x0048, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] – Reserved (Should be zero) 0x0 chip_dpd_state [15:12] R Chip is in the deep power down state 0x0 chip_sref_state [11:8] R Chip is in the self-refresh state 0x0 chip_pd_state [7:4] R Chip is in the power down state 0x0 chip_busy_state [3:0] R Chip is in the busy state [0] = chip0 busy state [1] = chip1 busy state [2] = chip2 busy state [3] = chip3 busy state 0x0

14.4.1.1.16 MrStatus

 Base Address: 0xC00E_0000  Address = Base Address + 0x0054, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] R Reserved (Should be zero) 0x0 mr_status [7:0] R Mode Registers Status 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-51 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.17 QosControl n (n = 0 to 15)

 Base Address: 0xC00E_0000  Address = Base Address + 0x0060, + 0x0068, + 0x0070, + 0x0078, + 0x0080, + 0x0088, + 0x0090, + 0x0098, + 0x00A0, + 0x00A8, + 0x00B0, + 0x00B8, + 0x00C0, + 0x00C8, + 0x00D0, + 0x00D8  Reset Value = 0x0000_0FFF Name Bit Type Description Reset Value RSVD [31:12] RW Reserved (Should be zero) 0x0 cfg_qos [11:0] RW QoS Cycles 0xn = n MBCLK cycles The matched ARID uses this value for its timeout counters instead of ConControl.timeout_cnt. 0xFFF

14.4.1.1.18 WrTraConfig

 Base Address: 0xC00E_0000  Address = Base Address + 0x00F4, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value row_addr [31:16] RW Row Address for Write Training 0x0 RSVD [15:4] – Reserved (Should be zero) 0x0 bank [3:1] RW Bank Address for Write Training 0x0 write_training_en [0] RW Write Training Enable Use this field to issue ACT command. Before setting this field, below things should be finished. Please see PHY manual.  Set write latency before write training(PHY's control register 26)  Set write training mode(PHY's control register 2) 0x0 = Disable, 0x1 = Enable (Issue ACT command) 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-52 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.19 RdlvlConfig

 Base Address: 0xC00E_0000  Address = Base Address + 0x00F8, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:2] – Reserved (Should be zero) 0x0 ctrl_rdlvl_data_en [1] RW Data eye training enable 0x0 ctrl_rdlvl_gate_en [0] RW Gate training enable This is only valid for DDR3 case. If LPDDR2-S4/LPDDR3 is used, this field must be set to 0x0. When ctrl_rdlvl_en = 1, Read leveling offset values will be used instead of ctrl_offsetr*. If read leveling is used, this value should be high during operation. This field should be set after dfi_init_complete is asserted. 0x0 = Disable, 0x1 = Enable 0x0

14.4.1.1.20 BRBRSVCONTROL

 Base Address: 0xC00E_0000  Address = Base Address + 0x0100, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved (Should be zero) 0x0 brb_rsv_en_w3 [7] RW Enable Write-BRB reservation for AXI port 3 0x0 brb_rsv_en_w2 [6] RW Enable Write-BRB reservation for AXI port 2 0x0 brb_rsv_en_w1 [5] RW Enable Write-BRB reservation for AXI port 1 0x0 brb_rsv_en_w0 [4] RW Enable Write-BRB reservation for AXI port 0 0x0 brb_rsv_en_r3 [3] RW Enable Read-BRB reservation for AXI port 3 0x0 brb_rsv_en_r2 [2] RW Enable Read-BRB reservation for AXI port 2 0x0 brb_rsv_en_r1 [1] RW Enable Read-BRB reservation for AXI port 1 0x0 brb_rsv_en_r0 [0] RW Enable Read-BRB reservation for AXI port 0 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-53 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.21 BRBRSVCONFIG

 Base Address: 0xC00E_0000  Address = Base Address + 0x0104, Reset Value = 0x8888_8888 Name Bit Type Description Reset Value brb_rsv_th_w3 [31:28] RW Write-BRB reservation threshold for AXI port 3 Write request from AXI port3 does not serviced when Write-BRB reservation is enabled for AXI port 3 and the occupancy of corresponding Write-BRB exceeds brb_rsv_th_w3. 0x8 brb_rsv_th_w2 [27:24] RW Enable Write-BRB reservation for AXI port 2 Write request from AXI port2 does not serviced when Write-BRB reservation is enabled for AXI port 2 and the occupancy of corresponding Write-BRB exceeds brb_rsv_th_w2. 0x8 brb_rsv_th_w1 [23:20] RW Enable Write-BRB reservation for AXI port 1 Write request from AXI port1 does not serviced when Write-BRB reservation is enabled for AXI port 1 and the occupancy of corresponding Write-BRB exceeds brb_rsv_th_w1. 0x8 brb_rsv_th_w0 [19:16] RW Enable Write-BRB reservation for AXI port 0 Write request from AXI port0 does not serviced when Write-BRB reservation is enabled for AXI port 0 and the occupancy of corresponding Write-BRB exceeds brb_rsv_th_w0. 0x8 brb_rsv_th_r3 [15:12] RW Enable Read-BRB reservation for AXI port 3 Read request from AXI port3 does not serviced when Read-BRB reservation is enabled for AXI port 3 and the occupancy of corresponding Read-BRB exceeds brb_rsv_th_w3. 0x8 brb_rsv_th_r2 [11:8] RW Enable Read-BRB reservation for AXI port 2 Read request from AXI port2 does not serviced when Read-BRB reservation is enabled for AXI port 2 and the occupancy of corresponding Read-BRB exceeds brb_rsv_th_w2. 0x8 brb_rsv_th_r1 [7:4] RW Enable Read-BRB reservation for AXI port 1 Read request from AXI port1 does not serviced when Read-BRB reservation is enabled for AXI port 1 and the occupancy of corresponding Read-BRB exceeds brb_rsv_th_w1. 0x8 brb_rsv_th_r0 [3:0] RW Enable Read-BRB reservation for AXI port 0 Read request from AXI port0 does not serviced when Read-BRB reservation is enabled for AXI port 0 and the occupancy of corresponding Read-BRB exceeds brb_rsv_th_w0. 0x8 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-54 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.22 BRBQOSCONFIG

 Base Address: 0xC00E_0000  Address = Base Address + 0x0108, Reset Value = 0x0000_0010 Name Bit Type Description Reset Value RSVD [31:12] R Reserved (Should be zero) 0x0 brb_qos_timer_dec [11:0] RW BRB timer decrementing size for QoS. The timer for request in BRB decreases by brb_qos_timer_dec for the following cases.  When the BRB is full  When the request is from the AXI port whose data buffer is full. 0x10

14.4.1.1.23 MemBaseConfig0

 Base Address: 0xC00E_0000  Address = Base Address + 0x010C, Reset Value = 0x0020_07F8 Name Bit Type Description Reset Value RSVD [31:27] – Reserved (Should be zero) 0x0 chip_base [26:16] RW AXI Base Address AXI base address [34:24] = chip_base, For example, if chip_base = 0x20, then AXI base address of memory chip0 becomes 0x2000_0000. 0x20 RSVD [15:11] – Reserved (Should be zero) 0x0 chip_mask [10:0] RW AXI Base Address Mask Upper address bit mask to determine AXI offset address of memory chip0. 0 = Corresponding address bit is not to be used for comparison 1 = Corresponding address bit is to be used for comparison For example, if chip_mask = 0x7F8, then AXI offset address be-comes 0x0000_0000 ~ 0x07FF_FFFF. If AXI base address of memory chip0 is 0x2000_0000, then memory chip0 has an ad-dress range of 0x2000_0000 ~ 0x27FF_FFFF. 0x7F8 NOTE: DRAM Start Address: 0x0000_0000 DRAM End Address: 0x7FFF_FFFF cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-55 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.24 MemBaseConfig1

 Base Address: 0xC00E_0000  Address = Base Address + 0x0110, Reset Value = 0x0020_07F8 Name Bit Type Description Reset Value RSVD [31:27] – Reserved (Should be zero) 0x0 chip_base [26:16] RW AXI Base Address AXI base address [34:24] = chip_base, For example, if chip_base = 0x20, then AXI base address of memory chip0 becomes 0x2000_0000. 0x20 RSVD [15:11] – Reserved (Should be zero) 0x0 chip_mask [10:0] RW AXI Base Address Mask Upper address bit mask to determine AXI offset address of memory chip0. 0 = Corresponding address bit is not to be used for comparison 1 = Corresponding address bit is to be used for comparison For example, if chip_mask = 0x7F8, then AXI offset address be-comes 0x0000_0000 ~ 0x07FF_FFFF. If AXI base address of memory chip0 is 0x2000_0000, then memory chip0 has an ad-dress range of 0x2000_0000 ~ 0x27FF_FFFF. 0x7F8 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-56 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.25 WRLVLCONFIG0

 Base Address: 0xC00E_0000  Address = Base Address + 0x0120, Reset Value = 0x0000_0010 Name Bit Type Description Reset Value RSVD [31:8] – Reserved (Should be zero) 0x0 t_wlo [7:4] RW Write Leveling Ouput Delay t_wlo * T(MPCLK) should be greater than or equal to the minimum value of memory tWLO and the minimum value is 1. 0x1 RSVD [3:1] – Reserved (Should be zero) 0x0 odt_on [0] RW Turn On ODT for Write Leveling 0x0 = ODT Turn off 0x1 = ODT Turn on, This field is only for write leveling. Turn on before write leveling and turn off after write leveling is finished. Write leveling procedure is MRS for Write leveling - ODT on - wrlvl_wrdata_en - Read ctrl_io_rdata - Change SDLL code of PHY. Refer to PHY manual for details. 0x0

14.4.1.1.26 WRLVLCONFIG1

 Base Address: 0xC00E_0000  Address = Base Address + 0x0124, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:1] – Reserved (Should be zero) 0x0 wrlvl_wrdata_en [0] RW Generate dfi_wrdata_en_p0 for Write Leveling Generate 1cycle pulse of dfi_wrdata_en_p0 for write leveling. Write leveling is supported in DDR3 and LPDDR3. NOTE: That if S/W write this field to 1 then, 1 cycle pulse of dfi_wrdata_en_p0 would be generated. Refer to PHY manual for write leveling. 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-57 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.27 WRLVLSTATUS

 Base Address: 0xC00E_0000  Address = Base Address + 0x0128, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:5] RW Reserved (Should be zero) 0x0 wrlvl_fsm [4:0] R Write Leveling Status 5'b0_0001: FSM IDLE 5'b0_0010: FSM_SETUP 5'b0_0100: FSM_ACCESS 5'b0_1000: FSM_DONE 5'b1_0000: FSM_TWLO wrlvl_eq is valid only when wrlvl_fsm is FSM_IDLE. Refer to PHY manual for write leveling. 0x0

14.4.1.1.28 CTRL_IO_RDATA

 Base Address: 0xC00E_0000  Address = Base Address + 0x0150, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ctrl_io_rdata [31:0] R ctrl_io_rdata from PHY 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-58 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.29 CACAL_CONFIG0

 Base Address: 0xC00E_0000  Address = Base Address + 0x0160, Reset Value = 0x003F_F010 Name Bit Type Description Reset Value dfi_address_p0 [31:12] RW dfi_address_p0 value for CA Calibration This value would be the expected value for comparing the address pattern received from memory. 0x3FF RSVD [11:8] RW Reserved (Should be zero) 0x0 t_adr [7:4] RW CSN Low to Data Output Delay t_adr * T(MPCLK) should be greater than or equal to the min-imum value of memory tADR and the minimum value is 1. 0x1 RSVD [3:1] – Reserved (Should be zero) 0x0 deassert_cke [0] RW Deassert CKE for CA Calibration 0x0 = Put CKE pin to normal operation 0x1 = Put CKE pin to low This field is only for CA calibration. De-assert CKE before CA calibration and put to normal operation after CA calibration is finished. CA calibration procedure is MRS for CA calibration - De- assert CKE - cacal_csn - Read ctrl_io_rdata - Change SDLL code of PHY. Refer to PHY manual for details. 0x0

14.4.1.1.30 CACAL_CONFIG1

 Base Address: 0xC00E_0000  Address = Base Address + 0x0164, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:1] RW Reserved (Should be zero) 0x0 cacal_csn [0] RW Generate dfi_csn_p0 for CA Calibration Generate 1cycle pulse of dfi_csn_p0 for CA calibration. CA calibration is supported in LPDDR3. NOTE: That if S/W writes this field to 1 then, 1 cycle pulse of dfi_csn_p0 would be generated. Refer to PHY manual for CA calibration. 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-59 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.1.31 CACAL_STATUS

 Base Address: 0xC00E_0000  Address = Base Address + 0x0168, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:5] R Should be zero 0x0 cacal_fsm [4:0] R Write Leveling Status 5'b0_0001: FSM IDLE 5'b0_0010: FSM_SETUP 5'b0_0100: FSM_ACCESS 5'b0_1000: FSM_DONE 5'b1_0000: FSM_TADR CTRL_IO_RDATA are valid only when wrlvl_fsm is FSM_IDLE. Refer to PHY manual for CA calibration. 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-60 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2 DDRPHY Register

14.4.1.2.1 PHY_CON0

 Base Address: 0xC00E_1000  Address = Base Address + 0x00, Reset Value = 0x1702_0240 Name Bit Type Description Reset Value RSVD [31:29] R Reserved for future use. This Value has no affect at current system 0 T_WrWrCmd [28:24] RW It controls the interval between Write and Write during DQ Calibration. This value should be always kept by 5'h17. It will be used for debug purpose 5'h17 RSVD [23:22] RW Reserved for future use. This Value has no affect at current system 2'b00 ctrl_upd_range [21:20] RW It decides how many differences between the new lock value and the current lock value which is used in Slave- DLL is needed for updating lock value. 2'b00 = To update always 2'b01 = To ignore the lower 1 bit in ctrl_lock_value 2'b10 = To ignore the lower 2 bits in ctrl_lock_value 2'b11 = To ignore the lower 3 bits in ctrl_lock_value 2'b00 T_WrRdCmd [19:17] RW It controls the interval between Write and Read by cycle unit during Write Calibration. It will be used for debug purpose. 3'b110 = tWTR = 4 cycles 3'b111 = tWTR = 6 cycles 3'b001 ctrl_wrlvl_en (=wrlvl_mode) [16] RW Write Leveling Enable 1'b0 RSVD [15] RW Reserved for future use. This Value has no affect at current system 1'b0 p0_cmd_en [14] RW 1'b0 = Issue Phase1 Read Command during read leveling 1'b1 = Issue Phase0 Read Command during read leveling 1'b0 byte_rdlvl_en [13] RW Byte Read Leveling enable. It should be set if memory supports toggling only 1 DQ bit except for other 7 bits during read leveling 1'b0 ctrl_ddr_mode [12:11] RW 2'b00 = DDR2 and LPDDR1 2'b01 = DDR3 2'b10 = LPDDR2 2'b11 = LPDDR3 1'b0 RSVD [10] RW Reserved for future use. This Value has no affect at current system 1'b0 ctrl_dfdqs [9] RW 1'b0 = Single-ended DQS 1'b1 = Differential DQS 1'b1 ctrl_shgate [8] RW This field controls the gate control signal 1'b0 = Gate signal length = “burst length / 2” + N (DQS 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-61 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Pull-Down mode, ctrl_pulld_dqs[3:0] == 4'b1111, N = 0,1,2…) 1'b1 = Gate signal length = “burst length / 2” - 1 ctrl_ckdis [7] RW This field controls the CK/CKB 1'b0 = Clock output is enabled 1'b1 = Clock output is disabled 1'b0 ctrl_atgate [6] RW If ctrl_atgate=0, Controller should generate ctrl_gate_p*, ctrl_read_p*. If ctrl_atgate=1, PHY will generate ctrl_gate_p*, ctrl_read_p*, but it has some constraints. This setting can be supported only over RL=4, BL and RL should be properly set to operate with ctrl_atgate=1. 1'b1 ctrl_read_disable [5] RW Read ODT (On-Die-Termination) Disable Signal. This signal should be one in LPDDR2 or LPDDR3 mode. 1'b0 = drive ctrl_read_p* normally 1'b1 = drive ctrl_read_p* to 0. (If using LPDDR2 or LPDDR3, ctrl_read_p* will be always 0 by enabling this field.) 1'b0 ctrl_cmosrcv [4] RW This field controls the input mode of I/O 1'b0 = Differential receiver mode for high speed operation 1'b1 = CMOS receiver mode for low speed operation (<

200 MHz)

1'b0 ctrl_read_width [3] RW The default is 1'b0. We strongly recommend that it should have one more idle cycle between read and write because the variation of data arrival time during read can be greater than 1 cycle. If it is 1'b1, the package and board should be carefully optimized with a short length and it should be used at the low frequency. 1'b0 = Termination on period is (BL/2+1.5) cycle (Default) 1'b1 = Termination on period is (B/2+1) cycle(Not recommended) 1'b0 ctrl_fnc_fb [2:0] RW Valid only when {mode_phy, mode_nand, mode_scan, mode_mux} is 4'b00000. For normal operation 3'b000 = Normal operation mode. For ATE test purpose 3'b010 = External FNC read feedback test mode. 3'b011 = Internal FNC read feedback test mode. For Board test purpose 3'b100 = External PHY read feedback test mode. When memory is not attached on the board 3'b101 = Internal PHY read feedback test mode. mode_highz should be set. 3'b110 = Internal PHY write feedback test mode. 3'b000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-62 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value mode_highz should be set. For Power Down 3'b111 = Power Down Mode for SSTL I/O cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-63 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.2 PHY_CON1

 Base Address: 0xC00E_1000  Address = Base Address + 0x04, Reset Value = 0x0921_0100 Name Bit Type Description Reset Value ctrl_gateadj [31:28] RW It adjusts the enable time of "ctrl_gate" on a clock cycle base. MSB (bit[3]) controls direction: 1'b1(subtract delay), 1'b0(add delay), Bit[2:0] set delay value 4'h0 ctrl_readadj [27:24] RW It adjusts the enable time of "ctrl_read" on a clock cycle base. MSB (bit[3]) controls direction: 1'b1(subtract delay), 1'b0(add delay), Bit[2:0] set delay value 4'h9 ctrl_gateduradj [23:20] RW It adjusts the duration cycle of "ctrl_gate" on a clock cycle base. MSB (bit[3]) controls direction: 1'b1(subtract delay), 1'b0(add delay), Bit[2:0] set delay value 4'h2 rdlvl_pass_adj [19:16] RW This field controls how many times "Read" should be operated well to determine if it goes into VWP (Valid Window Period) or not. (default: 4'h1) 4'h1 rdlvl_rddata_adj [15:0] RW It decides the pattern to be read during read or write calibration. (default: 16'h0100) 16'h0100 = DDR3 ("byte_rdlvl_en=1") 16'h0001 = LPDDR3 ("byte_rdlvl_en=1") 16'h0100 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-64 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.3 PHY_CON2

 Base Address: 0xC00E_1000  Address = Base Address + 0x08, Reset Value = 0x0001_0004 Name Bit Type Description Reset Value ctrl_readduradj [31:28] RW It adjusts the duration cycle of "ctrl_read" on a clock cycle base. MSB(bit3) controls direction: 1'b1(subtract delay), 1'b0(add delay), Bit[2:0] set delay value wr_deskew_en [27] RW DQ Calibration Start Signal to align DQ, DM during write 1'b0 wr_deskew_con [26] RW If it is enabled, PHY will use "Write Slave DLL Code" which has got during Read Leveling. 1'b0 rdlvl_en [25] RW When rd_cal_mode=1, Read leveling offset values will be used instead of ctrl_offsetr*. If read leveling is used, this value should be high during operation. 1'b0 rdlvl_gate_en [24] RW When gate_cal_mode=1, Gate leveling offset value will be used instead of ctrl_shiftc*. If gate leveling is used, this value should be high during operation 1'b0 rdlvl_ca_en [23] RW When ca_cal_mode=1, CA Calibration offset value will be used and updated 1'b0 rdlvl_incr_adj [22:16] RW It decides the step value of delay line to increase during read leveling (default: 7'h1, fine step delay). It should be smaller than 7'hf [22:21]=2'b00 : The step value will be "rdlvl_incr_adj[20:16]" [22:21]=2'b01 : The step value will be "T/16" [22:21]=2'b10 : The step value will be "T/32" [22:21]=2'b11 : The step value will be "T/64" 7'b1 RSVD [15] R Reserved (Should be zero) – WrDeskew_clear [14] RW Clear WrDeSkewCode after Write De-skewing 1'b0 RdDeskew_clear [13] RW Clear RdDeSkewCode after Read De-skewing 1'b0 DLLDeskewEn [12] RW Deskew Code is updated with the latest Master DLL lock value whenever "dfi_ctrlupd_req" is issued from controller during DLLDeskewEn=1. It is required to compensate On- chip VT variation 1'b0 rdlvl_start_adj [11:8] RW It decides the most left-shifted point when read leveling is started and the most right-shifted point when read leveling is ended. [9:8]=2'b00 : The most left-shifted code is 8'h00 [9:8]=2'b01 : The most left-shifted code is T/8 [9:8]=2'b10 : The most left-shifted code is T/8+T/16 [9:8]=2'b11 : The most left-shifted code is T/8-T/16 [11:10]=2'b00 : The most right-shifted Code is 8'hFF [11:10]=2'b01 : The most right-shifted Code is T/2+T/8 [11:10]=2'b10 : The most right-shifted Code is T/2+T/8+T/16 4'h0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-65 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value [11:10]=2'b11 : The most right-shifted Code is T/2+T/8- T/16 RSVD [7] RW Reserved (Should be zero) – InitDeskewEn [6] RW This field should be enabled before DQ Calibration is started 1'b0 RSVD [5:2] R Reserved (Should be zero) – rdlvl_gateadj [1:0] RW It determines how much earlier ctrl_gate* is asserted than RDQS when the transition of RDQS is detected. [1:0]=2'b00 : T/2(default) [1:0]=2'b01 : T/4 2'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-66 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.4 PHY_CON3

 Base Address: 0xC00E_1000  Address = Base Address + 0x0C, Reset Value = 0x0021_0842 Name Bit Type Description Reset Value RSVD [31:18] R Reserved (Should be zero) - ctrl_shiftc3 [17:15] RW GATEin signal delay amount for DDR. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. This value is limited by the half of the maximum delay in Master Delay Line. GATEin signal will be delayed by T/16 whenever it increases one. 000 = 0 (0° shift), 001 = T (365° shift), 010 = T/2 (180° shift), 011 = T/4 (90° shift) 100 = T/8 (45° shift), 101 = T/16 (22.5° shift) 3'b010 RSVD [14:13] R Reserved (Should be zero) - ctrl_shiftc2 [12:10] RW GATEin signal delay amount for DDR. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. This value is limited by the half of the maximum delay in Master Delay Line. GATEin signal will be delayed by T/16 whenever it increases one. 000 = 0 (0° shift), 001 = T (365° shift), 010 = T/2 (180° shift), 011 = T/4 (90° shift) 100 = T/8 (45° shift), 101 = T/16 (22.5° shift) 3'b010 RSVD [9:8] R Reserved (Should be zero) - ctrl_shiftc1 [7:5] RW GATEin signal delay amount for DDR. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. This value is limited by the half of the maximum delay in Master Delay Line. GATEin signal will be delayed by T/16 whenever it increases one. 000 = 0 (0° shift), 001 = T (365° shift), 010 = T/2 (180° shift), 011 = T/4 (90° shift) 100 = T/8 (45° shift), 101 = T/16 (22.5° shift) 3'b010 RSVD [4:3] R Reserved (Should be zero) - cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-67 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value ctrl_shiftc0 [2:0] RW GATEin signal delay amount for DDR. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. This value is limited by the half of the maximum delay in Master Delay Line. GATEin signal will be delayed by T/16 whenever it increases one. 000 = 0 (0° shift), 001 = T (365° shift), 010 = T/2 (180° shift), 011 = T/4 (90° shift) 100 = T/8 (45° shift), 101 = T/16 (22.5° shift) 3'b010 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-68 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.5 PHY_CON4

 Base Address: 0xC00E_1000  Address = Base Address + 0x10, Reset Value = 0x0808_0808 Name Bit Type Description Reset Value ctrl_offsetr3 [31:24] RW This field can be used to give offset to read DQS. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. The right-shifted value is limited by the quarter of the maximum delay in Master Delay Line. Read DQS offset amount:  ctrl_offsetr3[7] = 1: (tFS: fine step delay)  Read DQS 90° delay amount - ctrl_offsetr3[6:0]  tFS  ctrl_offsetr3[7] = 0: (tFS: fine step delay)  Read DQS 90° delay amount + ctrl_offsetr3[6:0]  tFS 8'h8 ctrl_offsetr2 [23:16] RW This field can be used to give offset to read DQS. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. The right-shifted value is limited by the quarter of the maximum delay in Master Delay Line. Read DQS offset amount:  ctrl_offsetr2[7] = 1: (tFS: fine step delay)  Read DQS 90° delay amount - ctrl_offsetr2[6:0]  tFS  ctrl_offsetr2[7] = 0: (tFS: fine step delay)  Read DQS 90° delay amount + ctrl_offsetr2[6:0]  tFS 8'h8 ctrl_offsetr1 [15:8] RW This field can be used to give offset to read DQS. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. The right-shifted value is limited by the quarter of the maximum delay in Master Delay Line. Read DQS offset amount:  ctrl_offsetr1[7] = 1: (tFS: fine step delay)  Read DQS 90° delay amount - ctrl_offsetr1[6:0]  tFS  ctrl_offsetr1[7] = 0: (tFS: fine step delay)  Read DQS 90° delay amount + ctrl_offsetr1[6:0]  tFS 8'h8 ctrl_offsetr0 [7:0] RW This field can be used to give offset to read DQS. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. The right-shifted value is limited by the quarter of the maximum delay in Master Delay Line. Read DQS offset amount:  ctrl_offsetr0[7] = 1: (tFS: fine step delay)  Read DQS 90° delay amount - ctrl_offsetr0[6:0]  tFS  ctrl_offsetr0[7] = 0: (tFS: fine step delay)  Read DQS 90° delay amount + ctrl_offsetr0[6:0]  tFS 8'h8 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-69 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.6 PHY_CON5

 Base Address: 0xC00E_1000  Address = Base Address + 0x14, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] R Reserved (Should be zero) 2'h0 readmodecon [7:0] RW Read Register Mode Control After Gate Leveling,  When ReadModeCon[7:0]='hD, Check "Gate Cycle"(0x50)  When ReadModeCon[7:0]='hE, Check "Gate Code"(0x50)  After Read Calibration,  When ReadModeCon[7:0]='h05, Check "VWML"(0x50)  When ReadModeCon[7:0]='h06, Check "VWMR"(0x50)  When ReadModeCon[7:0]='h07, Check "VWMC"(0x50)  When ReadModeCon[7:0]='h08, Check "VWMC"(0x50)  When ReadModeCon[7:0]='h01, Check "De-skew Code"(0x50)  After Write Calibration,  When ReadModeCon[7:0]='h05, Check "VWML"(0x50)  When ReadModeCon[7:0]='h06, Check "VWMR"(0x50)  When ReadModeCon[7:0]='h07, Check "VWMC"(0x50)  When ReadModeCon[7:0]='h09, Check "VWMC"(0x50)  When ReadModeCon[7:0]='h03, Check "De-skew Code"(0x50) NOTE: The result of VWM* will be over-written after each calibration. Check PHY_CON18 (=0x50) according to ReadModeCon[7:0]. 8'h0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-70 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.7 PHY_CON6

 Base Address: 0xC00E_1000  Address = Base Address + 0x18, Reset Value = 0x0808_0808 Name Bit Type Description Reset Value ctrl_offsetw3 [31:24] RW This field can be used to give offset to write DQ. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. The right-shifted value is limited by the quarter of the maximum delay in Master Delay Line. Write DQ offset amount :  ctrl_offsetw3[7] = 1 : (tFS: fine step delay)  Write DQ 270° delay amount - ctrl_offsetw3[6:0]  tFS  ctrl_offsetw3[7] = 0 : (tFS: fine step delay)  Write DQ 270° delay amount + ctrl_offsetw3[6:0] x tFS 0x8 ctrl_offsetw2 [23:16] RW This field can be used to give offset to write DQ. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. The right-shifted value is limited by the quarter of the maximum delay in Master Delay Line. Write DQ offset amount :  ctrl_offsetw2[7] = 1 : (tFS: fine step delay)  Write DQ 270° delay amount - ctrl_offsetw2[6:0]  tFS  ctrl_offsetw2[7] = 0 : (tFS: fine step delay)  Write DQ 270° delay amount + ctrl_offsetw2[6:0] x tFS 0x8 ctrl_offsetw1 [15:8] RW This field can be used to give offset to write DQ. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. The right-shifted value is limited by the quarter of the maximum delay in Master Delay Line. Write DQ offset amount :  ctrl_offsetw1[7] = 1 : (tFS: fine step delay)  Write DQ 270° delay amount - ctrl_offsetw1[6:0]  tFS  ctrl_offsetw1[7] = 0 : (tFS: fine step delay)  Write DQ 270° delay amount + ctrl_offsetw1[6:0] x tFS 0x8 ctrl_offsetw0 [7:0] RW This field can be used to give offset to write DQ. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. The right-shifted value is limited by the quarter of the maximum delay in Master Delay Line. Write DQ offset amount :  ctrl_offsetw0[7] = 1 : (tFS: fine step delay)  Write DQ 270° delay amount - ctrl_offsetw0[6:0]  tFS  ctrl_offsetw0[7] = 0 : (tFS: fine step delay)  Write DQ 270° delay amount + ctrl_offsetw0[6:0] x tFS 0x8 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-71 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.8 PHY_CON8

 Base Address: 0xC00E_1000  Address = Base Address + 0x20, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ctrl_offsetc3 [31:24] RW Gate offset amount for DDR. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. ctrl_offsetc [7] = 1 : (tFS: fine step delay) GATEout delay amount - ctrl_offsetc [6:0] x tFS ctrl_offsetc [7] = 0 : (tFS: fine step delay) GATEout delay amount + ctrl_offsetc [6:0] x tFS 0x0 ctrl_offsetc2 [23:16] RW Gate offset amount for DDR. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. ctrl_offsetc [7] = 1 : (tFS: fine step delay) GATEout delay amount - ctrl_offsetc [6:0] x tFS ctrl_offsetc [7] = 0 : (tFS: fine step delay) GATEout delay amount + ctrl_offsetc [6:0] x tFS 0x0 ctrl_offsetc1 [15:8] RW Gate offset amount for DDR. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. ctrl_offsetc [7] = 1 : (tFS: fine step delay) GATEout delay amount - ctrl_offsetc [6:0] x tFS ctrl_offsetc [7] = 0 : (tFS: fine step delay) GATEout delay amount + ctrl_offsetc [6:0] x tFS 0x0 ctrl_offsetc0 [7:0] RW Gate offset amount for DDR. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. ctrl_offsetc [7] = 1 : (tFS: fine step delay) GATEout delay amount - ctrl_offsetc [6:0] x tFS ctrl_offsetc [7] = 0 : (tFS: fine step delay) GATEout delay amount + ctrl_offsetc [6:0] x tFS 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-72 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.9 PHY_CON9

 Base Address: 0xC00E_1000  Address = Base Address + 0x24, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:8] – Reserved (Should be zero) 0x0 ctrl_offsetc4 (40-bit) [7:0] RW Gate offset amount for DDR. If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. ctrl_offsetc [7] = 1 : (tFS: fine step delay) GATEout delay amount - ctrl_offsetc [6:0] x tFS ctrl_offsetc [7] = 0 : (tFS: fine step delay) GATEout delay amount + ctrl_offsetc [6:0] x tFS 0x0

14.4.1.2.10 PHY_CON10

 Base Address: 0xC00E_1000  Address = Base Address + 0x28, Reset Value = 0x0000_0008 Name Bit Type Description Reset Value RSVD [31:25] – Reserved (Should be zero) 0x0 ctrl_resync [24] RW Active RISIG-EDGE signal. This signal should become LOW after set HIGH for normal operation. When this bit transits from LOW to HIGH, pointers of FIFO and DLL information is updated. In general, this bit should be set during initialization and refresh cycles. Refer to "MC- Initiated Update"(p105) to use ctrl_resync. 0x0 RSVD [23:8] – Reserved (Should be zero) 0x0 ctrl_offsetd [7:0] RW This field is for debug purpose. (For LPDDR2) If this field is fixed, this should not be changed during operation. This value is valid only after dfi_ctrlupd_req becomes HIGH and LOW. The right-shifted value is limited by the quarter of the maximum delay in Master Delay Line. offset amount for 270° clock generation: ctrl_offsetd[7] = 1 : (tFS: fine step delay) 270° delay amount - ctrl_offsetd[6:0] x tFS ctrl_offsetd[7] = 0 : 270° delay amount + ctrl_offsetd[6:0] x tFS 0x8 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-73 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.11 PHY_CON12

 Base Address: 0xC00E_1000  Address = Base Address + 0x30, Reset Value = 0x1010_0070 Name Bit Type Description Reset Value RSVD [31] – Reserved (Should be zero) 0x0 ctrl_start_point [30:24] RW Initial DLL lock start point. This is the number of delay cells and is the start point where "DLL" start tracing to be locked. Initial delay time is calculated by multiplying the unit delay of delay cell and this value. 7'h10 RSVD [23] – Reserved (Should be zero) 0x0 ctrl_inc [22:16] RW Increase amount of start point 7'h10 ctrl_force [14:8] RW This field is used instead of ctrl_lock_value[9:2] found by the DLL only when ctrl_dll_on is LOW ,i.e. If the DLL is off, this field is used to generate 270° clock and shift DQS by 90°. 0x0 ctrl_start [6] RW This field is used to start DLL locking. 0'b1 ctrl_dll_on [5] RW HIGH active start signal to turn on the DLL. This signal should be kept HIGH for normal operation. If this signal becomes LOW, DLL is turned off. This bit should be kept set before ctrl_start is set to turn on the DLL. 0'b1 ctrl_ref [4:1] RW This field determines the period of time when ctrl_locked is cleared. 4'b0000 = Don't use. 4'b0001 = ctrl_flock is de-asserted during 16 clock cycles, ctrl_locked is deasserted. 4'b0010 = ctrl_flock is de-asserted during 24 clock cycles, ctrl_locked is deasserted. 4'b1110 = ctrl_flock is de-asserted during 120 clock cycles, ctrl_locked is deasserted. 4'b1111 = Once ctrl_locked and dfi_init_complete are asserted, those won't be deasserted until rst_n is asserted. 4'h8 RSVD [0] – Reserved (Should be zero) 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-74 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.12 PHY_CON13

 Base Address: 0xC00E_1000  Address = Base Address + 0x34, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [31:17] R Reserved (Should be zero) – ctrl_lock_value [16:8] RW Locked delay line encoding value. ctrl_lock_value[8:2] : number of delay cells for coarse lock. ctrl_lock_value[1:0] : control value for fine lock. From ctrl_lock_value[8:0], tFS(fine step delay) can be calculated. tFS = tCK / ctrl_lock_value[9:0]. ctrl_clock [2] R Coarse lock information. According to clock jitter, ctrl_clock can be de-asserted. – ctrl_flock [1] R Fine lock information. According to clock jitter, ctrl_flock can be de-asserted. – ctrl_locked [0] R DLL stable lock information. This field is set after ctrl_flock is set. This field is cleared when ctrl_flock is de-asserted for some period of time specified by ctrl_ref[3:0] value. This field is required for stable lock status check.

14.4.1.2.13 PHY_CON14

 Base Address: 0xC00E_1000  Address = Base Address + 0x38, Reset Value = 0x001F_0000 Name Bit Type Description Reset Value RSVD [31:12] R Reserved (Should be zero) – ctrl_pulld_dq [11:8] RW Active HIGH signal to down DQ signals. For normal operation this field should be zero. When bus is idle, it can be set to pull-down or up the bus not to make bus high-z state. 4'h0 ctrl_pulld_dqs [3:0] RW Active HIGH signal to pull-up or down PDQS/NDQS signals. When using Gate Leveling in DDR3, this field can be zero. When bus is idle, it can be set to pull-down or up the bus not to make bus high-z state (PDQS/NDQS is pulled- down/up). For LPDDR2/LPDDR3 mode, this field should be always set for normal operation to make P/NDQS signals pull-down/up. 4'h0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-75 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.14 PHY_CON15

 Base Address: 0xC00E_1000  Address = Base Address + 0x3C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:21] R Reserved (Should be zero) – ctrl_fb_err [20:16] R Feedback test stop with error for each slice. Ctrl_fb_err[0]: error of data channel0. Ctrl_fb_err[1]: error of data channel1. Ctrl_fb_err[2]: error of data channel2 for 32-bit PHY. Error of control for 16-bit PHY. Ctrl_fb_err[3]: error of data channel3 for 32-bit PHY. Ctrl_fb_err[4]: error of control channel for 32-bit PHY. 5'h0 ctrl_fb_okay [12:8] R Feedback test completion without error for each slice. Ctrl_fb_oky[0]: okay of data channel0. Ctrl_fb_oky[1]: okay of data channel1. Ctrl_fb_oky[2]: okay of data channel2 for 32-bit PHY. Okay of control channel for 16-bit PHY. Ctrl_fb_oky[3]: okay of data channel3 for 32-bit PHY. Ctrl_fb_oky[4]: okay of control channel for 32-bit PHY. 5'h0 ctrl_fb_start [4:0] RW Feedback test start signal for each slice. Ctrl_fb_start[0]: start of data channel0 ctrl_fb_start[1]: start of data channel1 ctrl_fb_start[2]: start of data channel2 for 32-bit PHY start of control channel for 16-bit PHY ctrl_fb_start[3]: start of data channel3 for 32-bit PHY. Ctrl_fb_start[4]: start of control channel for 32-bit PHY. For this test, mode_highz should be set when memory is on the board 5'h0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-76 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.15 PHY_CON16

 Base Address: 0xC00E_1000  Address = Base Address + 0x40, Reset Value = 0x0800_0304 Name Bit Type Description Reset Value RSVD [31:28] RW Reserved (Should be zero) 0x0 zq_clk_en [27] RW ZQ I/O Clock enable 1'b1 zq_mode_dds [26:24] RW Driver strength selection. It recommends one of the following settings instead of 3'h0. 3'b100 = 48 Impedance output driver 3'b101 = 40 Impedance output driver 3'b110 = 34 Impedance output driver 3'b111 = 30 Impedance output driver 3'h0 zq_mode_term [23:21] RW On-die-termination(ODT) resistor value selection. "pblpddr3_dds" and "pblpddr3_dqs_dds" don't support ODT. 3'b001 = 120 Receiver termination 3'b010 = 60 Receiver termination 3'b011 = 40 Receiver termination 3'b100 = 30 Receiver termination 3'h0 zq_rgddr3 [20] RW GDDR3 mode enable signal(High: GDDR3 mode) 1'b0 zq_mode_noterm [19] RW Termination disable selection. 0 = Termination enable. 1 = Termination disable. DDR : 1'b1 DDR2/DDR3 : 1'b0(recommended) or 1'b1(when termination is not used) LPDDR2/LPDDR3 : 1'b1 gDDR3 : 1'b0 1'b0 zq_clk_div_en [18] RW Clock dividing enable 1'b0 zq_force_impn [17:15] RW Immediate control code for pull-down. 3'h0 zq_force_impp [14:12] RW Immediate control code for pull-up. 3'h0 zq_udt_dly [11:4] RW ZQ I/O clock enable duration for auto calibration mode. 8'h30 zq_manual_mode [3:2] RW Manual calibration mode selection 2'b00 = Force calibration 2'b01 = Long calibration 2;b10 = Short calibration 2'b01 zq_manual_str [1] RW Manual calibration start 1'b0 zq_auto_en [0] RW Auto calibration enable 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-77 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.16 PHY_CON17

 Base Address: 0xC00E_1000  Address = Base Address + 0x48, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [31:9] RW Reserved (Should be zero) 0x0 zq_pmon [8:6] R Control code found by auto calibration for pull-up. – zq_nmon [5:3] R Control code found by auto calibration for pull-down. – zq_error [2] R Calibration fail indication (High: calibration failed) – zq_pending [1] R Auto calibration enable status – zq_done [0] R ZQ Calibration is finished. 1'b0

14.4.1.2.17 PHY_CON18

 Base Address: 0xC00E_1000  Address = Base Address + 0x4C, Reset Value = 0x0055_5555 Name Bit Type Description Reset Value RSVD [31:28] R Reserved (Should be zero) 0x0 dm_fail_status [27:24] R It will be enabled if there is no pass period after DM Calibration. It should be read by zero if Calibration is done normally. Please refer to ReadModeCon (=PHY_CON5) to read. 0x0 T3_rddata_en [23:18] R Trddata_en timing parameter for data slice 3. Please refer to ReadModeCon (=PHY_CON5) to read. 0x15 T2_rddata_en [17:12] R Trddata_en timing parameter for data slice 2. Please refer to ReadModeCon (=PHY_CON5) to read. 0x15 T1_rddata_en [11:6] R Trddata_en timing parameter for data slice 1. Please refer to ReadModeCon (=PHY_CON5) to read. 0x15 T0_rddata_en [5:0] R Trddata_en timing parameter for data slice 0. Please refer to ReadModeCon (=PHY_CON5) to read. 0x15 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-78 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.18 PHY_CON19

 Base Address: 0xC00E_1000  Address = Base Address + 0x50, Reset Value = Undefined Name Bit Type Description Reset Value rdlvl_offsetr3 [31:24] R DQ Calibration SDLL code for data slice 3. Please refer to ReadModeCon(=PHY_CON5) to read. – rdlvl_offsetr2 [23:16] R DQ Calibration SDLL code for data slice 2. Please refer to ReadModeCon(=PHY_CON5) to read. – rdlvl_offsetr1 [15:8] R DQ Calibration SDLL code for data slice 1. Please refer to ReadModeCon(=PHY_CON5) to read. – rdlvl_offsetr0 [7:0] R DQ Calibration SDLL code for data slice 0. Please refer to ReadModeCon(=PHY_CON5) to read. –

14.4.1.2.19 PHY_CON20

 Base Address: 0xC00E_1000  Address = Base Address + 0x54, Reset Value = Undefined Name Bit Type Description Reset Value rdlvl_offsetc3 [31:24] R Gate Training SDLL code for data slice 3. Please refer to ReadModeCon(=PHY_CON5) to read. – rdlvl_offsetc2 [23:16] R Gate Training SDLL code for data slice 2. Please refer to ReadModeCon(=PHY_CON5) to read. – rdlvl_offsetc1 [15:8] R Gate Training SDLL code for data slice 1. Please refer to ReadModeCon(=PHY_CON5) to read. – rdlvl_offsetc0 [7:0] R Gate Training SDLL code for data slice 0. Please refer to ReadModeCon(=PHY_CON5) to read. –

14.4.1.2.20 PHY_CON21

 Base Address: 0xC00E_1000  Address = Base Address + 0x58, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value vwm_fail_status [31:0] R It will be enabled if there is no pass period after DQ Calibration. It should be read by zero if Calibration is done normally. Please refer to ReadModeCon (=PHY_CON5) to read. 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-79 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.21 PHY_CON22

 Base Address: 0xC00E_1000  Address = Base Address + 0x5C, Reset Value = 0x0000_0208 Name Bit Type Description Reset Value RSVD [31:20] R Reserved (Should be zero) – lpddr2_addr [19:0] RW LPDDR2/LPDDR3 Address. Default value (=0x208) is Mode Register Reads to DQ Calibration registers MR32. Reads to MR32 return DQ Calibration Pattern "1111-0000- 1111-0000" on DQ[0], DQ[8], DQ[16], and DQ[24] for x32 devices. When doing Write Training, This field should be set by READ command. For example, lpddr2_addr2 will be 20'h5 if the column address is 11'h0 and bank address is 3'b000. According to READ Command definition in LPDDR2 or LPDDR3 lpddr2_addr[19:0] = "C11-C10-C9-C8-C7-C6-C5- C4-C3-AP-BA2-BA1-BA0-C2-C1-R-R-H-L-H" (C means Column Address, BA means Bank Address, R means Reserved) In case of CA swap mode, lpddr2_addr=20'h41 for Read Training and lpddr2_addr=20'h204 for Write Training if the column address is 11'h0 and bank address is 3'b000. lpddr2_addr[19:0] = "AP-C3-C9-C5-C6-C7-C8-C4-C10- C11-H-L-BA0-R-R-C1-C2-H-B1-B2"(CA swap mode) 0x208

14.4.1.2.22 PHY_CON23

 Base Address: 0xC00E_1000  Address = Base Address + 0x60, Reset Value = 0x0000_03FF Name Bit Type Description Reset Value RSVD [31:20] R Reserved (Should be zero) – lpddr2_default [19:0] RW LPDDR2/LPDDR3 Default Address 0x3ff cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-80 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.23 PHY_CON24

 Base Address: 0xC00E_1000  Address = Base Address + 0x64, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ddr3_default [31:16] RW DDR3 Default Address 0x0 ddr3_addr [15:0] RW DDR3 Address 0x0 ca_swap_mode [0] RW If ctrl_ddr_mode[1]=1 and ca_swap_mode=1, PHY will be in "CA swap mode" for POP. In "CA swap mode", CA[9:0] will be swapped in the following way. CA[0] CA[9] CA[1] CA[8] CA[2] CA[7] CA[3] CA[6] CA[4] CA[5] CA[5] CA[4] CA[6] CA[3] CA[7] CA[2] CA[8] CA[1] CA[9] CA[0] NOTE: Don't use "ctrl_atgate=1" in normal operation when ca_swap_mode = 1. "ctrl_atgate" can be enabled only during calibration. 0x0

14.4.1.2.24 PHY_CON25

 Base Address: 0xC00E_1000  Address = Base Address + 0x68, Reset Value = 0x105E_107E Name Bit Type Description Reset Value RSVD [31:30] R Reserved (Should be zero) – ddr3_cmd [29:16] RW DDR3 Command 0x105E RSVD [15:14] R Reserved (Should be zero) – lpddr2_cmd [13:0] RW LPDDR2/3 Command. This field should be "16'h000E" using LPDDR2 or LPDDR3. 0x107E

14.4.1.2.25 PHY_CON26

 Base Address: 0xC00E_1000  Address = Base Address + 0x6C, Reset Value = 0x0008_107F Name Bit Type Description Reset Value RSVD [31:21] R Reserved (Should be zero) – T_wrdata_en [20:16] RW Clock cycles between write command and the first edge of DQS which can capture the first valid DQ. For example, if WL is 6, It should be set as 7(=WL+1) in LPDDR3, 6(=WL) in DDR3. 0x8 cmd_default [13:0] RW Default Command 16'h000F(LPDDR2, LPDDR3) 16'h107F(DDR2, DDR3) 0x107F cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-81 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.26 PHY_CON27

 Base Address: 0xC00E_1000  Address = Base Address + 0x70, Reset Value = Undefined Name Bit Type Description Reset Value rlvl_vwml3 [31:24] R Left Code Value in Read Valid Window Margin for Data Slice3. Please refer to ReadModeCon (=PHY_CON5) to read. rlvl_vwml2 [23:16] R Left Code Value in Read Valid Window Margin for Data Slice2. Please refer to ReadModeCon (=PHY_CON5) to read. rlvl_vwml1 [15:8] R Left Code Value in Read Valid Window Margin for Data Slice1. Please refer to ReadModeCon (=PHY_CON5) to read. rlvl_vwml0 [7:0] R Left Code Value in Read Valid Window Margin for Data Slice0. Please refer to ReadModeCon (=PHY_CON5) to read.

14.4.1.2.27 PHY_CON28

 Base Address: 0xC00E_1000  Address = Base Address + 0x74, Reset Value = Undefined Name Bit Type Description Reset Value rlvl_vwmr3 [31:24] R Right Code Value in Read Valid Window Margin for Data Slice3. Please refer to ReadModeCon (=PHY_CON5) to read rlvl_vwmr2 [23:16] R Right Code Value in Read Valid Window Margin for Data Slice2. Please refer to ReadModeCon (=PHY_CON5) to read. rlvl_vwmr1 [15:8] R Right Code Value in Read Valid Window Margin for Data Slice1. Please refer to ReadModeCon (=PHY_CON5) to read. rlvl_vwmr0 [7:0] R Right Code Value in Read Valid Window Margin for Data Slice0. Please refer to ReadModeCon (=PHY_CON5) to read. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-82 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.28 PHY_CON29

 Base Address: 0xC00E_1000  Address = Base Address + 0x78, Reset Value = 0x0501_0203 Name Bit Type Description Reset Value Version_Info [31:0] R Version Information 0x0501_0203

14.4.1.2.29 PHY_CON30

 Base Address: 0xC00E_1000  Address = Base Address + 0x7C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ctrl_wrlvl3_code [30:24] RW Write Level Slave DLL Code Value for Data_Slice 3 (0x8 to 0x38) 0x0 ctrl_wrlvl2_code [23:17] RW Write Level Slave DLL Code Value for Data_Slice 2 (0x8 to 0x38) 0x0 ctrl_wrlvl [16] RW Write Level Enable 0x0 RSVD [15] R Reserved (Should be zero) – ctrl_wrlvl1_code [14:8] RW Write Level Slave DLL Code Value for Data_Slice 1 (0x8 to 0x38) 0x0 RSVD [7] R Reserved (Should be zero) – ctrl_wrlvl0_code [6:0] RW Write Level Slave DLL Code Value for Data_Slice 0 (0x8 to 0x38) 0x0

14.4.1.2.30 PHY_CON31

 Base Address: 0xC00E_1000  Address = Base Address + 0x80, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value CA4DeSkewCode [31:28] RW DeSkew Code for CA[4] (0x8 to 0x60) 0x0 CA3DeSkewCode [27:21] RW DeSkew Code for CA[3] (0x8 to 0x60) 0x0 CA2DeSkewCode [20:14] RW DeSkew Code for CA[2] (0x8 to 0x60) 0x0 CA1DeSkewCode [13:7] RW DeSkew Code for CA[1] (0x8 to 0x60) 0x0 CA0DeSkewCode [6:0] RW DeSkew Code for CA[0] (0x8 to 0x60) 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-83 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.31 PHY_CON32

 Base Address: 0xC00E_1000  Address = Base Address + 0x84, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value CA9DeSkewCode [31] RW DeSkew Code for CA[9] (0x8 to 0x60) 0x0 CA8DeSkewCode [30:24] RW DeSkew Code for CA[8] (0x8 to 0x60) 0x0 CA7DeSkewCode [23:17] RW DeSkew Code for CA[7] (0x8 to 0x60) 0x0 CA6DeSkewCode [16:10] RW DeSkew Code for CA[6] (0x8 to 0x60) 0x0 CA5DeSkewCode [9:3] RW DeSkew Code for CA[5] (0x8 to 0x60) 0x0 CA4DeSkewCode [2:0] RW DeSkew Code for CA[4] (0x8 to 0x60) 0x0

14.4.1.2.32 PHY_CON33

 Base Address: 0xC00E_1000  Address = Base Address + 0x88, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value CKE0DeSkewCode [31:27] RW DeSkew Code for CKE[0], (0x8~0x60) 0x0 CS1DeSkewCode [26:20] RW DeSkew Code for CS[1] (0x8~0x60) 0x0 CS0DeSkewCode [19:13] RW DeSkew Code for CS[0] (0x8~0x60) 0x0 CKDeSkewCode [12:6] RW DeSkew Code for CK, (0x8~0x60) 0x0 CA9DeSkewCode [5:0] RW DeSkew Code for CA[9] (0x8~0x60) 0x0

14.4.1.2.33 PHY_CON34

 Base Address: 0xC00E_1000  Address = Base Address + 0x8C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:9] R Reserved (Should be zero) – CKE1DeSkewCode [8:2] RW DeSkew Code for CKE[1] (0x8~0x60) 0x0 CKE0DeSkewCode [1:0] RW DeSkew Code for CKE[0] (0x8~0x60) 0x0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-84 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.34 PHY_CON37

 Base Address: 0xC00E_1000  Address = Base Address + 0x98, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:6] R Reserved (Should be zero) – RSTDeSkewCode [5:0] RW DeSkew Code for Reset (0x8~0x38) 0x0

14.4.1.2.35 PHY_CON39

 Base Address: 0xC00E_1000  Address = Base Address + 0xA0, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:28] R Reserved (Should be zero) – Da3DS [27:25] RW Driver Strength Selection for Data Slice 3 0x0 Da2DS [24:22] RW Driver Strength Selection for Data Slice 2 0x0 Da1DS [21:19] RW Driver Strength Selection for Data Slice 1 0x0 Da0DS [18:16] RW Driver Strength Selection for Data Slice 0 0x0 CaCkDrvrDS [11:9] RW Driver Strength Selection for CK 0x0 CaCkeDrvrDS [8:6] RW Driver Strength Selection for Cke[1:0] 0x0 CaCSDrvrDS [5:3] RW Driver Strength Selection for CS[1:0] 0x0 CaAdrDrvrDS [2:0] RW Driver Strength Selection for ADCT[15:0]. 0x0

14.4.1.2.36 PHY_CON40

 Base Address: 0xC00E_1000  Address = Base Address + 0xA4, Reset Value = 0x0000_0007 Name Bit Type Description Reset Value ctrl_zq_clk_div [31:0] RW ZQ Clock divider setting value 0x7

14.4.1.2.37 PHY_CON41

 Base Address: 0xC00E_1000  Address = Base Address + 0xA8, Reset Value = 0x0000_00F0 Name Bit Type Description Reset Value ctrl_zq_timer [31:0] RW It controls the interval between each ZQ calibration 0xF0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-85 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.2.38 PHY_CON42

 Base Address: 0xC00E_1000  Address = Base Address + 0xAC, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:13] R Reserved (Should be zero) – ctrl_bstlen [12:8] RW Burst Length(BL) 5'h0 RSVD [7:5] RW Reserved (Should be zero) – ctrl_rdlat [4:0] RW Read Latency(RL) 5'h0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-86 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3 MCUS Memory Control Register

14.4.1.3.1 MEMBW

 Base Address: 0xC005_1000  Address = Base Address + 0x00, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [31] RW Reserved (Should be zero) 1'b0 IntSramShadow1 [30] RW Base Address of Internal ROM 0 = Bass address = 0x0000_0000 1 = Bass address = 0x3400_0000 CfgBootMode RSVD [29:2] RW Reserved 1'b0 SR1BW [1] RW Set data bus width of static #1 0 = Byte (8-bit) 1 = Half-word (16-bit) 1'b0 SR0BW [0] RW Set data bus width of static #0 0 = Byte (8-bit) 1 = Half-word (16-bit) CfgSTBUSWidt h cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-87 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.2 MEMTIMEACSL

 Base Address: 0xC005_1000  Address = Base Address + 0x04, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [31:8] RW Reserved (Should be zero) 24'b0 TAcs1 [7:4] RW tACS of static #1 tACS = TACS + 1 4'b11 TAcs0 [3:0] RW tACS of static #0 tACS = TACS + 1 0000 = 1 cycle 0001 = 2 cycle 0010 = 3 cycle 0011 = 4 cycle 0100 = 5 cycle 0101 = 6 cycle 0110 = 7 cycle 0111 = 8 cycle 1000 = 9 cycle 1001 = 10 cycle 1010 = 11 cycle 1011 = 12 cycle 1100 = 13 cycle 1101 = 14 cycle 1110 = 15 cycle 1111 = 0 cycle CfgBootMode cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-88 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.3 MEMTIMEACSH

 Base Address: 0xC005_1000  Address = Base Address + 0x08, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:24] RW Reserved (Should be zero) 8'b0 TAcs13 [23:19] RW tACS of static #13 tACS = TACS + 1 (Unit : BCLK) 4'b0 RSVD [19:0] RW Reserved (Should be zero) -

14.4.1.3.4 MEMTIMECOSL

 Base Address: 0xC005_1000  Address = Base Address + 0x0C, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [31:8 RW Reserved (Should be zero) - tCOS1 [7:4] RW tCOS of static #1 tCOS = TCOS + 1 (Unit : BCLK) 4'b11 tCOS0 [3:0] RW tCOS of static #0 tCOS = TCOS + 1 (Unit : BCLK) 0000 = 1 cycle 0001 = 2 cycle 0010 = 3 cycle 0011 = 4 cycle 0100 = 5 cycle 0101 = 6 cycle 0110 = 7 cycle 0111 = 8 cycle 1000 = 9 cycle 1001 = 10 cycle 1010 = 11 cycle 1011 = 12 cycle 1100 = 13 cycle 1101 = 14 cycle 1110 = 15 cycle 1111 = 0 cycle CfgBootMode cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-89 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.5 MEMTIMECOSH

 Base Address: 0xC005_1000  Address = Base Address + 0x10, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [31:24] RW Reserved (Should be zero) - tCOS13 [23:20] RW tCOS of static #13 t COS = TCOS + 1 (Unit : BCLK) 4'b0 tCOS8 [19] RW tCOS of static #8 tCOS = TCOS + 1 (Unit : BCLK) -

14.4.1.3.6 MEMTIMEACC0

 Base Address: 0xC005_1000  Address = Base Address + 0x14, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [31:16] RW Reserved (Should be zero) - tACC1 [15:8] RW tACC of static #1 8'b01000 tACC0 [7:0] RW tACC of static #0 CfgBootMode

14.4.1.3.7 MEMTIMEACC1

 Base Address: 0xC005_1000  Address = Base Address + 0x18, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:0] RW Reserved (Should be zero) 0x0000_0000

14.4.1.3.8 MEMTIMEACC2

 Base Address: 0xC005_1000  Address = Base Address + 0x1C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:0] RW Reserved (Should be zero) 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-90 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.9 MEMTIMEACC3

 Base Address: 0xC005_1000  Address = Base Address + 0x20, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16 RW Reserved (Should be zero) 16'b0 tACC13 [15:8] RW tACC of static #13 8'b0 RSVD [7:0] RW Reserved (Should be zero) 8'b0

14.4.1.3.10 MEMTIMESACC0

 Base Address: 0xC005_1000  Address = Base Address + 0x24, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] RW Reserved (Should be zero) 16/b0 tSACC1 [15:8] RW tSACC of static #1 8'b0 tSACC0 [7:0] RW tSACC of static #0 8'b0

14.4.1.3.11 MEMTIMESACC1

 Base Address: 0xC005_1000  Address = Base Address + 0x28, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:0] RW Reserved (Should be zero) 0x0000_0000

14.4.1.3.12 MEMTIMESACC2

 Base Address: 0xC005_1000  Address = Base Address + 0x2C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:0] RW Reserved (Should be zero) 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-91 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.13 MEMTIMESACC3

 Base Address: 0xC005_1000  Address = Base Address + 0x30, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:15] RW Reserved (Should be zero) 16'b0 tSACC13 [15:8] RW tSACC of static #13 8'b0 RSVD [7:0] RW Reserved (Should be zero) 8'b0

14.4.1.3.14 MEMTIMECOHL

 Base Address: 0xC005_1000  Address = Base Address + 0x44, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [31:8] RW Reserved (Should be zero) 24'b0 tCOH1 [7:4] RW tCOH of static #1 4'b11 tCOH0 [3:0] RW tCOH of static #0 tCOH = TCOH + 1 (Unit : BCLK) 0000 = 1 cycle 0001 = 2 cycle 0010 = 3 cycle 0011 = 4 cycle 0100 = 5 cycle 0101 = 6 cycle 0110 = 7 cycle 0111 = 8 cycle 1000 = 9 cycle 1001 = 10 cycle 1010 = 11 cycle 1011 = 12 cycle 1100 = 13 cycle 1101 = 14 cycle 1110 = 15 cycle 1111 = 0 cycle CfgBootMode cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-92 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.15 MEMTIMECOHH

 Base Address: 0xC005_1000  Address = Base Address + 0x48, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31::24] RW Reserved (Should be zero) 8'b0 tCOH13 [23:20] RW tCOH of static #13. 4'b0 RSVD [19:0] RW Reserved 20'b0

14.4.1.3.16 MEMTIMECAHL

 Base Address: 0xC005_1000  Address = Base Address + 0x4C, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [31:8] RW Reserved (Should be zero) 24'b0 tCAH1 [7:4] RW tCAH of static #1 4'b11 tCAH0 [3:0] RW tCAH of static #0 tCAH = TCAH + 1 (Unit : BCLK) 0000 = 1 cycle 0001 = 2 cycle 0010 = 3 cycle 0011 = 4 cycle 0100 = 5 cycle 0101 = 6 cycle 0110 = 7 cycle 0111 = 8 cycle 1000 = 9 cycle 1001 = 10 cycle 1010 = 11 cycle 1011 = 12 cycle 1100 = 13 cycle 1101 = 14 cycle 1110 = 15 cycle 1111 = 0 cycle CfgBootMode cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-93 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.17 MEMTIMECAHH

 Base Address: 0xC005_1000  Address = Base Address + 0x50, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:24] RW Reserved (Should be zero) 8'b0 tCAH13 [23:20] RW tCAH of static #13 4'b0 RSVD [19:0] RW Reserved 20'b0

14.4.1.3.18 MEMBURSTL

 Base Address: 0xC005_1000  Address = Base Address + 0x54, Reset Value = 0x0000_0008 Name Bit Type Description Reset Value RSVD [9:8] RW Reserved (Should be zero) 2'b0 BWRITE1 [7:6] RW Write Access Control of static #1 00 = Disable 01 = 4 byte burst Access 10 = 8 byte burst Access 11 = 16 byte burst Access 2'b00 BREAD1 [5:4] RW Read Access Control of static #1 00 = Disable 01 = 4 byte burst Access 10 = 8 byte burst Access 11 = 16 byte burst Access 2'b01 BWRITE0 [3:2] RW Write Access Control of static #0 00 = Disable 01 = 4 byte burst Access 10 = 8 byte burst Access 11 = 16 byte burst Access 2'b00 BREAD0 [1:0] RW Read Access Control of static #0 00 = Disable 01 = 4 byte burst Access 10 = 8 byte burst Access 11 = 16 byte burst Access 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-94 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.19 MEMWAIT

 Base Address: 0xC005_1000  Address = Base Address + 0x5C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:4] RW Reserved (Should be zero) 'b0 WAITENB1 [3] RW Wait Enable control of static #1 0 = Disable Wait Control 1 = Enable Wait Control 1'b0 WAITPOL1 [2] RW Wait Polarity control of static #1 If it is set to low active wait signal, the wait is enabled when the input signal is low. If it is set to high active wait signal, the wait is enabled when the input signal is high. 0 = High active wait signal 1 = Low active wait signal 1'b0 WAITENB0 [1] RW Wait Enable control of static #0 0 = Disable Wait Control 1 = Enable Wait Control 1'b0 WAITPOL0 [0] RW Wait Polarity control of static #0 If it is set to low active wait signal, the wait is enabled when the input signal is low. If it is set to high active wait signal, the wait is enabled when the input signal is high. 0 = High active wait signal 1 = Low active wait signal 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-95 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.20 NFCONTROL

 Base Address: 0xC005_1000  Address = Base Address + 0x1088, Reset Value = Undefined Name Bit Type Description Reset Value NCSENB [31] RW nNCS Enable 0 = Disable 1 = Enable 1'b0 NFECCAUTORSTEN B [30] RW 0 = Auto Reset Disable 1 = Auto Reset Enable 1'b1 NFECCMode [29:27] RW Number of Error correction bit 0 = 4-bit 1 = 8-bit 2 = 12-bit 3 = 16-bit 4 = 24-bit (Only data Size 1024 byte) 5 = 24 bits 6 = 40 bits (Only data Size 1024 byte) 7 = 60 bits (Only data Size 1024 byte) 3'b000 RSVD [26:16] R Reserved (Should be zero) 11'b0 IRQPEND [15] RW Interrupt pending bit of RnB signal detect. Read: 0 = Not pended 1 = Pended Writ: 0 = No affect 1 = Clear 1'bx ECCIRQPEND [14] RW Interrupt pending bit of ECC Done signal detect. Read: 0 = Not pended 1 = Pended Write: 0 = No affect 1 = Clear 1'bx RSVD [14:12] R Reserved (Should be zero) 3'h0 ECCrst [11] W HW ECC block reset NFECCL, NFECCH, NFCNT, NFECCSTATUS, NFSYNDRONE31/75 Registers Reset 1'b0 RSVD [10] R Reserved (Should be zero) 1'bx RnB [9] R Ready/Busy check of NAND Flash operation. 0 = Busy 1 = Ready 1'bx IRQENB [8] RW Set interrupt enable/disable at the rising edge of RnB 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-96 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value signal of NAND Flash. 0 = Disable 1 = Enable ECCIRQENB [7] RW Set interrupt enable/disable ECC done signal of NAND Flash controller. 0 = Disable 1 = Enable 1'b0 NFCartrideENB [6:5] RW Set NAND Flash Cartridge Enable Used SDEX bus of NAND access. Write 00 = Disable 01 = Enable Read 00 = Disable 10 = Enable 1'b0 NFTYPE [4:3] RW Set NAND Flash Type for NAND Booting. 00 = Small block 3 address NAND 01 = Small block 4 address NAND 10 = Large block 4 address NAND 11 = Large block 5 address NAND CfgNFType RSVD [2] RW Reserved (Should be zero) 1'b0 NFBANK [1:0] RW Set NAND Flash bank for access. This bit determines which one will be selected out of nNCS[2:0]. Selected nNCS applied after NFBANK is changed and static memory is accessed. 0 = nNCS[0] 1 = nNCS[1] 2 = nNCS[2] 3 = Reserved 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-97 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.21 NFECCTRL

 Base Address: 0xC005_1000  Address = Base Address + 0x108C, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:29] R Reserved (Should be zero) – ERROR [28] R Result of Decode 0 = No Error 1 = Error 1'b0 NUMBEROFERROR [28] W Number Of Error 5'h0 DECMODE [24] RW 0 = Encoder 1 = Decoder 1'b0 Loadelp [27] W Load ELP Register – DECMODE [26] W 0 = Encoder 1 = Decoder 1'b0 RSVD [25] RW Reserved (Must be zero) – NUMBEROFELP [24:18] RW Number Of ELP When NFECCMODE Register = 0 then 4 When NFECCMODE Register = 1 then 8 When NFECCMODE Register = 2 then 12 When NFECCMODE Register = 3 then 16 When NFECCMODE Register = 4 then 24 5'h0 PARITYCONUT [17:10] RW Number of Parity byte When NFECCMODE Register = 0 then 5 When NFECCMODE Register = 1 then 12 When NFECCMODE Register = 2 then 18 When NFECCMODE Register = 3 then 25 When NFECCMODE Register = 4 then 41 6'h0 NFCOUNTVALUE [9:0] RW Number of NAND Read and Write data When NFECCMODE Register = 0 to 3 then 512 When NFECCMODE Register = 4 then 1024 10'h0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-98 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.22 NFCNT

 Base Address: 0xC005_1000  Address = Base Address + 0x90, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:26] R Reserved (Should be zero) 6'h0 nfwrcnt [25:16] R NAND Flash Write Data Count – RSVD [15:10] R Reserved (Should be zero) 6'h0 NFRDCNT [9:0] R NAND Flash Read Data Count –

14.4.1.3.23 NFECCSTATUS

 Base Address: 0xC005_1000  Address = Base Address + 0x94, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:22] R Reserved (Should be zero) 10'h0 NUMELPERROR [21:16] R Number of ELP Error 6'b RSVD [15:12] R Reserved (Should be zero) 4'h0 NFERRFLAG [11] R If ECC check data error occurs, SYNDROMERROR is set as "1" When reading ECC Register Data, it's cleared. 0 = No Error 1 = Error 1'b0 NUMECCERROR [10:4] R Number of ECC Error 7'b0 SYNDROMERROR [3] R If Syndrom check data error occurs, SYNDROMERROR is set as "1" When reading ECC Register Data, it's cleared. 0 = No Error 1 = Error 1'b0 NFCHECKERROR [2] R When completing NAND Read operating, error check on Read Data. If Read Data Error occurs, NFCHECKERROR is set as "1". Then NAND Address/Command wirites, the register is cleared. 0 = No Error 1 =Data Error 1'b0 NFECCDECDONe [1] R When reading NAND Data with 512 byte plus 51 Cycles (BCLK), NFECCDECDONE is set as "1". When NAND Address/Command wirites, it's cleared. 0 = IDLE or RUN 1 = End 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-99 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value NFECCENCDONE [0] R After writing NAND DATA with 512 byte, NFECCENCDONE is set as "1". When reading ECC Register Data, it's cleared. 0 = IDLE or RUN 1 = End 1'b0

14.4.1.3.24 NFTIMEACS

 Base Address: 0xC005_1000  Address = Base Address + 0x98, Reset Value = 0x0000_0007 Name Bit Type Description Reset Value RSVD [31:12] RW Reserved (Should be zero) 20'b0 tnfacs2 [11:8] RW NAND tNFACS of Nand Bank 2 4'h0 tnfacs1 [7:4] RW NAND tNFACS of Nand Bank 1 4'h0 tnfacs0 [3:0] RW NAND tNFACS of Nand Bank 0 tNFACS = TNFACS + 1 (Unit : BCLK) 0000 = 1 cycle 0001 = 2 cycle 0010 = 3 cycle 0011 = 4 cycle 0100 = 5 cycle 0101 = 6 cycle 0110 = 7 cycle 0111 = 8 cycle 1000 = 9 cycle 1001 = 10 cycle 1010 = 11 cycle 1011 = 12 cycle 1100 = 13 cycle 1101 = 14 cycle 1110 = 15 cycle 1111 = 0 cycle 4'h7 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-100 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.25 NFTIMECOS

 Base Address: 0xC005_1000  Address = Base Address + 0x9C, Reset Value = 0x0000_0007 Name Bit Type Description Reset Value RSVD [31:12] RW Reserved (Should be zero) 20'b0 tnfcos2 [11:8] RW NAND tNFCOS of Nand Bank 2 4'h0 tnfcos1 [7:4] RW NAND tNFCOS of Nand Bank 1 4'h0 tnfcos0 [3:0] RW NAND tNFCOS of Nand Bank 0 tNFCOS = TNFCOS + 1 (Unit : BCLK) 0000 = 1 cycle 0001 = 2 cycle 0010 = 3 cycle 0011 = 4 cycle 0100 = 5 cycle 0101 = 6 cycle 0110 = 7 cycle 0111 = 8 cycle 1000 = 9 cycle 1001 = 10 cycle 1010 = 11 cycle 1011 = 12 cycle 1100 = 13 cycle 1101 = 14 cycle 1110 = 15 cycle 1111 = 0 cycle 4'h7 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-101 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.26 NFTIMEACC0

 Base Address: 0xC005_1000  Address = Base Address + 0xA0, Reset Value = 0x0000_000F Name Bit Type Description Reset Value RSVD [31:24] RW Reserved (Should be zero) 8'b0 tNFacc2 [23:16] RW tANFCC of NAND Bank 2 8'h00 tNFacc1 [15:8] RW tANFCC of NAND Bank 1 8'h00 tNFacc0 [7:0] RW tANFCC of NAND Bank 0 tNFACC = TNFACC +1 Cycle 8'h0f

14.4.1.3.27 NFTIMEOCH

 Base Address: 0xC005_1000  Address = Base Address + 0xA8, Reset Value = 0x0000_0007 Name Bit Type Description Reset Value RSVD [31:12] RW Reserved (Should be zero) 20'b0 tnfOCH2 [11:8] RW NAND tNFOCH of Nand Bank 2 4'h0 tnfOCH1 [7:4] RW NAND tNFOCH of Nand Bank 1 4'h0 tnfOCH0 [3:0] RW NAND tNFOCH of Nand Bank 0 tNFOCH = TNFOCH + 1 (Unit : BCLK) 0000 = 1 cycle 0001 = 2 cycle 0010 = 3 cycle 0011 = 4 cycle 0100 = 5 cycle 0101 = 6 cycle 0110 = 7 cycle 0111 = 8 cycle 1000 = 9 cycle 1001 = 10 cycle 1010 = 11 cycle 1011 = 12 cycle 1100 = 13 cycle 1101 = 14 cycle 1110 = 15 cycle 1111 = 0 cycle 4'h7 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-102 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.28 NFTIMECAH

 Base Address: 0xC005_1000  Address = Base Address + 0xAC, Reset Value = 0x0000_0007 Name Bit Type Description Reset Value RSVD [31:12] RW Reserved (Should be zero) 20'b0 tnfcAH2 [11:8] RW NAND tNFCOS of Nand Bank 2 4'h0 tnfcAH1 [7:4] RW NAND tNFCOS of Nand Bank 1 4'h0 tnfcAH0 [3:0] RW NAND tNFCAH of Nand Bank 0 tNFCAH = TNFCAH + 1 (Unit : BCLK) 0000 = 1 cycle 0001 = 2 cycle 0010 = 3 cycle 0011 = 4 cycle 0100 = 5 cycle 0101 = 6 cycle 0110 = 7 cycle 0111 = 8 cycle 1000 = 9 cycle 1001 = 10 cycle 1010 = 11 cycle 1011 = 12 cycle 1100 = 13 cycle 1101 = 14 cycle 1110 = 15 cycle 1111 = 0 cycle 4'h7 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-103 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.29 NFECCn (n = 0 to 26)

 Base Address: 0xC005_1000  Address = Base Address + 0x10B0, + 0x10B4, + 0x10B8, + 0x10BC, + 0x10C0, + 0x10C4, + 0x10C8, + 0x10CC, + 0x10D0, + 0x10D4, + 0x10D8, + 0x10DC, + 0x10E0, + 0x10E4, + 0x10E8, + 0x10EC, + 0x10F0, + 0x10F4, + 0x10F8, + 0x10FC, + 0x1100, + 0x1104, + 0x1108, + 0x110C, + 0x1110, + 0x1114, + 0x1118, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ECC[n] [31:0] R Represents 512/1024 byte ECC parity code during Write operation by H/W ECC generation block 32'h0

14.4.1.3.30 NFORGECCn (n = 0 to 26)

 Base Address: 0xC005_1000  Address = Base Address + 0x111C, + 0x1120, + 0x1124, + 0x1128, + 0x112C, + 0x1130, + 0x1134, + 0x1138, + 0x113C, + 0x1140, + 0x1144, + 0x1148, + 0x114C, + 0x1150, + 0x1154, + 0x1158, + 0x115C, + 0x1160, + 0x1164, + 0x1168, + 0x116C, + 0x1170, + 0x1174, + 0x1178, + 0x117C, + 0x1180, + 0x1184, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value ORGECC[n] [31:0] RW When NAND Read operates, firstly read Original ECC Data already saved in the NAND Spare area and then wrties in Register. 32'h0

14.4.1.3.31 NFSYNDROMEn (n = 0 to 29)

 Base Address: 0xC005_1000  Address = Base Address + 0x1188, + 0x118C, + 0x1190, + 0x1194, + 0x1198, + 0x119C, + 0x11A0, + 0x11A4, + 0x11A8, + 0x11AC, + 0x11B0, + 0x11B4, + 0x11B8, + 0x11BC, + 0x11C0, + 0x11C4, + 0x11C8, + 0x11CC, + 0x11D0, + 0x11D4, + 0x11D8 + 0x11DC, + 0x11E0, + 0x11E4, + 0x11E8, + 0x11EC, + 0x11F0, + 0x11F4, + 0x11F8, + 0x11FC, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:30] R Reserved (Should be zero) 2'b0 SYNDROM [3+(nx4)] [29:16] R ECC Decoder Result Odd Syndrome Data3 (offset n x4) 14'h0 RSVD [15:14] R Reserved (Should be zero) 2'b0 SYNDROM [1+(nx4)] [13:0] R ECC Decoder Result Odd Syndrome Data1 (offset n x4) 14'h0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-104 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.32 NFELPn (n = 0 to 59)

 Base Address: 0xC005_1000  Address = Base Address + 0x1200, 0x1204, 0x1208, 0x120C, 0x1210, 0x1214, 0x1218, 0x121C, 0x1220, 0x1224, 0x1228, 0x122C, 0x1230, 0x1234, 0x1238, 0x123C, 0x1240, 0x1244, 0x1248, 0x124C, 0x1250, 0x1254, 0x1258, 0x125C, 0x1260, 0x1264, 0x1268, 0x126C, 0x1270 0x1274, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [31:28] RW Reserved (Should be zero) – ELP[2+(nx2) [27:14] RW 2nd ELP (Error locator polynomial) register – ELP[1+(nx2)] [13:0] RW 1st t ELP (Error locator polynomial) register –

14.4.1.3.33 NFERRORLOCATIONn (n = 0 to 59)

 Base Address: 0xC005_1000  Address = Base Address + 0x1278, 0x127C, 0x1280, 0x1284, 0x1288, 0x128C, 0x1290, 0x1294, 0x1298, 0x129C, 0x12A0, 0x12A4, 0x12A8, 0x12AC, 0x12B0, 0x12B4, 0x12B8, 0x12BC, 0x12C0, 0x12C4, 0x12C8, 0x12CC, 0x12D0, 0x12D4, 0x12D8, 0x12DC, 0x12E0, 0x12E4, 0x12E8, 0x12EC, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [31:28] R Reserved (Should be zero) – Error[2+(nx2)] [27:14] R 2nd location of error – Error[1+(nx2)] [13:0] R 1st location of error –

14.4.1.3.34 AUTO SYNDROM REGISTER(AUTOSYND)

 Base Address: 0xC005_1000  Address = Base Address + 0x12F0, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:2] R Reserved (Should be zero) – CPUSYND [1] W User can write the SYNDROM value or auto SYNDROM value. 0 = Auto 1 = User write 1'b0 CPUELP [0] W User can write the ELP value or auto ELP value. 0 = Auto 1 = User write 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 14-105 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

14.4.1.3.35 NFWSYNDRONEn (n = 0 to 29)

 Base Address: 0xC005_1000  Address = Base Address + 0x12F4, 0x12F8, 0x12FC, 0x1300, 0x1304, 0x1308, 0x130C, 0x1310, 0x1314, 0x1318, 0x131C, 0x1320, 0x1324, 0x1328, 0x132C, 0x1330, 0x1334, 0x1338, 0x133C, 0x1340, 0x1344, 0x1348, 0x134C, 0x1350, 0x1354, 0x1358, 0x135C, 0x1360, 0x1364, 0x1368, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:30] R Reserved (Should be zero) 2'b0 SYNDROM [3+(nx4)] [29:16] W ECC Decoder Result Odd Syndrome Data3 (offset n x4) 14'h0 RSVD [15:14] R Reserved 2'b0 SYNDROM [1+(nx4)] [13:0] W ECC Decoder Result Odd Syndrome Data1 (offset n x4) 14'h0

14.4.1.4 MCUS Memory Control Register

14.4.1.4.1 NFDATA

 Base Address: 0x2C00_0000  Address = Base Address + 0x0000, Reset Value = Undefined Name Bit Type Description Reset Value NFDATA [31:0] RW NAND flash data register. In case of 16-bit access on this register, it generates 8-bit access cycle in twice automatically. In case of 32-bit access on this register, it also generates four 8-bit access cycles automatically.

14.4.1.4.2 NFCMD

 Base Address: 0x2C00_0000  Address = Base Address + 0x0010, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [15:8] – Reserved (Should be zero) 8'h0 NFCMD [7:0] W NAND flash command register. Writing on this register generates a command cycle with CLE signal and transfers this value on data bus automatically. You have to write only 8-bit data on this register. Do not access this register with 16/32-bit data. 8'hx

14.4.1.4.3 NFADDR

 Base Address: 0x2C00_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 14 Memory Controller 106 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  Address = Base Address + 0x0018, Reset Value = Undefined Name Bit Type Description Reset Value RSVD [15:8] – Reserved (Should be zero) 8'hx NFADDR [7:0] W NAND flash address register. Writing on this register generates an address cycle with ALE signal and transfers this value on data bus automatically. You have to write only 8-bit data on this register. Do not access this register with 16/32-bit access. Only byte access is available. 8'hx cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15 GPIO Controller

15.1 Overview

15.1.1 Features

 Programmable Pull-Up Control  Edge/Level Detect  Supports programmable Pull-Up resistance.  Supports four event detection modes  Rising Edge Detection  Falling Edge Detection  Low Level Detection  High Level Detection  The number of GPIOs: 160 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.2 Block Diagram

Figure 15-1 GPIO Block Diagram cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.3 Functional Description

S5P4418 GPIO Pins have an internal pull-up resistance of 100 k. The current of the pull-up resistance (for VDD = 3.3 V and V (PAD) = 0 V) is listed in the table below: Pull Up Min. Typ. Max. Unit ENABLE 10 33 72 uA DISABLE – – 0.1 uA Most S5P4418 GPIO ports contain the Alternate function (some ports supports up to Alternate Function2). All GPIO ports should be set as GPIO function or Alternate Function suitable for the user's purposes and this setting can easily be performed with GPIO registers. In addition, all GPIO pull-up resistances are enabled/ disabled. This setting operates when the system is fully booted and does not affect the system in initial booting. If there is a value which needs to be determined in system booting, the value is given by inserting a pull up/down resistance from outside.

15.3.1 Input Operation

To use GPIO for input, the GPIO function should be selected by setting the relevant bit of the GPIO Alternate Function Select register as b'00 to select the GPIO function. In addition, the GPIO Input mode should be, also, selected by the GPIOx Output Enable register (GPIOxOUTENB) as “0”. An input signal is detected by selecting a desired detection type with the GPIOx Event Detect Mode register. Four types of input signal can be detected: Low Level, High Level, Falling edge and Rising edge. The GPIOx Event Detect Mode registers consist of GPIOx Event Detect Mode register0 (GPIOxDETMODE0) and GPIOx Event Detect Moderegister1 (GPIOxDETMODE1). To use interrupt, set the GPIOx Interrupt Enable Register (GPIOxINTENB) as “1”. The GPIOx Event Detect Register (GPIOxDET) enables checking the generation of an event via GPIO and may be used as the Pending Clear function when an interrupt occurs. When the GPIOx PAD Status Register (GPIOxPAD) is set as GPIO Input mode, the levelof the relevant GPIOx PAD can be checked. The Open drain pins (GPIOB[7:4] and GPIOC[8]) operate in Input mode only when the GPIOx Output register (GPIOxOUT) is set as “1”. The Open drain pins are operated by the GPIOx Output Register (GPIOxOUT) even if the GPIOx Output Enable register (GPIOxOUTENB) is set as Input mode. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.3.2 Output Operation

To use GPIO for output, the GPIO function should be selected by setting the relevant bit of the GPIOx. Alternate Function Select register should be set as b'00 to select the GPIO function. In addition, the GPIOx Output mode should also be selected by setting the GPIOx Output Enable register as "1". If you set a desired output value (low level: "0", high level: "1") with the GPIOx Output Register (GPIOxOUT), the value is reflected to the corresponding bit. The Open drain pins (GPIOB[7:4] and GPIOC[8]) operate in output mode only when the GPIOx Output register (GPIOxOUT) is set as "0". The Open drain pins are operated by the GPIOx Output Register (GPIOxOUT) even if the GPIOx Output Enable register(GPIOxOUTENB) is set as Input mode.

15.3.3 Alternate Function Operation

Among the 151 GPIO pins of the S5P4418, most GPIO pins have an Alternate function. However, the Alternate function and the GPIO function should not be used simultaneously. Therefore, Alternate Function1 and Alternate Function2 are operated by setting the corresponding bits of the GPIOx Alternate Function Select register as b'01 and b'10, respectively. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4 Register Description

15.4.1 Register Map Summary

 Base Address: C001_A000h (GPIOA)  Base Address: C001_B000h (GPIOB)  Base Address: C001_C000h (GPIOC)  Base Address: C001_D000h (GPIOD)  Base Address: C001_E000h (GPIOE) Register Offset Description Reset Value GPIOxOUT A000h, B000h, C000h, D000h, E000h GPIOx output register 32'h0 GPIOxOUTENB A004h, B004h, C004h, D004h, E004h GPIOx output enable register 32'h0 GPIOxDETMODE0 A008h, B008h, C008h, D008h, E008h GPIOx event detect mode register 0 2'b00 GPIOxDETMODE1 A00Ch, B00Ch, C00Ch, D00Ch, E00Ch GPIOx event detect mode register 1 2'b00 GPIOxINTENB A010h, B010h, C010h, D010h, E010h GPIOx interrupt enable register 32'h0 GPIOxDET A014h, B014h, C014h, D014h, E014h GPIOx event detect register 32'h0 GPIOxPAD A018h, B018h, C018h, D018h, E018h GPIOx PAD status register 32'h0 RSVD A01Ch, B01Ch,C Reserved Undefined cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value 01Ch,D0 1Ch,E01 Ch GPIOxALTFN0 A020h, B020h, C020h, D020h, E020h GPIOx alternate function select register 0 2'b00 GPIOxALTFN1 A024h, B024h, C024h, D024h, E024h GPIOx alternate function select register 1 2'b00 GPIOxDETMODEEX A028h, B028h, C028h, D028h, E028h GPIOx event detect mode extended register 1'b0 GPIOxDETENB A03Ch, B03Ch, C03Ch, D03Ch, E03Ch GPIOx detect enable register 32'h0 GPIOx_SLEW A040h, B040h, C040h, D040h, E040h GPIOx slew register 32'hffffffff GPIOx_SLEW_DISABLE _DEFAULT A044h, B044h, C044h, D044h, E044h GPIOx slew disable default register 32'hffffffff GPIOx_DRV1 A048h, B048h, C048h, D048h, E048h GPIOx DRV1 register 32'h0 GPIOx_DRV1_DISABLE _DEFAULT A04Ch, B04Ch, C04Ch, D04Ch, E04Ch GPIOx DRV1 disable default register 32'hffffffff GPIOx_DRV0 A050h, B050h, C050h, D050h, GPIOx DRV0 register 32'h0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value E050h GPIOx_DRV0_DISABLE _DEFAULT A054h, B054h, C054h, D054h, E054h GPIOx DRV0 disable default register 32'hffffffff GPIOx_PULLSEL A058h, B058h, C058h, D058h, E058h GPIOx PULLSEL register 32'h0 GPIOx_PULLSEL_DISA BLE_DEFAULT A05Ch, B05Ch, C05Ch, D05Ch, E05Ch GPIOx PULLSEL disable default register 32'h0 GPIOx_PULLENB A060h, B060h, C060h, D060h, E060h GPIOx PULLENB register 32'h0 GPIOx_PULLENB_DISA BLE_DEFAULT A064h, B064h, C064h, D064h, E064h GPIOx PULLENB disable default register 32'h0 NOTE: ''GPIOx Register ( x = A, B, C, D, E ) cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4.1.1 GPIOxOUT

15.4.1.2 GPIOxOUTENB

S5P4418_UM 15 GPIO Controller 15-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4.1.3 GPIOxDETMODE0

 Base Address: C001_A000h (GPIOA)  Base Address: C001_B000h (GPIOB)  Base Address: C001_C000h (GPIOC)  Base Address: C001_D000h (GPIOD)  Base Address: C001_E000h (GPIOE)  Address = Base Address + A008h, + B008h, + C008h, + D008h, + E008h, Reset Value = 2'b00 Name Bit Type Description Reset Value GPIOXDETMODE0_ 15 [31:30] RW Specifies Detect mode when GPIOx15 is in Input mode. It is configured the combination of GPIOXDET_EX15 (1- bit) + GPIOXDETMODE0_15 (2-bit). Considers GPIOXDET_EX15 as well as GPIOXDETMODE0_15. NOTE: First bit is GPIOXDET_EX15 Second and third bit is GPIOXDETMODE0_15 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE0_ 14 [29:28] RW Specifies Detect mode when GPIOx14 is in Input mode. It is configured the combination of GPIOXDET_EX14 (1- bit) + GPIOXDETMODE0_14 (2-bit). Considers GPIOXDET_EX14 as well as GPIOXDETMODE0_14. NOTE: First bit is GPIOXDET_EX14 Second and third bit is GPIOXDETMODE0_14 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE0_ 13 [27:26] RW Specifies Detect mode when GPIOx13 is in Input mode. It is configured the combination of GPIOXDET_EX13 (1- bit) + GPIOXDETMODE0_13 (2-bit). Considers GPIOXDET_EX13 as well as GPIOXDETMODE0_13. NOTE: First bit is GPIOXDET_EX13 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Second and third bit is GPIOXDETMODE0_13 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDETMODE0_ 12 [25:24] RW Specifies Detect mode when GPIOx12 is in Input mode. It is configured the combination of GPIOXDET_EX12 (1- bit) + GPIOXDETMODE0_12 (2-bit). Considers GPIOXDET_EX12 as well as GPIOXDETMODE0_12. NOTE: First bit is GPIOXDET_EX12 Second and third bit is GPIOXDETMODE0_12 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE0_ 11 [23:22] RW Specifies Detect mode when GPIOx11 is in Input mode. It is configured the combination of GPIOXDET_EX11 (1- bit) + GPIOXDETMODE0_11 (2-bit). Considers GPIOXDET_EX11 as well as GPIOXDETMODE0_11. NOTE: First bit is GPIOXDET_EX11 Second and third bit is GPIOXDETMODE0_11 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE0_ 10 [21:20] RW Specifies Detect mode when GPIOx10 is in Input mode. It is configured the combination of GPIOXDET_EX10 (1- bit) + GPIOXDETMODE0_10 (2-bit). Considers GPIOXDET_EX10 as well as GPIOXDETMODE0_10. NOTE: First bit is GPIOXDET_EX10 Second and third bit is GPIOXDETMODE0_10 000 = Low Level 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDETMODE0_ 9 [19:18] RW Specifies Detect mode when GPIOx9 is in Input mode. It is configured the combination of GPIOXDET_EX9 (1-bit) + GPIOXDETMODE0_9 (2-bit). Considers GPIOXDET_EX9 as well as GPIOXDETMODE0_9. NOTE: First bit is GPIOXDET_EX9 Second and third bit is GPIOXDETMODE0_9 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE0_ 8 [17:16] RW Specifies Detect mode when GPIOx8 is in Input mode. It is configured the combination of GPIOXDET_EX8 (1-bit) + GPIOXDETMODE0_8 (2-bit.). Considers GPIOXDET_EX8 as well as GPIOXDETMODE0_8. NOTE: First bit is GPIOXDET_EX8 Second and third bit is GPIOXDETMODE0_8 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE0_ 7 [15:14] RW Specifies Detect mode when GPIOx7 is in Input mode. It is configured the combination of GPIOXDET_EX7 (1-bit) + GPIOXDETMODE0_7 (2-bit). Considers GPIOXDET_EX7 as well as GPIOXDETMODE0_7. NOTE: First bit is GPIOXDET_EX7 Second and third bit is GPIOXDETMODE0_7 000 = Low Level 001 = High Level 010 = Falling Edge 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDETMODE0_ 6 [13:12] RW Specifies Detect mode when GPIOx6 is in Input mode. It is configured the combination of GPIOXDET_EX6 (1-bit) + GPIOXDETMODE0_6 (2-bit). Considers GPIOXDET_EX6 as well as GPIOXDETMODE0_6. NOTE: First bit is GPIOXDET_EX6 Second and third bit is GPIOXDETMODE0_6 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE0_ 5 [11:10] RW Specifies Detect mode when GPIOx5 is in Input mode. It is configured the combination of GPIOXDET_EX5 (1-bit) + GPIOXDETMODE0_5 (2-bit). Considers GPIOXDET_EX5 as well as GPIOXDETMODE0_5. NOTE: First bit is GPIOXDET_EX5 Second and third bit is GPIOXDETMODE0_5 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE0_ 4 [9:8] RW Specifies Detect mode when GPIOx4 is in Input mode. It is configured the combination of GPIOXDET_EX4 (1-bit) + GPIOXDETMODE0_4 (2-bit). Considers GPIOXDET_EX4 as well as GPIOXDETMODE0_4. NOTE: First bit is GPIOXDET_EX4 Second and third bit is GPIOXDETMODE0_4 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 101 to 111 = Reserved GPIOXDETMODE0_ 3 [7:6] RW Specifies Detect mode when GPIOx3 is in Input mode. It is configured the combination of GPIOXDET_EX3 (1-bit) + GPIOXDETMODE0_3 (2-bit). Considers GPIOXDET_EX3 as well as GPIOXDETMODE0_3. NOTE: First bit is GPIOXDET_EX3 Second and third bit is GPIOXDETMODE0_3 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE0_ 2 [5:4] RW Specifies Detect mode when GPIOx2 is in Input mode. It is configured the combination of GPIOXDET_EX2 (1-bit) + GPIOXDETMODE0_2 (2-bit). Considers GPIOXDET_EX2 as well as GPIOXDETMODE0_2. NOTE: First bit is GPIOXDET_EX2 Second and third bit is GPIOXDETMODE0_2 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE0_ 1 [3:2] RW Specifies Detect mode when GPIOx1 is in Input mode. It is configured the combination of GPIOXDET_EX1 (1-bit) + GPIOXDETMODE0_1 (2-bit). Considers GPIOXDET_EX1 as well as GPIOXDETMODE0_1. NOTE: First bit is GPIOXDET_EX1 Second and third bit is GPIOXDETMODE0_1 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE0_ [1:0] RW Specifies Detect mode when GPIOx0 is in Input mode. 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value

0 It is configured the combination of GPIOXDET_EX0 (1-bit)

+ GPIOXDETMODE0_0 (2-bit). Considers GPIOXDET_EX0 as well as GPIOXDETMODE0_0. NOTE: First bit is GPIOXDET_EX0 Second and third bit is GPIOXDETMODE0_0 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4.1.4 GPIOxDETMODE1

 Base Address: C001_A000h (GPIOA)  Base Address: C001_B000h (GPIOB)  Base Address: C001_C000h (GPIOC)  Base Address: C001_D000h (GPIOD)  Base Address: C001_E000h (GPIOE)  Address = Base Address + A00Ch, + B00Ch, + C00Ch, + D00Ch, + E00Ch, Reset Value = 2'b00 Name Bit Type Description Reset Value GPIOXDETMODE1_ 31 [31:30] RW Specifies Detect mode when GPIOx31 is in Input mode. It is configured the combination of GPIOXDET_EX31 (1- bit) + GPIOXDETMODE1_31 (2-bit). Considers GPIOXDET_EX31 as well as GPIOXDETMODE1_31. NOTE: First bit is GPIOXDET_EX31 Second and third bit is GPIOXDETMODE1_31 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE1_ 30 [29:28] RW Specifies Detect mode when GPIOx30 is in Input mode. It is configured the combination of GPIOXDET_EX30 (1- bit) + GPIOXDETMODE1_30 (2-bit). Considers GPIOXDET_EX30 as well as GPIOXDETMODE1_30. NOTE: First bit is GPIOXDET_EX30 Second and third bit is GPIOXDETMODE1_30 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE1_ 29 [27:26] RW Specifies Detect mode when GPIOx29 is in Input mode. It is configured the combination of GPIOXDET_EX29 (1- bit) + GPIOXDETMODE1_29 (2-bit). Considers GPIOXDET_EX29 as well as GPIOXDETMODE1_29. NOTE: First bit is GPIOXDET_EX29 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Second and third bit is GPIOXDETMODE1_29 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDETMODE1_ 28 [25:24] RW Specifies Detect mode when GPIOx28 is in Input mode. It is configured the combination of GPIOXDET_EX28 (1- bit) + GPIOXDETMODE1_28 (2-bit). Considers GPIOXDET_EX28 as well as GPIOXDETMODE1_28. NOTE: First bit is GPIOXDET_EX28 Second and third bit is GPIOXDETMODE1_28 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE1_ 27 [23:22] RW Specifies Detect mode when GPIOx27 is in Input mode. It is configured the combination of GPIOXDET_EX27 (1- bit) + GPIOXDETMODE1_27 (2-bit). Considers GPIOXDET_EX27 as well as GPIOXDETMODE1_27. NOTE: First bit is GPIOXDET_EX27 Second and third bit is GPIOXDETMODE1_27 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE1_ 26 [21:20] RW Specifies Detect mode when GPIOx26 is in Input mode. It is configured the combination of GPIOXDET_EX26 (1- bit) + GPIOXDETMODE1_26 (2-bit). Considers GPIOXDET_EX26 as well as GPIOXDETMODE1_26. NOTE: First bit is GPIOXDET_EX26 Second and third bit is GPIOXDETMODE1_26 000 = Low Level 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDETMODE1_ 25 [19:18] RW Specifies Detect mode when GPIOx25 is in Input mode. It is configured the combination of GPIOXDET_EX25 (1- bit) + GPIOXDETMODE1_25 (2-bit). Considers GPIOXDET_EX25 as well as GPIOXDETMODE1_25. NOTE: First bit is GPIOXDET_EX25 Second and third bit is GPIOXDETMODE1_25 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE1_ 24 [17:16] RW Specifies Detect mode when GPIOx24 is in Input mode. It is configured the combination of GPIOXDET_EX24 (1- bit) + GPIOXDETMODE1_24 (2-bit). Considers GPIOXDET_EX24 as well as GPIOXDETMODE1_24. NOTE: First bit is GPIOXDET_EX24 Second and third bit is GPIOXDETMODE1_24 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE1_ 23 [15:14] RW Specifies Detect mode when GPIOx23 is in Input mode. It is configured the combination of GPIOXDET_EX23 (1- bit) + GPIOXDETMODE1_23 (2-bit). Considers GPIOXDET_EX23 as well as GPIOXDETMODE1_23. NOTE: First bit is GPIOXDET_EX23 Second and third bit is GPIOXDETMODE1_23 000 = Low Level 001 = High Level 010 = Falling Edge 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDETMODE1_ 22 [13:12] RW Specifies Detect mode when GPIOx22 is in Input mode. It is configured the combination of GPIOXDET_EX22 (1- bit) + GPIOXDETMODE1_22 (2-bit). Considers GPIOXDET_EX22 as well as GPIOXDETMODE1_22. NOTE: First bit is GPIOXDET_EX22 Second and third bit is GPIOXDETMODE1_22 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE1_ 21 [11:10] RW Specifies Detect mode when GPIOx21 is in Input mode. It is configured the combination of GPIOXDET_EX21 (1- bit) + GPIOXDETMODE1_21 (2-bit). Considers GPIOXDET_EX21 as well as GPIOXDETMODE1_21. NOTE: First bit is GPIOXDET_EX21 Second and third bit is GPIOXDETMODE1_21 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE1_ 20 [9:8] RW Specifies Detect mode when GPIOx20 is in Input mode. It is configured the combination of GPIOXDET_EX20 (1- bit) + GPIOXDETMODE1_20 (2-bit). Considers GPIOXDET_EX20 as well as GPIOXDETMODE1_20. NOTE: First bit is GPIOXDET_EX20 Second and third bit is GPIOXDETMODE1_20 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 101 to 111 = Reserved GPIOXDETMODE1_ 19 [7:6] RW Specifies Detect mode when GPIOx19 is in Input mode. It is configured the combination of GPIOXDET_EX19 (1- bit) + GPIOXDETMODE1_19 (2-bit). Considers GPIOXDET_EX19 as well as GPIOXDETMODE1_19. NOTE: First bit is GPIOXDET_EX19 Second and third bit is GPIOXDETMODE1_19 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE1_ 18 [5:4] RW Specifies Detect mode when GPIOx18 is in Input mode. It is configured the combination of GPIOXDET_EX18 (1- bit) + GPIOXDETMODE1_18 (2-bit). Considers GPIOXDET_EX18 as well as GPIOXDETMODE1_18. NOTE: First bit is GPIOXDET_EX18 Second and third bit is GPIOXDETMODE1_18 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE1_ 17 [3:2] RW Specifies Detect mode when GPIOx17 is in Input mode. It is configured the combination of GPIOXDET_EX17 (1- bit) + GPIOXDETMODE1_17 (2-bit). Considers GPIOXDET_EX17 as well as GPIOXDETMODE1_17. NOTE: First bit is GPIOXDET_EX17 Second and third bit is GPIOXDETMODE1_17 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 2'b00 GPIOXDETMODE1_ [1:0] RW Specifies Detect mode when GPIOx16 is in Input mode. 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value

16 It is configured the combination of GPIOXDET_EX16 (1-

bit) + GPIOXDETMODE1_16 (2-bit). Considers GPIOXDET_EX16 as well as GPIOXDETMODE1_16. NOTE: First bit is GPIOXDET_EX16 Second and third bit is GPIOXDETMODE1_16 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4.1.5 GPIOxINTENB

15.4.1.6 GPIOxDET

S5P4418_UM 15 GPIO Controller 15-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4.1.7 GPIOxPAD

15.4.1.8 GPIOxALTFN0

S5P4418_UM 15 GPIO Controller 15-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 GPIOXALTFN0_11 [23:22] RW GPIOx[11]: Selects the function of GPIOx 11pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN0_10 [21:20] RW GPIOx[10]: Selects the function of GPIOx 10pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN0_9 [19:18] RW GPIOx[9]: Selects the function of GPIOx 9pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN0_8 [17:16] RW GPIOx[8]: Selects the function of GPIOx 8pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN0_7 [15:14] RW GPIOx[7]: Selects the function of GPIOx 7pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN0_6 [13:12] RW GPIOx[6]: Selects the function of GPIOx 6pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN0_5 [11:10] RW GPIOx[5]: Selects the function of GPIOx 5pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN0_4 [9:8] RW GPIOx[4]: Selects the function of GPIOx 4pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 11 = ALT Function3 GPIOXALTFN0_3 [7:6] RW GPIOx[3]: Selects the function of GPIOx 3pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN0_2 [5:4] RW GPIOx[2]: Selects the function of GPIOx 2pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN0_1 [3:2] RW GPIOx[1]: Selects the function of GPIOx 1pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN0_0 [1:0] RW GPIOx[0]: Selects the function of GPIOx 0pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4.1.9 GPIOxALTFN1

 Base Address: C001_A000h (GPIOA)  Base Address: C001_B000h (GPIOB)  Base Address: C001_C000h (GPIOC)  Base Address: C001_D000h (GPIOD)  Base Address: C001_E000h (GPIOE)  Address = Base Address + A024h, + B024h, + C024h, + D024h, + E024h, Reset Value = 2'b00 Name Bit Type Description Reset Value GPIOXALTFN1_31 [31:30] RW GPIOx[31]: Selects the function of GPIOx 31pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_30 [29:28] RW GPIOx[30]: Selects the function of GPIOx 30pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_29 [27:26] RW GPIOx[29]: Selects the function of GPIOx 29pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_28 [25:24] RW GPIOx[28]: Selects the function of GPIOx 28pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_27 [23:22] RW GPIOx[27]: Selects the function of GPIOx 27pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_26 [21:20] RW GPIOx[26]: Selects the function of GPIOx 26pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_25 [19:18] RW GPIOx[25]: Selects the function of GPIOx 25pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-26 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 11 = ALT Function3 GPIOXALTFN1_24 [17:16] RW GPIOx[24]: Selects the function of GPIOx 24pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_23 [15:14] RW GPIOx[23]: Selects the function of GPIOx 23pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_22 [13:12] RW GPIOx[22]: Selects the function of GPIOx 22pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_21 [11:10] RW GPIOx[21]: Selects the function of GPIOx 21pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_20 [9:8] RW GPIOx[20]: Selects the function of GPIOx 20pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_19 [7:6] RW GPIOx[19]: Selects the function of GPIOx 19pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_18 [5:4] RW GPIOx[18]: Selects the function of GPIOx 18pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_17 [3:2] RW GPIOx[17]: Selects the function of GPIOx 17pin. 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 2'b00 GPIOXALTFN1_16 [1:0] RW GPIOx[16]: Selects the function of GPIOx 16pin. 2'b00 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 00 = ALT Function0 01 = ALT Function1 10 = ALT Function2 11 = ALT Function3 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-28 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4.1.10 GPIOxDETMODEEX

 Base Address: C001_A000h (GPIOA)  Base Address: C001_B000h (GPIOB)  Base Address: C001_C000h (GPIOC)  Base Address: C001_D000h (GPIOD)  Base Address: C001_E000h (GPIOE)  Address = Base Address + A028h, + B028h, + C028h, + D028h, + E028h, Reset Value = 1'b0 Name Bit Type Description Reset Value GPIOXDET_EX31 [31] RW Specifies Detect mode when GPIOx31 is in Input mode. It is configured the combination of GPIOXDET_EX31 (1- bit) + GPIOXDETMODE1_31 (2-bit). Considers GPIOXDET_EX31 as well as GPIOXDETMODE1_31. NOTE: First bit is GPIOXDET_EX31 Second and third bit is GPIOXDETMODE1_31 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX30 [30] RW Specifies Detect mode when GPIOx30 is in Input mode. It is configured the combination of GPIOXDET_EX30 (1- bit) + GPIOXDETMODE1_30 (2-bit). Considers GPIOXDET_EX30 as well as GPIOXDETMODE1_30. NOTE: First bit is GPIOXDET_EX30 Second and third bit is GPIOXDETMODE1_30 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX29 [29] RW Specifies Detect mode when GPIOx29 is in Input mode. It is configured the combination of GPIOXDET_EX29 (1- bit) + GPIOXDETMODE1_29 (2-bit). Considers GPIOXDET_EX29 as well as GPIOXDETMODE1_29. NOTE: First bit is GPIOXDET_EX29 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-29 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Second and third bit is GPIOXDETMODE1_29 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDET_EX28 [28] RW Specifies Detect mode when GPIOx28 is in Input mode. It is configured the combination of GPIOXDET_EX28 (1- bit) + GPIOXDETMODE1_28 (2-bit). Considers GPIOXDET_EX28 as well as GPIOXDETMODE1_28. NOTE: First bit is GPIOXDET_EX28 Second and third bit is GPIOXDETMODE1_28 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX27 [27] RW Specifies Detect mode when GPIOx27 is in Input mode. It is configured the combination of GPIOXDET_EX27 (1- bit) + GPIOXDETMODE1_27 (2-bit). Considers GPIOXDET_EX27 as well as GPIOXDETMODE1_27. NOTE: First bit is GPIOXDET_EX27 Second and third bit is GPIOXDETMODE1_27 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX26 [26] RW Specifies Detect mode when GPIOx26 is in Input mode. It is configured the combination of GPIOXDET_EX26 (1- bit) + GPIOXDETMODE1_26 (2-bit). Considers GPIOXDET_EX26 as well as GPIOXDETMODE1_26. NOTE: First bit is GPIOXDET_EX26 Second and third bit is GPIOXDETMODE1_26 000 = Low Level 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-30 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDET_EX25 [25] RW Specifies Detect mode when GPIOx25 is in Input mode. It is configured the combination of GPIOXDET_EX25 (1- bit) + GPIOXDETMODE1_25 (2-bit). Considers GPIOXDET_EX25 as well as GPIOXDETMODE1_25. NOTE: First bit is GPIOXDET_EX25 Second and third bit is GPIOXDETMODE1_25 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX24 [24] RW Specifies Detect mode when GPIOx24 is in Input mode. It is configured the combination of GPIOXDET_EX24 (1- bit) + GPIOXDETMODE1_24 (2-bit). Considers GPIOXDET_EX24 as well as GPIOXDETMODE1_24. NOTE: First bit is GPIOXDET_EX24 Second and third bit is GPIOXDETMODE1_24 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX23 [23] RW Specifies Detect mode when GPIOx23 is in Input mode. It is configured the combination of GPIOXDET_EX23 (1- bit) + GPIOXDETMODE1_23 (2-bit). Considers GPIOXDET_EX23 as well as GPIOXDETMODE1_23. NOTE: First bit is GPIOXDET_EX23 Second and third bit is GPIOXDETMODE1_23 000 = Low Level 001 = High Level 010 = Falling Edge 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-31 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDET_EX22 [22] RW Specifies Detect mode when GPIOx22 is in Input mode. It is configured the combination of GPIOXDET_EX22 (1- bit) + GPIOXDETMODE1_22 (2-bit). Considers GPIOXDET_EX22 as well as GPIOXDETMODE1_22. NOTE: First bit is GPIOXDET_EX22 Second and third bit is GPIOXDETMODE1_22 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX21 [21] RW Specifies Detect mode when GPIOx21 is in Input mode. It is configured the combination of GPIOXDET_EX21 (1- bit) + GPIOXDETMODE1_21 (2-bit). Considers GPIOXDET_EX21 as well as GPIOXDETMODE1_21. NOTE: First bit is GPIOXDET_EX21 Second and third bit is GPIOXDETMODE1_21 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX20 [20] RW Specifies Detect mode when GPIOx20 is in Input mode. It is configured the combination of GPIOXDET_EX20 (1- bit) + GPIOXDETMODE1_20 (2-bit). Considers GPIOXDET_EX20 as well as GPIOXDETMODE1_20. NOTE: First bit is GPIOXDET_EX20 Second and third bit is GPIOXDETMODE1_20 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-32 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 101 to 111 = Reserved GPIOXDET_EX19 [19] RW Specifies Detect mode when GPIOx19 is in Input mode. It is configured the combination of GPIOXDET_EX19 (1- bit) + GPIOXDETMODE1_19 (2-bit). Considers GPIOXDET_EX19 as well as GPIOXDETMODE1_19. NOTE: First bit is GPIOXDET_EX19 Second and third bit is GPIOXDETMODE1_19 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX18 [18] RW Specifies Detect mode when GPIOx18 is in Input mode. It is configured the combination of GPIOXDET_EX18 (1-bit) + GPIOXDETMODE1_18 (2-bit). Considers GPIOXDET_EX18 as well as GPIOXDETMODE1_18. NOTE: First bit is GPIOXDET_EX18 Second and third bit is GPIOXDETMODE1_18 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX17 [17] RW Specifies Detect mode when GPIOx17 is in Input mode. It is configured the combination of GPIOXDET_EX17 (1- bit) + GPIOXDETMODE1_17 (2-bit). Considers GPIOXDET_EX17 as well as GPIOXDETMODE1_17. NOTE: First bit is GPIOXDET_EX17 Second and third bit is GPIOXDETMODE1_17 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX16 [16] RW Specifies Detect mode when GPIOx16 is in Input mode. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-33 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value It is configured the combination of GPIOXDET_EX16 (1- bit) + GPIOXDETMODE1_16 (2-bit). Considers GPIOXDET_EX16 as well as GPIOXDETMODE1_16. NOTE: First bit is GPIOXDET_EX16 Second and third bit is GPIOXDETMODE1_16 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDET_EX15 [15] RW Specifies Detect mode when GPIOx15 is in Input mode. It is configured the combination of GPIOXDET_EX15 (1- bit) + GPIOXDETMODE0_15 (2-bit). Considers GPIOXDET_EX15 as well as GPIOXDETMODE0_15. NOTE: First bit is GPIOXDET_EX15 Second and third bit is GPIOXDETMODE0_15 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX14 [14] RW Specifies Detect mode when GPIOx14 is in Input mode. It is configured the combination of GPIOXDET_EX14 (1- bit) + GPIOXDETMODE0_14 (2-bit). Considers GPIOXDET_EX14 as well as GPIOXDETMODE0_14. NOTE: First bit is GPIOXDET_EX14 Second and third bit is GPIOXDETMODE0_14 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX13 [13] RW Specifies Detect mode when GPIOx13 is in Input mode. It is configured the combination of GPIOXDET_EX13 (1- bit) + GPIOXDETMODE0_13 (2-bit). 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-34 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Considers GPIOXDET_EX13 as well as GPIOXDETMODE0_13. NOTE: First bit is GPIOXDET_EX13 Second and third bit is GPIOXDETMODE0_13 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDET_EX12 [12] RW Specifies Detect mode when GPIOx12 is in Input mode. It is configured the combination of GPIOXDET_EX12 (1- bit) + GPIOXDETMODE0_12 (2-bit). Considers GPIOXDET_EX12 as well as GPIOXDETMODE0_12. NOTE: First bit is GPIOXDET_EX12 Second and third bit is GPIOXDETMODE0_12 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX11 [11] RW Specifies Detect mode when GPIOx11 is in Input mode. It is configured the combination of GPIOXDET_EX11 (1- bit) + GPIOXDETMODE0_11 (2-bit). Considers GPIOXDET_EX11 as well as GPIOXDETMODE0_11. NOTE: First bit is GPIOXDET_EX11 Second and third bit is GPIOXDETMODE0_11 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX10 [10] RW Specifies Detect mode when GPIOx10 is in Input mode. It is configured the combination of GPIOXDET_EX10 (1- bit) + GPIOXDETMODE0_10 (2-bit). Considers GPIOXDET_EX10 as well as GPIOXDETMODE0_10. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-35 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value NOTE: First bit is GPIOXDET_EX10 Second and third bit is GPIOXDETMODE0_10 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDET_EX9 [9] RW Specifies Detect mode when GPIOx9 is in Input mode. It is configured the combination of GPIOXDET_EX9 (1-bit) + GPIOXDETMODE0_9 (2-bit). Considers GPIOXDET_EX9 as well as GPIOXDETMODE0_9. NOTE: First bit is GPIOXDET_EX9 Second and third bit is GPIOXDETMODE0_9 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX8 [8] RW Specifies Detect mode when GPIOx8 is in Input mode. It is configured the combination of GPIOXDET_EX8 (1-bit) + GPIOXDETMODE0_8 (2-bit). Considers GPIOXDET_EX8 as well as GPIOXDETMODE0_8. NOTE: First bit is GPIOXDET_EX8 Second and third bit is GPIOXDETMODE0_8 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX7 [7] RW Specifies Detect mode when GPIOx7 is in Input mode. It is configured the combination of GPIOXDET_EX7 (1-bit) + GPIOXDETMODE0_7 (2-bit). Considers GPIOXDET_EX7 as well as GPIOXDETMODE0_7. NOTE: First bit is GPIOXDET_EX7 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-36 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value Second and third bit is GPIOXDETMODE0_7 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDET_EX6 [6] RW Specifies Detect mode when GPIOx6 is in Input mode. It is configured the combination of GPIOXDET_EX6 (1-bit) + GPIOXDETMODE0_6 (2-bit). Considers GPIOXDET_EX6 as well as GPIOXDETMODE0_6. NOTE: First bit is GPIOXDET_EX6 Second and third bit is GPIOXDETMODE0_6 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX5 [5] RW Specifies Detect mode when GPIOx5 is in Input mode. It is configured the combination of GPIOXDET_EX5 (1-bit) + GPIOXDETMODE0_5 (2-bit). Considers GPIOXDET_EX5 as well as GPIOXDETMODE0_5. NOTE: First bit is GPIOXDET_EX5 Second and third bit is GPIOXDETMODE0_5 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX4 [4] RW Specifies Detect mode when GPIOx4 is in Input mode. It is configured the combination of GPIOXDET_EX4 (1-bit) + GPIOXDETMODE0_4 (2-bit). Considers GPIOXDET_EX4 as well as GPIOXDETMODE0_4. NOTE: First bit is GPIOXDET_EX4 Second and third bit is GPIOXDETMODE0_4 000 = Low Level 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-37 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDET_EX3 [3] RW Specifies Detect mode when GPIOx3 is in Input mode. It is configured the combination of GPIOXDET_EX3 (1-bit) + GPIOXDETMODE0_3 (2-bit). Considers GPIOXDET_EX3 as well as GPIOXDETMODE0_3. NOTE: First bit is GPIOXDET_EX3 Second and third bit is GPIOXDETMODE0_3 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX2 [2] RW Specifies Detect mode when GPIOx2 is in Input mode. It is configured the combination of GPIOXDET_EX2 (1-bit) + GPIOXDETMODE0_2 (2-bit). Considers GPIOXDET_EX2 as well as GPIOXDETMODE0_2. NOTE: First bit is GPIOXDET_EX2 Second and third bit is GPIOXDETMODE0_2 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 GPIOXDET_EX1 [1] RW Specifies Detect mode when GPIOx1 is in Input mode. It is configured the combination of GPIOXDET_EX1 (1-bit) + GPIOXDETMODE0_1 (2-bit). Considers GPIOXDET_EX1 as well as GPIOXDETMODE0_1. NOTE: First bit is GPIOXDET_EX1 Second and third bit is GPIOXDETMODE0_1 000 = Low Level 001 = High Level 010 = Falling Edge 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-38 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved GPIOXDET_EX0 [0] RW Specifies Detect mode when GPIOx0 is in Input mode. It is configured the combination of GPIOXDET_EX0 (1-bit) + GPIOXDETMODE0_0 (2-bit). Considers GPIOXDET_EX0 as well as GPIOXDETMODE0_0. NOTE: First bit is GPIOXDET_EX0 Second and third bit is GPIOXDETMODE0_0 000 = Low Level 001 = High Level 010 = Falling Edge 011 = Rising Edge 100 = Both(Rising & Falling) Edge 101 to 111 = Reserved 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 15 GPIO Controller 15-39 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4.1.11 GPIOxDETENB

15.4.1.12 GPIOx_SLEW

S5P4418_UM 15 GPIO Controller 15-40 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4.1.13 GPIOx_SLEW_DISABLE_DEFAULT

15.4.1.14 GPIOx_DRV1

S5P4418_UM 15 GPIO Controller 15-41 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4.1.15 GPIOx_DRV1_DISABLE_DEFAULT

15.4.1.16 GPIOx_DRV0

S5P4418_UM 15 GPIO Controller 15-42 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4.1.17 GPIOx_DRV0_DISABLE_DEFAULT

15.4.1.18 GPIOx_PULLSEL

S5P4418_UM 15 GPIO Controller 15-43 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

15.4.1.19 GPIOx_PULLSEL_DISABLE_DEFAULT

15.4.1.20 GPIOx_PULLENB

15.4.1.21 GPIOx_PULLENB_DISABLE_DEFAULT

S5P4418_UM 15 GPIO Controller Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 0 = Use Default Pull Enb 1 = Use GPIOx_PULLENB Value cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-1 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16 Ethernet MAC

16.1 Overview

The GMAC enables a host to transmit and receive data over Ethernet in compliance with the IEEE802.3 -2008 standard. EMAC supports 10/100/1000Mbps data transfer rates, and it has Reduced Gigabit Media Independent Interface (RGMII) with External PHY chip.

16.1.1 MAC Core Features

 Supports 10/100/1000 Mbps data transfer rates with the following phy interfaces:  RGMII interface to communicate with an external gigabit PHY  Supports both full-duplex and half-duplex operation  Automatic CRC and pad generation controllable on receive frames  Programmable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16KB  Programmable Inter Frame Gap (40-96 bit times in steps of 8)  Support a variety of flexible address filtering mode  Separate transmission, reception, and control interface to the Application9  MDIO Master Interface for PHY device configuration and management  Compliant to the following standards:  IEEE 802.3 - 2002 for Ethernet MAC  IEEE 1588 - 2002 standard for precision networked clock synchronization  RGMII specification version 2.0 from HP/Marvell. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-2 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.1.2 DMA Block Features

 32/64/128-bit data transfer  Single-channel Transmit and Receive engines  Optimization for packet-oriented DMA transfers with frame delimiters  Byte-aligned addressing for data buffer support  Descriptor architectures, allowing large blocks of data transfer with minimum CPU intervention; each descriptor can transfer up to 8 KB of data  Individual programmable burst size for Transmit and Receive DMA Engines for optimal host bus utilization  Programmable interrupt options for different operational conditions  Per-frame Transmit/Receive complete interrupt control  Round-robin or fixed-priority arbitration between Receive and Transmit Engines  Start/Stop mode  Separate port for host CSR (Control and Status Register) access and host data interface cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-3 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.2 Block Diagram

Figure 16-1 Block Diagram of the Ethernet MAC cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-4 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Figure 16-2 RGMII Interface between MAC and Gigabit Ethernet PHY cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-5 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3 Register Description

16.3.1 Register Map Summary

 Base Address: C006_1000h (MAC DMA) Register Offset Description Reset Value MAC DMA Ethernet MAC DMA register 0 0x00h Bus Mode Register 0x0000_0101 Ethernet MAC DMA register 1 0x04h Transmit Poll Demand Register 0x0000_0000 Ethernet MAC DMA register 2 0x08h Receive Poll Demand Register 0x0000_0000 Ethernet MAC DMA register 3 0x0Ch Receive Descriptor List Address Register 0x0000_0000 Ethernet MAC DMA register 4 0x10h Transmit Descriptor List Address Register 0x0000_0000 Ethernet MAC DMA register 5 0x14h Status Register 0x0000_0000 Ethernet MAC DMA register 6 0x18h Operation Mode Register 0x0000_0000 Ethernet MAC DMA register 7 0x1Ch Interrupt Enable Register 0x0000_0000 Ethernet MAC DMA register 8 0x20h Missed Frame and Buffer Overflow Control Register 0x0000_0000 RSVD 0x24h to 0x44h Reserved – Ethernet MAC DMA register 18 0x48h Current Host Transmit Descriptor Register 0x0000_0000 Ethernet MAC DMA register 19 0x4Ch Current Host Receive Descriptor Register 0x0000_0000 Ethernet MAC DMA register 20 0x50h Current Host Transmit Buffer Address Register 0x0000_0000 Ethernet MAC DMA register 21 0x54h Current Host Receive Buffer Address Register 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-6 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.  Base Address: C006_0000h (MAC Core) Register Offset Description Reset Value MAC Core Ethernet MAC Register 0 0x00h MAC Configuration Register 0x0000_0000 Ethernet MAC Register 1 0x04h MAC Frame Filter Register 0x0000_0000 Ethernet MAC Register 2 0x08h Hash Table High Register 0x0000_0000 Ethernet MAC Register 3 0x0Ch Hash Table Low Register 0x0000_0000 Ethernet MAC Register 4 0x10h GMII Address Register 0x0000_0000 Ethernet MAC Register 5 0x14h GMII Data Register 0x0000_0000 Ethernet MAC Register 6 0x18h Flow Control Register 0x0000_0000 Ethernet MAC Register 7 0x1Ch VALN Tag Register 0x0000_0000 Ethernet MAC Register 8 0x20h Version Register 0x0000_0037 Ethernet MAC Register 9 0x24h Debug Register 0x0000_0000 RSVD 0x28h to 0x34h Reserved – Ethernet MAC Register 14 0x38h Interrupt Status Register 0x0000_0000 Ethernet MAC Register 15 0x3Ch Interrupt Mask Register 0x0000_0000 Ethernet MAC Register 16 0x40h MAC Address0 High Register 0x0000_FFFF Ethernet MAC Register 17 0x44h MAC Address0 Low Register 0xFFFF_FFFF Ethernet MAC Register 18 0x48h MAC Address1 High Register 0x0000_FFFF Ethernet MAC Register 19 0x4Ch MAC Address1 Low Register 0xFFFF_FFFF Ethernet Mac Register 20 ~ 47 0x50h to 0xBCh MAC Address1 High Register MAC Address1 Low Register 0x0000_FFFF 0xFFFF_FFFF Ethernet MAC Register 48 0xC0h AN Control Register 0x0000_0000 Ethernet MAC Register 49 0xC4h AN Status Register 0x0000_0000 Ethernet MAC Register 50 0xC8h Auto-Negotiation Advertisement Register 0x0000_0000 Ethernet MAC Register 51 0xCCh Auto-Negotiation Link Partner Ability Register 0x0000_0000 Ethernet MAC Register 52 0xD0h Auto-Negotiation Expansion Register 0x0000_0000 Ethernet MAC Register 53 0xD4h TBI Extended Status Register 0x0000_0000 Ethernet MAC Register 54 0xD8h SGMII/RGMII/SMII Control and Status Register 0x0000_0000 RSVD 0xE0h to 0x6FCh Reserved – Ethernet MAC Register 448 0x700h Time Stamp Control Register 0x0000_0000 Ethernet MAC Register 449 0x704h Sub-Second Increment Register 0x0000_0000 Ethernet MAC Register 450 0x708h System Time - Second Register 0x0000_0000 Ethernet MAC Register 451 0x70Ch System Time - Nano second Register 0x0000_0000 Ethernet MAC Register 452 0x710h System Time - Second Update 0x0000_0000 Ethernet MAC Register 453 0x714h System Time - Nano Second Update Register 0x0000_0000 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-7 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Register Offset Description Reset Value Ethernet MAC Register 454 0x718h Timestamp Addend Register 0x0000_0000 Ethernet MAC Register 455 0x71Ch Target Time Second Register 0x0000_0000 Ethernet MAC Register 456 0x720h Target Time Nano Second Register 0x0000_0000 Ethernet MAC Register 457 0x724h System Time - Higher Word Seconds Register 0x0000_0000 Ethernet MAC Register 458 0x728h Timestamp Status Register 0x0000_0000 RSVD 0x72Ch to 0x7FCh Reserved – Ethernet MAC Register 512 ~ 543 0x800h to 0x87Ch MAC Address1 High Register MAC Address1 Low Register 0x0000_FFFF 0xFFFF_FFFF cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-8 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.1 MAC DMA Register

16.3.1.1.1 Ethernet MAC DMA Register 0

 Base Address: C006_1000h  Address = Base Address + 0x00h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RIB [31] RW Rebuild INCRx Burst When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. This bit is valid only in the GMAC-AHB configuration. It is reserved in all other configuration. 1'b0 RSVD [30] – Reserved 1'b0 PRWG [29:28] RW Channel Priority Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. 00 = The priority weight is 1. 01 = The priority weight is 2. 10 = The priority weight is 3. 11 = The priority weight is 4. This field is present in all DWC_GMAC configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). 2'b0 TXPR [27] RW Transmit Priority When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). 1'b0 MB [26] RW Mixed Burst When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. 1'b0 AAL [25] RW Address-Aligned Beats When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-9 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value PBLX8 [24] RW PBLx8 Mode When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64,128, and 256 beats depending on the PBL value. 1'b0 USP [23] RW Use Separate PBL When set high, this bit configures the Rx DMA to use the value configured in Bits[22:17] as PBL. The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. 1'b0 RPBL [22:17] RW Rx DMA PBL This field indicates the maximum number of beats to be transferred in one RxDMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. 6'h10 FB [16] RW Fixed Burst This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8,or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. For more information, see Bit 0 (UNDEF) of the AXI Bus Mode register in the GMAC-AXI configuration. 1'b0 PR [15:14] RW Priority Ratio These bits control the priority ratio in the weighted round- robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. 00 = The Priority Ratio is 1:1. 01 = The Priority Ratio is 2:1. 10 = The Priority Ratio is 3:1. 11 = The Priority Ratio is 4:1. In the GMAC-AXI configuration, these bits are reserved and read-only (RO). 2'b0 PBL [13:8] RW Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The 6'h01 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-10 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps: Set the PBLx8 mode. Set the PBL. For example, if the maximum number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL to 8. The PBL values have the following limitation: The maximum number of possible beats (PBL) is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified. ATDS [7] RW Alternate Descriptor Size When set, the size of the alternate descriptor increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and anyone of the following features during core configuration:  Advanced Timestamp feature  IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). This bit preserves the backward compatibility for the descriptor size. In versions prior to 3.50a, the descriptor size is 16 bytes for both normal and enhanced descriptors. In version 3.50a, descriptor size is increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features. 1'b0 DSL [6:2] RW Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring 5'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-11 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value mode. DA [1] RW DMA Arbitration Scheme This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. 0 = Weighted round-robin with Rx:Tx or Tx:Rx - The priority between the paths is according to the priority specified in Bits[15:14] (PR) and priority weights specified in Bit[27] (TXPR). 1 = Fixed priority - The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. In the GMAC-AXI configuration, these bits are reserved and are read-only (RO). 1'b0 SWR [0] RW Software Reset When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the DWC_GMAC clock domains. Before reprogramming any register of the DWC_GMAC, you should read a zero (0) value in this bit. NOTE:  The Software reset function is driven only by this bit. Bit[0] of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function.  The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. The time to complete the software reset operation depends on the frequency of the slowest active clock. 1'b1 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-12 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.1.2 Ethernet MAC DMA Register 1

 Base Address: C006_1000h  Address = Base Address + 0x04h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value TPD [31:0] RW Transmit Poll Demand When these bits are written with any value, the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. If the descriptor is available, the transmission resumes. When this register is read, it always returns zero. 32'b0

16.3.1.1.3 Ethernet MAC DMA Register 2

 Base Address: C006_1000h  Address = Base Address + 0x08h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RPD [31:0] RW Receive Poll Demand When these bits are written with any value, the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. If that descriptor is not available (owned by the Host), the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. If the descriptor is available, the Rx DMA returns to the active state. When this register is read, it always returns zero. 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-13 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.1.4 Ethernet MAC DMA Register 3

 Base Address: C006_1000h  Address = Base Address + 0x0Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RDESLA [31:0] RW Start of Receive List This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). 32'b0

16.3.1.1.5 Ethernet MAC DMA Register 4

 Base Address: C006_1000h  Address = Base Address + 0x10h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value TDESLA [31:0] RW Start of Transmit List This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-14 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.1.6 Ethernet MAC DMA Register 5

 Base Address: C006_1000h  Address = Base Address + 0x14h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31] – Reserved 1'b0 GLPII/GTMSI [30] R GLPII: GMAC LPI Interrupt (for Channel 0) This bit indicates an interrupt event in the LPI logic of the MAC. To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_GMAC to get the exact cause of the interrupt and clear its source. NOTE: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_GMAC. To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. NOTE: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. 1'b0 TTI [29] R Timestamp Trigger Interrupt This bit indicates an interrupt event in the Timestamp Generator block of the DWC_GMAC. The software must read the corresponding registers in the DWC_GMAC to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the DWC_GMAC subsystem (sbd_intr_o) is high. This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. 1'b0 GPI [28] R GMAC PMT Interrupt This bit indicates an interrupt event in the PMT module of the DWC_GMAC. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0. The interrupt signal from the DWC_GMAC subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the Power Management feature is enabled. Otherwise, this bit is reserved. NOTE: The GPI and pmt_intr_o interrupts are generated in 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-15 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value different clock domains. GMI [27] R GMAC MMC Interrupt This bit reflects an interrupt event in the MMC module of the DWC_GMAC. The software must read the corresponding registers in the DWC_GMAC to get the exact cause of the interrupt and clear the source of interrupt to make this bit as1'b0. The interrupt signal from the DWC_GMAC subsystem (sbd_intr_o) is high when this bit is high. This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. 1'b0 GLI [26] R GMAC Line Interface Interrupt When set, this bit reflects any of the following interrupt events in the DWC_GMAC interfaces (if present and enabled in your configuration):  PCS (TBI, RTBI, or SGMII): Link change or auto- negotiation complete event  SMII or RGMII: Link change event  General Purpose Input Status (GPIS): Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, the software must first read Bit 11and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), read any of the following corresponding registers:  PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register)  SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register)  General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_GMAC subsystem (sbd_intr_o) is high when this bit is high. 1'b0 EB [25:23] R Error Bits This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI)is set. This field does not generate an interrupt. 0 0 0: Error during Rx DMA Write Data Transfer 0 1 1: Error during Tx DMA Read Data Transfer 1 0 0: Error during Rx DMA Descriptor Write Access 1 0 1: Error during Tx DMA Descriptor Write Access 1 1 0: Error during Rx DMA Descriptor Read Access 1 1 1: Error during Tx DMA Descriptor Read Access NOTE: 001 and 010 are reserved. 3'b0 TS [22:20] R Transmit Process State This field indicates the Transmit DMA FSM state. This field 3'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-16 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value does not generate an interrupt. 3'b000: Stopped; Reset or Stop Transmit Command issued 3'b001: Running; Fetching Transmit Transfer Descriptor 3'b010: Running; Waiting for status 3'b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) 3'b100: TIME_STAMP write state 3'b101: Reserved for future use 3'b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow 3'b111: Running; Closing Transmit Descriptor RS [19:17] R Receive Process State This field indicates the Receive DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped: Reset or Stop Receive Command issued 3'b001: Running: Fetching Receive Transfer Descriptor 3'b010: Reserved for future use 3'b011: Running: Waiting for receive packet 3'b100: Suspended: Receive Descriptor Unavailable 3'b101: Running: Closing Receive Descriptor 3'b110: TIME_STAMP write state 3'b111: Running: Transferring the receive packet data from receive buffer to host memory 3'b0 NIS [16] RW Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register):  Register 5[0]: Transmit Interrupt  Register 5[2]: Transmit Buffer Unavailable  Register 5[6]: Receive Interrupt  Register 5[14]: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. 1'b0 AIS [15] RW Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register):  Register 5[1]: Transmit Process Stopped  Register 5[3]: Transmit Jabber Timeout  Register 5[4]: Receive FIFO Overflow  Register 5[5]: Transmit Underflow  Register 5[7]: Receive Buffer Unavailable 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-17 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value  Register 5[8]: Receive Process Stopped  Register 5[9]: Receive Watchdog Timeout  Register 5[10]: Early Transmit Interrupt  Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. ERI [14] RW Early Receive Interrupt This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). 1'b0 TBI [13] RW Fatal Bus Error Interrupt This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. 1'b0 RSVD [12:11] – Reserved 2'b0 ETI [10] RW Early Transmit Interrupt This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. 1'b0 RWT [9] RW Receive Watchdog Timeout When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. 1'b0 RPS [8] RW Receive Process Stopped This bit is asserted when the Receive Process enters the Stopped state. 1'b0 RU [7] RW Receive Buffer Unavailable This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. 1'b0 RI [6] RW Receive Interrupt This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor. The reception remains in the Running state. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-18 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value UNF [5] RW Transmit Underflow This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. 1'b0 OVF [4] RW Receive Overflow This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. 1'b0 TJT [3] RW Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled).When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. 1'b0 TU [2] RW Transmit Buffer Unavailable This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-19 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.1.7 Ethernet MAC DMA Register 6

 Base Address: C006_1000h  Address = Base Address + 0x18h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:27] – Reserved 5'b0 DT [26] RW Disable Dropping of TCP/IP Checksum Error Frames When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). 1'b0 RSF [25] RW Receive Store and Forward When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. 1'b0 DFF [24] RW Disable Flushing of Received Frames When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. This bit is reserved (and RO) in the GMAC-MTL configuration. 1'b0 RFA_2 [23] RW MSB of Threshold for Activating Flow Control If the DWC_GMAC is configured for an Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half duplex and full-duplex modes. This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: 100 = Full minus 5 KB, that is, FULL - 5 KB 101 = Full minus 6 KB, that is, FULL - 6 KB 110 = Full minus 7 KB, that is, FULL - 7 KB 111 = Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. 1'b0 RFD_2 [22] RW MSB of Threshold for Deactivating Flow Control If the DWC_GMAC is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full- duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: 100 = Full minus 5 KB, that is, FULL - 5 KB 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-20 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 101 = Full minus 6 KB, that is, FULL - 6 KB 110 = Full minus 7 KB, that is, FULL - 7 KB 111 = Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. TSF [21] RW Transmit Store and Forward When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits [16:14] are ignored. This bit should be changed only when the transmission is stopped. 1'b0 TFT [20] RW Flush Transmit FIFO When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. NOTE: The flush operation is complete only when the Tx FIFO is emptied of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. In order to complete this flush operation, the PHY transmit clock (clk_tx_i) is required to be active. 1'b0 RSVD [19:17] – Reserved 3'b0 TTC [16:14] RW Transmit Threshold Control These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the In addition, full frames with a length less than the threshold are also These bits are used only when Bit 21 (TSF) is reset. 000 = 64 001 = 128 010 = 192 011 = 256 100 = 40 101 = 32 110 = 24 111 = 16 3'b0 ST [13] RW Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-21 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5(Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4(Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. RFD [12:11] RW Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. 00 = Full minus 1 KB, that is, FULL - 1 KB 01 = Full minus 2 KB, that is, FULL - 2 KB 10 = Full minus 3 KB, that is, FULL - 3 KB 11 = Full minus 4 KB, that is, FULL - 4 KB The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. NOTE: For proper flow control, the value programmed in the "RFD_2, RFD" fields should be equal to or more than the value programmed in the "RFA_2, RFA" fields. 2'b0 RFA [10:9] RW Threshold for Activating Flow Control (in half-duplex and full- duplex modes) These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. 00 = Full minus 1 KB, that is, FULL-1KB. 01 = Full minus 2 KB, that is, FULL-2KB. 10 = Full minus 3 KB, that is, FULL-3KB. 11 = Full minus 4 KB, that is, FULL-4KB. These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8(EFC) is set high. If the Rx FIFO is 8 KB 2'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-22 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. NOTE: When FIFO size is exactly 4 KB, although the DWC_GMAC allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition. EFC [8] RW Enable HW Flow Control When this bit is set, the flow control signal operation based on the fill-level of RxFIFO is enabled. When reset, the flow control operation is disabled. This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. 1'b0 FEF [7] RW Forward Error Frames When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. NOTE: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status in the following configurations:  The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected.  The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features: L3-L4 filter in GMAC-CORE or GMAC-MTL configurations Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC- AXI configurations. 1'b0 FUF [6] RW Forward Undersized Good Frames When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-23 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value lower value of Receive Threshold, for example, RTC = 01. DGF [5] RW Drop Giant Frames When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO. NOTE: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default:  Configurations in which IP Checksum Offload (Type 1) is selected in Rx  Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format  Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). 1'b0 RTC [4:3] RW Threshold Control These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are automatically transferred. The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. 00 = 64 01 = 32 10 = 96 11 = 128 2'b0 OSF [2] RW Operate on Second Frame When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. 2'b0 SR [1] RW Start or Stop Receive When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only 2'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-24 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. RSVD [0] – Reserved 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.1.8 Ethernet MAC DMA Register 7

 Base Address: C006_1000h  Address = Base Address + 0x1Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:17] – Reserved 15'b0 NIE [16] RW Normal Interrupt Summary Enable When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): Register 5[0]: Transmit Interrupt Register 5[2]: Transmit Buffer Unavailable Register 5[6]: Receive Interrupt Register 5[14]: Early Receive Interrupt 1'b0 AIE [15] RW Abnormal Interrupt Summary Enable When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register): Register 5[1]: Transmit Process Stopped Register 5[3]: Transmit Jabber Timeout Register 5[4]: Receive Overflow Register 5[5]: Transmit Underflow Register 5[7]: Receive Buffer Unavailable Register 5[8]: Receive Process Stopped Register 5[9]: Receive Watchdog Timeout Register 5[10]: Early Transmit Interrupt Register 5[13]: Fatal Bus Error 1'b0 ERE [14] RW Early Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. 1'b0 FBE [13] RW Fatal Bus Error Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. 1'b0 RSVD [12:11] – Reserved 2'b0 ETE [10] RW Early Transmit Interrupt Enable When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. 1'b0 RWE [9] RW Receive Watchdog Timeout Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-26 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. RSE [8] RW Receive Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. 1'b0 RUE [7] RW Receive Buffer Unavailable Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. 1'b0 RIE [6] RW Receive Interrupt Enable When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. 1'b0 UNE [5] RW Underflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. 1'b0 OVE [4] RW Overflow Interrupt Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. 1'b0 THE [3] RW Transmit Jabber Timeout Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. 1'b0 TUE [2] RW Transmit Buffer Unavailable Enable When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. 1'b0 TSE [1] RW Transmit Stopped Enable When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. 1'b0 TIE [0] RW Transmit Interrupt Enable When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-27 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.1.9 Ethernet MAC DMA Register 8

 Base Address: C006_1000h  Address = Base Address + 1020h, Reset Value = Name Bit Type Description Reset Value RSVD [31:29] – Reserved 3'b0 OVFCNTOVF [28] RW Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow Frame Counter (Bits[27:17])overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. 1'b0 OVFFRMCNT [27:17] RW Overflow Frame Counter This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1'b1. 11'b0 MISCNTOVF [16] RW Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zero sand this bit indicates that the rollover happened. 1'b0 MISFRMCNT [15:0] RW Missed Frame Counter This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1'b1. 16'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-28 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.1.10 Ethernet MAC DMA Register 18

 Base Address: C006_1000h  Address = Base Address + 0x48h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value CURTDESAPTR [31:0] RW Host Transmit Descriptor Address Pointer Cleared on Reset. Pointer updated by the DMA during operation. 32'b0

16.3.1.1.11 Ethernet MAC DMA Register 19

 Base Address: C006_1000h  Address = Base Address + 0x4Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value CURRDESAPTR [31:0] RW Host Receive Descriptor Address Pointer Cleared on Reset. Pointer updated by the DMA during operation. 32'b0

16.3.1.1.12 Ethernet MAC DMA Register 20

 Base Address: C006_1000h  Address = Base Address + 0x50h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value CURTBUFAPTR [31:0] RW Host Transmit Buffer Address Pointer Cleared on Reset. Pointer updated by the DMA during operation. 32'b0

16.3.1.1.13 Ethernet MAC DMA Register 21

 Base Address: C006_1000h  Address = Base Address + 0x54h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value CURRBUFAPTR [31:0] RW Host Receive Buffer Address Pointer Cleared on Reset. Pointer updated by the DMA during operation. 32'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-29 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.2 MAC Core Register

16.3.1.2.1 Ethernet MAC Register 0

 Base Address: C006_0000h  Address = Base Address + 0x00h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31] – Reserved 1'b0 SARC [30:28] RW Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. 2'b10: If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0registers (registers 16 and 17) in the SA field of all transmitted frames. If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. 2'b11: If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0registers (registers 16 and 17) in the SA field of all transmitted frames. If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. NOTE:  Changes to this field take effect only on the start of a frame. If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value.  These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. 3'b0 TWOKPE [27] RW IEEE 802.3as Support for 2K Packets When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522bytes for tagged) as Giant frames. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-30 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value When Bit 20 is set, setting this bit has no effect on Giant Frame status. SFTERR [26] RW SMII Force Transmit Error When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. 1'b0 CST [25] RW CRC Stripping for Type Frames When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. 1'b0 TC [24] RW Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the transmission of duplex mode, link speed, and linkup or down information to the PHY in the RGMII, SMII, or SGMII port. When this bit is reset, no such information is driven to the PHY. This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. 1'b0 wd [23] RW Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,384 bytes. When this bit is reset, the MAC does not allow a receive frame which more than 2,048 bytes (10,240 if JE is set high) or the value programmed in Register 55(Watchdog Timeout Register). The MAC cuts off any bytes received after the watchdog limit number of bytes. 1'b0 JD [22] RW Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,384 bytes. When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. 1'b0 be [21] RW Frame Burst Enable When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex- only configurations. 1'b0 JE [20] RW Jumbo Frame Enable When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-31 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value reporting a giant frame error in the receive frame status. IFG [19:17] RW Inter-Frame Gap These bits control the minimum IFG between frames during transmission. 000 = 96-bit times 001 = 88-bit times 010 = 80-bit times 111 = 40-bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC- CORE configuration and 80 bit times (and above) in other configurations. 3'b0 DCRS [16] RW Disable Carrier Sense During Transmission When set high, this bit makes the MAC transmitter ignore the (G) MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. This bit is reserved (and RO) in the full-duplex-only configurations. 1'b0 PS [15] RW Port Select This bit selects the Ethernet line speed. 0 = For 1000 Mbps operations 1 = For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default10/100/1000 Mbps configuration, this bit is R_W. The mac_portselect_o ormac_speed_o[1] signal reflects the value of this bit. 1'b0 FES [14] RW Speed This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMIIinterface: 0 = 10 Mbps 1 = 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. This bit generates link speed encoding when Bit 24(TC) is set in the RGMII, SMII, or SGMII mode. This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. In configurations with RGMII, SGMII, SMII, or RevMII 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-32 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. DO [13] RW Disable Receive Own When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full- duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. 1'b0 LM [12] RW Loopback Mode When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G) MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. 1'b0 DM [11] RW Duplex Mode When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex- only configuration. 1'b0 IPC [10] RW Checksum Offload When this bit is set, the MAC calculates the 16-bit one's complement of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25-26 or 29-30 (VLAN tagged)of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bitchecksum calculated for the IP header datagram payload (bytes after the IPv4header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset, this function is disabled. When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. When this bit is reset, the COE function in the receiver is disabled and the corresponding PCE and IP HCE status bits are always cleared. If the IP Checksum Offload feature is not enabled during core configuration, this bit is reserved (RO with default value). 1'b0 DR [9] RW Disable Retry 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-33 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex mode and is reserved (RO with default value) in the full-duplex-only configuration. LUD [8] RW Link Up or Down This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: 0 = Link Down 1 = Link Up This bit is reserved (RO with default value) and is enabled when the RGMII, SGMII, or SMII interface is enabled during core configuration. 1'b0 ACS [7] RW Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. Note: For information about how the settings of Bit 23 (CST) and this bit impact the frame length 1'b0 BL [6:5] RW Back-Off Limit The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half- duplex mode and is reserved (RO)in the full-duplex-only configuration. 00: k= min (n, 10) 01: k = min (n, 8) 10: k = min (n, 4) 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0  r < 2k 2'b0 DC [4] RW Deferral Check When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288-bit times in the 10 or 100 Mbps 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-34 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value mode. If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. For example, if the transmitter defers for 10,000bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0 and it is restarted. When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. TE [3] RW Transmitter Enable When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. 1'b0 RE [2] RW Receiver Enable When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. 1'b0 PRELEN [1:0] RW Preamble Length for Transmit frames These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. 2'b00 = 7 bytes of preamble 2'b01 = 5 bytes of preamble 2'b10 = 3 bytes of preamble 2'b11 = Reserved 2'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-35 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.2.2 Ethernet MAC Register 1

 Base Address: C006_0000h  Address = Base Address + 0x04h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RA [31] RW Receive All When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter. 1'b0 RSVD [30:22] – Reserved 9'b0 DNTU [21] RW Drop non-TCP/UDP over IP Frames When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. If the Layer 3 and Layer 4 Filtering feature is not selected during core configuration, this bit is reserved (RO with default value). 1'b0 IPFE [20] RW Layer 3 and Layer 4 Filter Enable When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. If the Layer 3 and Layer 4 Filtering feature is not selected during core configuration, this bit is reserved (RO with default value). 1'b0 RSVD [19:17] – Reserved 3'b0 VTFE [16] RW VLAN Tag Filter Enable When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. 1'b0 RSVD [15:11] – Reserved 5'b0 HPF [10] RW Hash or Perfect Filter When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. This bit 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-36 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value is reserved (and RO) if the Hash filter is not selected during core configuration. SAF [9] RW Source Address Filter Enable When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. NOTE: According to the IEEE specification, Bit 47 of the SA is reserved and set to 0.However, in DWC_GMAC, the MAC compares all 48 bits. The software driver should take this into consideration while programming the MAC address registers for SA. 1'b0 SAIF [8] RW SA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. 1'b0 PCF [7:6] RW Pass Control Frames These bits control the forwarding of all control frames (including uni-cast and multicast Pause frames). 00 = MAC filters all control frames from reaching the application. 01 = MAC forwards all control frames except Pause frames to application even if they fail the Address filter. 10 = MAC forwards all control frames to application even if they fail the Address Filter. 11 = MAC forwards control frames that pass the Address Filter. The following conditions should be true for the Pause frames processing:  Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1.  Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register6 (Flow Control Register) is set.  Condition 3: The Type field of the received frame is 0x8808 and the OPCODE Field is 0x0001. NOTE: This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the Pause frame filtering may be 2'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-37 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value inconsistent. When Condition 1 is false, the Pause frames are considered as generic control frames. Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application). DBF [5] RW Disable Broadcast Frames When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM module passes all received broadcast frames. 1'b0 PM [4] RW Pass All Multicast When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is 1) are passed. When reset, filtering of multicast frame depends on HMC bit. 1'b0 DAIF [3] RW DA Inverse Filtering When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset, normal filtering of frames is performed. 1'b0 HMC [2] RW Hash Multicast When set, MAC performs destination address filtering of received multicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. If Hash Filter is not selected during core configuration, this bit is reserved (and RO). 1'b0 HUC [1] RW Hash Unicast When set, MAC performs destination address filtering of unicast frames according to the hash table. When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. If Hash Filter is not selected during core configuration, this bit is reserved (and RO). 1'b0 PR [0] RW Promiscuous Mode When this bit is set, the Address Filter module passes all incoming frame sir respective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-38 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.2.3 Ethernet MAC Register 2

 Base Address: C006_0000h  Address = Base Address + 0x08h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value HTH [31:0] RW Hash Table High. This field contains the upper 32 bits of the Hash table. 32'b0

16.3.1.2.4 Ethernet MAC Register 3

 Base Address: C006_0000h  Address = Base Address + 0x0Ch, Reset Value = Name Bit Type Description Reset Value HTL [31:0] RW Hash Table Low. This field contains the lower 32 bits of the Hash table. 32'b0

16.3.1.2.5 Ethernet MAC Register 4

 Base Address: C006_0000h  Address = Base Address + 0010h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] – Reserved 16'b0 PA [15:11] RW Physical Layer Address This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. 5'b0 GR [10:6] RW GMII Register These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. 5'b0 CR [5:2] RW CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. The CSR clock corresponding to different GMAC configurations. The suggested range of CSR clock frequency applicable for each value (when Bit[5]= 0) ensures that the MDC clock is approximately between the frequency range1.0 MHz-2.5MHz. 0000 = The CSR clock frequency is 60-100 MHz and the MDC clock frequency is CSR clock/42. 0001 = The CSR clock frequency is 100-150 MHz and the MDC clock frequency is CSR clock/62. 0010 = The CSR clock frequency is 20-35 MHz and the MDC clock frequency is CSR clock/16. 4'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-39 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 0011 = The CSR clock frequency is 35-60 MHz and the MDC clock frequency is CSR clock/26. 0100 = The CSR clock frequency is 150-250 MHz and the MDC clock frequency is CSR clock/102. 0101 = The CSR clock frequency is 250-300 MHz and the MDC clock is CSR clock/124. 0110, 0111 = Reserved When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the following values only if the interfacing chips support faster MDC clocks. 1000 = CSR clock/4 1001 = CSR clock/6 1010 = CSR clock/8 1011 = CSR clock/10 1100 = CSR clock/12 1101 = CSR clock/14 1110 = CSR clock/16 1111 = CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. GW [1] RW GMII Write When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register. 1'b0 GB [0] RW GMII Busy This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present. 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-40 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.2.6 Ethernet MAC Register 5

 Base Address: C006_0000h  Address = Base Address + 0x14h, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:16] – Reserved 16'b0 GD [15:0] RW GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation or the 16- bit data value to be written to the PHY or RevMII before a Management Write operation. 16'b0

16.3.1.2.7 Ethernet MAC Register 6

 Base Address: C006_0000h  Address = Base Address + 0018h, Reset Value = Name Bit Type Description Reset Value PT [31:16] RW Pause Time This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain 16'b0 RSVD [15:8] – Reserved 8'b0 DZQP [7] RW Disable Zero-Quanta Pause When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signals bd_flowctrl_i/mti_flowctrl_i). When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. 1'b0 RSVD [6] – Reserved 1'b0 PLT [5:4] RW Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 - 28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: 2'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-41 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value 00 = The threshold is Pause time minus 4 slot times (PT - 4 slot times). 01 = The threshold is Pause time minus 28 slot times (PT - 28 slot times). 10 = The threshold is Pause time minus 144 slot times (PT - 144 slot times). 11 = The threshold is Pause time minus 256 slot times (PT - 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. UP [3] RW Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set, the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. When this bit is reset, the MAC only detects Pause frames with unique multicast address. NOTE: The MAC does not process a Pause frame if the multicast address of received frame is different from the unique multicast address. 1'b0 PFE [2] RW Receive Flow Control Enable When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. 1'b0 TFE [1] RW Transmit Flow Control Enable In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. 1'b0 FCP_BPA [0] RW Flow Control Busy or Backpressure Activate This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is 1'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-42 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. Name Bit Type Description Reset Value cleared. In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically O Red with the mti_flowctrl_iinput signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

S5P4418_UM 16 Ethernet MAC 16-43 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.

16.3.1.2.8 Ethernet MAC Register 7

 Base Address: C006_0000h  Address = Base Address + 0x1Ch, Reset Value = 0x0000_0000 Name Bit Type Description Reset Value RSVD [31:20] – Reserved 12'b0 VTHM [19] RW VLAN Tag Hash Table Match Enable When set, the most significant four bits of the VLAN tag's CRC are used to index the content of Register 354 (VLAN Hash Table Register). A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. If the VLAN Hash feature is not enabled during core configuration, this bit is reserved (RO with default value). 1'b0 ESVL [18] RW Enable S-VLAN When this bit is set, the MAC transmitter and receiver also consider the S-VLAN(Type = 0x88A8) frames as valid VLAN tagged frames. 1'b0 VTIM [17] RW VLAN Tag Inverse Match Enable When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. The frames with matched VLAN Tag are marked as matched. 1'b0 ETV [16] RW Enable 12-Bit VLAN Tag Comparison When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. 1'b0 VL [15:0] RW VLAN Tag Identifier for Receive Frames This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. The following list describes the bits of this field: Bits [15:13]: User Priority 16'b0 cn / Splendid_wu at 2014.10.27 SAMSUNG Confidential

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S5P4418 specifications and overview.

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Application Processor

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Application Processor

Source title S5P4418 Datasheet(PDF) - Samsung semiconductor

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