S5K711CA SAMSUNG | Alldatasheet
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1/7 INCH CIF CMOS IMAGE SENSOR S5K711CA, S5K711LA S5K711CA, S5K711LA (1/7” CIF CMOS Image Sensor) Preliminary Specification Revision 0.2 Apr. 2002
S5K711CA, S5K711LA 1/7” CIF CMOS IMAGE SENSOR DOCUMENT TITLE 1/7” Optical Size 352x352(CIF) 3.3V/2.8V CMOS Image Sensor
REVISION HISTORY
Revision No. History Draft Date Remark 0.0 Initial Draft Feb. 16, 2002 Preliminary 0.1 Pin description error corrected (LHOLD polarity). Feb. 21, 2002 Preliminary Timing chart added. 0.2 STRB signal polarity error corrected Apr. 10, 2002 Preliminary SFCM timing diagram corrected Operation description added.
1/7 INCH CIF CMOS IMAGE SENSOR S5K711CA, S5K711LA INTRODUCTION The S5K711CA and S5K711LA are highly integrated single chip CMOS image sensors fabricated by SAMSUNG 0.35µm CMOS image sensor process technology. It is developed for imaging application to realize high-efficiency and low-power photo sensor. The sensor has 352 x 352 effective pixels with 1/7 inch optical format. The sensor has on-chip 8-bit ADC blocks to digitize the pixel output and also on-chip CDS to reduce Fixed Pattern Noise (FPN) drastically. With its few interface signals and 8-bit raw data directly connected to the external devices, a camera system can be configured easily. S5K711CA is suitable for a camera system with standard 3.3V logic operation and S5K711LA is suitable for low power camera module with 2.8V power supply.
FEATURES
— Process Technology: 0.35µm DPTM CMOS — Optical Size: 1/7 inch — Unit Pixel: 5.6 µm X 5.6 µm — Effective Resolution: 352X352, CIF — Line Progressive Read Out. — 8-bit Raw Image Data Output — Programmable Exposure Time — Programmable Gain Control — Auto Dark Level Compensation — Windowing and Panning — Sub-Sampling (2X, 3X, 4X) — Cotinuous and Single Frame Capture Mode — Standby-Mode for Power Saving — Maximum 70 Frame per Second — Bad Pixel Replacement — Single Power Supply Voltage: 3.3V or 2.8V — Package Type: 32-CLCC/PLCC PRODUCTS Product Code Power Supply Backend Process
Description
3.3 V S5K711LA01 2.8 V None Monochrome image sensor S5K711CA02 3.3 V S5K711LA02 2.8 V On-chip micro lens High sensitivity monochrome Image sensor S5K711CA03 3.3 V S5K711LA03 2.8 V On-chip color filter and micro lens RGB color image sensor
S5K711CA, S5K711LA 1/7” CIF CMOS IMAGE SENSOR BLOCK DIAGRAM Timing Generator RSTN STBYN MCLK VSYNC HSYNC DCLK SCL SDA STRB Main Clock Divider I2C Interface Control Registers Active Pixel Sensor Array Row Driver Even Column CDS Odd Column CDS 8-bit Column ADC 8-bit Column ADC VDDD VSSD VDDA VSSA Post Processing DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 LHOLD
1/7 INCH CIF CMOS IMAGE SENSOR S5K711CA, S5K711LA BLOCK DIAGRAM (TOP VIEW ON CHIP. DISPLAYED IMAGE WILL BE FLIPPED.) (14,14) read out start point Active Pixels Optical Black Pixels (0,0) Effective Active Pixel 352X352 R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G
S5K711CA, S5K711LA 1/7” CIF CMOS IMAGE SENSOR PIN CONFIGURATION DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 STBYN VSSA VDDA STRB LHOLD VDDA VSSA TEST2 (NC) VDDA VSSA VSSD MCLK SCL SDA RSTN (NC) VDDA VSSA VDDD DCLK HSYNC VSYNC TEST1 First Readout Pixel
1/7 INCH CIF CMOS IMAGE SENSOR S5K711CA, S5K711LA MAXIMUM ABSOLUTE LIMIT Characteristic Symbol Value Unit Operating voltage (VDDD, VDDA supply relative to VSSD, VSSA) VDD -0.3 to 3.8 V Input voltage VIN -0.3 to VDD+0.3 (Max. 3.8) Operating temperature TOPR -20 to +60 Storage temperature TSTG -40 to +125(1) -40 to +85(2) NOTES: The maximum allowed storage temperature for S5K711C(L)X01. The maximum allowed storage temperature for S5K711C(L)X02 and S5K711C(L)X03.
S5K711CA, S5K711LA 1/7” CIF CMOS IMAGE SENSOR
ELECTRICAL CHARACTERISTICS
(TA = -20 to +60°C, CL = 15pF) Characteristics Symbol Condition Min Typ Max Unit Operating voltage VDD VDDD, VDDA 3.0 3.3 3.6 V 2.55 2.8 3.05 Input voltage (1) VIH 0.8VDD VIL 0.2VDD Input leakage current(2) IIL VIN = VDD to VSS -10 µA Input leakage current with pull-down(3) IILD VIN = VDD High Level Output VOH IOH = -1µA VDD-0.05 V voltage (4) IOH = -4mA 2.4 Low Level Output VOL IOL = 1µA 0.05 voltage (5) IOL = 4mA 0.4 High-Z output leakage current (6) IOZ VOUT = VDD µA Supply current ISTB STBYN=Low(Active) All input clocks = Low µA IDD fMCLK = 12 MHz VDD = 3.3V (7) mA 0 lux illumination VDD = 2.8V (8) NOTES: Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA, TEST1, TEST2 pin. MCLK, RSTN, STBYN, STRB, SCL, SDA pin TEST1, TEST2 pin DCLK, HSYNC, VSYNC, DATA0 to DATA7 pin DCLK, HSYNC, VSYNC, DATA0 to DATA7, SCL, SDA pin SDA pin when in High-Z output state S5K711CA S5K711LA
1/7 INCH CIF CMOS IMAGE SENSOR S5K711CA, S5K711LA Imaging Characteristics (Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) is used. Electrical operating conditions follow the recommended typical values. The control registers are set to the default values. TA = 25°C if not specified.) NOTES: 1. Measured minimum output level at 100 lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole pixel area to elemiate the values from defective pixels. 2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values are used for color version. 3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec. 4. 20 log (saturation level/ dark level rms noise excluding fixed pattern noise). 48dB is limited by 8-bit ADC. 5. 20 log (average output level/rms noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure time 1/30 sec. 6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to elemiate the values from defective pixels. 7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to elemiate the values from defective pixels. 8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. 9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. Characteristic Symbol Condition Min Typ Max Unit Saturation level(1) VSAT S5K711CA 950 1000 mV S5K711LA 850 900 Sensitivity(2) S S5K711(C,L)X01 1500 mV/lux sec S5K711(C,L)X02 4000 S5K711(C,L)X03 1500 Dark level(3) VDARK TA = 40°C mV/sec TA = 60°C 100 Dynamic range(4) DR dB Signal to noise ratio(5) S/N Dark signal non-uniformity(6) DSNU TA = 60°C 100 mV/sec Photo response non- uniformity(7) PRNU Vertical fixed pattern noise(8) VFPN Horizontal fixed pattern noise(9) HFPN
S5K711CA, S5K711LA 1/7” CIF CMOS IMAGE SENSOR AC Characteristics (VDD = 3.0V to 3.6V for S5K711CA, VDD = 2.55V to 3.05V for S5K711LA, Ta = -20 to + 60 °C, CL = 50pF) NOTES: 1. The period time of main input clock, MCLK. I2C Serial Interface Characteristics Characteristic Symbol Condition Min Typ Max Unit Main input clock frequency fMCLK Duty = 50% MHz Data output clock frequency fDCLK Propagation delay time tPDMV VSYNC output ns from main input clock tPDMH HSYNC output tPDMD DCLK output tPDMO DATA output Propagation delay time tPDDV VSYNC output from data output clock tPDDH HSYNC output tPDDO DATA output Reset input pulse width tWRST RSTN=low(active) TMCLK(1) Standby input pulse width tWSTB STBYN=low(active) Characteristic Symbol Condition Min Typ Max Unit Clock frequency fSCK 400 kHz Clock high pulse width tWH SCK 800 ns Clock low pulse width tWL SCK 1000 Clock rise/fall time tR/tF SCK, SDA 300 Data set-up time tDS SDA to SCK 300 Data hold time tDH SDA to SCK 1200 START condition hold time tSTH TMCLK STOP condition setup time tSTS STOP to new START gap tGSS Capacitance for each pin CPIN SCL, SDA pF Capacitive bus load CBUS SCL, SDA 200 Pull-up resistor RPU SCL, SDA to VDD 1.5 kΩ
Table 1. Pin Description Master clock pulse input for all timing generators. Activating power saving mode. reduced, the unused lower bits are set to 0. Image data output synchronizing pulse output. Horizontal synchronizing pulse or data valid signal output. Vertical synchronizing pulse or line valid signal output.
S5K711CA, S5K711LA 1/7” CIF CMOS IMAGE SENSOR Control Registers Address (Hex) Reset Value Bits Mnemonic [5] sckinv (Factory use only) Column color inversion [4] idinv (Factory use only) Line color inversion [3] bprm Bad pixel replacement mode 0b: disabled (default), 1b: enabled [2] dlcm Dark level compensation mode 0b: manual (default), 1b: auto [1] ccsm Color channel separation mode 0b: not separated (default), 1b: separated 00h 00h [0] shutc Electronic shutter mode 0b: disabled (default), 1b: enabled [7] mircv Vertical mirror control 0b: normal (default), 1b: mirrored [6] mirch Horizontal mirror control 0b: normal (default), 1b: mirrored [5:4] mcdiv Main clock divider 00b: DCLK=MCLK, 01b: DCLK=MCLK÷2 (default) 10b: DCLK=MCLK÷4, 11b: DCLK=MCLK÷8 [3:2] subsr Row subsampling mode 00b: disabled (default), 01b: 2X, 10b: 3X, 11b: 4X 01h 10h [1:0] subsc Column subsampling mode 00b: disabled (default), 01b: 2X, 10b: 3X, 11b: 4X 02h 00h [0] wrp_high 03h 0Eh [7:0] wrp_low Row start point for window of interest wrp[8:0] = 14d(default) 04h 00h [0] wcp_high 05h 0Eh [7:0] wcp_low Column start point for window of interest wcp[8:0] = 14d(default) 06h 01h [0] wrd_high 07h 20h [7:0] wrd_low Row depth for window of interest wrd[8:0] = 288d(default) 08h 01h [1:0] wcw_high 09h 60h [7:0] wcw_low Column width for window of interest wcw[9:0] = 352d(default) 0Ah 80h [7:0] offsdef (Factory use only) Analog offset reference offsdef[7:0] = 128d (default)
1/7 INCH CIF CMOS IMAGE SENSOR S5K711CA, S5K711LA Address (Hex) Reset Value Bits Mnemonic [3] sfcen Single frame capture enable 0b: disabled (default), 1b: enabled 0Bh 01h [2:0] sint_high 0Ch 8Fh [7:0] sint_low Integration time in single frame capture mode sint[10:0] = 399d (default) 0Dh 00h [3:0] cintr_high 0Eh C7h [7:0] cintr_low Row-step integration time in continuous frame capture mode cintr[11:0] = 199d (default) 0Fh 00h [4:0] cintc_high 10h 00h [7:0] cintc_low Column-step integration time in continuous frame capture mode cintc[12:0] = 0d (default) 11h 01h [7:0] vswd VSYNC width vswd[7:0] = 1d (default) [5] vspolar VSYNC polarity 0: active high (default), 1: active low [4] vsdisp VSYNC display mode 0: sync mode (default), 1: data valid mode 12h 00h [1:0] vsstrt_high 13h 00h [7:0] vsstrt_low VSYNC start position vsstrt[9:0] = 0d (default) 14h 00h [3:0] vblank_high 15h 6Fh [7:0] vblank_low Vertical blank depth vblank[11:0] = 111d (default) 16h 20h [7:0] hswd HSYNC width hswd[7:0] = 32d (default) [5] hspolar HSYNC polarity 0: active high (default), 1: active low [4] hsdisp HSYNC display mode 0: sync mode (default), 1: data valid mode 17h 00h [1:0] hsstart_high 18h 00h [7:0] hsstart_low HSYNC start position hsstrt[9:0] = 0d (default) 19h 00h [5:0] hblank_high 1Ah 94h [7:0] hblank_low Horizontal blank depth hblank[13:0] = 148d (default)
S5K711CA, S5K711LA 1/7” CIF CMOS IMAGE SENSOR Address (Hex) Reset Value Bits Mnemonic [3:0] sgg1 1st sectional global gain sgg1[3:0] = 7d (default) 1Bh 77h [7:4] sgg2 2nd sectional global gain sgg2[3:0] = 7d (default) [3:0] sgg3 3rd sectional global gain sgg3[3:0] = 7d (default) 1Ch 77h [7:4] sgg4 4th sectional global gain sgg4[3:0] = 7d (default) 1Dh 00h [6:0] pgcr Red channel gain pgcr[6:0] = 0d (default) 1Eh 00h [6:0] pgcg1 Green(Red row) channel gain or all channel gain (ccsm=0) pgcg1[6:0] = 0d (default) 1Fh 00h [6:0] pgcg2 Green(Blue row) channel gain pgcg2[6:0] = 0d (default) 20h 00h [6:0] pgcb Blue channel gain pgcb[6:0] = 0d (default) 21h 80h [7:0] offsr Red channel analog offset offsr[7:0] = 128 (default) 22h 80h [7:0] offsg1 Green(Red row) channel analog offset or all channel offset (ccsm=0) offsg1[7:0] = 128 (default) 23h 80h [7:0] offsg2 Green(Blue row) channel analog offset offsg2[7:0] = 128 (default) 24h 80h [7:0] offsb Blue channel analog offset offsb[7:0] = 128 (default) 25h 14h [6:0] pthresh Bad pixel threshold pthresh[6:0] = 20d (default) 26h 00h [7:0] adcoffs ADC offset adcoffs[7:0] = 0d (default) [4] clipen (Factory use only) Reset clipping enable 27h 01h [3:0] p12stp (Factory use only) P12 start control
1/7 INCH CIF CMOS IMAGE SENSOR S5K711CA, S5K711LA Address (Hex) Reset Value Bits Mnemonic [7:5] stbystrt (Factory use only) Stand-by start 28h 40h [4:0] stbystp (Factory use only) Stand-by stop 29h 00h [7:0] rxstrt (Factory use only) Reset start control 2Ah 00h [7:0] blank Blank register for general purpose [3] vtest (Factory use only) Vertical function test mode [2] htest (Factory use only) Horizontal function test mode [1] i2ctest (Factory use only) IIC test mode 2Bh 02h [0] nandtree (Factory use only) NAND tree test mode
(mcdiv). If ratio of 1 is used, the duty must be within 40% to 60%. signal outputs indicate that the output data is valid (hsdisp=1) or the output rows are valid (vsdisp=1). Figure 4. WOI definition. Control Register (mirch) and Vertical Mirror Control Register (mircv). Control Registers, subsr and subsc. The sub-sampling is performed only in the Bayer space.
Figure 5. Bayer Space Sub-Sampling Examples where cintr = 1 to { wrd / (subsr+1) + vblank }, cintc = 0 to { wcw / (subsc+1) + hblank –180 }.
- Analog to Digital Converter ( ADC)
channel gain and offset control. The ADC resolution is fixed to 8bit. for the reset level and once for the actual signal level sampling. Figure 6. Relative Channel Gain
each register value decides the gain for each quarter section of output code level. Figure 7. Relative Global Gain the resulting gain over unity for assuring appropriate ADC conversion range.
S5K711CA, S5K711LA 1/7” CIF CMOS IMAGE SENSOR TIMING CHART VERTICAL TIMING DIAGRAM Continuous Frame Capture Mode ( Default Case ) ( Delayed Vertical Sync Case) ( Vertical Data Valid Mode Case) vsdisp=1 HSYNC wrd (288 rows) 1 frame = wrd + vblank (399 rows ) wrp (14th row) VSYNC vswd (1row) rows DATA vblank (111 rows) HSYNC 1 frame = wrd + vblank VSYNC vsstrt DATA HSYNC (hsdisp=0) wrd VSYNC DATA vblank 2 rows vswd 2 rows HSYNC (hsdisp=1)
1/7 INCH CIF CMOS IMAGE SENSOR S5K711CA, S5K711LA VERTICAL TIMING DIAGRAM (continued) Single Frame Capture Mode HSYNC VSYNC DATA STRB Integration time for 1st readout row Normal frame output Integration time for 2nd readout row Integration time for 3rd readout row Integration time for 4th readout row 2 rows sint X (1 row time) 3 rows 1 row 1 row 1 row
S5K711CA, S5K711LA 1/7” CIF CMOS IMAGE SENSOR HORIZONTAL TIMING DIAGRAM ( Default Case ) ( Delayed Horizontal Sync Case ) ( Horizontal Data Valid Mode Case ) hsdisp=1 wcw ( 352 columns ) 1 row = wcw + hblank ( 500 columns ) hswd ( 32 DCLK) hblank ( 148 columns ) HSYNC VSYNC DATA DCLK
10 DCLK
( 14th column) wcw 1 row = wcw + hblank hsstrt HSYNC VSYNC DATA DCLK hswd
42 DCLK
1/7 INCH CIF CMOS IMAGE SENSOR S5K711CA, S5K711LA LINE HOLD MODE TIMING DIAGRAM HSYNC DATA (i)-th row (i+1)-th row (i+2)-th row LHOLD hblank – 42 DCLK hblank
S5K711CA, S5K711LA 1/7” CIF CMOS IMAGE SENSOR PACKAGE DIMENSION BOTTOM VIEW SIDE VIEW TOP VIEW Center of Image Area from package center) Max. Chip Rotation = ±1.5 degree Max. Chip Tilt = 0.05mm 0.51 ± 0.08 R 0.15
4 Corners
0.889 ± 0.18 7.112 ± 0.13 1.016 ± 0.08 1.65 ± 0.18 0.55 ± 0.05 Glass 32pin CLCC