S5K437CA SAMSUNG | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 36
Technical content
(1/4" VGA CMOS Image Sensor) DATA SHEET Revision 1.1
1/4" Optical Size 640 × 480 (VGA) 2.8V CMOS Image Sensor
REVISION HISTORY
Revision No. History Draft Date Remark 0.0 Initial Draft Mar, 01. 2004 1.0 Changed the operation frequency (30MHz → 24.54MHz). Added the shutter operation range limit. Added recommended value for selection of OB_AREA. Added CHIP pad description. May, 18. 2004
1.1 Added AC characteristic timing diagram
(include Standby timing diagram) July, 15. 2004
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX INTRODUCTION S5K437CX is a highly integrated single chip CMOS image sensor developed by SAMSUNG with the 0.35µm CMOS image sensor process technology. It is designed to implement high-efficient and low-power photo sensor in the imaging application. The sensor has 640 x 480 effective pixels with 1/4 inch optical format. The sensor digitizes the pixel output with the on-chip 10-bit ADC blocks and drastically Fixed Pattern Noise (FPN) with the on- chip CDS. With the interface signals and 10-bit raw data directly connected to the external devices, you can easily set up the camera system. S5K437CX is suitable for low power camera module with 2.8V power supply.
FEATURES
- Process Technology: 0.35 µm DPTM CMOS
- Optical Size: 1/4 inch
- Unit Pixel: 5.6 µm X 5.6 µm
- Effective Resolution: 640X480, VGA
- Line Progressive Read Out.
- 10-bit Raw Image Data Output
- Programmable Exposure Time
- Programmable Gain Control
- Auto Dark Level Compensation
- Windowing and Panning
- Sub-Sampling (2X, 3X, 4X)
- Standby-Mode for Power Saving
- Maximum 30 Frame per Second
- Bad Pixel Replacement
- Single Power Supply Voltage: 2.8V
- Package Type: 48-CLCC (TEST Only) PRODUCTS Product Code Power Supply Backend Process Description S5K437CX01 2.8 V None Monochrome image sensor S5K437CX02 2.8 V On-chip micro lens High sensitivity monochrome image sensor S5K437CX03 2.8 V On-chip color filter and micro lens RGB color image sensor
Figure 1. Block Diagram
Figure 2. Pixel Array Configuration
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX CHIP PAD CONFIGURATION (0,0) CHIP ID Effective Pixel Area (640X480) 14 23 51 3 8 3 4
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX CHIP PAD DESCRIPTION Pin No I/O Name Function VDDD (18) Power Digital power For logical circuit ( VDD ± 10% ) VSSD (1) Power supply 0V (GND) VDDIO (19,28) Power I/O power supply For I/O circuit ( VDD ± 10% ) VSSIO (29,38) Power 0V (GND) VDDA (4,15,27,30) Power Analog power supply For analog circuit ( VDD ± 10% ) VSSA ,32) Power 0V (GND) MCLK (37) I Master clock Master clo ck pulse input for all timing generators. RSTN (34) I Reset Initializing all the device registers. (Active low) STBYN (33) I Standby Activating power saving mode. (high = normal operation, low = power saving mode) DATA0~DATA9 (5~14) O Image data output 10-bit image data out puts. When ADC resolution is reduced, the unused lower bits are set to 0. DCLK (20) O Data clock Image data output synchronizing pulse output. HSYNC (21) O Horizontal sync clock Horizontal sy nchronizing pulse or data valid signal output. VSYNC (22) O Vertical sync clock Vertical synchronizing pulse or line valid signal output. SCL (36) I Serial interface clock I2C serial interface clock input SDA (35) I/O Serial interface data I2C serial interface data bus (external pull-up resistor required) TEST1 (23) I Test input 1 Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. TEST2 (24) I Test input 2 Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins.
Figure 3. Pin Configuration
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX PACKAGE PIN DESCRIPTION (48CLCC, TEST ONLY) Pin No I/O Name Function VDDD (24) Power Digital power supply For logical circuit ( VDD ± 10% ) VSSD (1) Power 0V (GND) VDDIO (26,35) Power I/O power supply For I/O circuit ( VDD ± 10% ) VSSIO (38,47) Power 0V (GND) VDDA (4,21,34,39) Power Analog power supply For analog circuit ( VDD ± 10% ) VSSA ,41) Power 0V (GND) MCLK (46) I Master clock Master clo ck pulse input for all timing generators. RSTN (43) I Reset Initializing all the device registers. (Active low) STBYN (42) I Standby Activating power saving mode. ( high=normal operation, low=power saving mode ) DATA0~DATA9 (6,9 ~ 16,19) O Image data output 10-bit image data out puts. When ADC resolution is reduced, the unused lower bits are set to 0. DCLK (27) O Data clock Image data output synchronizing pulse output. HSYNC (28) O Horizontal sync clock Horizontal sy nchronizing pulse or data valid signal output. VSYNC (29) O Vertical sync clock Vertical synchronizing pulse or line valid signal output. SCL (45) I Serial interface clock I2C serial interface clock input SDA (44) I/O Serial interface data I2C serial interface data bus (external pull-up resistor required) TEST1 (30) I Test input 1 Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. TEST2 (31) I Test input 2 Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins.
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX MAXIMUM ABSOLUTE LIMIT Characteristic Symbol Value Unit Operating voltage (VDDD, VDDIO, VDDA supply related to VSSD, VSSIO, VSSA, VBBA) VDD -0.3 to 3.8 V Input voltage VIN -0.3 to V DD+0.3 (Max. 3.8) Operating temperature TOPR -20 to +60 °C Storage temperature TSTG -40 to +125(1) -40 to +85(2) NOTES: 1. Storage temperature tole rance for S5K437C(L)X01. 2. Storage temperature tolerance fo r S5K437C(L)X02 and S5K437C(L)X03.
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX
ELECTRICAL CHARACTERISTICS
(TA = -20 to +60°C, CL = 15pF) Characteristics Symbol Condition Min Typ Max Unit Operating voltage VDD VDDD, VDDIO, VDDA 2.55 2.8 3.05 V Input voltage (1) VIH - 0.8VDD - - VIL - 0 - 0.2VDD Input leakage current(2) IIL V IN = VDD to VSS -10 - 10 µA Input leakage current with pull-down(3) IILD V IN = VDD 10 30 60 High Level Output voltage (4) VOH IOH = -1µA VDD- 0.05 - - V IOH = -4mA 2.4 - - Low Level Output VOL IOL = 1µA - - 0.05 voltage (5) IOL = 4mA - - 0.4 High-Z output leakage current (6) IOZ V OUT = VDD - - 10 µA Supply current ISTB STBYN = Low(Active) All input clocks = Low - - 10 µA IDD f mclk = 24.54MHz VDD = 2.8V - 18 - mA 0 lux illumination NOTES: 1. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA, TEST1, TEST2 pin. 2. MCLK, RSTN, STBYN, STRB, SCL, SDA pin 3. TEST1, TEST2 pin 4. DCLK, HSYNC, VSYNC, DATA0 to DATA9 pin 5. DCLK, HSYNC, VSYNC, DATA0 to DATA9, SCL, SDA pin 6. SDA pin when in High-Z output state
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX Imaging Characteristics (Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) are used. It is recommended that the sensor should operate in compliance to the following typical values. The control registers are set to the default values. TA = 25°C unless otherwise specified.) Characteristics Symbol Condition Min Typ Max Unit Saturation level(1) VSAT S5K437CX 850 900 - mV Sensitivity(2) S S5K437CX01 - 1500 - mV/ S5K437CX02 - 4000 - lux sec S5K437CX03 - 1500 - Dark level(3) VDARK TA = 40°C - 9 18 mV/sec TA = 60°C - 50 100 Dynamic range(4) DR - 60 - dB Signal to noise ratio(5) S/N - 40 - Dark signal non- uniformity(6) DSNU TA = 60°C - - 100 mV/sec Photo response non- uniformity(7) PRNU - 4 8 % Vertical fixed pattern noise(8) VFPN 4 8 % Horizontal fixed pattern noise(9) HFPN 4 8 % NOTES: 1. Minimum output level measured at 100 lu x illumination for exposure time 1/30 sec. 7X7 rank filter is applied to the whole pixel area to eliminate the values from defective pixels. 2. Average output measured at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values are used for color version. 3. Average output measur ed at zero illumination without any offset compensation for exposure time 1/30 sec. 4. 20 log (saturation level/ dark leve l rms noise excluding fixed pattern noise). 60dB is limited by 10-bit ADC. 5. 20 log (average output level/rms noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure time 1/30 sec. 6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median filter is applied to the whole pixel area to eliminate the values from defective pixels. 7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level illumination for exposure time 1/30 se c. 7X7 median filter is applied to the whole pixel area to eliminate the values from defective pixels. 8. For the column-averaged pixel output values, maximum relati ve deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. 9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation le vel illumination for exposure time 1/30 sec.
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX AC Characteristics (VDD = 2.55V to 3.05V for S5K437CX, Ta = -20 to + 60 °C, CL = 50pF) Characteristic Symbol Condition Min Typ Max Unit Main input clock frequency fMCLK Duty = 50% 4 (1) 12 24.54 (3) MHz Data output clock frequency fDCLK - 2 6 12.27 Propagation delay time tPDMV VSYNC output - - 20 ns from main input clock tPDMH HSYNC output - - 20 tPDMD DCLK output - - 15 tPDMO DATA output - - 20 Propagation delay time tPDDV VSYNC output - - 10 from data output clock tPDDH HSYNC output - - 5 tPDDO DATA output - - 5 Reset input pulse width tWRST RSTN = low (active) 5 - - TMCLK (2) Standby input pulse width tWSTB STBYN = low (active) 4 - - NOTES: 1. 8-bit ADC resolution case. If 10-bit ADC resolu tion is used, the frequency should be over 12MHz. 2. The period time of main input clock, MCLK. tPDMD DATA MCLK DCLK 0.5VDD HSYNC VSYNC tPDDO tPDMO tPDMD tPDDH tPDMH tPDDH tPDMH tPDDV tPDMV
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX I 2C Serial Interface Characteristics Characteristic Symbol Condition Min Typ Max Unit Clock frequency fSCK - - - 400 kHz Clock high pulse width tWH SCK 800 - - ns Clock low pulse width tWL SCK 1000 - - Clock rise/fall time tR/tF SCK, SDA - - 300 Data set-up time tDS SDA to SCK 300 - - Data hold time tDH SDA to SCK 1200 - - START condition hold time tSTH - 4 TMCLK STOP condition setup time tSTS - 4 - - STOP to new START gap tGSS - 8 - - Capacitance for each pin CPIN SCL, SDA - - 4 pF Capacitive bus load CBUS SCL, SDA - - 200 Pull-up resistor RPU SCL, SDA to V DD 1.5 - 10 kΩ RSTN STBYN tWSTB tWRST MCLK system reset partial power down complete power down
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX CONTROL REGISTERS Addres s (Hex) Reset Value Bits Mnemonic Description 00h 02h [5] bprm Bad pixel replacement mode 0b: disabled (default), 1b: enabled [4] Not use [3] ccsm Color channel separation mode 0b: not separated (default), 1b: separated [2] shutc Electronic shutter mode 0b: disabled (default), 1b: enabled [1:0] adcres ADC resolution 00b: 8-bit, 01b: 9-bit, 10b: 10-bit (default) 01h 10h [7] mircv Vertical mirror control 0b: normal (default), 1b: mirrored [6] mirch Horizontal mirror control 0b: normal (default), 1b: mirrored [5:4] mcdiv Main clock divider 00b: DCLK=MCLK, 01b: DCLK=MCLK÷ 2 (default) 10b: DCLK=MCLK÷ 4, 11b: DCLK=MCLK÷ 8 [3:2] subsr Row subsampling mode 00b: disabled (default), 01b: 2X, 10b: 3X, 11b: 4X [1:0] subsc Column subsampling mode 00b: disabled (default), 01b: 2X, 10b: 3X, 11b: 4X 02h 00h [0] wrp_high Row start point for window of interest 03h 0Eh [7:0] wrp_low wrp[8:0] = 14d(default) 04h 00h [0] wcp_high Column start point for window of interest 05h 0Eh [7:0] wcp_low wcp[8:0] = 14d(default) 06h 01h [0] wrd_high Row depth for window of interest 07h E0h [7:0] wrd_low wrd[8:0] = 480d(default) 08h 02h [1:0] wcw_high Column width for window of interest 09h 80h [7:0] wcw_low wcw[9:0] = 640d(default) 0Ah 80h [7:0] (Factory use only)
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX Addres s (Hex) Reset Value Bits Mnemonic Description 0Dh 01h [4:0] cintr_high Row-step integration time in continuous frame capture mode (range is described in operation description) 0Eh 06h [7:0] cintr_low cintr[12:0] = 262d (default) 0Fh 00h [5:0] cintc_high Column-step integration time in continuous frame capture mode (range is described in operation description) 10h 00h [7:0] cintc_low cintc[13:0] = 0d (default) 11h 01h [7:0] vswd VSYNC width vswd[7:0] = 1d (default) 12h 00h [5] vspolar VSYNC polarity 0: active high (default), 1: active low [4] vsdisp VSYNC display mode 0: sync mode (default), 1: data valid mode [1:0] vsstrt_high VSYNC start position vsstrt[9:0] = 0d (default) 13h 00h [7:0] vsstrt_low 14h 00h [4:0] vblank_high Vertical blank depth vblank[12:0] = 45d (default) 15h 2Dh [7:0] vblank_low 16h 20h [7:0] hswd HSYNC width hswd[7:0] = 32d (default) 17h 00h [5] hspolar HSYNC polarity 0: active high (default), 1: active low [4] hsdisp HSYNC display mode 0: sync mode (default), 1: data valid mode [1:0] hsstart_high HSYNC start position 18h 00h [7:0] hsstart_low hsstrt[9:0] = 0d (default) 19h 00h [5:0] hblank_high Horizontal blank depth 1Ah 8Ch [7:0] hblank_low hblank[13:0] = 140d (default)
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX Addres s (Hex) Reset Value Bits Mnemonic Description 1Bh 77h [3:0] sgg1 1st quadrisectional global gain 7d (default) [7:4] sgg2 2nd quadrisectional global gain 7d (default) 1Ch 77h [3:0] sgg3 3rd quadrisectional global gain 15d (default) [7:4] sgg4 4th quadrisectional global gain 15d (default) 1Dh 00h [6:0] pgcr Red channel gain pgcr[6:0] = 0d (default) 1Eh 00h [6:0] pgcg1 Green(Red row) channel gain or all channel gain (ccsm = 0) pgcg1[6:0] = 0d (default) 1Fh 00h [6:0] pgcg2 Green(Blue row) channel gain pgcg2[6:0] = 0d (default) 20h 00h [6:0] pgcb Blue channel gain pgcb[6:0] = 0d (default) 21h 80h [7:0] offsr Red channel analog offset Offsr[7:0] = 128 (default) 22h 80h [7:0] offsg1 Green(Red row) channel analog offset or all channel offset (ccsm=0) offsg1[7:0] = 128 (default) 23h 80h [7:0] offsg2 Green(Blue row) channel analog offset offsg2[7:0] = 128 (default) 24h 80h [7:0] offsb Blue channel analog offset offsb[7:0] = 128 (default) 25h 14h [6:0] pthresh Bad pixel threshold pthresh[6:0] = 20d (default) 26h 00h [7:0] adcoffs ADC offset adcoffs[7:0] = 0d (default)
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX Addres s (Hex) Reset Value Bits Mnemonic Description 27h 0Ch [5] (Factory use only) [4] NOT USE [3:0] (Factory use only) 28h 40h [7:5] (Factory use only) [4:0] (Factory use only) 29h 00h [7:0] (Factory use only) 2Ah 00h [7:0] blank Blank register for general purpose 2Bh 02h [7:6] (Factory use only) [5] (Factory use only) [4] (Factory use only) [3] (Factory use only) [2] (Factory use only) [1] (Factory use only) [0] (Factory use only) 2Ch 00h [7] adlc_mod_d Adlc mode always enable when 0b: disabled (default), 1b: enabled [6] adlc_mod_c Adlc mode works when gain value is changed 0b: disabled (default), 1b: enabled [5] adlc_mod_b Adlc mode works when shutter value is changed 0b: disabled (default), 1b: enabled [4] adlc_mod_a Adlc mode works till adlc length value 0b: disabled (default), 1b: enabled [3:2] feedback_gain_B Feedback gain value about ADLC ADLC formula : Dnew = A*(OBold + OBnew) + B*Dold 00b : 0 (default), 01b : 0.5, 10b : 0.75, 11b : 1 [1:0] feedback_gain_A Feedback gain value about ADLC 00b : 0 (default), 01b : 0.5, 10b : 0.25, 11b : 0.125
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX Addres s (Hex) Reset Value Bits Mnemonic Description 2Dh 10h [7] mckout_en DCK pad control 0b : stable value (default), 1b : output enable [6] b2 I/O driver fan-out control register. [4] b0 {111} (3/3) [3] OB_sel ADLC formura : Dnew = A*(OBold + OBnew) + B*Dold 0b : OBold = OBold (default) 1b : OBold = OBnew [2] OB_area OB area selection 0b : 128 * 8 (default), 1b : 512*2 (recommend) [1:0] adlc_length ADLC function works only during this value when adlc_mod_a enabled, 00b : 1 frame, 01b : 2 frames, 10b : 3 frames, 11b : 4 frames 2Eh CCh [7:4] (Factory use only) [3:0] (Factory use only) 2F 0Ch [4] tg_sel Pixel TG signal selection 0b: disabled (default), 1b: enabled [3:0] (Factory use only
sync signal outputs indicate that the output data is valid (hsdisp = 1) or the output rows are valid (vsdisp = 1). on the red and green column of Bayer pattern. Figure 4 illustrates the WOI on the displayed pixel image. Figure 4. WOI definition Mirror Control Register (mirch) and Vertical Mirror Control Register (mircv). Registers, subsr and subsc. The sub-sampling is performed only in the Bayer space.
Figure 5. Bayer Space Sub-Sampling Examples incident light on image sensor, and then, the data readout sequence starts.
- Analog to Digital Converter ( ADC)
channel gain and offset control. is sampled twice - one for the reset level and one for the actual signal level sampling. Figure 6. Relative Channel Gain
Figure 9. Quadrisectional Global Gain Control the enabled frame, and analog-to-digital conversion range is shifted to compensate the dark level for that frame. subtract the output image data. Please note that all the 8-bit data are used for an offset value without a sign bit.
reduces the line resolution in the horizontal direction. high-to-low transition of SCL. Figure 10. I2C Bus Write Cycle
Figure 11. I2C Bus Read Cycle
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX TIMING CHART VERTICAL TIMING DIAGRAM Continuous Frame Capture Mode (Default Case) HSYNC wrd (480 rows) 1 frame = wrd + vblank (525 rows ) wrp (14th row) VSYNC vswd (1row) DATA vblank (45rows) (Delayed Vertical Sync Case) HSYNC 1 frame = wrd + vblank (525 rows) VSYNC vsstrt DATA 2 rows vswd 2 rows
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX (Vertical Data Valid Mode Case) vsdisp = 1 HSYNC (hsdisp=0) wrd VSYNC DATA vblank HSYNC (hsdisp=1)
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX Horizontal Timing Diagram (Default Case) wcw ( 640 columns ) 1 row = wcw + hblank ( 780columns) hswd (32 DCLK) hblank (140columns) HSYNC VSYNC DATA DCLK DCLK wcp (14th column) (Delayed Horizontal Sync Case) wcw 1 row = wcw + hblank hsstrt HSYNC VSYNC DATA DCLK hswd
42 DCLK 42 DCLK
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX (Horizontal Data Valid Mode Case ) hsdisp = 1 wcw HSYNC VSYNC DATA DCLK
42 DCLK hblank
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX 48CLCC PACKAGE DIMENSION (TEST ONLY) 0.51 + 0.08 R 0.15
4 Corners
1.016 + 0.18 11.176 + 0.13 1.016 + 0.08 Center of Image Area from package center) Max. Chip Rotation = + 1.5 degree Max. Chip Tilt = 0.05mm Center of Image Area from package center) Max. Chip Rotation = + 1.5 degree Max. Chip Tilt = 0.05mm TOP VIEW SIDE VIEW BOTTOM VIEW 19 30 64 3 481 X 0.55 + 0.05 Glass 1.65 + 0.18
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX
1/4 INCH VGA CMOS IMAGE SENSOR S5K437CX NOTES 2004 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung-Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900 Homepage: www.samsungsemi.com