S5K433CA SAMSUNG | Alldatasheet
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1/4 INCH VGA CMOS IMAGE SENSOR S5K433CA, S5K433LA S5K433CA, S5K433LA (1/4” VGA CMOS Image Sensor) Preliminary Specification Revision 0.3.1 July 2002
S5K433CA, S5K433LA 1/4” VGA CMOS IMAGE SENSOR DOCUMENT TITLE 1/4” Optical Size 640x480(VGA) 3.3V/2.8V CMOS Image Sensor
REVISION HISTORY
Revision No. History Draft Date Remark 0.0 Initial Draft Feb. 16, 2002 Preliminary 0.1 Pin description error corrected (LHOLD polarity). Feb. 21, 2002 Preliminary Timing chart added. 0.2 STRB signal polarity error corrected Apr. 10, 2002 Preliminary SFCM timing diagram corrected Operation description added.
0.3 DC timing characteristics specification changed July 8, 2002 Preliminary
AC timing characteristics specification changed STRB and LHOLD pins are deleted
0.3.1 Minor description error corrected July 15, 2002 Preliminary
1/4 INCH VGA CMOS IMAGE SENSOR S5K433CA, S5K433LA INTRODUCTION The S5K433CA and S5K433LA are highly integrated single chip CMOS image sensors fabricated by SAMSUNG 0.35µm CMOS image sensor p rocess technology. It is developed for imag ing application to realize high-efficiency and low -power photo sensor. The sensor has 640 x 480 effective pixels with 1/4 inch optical format. The sensor has on -chip 10-bit ADC blocks to digitize the pixel output and also on -chip CDS to reduce Fixed Pattern Noise (FPN) drastically. With its few interface signals and 10 -bit raw data directly connected to the external devices, a camera system can be configured easily. S5K433CA is suitable for a camera system with standard 3.3V logic operation and S5K433LA is suitable for low power camera module with 2.8V power supply.
FEATURES
— Process Technology: 0.35µm DPTM CMOS — Optical Size: 1/4 inch — Unit Pixel: 5.6 µm X 5.6 µm — Effective Resolution: 640X480, VGA — Line Progressive Read Out. — 10-bit Raw Image Data Output — Programmable Exposure Time — Programmable Gain Control — Auto Dark Level Compensation — Windowing and Panning — Sub-Sampling (2X, 3X, 4X) — Standby-Mode for Power Saving — Maximum 36 Frame per Second — Bad Pixel Replacement — Single Power Supply Voltage: 3.3V or 2.8V — Package Type: 48-CLCC/PLCC PRODUCTS Product Code Power Supply Backend Process Description S5K433CA01 3.3 V S5K433LA01 2.8 V None Monochrome image sensor S5K433CA02 3.3 V S5K433LA02 2.8 V On-chip micro lens High sensitivity monochrome Image sensor S5K433CA03 3.3 V S5K433LA03 2.8 V On-chip color filter and micro lens RGB color image sensor
Figure 1. Block Diagram
Figure 2. Pixel Array Configuration
Figure 3. Pin Configuration
1/4 INCH VGA CMOS IMAGE SENSOR S5K433CA, S5K433LA MAXIMUM ABSOLUTE LIMIT Characteristic Symbol Value Unit Operating voltage (VDDD, VDDIO, VDDA supply relative to VSSD, VSSIO, VSSA, VBBA) VDD -0.3 to 3.8 V Input voltage VIN -0.3 to VDD+0.3 (Max. 3.8) Operating temperature TOPR -20 to +60 Storage temperature TSTG -40 to +125(1) °C -40 to +85(2) NOTES: 1. The maximum allowed storage temperature for S5K433C(L)X01. 2. The maximum allowed storage temperature for S5K433C(L)X02 and S5K433C(L)X03.
S5K433CA, S5K433LA 1/4” VGA CMOS IMAGE SENSOR
ELECTRICAL CHARACTERISTICS
(TA = -20 to +60°C, CL = 15pF) Characteristics Symbol Condition Min Typ Max Unit Operating voltage VDD VDDD, VDDIO, S5K433CA 3.0 3.3 3.6 V VDDA S5K433LA 2.55 2.8 3.05 Input voltage (1) VIH - 0.8VDD - - VIL - 0 - 0.2VDD Input leakage current(2) IIL VIN = VDD to VSS -10 - 10 µA Input leakage current with pull-down(3) IILD VIN = VDD 10 30 60 High Level Output VOH IOH = -1µA VDD-0.05 - - V voltage (4) IOH = -4mA S5K433CA 2.4 - - S5K433LA 1.9 - - Low Level Output VOL IOL = 1µA - - 0.05 voltage (5) IOL = 4mA - - 0.4 High-Z output leakage current (6) IOZ VOUT = VDD - - 10 µA Supply current ISTB STBYN=Low(Active) All input clocks = Low - - 10 µA IDD fMCLK = 24.54MHz VDD = 3.3V (7) - 27 - mA 0 lux illumination VDD = 2.8V (8) - 18 - NOTES: 1. Applied to MCLK, RSTN, STBYN, SCL, SDA, TEST1, TEST2 pin. 2. MCLK, RSTN, STBYN, SCL, SDA pin 3. TEST1, TEST2 pin 4. DCLK, HSYNC, VSYNC, DATA0 to DATA9 pin 5. DCLK, HSYNC, VSYNC, DATA0 to DATA9, SCL, SDA pin 6. SDA pin when in High-Z output state 7. S5K433CA 8. S5K433LA
1/4 INCH VGA CMOS IMAGE SENSOR S5K433CA, S5K433LA Imaging Characteristics (Light source with 3200K of color temperature and IR cut filter (CM -500S, 1mm thickness) is used. Electrical operating conditions follow the recommended typical values. The control registers are set to the default values . TA = 25°C if not specified.) NOTES: 1. Measured minimum output level at 100 lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole pixel area to eliminate the values from defective pixels. 2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values are used for color version. 3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec. 4. 20 log (saturation level/ dark level rms noise excluding fixed pattern noise). 60dB is limited by 10 -bit ADC. 5. 20 log (average output level/rms noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure time 1/30 sec. 6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from defective pixels. 7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from defective pixels. 8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. 9. For the row-averaged pixel output values, maximum relative deviation of values from 7 -depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. Characteristic Symbol Condition Min Typ Max Unit Saturation level(1) VSAT S5K433CA 950 1000 - mV S5K433LA 850 900 - Sensitivity(2) S S5K433(C,L)X01 - 1500 - mV/lux sec S5K433(C,L)X02 - 4000 - S5K433(C,L)X03 - 1500 - Dark level(3) VDARK TA = 40°C - 9 18 mV/sec TA = 60°C - 50 100 Dynamic range(4) DR - 60 - dB Signal to noise ratio(5) S/N - 40 - Dark signal non-uniformity(6) DSNU TA = 60°C - - 100 mV/sec Photo response non- uniformity(7) PRNU - 4 8 % Vertical fixed pattern noise(8) VFPN 4 8 % Horizontal fixed pattern noise(9) HFPN 4 8 %
S5K433CA, S5K433LA 1/4” VGA CMOS IMAGE SENSOR AC Characteristics (VDD = 3.0V to 3.6V for S5K433CA, VDD = 2.55V to 3.05V for S5K433LA, Ta = -20 to + 60 ° C, CL = 50pF) NOTES: 1. 8-bit ADC resolution case. If 10-bit ADC resolution is used, the frequency should be over 12MHz. 2. The period time of main input clock, MCLK. Characteristic Symbol Condition Min Typ Max Unit Main input clock frequency fMCLK Duty = 50% 3(1) 24.54 30 MHz Data output clock frequency fDCLK - 2 12.27 15 Propagation delay time tPDMD DCLK output - - 20 ns from main input clock tPDMO DATA output - - 25 tPDMH HSYNC output - - 25 tPDMV VSYNC output - - 25 Propagation delay time tPDDO DATA output - - 10 from data output clock tPDDH HSYNC output - - 10 tPDDV VSYNC output - - 10 Reset input pulse width tWRST RSTN=low(active) 5 - - TMCLK (2) Standby input pulse width tWSTB STBYN=low(active) 4 - - tPDMD DATA MCLK DCLK 0.5VDD HSYNC VSYNC tPDDO tPDMO tPDMD tPDDH tPDMH tPDDH tPDMH tPDDV tPDMV
1/4 INCH VGA CMOS IMAGE SENSOR S5K433CA, S5K433LA I2C Serial Interface Characteristics Characteristic Symbol Condition Min Typ Max Unit Clock frequency fSCK - - - 400 kHz Clock high pulse width tWH SCL 800 - - ns Clock low pulse width tWL SCL 1000 - - Clock rise/fall time tR/tF SCL, SDA - - 300 Data set-up time tDS SDA to SCL 300 - - Data hold time tDH SDA to SCL 1200 - - START condition hold time tSTH - 4 TMCLK STOP condition setup time tSTS - 4 - - STOP to new START gap tGSS - 8 - - Capacitance for each pin CPIN SCL, SDA - - 4 pF Capacitive bus load CBUS SCL, SDA - - 200 Pull-up resistor RPU SCL, SDA to VDD 1.5 - 10 kΩ SDA SCL 0.1VDD 0.9VDD tSTRS tSTRH tWL tDH tWH tDS tF tR 0.1VDD 0.9VDD tSTPS RSTN STBYN tWSTB tWRST MCLK system reset partial power down complete power down
S5K433CA, S5K433LA 1/4” VGA CMOS IMAGE SENSOR PIN DESCRIPTION Pin No I/O Name Function VDDD (24) Power Digital power supply For logical circuit ( VDD ± 10% ) VSSD (1) Power 0V (GND) VDDIO (26, 35) Power I/O power supply For I/O circuit ( VDD ± 10% ) VSSIO (47, 38) Power 0V (GND) VDDA (4, 21, 34, 39) Power Analog power supply For analog circuit ( VDD ± 10% ) VSSA (3, 22, 33, 40) Power 0V (GND) VBBA (2, 23, 32, 41) Power For analog circuit bulk bias ( 0V) MCLK (46) I Master clock Master clock pulse input for all timing generators. RSTN (43) I Reset Initializing all the device registers. (Active low) STBYN (42) I Standby Activating power saving mode. ( high=normal operation, low=power saving mode ) DATA0~DATA9 (6, 9~16, 19) O Image data output 10-bit image data outputs. When ADC resolution is reduced, the unused lower bits are set to 0. DCLK (27) O Data clock Image data output synchronizing pulse output. HSYNC (28) O Horizontal sync clock Horizontal synchronizing pulse or data valid signal output. VSYNC (29) O Vertical sync clock Vertical synchronizing pulse or line valid signal output. SCL (45) I Serial interface clock I2C serial interface clock input SDA (44) I/O Serial interface data I2C serial interface data bus (external pull-up resistor required) TEST1 (30) I Test input 1 Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. TEST2 (31) I Test input 2 Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins.
1/4 INCH VGA CMOS IMAGE SENSOR S5K433CA, S5K433LA CONTROL REGISTERS Address (Hex) Reset Value Bits Mnemonic Description [5] bprm Bad pixel replacement mode 0b: disabled (default), 1b: enabled [4] dlcm Dark level compensation mode 0b: manual (default), 1b: auto [3] ccsm Color channel separation mode 0b: not separated (default), 1b: separated [2] shutc Electronic shutter mode 0b: disabled (default), 1b: enabled 00h 02h [1:0] adcres ADC resolution 00b: 8-bit, 01b: 9-bit, 10b: 10-bit (default) [7] mircv Vertical mirror control 0b: normal (default), 1b: mirrored [6] mirch Horizontal mirror control 0b: normal (default), 1b: mirrored [5:4] mcdiv Main clock divider 00b: DCLK=MCLK, 01b: DCLK=MCLK÷ 2 (default) 10b: DCLK=MCLK÷ 4, 11b: DCLK=MCLK÷ 8 [3:2] subsr Row subsampling mode 00b: disabled (default), 01b: 2X, 10b: 3X, 11b: 4X 01h 10h [1:0] subsc Column subsampling mode 00b: disabled (default), 01b: 2X, 10b: 3X, 11b: 4X 02h 00h [0] wrp_high 03h 0Eh [7:0] wrp_low Row start point for window of interest wrp[8:0] = 14d(default) 04h 00h [0] wcp_high 05h 0Eh [7:0] wcp_low Column start point for window of interest wcp[8:0] = 14d(default) 06h 01h [0] wrd_high 07h E0h [7:0] wrd_low Row depth for window of interest wrd[8:0] = 480d(default) 08h 02h [1:0] wcw_high 09h 80h [7:0] wcw_low Column width for window of interest wcw[9:0] = 640d(default) 0Ah 80h [7:0] (Factory use only))
S5K433CA, S5K433LA 1/4” VGA CMOS IMAGE SENSOR Address (Hex) Reset Value Bits Mnemonic Description [4] [3] 0Bh 02h [2:0] 0Ch 0Dh [7:0] (factory use only) 0Dh 01h [4:0] cintr_high 0Eh 06h [7:0] cintr_low Row-step integration time in continuous frame capture mode cintr[12:0] = 262d (default) 0Fh 00h [5:0] cintc_high 10h 00h [7:0] cintc_low Column-step integration time in continuous frame capture mode cintc[13:0] = 0d (default) 11h 01h [7:0] vswd VSYNC width vswd[7:0] = 1d (default) [5] vspolar VSYNC polarity 0: active high (default), 1: active low [4] vsdisp VSYNC display mode 0: sync mode (default), 1: data valid mode 12h 00h [1:0] vsstrt_high 13h 00h [7:0] vsstrt_low VSYNC start position vsstrt[9:0] = 0d (default) 14h 00h [4:0] vblank_high 15h 2Dh [7:0] vblank_low Vertical blank depth vblank[12:0] = 45d (default) 16h 20h [7:0] hswd HSYNC width hswd[7:0] = 32d (default) [5] hspolar HSYNC polarity 0: active high (default), 1: active low [4] hsdisp HSYNC display mode 0: sync mode (default), 1: data valid mode 17h 00h [1:0] hsstart_high 18h 00h [7:0] hsstart_low HSYNC start position hsstrt[9:0] = 0d (default) 19h 00h [5:0] hblank_high 1Ah 8Ch [7:0] hblank_low Horizontal blank depth hblank[13:0] = 140d (default)
1/4 INCH VGA CMOS IMAGE SENSOR S5K433CA, S5K433LA Address (Hex) Reset Value Bits Mnemonic Description [3:0] sgg1 1st quadrisectional global gain sgg1[3:0] = 7d (default) 1Bh 77h [7:4] sgg2 2nd quadrisectional global gain sgg2[3:0] = 7d (default) [3:0] sgg3 3rd quadrisectional global gain sgg3[3:0] = 7d (default) 1Ch 77h [7:4] sgg4 4th quadrisectional global gain sgg4[3:0] = 7d (default) 1Dh 00h [6:0] pgcr Red channel gain pgcr[6:0] = 0d (default) 1Eh 00h [6:0] pgcg1 Green(Red row) channel gain or all channel gain (ccsm=0) pgcg1[6:0] = 0d (default) 1Fh 00h [6:0] pgcg2 Green(Blue row) channel gain pgcg2[6:0] = 0d (default) 20h 00h [6:0] pgcb Blue channel gain pgcb[6:0] = 0d (default) 21h 80h [7:0] offsr Red channel analog offset offsr[7:0] = 128 (default) 22h 80h [7:0] offsg1 Green(Red row) channel analog offset or all channel offset (ccsm=0) offsg1[7:0] = 128 (default) 23h 80h [7:0] offsg2 Green(Blue row) channel analog offset offsg2[7:0] = 128 (default) 24h 80h [7:0] offsb Blue channel analog offset offsb[7:0] = 128 (default) 25h 14h [6:0] pthresh Bad pixel threshold pthresh[6:0] = 20d (default) 26h 00h [7:0] adcoffs ADC offset adcoffs[7:0] = 0d (default) [5] - (Factory use only) [4] - (Factory use only) 27h 01h [3:0] p12stp (Factory use only) P12 start control
S5K433CA, S5K433LA 1/4” VGA CMOS IMAGE SENSOR Address (Hex) Reset Value Bits Mnemonic Description [7:5] - (Factory use only) - 28h 40h [4:0] - (Factory use only) - 29h 00h [7:0] - (Factory use only) - 2Ah 00h [7:0] blank Blank register for general purpose [5] - (Factory use only) [4] - (Factory use only) [3] - (Factory use only) [2] - (Factory use only) [1] - (Factory use only) 2Bh 02h [0] - (Factory use only)
signal outputs indicate that the output data is valid (hsdisp=1) or the output rows are valid (vsdisp=1). Figure 4. WOI definition. Control Register (mirch) and Vertical Mirror Control Register (mircv). Control Registers, subsr and subsc. The sub-sampling is performed only in the Bayer space.
Figure 5. Bayer Space Sub-Sampling Examples where cintr = 0 to {TBD}, cintc = 0 to {TBD}. by SFCM Integration Time Register (sint). The light integration period for each rows progresses with reading rows.
- Analog to Digital Converter ( ADC)
effective output bits is reduced, upper n-bits of output ports are valid and lower bits always has value of “0”. for the reset level and once for the actual signal level sampling. Figure 6. Relative Channel Gain
Figure 9. Quadrisectional Glabal Gain Control under dark state. If user wants the dark level which is not zero, the ADC Offset Register ( adcoffs) can be used. that the all the 8-bit data are used for an offset value without sign bit. less or greater than horizontally neighboring pixels in same color channel by the preset threshold value ( pthresh). reduces the line resolution in horizontal direction.
1/4 INCH VGA CMOS IMAGE SENSOR S5K433CA, S5K433LA TIMING CHART VERTICAL TIMING DIAGRAM Continuous Frame Capture Mode ( Default Case ) ( Delayed Vertical Sync Case) ( Vertical Data Valid Mode Case) vsdisp=1 HSYNC wrd (480 rows) 1 frame = wrd + vblank ( 525 rows ) wrp (14th row) VSYNC vswd (1row) rows DATA vblank (45 rows) HSYNC 1 frame = wrd + vblank VSYNC vsstrt DATA HSYNC (hsdisp=0) wrd VSYNC DATA vblank 2 rows vswd 2 rows HSYNC (hsdisp=1)
S5K433CA, S5K433LA 1/4” VGA CMOS IMAGE SENSOR HORIZONTAL TIMING DIAGRAM ( Default Case ) ( Delayed Horizontal Sync Case ) ( Horizontal Data Valid Mode Case ) hsdisp=1 wcw ( 640 columns ) 1 row = wcw + hblank ( 780 columns ) hswd ( 32 DCLK) hblank ( 140 columns ) HSYNC VSYNC DATA DCLK
10 DCLK
( 14th column) wcw 1 row = wcw + hblank hsstrt HSYNC VSYNC DATA DCLK hswd
42 DCLK 42 DCLK
42 DCLK hblank
1/4 INCH VGA CMOS IMAGE SENSOR S5K433CA, S5K433LA PACKAGE DIMENSION BOTTOM VIEW SIDE VIEW TOP VIEW Center of Image Area from package center) Max. Chip Rotation = ±1.5 degree Max. Chip Tilt = 0.05mm 0.51 ± 0.08 R 0.15
4 Corners
1.016 ± 0.18 11.176 ± 0.13 1.016 ± 0.08 1.65 ± 0.18 0.55 ± 0.05 Glass 6 43 48 1 19 30 48pin CLCC