S5K3A1EA SAMSUNG | Alldatasheet
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1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA S5K3A1EA (1/3” SXGA CMOS Image Sensor) Preliminary Specification Revision 0.4 Jun, 2004
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR DOCUMENT TITLE 1/3” Optical Size 1280x1024(SXGA) 2.8V / 1.8V CMOS Image Sensor
REVISION HISTORY
Revision No. History Draft Date Remark 0.0 Initial Draft Feb.03, 2004 Preliminary 0.1 DC Characteristics Changed. Mar.29.2004 0.2 Register Map Updated. Apr.09.2004 0.3 Imaging Characteristics Changed Jun.10.2004 0.4 Imaging Characteristics Changed Jun.11.2004 S5K3A1EA13 Product Added AC Characteristics Changed Ob_area Recommended Setting Changed
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA INTRODUCTION The S5K3A1EA is highly integrated single chip CMOS image sensor, fabricated by SAMSUNG 0.18um CMOS image sensor process technology. It is developed for image application to realize high efficiency photo sensor. The sensor has 1280 x 1024 effective pixels with 1/3 inch optical format. The sensor has on-chip 10-bit ADC blocks to digitize the pixel output and also on-chip CDS to reduce Fixed Pattern Noise (FPN) drastically. With its few interface signals and 10-bit raw data directly connected to the external devices, a camera system can be configured easily.
FEATURES
— Process Technology: 0.18 µm Dual Gate Oxide SPQM CMOS — Optical Size: 1/3 inch — Unit Pixel: 3.8 µm X 3.8 µm — Effective Resolution: 1280X1024, SXGA — Line Progressive Read Out. — 10-bit Raw Image Data Output — Windowing and Panning — Sub-Sampling (2X, 4X, 8X) — Timing Generator for Frame Memoryless Scaler — Timing Generator for Stepless Zooming — Continuous and Single Frame Capture Mode — Programmable Exposure Time and Gain Control — Auto Dark Level Compensation — Standby Mode for Power Saving — Maximum 15 Frames per Second for Full Fram e Readout with 24 MHz Output Data Rate — Bad Pixel Replacement — Dual Power Supply Voltage: 2.8V/1.8V (2.8V for analog, 1.8V for digital) — Package Type: 48-CLCC/PLCC PRODUCTS Product Code Power Supply Backend Process Description S5K3A1EA01 2.8V / 1.8 V None Monochrome image sensor S5K3A1EA02 2.8V / 1.8 V On-chip micro lens High sensitivity monochrome Image sensor S5K3A1EA03 2.8V / 1.8 V On-chip color filter and micro lens RGB color image sensor S5K3A1EA13 2.8V / 1.8 V On-chip color filter and micro lens RGB color image sensor
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR BLOCK DIAGRAM Timing Generator RSTN STBYN MCLK VSYNC HSYNC DCLK SCL SDA STRB Main Clock Divider I2C Interface Control Registers Active Pixel Sensor Array Row Driver Even Column CDS Odd Column CDS 10-bit Column ADC 10-bit Column ADC VDDD VSSD VDDA VSSA Post Processing DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 VDDIO VSSIO
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA PIXEL ARRAY MAP (TOP VIEW ON CHIP. DISPLAYED IMAGE WILL BE FLIPPED.) Active Pixels Optical Black Pixels (14,14) read out start point (0,0) Default Window of Interest 1280X1024 10 4 R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G R B G G
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR PIN CONFIGURATION DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 SDA SCL RSTN STBYN STRB VDDA VSSA TEST1 HSYNC VSYNC VSSIO First Readout Pixel DATA0 DATA9 MCLK DCLK VSSD VDDA VSSA VSSA VDDA VDDA VSSA VSSA VDDA VDDD VSSD VDDIO VDDD VDDA VSSA VSSA VDDA VDDA VSSA VSSA VDDA VDDD VSSD TEST2 VREF
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA MAXIMUM ABSOLUTE RATINGS Characteristic Symbol Value Unit Analog maximum absolute voltage (VDDA supply relative to VSSA ) VDDH -0.3 to 3.8 V Digital and I/O maximum absolute voltage (VDDIO supply relative to VSSIO VDDD supply relative to VSSD) V DDL -0.3 to 2.7 Input voltage VIN -0.3 to 2.7 Operating temperature TOPR -20 to +60 °C Storage temperature TSTG -40 to +125(1) -40 to +85(2) NOTES: 1. The maximum allowed storage temperature for S5K3A1EA01. 2. The maximum allowed storage temperat ure for S5K3A1EA02 and S5K3A1EA03.
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR
ELECTRICAL CHARACTERISTICS
(TA = -20 to +60°C, CL = 15pF) Characteristics Symbol Condition Min Typ Max Unit Operating voltage VDDH applied to VDDA pins 2.6 2.8 3.0 V VDDL applied to VDDIO and VDDD pin 1.65 1.8 1.95 Input voltage(1) VIH - 1.27 - - VIL - - - 0.57 Input leakage current(2) IIL V IN = VDDL -10 - 10 µA Input leakage current with pull-down(3) IILD V IN = VDDL 5 18 40 VOH IOH = -1µA VDDL- 0.05 - - V High level output voltage(4) IOH = -4mA 1.2 - - VOL IOL = 1µA - - 0.05 Low level output voltage(5) IOL = 4mA - - 0.45 High-Z output leakage current(6) IOZ V OUT = VSS or VDDL -10 - 10 µA Input capacitance(1) CIN - - - 4 pF ISTBL STBYN=Low(Active) All input clocks = Low 0 lux illumination applied to VDDIO and VDDD pin - - 10 µA Supply current ISTBH STBYN=Low(Active) All input clocks = Low 0 lux illumination applied to VDDA pin - - 10 µA IDDL f MCLK = 12MHz 0 lux illumination applied to VDDIO and VDDD pin - 10 15 mA IDDH f MCLK = 12MHz 0 lux illumination applied to VDDA pin - 20 25 mA NOTES: 1. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA, TEST1, TEST2 pins. 2. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA pins 3. Applied to TEST1, TEST2 pin 4. Applied to DCLK, HSYNC, VSYNC, DATA0 to DATA9 pin. I OH : High level output current 5. Applied to DCLK, HSYNC, VSYNC, DATA0 to DATA9, SCL, SDA pin. IOL : Low level output current 6. Applied to SDA pin w hen in High-Z output state
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR Imaging Characteristics (Light source with 3200K of color temperature and IR cu t filter (CM-500S, 1mm thick ness) is used. Electrical operating conditions follow the recommended typical values. The control registers are set to the default values. TA = 25°C if not specified.) NOTES: 1. Measured minimum output level at 100 lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole pixel area to eliminate the values from defective pixels. 2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values are used for color version. 3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec. 4. 20 log (saturation level/ dark leve l RMS noise excluding fixed pattern noise). 60dB is limited by 10-bit ADC. 5. 20 log (average output level / RMS noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure time 1/30 sec. 6. Difference between maximum and minimum pi xel output levels at zero illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from defective pixels. 7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to eliminate the values from defective pixels. 8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. 9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 rows at 25% of saturation level illumination for exposure time 1/30 sec. Characteristic Symbol Condition Min Typ Max Unit Saturation level(1) VSAT - 600 650 - mV Sensitivity(2) S - - 1500 - mV/lux sec Dark level(3) VDARK TA = 40°C - 4 8 mV/sec TA = 60°C - 20 40 Dynamic range(4) DR - - 60 - dB Signal to noise ratio(5) S/N - - 40 - Dark signal non-uniformity(6) DSNU TA = 60°C - - 40 mV/sec Photo response non- uniformity(7) PRNU - - 4 8 % Vertical fixed pattern noise(8) VFPN - 4 8 % Horizontal fixed pattern noise(9) HFPN - 4 8 %
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA AC Characteristics (VDDH = 2.8V ± 0.25V, VDDL = 1.8V ± 0.15V, TA = -20 to + 60 °C, CL = 10pF) NOTES: 1. T MCLK is the period of the master input clock, MCLK. Characteristic Symbol Condition Min Typ Max Unit Main input clock frequency fMCLK Duty = 50% 6 12 48 MHz Data output clock frequency fDCLK - 6 12 30 tPDMV VSYNC output - - 10 ns Propagation delay time from main input clock tPDMH HSYNC output - - 10 tPDMD DCLK output - - 6 tPDMO DATA output - - 10 tPDDV VSYNC output - - 4 Propagation delay time from data output clock tPDDH HSYNC output - - 4 tPDDO DATA output - - 4 Reset input pulse width tWRST RSTN=low(active) 5 - - TMCLK(1) Standby input pulse width tWSTB STBYN=low(active) 4 - - tPDMD DATA MCLK DCLK 0.5VDD HSYNC VSYNC tPDDO tPDMO tPDMD tPDDH tPDMH tPDDH tPDMH tPDDV tPDMV
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR I 2C Serial Interface Characteristics (1) NOTES: 1. I 2C is a proprietary Phillips interface bus. 2. T MCLK is the period of the master input clock, MCLK. Characteristic Symbol Condition Min Typ Max Unit Clock frequency fSCL - - - 400 kHz Clock high pulse width tWH SCL 0.6 - - µs Clock low pulse width tWL SCL 1.3 - - Clock rise/fall time tR/tF SCL, SDA - - 0.3 Data set-up time tDS SDA to SCL 0.1 - - Data hold time tDH SCL to SDA - - 0.9 START condition setup time tSTRS - 4 TMCLK(2) START condition hold time tSTRH - 4 STOP condition setup time tSTPS - 4 - - STOP to new START gap tGSS - 8 - - Capacitance for each pin CPIN SCL, SDA - - 4 pF Capacitive bus load CBUS SCL, SDA - - 200 Pull-up resistor RPU SCL, SDA to V DD 1.5 - 10 kΩ SDA SCL 0.1VDD 0.9VDD tSTRS tSTRH tWL tDH tWH tDS tF tR 0.1VDD 0.9VDD tSTPS RSTN STBYN tWSTB tWRST MCLK system reset partial power down complete power down
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA PIN DESCRIPTION Pin No I/O Name Function VDDD (6,25,48) Power Digital power supply For logical circuit (VDDL) VDDIO (5) Power For I/O circuit (VDDL) VSSD (19,26,47) Power 0V (GND) VSSIO (20) Power 0V (GND) VDDA(1,4,21,24, 28,29,37,44,45) Power Analog power supply For analog circuit (VDDH) VSSA(2,3,22,23, 27,30,36,43,46) Power 0V (GND) MCLK (7) I Master clock Master clo ck pulse input for all timing generators. RSTN (40) I Reset Initializing all the device registers. (Active low) STBYN (39) I Standby Activating power saving mode. ( high=normal operation, low=power saving mode ) STRB (38) I Strobe Triggering the integration start and stop when single frame capture mode. DATA0~DATA9 (8 ~ 17) O Image data output 10-bit image data outputs. When ADC resolution is reduced, the unused lower bits are set to 0. DCLK (18) O Data clock Image data output synchronizing pulse output. HSYNC (32) O Horizontal sync clock Horiz ontal synchronizing pulse or data valid signal output. VSYNC (31) O Vertical sync clock Vertical synchronizing pulse or line valid signal output. SCL (41) I Serial interface clock I2C serial interface clock input SDA (42) I/O Serial interface data I2C serial interface data bus (external pull-up resistor required) VREF (35) I/O Reference voltage For proper oper ation, the external capacitor larger than 0.1uF must be connected between VREF and VDDA. TEST1 (33) I Test input 1 Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. TEST2 (34) I Test input 2 Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins.
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR CONTROL REGISTERS Address (Hex) Reset Value Bits Mnemonic Description [7] p2_r_con (Factory use only) CDS timing control [6] bprm Bad pixel replacement mode 0b: disabled (default), 1b: enabled [5] ccsm Color channel separation mode 0b: not separated (default), 1b: separated [4:2] mcdiv Main clock divider 000b: DCLK=MCLK(default), 001b: DCLK=MCLK÷2 010b: DCLK=MCLK÷4, 011b: DCLK=MCLK÷8 100b: DCLK=MCLK÷16, 101b: DCLK=MCLK÷32 111b: forbidden value [1] shutc Electronic shutter mode 0b: disabled (default), 1b: enabled 00h 01h [0] adcres ADC resolution 0b: 8-bit, 1b: 10-bit (default) [7] shut_err_cor Shutter error correction register [6] Not_use [5] mircv Vertical mirror control 0b: normal (default), 1b: mirrored [4] mirch Horizontal mirror control 0b: normal (default), 1b: mirrored [3:2] subsr Row sub-sampling mode 00b: disabled (default), 01b: 2X, 10b: 4X, 11b: 8X 01h 00h [1:0] subsc Column sub-sampling mode 00b: disabled (default), 01b: 2X, 10b: 4X, 11b: 8X 02h 00h [2:0] wrp_high 03h 0Eh [7:0] wrp_low Row start point for window of interest wrp[10:0] = 14d(default) 04h 00h [2:0] wcp_high 05h 0Eh [7:0] wcp_low Column start point for window of interest wcp[10:0] = 14d(default) 06h 04h [2:0] wrd_high 07h 00h [7:0] wrd_low Row depth for window of interest wrd[10:0] = 1024d(default) 08h 05h [2:0] wcw_high 09h 00h [7:0] wcw_low Column width for window of interest wcw[10:0] = 1280d(default) 0Ah 80h [7:0] offsdef (Factory use only) Analog offset reference offsdef[7:0] = 128d (default)
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA Address (Hex) Reset Value Bits Mnemonic Description 0Bh 04h [7:0] sint_high 0Ch 65h [7:0] sint_low Integration time in single frame capture mode sint[15:0] = 1125d (default) 0Dh 04h [7:0] cintr_high 0Eh 65h [7:0] cintr_low Row-step integration time in continuous frame capture mode cintr[15:0] = 1125d (default) 0Fh 00h [7:0] cintc_high 10h 00h [7:0] cintc_low Column-step integration time in continuous frame capture mode cintc[15:0] = 0d (default) [7] hspolar HSYNC polarity 0: active high (default), 1: active low [6] hsdisp HSYNC display mode 0: sync mode (default), 1: data valid mode [5] vspolar VSYNC polarity 0: active high (default), 1: active low [4] vsdisp VSYNC display mode 0: sync mode (default), 1: data valid mode [3] global_mod Single frame capture integration mode Field shift shutter mode [2] roll_mod Single frame capture integration mode Rolling shutter mode [1] mech_mod Single frame capture integration mode simultaneous frame integration with mechanical shutter 11h 00h [0] sfcen Single frame capture mode enable 0b: disabled (default), 1b: enabled 12h 01h [7:0] vswd VSYNC width vswd[7:0] = 1d (default) 13h 00h [7:0] vsstrt_high 14h 00h [7:0] vsstrt_low VSYNC start position vsstrt[9:0] = 0d (default) 15h 00h [7:0] vblank_high 16h 65h [7:0] vblank_low Vertical blank depth vblank[12:0] = 101d (default) 17h 20h [7:0] hswd HSYNC width hswd[7:0] = 32d (default) 18h 00h [7:0] hsstrt_high 19h 00h [7:0] hsstrt_high HSYNC start position hsstrt[9:0] = 0d (default) 1Ah 00h [7:0] hblank_high 1Bh 8Eh [7:0] hblank_low Horizontal blank depth hblank[15:0] = 142d (default)
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR Address (Hex) Reset Value Bits Mnemonic Description 1Ch 00h [6:0] pgcr Red channel gain pgcr[6:0] = 0d (default) 1Dh 00h [6:0] pgcg1 Green(Red row) channel gain or all channel gain (ccsm=0) pgcg1[6:0] = 0d (default) 1Eh 00h [6:0] pgcg2 Green(Blue row) channel gain pgcg2[6:0] = 0d (default) 1Fh 00h [6:0] pgcb Blue channel gain pgcb[6:0] = 0d (default) 20h 0Fh [4:0] sgg1 1st quadrisectional global gain sgg1[4:0] = 0F(default) 21h 0Fh [4:0] sgg2 2nd quadrisectional global gain sgg2[4:0] = 0F(default) 22h 0Fh [4:0] sgg3 3rd quadrisectional global gain sgg3[4:0] = 0F(default) 23h 0Fh [4:0] sgg4 4th quadrisectional global gain sgg4[4:0] = 0F(default) 24h 80h [7:0] offsr Red channel analog offset Offsr[7:0] = 128 (default) 25h 80h [7:0] offsg1 Green(Red row) channel analog offset or all channel offset (ccsm=0) offsg1[7:0] = 128 (default) 26h 80h [7:0] offsg2 Green(Blue row) channel analog offset offsg2[7:0] = 128 (default) 27h 80h [7:0] offsb Blue channel analog offset offsb[7:0] = 128 (default) [7] clipen (Factory use only) Reset clipping enable 28h 14h [6:0] pthresh Bad pixel threshold pthresh[6:0] = 20d (default) 29h 00h [7:0] adcoffs ADC offset (count delay register) adcoffs[7:0] = 0d (default) ADLC formula : D final = D(n) + adcoffs When adcoffs[7] is 1 , adc offset is +adcoffs[6:0], else adc offset is - adcoffs[6:0]
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA Address (Hex) Reset Value Bits Mnemonic Description [7:5] stbystrt (Factory use only) Stand-by start 2Ah 40h [4:0] stbystp (Factory use only) Stand-by stop 2Bh 00h [7:0] rxstrt (Factory use only) Reset start control 2Ch 00h [7:0] blank Blank register for general purpose [7:6] Not_use [5] id_inv (Factory use only) Line color inversion [4] sck_inv (Factory use only) Column color inversion [3:2] Not_use [1] i2ctest (Factory use only) IIC test mode 2Dh 02h [0] nandtree (Factory use only) NAND tree test mode [7] adlc_mod_d Adlc mode always enable when this register is high. 0b: disabled (default), 1b: enabled [6] adlc_mod_c Adlc mode works when gain values are changed 0b: disabled (default), 1b: enabled [5] adlc_mod_b Adlc mode works when shutter values are changed 0b: disabled (default), 1b: enabled [4] adlc_mod_a Adlc mode works till adlc length value 0b: disabled (default), 1b: enabled [3:2] feedback_gain_B Feedback gain value about ADLC 00b : 0, 01b : 0.5(default), 10b : 0.75, 11b : 1 ADLC formula : D final = D(n) + adcoffs D(n) = A*(OB(n) + OB(n-1)) + B*D(n-1) 2Eh 06h [1:0] feedback_gain_A Feedback gain value about ADLC 10b : 0.25(default), 11b : 0.125
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR Address (Hex) Reset Value Bits Mnemonic Description [7] dckout_en DCK pad control 0b : output enable (default), 1b : stable value [6] dfo I/O driver fan-out control register. [5] fixvs VSYNC always high at frame start point. 0b: disabled (default), 1b: enabled [4] isp_sel (Factory use only) [3] ob_sel ADLC formula : D = D(n) + adcoff D(n) = A*(OB(n) + OB(n-1)) + B*D(n-1) 0b : OB(n-1) = OB(n-1) (default) 1b : OB(n-1) = OB(n) [2] ob_area OB area selection 0b:128*8 (default), 1b:512*2 (recommended) 2Fh 00h [1:0] adlc_length ADLC function works only during this value when adlc_mod_a enabled, 00b : 1 frame, 01b : 2 frames, 10b : 3 frames, 11b : 4 frames [7:6] Not_use [5] pwr_save2 (Factory use only) rx & tx signals are enable only active area. 0b: disabled (default), 1b: enabled [4] pwr_save1 (Factory use only) 0b: disabled (default), 1b: enabled [3] ggo_en (Factory use only) 0b: disabled (default), 1b: enabled [2] rsm_en (Factory use only)When this register is zero, H-sync keeps same period in one frame. [1] gbmod Guardband mode 0b: disabled, 1b: enabled(default) 30h 02h [0] stpless_mod Stepless mode enable 0b: disabled (default), 1b: enabled 31h 1Eh [7:0] gb_start Guardband start position 32h 32h [7:0] gb_end Guardband end position 33h 00h [5:0] vs_postc_high 34h 00h [7:0] vs_postc_low Keep the same frame in zoom mode. This register compensates remainder of frame. [7:4] p12_stp (Factory use only) CDS timing control 35h CCh [3:0] p11_stp (Factory use only) CDS timing control [7:4] p2r_stp (Factory use only) CDS timing control 36h CCh [3:0] p2_stp (Factory use only) CDS timing control
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA Address (Hex) Reset Value Bits Mnemonic Description 37h 00h [7:0] holdline_high 38h 00h [7:0] holdline_low Active output delay about its register value 39h 0Ah [7:0] vsend_ofset-high This register value is must larger than OB line. [7] Not use [6] tx_add (Factory use only)Add tg to reduce NIT. [5] shutx_sel (Factory use only)Enlarge shutter TX width to reduce NIT. [4] cal_en (Factory use only) calibration enable 3Ah 1Ah [3:0] cal_stp (Factory use only) calibration signal control
the duty must be within 40% to 60%. sync signal outputs indicate that the output data is valid (hsdisp=1) or the output rows are valid (vsdisp=1). Figure 1. WOI definition. Control Register (mirch) and Vertical Mirror Control Register (mircv).
Bayer space sub-sampling examples are shown. Figure 2. Bayer Space Sub-Sampling Examples Table 1. Restriction of h-blank period (minimum 1H-period(dck) Setting procedure of hblank, vblank and vs_postc is as follows.
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR In CFCM operation, the integration time is controlled by shutter operation. The shutter operation is done when shutter control register (shutc) is set to “1”. In shutter operation, the integration time is determined by the Row Step Integration Time Control Register(cintr) and Column Step Integration Time Control Register(cintc) In CFCM integration time control. There are two different modes. One is normal shutter mode. The other is shutter TX wide mode to reduce nonlinear integration time. The effective integration time(EIT) formulas of each mode are as follows. 1) normal mode (00h[2] = 1, 01h[7] = 1, 3Ah[5] = 1) EIT = (cintr - 1) x ( (wcw>>subsc) + hblank ) + cintc + 145 (dck) restriction of cintr? 1 <= cintr <= (wrd>>subsr) + vblankr –1 restriction of cintc? 0 <= cintc <= (wcw>>subsc) + hblank - 7 2) shutter TX wide mode (00h[2] = 1, 01h[7] = 0, 3Ah[5] = 1) EIT = (cintr - 1) x ( (wcw>>subsc) + hblank ) + cintc + 145 (dck) restriction of cintr? 1 <= cintr <= (wrd>>subsr) + vblankr - 1 restriction of cintr? case of (1 <= cintr <= (wrd>>subsr) + vblankr - 2) 0 <= cintc <= (wcw>>subsc) + hblank - 7 case of (cintr = (wrd>>subsr) + vblankr - 1) 0 <= cintc <= (wcw>>subsc) + hblank - 195 1-8. Single Frame Capture Mode(SFCM) Integration Time Control To capture a still image, SFCM can be se t by Single Frame Capture Enable Register( sfcen). There are two types of integration mode implemented. In the rolling shutter mode (sfcim=0), the integration time is controlled by SFCM Integration Time Register ( sint). The light integration period for each rows progresses with reading rows. The integration time is expressed as : Integration Time = sint * (1 line time) In the mechanical shutter mode ( sfcim=1), the integration time for all rows is the period during the external input signal, STRB is active. After STRB goes to be inactive, the external mec hanical shutter should shut off incident lignt on image sensor and the data readout sequence starts. 2. Analog to Digital Converter ( ADC) The image sensor has on-chip ADC. Two-channel co lumn parallel ADC scheme is used for separated color channel gain and offset control. 2-1. ADC resolution The default value of ADC resolution is 10bit and can be changed to 8bit or 9bit by control the ADC Resolution Control Register (adcres). Lowering ADC resolution reduces the required minimum line time. When the number of effective output bits is reduced, upper n-bits of output ports are valid and lower bits always have values of “0”. 2-2. Correlated Double Sampling ( CDS ) The analog output signal of each pixel includes some te mporal random noise caused by the pixel reset action
sampled twice, once for the reset level and once for the actual signal level. Figure 3. Relative Channel Gain ggo_en=L, the global gain is determined by the following formula.
Table 2. Recommended Minimum Global Gain Setting (adcres = H)
approximation curve as shown in Figure 6. Figure 6. Quadrisectional Glabal Gain Control
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA 3. Post Processing 3-1. Dark Level Compensation The dark level of Image sensor is defined as average out put level without illumination. It includes pixel ouput caused by leakage current of the photodi odes and ADC offset. To compensate t he dark level, the output level of optical black(OB) pixels can be a good reference value. When Auto Dark Level Compensation Register ( dlcm) is set, the image sensor detects the OB pixel level at the start of every frame and anglog-to-digital conversion range is shifted to compensate the dark level for that frame. So, the resulting output data of that frame will be almost zero under dark state. If user wants the dark level which is not zero, the ADC Offset Register ( adcoffs) can be used. The lower 7-bit value represent the offset value in outout code for compensation and the MSB is the sign to define whether the offset is positive ( adcoffs[7]=0) or negative ( adcoffs[7]=1). When not in auto dark level compensation mode, the adcoffs[7:0] act as a output code value to subt ract the output image data. Please notify that the all the 8-bit data are used for an offset value without sign bit. ADLC formula : Dfinal = D(n) + adcoffs D(n) = (feed_gain_a)*(OB(n) + OB(n-1)) + (feed_gain_b)*D(n-1) 3-2. Bad Pixel Replacement When the Bad Pixel Replacement Register ( bprm) is enabled, the image sensor check that the image data is less or greater than horizontally neighboring pixels in same color channel by the preset threshold value (pthresh). If satisfied, the output of the pixel is replaced by t he averaged value of the neighboring two pixels. The detectable defected pixels are rare and the bad pixel replacement action can remove defected image effectively. But it reduces the line resolution in horizontal direction. 4. I2C Serial Interface The I 2C is an industry standard serial interface. The I 2C contains a serial two-wire half duplex interface that features bi-directional operation, master or slave mode. The general SDA and SCL are the bi-directional data and clock pins, respectively. These pins are open-drain type ports and will require a pull-up resistor to VDD. The image sensor operates in salve mode only and the SCL is input only. The I 2C bus interface is composed of following parts : START signal, 7-bit slave device addr ess (0010001b) transmission followed by a read/write bit, an acknowledgement signal from the slave, 8-bit data transfer followed by an acknowledgement signal and STOP signal. The SDA bus line may only be changed while SCL is low. The data on the SDA bus line is valid on the high-to-low transition of SCL.
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA TIMING CHART VERTICAL TIMING DIAGRAM Continuous Frame Capture Mode ( Default Case ) ( Delayed Vertical Sync Case) ( Vertical Data Valid Mode Case) vsdisp=1 wrp(14th row) VSYNC HSYNC vswd (1row) wrd (1024 rows) vblank (101 rows) DATA 1 frame = wrd + vblank ( 1125 rows ) 10 rows = vsend_ofset 1 frame = wrd + vblank ( 1125 rows ) wrp(14th row) VSYNC HSYNC DATA vsstrt vswd 2rows2rows 10 rows = vsend_ofset wrp(14th row) wrd (1024 rows) vblank (101 rows) VSYNC HSYNC (hsdisp=0) DATA HSYNC (hsdisp=1) 10 rows = vsend_ofset
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR VERTICAL TIMING DIAGRAM (continued) ( Short OB Line & Fixed Vertical Sync mode) isp_sel = 1& fix_vs = 1 ( Short OB Line & Normal Sync mode) isp_sel = 1, vsstrt = 1117d, vswd = 2d wrp(14th row) VSYNC HSYNC vswd (1row) wrd (1024 rows) vblank (101 rows) DATA 1 frame = wrd + vblank ( 1125 rows ) wrp(14th row) 4 rows = vsend_ofset Normal frame output wrp(14th row) wrd (1024 rows) wrp(14th row) vblank (101 rows) DATA HSYNC VSYNC DEFAULT VSYNC vsstrt (1117 rows) 4 rows = vsend_ofset vswd (2rows) Normal frame output 1 frame = wrd + vblank ( 1125 rows )
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA VERTICAL TIMING DIAGRAM (continued) Single Frame Capture Mode ( Rolling Shutter Case, sfcen = 1 & roll_mod = 1 ) ( Mechanical Shutter Case, sfcen=1 & mech_mod = 1 ) Normal frame output VSYNC HSYNC DATA STRB Integration time for 1st readout row Integration time for 2nd readout row Integration time for 3rd readout row Integration time for 4th readout row sint X (1 row time) = integration time wrp(14th row) wrd (1024 rows) External Mechanical Shutter VSYNC HSYNC DATA STRB Can be opened Should be closed wrd (1024 rows) wrp(14th row) Normal frame output Integration time for all pixels
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR ( Global Shutter Case, sfcen=1 & global_mod = 1 ) VSYNC HSYNC DATA STRB wrd (1024 rows) wrp(14th row) Normal frame output Integration time for all pixels
1/3 INCH SXGA CMOS IMAGE SENSOR S5K3A1EA HORIZONTAL TIMING DIAGRAM ( Default Case ) ( Delayed Horizontal Sync Case ) ( Horizontal Data Valid Mode Case ) hsdisp=1 wcw 1 row = wcw + hblank hsstrt HSYNC VSYNC DATA DCLK hswd wcw HSYNC VSYNC DATA DCLK hblank wcw ( 1280 columns ) 1 row = wcw + hblank ( 1422 columns ) hswd hblank ( 142 columns ) HSYNC VSYNC DATA DCLK wcp ( 14th column)
10 DCLK
S5K3A1EA 1/3” SXGA CMOS IMAGE SENSOR PACKAGE DIMENSION 48pin CLCC (unit = mm) BOTTOM VIEW SIDE VIEW TOP VIEW 0.51 ± 0.08 R 0.15
4 Corners
1.016 ± 0.18 11.176 ± 0.13 1.016 ± 0.08 1.65 ± 0.18 0.55 ± 0.05 Glass Center of Image Area from package center) Max. Chip Rotation = ±1.5 degree Max. Chip Tilt = 0.05mm 6 43 481 19 30