S5H1420 SAMSUNG | Alldatasheet
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-1- [Channel Lab] 4VXPO10#09 .BFUBOEPOH :PVOHUPOHHV 4VXPOTJ (ZFPOHHJEP ,PSFB S5H1420 [Channel Decoder for DVB-S/DSS] DATA SHEET Samsung Electronics Co, Ltd. 10 Jan. 2004 (Version 4.5.1) Note: This documentation is preliminary and is subject to change. Samsung Electronics Co, Ltd. reserves the right to do any kind of modification in this data sheet regarding hardware or software implementations without notice. Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 2 TABLE O F C ONTENTS p age Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 3 1. INTRODUCTION
1.1 Overview
The S5H1420 is a single chip channel decoder IC f or DBS (Di gital Broadcasting System for Satellite) receiver. It consists of a multi-standard QPSK/BPSK demodulator and FEC (Forward Error Correction) decoder com pliant with DVB-S and DSS standa rd. For multi-antenna control it provide s DiSEqC1.x and 2.0 standards.
1.2 Features
■ Compliant to DVB-S and DSS standard. ■ Single chip decoder (ADC/QPSK/FEC). ■ Flexible Interface (I2C, MPEG2). ■ DiSEqC 1.x or 2.0 specification support. ■ Satellite dish control. ■ DC offset cancellation. ■ Automatic gain control ■ Nyquist filter: 0.35 for DVB-S, 0.2 for DSS. ■ Fully digital synchronization. Symbol timing recovery range up to ± 50000 ppm. Carrier recovery range up to ±12.5% of symbol rate. ■ Carrier offset cancellation up to ±1/2sampling frequency ■ Modulation rate from 1 to 87Mbps(1 ~ 50 Msps) ■ QPSK demodulation quality estimation ■ Viterbi decoding quality estimation. Viterbi Input and output BER measurement. Support depuncturing code rate from 1/2 to 7/8. ■ Convolutional deinterleaver and Reed-Solomon decoder ■ Automatic byte and frame synchronization ■ Automatic spectral inversion ambiguity resolution. ■ I2C repeater for RF part ■ Power down control ■ Low power CMOS technology ■ 3.3V Single power using diode for 2.5V ■ Compact size package: 64LQFP-1010
1.3 Applications
1.4 Ordering information
Type Number Package Description 1. S5H1420X01 64 LQFP-1010 Plastic Low Profile Quad Flat Package; 64 leads (lead length 1.0mm) Body 10x10x1.0 mm Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 4
1.5 Functional bock diagram
- PIN INFORMATION
2.1 Pin Assignment
Figure1: Pin-out for 64-pin LQFP S5H1420 64-LQFP Top View VSEL RESET_N ERROR SYNC VDD25 DATA0 DATA1 DATA2 VDD25 VSS25 ID_SEL1 ID_SEL0 CLK_SEL SCL SDA VDD25 VSS25 RFSDA FMHZCLKOUT TEST_SEL0 DATA6 NC AVDD_PLL DATA7 VSS33 AVDD_ADC ADC_OSC_IN VDD25 RFSCL VSS25 VDD33 VREF_H AGC VSS25 AVSS_ADC VDD25 BYTE_CLK LNB_EN VREF_L AVBB_ADC QN AVSS_ADC QP OLF DiSEqC TEST_SEL1 AVDD_ADC CML VALID NC VSS25 IP 383940424344454748 343637 33 VSS33 VDD33 DATA3 DATA4 DATA5 AVSS_PLL AVBB_PLL AVDD_PLL XTAL_OUT XATL_IN AVSS_PLL 2 3 4 5 6 7 8 10 11 12 13 14 15 16 354146 IN Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 5
2.2 Pin descriptions
Pin Name I/O Cell Type Pin Number Description OLF Input 1 LNB Over Load Flag RESET_N Schmitt Trigger 2 H/W Reset (Active Low) ERROR Error_out 3 Error indicator output SYNC Sync_out 4 Synchronization output VALID Valid_out 5 Valid data period NC NC 6 NC DATA Output [7] 30 MPEG2 Stream Serial Data DATA Output [7:0] [:] MPEG2 Stream Parallel Data SDA I/O-open drain(5V) 21 Serial Data from host SCL Input(5V) 22 Serial Clock from host CLK_SEL Input 23 Master Clock Select ID_SEL0 Input 24 I2C Address Select[T0] ID_SEL1 Input 24 I2C Address Select[T1] TEST_SEL0 Input 28 Test Mode Select[T2] TEST_SEL1 Input 29 Test Mode Select[T3] NC NC 18 No connection XTAL_IN Oscillator Input 36 Crystal Oscillator Input XTAL_OUT Oscillator Output 37 Crystal Oscillator Output FMHZCLKOUT Output 38 Reference Clock Output RFSDA I/O-open drain (5V) 41 RF Module Control SDA RFSCL n-ch-open drain (5V) 42 RF Module Control SCL ADC_OSC_IN Oscillator Input 45 Oscillator Input AVDD_ADC Digital Power 46 ADC Total Power IP Inphase Positive 47 ADC Analog Input IN Inphase Negative 48 ADC Analog Input QN Quadrature Negative 50 ADC Analog Input QP Quadrature Positive 51 ADC Analog Input VREF_L Analog Reference 53 ADC Bottom Reference Voltage VREF_H Analog Reference 54 ADC Top Reference Voltage CML Analog Reference 55 Common Mode Level Voltage AGC n-ch Open Drain(5V) 60 Gain Control Output DISEQC Bidirectional (5V) 61 Antenna Select BYTE_CLOCK Output (3.3V) 62 Data Transfer clock VSEL Output 63 LNB Voltage Select Flag LNB_EN Output 64 LNB Enable Flag RF Interface & ADC Power Supply (24) AVDD_ADC 46, 57 AVSS_ADC 56, 49 ADC AVBB_ADC 52 AVDD_PLL 31 AVSS_PLL 32 AVBB_PLL 33 AVDD_PLL 34 PLL AVSS_PLL 35 VSS33 13, 39 IO VDD33 14, 40 VSS25 7, 19, 26, 43, 58 Logic VDD25 8, 20, 27, 44, 59 Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 6 3. FUNCTIONAL DESCRIPTION
3.1 Signal processing
3.1.1 I and Q inputs
The dual ADC can get differe ntial (IP/IN, QP/QN) o r single inputs (IP, QP), I/Q signals from the tuner are fe d to th e IP and QP inputs th rough a DC coupling capacitor a nd IN and QN must b e set DC voltage as CML (typical: 1/2VDD). Th e reference voltage of high [VREF-H] and low [VREF-L] sho uld be supplied from external generator for application flexibility.
3.1.2 PRE-AGC
The po wer o f I/Q signal is com pared to a progra mmable thre shold value, and the differe nce is integrated. This signal is then converted into a Pulse Width Modulation (PWM) signal to drive the AGC output and it will be lo w pass filtered by a simple RC analog filter to cont rol the gain comma nd of any amplifier before th e A/D converter. T he PWM o utput ope rates at fclk/ (1, 4, 8 and 16) i n order to decrease the radiated noise and to simplify the filter design, and is a 5 V tolerant open drain stage. The PRE-AGC Controls are in Address 0x07 and the PRE-AGC integrator register is in Address 0x15.
3.1.3 Root raised cosine and rate conversion filter
The Root rai sed cosi ne (RRC) and ra te conversion f ilter performs anti-ali asing filtering, root raise d cosine shaping, rate conversion, timing synchronization and tracking with the timing loop. Two roll-off factors are available: 0.35 (DVB-S) and 0.20 (DSS).
3.1.4 Offset cancellation
This device sup presses the resi dual I/Q DC comp onent in the QPSK system control registe r in Addresses 0x05 and 0x06.
3.1.5 POST-AGC
The POST-AGC shall be able to adjust the gain of the incoming I/Q sample from the RRC and rate conversion filter and implement the closed loop that sets the gain adjustment. The reset value (0x8000) of the POST-AGC integ rator register can allow an initial set tling t ime of less t han 50k master clo ck periods. The POST-AGC Controls are in Address 0x08 and the POST-AGC integrator register is in Address 0x16.
3.2 Timing recovery
3.2.1 Timing control
The timing loop is programmed with the expected symbol frequency. We have δ parameter, which determine one or two sampling method. It can be expressed as: ( 1+ α)ĕ fs ym > clkf for δ =1. In contrast, (1+ α)ĕ fs ym < clkf for δ =2. Where α is roll-off factor: 0.35 for DVB-S, 0.2 for DSS. Thus Timing NCO frequency word register setting is: NCO frequency word = sym clk f f ĕ224ĕδ Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 7
3.2.2 Loop equation
The timing loop may be considered as a second order loop. The loop equation may be calculated using the following formula: ε= 1<< ((Pg+8) – Ig) ω = Φtĕ(1<< Ig) Where, Pg is propagational gain, Ig is integral gain and Φt is timing factor. Φt = 5.0 × And we can choose Loop Bandwidth (BL), as follows: sym clk f f 242 11(2 1 2ξξω +×××=BL Where ξ is the reference level of the ε and ω. ξ = ω ε×
3.2.3 Timing lock indicator
The timing detecto r need to a lot of symbol s for stab ilization in orde r to lock after tuning freq uency change of RF and it takes a 1-bit input signal, and uses the presence or absence of locking information to either count up or count down respectively. The counter operates up to rea ches its maximum value wh en the lock si gnal goes active. Two cases can cause the lock signal to go to unlocked state; one is assertion of the active-low reset and the other the counte r go ze ro agai n. Use r can monitor the M SB 8 bits of TLL (timing lock loo p) counter in Address 0x1a and the TLL lock flag in Address 0x14.
3.3 Carrier recovery
The tracking range of the derotator is ± fclk /2 (± fsampling/2). This algorithm is used wit h QPSK reception, over a small range of capture pha ses and with a channel noise value over 3.0 dB.
3.3.1 Loop equation
Like the timing loop, the carrier loop is a second-order system where two parameters, ε and ω. ε= 1<< ((Pg+8) – Ig) ω = Φpĕ(1<< Ig) Where, Pg is propagational gain, Ig is integral gain and Φp is phase factor. sym clk f f 242 Φp = 75.4 × Also, we can choose Loop Bandwidth (BL), as follows: 11(2 1 2ξξω +×××=BL Where ξ is the reference level of the ε and ω. ξ = ω ε×
3.3.2 Carrier lock detector
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DBS Channel Decoder for DVB-S/DSS - - 8 The carrier lock detector operates the same as the timing lock detector in the Phase locked loop (PLL). User can monitor the MSB 8 bits of PLL lock counter in Address 0x19 and the PLL lock flag in Address 0x14.
3.3.3 Derotator frequency
The derotator frequency can be either measured (read operation) or forced (write operation). fderot = 2sym clk f f
3.3.4 Automatic frequency detector
The automatic frequency detector (AFD) can evaluate the carrier frequency offset quickly, and may be coupled to the carrier recovery loop. The digital loop filter of PLL has two path s, pr oportional an d integral, with program mable gai n respectively. The integ ral path co ntains an accumulator whose conte nts can b e an alyzed a s a averaged carrier frequency offset. The phase error signal goes into two paths, the respe ctive gains are applied, the “I” path is integrated, and the two are add ed together. A Kicker of AFD c an help PLL to achieve lock fast. The Kicker find s the phase error sig nal for large transitions, inserts a large value, into the “I” path. Therefore, PLL can trace the large frequency offset.
3.3.5 False lock
A false lock occurs when phase lock has been detected in the QPSK, but the correct central frequency has not yet been reached. This situat ion occurs in QPSK for frequency offset points that are multiples of fsym /4, where fsym is the QPSK symbol rate, and also at other offsets dictated by the discrete nat ure of the carri er recovery loop. Therefore, the carri er recovery loop must be ha ndled to take care of a false lock condition.
3.4 Forward Error Correction
3.4.1 FEC modes
Since the S5H1420 is a multi-standard decoder, several combinations are possible, at different levels: ■ the demodulator may accept either QPSK or BPSK signal s - the only impact is on the carrier algorithm choice. The algorithm choice also affects the carrier lock detector and the noise evaluation. ■ there are two prim ary options concerning the FEC operation - between DVB-S, DSS and Reserved Mode. ■ there a re two options concerning th e FEC feedi ng. The first is IQ flow, whi ch is th e usual case in QPSK modes DVB-S or DSS. The second mode is I-only flow, used for BPSK. The FEC Mode Register is in Address Hex 22. In Modes DVB-S and DSS, data is fed to the Soft Decisions.
3.4.2 Soft decisions
The adaptive equalizer output is converted into 4-bit sign-magnitude format by the soft decision block, for use by the Viterbi decode r. The MSB corre sponds to the sliced bit value. The 3 LSBs of the soft decisions represent the confidence of the sli ced bit value, where 111 are high confidence, and 000 is low confide nce. A prog rammable set of thresh olds can be u sed in gene rating the three LSBs and, consequently, in optimizing the Viterbi decoder performance as a function of code rate.
3.4.3 Viterbi decoder and synchronization
The co nvolutional co des are generated by the polynomial Gx = 171 octet s and G y = 133 octets in modes DVB-S or DSS. The Viterbi decoder computes for each symbol the metrics of the four possible paths, p roportional to the square of the Euc lidian d istance b etween the received I and Q and th e theoretical symbol value. The puncture rate and phase are estimated on the error rate basis. Several rates are allowed and may be enabled/disabled through register programming: Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 9 ■1/2, 2/3, 6/7 for DSS For each enabled rate, the current error rate is compared to a programmable threshold. If it is greater than this threshold, another phase (or another rate) is tried until the right rate is obtained. A programmable hysterics is added to avoid losing the phase during short-term perturbation. The rate may also be imposed by external softwa re, and th e phase is in cremented only upon re quest by th e microprocessor. The e rror rate may be read at any ti me in ord er to use a n algorithm other than that implemented. The Viterbi d ecoder prod uces an absol ute deco ding. The decod er is cont rolled via several Viterbi Threshold Registers (Registers 29, 2A, 2B, 2C, 2D and 2E). For each Viterbi Threshold Register, bits 7 to 0 re present a norm alization rate th reshold – t he average number of n ormalization occurring during sync periods. The sync period is controlled via Viterbi Sync Register (Register 2F). The puncture Rate and Viterbi initial configuration is in Add ress 30, 31. The automatic rate research is o nly done through the enabled rates (see the corresponding bit set in th e Puncture register). In DSS, it is reco mmended that you disable puncture rates 3/4, 5/6 and 7/8 in order to save time in the synchronization process. The Viterbi decoder sync search can control using the Puncture register.
3.4.4 Synchronization
In DVB-S, the packet length after inner decoding is 204. The sync word is the first byte of each packet. Its value is Hex 47, but this value is co mplemented every 8 packets. In DSS, the pa cket length is 147 and the sync word is Hex 1D. An Up/Down Sync co unter co unts whenever a sync word is recognized with the corre ct timing an d counts down during each missing sync word. This counter is bounded by a programmable maximum - when this value is reached, the SYNC_FLAG bit (“locked”) is set in the SYNC02 register. When the event counter counts down to until 0, this flag is reset.
3.4.5 Error monitoring
A 16-bit counter, ERRCNT, allows the counting of errors at different levels. ERRCNT is fed either by: ■ the input QPSK bit errors (that are corrected by the Viterbi decoder), or, ■ the bit, or, ■ the byte error (it will be corrected by the Reed-Solomon decoder) ■ the packet error (It is uncorrectable and lead to a pulse at the ERROR output) The content of ERRCNT may be transferre d to t he read only reg isters ERR_CNT_L (LSB) and ERR- CNT_H (MSB). Two functional modes are proposed, depending on a control register bit: 1. ERR_DISP = 0. The uncorrectable block flag ERROR that error count is not incremented. 2. ERR_DISP = 1. The uncorrectable block flag ERROR that error is counted as 27 erroneous bits (It has nine erroneous bytes with three corrupted bits per byte).
3.4.6 Convolutional deinterleaver
In DVB-S, the Convol utional deinte rleaver is 17 ×12. The peri odicity of 204 bytes per sync byte is retained. In DSS, the Co nvolutional d einterleaver i s 146 ×13, and there is al so a perio dicity of 147 bytes per sync byte. The deinterleaver may be bypassed.
3.4.7 Reed-Solomon decoder and descrambler
The input blocks are 204-byte long with 16 parity bytes in DVB-S. The sync byte is the first byte of the block. Up to 8 byte errors may be fixed. The code generator polynomial is: Over the Galois Field generated by: α 8 +α 4 +α 3 +α 2 + 1=0 Energy dispersal descrambler and output energy dispersal descrambler generator: χ 15 + χ 14 + 1 The polynomial is initialized every eight blocks with the sequence 100101010000000. The sync words are unscrambled and the scrambler is reset every 8 packets. Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 10 The output interfa ce may be forced i nto high imp edance mo de by setting MPEG_OEN =0 in the Address 39. Doing this affects the DATA [7:0], BYT E_CLOCK, SYNC, VALID and ERROR pins. The output stream is either parallel (byte stream) or serial (bit stream) depending on bit 1 of Address 39.
3.4.8 Spectrum Inverse of Code Rate 5/6
In case of Code Rate 5/6, because of its character, regardless of condition of spectrum it can be locked. Rest of the code rates except 5/6, if V iterbi is locked, byte becomes sync but in case of cod e rate 5/6, even if V iterbi is locke d there are cha nces byte does not beco me sync. Therefore, in ca se of Code Rate 5/6, it should be processed using S/W. Processing procedure is like below. 1. When the rest is locked except byte sync, code rate check 5/6. - Code rate monitoring : Addr [0x32], Bit position[0-2] 2. When Code Rate is 5/6, Check inverse spectrum status. - Spectrum inverse monitoring : Addr [0x32], Bit poisition[3] 3. Inverse inversion spectrum. - Spectrum inverse setting : Addr [0x31], Bit poisition[3], Set 1 Addr [0x31], Bit poisition[4], Set 1 or 0
3.4.9.1 Parallel output interface
A schematic diagram of the parallel output interface is shown in Figure 4. The parallel output format is compliant with the DVB-S common interface protocol. When the byte sync is not found (SYNC_FLAG = 0 in the SYNC02 register), VALID (corresponding to the MiVAL signal of the DVB-S common interface standard) remains at a low level. BYTE_CLOCK has a duty cycle between 40 and 60%. The VALID signal is generated depending on bit 2 of Address 39. Th e BYTE_CLOCK, SYNC, VAL ID and E RROR signal polarity is controlled depending on contents in the Register 38.
3.4.9.2 Serial output interface
The serial output interface is shown in Figure5. The serial bit stream is available on D7, where MSB is first to reconstruct the original order. If MPEG_DOUT = 1, then the parity bits a re output (Register 39). If MPEG_DOUT =0, the data is null during the parity time slots. SYNC is only high during the first bit of each packet, instead of during the first byte in Parallel mode. ERROR has the same function as in parallel mode. BYTE_CLOCK is t he serial bit clock; it is same the master clock, fclk. All of the o utputs are synchronous of the same master clock edge. D7, SYNC, VALID and ERROR may be properly sampled externally by the rising edge of BYTE_CLOCK. The first bit detecte d in a valid pa cket may be d ecoded if it is foun d on the ap propriate edg e of BYTE_CLOCK, where SYNC = 1, ERROR = 0, VALID = 1. The following bits only require the assertion of VALID (while VALID = 1,). Outputs D0 to D6 remain at low level in serial mode. Samsung Electronics Co, Ltd. Proprietary Information
- - 11 S5H1420 DBS Channel Decoder for DVB-S/DSS BYTE_CLOCK CDCLK_POL=1 SYNC VALID ERROR MPEG_ERR=1 No Error No Error ParityData Uncorrectible Packet Figure4 : Parallel output interface CDCLK_POL=0 MPEG_CLK=1 MPEG_CLK=0 MPEG_CLK=1 MPEG_CLK=0 MPEG_ERR=0 SYNC VALID MPEG_DOUT=1 ERROR DATA Parity ParityUseful Data First bit of the packet 1 packet 1/fclk Figure5 : Serial output interface BYTE_CLOCK CDCLK_POL=1 CDCLK_POL=0 MPEG_DOUT=0 MPEG_ERR=0 MPEG_ERR=1 Table 0 Bit1 of 0x39 Bit4 of 0x02 SER_PAR SER_SEL_MODE MPEG Data MPEG Clock Parallel 0 1 DATA [7:0] BYTE_CLK Serial 1 1 DATA[7] BYTE_CLK Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 12
3.4.9.3 MPEG Clock Control
- Through Register Setting, S5H1420 can control MPEG CLOCK to MCU. STB MCU 60MHz 81MHz Symbol Rate Symbol Rate >= 25 Symbol Rate < 25 Symbol Rate >= 25 Symbol Rate < 25 S5H1420 Master Clock 59MHz 88MHz 80MHz 88MHz Sampling 1 2 1 2 - Control register, 3-bit, uses Address 0x22 (MPEG_CLK_INTL [2:0]) - If Control registers changes, Some blocks will be reset automatically. - In case, Auto reset does not work, these blocks’ reset can be done manually. - MPEC IF Clock is made by Control Register and the Rules are as follows - Tmp = (fM CLK/fSR)*(1/(2*CR)), fMCLK : System Clo ck Frequency,fSR : Symbol Rate, CR : Code Rate MCLK=88 MHz MPEG Clock (MHz) Control Register (0x22) MPEG Clock(Parallel) MPEG Clock (Serial) Range Divide Serial Parallel
0 FMCLK/8 FMCLK 1<Tmp≤2 1 88 11
1 FMCLK/16 FMCLK/2 2<Tmp≤5 2 44 5.5 2 FMCLK/32 FMCLK/4 5<Tmp≤9 3 22 2.75 3 FMCLK/64 FMCLK/8 9<Tmp≤13 4 11 1.375 4 FMCLK/96 FMCLK/12 13<Tmp≤17 5 7.3333 0.9166625 5 FMCLK/128 FMCLK/16 17<Tmp≤25 6 5.5 0.6875 6 FMCLK/192 FMCLK/24 25<Tmp≤33 7 3.6666 0.458325 7 FMCLK/256 FMCLK/32 33<Tmp 8 2.75 0.34375 Example1) System Clock Frequency = 88MHZ, Symbol Rate : 44MSps Code Rate Tmp Value Setting Control Register Value 1/2 2 1 2/3 1.5 0 3/4 1.333 0 5/6 1.2 0 6/7 1.166 0 7/8 1.142 0 Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 13
3.5 Front end interfaces
3.5.1 I2C interface
The standard I2C protocol is used whereby the first byte is Hex A0 for a write operation, or Hex A1 for a read operation.
3.5.2 Write operation
The byte sequence is as follows: ■ the first byte gives the device Address plus the direction bit (R/W = 0). ■ the second byte contains the internal Address of the first register to be accessed. ■ the next byte is written in the internal register. Following bytes (if any) are written in successive internal registers. ■ the transfer lasts until stop conditions are encountered. ■ the S5H1420 acknowledges every byte transfer.
3.5.3 Read operation
The Add ress of the first regi ster to read is p rogrammed in a write op eration witho ut data, and terminated by the stop condition. Then, another start is followed by the device Address and R/W= 1. All following bytes are now data to be read at successive positions starting from the initial Address. Figure 2 shows the I2C Normal Mode Write and Read Registers. Figure 2: I2C Read and Write operations in Mode Write register 0 to 3 with AA, BB, CC, and DD 4UBSU "$, %FWJDF "EESFTT 8SJUF% 3FHJTUFS "EESFTT Read register 2 and 3 4UBSU %FWJDF"EESFTT 3FBE% "$, %BUB3FBE$$ "$, %BUB3FBE%% "$, 4UPQ 4UPQ4UBSU %FWJDF"EESFTT8SJUF% "$, 3FHJTUFS"EESFTT "$,
3.5.4 Identification register
The Identification Register (at Address Hex 00) gives the release number of the circuit. The content of this register at reset is presently (Hex02)
3.5.5 Sampling frequency
The S5H1420 converts the analog inputs into digital 6 bit I an d Q flow. T he sampling frequency is fclk which is derived from a n external reference de scribed in Se ction 3.5.6 ‘ Clock g eneration’. The maximum value of fclk is 90 MHz. The sampling causes the repetition of the input spectrum at ea ch integer multiple of fclk One has to ensure that no frequency component is folded in the useful signal bandwidth of fsym (1+ α)/2 where fsym is the symbol frequency, and α is the roll-off value.
3.5.6 Clock generation
An integrated PLL i s the circuit synchronizing an output signal (generated by a VCO with a reference signal in freq uency as wel l as in pha se. In this application, it incl udes the following basic blocks. The phase freq uency detecto r to detect the phase diffe rence betwe en the referen ce freq uency and the output frequency (after division) and to control the charge pumps voltage. Register setting can program the desired frequency. fout = (m×fin)/ (p×s) fin: input frequency, m=M+8, p=P+2, s=2^S M: Register 03, P: Register 04 [5:0], S: Register 04[7:6] Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 14
3.5.7 I2C bus repeater
In low symbo l rate applica tions, signal pollution ge nerated by the SDA/SCL lines of the I 2C bus may dramatically worsen tuner phase noise. In order to avoid this problem, the S5H1420 offers an I2C bus repeater so that the RFSDA and RFSCL a re active only when necessary. Both RFSDA and RFSCL pins are set high at reset. When the microprocessor writes a 1 int o register bit I2C_RPT, the next I2C message on SDA and SCL is re peated on the RFSDA and RFSCL pins resp ectively, until stop conditions are detected. To write to the tuner, the external microprocessor must, for each tuner message, perform the following: ■ Program 1 in I2C_RPT. ■ Send the message to the tuner. Any size of byte transfers is allowed, regardless of the Address, until the stop conditions are detected. Transfers are fully bi-directional. The I2C_RPT bit is automatically reset at the stop conditio n. The I2C repeater register in Address Hex 02 controls configuration.
3.5.9 DiSEqC interface
This interface allows for the simplif ication of real tim e processing of the dialog from micro processor to LNB. It includes regi ster set (8 bytes) that is filled by the micro processor via the I 2C bus, and the n transmitted by modulating to 22 kHz clock. The S5H1420 support DiSEqC2.0 for bi-directional interface between microprocessor to LNB and can change the tone frequency by register setting. < Transmission > The S5H1420 have three modes for DiSEqC Interface. ■ Continuous Mode: The S5H1420 generates continuous tone signal until the mode changes. ■ Tone Burst Mode: For the “Modulated Tone Burst”, only one byte (with value Hex FF) and parity bit 1 is sent. As a result, the output signal is 9 bursts of 0.5ms, separated by 8 intervals of 1ms. For the “Unmodulated Tone Burst” only one byte (with value Hex 00) is sent. The parity bit is still 1, and as a result, the signal is a continuous train of 12.5ms. ■ DiSEqC Mode: DiSEqC is a co mmand-based protocol used to control multi ple LNBs in a cascaded network configuration. The S5H1 420 complies with DiSEqC2.0. Fi gure illustrates a typical application of the DiSEqC mode. < Receive > The S5H1420 receives the data from L NBs using DiSEqC pin. In ord er to receive the data from LNB s should set the register RCV_EN to 1. The received data is stored to register set. Two control signals are available on the I2C bus: DiS_RDY (Transfer Ready/Finish) and DiS_LENGTH (Message Length). A typical byte transfer loop, as seen from the microprocessor, may be the following: While (there is data to transfer)
1 Read the DiS_RDY signals
2 If DiS_RDY =0, Write byte to transfer in the register set. 3 Set the DiS_LENGTH. 4 Set the DiS_RDY =1. Note, for the above transfer loop, the following: ■ At the beginning, the register set is empty (DiS_RDY =0). This is the idle state. ■ As soon as set the DiS_RDY =1, the transfer will begin. ■ After the last transmitted byte, the interface will go into the idle state. Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 15 Figure3: Schematic showing Bit Transmission Transmission of 1's Transmission of 0's B 48*5$)@$0/ b)SWITCH_CON=0 Idle 11 Periods 11 Periods 11 Periods Next bit Table1 LNB_CON SWITCH_CON Register set Output
00 X Empty Continuous tone
0 DATA=00 Unmodulated tone burst 01 1 DATA=FFor00 Module tone burst
Note: 1 Byte to transfer in DiSEqC mode.
2 I n M ode L NB_CON (1:0) =1 0, t he Di SEqC pin return t o hi gh 2 mode once t he t ransmission i s
completed. Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 16 4. REGISTER LIST ࠙Add Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ID 0x00 ID01 S5H1420_ID 0x01 CON_0 0 SOFT_RST 0 0 DSS_DVB SYSTEM 0x02 CON_1 0 0 SER_SEL 0 0 PWR_DN I2C_RPT 0x03 PLL01 M PLL 0x04 PLL02 S P 0X05 QPSK01 KICK_EN 0 1 DC_EN 1 1 MODE Q_START 0X06 QPSK02 1 1 0 1 DUMP_ACC DC_WIN 0x07 Pre01 INV_PULSE 0 1 PRE_TH 0x08 Post01 0 0 POST_TH 0x09 Loop01 WT_TNCO WT_PNCO 1 1 0 0 0 0 0x0A Loop02 LOOP_OUT KICK_VAL KICK_MUL 0x0B Loop03 IGA_PLF PGA_PLF 0x0C Loop04 IGT_PLF PGT_PLF 0x0D Loop05 IG_TLF PG_TLF 0x0E Pnco01 PNCO0[31:24] 0x0F Pnco02 PNCO1[23:16] 0X10 Pnco03 PNCO2[15:08] 0X11 Tnco01 TNCO0[31:24] 0X12 Tnco02 TNCO1[23:16] 0X13 Tnco03 TNCO2[15:08] 0x14 Monitor01 Reserved TLOCK PLOCK 0x15 Monitor02 PRE_LEVEL 0x16 Monitor03 POST_LEVEL 0x17 Monitor04 DC_I_LEVEL 0x18 Monitor05 DC_Q_LEVEL QPSK 0x19 Monitor06 Reserved 0x1A Monitor07 Reserved 0x1F Monitor12 QPSK_OUT DC_FREEZE 0x22 FEC01 0 0 0 0 MPEG_CLK_INTL 0x23 Soft01 Reserved 0x24 Soft02 Reserved 0x25 Soft03 Reserved 0x26 Soft04 Reserved 0x27 Soft05 Reserved 0x28 Soft06 Reserved 0x29 Vit01 Reserved 0X2A Vit02 Reserved 0X2B Vit03 Reserved 0X2C Vit04 Reserved 0X2D Vit05 Reserved 0X2E Vit06 Reserved 0X2F Vit07 Reserved 0X30 Vit08 0 0 VIT_SR78 VIT_SR67 VIT_SR56 VIT_SR34 VIT_SR23 VIT_SR12 0X31 Vit09 PARM_FIX INV_SPEC VIT_FR 0x32 Vit10 VIT_SPEC_STS VIT_CR 0x33 Vit11 0x34 Vit12 0x35 Sync01 SYNC_MISS_TH SYNC_HIT_TH 0x36 Sync02 BYTE_SYNC Reserved VIT_SYNC 0X37 Rs01 0X38 Mpeg01 ERR_POL SYNC_POL VALID_POL CDCLK_POL 0X39 Mpeg02 1 1 1 CLK_CONT 1 SER_PAR DSS_SYNC 0X3A DiS01 TONE_FREQ 0X3B DiS02 RCV_EN DIS_LENGTH DIS_RDY SWITCH_CON LNB_CON 0X3C DIS03 OLF_N LNB_DN V18_13V 0X3D DiS04 LNB_MESGE0 0X3E DiS05 LNB_MESGE1 0X3F DiS06 LNB_MESGE2 0X40 DiS07 LNB_MESGE3 0X41 DiS08 LNB_MESGE4 0X42 DiS09 LNB_MESGE5 0X43 DiS10 LNB_MESGE6 0X44 DiS11 LNB_MESGE7 0x45 Rf01 SLAVE_ADDR 0X46 Err01 ALARM _MODE ERR_CNT_PRD ERR_SRC 0x47 Err02 ERR_CNT_L 0x48 Err03 ERR_CNT_H FEC 0x49 Err04 PARITY_ERR Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 17 ID control register (Address: 0x00) Addr. RegName (Reset val) Signal name Width Property Description 0x00 ID01 (0x03) S5H1420_ID [7:0] R Revision ID System control registers (Address: 0x01-0x02) Addr. RegName (Reset val) Signal name Width Property Description [4] R/W Set to “0” System soft reset mode (active high) SOFT_RST [3] R/W [1] Enable [0] Disable [2] R/W Set to “0” [1] R/W Set to “0” DSS/DVB mode selection 0x01 CON_0 (0x00) DSS_ DVB [0] R/W [1] DSS [0] DVB [6] R/W Set to “0” [5] R/W Set to “0” SER_SEL [4] R/W Set to “1” [3] R/W Set to “0” [2] R/W Set to “0” Power down mode [1] Power down enable PWR_DN [1] R/W [0] Power down disable I2C repeater control [1] I2C repeater enable, [0] I2C repeater disable. Note: The master should be set this bit to “1” in order to interface with the tuner. 0x02 CON_1 (0x00) I2C_RPT [0] R/W When the master is not communicated with the tuner, this bit should be set to “0” PLL control registers (Address: 0x03-0x04) Addr. RegName Signal name Width Property Description PLL programming information 0x03 PLL01 (0x50) M [7:0] R/W Fout = ((M+8)Fin)/((P+2)×2 s P [5:0] R/W Fin = 4 MHz 0x04 PLL02 (0x40) S [7:6] R/W Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 18 QPSK control registers (Address: 0x05 – 0x06) Addr. RegName (Reset val) Signal name Width Property Description KICK_EN [7] R/W [1] PLL Kicker enable [0] Disable [6] R/W Set to “0” [5] R/W Set to “1” DC offset remove DC_EN [4] R/W [1] Enable [0] Disable [3] R/W Set to “1” [2] R/W Set to “1” QPSK operation mode [1] 1 sampling/1 symbol MODE [1] R/W [0] 2 sampling/1 symbol QPSK start signal 0x05 QPSK01 (0xBC) Q_START [0] R/W [1] Start [0] Idle [7] R/W Set to “1” [6] R/W Set to “1” [5] R/W Set to “0” [4] R/W Set to “0” Dump phase loop filter & timing loop filter accumulator DUMP_ACC [3] R/W [0 and then 1] The read operation enabled, when user set DUMP_ACC “0” and then “1”. 0x06 QPSK02 (0xC1) DC_WIN [2:0] R/W Window position from MSB removing DC offset. Unsigned integer (0 DC_WIN 7) AGC control registers (Address: 0x07 – 0x08) Addr. RegName (Reset val) Signal name Width Property Description PWM signal is reversed [1] PWM signal active low INV_PULSE [7] R/W [0] PWM signal active high [6] R/W Set to “0” [5] R/W Set to “1” 0x07 Pre01 (0x30) PRE_TH [4:0] R/W PRE-AGC threshold [7:6] R/W Set to “0” 0x08 Post01 (0x10) POST_TH [5:0] R/W POST-AGC threshold Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 19 Loop filter control registers (Address: 0x09 – 0x0D) Addr. RegName (Reset val) Signal name Width Property Description Write TNCO center frequency WT_TNCO [7] R/W [0 and then 1] The write operation enabled, when user set Write PNCO center frequency WT_PNCO [6] R/W [0 and then 1] The write operation enabled, when user set [5] R/W Set to “1” [4] R/W Set to “1” [3] R/W Set to “0” [2] R/W Set to “0” [1] R/W Set to “0” 0x09 Loop01 (0x30) [0] R/W Set to “0” Loop filter monitoring selection [1] Loop filter accumulator + NCO LOOP_OUT [7] R/W [0] Loop filter accumulator KICK_VAL [6:4] R/W The value that gets injected into the accumulator when a “kick” is needed. 0x0A Loop02 (0x65) KICK_MUL [3:0] R/W The number of bits KICK_VAL is up-shifted (2 N ) before it is injected into the accumulator. PGA_PLF [3:0] R/W Phase loop, proportional gain (2 PGA_PLF ) in the acquisition mode (default +8 added) 0x0B Loop03 (0x78) IGA_PLF [7:4] R/W Phase loop, integral gain (2 IGA_PLF ) in the acquisition mode PGT_PLF [3:0] R/W Phase loop, proportional gain in the tracking mode (default +8 added) 0x0C Loop04 (0x28) IGT_PLF [7:4] R/W Integral gain in the tracking mode PG_TLF [3:0] R/W Timing loop, proportional gain (default +8 added) 0x0D Loop05 (0x17) IG_TLF [7:4] R/W Timing loop, integral gain NCO control registers (Address: 0x0E – 0x13) Addr. RegName (Reset val) Signal name Width Property Description LOOP_OUT [1] 0x0E Pnco01 Read PLF accumulator + PNCO LOOP_OUT [0] 0x0F Pnco02 Read PLF accumulator 0x10 Pnco03 LOOP_OUT [1] 0x11 Tnco01 Read TLF accumulator + TNCO LOOP_OUT [0] 0x12 Tnco02 Read TLF accumulator 0x13 Tnco03 Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 20 QPSK monitoring registers (Address: 0x14 – 0x1F) Addr. RegName (Reset val) Signal name Width Property Description [7:4] R Reserved [3:2] R Reserved Timing loop lock (Symbol sync) [1] Timing loop has locked TLOCK [1] R [0] Timing loop has not locked Phase loop lock (Carrier sync) [1] Phase loop has locked 0x14 Monitor01 (0x00) PLOCK [0] R [0] Phase loop has not locked 0x15 Monitor02 (0x00) PRE_LEVEL [7:0] R PRE-AGC gain level 0x16 Monitor03 (0x00) POST_LEVEL [7:0] R POST-AGC gain level 0x17 Monitor04 (0x00) DC_I_LEVEL [7:0] R DC offset of I samples 0x18 Monitor05 (0x00) DC_Q_LEVEL [7:0] R DC offset of Q samples 0x19 Monitor06 (0x00) [7:0] R Reserved 0x1A Monitor07 (0x00) [7:0] R Reserved (0x1B ~ 0x1E ) Reserved [7] Reserved QPSK_OUT [6:1] R QPSK output monitoring 0x1F Monitor12 (0x00) DC_FREEZE [0] R/W [1] Do not update DC_OFFSET (0x20 ~ 0x21) Reserved Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 21 FEC control registers (Address: 0x22) Addr. RegName (Reset val) Signal name Width Property Description [6] R/W Set to “0” [5] R/W Set to “0” [4] R/W Set to “0” [3] R/W Set to “0” Tmp=(FMClk/FSR)(1/(2CR)) FMClk: System Clock Frequency FSR: Symbol Rate, CR: Code Rate 0: 1<Tmp2 4: 13<Tmp17 1: 2<Tmp5 5: 17<Tmp25 2: 5<Tmp9 6: 25<Tmp33 0x22 FEC01 (0x01) MPEG_CLK_INTL [2:0] R/W 3: 9<Tmp13 7: 33<Tmp Viterbi control registers (Address: 0x30 – 0x31) Addr. RegName (Reset val) Signal name Width Property Description [7] R/W Set to “0” [6] R/W Set to “0” [1] Include code rate 7/8 in sync search VIT_SR78 [5] R/W [0] Disable [1] Include code rate 6/7 in sync search VIT_SR67 [4] R/W [0] Disable [1] Include code rate 5/6 in sync search VIT_SR56 [3] R/W [0] Disable [1] Include code rate 3/4 in sync search VIT_SR34 [2] R/W [0] Disable [1] Include code rate 2/3 in sync search VIT_SR23 [1] R/W [0] Disable [1] Include code rate 1/2 in sync search 0x30 Vit08 (0xFF) VIT_SR12 [0] R/W [0] Disable Parameter fix mode [1] Known parameter PARM_FIX [4] R/W [0] Unknown parameter Initial spectrum information VIT_INV_SPEC [3] R/W [1] Inv spectrum [0] Not inv spectrum Start synchronization search at code rate as follows: 0x31 VIT9 (0x00) VIT_FR [2:0] R/W Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 22 Viterbi status registers (Address: 0x32) Addr. RegName (Reset val) Signal name Width Property Description Spectrum information monitoring [1] Inv spectrum VIT_SPEC_STS [3] R [0] Not inv spectrum Viterbi decoder current code rate [0] R=1/2 [1] R=2/3 [2] R=3/4 [3] R=5/6 [4] R=6/7 0x32 VIT10 (0x00) VIT_CR [2:0] R [5] R=7/8 SYNC control register (Address: 0x35) Addr. RegName (Reset val) Signal name Width Property Description SYNC_MISS_TH [7:4] R/W Sync byte detector’s miss threshold Sync byte detector’s hit threshold 0x35 Sync01 (0x33) SYNC_HIT_TH [3:0] R/W *Note: This value should be greater than 2 SYNC status register (Address: 0x36) Addr. RegName (Reset val) Signal name Width Property Description [1] Acquire byte sync BYTE_SYNC [5] R [0] Not acquire byte sync [4:1] R Reserved [1] Viterbi decoder is in sync 0x36 Sync02 (0x00) VIT_SYNC [0] R [0] Viterbi decoder is out of sync Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 23 MPEG control registers (Address: 0x38~0x39) Addr. RegName (Reset val) Signal name Width Property Description Packet error polarity ERR_POL [3] R/W [1] Active low [0] Active high Sync polarity SYNC_POL [2] R/W [1] Active low [0] Active high Data valid polarity VALID_POL [1] R/W [1] Active low [0] Active high CDCLK polarity [1] Falling edge event 0x38 Mpeg01 (0x00) CDCLK_POL [0] R/W [0] Rising edge event [6] R/W Set to “1” [5] R/W Set to “1” [4] R/W Set to “1” Clock continuous mode CLK_CONT [3] R/W [1] Continuous clock, [0] Cloc k is enable duri ng p ayload dat a transfer [2] R/W Set to “1” Serial / Parallel mode SER_PAR [1] R/W [1] Serial mode, [0] Parallel mode DSS sync mode 0x39 Mpeg02 (0x3D) DSS_SYNC [0] R/W [1] Output sync, [0] No output sync DiSEqC control registers (Address: 0x3A~ 0x3C) Addr. RegName (Reset val) Signal name Width Property Description Tone frequency ratio 0x3A DiS01 (0x01) TONE_FREQ [7:0] R/W *Note: ftone = fclk / (TONE_FREQ ×32) DiSEqC receive enable mode RCV_EN [7] R/W [1] Receive enable [0] Receive disable DIS_LENGTH [6:4] R/W Message length Data Transfer ready / finish [1] Ready [0] Finish DIS_RDY [3] R/W *Note: The Microprocessor set to “1” only when this bit is “0”. When this bit is “1”, the slaver is not yet received message. The slaver is starting to receive the signal at the rising edge detection Satellite switch in tone burst mode SWICH_CON [2] R/W [1] Satellite B [0] Satellite A LNB control mode [0] Continuous mode [1] Tone burst mode [2] DiSEqC mode 0x3B DiS02 (0x00) LNB_CON [1:0] R/W [3] Reserved Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 24 Addr. RegName (Reset val) Signal name Width Property Description OLF_N [2] R/W [1] Disable [0] OLF (active low) LNB_DN [1] R/W [1] LNB down [0] Disable (active high) 13V/18V select register 0x3C DiS03 (0x04) 18V_13V [0] R/W [1] 18V [0] 13V DiSEqC message registers (Address: 0x3D~0x44) Addr. RegName (Reset val) Signal name Width Property Description LNB message contents 0x3D DiS04 (0x00) LNB_MESGE0 [7:0] R/W *MSB sent first on each byte 0x3E DiS05 (0x3E) LNB_MESGE1 [7:0] R/W 0x3F DiS06 (0x00) LNB_MESGE2 [7:0] R/W 0x40 DiS07 (0x00) LNB_MESGE3 [7:0] R/W 0x41 DiS08 (0x00) LNB_MESGE4 [7:0] R/W 0x42 DiS09 (0x00) LNB_MESGE5 [7:0] R/W 0x43 DiS10 (0x00) LNB_MESGE6 [7:0] R/W 0x44 DiS11 (0x00) LNB_MESGE7 [7:0] R/W RF slave register (Address: 0x45) Addr. RegName (Reset val) Signal name Width Property Description 0x45 Rf01 (0x61) SLAVE_ADDR [6:0] R/W RF tuner slave Address (SOC VERSION) Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 25 Error control register (Address: 0x46) Addr. RegName (Reset val) Signal name Width Property Description [4] R/W Set to “1” [3:2] R/W Set to “1” Error monitoring source [0] QPSK bit errors [1] Viterbi bit errors [2] Viterbi byte errors 0x46 Err01 (0x00) ERR_SRC [1:0] R/W [3] Packet errors Error monitoring registers (Address: 0x47-0x49) Addr. RegName (Reset val) Signal name Width Property Description 0x47 Err02 (0x00) ERR_CNT_L [7:0] R Error counter value register (LSB 8 bits) 0x48 Err03 (0x00) ERR_CNT_H [7:0] R Error counter value register (MSB 8 bits) 0x49 Err04 (0x00) PARITY_ERR [7:0] R Error flag for DiSEqC receive data Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 26 5. ELECTERICAL CHARACTERISTICS
5.1 Absolute maximum ratings
Symbol Parameter Range Unit VCC DC Supply Voltage -0.3 to 4.6 V VIN 3.3V Input Voltage -0.3 to VDD+0.3 V IIN DC 3.3V Input Current +/- 10 mA Tstg Storage Temperature -40 to +125 ºC Topr Operation Temperature 0 to +70 ºC
5.2 Recommended operating conditions
Symbol Parameter Range Unit VCC DC Supply Voltage 3.0 to 3.6 V TJ Junction Temperature MAX 125 ºC TR Thermal Resistance 45 ºC /W VIN DC Input 0 to VCC V VOUT Output Voltage 0 to VCC TLT Lead Temperature (soldering 10 sec) 300 ºC
5.3 DC electrical characteristics
(VDD = 3.3+/-10%, Ta = -40(C~ -85(C, unless otherwise specified) Symbol Description Test Condition Min Typ Max Unit VCC33 I/O Supply Voltage 3.0 3.3 3.6 V VCC25 Internal Supply Voltage 2.2 2.5 2.7 V All In out 0.7 VDD Vih Input Voltage Low Rst_n, S_clk - - 2.1 V All Input 0.3VD D - - V Vil Input Voltage High Rst_n, S_clk 0.8 - - Iih High Level Input Current VIN = VDD - 10 - + 10 uA Iil Low Level Input Current VIN = VSS -10 - +10 uA Vol Output Low Voltage IOL = 8mA - - 0.4 V Voh Output High Voltage IOH = -6mA 2.4 - VDD V Ioz 3-State Outp ut Leakage Current VOH = VSS or VDD -10 - +10 uA Icc Dynamic Supply Current Fin = 4.0MHz, VDD = 3.6V - - TBD mA
5.4 A/D converter
(Vcc25 = 2.5+/-5%, Ta = -40(C~ -85(C, unless otherwise specified) Symbol Description Test Condition Min Typ Max Unit VREF-H Reference Voltage High Input VREF-H Value 1.5 1.6 1.7 V VREF-L Reference Voltage Low Input VREF-L Value 0.8 0.9 1.0 V Ain Analog Input (IP/IN/QP/QN) (VREF-H)-(VREF-L) 0.5 0.7 0.9 VPP CML Common Mode Level CML Output - 1.25 - 7 IDD 45M Average VDD_2.5V Current VDD=2.6V = 59MHz - - mA IDD 45M Average VDD_2.5V Current VDD=2.6V = 88MHz - - mA INE Integral Linearity Error FIN=30MHz, FS=90MHz - - 1.0 dB DLE Differential Linearity Error FIN=30MHz, FS=90MHz - - 2.0 dB OFF Offset Error Voltage FIN=30MHz, FS=90MHz - 1.0 - dB GAIN Gain Error Voltage FIN=30MHz, FS=90MHz - 2.0 - dB SNDR Signal to Noise & Distortion Ratio FIN=30MHz, FS=90MHz -32 -30 -28 dB FIN Analog Input Bandwidth - - 30 MHz FS Sampling Frequency - - 90 MHz Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 27
5.5 Timing characteristics
CLK_OUT D[7:0], D/P STR_OUT, ERROR tCKSU tCKH Figure 6 Figure 8 tCKSU tCKH CLK_OUT D[7:0], D/P STR_OUT, ERROR Figure 7 tCKSU tCKH CLK_OUT D[7:0], D/P STR_OUT, ERROR CLK_OUT D[7:0], D/P STR_OUT, ERROR tCKSU tCKH Figure 9 Symbol P arameter Min Typ Max Unit fVC O I nternal VCO freque nc y 300 400 MHz fCL K_IN CLK_IN OR XTAL frequenc y 4 30 MHz PA R ALLEL OU TP UT D [7:0], D/ P, CL K_O UT, STR_ OU T, E RRO R OU T PUT CH ARAC TERITICS Bit RS= 1 in RS CONTRO L RE GISTER(Address33). Refer to Figure 6 tCL K_duty C LK_OUT duty cycle 40 50 60 % tCKS U D[7:0], D/P, STR_ OUT, ERRO R stable before CLK_OUT Falling E dge 2*Tm(1) ns tCK H D[7:0], D/P, STR_OUT, ERROR stabl e after CLK_OUT Falling Edge 2*Tm(1) ns Bit RS= 0 in RS CONTRO L RE GISTER(Address33). Refer to Figure 7 tCKS U D[7:0], D/P, STR_ OUT, ERRO R stable before CLK_OUT Falling E dge 2*Tm(1) ns tCK H D[7:0], D/P, STR_OUT, ERROR stabl e after CLK_OUT Falling Edge 2*Tm(1) ns SERIAL O U TP U T D[ 7 : 0 ] , D/ P , CL K _ O U T, S T R_ O U T , E R R O R O U T P U T C H A R A C TE RI T I CS Bit RS= 1 in RS CO NTRO L RE GISTER(Address33). fCLK = 90MHz. Refer to Figure 8 tCKS U D[7:0], D/P, STR_ OUT, ERRO R stable before CLK_OUT Falling E dge 3.5 ns tCK H D[7:0], D/P, STR_OUT, ERROR stabl e after CLK_OUT Falling Edge 2 ns Bit RS= 0 in RS CO NTRO L RE GISTER(Address33). fCL K = 90M Hz. Refer to Figure 9 tCKS U D[7:0], D/P, STR_ OUT, ERRO R stable before CLK_OUT Falling E dge 3.5 ns tCK H D[7:0], D/P, STR_OUT, ERROR stabl e after CLK_OUT Falling Edge 2 ns Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 28
5.6 I2C bus characteristics
Symbol Parameter Test Condition s Min Typ Max Unit VIL VIH Low Level input Voltage High Level input Voltage Pull up to 5V 10% - 0.5 2.0 0.8 5.5 V V VOH VOL High Level output Voltage Low Level output Voltage Pull up to 5V 10% 5.5 0.4 V V ILK Input Leakage Current VIN = 0V to 5V -10 10 uA CIN Input Capacitance 0 3.5 pF IOL Output Sink Current VOL = 0.5V 10 mA fSCLN fSCLS SCL Clock Frequency Normal Mode Standby Mode fM_CLK /40 fM_CLK /10 tBUF Bus Free Time between a STOP and START Condition 1.3 us tHD,STA Hold Time(repeated)START Condition. After this period, the first clock pulse is generated 0.6 us tLOW tHIGH Low Period of the SCL Clock High Period of the SCL Clock 1.3 0.6 us us tSU,STA Setup Time for a repeated START Condition 0.6 us tSU,STO Setup Time for STOP Condition 0.6 us tSU,DAT Data Setup Time 100 ns tR, tF Rise and Fall Time of both SDA and SCL signals 300 ns CB Capacitive Load for each Bus Line 400 pF I2C bus timing diagram U#6' U-08 U3 U' U)% 45" U46 %"5 U46 45" U46 450 4%" 4$- U)*() U)%45" U41 U)% %"5 Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 29 6. APPLICATION EXAMPLES # Application example (with DVB-S I/Q Tuner) VSS25D LNB_EN VDD25D VSEL AGC ERROR SYNC VALID AVBB_PLL AVSS_PLL AVDD_PLL OLF VSS33 SCL SDA AVSS_PLL VDD25 VDD25 VSS25 DATA0 DATA1 VSS25 VSS33 IN AVDD_ADC RFSCL FMHZCLKOUT VDD33 DATA7 DiSEqC TEST_SEL1 RFSDA VDD25 NC DATA2 DATA3 DATA4 DATA5 DATA6 NC AVBB_ADC AVSS_ADC IP AVDD_ADC QN AVSS_ADC QP CML VREF_L VREF_H ID_SEL0 ID_SEL1 VSS25 VDD25 XTAL_OUT XTAL_IN TEST_SEL0 VSS25 VDD33 CLK_SEL 12345678910111213141516 48474645444342414039383736353433 BYTE_CLK RESET_N ADC_OSC_IN S5H1420 (64LQFP-1010) $.- 73&'@) 73&'@- .)[ 73&'@) 73&'@- ʃ ʃ ʃ Lʃ Lʃ 7@% 7@" LNBP SMPS 7@% 7%% 7%%@% 7%%@" 744@% 744@" MPEG2 Serial Interface MPEG2 Parallel Interface Lʃ3 Lʃ O' $ Lʃ Lʃ $.- AVDD_PLL $.- $.- 3.ʃ ʃ ʃ ʃ ʃ 4BUFMMJUFEJTI ,)[ "($ 3'4%" 3'4$- DATA 7 Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 30 7. Package Dimension #64 NOTE: Dimensions are in millimeters. 10.00 12.00 + 0.20 10.00 12.00 + 0.20 0.50 0.127 + 0.073 - 0.037 0.45 - 0.75
0.05 MIN
1.40 + 0.05
1.60 MAX
0.20 + 0.07 - 0.03
0.08 MAX M
0.08 MAX
0.25TYP Samsung Electronics Co, Ltd. Proprietary Information
DBS Channel Decoder for DVB-S/DSS - - 31 8. Data sheet update history - 2004-01-05 : Release version : 4.5 Add chapter : 3.4.8 Spectrum Inverse of Code Rate 5/6 (Page 10). Add chapter : 3.4.9.3 MPEG Clock Control (Page 12). Change register map : )JEFVOOFDFTTBSZSFHJTUFS'JFMEUPVTFS(Page 16). - 2004-01-10 : Release version : 4.5.1 Update chapter : 3.2.2 Loop equation (Page 7). Update chapter : 3.3.1 Loop equation (Page 7). Update chapter : 3.4.9.2 Serial output interface (Page 10). Update chapter : 3.4.9.3 MPEG Clock Control (Page 12). Samsung Electronics Co, Ltd. www.samsung.com T : 82-31-279-7640 Suwon P.O.BOX 416 Maetan-3dong, YoungTong-gu, Suwon-si, Gyeonggi-do, Korea 442-742 Samsung Electronics Co, Ltd. Proprietary Information