S5D0127X01

S5D0127X01 SAMSUNG | Alldatasheet

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MULTIMEDIA VIDEOS5D0127X01 Data Sheet PAGE 1 OF 96Modified on May/04/2000 MULTISTANDARD VIDEO DECODER/SCALER The S5D0127X01 converts analog NTSC, PAL or SECAM video in composite, S-video, or component format to digitized component video. Output data can be selected for CCIR 601 or square pixel sample rates in either YCbCr or RGB formats. The digital video can be scaled down in both the horizontal and vertical directions. The S5D0127X01 also decodes Intercast, Teletext, Closed Caption, and WSS data with a built-in bit data slicer. Digitized CVBS data can be output directly during VBI for external processing.

FEATURES

• Accepts NTSC-M/N/4.43, PAL-M/N/B/G/H/I/D/K/L and SECAM formats with auto detection
• 6 analog inputs: 3 S-video, 6 composite, or 1 3-wire YCbCr component video
• 2-line luma and chroma comb filters including adaptive luma comb for NTSC
• Programmable luma bandwidth, contrast, brightness, and edge enhancement
• Programmable chroma bandwidth, hue, and saturation
• High quality horizontal and vertical down scaler
• Intercast, Teletext and Closed Caption decoding with built-in bit slicer
• Direct output of digitized CVBS during VBI for Intercast application
• Analog square pixel or CCIR 601 sample rates
• Output in 4:4:4, 4:2:2, or 4:1:1 YCbCr component, or 24-bit or 16-bit RGB formats with dithering
• YCbCr 4:2:2 output can be 8 or 16 bits wide with embedded timing reference code support for 8-bit mode
• Simultaneous scaled and non-scaled digital output ports outputs for 8-bit mode.
• Direct access to scaler via bi-directional digital port.
• Programmable Gamma correction table
• Programmable timing signals
• Industry standard IIC interface

APPLICATIONS

• Multimedia

100 PQFP

ORDERING INFORMATION

Device Package Temperature Range S5D0127X01- Q0R0 100 PQFP -20°~+70°C

• Digital Video
• Video Capture/Editing

RELATED PRODUCTS

• S5D0123X01 MULTISTANDARD VIDEO ENCODER

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 2 OF 96Modified on May/04/2000 BLOCK DIAGRAM IIC Host Interface Reference Generator/ Compensation 6 input MUX 2-AGCs 2-ADCs Gain/Offset Control Luma Processing Chroma Processing VBI Data Decoding SRAM Variable LPF Comb Filter Horizontal Color Space Converter Gamma LUT Digital Input Timing Line Lock, Timing Generation HS1 HS2 VS HAV VAV CK CK2 SCH PID EHAV EVAV OEN Y[7:0] CCEN CCDAT SCLK SDAT AEX1,0 AY[2:0] AC[2:0] COMP2 VRT VRB HS1 VS XTALI XTALO Scaler C[7:0] EXV[7:0] Data Format Vertical Scaler Output EXV Control Direct. Sliced VBI or Raw CVBS Scaler Input OR Simultaneous Non Scaler Output OR 24-bit Output Non Scaler Output

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 3 OF 96Modified on May/04/2000 PIN ASSIGNMENT - 100 PQFP 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 EHAV VSS XTALO XTALI VDDA1 RST VDD3 VSS VSS OEN EXV0 PID CK VSS VDD CK2 ODD VS SCH(PORTB) HAV VSS VSS VDD3 VDD3 S5D0127X01 VDDA COMP2 TEST VSS AC2 VDDA AC1 VSS AC0 VDDA AY2 VSS AY1 VDDA AY0 VSS VRT HS2(IIC) SCLK CCEN CCDAT SDAT EXV7 AEX1 AEX0 EXV6 VDD3 VDD3 VSS VSS EXV5 TESTEN PORTA VDD VSS EXV3 EXV4 100 NCP NCP VAV(OENC0) EVAV(OENC1) VDD3 HS1 NCP NCP NCP NCP NCP NCP NCP NCP NCP NCP VRB NCP NCP EXV1 EXV2 NCP NCP

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 4 OF 96Modified on May/04/2000 PIN DESCRIPTION Pin Name Pin # Type Description INPUT AY0 84 I 1 of 6 analog CVBS or 1of 3 S-video Y inputs. AY1 86 I 1 of 6 analog CVBS or 1of 3 S-video Y inputs. AY2 88 I 1 of 6 analog CVBS input or 1 of 3 S-video Y inputs or Y input for 3 wire component input AC0 90 I 1 of 6 analog CVBS or 1 of 3 S-video C inputs. AC1 92 I 1 of 6 analog CVBS or 1 of 3 S-video C inputs or Cb input for 3 wire component input AC2 94 I 1 of 6 analog CVBS or 1 of 3 S-video C inputs or Cr input for 3 wire component input XTALI 8 I Pin 1 for an external crystal or TTL clock input. XTALO 7 O Pin 2 for an external crystal. RST 10 I Chip reset. Active low signal. OUTPUT (All output pins can be selectively three-stated) Y0 - Y7, C0 - C7 45-48,53-56,33- 39,44 O Digital video outputs. EXV0 - EXV7 16,27,28,61-63, 68,71 I/O Expanded digital video I/O port. Can be configured as an additional 8-bit output port (no scaling), or additional outputs of the main digital output stream for 24 bit output modes, as an 8-bit input for direct digital access of the down scaler. HS1 26 I/O Programmable horizontal timing signal. One pulse every video line. When the EXV port is configured as an input, this pin can be programmed as an input. HS2(IIC ) 76 I/O Programmable horizontal timing signal. One pulse every video line. At power up, this pin needs a 10 kΩ pull-down resistor to configure the chip to operate in IIC mode. VS 23 I/O Programmable vertical timing signal. When the EXV port is configured as an input, this pin can be programmed as an input. HAV 25 O Programmable horizontal active video flag. VAV(OENC0) 3 I/O Programmable vertical active video flag. During reset, the pin is an input and the logic state of this pin is latched into the OENC[0] register bit. Use a 10 kΩ resistor for pull-up or pull-down. EHAV 5 O Valid pixel data flag. Polarity is programmable. Active when output video data is valid.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 5 OF 96Modified on May/04/2000 EVAV(OENC1) 4 I/O Valid line flag. Polarity is programmable. Active when output video line is valid. During reset, the pin is an input and the logic state of this pin is latched into the OENC[1]register bit. Use a 10 kΩ resistor for pull-up or pull-down. ODD 22 O Odd field flag. Polarity is programmable. Active for fields 1 and 3. PID 17 O PAL ID flag. High for phase alternating line. OEN 15 I Digital video data, timing and clock output 3-state control. CK 18 I/O Pixel clock. In normal decoding mode, this is an output. When the EXV port is used as an input, this can be programmed as an input pixel clock. CK2 21 O Pixel output clock (rate is one half of CK) aligned to HAV signal. CCDAT 73 O Sliced VBI data output. Data can be from Closed Caption, Teletext, Intercast, or WSS type encoded data. CCEN 74 O When high, this pin indicates that valid VBI data is being clocked out at the CCDAT pin or at the digital video output. MULTI-PURPOSE I/O PORTS AND TEST ENABLE PORTA 58 I/O Multi-purpose I/O port. SCH(PORTB) 24 I/O Multi-purpose I/O port. TESTEN 57 I When tied to VDD, the chip is put into the test mode. For normal use, this pin should be connected to VSS. TEST 96 I When tied to VDD, the chip is put into the test mode. For normal use, this pin should be connected to VSS. REFERENCE AND COMPENSATION VRT 77 I/O ADC VRT compensation (requires an external 0.1 µF capacitor connected to VSS). VRB 78 I/O ADC VRB compensation (requires an external 0.1 µF capacitor connected to VSS). COMP2 97 I/O Internal 1.3 V reference (requires an external 0.1 µF capacitor connected to VSS). HOST INTERFACE SCLK 75 I Serial clock for IIC host interface. SDAT 72 I/O Serial data for IIC host interface. AEX0 - AEX1 69 - 70 I Device ID selection for IIC host interface. PIN DESCRIPTION (Continued) Pin Name Pin # Type Description

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 6 OF 96Modified on May/04/2000 POWER AND GROUND VDD 20,59 PWR Digital power supply for output buffers. The voltage can be +5V or 3.3V depending on interface requirement. VDD3 11,12,42,43,66, +3.3V Digital power supply for internal logic. VDDA 85,89,93,98 +5V Analog power supply for ADC, AGC and reference circuits. VDDA1 9 +5V Analog power supply for clock generation circuitry. VSS 6,13,14,19,40, 41,60,64,65,83, 87,91,95 GND Common ground. NC 79-82,99,100 - These pins are directly connected to the die substrate. If electrical connect is desired (not required) only connection to VSS is allowed. PIN DESCRIPTION (Continued) Pin Name Pin # Type Description

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 7 OF 96Modified on May/04/2000 PIN CROSS REFERENCE: NUMERICAL ORDER BY PIN NUMBER Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name

1 NCP 26 HS1 51 NCP 76 HS2(IIC)

2 NCP 27 EXV1 52 NCP 77 VRT

3 VAV(OENC0) 28 EXV2 53 Y4 78 VRB

4 EVAV(OENC1) 29 NCP 54 Y5 79 NCP

5 EHAV 30 NCP 55 Y6 80 NCP

6 VSS 31 NCP 56 Y7 81 NCP

7 XTALO 32 NCP 57 TESTEN 82 NCP

8 XTALI 33 C0 58 PORTA 83 VSS

9 VDDA1 34 C1 59 VDD 84 AY0

10 RST 35 C2 60 VSS 85 VDDA

11 VDD3 36 C3 61 EXV3 86 AY1

12 VDD3 37 C4 62 EXV4 87 VSS

13 VSS 38 C5 63 EXV5 88 AY2

14 VSS 39 C6 64 VSS 89 VDDA

15 OEN 40 VSS 65 VSS 90 AC0

16 EXV0 41 VSS 66 VDD3 91 VSS

17 PID 42 VDD3 67 VDD3 92 AC1

18 CK 43 VDD3 68 EXV6 93 VDDA

19 VSS 44 C7 69 AEX0 94 AC2

20 VDD 45 Y0 70 AEX1 95 VSS

21 CK2 46 Y1 71 EXV7 96 TEST

22 ODD 47 Y2 72 SDAT 97 COMP2

23 VS 48 Y3 73 CCDAT 98 VDDA

24 SCH(PORTB) 49 NCP 74 CCEN 99 NCP

25 HAV 50 NCP 75 SCLK 100 NCP

support direct 8-bit YCbCr input for high quality video scaling and other processing. Figure 1. Analog Front End frequency signal reduction. This can be implemented with a 400 pF capacitor in parallel with the 75 Ω load. Figure 2. Typical Analog Video Input

8 Bit ADC

as 2X faster during acquisition via the AGC_LKG. Figure 3. Selection of analog video input or digital CCIR 656 data is with the INPSL[1:0] register bits. The S5D0127X01 can operate in master or slave timing mode when the chip is programmed for digital video input.

0 AY0 Composite

1 AY1 Composite

2 AY2 Composite

4 AC0 Composite

5 AC1 Composite

6 AC2 Composite

8 AY0, AC0 S-Video

9 AY1, AC1 S-Video

CMDD register. Timing selection is through either SYNDIR or EAV bit. Figure 3. 8-bit YCbCr Input Data Path *1: CKDIR = 0 - CK is output and is internally generated. CKDIR = 1 - CK is input from an external source. *2: SYNDIR = 0 - HS1 and VS are output. SYNDIR = 1 - HS1 and VS are inputs from external sources. *3: EAV = 0 - chip will not sync to embedded timing. EAV = 1 - chip will sync to embedded timing. Note: the combination X11 for CKDIR, SYNDIR, EAV is not valid.

When in digital input mode, all programmable timing registers (such as HAVB,HAVE, HS2B etc.) are still functional. effect. An example of horizontal timing for digital input is shown in Figure 4. Figure 4. Horizontal Timing for EXV Port as Digital Input connected to the internal CBG signal (DATAA[2:0] = 3). internal chroma clamp be disabled (COFFENB = 1) due to slight Cb/Cr leakage.

• Fundamental or third overtone
• Load capacitance of ~20 pF
• Series resistance of 40 Ω or less
• Frequency deviation of 50 ppm or less over operating temperature range

Figure 5. Standard Clock Configurations constants for the various combinations of input formats and output pixel rates.

24.576 MHz

24.576 MHz22 pF

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 13 OF 96Modified on May/04/2000 The time constants for the pixel clock tracking loop can be adjusted with the HFSEL[1:0] bits. In addition to providing the pixel clock, the S5D0127X01 also outputs various timing signals to indicate the beginning of a line, a field, and for field and frame identification. All the timing and clock pins may be optionally put into high impedance state. Three-state of these pins are software controlled and initial state of these pins at power up is controlled via two configuration pins: 3 and 4. The S5D0127X01 can generate all the video timing without video input. This enables the S5D0127X01 to be used as a video timing generator for a system that contains both the S5D0127X01 for live video input and a MPEG decoder which requires a video timing generator. 1.2.3. Horizontal Timing The S5D0127X01 creates many internal timing signals aligned to the horizontal sync tip (mid-way of the falling edge of horizontal sync, typically ADC code 36). These include locations of color burst (CBG, CBGW) used in chrominance processing, back porch (BPG), and sync tip timing signals (SLICE, FS_PULSE) used for AGC and clamp functions. SLICE is low whenever the input is below half way level of horizontal sync (typically ADC code 36). FS_PULSE is a single clock pulse coincide with the start of SLICE. One of these internal signals can be made available at the PORTA or PORTB pin at any time. The chip outputs two horizontal synchronization signals: HS1 and HS2 . The start and stop locations for these signals are fully programmable. Offset programmed to HSxB, HSxE, and HSxBE0 are added to the default edge locations as shown in Table 4. Note that there are different modulo numbers for different input video standards and output pixel rates. Table 3: Timing for Different Pixel Rates CCIR 601 Data Rates Square Pixel Data Rates UnitsM N,B,G,H,I,D,K,K1,L M N,B,G,H,I,D,K,K1,L Field Rate 60 50 60 50 Hz Pixels/Line (N) 858 864 780 944 Pixels Active Pixels/Line 720 720 640 768 Pixels Active Lines/Frame 480 580 480 580 Lines Pixel Rate 13.5 13.5 12.27 14.75 MHz ADC Sampling Rate 27 27 24.54 29.5 MHz

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 14 OF 96Modified on May/04/2000 An additional signal, HAV, is provided for horizontal video cropping. This signal has programmable polarity, start and stop locations. Two 11-bit registers, HAVB and HAVE, are used to define the first and last pixel locations of the horizontal portion of the cropped video. Numbers programmed into these registers are used as offset to the default locations as shown in Table 4. Note that even though HAVB and HAVE have 1-CK resolution, the difference between them should be maintained at multiple of 4 CKs for correct output. Table 4 shows the default edge locations relative to the midway of the falling edge of the analog horizontal sync. Note the numbers shown are in multiple of CK clocks. Figure 6 shows the approximate locations for the horizontal timing signals. Horizontal timing signals used for scaling will be described in Section 1.6.1. Table 4: Horizontal Timing Signal Edge Locations (in # of CK) Description Signal

60 Hz 50 Hz

(modulo 1716) Square Pixel (modulo 1560) CCIR 601 (modulo 1728) Square Pixel (modulo 1888) Chip delay 120 120 120 120 Sync gate (1-CK pulse) SYG 72 72 72 72 Back porch gate BPG [147 222] [129 204] [154 234] [168 254] Color burst gate (1-CK pulse) CBG 222 204 234 254 Wide color burst gate CBGW [159 254] [147 233] [173 254] [186 277] Two pulses per line (1-CK each pulse) FH2 42, 900 42, 822 42, 906 42, 986 Default one pulse per line HS1 [65 238] [45 220] [69 250] [65 270] Default one pulse per line HS2 [65 238] [45 220] [69 250] [65 270] Default horizontal cropping HAV [351 75] [334 58] [379 91] [415 59]

Figure 6. Approximate Locations for the Horizontal Timing Signals The vertical timing signals include VS, VAV, ODD, SCH, and PID. and VAVE registers, respectively.

phase of the color burst relative to the sync tip must be measured. That information is provided by the SCH pin. that have a constant sync tip to color burst relationship. This is not the case with consumer VCRs. Figure 7. Short Term Vertical Timing

60 Hz - CCIR 601 = 885, Square = 708

50 Hz - CCIR 601 = 891, Square = 971 0, except 60 Hz Square = 2

Note: Numbers shown are in CK. Active high polarities are used. Timing shown for VAV and EVAV are with qualifier off.

60 Hz - 261

50 Hz - CCIR 601 = 273, Square = 341

Figure 12. Luminance Signal and BRT=0) are summarized in Table 5. 0-100% values from standard CCIR 601 levels to full range levels.The gain variations are shown in Table 6.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 20 OF 96Modified on May/04/2000 For CCIR 601 digital video input (INPSL[1:0] = 1), register UNIT must be set to 1 to produce unit gain. 1.3.2. Horizontal Luma Frequency Shaping The luma path contains many programmable filters for different purposes. The combination of these filters will give different frequency characteristics. The over sampled video data from the ADC pass through a decimation filter. The decimation filter has user programmable bandwidth. Three registers are used to control the decimation filter characteristics and each is designed for certain purposes. The HYBWI, when set to “1”, provides extra bandwidth for very high quality video source. The HYBWR, when set to “1”, reduces the bandwidth so high frequency noise can be eliminated. The 3-bit register HYLPF[2:0] provides the necessary bandwidth reduction for horizontal scaling. When all three registers are programmed to “0”, the decimation filter has the bandwidth of the normal video. The S5D0127X01 provides the option of bypassing the decimation filter. This option should be used only when the input video is band limited and with low high frequency noise. For composite video input, the notch filter can be enabled (CTRAP set to “1”) to extract the luminance. The notch filter has different center frequencies for different input video format. User selectable peaking function is included for edge enhancement. The notch filter should be bypassed for S-video and component video input, or if luma comb filter is enabled. The luminance filter characteristics have been designed to be very similar for all combinations of 60/50 Hz video and CCIR 601/square pixel sampling rates. Figure 13 and Figure 14 show the output characteristics of the luminance path with different filter combinations for the supported input standards and output pixel rates.

A simplified block diagram for the horizontal chroma processing unit is shown in Figure 17. Figure 17. Horizontal Chroma Processing Unit standard. Details of the various chroma processing blocks follow.

Figure 18. Chroma IF Compensation Frequency Response obtained. When external calibration is desired, the gain feed back loop can be “opened” by setting TSTCGN=1. The SAT then controls bits 8 through 1 of a 10 bit multiplier. control. This register is 2’s compliment. The demodulation circuit also contains a programmable low pass filter and a coring function for noise reduction.

Figure 21. De-emphasis Filter Frequency Response standard input automatically. delay for Cb and Cr alignment. This enables the two components to be sampled by one ADC. can be reset using the RTC_DTO bit. For PAL mode, the PID polarity can be controlled with the RTC_PID bit. diagram for the vertical processing section is shown in Figure 22.

Figure 22. Vertical Processing selected automatically based on the video input. Filter coefficients may also be set manually. programming the luma comb control register MNYCMB to “1”, and by choosing the value 3 or 4 for YCMBCO[2:0]. luma line delay matches the chroma path line delay. Special filtering is applied to ensure that high vertical bandwidth is retained for the luma path. automatically selected based on the input video standard or manually set using NMCCMB and CCMBCO[2:0].

and vertical direction to an arbitrary size. chroma. Scaled pixel data are stored in an on-chip FIFO so they can be sent out in a continuous stream. edge of HAV if the total number of scaled pixels is even, or is one pixel clock earlier if the number is odd. Figure 23. Horizontal Scaler Timing for CIF Output (CCIR 601 Pixel Rate) peaking control register HYPK[1:0]. The high quality filter ensures minimal artifacts for any scaling ratio.

valid within the vertically cropped region. ratio is less than 1/2, this bit should be set to “1” to eliminate any aliasing effect. Luma vertical scaler interpolation filter frequency response is shown in Figure 28. Figure 28. Luma Vertical Scaler Interpolation Filter Frequency Response possible to interface the S5D0127X01 to the memory controller without using EVAV. for the 3-tap and 5-tap filters are shown in Figure 29.

Figure 29. Chroma Vertical Scaler Interpolation Filter Frequency Response

• Closed Caption Line 21 Data Service (EIA-608)
• 525 line / 60Hz Teletext systems B,C,D (ITU-R BT.653-2)
• 625 line / 50Hz Teletext systems A,B,C,D (ITU-R BT.653-2)
• Copy Generation Management System (EIA/IS-702)
• Wide Screen Signalling (WSS ETS 300 294). Note that the SMPTE data slicing is removed for the S5D0127X01 and replaced with the WSS / CGMS processing. This data can be accessed from the part via four different methods:
• Enabling the “Raw un-processed 27MHz” Y ADC samples to be output for the appropriate lines in place of the normal YUV data.
• Slicing the data (creating a clock and comparing the data to a threshold at the clock) and bursting this data out on Y output.
• Reading the sliced data from two internal registers via the IIC bus.
• Via 2 external pins that output the sliced VBI data and the time at which the slice is valid. A simplified block diagram for the VBI section is shown in Figure 30.

Figure 30. VBI Decoder Block Diagram

8 Y[7:0]

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 34 OF 96Modified on May/04/2000 Table 7 lists all the video standards that the VBI data slicer supports. Some of these modes are auto detected based on the current video input standard, Configuring the VBI processing consists of many different steps which are individually explained below. 1.7.1. Enabling the VBI Processor The VBI processor can be enabled independently for the ODD or EVEN fields with the ODDEN and EVENEN bits. Some VBI data is only present on line in 1 of the 2 fields, These independent field enables allow control of the total VBI data output from the chip. These controls apply to all VBI Lines, Thus it is not possible to enable Closed caption line 21 for the Even field and line 19 Teletext for both the odd and even field. 1.7.2. Selecting the Type of Output Data As previously mentioned, there are 4 different ways the VBI data can be extracted. Three of these are selected as shown in the table, the fourth method (CCEN and CCDAT pins) is always available if VBI processing is enabled. Table 7: Video Standards Supported by VBI Decoder Mode Value of Chip Detec- tion Bits Required Values of Registers to enable Standard Characteristics of the Stan- dard Format SECAM VBIL0-15 TT_SYS Data Rate (MHz) Number of Bits (bytes) 60Hz Teletext system C (NTSC / Intercast) 1 0 2 0 5.727272 272 (34) 50Hz Teletext system B (PAL) 0 0 2 0 6.9375 344 (43) 50Hz Teletext system A (SECAM) 0 1 2 0 6.203125 304 (38) 60Hz Teletext system B 0 1 2 1 5.727272 280 (35) 50Hz Teletext system C 0 1 2 2 5.734375 272 (34) 50Hz Teletext system D 0 1 2 3 5.6457875 280 (35) 60Hz Teletext system D 0 1 2 3 5.727272 280 (35) Closed Caption NTSC 601 N/A N/A 1 N/A 0.5035 16 (2) CGMS (NTSC 60Hz) 1 N/A 3 N/A 0.447443 20 (3) WSS (PAL 50Hz) 0 N/A 3 N/A 5.0000 84

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 35 OF 96Modified on May/04/2000 The S5D0127X01 adds an additional output mode and flexibility to vary the modes from line to line. If VBCVBS=0 and VBINSRT=1 S5D0127X01 will output sliced data on enabled lines. By setting VBIMID to 1, any line for which VBIL=3 will output raw ADC data instead of WSS or CGMS. This mode allows a mixture of sliced and raw data. This can be used to output raw data from a teletext line and sliced data from a closed caption line. 1.7.3. Select Individual Lines Enabled for VBI Processing The S5D0127X01 allows programmable selection of processing for the various video lines. For example Teletext/Intercast data can be sliced for lines 14 - 17, and closed caption for line 21. Each 2-bit register VBIL0 through VBIL15 defines how a specific VBI line is processed. As can be seen in Figure 36 for 60 Hz and Figure 37 for 50 Hz video, the following alignments exist: Table 8: VBI Data Output Mode (VBILn != 0) VBCVBS VBINSRT Output Mode 0 0 The VBI data is available via the internal registers CCDAT1 and CCDAT2. Only the last 2 extracted bytes are stored in these registers. Thus, this mode is only useful for extraction of Closed Caption data. 0 1 This mode enables output of the sliced VBI data. 1 0 This mode enables output of direct data from the ADC. 1 1 This mode is invalid. Table 9: VBI Line(s) Selection VBIL number Line Number That the VBIL Processing command applies to (Assuming ODDOS=1) Odd Field 60 Hz Even Field 60 Hz Odd Field 50 Hz Even Field 50Hz VBIL0 All Lines Except 10-24 All Lines Except 273-287 All lines Except 7-21 All lines Except 320 - 334 VBIL1 9&10 272&273 6&7 319&320 VBIL2 11 274 8 321 VBIL3 12 275 9 322 VBIL4 13 276 10 323 VBIL5 14 277 11 324 VBIL6 15 278 12 325 VBIL7 16 279 13 326 VBIL8 17 280 14 327 VBIL9 18 281 15 328 VBIL10 19 282 16 329 VBIL11 20 283 17 330 VBIL12 21 284 18 331 VBIL13 22 285 19 332 VBIL14 23 286 20 333 VBIL15 24&25 287&288 21&22 334&335

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 37 OF 96Modified on May/04/2000 always digitized at the CK clock rate. CVBS data is available when HAV is active. Raw CVBS data is output in a similar fashion as decoded video. For 8-bit output format, data is output at CK rate using the same 8-bit port as the decoded video. For 16-bit and 24-bit output format, data is output at CK2 rate using Y and C ports. The sequence of data output is CVBS2n on Y, and CVBS2n+1 on C (note that EXV port is not used in 24-bit format for outputting raw CVBS data). For Closed Caption data, two read-only registers, CCDAT1 and CCDAT2, are provided so the Closed Caption data can be read via the host interface. The VBIFLG bit can be polled to see if data captured in the two registers can be safely read. 1.8. COLOR SPACE CONVERTER The color space converter processes the video data as YCbCr 4:4:4 when converting to RGB. A programmable limiter (YCRANG) can be imposed on the Y/C data to limit the ranges. One can choose to limit the Y/C to 1 - 254, or Y to 16 - 235 and C to 16 - 240. When selected, YCbCr 4:4:4 is converted to 24 bit RGB according to the following equations: For 16-bit RGB output, truncation with dithering is used to convert the data from 24 bit to 16 bit. 1.9. GAMMA CORRECTION The S5D0127X01 programmable gamma tables allows the customer to apply many different type of corrections. These corrections can be a standard 2.2 factor for NTSC or 2.8 for PAL. These factors can be applied in the RGB or YUV domains. A basic standard gamma equation of when applied to the R, G, or B signals, generates the response shown as the upper curve below. It is the inverse of the monitor response and thus compensates to produce a linear response. RC Y 1.375CR+= GC Y 0.703CR– 0.328CB–= BC Y 1.734CB+= RR '2.2=

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 39 OF 96Modified on May/04/2000 For ease of design, the difference between adjacent points must also be loaded. The complete data values for the previous gamma factor of 1/2.2 is shown in the table below. The flexibility of this architecture is shown in the following example. Here it is assumed that the S5D0127X01 is operating in a YUV output mode but some form of Gamma correction is required. By converting the RGB gamma correction function back to the YUV color space, the following function can be applied to the U and V signals for improved color performance. This flexibility can be extended in software to produce many type of customer defined transfer functions. Table 10: RGB Gamma LUT Values Offset GAMMA program at index Offset+40h GAMMAD program at index Offset+60h 0 0 53 1 53 20 2 73 14 3 87 12 4 99 11 5 110 10 6 120 8 7 128 8 8 136 8 9 144 7 A 151 7 B 158 6 C 164 6 D 170 6 E 176 5 F 181 6 10 187 5 11 192 5 12 197 5 13 202 5 14 207 4 15 211 5 16 216 4 17 220 5 18 225 4 19 229 4 1A 233 4 1B 237 4 1C 241 4 1D 245 4 1E 249 3 1F 252 4

Figure 34. Gamma Correction for Cb and Cr

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 41 OF 96Modified on May/04/2000 1.10. DIGITAL VIDEO OUTPUT The S5D0127X01 can output digital video data in various formats, which are tabulated in Table 11. All 8-bit output Table 11: Digital Video Output Format Clock CK2 CK OFMT 0 1 4 5 6 7 2, 3 Type YCbCr 4:2:2 YCbCr 4:1:1 YCbCr 4:4:4 RGB 565 RGB 888 RGB

888 YCbCr 4:2:2

Pin 2N +1 4N +1 +2 +3 N N N N 4N +1 +2 +3 C0 Cb0 Cr0 Cb0 B0 B0 B3 C1 Cb1 Cr1 Cb1 B1 B1 B4 C2 Cb2 Cr2 Cb2 B2 B2 B5 C3 Cb3 Cr3 Cb3 B3 B3 B6 C4 Cb4 Cr4 Cr6 Cr4 Cr2 Cr0 Cb4 B4 B4 B7 C5 Cb5 Cr5 Cr7 Cr5 Cr3 Cr1 Cb5 G0 B5 G2 C6 Cb6 Cr6 Cb6 Cb4 Cb2 Cb0 Cb6 G1 B6 G3 C7 Cb7 Cr7 Cb7 Cb5 Cb3 Cb1 Cb7 G2 B7 G4 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 G3 G0 G5 Cb0 Y0 Cr0 Y0 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 G4 G1 G6 Cb1 Y1 Cr1 Y1 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 G5 G2 G7 Cb2 Y2 Cr2 Y2 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 R0 G3 R3 Cb3 Y3 Cr3 Y3 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 R1 G4 R4 Cb4 Y4 Cr4 Y4 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 R2 G5 R5 Cb5 Y5 Cr5 Y5 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 R3 G6 R6 Cb6 Y6 Cr6 Y6 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 R4 G7 R7 Cb7 Y7 Cr7 Y7 EXV0 Cr0 R0 B0 EXV1 Cr1 R1 B1 EXV2 Cr2 R2 B2 EXV3 Cr3 R3 G0 EXV4 Cr4 R4 G1 EXV5 Cr5 R5 R0 EXV6 Cr6 R6 R1 EXV7 Cr7 R7 R2

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 42 OF 96Modified on May/04/2000 formats use CK as pixel clock; the other formats use CK2 as pixel clock. The first pixel is always aligned to the leading edge of the HAV signal. 1.10.1. Validation Code Insertion S5D0127X01 inserts validation codes during inactive video (HAV is inactive), and invalid video (HAV is active but EHAV is inactive) to assist in recognition of scaled data and VBI data. Table 12 lists the available codes, when they are inserted, and related programming registers. An example timing diagram for some of the programmable modes is shown in Figure 35. In this diagram, The field rate is 60 Hz, A CCIR 601 sampling rate has been selected thus giving 720 active pixels. The horizontal scaling ratio has been selected for an output of 718 out of 720 pixels. Table 12: Invalid and Unused Code Insertion Code Description INVALY This user programmed code is inserted in the Y or G output stream in scaling operation when HAV is active while EHAV is inactive. Insertion of this code is independent of the output format. Related register is INVALY. INVALU This user programmed code is inserted in the U or B output stream in scaling operation when HAV is active while EHAV is inactive. Insertion of this code is independent of the output format. Related register is INVALU. INVALV This user programmed code is inserted in the V or R output stream in scaling operation when HAV is active while EHAV is inactive. Insertion of this code is independent of the output format. Related register is INVALV. UNUSEY This user programmed code is inserted in the Y or G output stream when HAV is inactive and no other reference code is inserted. Insertion of this code is independent of the output format. Related register is UNUSEY. UNUSEU This user programmed code is inserted in the U or B output stream when HAV is inactive and no other reference code is inserted. Insertion of this code is independent of the output format. Related register is UNUSEU. UNUSEV This user programmed code is inserted in the V or R output stream when HAV is inactive and no other reference code is inserted. Insertion of this code is independent of the output format. Related register is UNUSEV.

Figure 35. Horizontal Data Timing for Various Output Modes 656 standard. An optional set of 656 Op Codes can be enabled to identify VBI data using the TASKB bit. current line is processing VBI data (sliced or raw ADC data format).

Figure 36. Vertical Timing for 60 Hz Video

60 Hz EVEN FIELD

60 Hz ODD FIELD

656 SAV EAV Codes for VSE=0, VALIGN=1

Figure 37. Vertical Timing For 50 Hz Video

50 Hz EVEN FIELD

proper transition locations of the SAV and EAV Op Codes VSE=0 and VALIGN=1. The S5D0127X01 supports the IIC serial interface for programming the chip registers. S5D0127X01’s can be used in one system each with a unique address. Figure 38. IIC Slave Device ID and R/ W Byte

656 FVH values

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 48 OF 96Modified on May/04/2000 2. CONTROL REGISTER DESCRIPTION This section contains information concerning the programmable control registers. Table 14 provides the default power up values for each index, and a bit map for each register. The following pages describe each register in detail and the possible programing values (an * indicates the power-on default). Gamma correction registers are write only. When the index register points to any of the Gamma correction register, the Gamma look-up table is put into a program mode. Normal operation resumes when the index is outside the range from 0x40 to 0xFF. Table 14: Register Summary Index Mnemonic Default Bit Map 7 6 5 4 3 2 1 0 0x00 STAT RO CHIPID VBIFLG NOVID FFRDET PALDET CDET HLOCK CLOCK 0x01 CMDA 2C POWDN VSE HFSEL[1:0] XT24 PIXSEL MNFMT IFMT 0x02 CMDB 20 AGCGN VALIGN AGCOVF AGCFRZ INSEL[3:0] 0x03 CMDC 00 VMEN TSTGE1 0 TSTGPK TSTGPH TSTGFR[1:0] TSTGEN 0x04 CMDD 00 EAV 0 CKDIR INPSL[1:0] SYNDIR Y1MHZ GPPORT 0x05 HAVB 00 HAVB[7:0] 0x06 HAVE 00 HAVE[7:0] 0x07 HS1B 00 HS1B[8:1] 0x08 HS1E 00 HS1E[8:1] 0x09 HS2B 00 HS2B[8:1] 0x0A HS2E 00 HS2E[8:1] 0x0B AGC 50 AGC[7:0] 0x0C HXTRA 00 HAVB[10:8] HAVE[10:8] HS1BE0 HS2BE0 0x0D CDEM 00 OUTHIZ FSEC 0 CIFCMP[1:0] 0 0 0 0x0E PORTAB 00 DIRB DATAB[2:0] DIRA DATAA[2:0] 0x0F LUMA 00 0 UNIT RGBH PED HYBWR CTRAP HYPK[1:0] 0x10 CON 00 CONT[7:0] 0x11 BRT 00 BRT[7:0] 0x12 CHROMA 08 ACCFRZ PALM PALN CBW CORE[1:0] CKILL[1:0] 0x13 CHROMB 00 CDLY[3:0] SCHCMP[3:0] 0x14 DEMOD 00 FSCDET SECDET CDMLPF CTRACK MNFSC[1:0] MNSECAM[1:0] 0x15 SAT 00 SAT[7:0] 0x16 HUE 00 HUE[7:0] 0x17 VERTIA 00 MNYCMB YCMBCO[2:0] VRT2X VCTRL[2:0] 0x18 VERTIB 00 HYLPF[2:0] HYBWI HYDEC VSCLEN[1:0] 0 0x19 VERTIC 03 MNCCMB CCMBCO[2:0] ACMBEN VYBW EVAVEV EVAVOD 0x1A HSCLL 00 HSCL[6:0] CMBMOD 0x1B HSCLH 00 HSCL[14:7] 0x1C VSCLL FC VSCL[5:0] ACMBCO ACMBRE 0x1D VSCLH FF VSCL[13:6] 0x1E OFMTA - GAMEN[1:0] OENC[1:0] OFMT[3:0] 0x1F OFMTB 00 VSVAV EVAND[1:0] EVHS1 EVHAV EVEHAV EVAVG EVANDL

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 49 OF 96Modified on May/04/2000 0x20 VBICTL 00 VBCVBS VYFMT[1:0] VBINSRT ODDEN EVENEN ODDOS[1:0] 0x21 CCDAT1 RO b0 b1 b2 b3 b4 b5 b6 P1 0x22 CCDAT2 RO b0 b1 b2 b3 b4 b5 b6 P2 0x23 VBIL30 00 VBIL3 VBIL2 VBIL1 VBIL0 0x24 VBIL74 00 VBIL7 VBIL6 VBIL5 VBIL4 0x25 VBIL118 00 VBIL11 VBIL10 VBIL9 VBIL8 0x26 VBIL1512 00 VBIL15 VBIL14 VBIL13 VBIL12 0x27 TTFRAM 00 TTFRAM[7:0] 0x28 TESTA 00 0 0 0 0 0 0 0 0 0x29 UVOFFH 00 TSTCLC TSTCGN 0 TSTCFR UOFFST[5:4] VOFFST[5:4] 0x2A UVOFFL 33 UOFFST[3:0] VOFFST[3:0] 0x2B UGAIN 00 UGAIN[7:0] 0x2C VGAIN 00 VGAIN[7:0] 0x2D VAVB 23 VAVB[6:1] VAVOD0 VAVEV0 0x2E VAVE 82 VAVE[8:1] 0x2F CTRACK 00 0 0 DMCTL[1:0] CGTC[1:0] CFTC[1:0] 0x30 POLCTL 00 EVAVPL VSPL ODDPL HAVPL EHAVPL HS2PL VAVPL HS1PL 0x31 REFCOD 00 YCRANG 0 0 0 0 0 0 0 0x32 INVALY 10 INVALY[7:0] 0x33 INVALU 80 INVALU[7:0] 0x34 INVALV 80 INVALV[7:0] 0x35 UNUSEY 10 UNUSEY[7:0] 0x36 UNUSEU 80 UNUSEU[7:0] 0x37 UNUSEV 80 UNUSEV[7:0] 0x38 EXCTRL 00 0 ENINCST 0 - AUCPWD 0 0 CLEVEL 0x39 TRACKA 00 STCTRL MAC_DETVCR_DET VCR_LEV[1:0] ATCTRAP VCTRAP AGCLSB 0x3A VBICTLB 00 VBISWAP TT_SYS[1:0] VBIMID NEW_CC CC_OVFL YOFFENB COFFENB 0x3B TRACKB 00 ALT656 VBI_PH VBI_FR PH_CTRLVNOISCT AGC_LPG[1:0] AGC_LKG 0x3C RTC 00 RTC_DTO RTC_PID 0 TDMOD 0 0 0 0 0x3D CMDE 09 ODFST VSALG HCORE[1:0] CHIPREVID 0x3E VSDEL 00 TR_MS NOVIDC VSDEC[5:0] 0x3F CMDF 00 CTRAPFSC VIPMODE EVAVY UVDLEN UVDLSL REGUD TASKB CBWI 0x40-5F GAMMA - GAMMA0[7:0] - GAMMA31[7:0] 0x60-7F GAMMAD - - - GAMMAD0[5:0] - GAMMAD31[5:0] 0xC0-DF GAMUV - GAMUV0[7:0] - GAMUV31[7:0] 0xE0-FF GAMUVD - - - GAMUVD0[5:0] - GAMUVD31[5:0] Table 14: Register Summary Index Mnemonic Default Bit Map 7 6 5 4 3 2 1 0

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 50 OF 96Modified on May/04/2000 Read Only Status Bits Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h STAT CHIPID VBIFLG NOVID FFRDET PALDET CDET HLOCK CLOCK CLOCK Status for color lock. 0 Not locked. 1 Color lock achieved. HLOCK Status for current line tracking mode. 0 Chip is in initial tracking mode. 1 Chip is in steady state tracking mode. CDET Status for detection of color. 0 No color signal is detected. 1 Color signal is detected. PALDET Status for current detected color format. Information contained in this bit is valid only if CLOCK is 1. 0 NTSC color format. 1 PAL color format. FFRDET Status for current detected field frequency. 0 50 Hz field frequency, i.e. N,B,G,H,I,D,K,K1,L system. 1 60 Hz field frequency, i.e. M system. NOVID Video detect flag. This bit should not be used for detecting the presence of a TV channel from the output of a TV tuner. 0 Sync has been detected for the last 32 lines. 1 No sync has been detected. VBIFLG Vertical blanking interval flag. 0 Video is in active region. 1 Video is in vertical blanking region. CHIPID Chip version ID. Please refer to the CHIPREVID bits for additional information 0 KS0122S. 1 S5D0124D01.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 51 OF 96Modified on May/04/2000 Control Register A Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01h CMDA POWDN VSE HFSEL[1:0] XT24 PIXSEL MNFMT IFMT IFMT Manual video input standard select. Standard selection can be controlled automatically if MNFMT=0. 0 Chip is forced to assume input is 50 Hz.* 1 Chip is forced to assume input is 60 Hz. MNFMT Manual input format control override. When this bit is 1 the IFMT bit is enabled.

0 The chip determines the input video standard based on the detected field rate:*

NTSC if 60 Hz. PAL/SECAM if 50 Hz. 1 Input video standard is selected with the IFMT bit. PIXSEL Select pixel sampling rate. 0 Output data is at square pixel rate. 1 Output data is at CCIR 601 rate.* XT24 Select the external clock reference frequency. 0 External clock is 26.8 MHz. 1 External clock is 24.576 MHz.* HFSEL[1:0] Horizontal tracking loop frequency select. 0 Force loop to very fast. 1 Force loop to fast. 2 Force loop to VCR time constant.* 3 Force loop to TV time constant. VSE Change the vertical end location of the VS. 0 Line 10/10.5.* 1 Line 9/9.5. POWDN Power down mode. 0 Normal operation.*

1 All chip functions except microprocessor interface and CK/CK2 generation are

disabled. The output of the CK/CK2 pins retains the most recent frequency when the power down mode is enabled.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 52 OF 96Modified on May/04/2000 Control Register B Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 02h CMDB AGCGN VALIGN AGCOVF AGCFRZ INSEL[3:0] INSEL[3:0] Analog input channel select. 0 AY0 is composite input.* 1 AY1 is composite input. 2 AY2 is composite input. 4 AC0 is composite input. 5 AC1 is composite input. 6 AC2 is composite input. 8 AY0 is luminance input, AC0 is chrominance input. 9 AY1 is luminance input, AC1 is chrominance input. A AY2 is luminance input, AC2 is chrominance input. F AY2 is luminance input, AC1 is Cb input, AC2 is Cr input. AGCFRZ Freeze the analog AGC for the Y and C paths at their current values. 0 AGC is running. Reading AGC register returns the current AGC gain.* 1 AGC is frozen. Gain can be changed or read with AGC register. AGCOVF AGC gain control mode. 0 AGC gain tracks to sync tip and back porch delta.

1 If ADC overflows, AGC gain will be reduced (this has higher priority over normal

sync tip - back porch tracking).* VALIGN VS edge alignment control.

0 VS leading edge occurs during serration pulses (typically within the first serration

pulse). VS trailing edge is aligned to half line or beginning of the line depending on the field.*

1 VS leading edge is aligned to half line or beginning of the line depending on the

field. VS trailing edge is always aligned to beginning of the line. AGCGN AGC gain calculation. 0 Normal mode. AGC gain calculation is based on sync tip to back porch difference equal to 68 ADC code.*

1 AGC gain calculation is base on sync tip to back porch difference equal to 54 ADC

code. This will reduce the AGC gain by a factor of 1/1.25 compare to normal mode. When used in conjunction with PED and RGBH, this effectively increases the input dynamic range.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 53 OF 96Modified on May/04/2000 Control register C Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 03h CMDC VMEN TSTGE1 0 TSTGPK TSTGPH TSTGFR[1:0] TSTGEN TSTGEN Enable manual control of horizontal phase and frequency tracking. 0 Auto phase and frequency tracking.*

1 Enable manual control of horizontal phase and frequency with TSTGFR[1:0] and

TSTGPH. TSTGFR[1:0] When TSTGEN == 1, these two bits control the horizontal frequency tracking. 00 Stop frequency tracking and freeze the frequency at the current value.* 01 Horizontal frequency tracks the input. 1X Horizontal frequency tracking ignores video input and runs at nominal value based on the field rate and output pixel rate selected by IFMT and PIXEL bits. TSTGPH When TSTGEN == 1, this bit controls the horizontal phase tracking. 0 No phase tracking.* 1 Horizontal phase tracks the input video or HS1 input if in slave mode. TSTGPK If TSTGE1 == 1, this bit controls AGC. 0 AGC clamps to back porch and gain is set based on sync tip-back porch difference.* 1 AGC clamps to sync tip and gain is set based on peak-valley difference. TSTGE1 Enables the function of TSTGPK. 0 Disables TSTGPK.* 1 Enables TSTGPK. VMEN Vertical master mode. 0 Normal vertical sync operation.* 1 Vertical sync ignores input and free runs at 50 Hz or 60 Hz. This mode can be used to generate video timing for a slave device.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 54 OF 96Modified on May/04/2000 Control Register D Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 04h CMDD EAV 0 CKDIR INPSL[1:0] SYNDIR Y1MHZ GPPORT GPPORT General purpose port. This register is useful only if DATAA[2:0] == 7. If DIRA == 0, this bit is read only and reflects the logic state at PORTA pin. If DIRA == 1, any value written to this bit will appear at PORTA pin. Y1MHZ Luma bandwidth control. 0 Luma bandwidth is controlled by other luma filters in the luma path.* 1 Luma data is low pass filtered to 1MHz bandwidth. SYNDIR HS1 and VS pin direction control. 0 HS1 and VS are output.* 1 HS1 and VS are input. INPSL[1:0] Video input and clock source select. 0 Video source is analog and connected to the chip’s analog input. Clock is internally generated.* 1 Video source is 8-bit digital CbYCr and connected to EXV0 through EXV7 pins. 3 Video source is 8-bit digitized CVBS and connected to EXV0 through EXV7 pins. CKDIR Clock select. 0 Clock is from internal clock generator. A reference clock at XTALI pin is required.* 1 Clock is from CK pin. When this is selected, the CK pin automatically becomes an input. EAV In 8-bit digital CbYCr input mode, this bit selects the sync source. 0 Horizontal and vertical syncs are from HS1 and VS pins, respectively.* 1 Syncs are embedded in the 8-bit digital data stream (CCIR 656 compatible).

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 55 OF 96Modified on May/04/2000 HAV Start Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05h HAVB HAVB[7:0] 0Ch HXTRA HAVB[10:8] HAVE[10:8] HS1BE0 HS2BE0 HAVB[10:0] This 11-bit register is used to define the start location of the HAV signal relative to the sync tip (for CVBS input, this is the composite video sync tip. For 8-bit CbYCr input, this is the leading edge of the HS1 or EAV). The content of this register is a 2’s complement number which is used as an offset to the default. The resolution for this register is 1 CK clock. HAV End Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 06h HAVE HAVE[7:0] 0Ch HXTRA HAVB[10:8] HAVE[10:8] HS1BE0 HS2BE0 HAVE[10:0] This 11-bit register is used to define the end location of the HAV signal relative to the sync tip. The content of this register is a 2’s complement number which is used as an offset to the default The resolution for this register is 1 CK clock. HS1 Start Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 07h HS1B HS1B[8:1] 0Ch HXTRA HAVB[10:8] HAVE[10:8] HS1BE0 HS2BE0 HS1B[8:1] - HS1BE0 If HS1 is programmed as an output, this 9-bit register defines the start location of the HS1 signal. The content of this register is a 2’s complement number which is used as an offset to the default. The resolution for this register is 1 CK clock.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 56 OF 96Modified on May/04/2000 HS1 End Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 08h HS1E HS1E[8:1] 0Ch HXTRA HAVB[10:8] HAVE[10:8] HS1BE0 HS2BE0 HS1E[8:1] - HS1BE0 If HS1 is programmed as an output, this 9-bit register defines the end location of the HS1 signal. The content of this register is a 2’s complement number which is used as an offset to the default. The resolution for this register is 1 CK clock. HS2 Start Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 09h HS2B HS2B[8:1] 0Ch HXTRA HAVB[10:8] HAVE[10:8] HS1BE0 HS2BE0 HS2B[8:1] - HS2BE0 This 9-bit register defines the start location of the HS2 signal. The content of this register is a 2’s complement number which is used as an offset to the default HS2B location. The resolution for this register is 1 CK clock. HS2 End Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0Ah HS2E HS2E[8:1] 0Ch HXTRA HAVB[10:8] HAVE[10:8] HS1BE0 HS2BE0 HS2E[8:1] - HS2BE0 This 9-bit register defines the end location of the HS2 signal. The content of this register is a 2’s complement number which is used as an offset to the default HS2E location. The resolution for this register is 1 CK clock.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 57 OF 96Modified on May/04/2000 AGC Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0B AGC AGC[7:0] AGC[7:0] This register is used to manually set AGC when AGCFRZ is set to “1”. The content in the register is unsigned. Chroma Demodulation Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0Dh CDEM OUTHIZ FSEC 0 CIFCMP[1:0] 0 0 0 CIFCMP[1:0] IF compensation for the chroma path. 0 No compensation.* 1 Upper chroma side band is 1 dB higher than lower side band. 2 Upper chroma side band is 3 dB higher than lower side band. 3 Upper chroma side band is 6 dB higher than lower side band. FSEC Chroma frequency demodulation filter select for SECAM video. 0 Select SECAM chroma frequency demodulation filter if SECAM video is detected.* 1 Always use SECAM chroma frequency demodulation filter. OUTHIZ This is the software output three-state control bit. If this bit is set to a “1”, or the OEN pin is at a logic LOW level, output pins can be selectively put in the high impedance state using the additional software control bits OENC[1:0]. 0 This is default setting.*

1 This will enable the output pins to be three-stated regardless the state of the OEN

pin.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 58 OF 96Modified on May/04/2000 Port A and B Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0Eh PORTAB DIRB DATAB[2:0] DIRA DATAA[2:0] DATAA[2:0] Port A data select. For internal gate signal locations. 0 Port A is disconnected from the internal signal path.* 1 Port A is connected to the BPG (back porch gate) signal. 2 Port A is connected to the SYG (sync tip gate) signal. 3 Port A is connected to the CBG (color burst gate) signal. 4 Port A is connected to the CBGW (color burst gate wide) signal. The CBGW is high for the entire color burst period. 5 Port A is connected to the SLICE (mid way of the sync tip) signal. 6 Port A is connected to the VBI (vertical blanking interval) signal. 7 Port A is connect to the GPPORT bit. DIRA Port A direction control. 0 Port A is configured as input. The input is connected directly to the signal path selected by DATAA[2:0]. The internally generated gate signal is disconnected from the signal path.*

1 Port A is an output and is driven by the internally generated signal as selected by

DATAA[2:0]. DATAB[2:0] Port B data select. For internal gate signal locations. 0 Port B is disconnected from the internal signal path.* 1 Port B is connected to the SCH (sync tip to color burst phase) signal. 2 Port B is connected to the FH2 (twice per line pulses) signal. 3 Port B is connected to the FS_PULSE (falling edge of the sync tip) signal. 4 Port B is connected to the VBI_CVBS (VBI raw ADC) signal. This signal is high for those lines that output data directly from the ADC (not YUV or RGB data). 5 Port B is connected to the VBI_PROC (VBI sliced) signal. This signal is high for those video lines that output sliced VBI data. 6 Port B is connected to the VS (Vertical Sync) signal. 7 Port B is configured as the RTCO (Real Time Control Output). This single pin serial interface transmits phase and frequency information to a video encoder so that it may operate directly from the S5D0127X01 output clock. DIRB Port B direction control. 0 Port B is configured as input. The input is connected directly to the signal path selected by DATAB[2:0]. The internally generated gate signal is disconnected from the signal path.*

1 Port B is an output and is driven by the internally generated signal as selected by

DATAB[2:0].

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 59 OF 96Modified on May/04/2000 Luma Control Register Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0F LUMA 0 UNIT RGBH PED HYBWR CTRAP HYPK[1:0] HYPK[1:0] Luminance horizontal peaking control around 3 MHz. 0 Less than nominal peaking.* 1 Nominal peaking. 2 Increased peaking. 3 Maximum peaking. CTRAP Chroma trap (notch filter) in the luma path. 0 No chroma trap. This mode is recommended for S-video or component video input.* 1 Chroma trap is enabled. HYBWR Luminance horizontal bandwidth reduction control. 0 Full bandwidth.* 1 Reduced bandwidth. PED Enable gain correction for 7.5 blank-to-black setup (pedestal). 0 No pedestal. 0% = Y code 16. 100% = Y code 235.* 100% input produce Y code 16 - 235. RGBH High gain to produce full range Y for 0% (or 7.5% if PED = 1) to 100% input. 0 Black (0% or 7.5%) to peak white(100%) input produce Y code 16 to 235.*. 1 Black (0% or 7.5%) to peak white(100%) input produce Y code 0 to 255. UNIT When PED and RGBH are both set to a “1”, setting this bit to a “1” produces a unit gain for CCIR 601 digital input (INPSL[1:0] = 1). 0 Luma DC gain is controlled by PED and RGBH as described for each bit.* 1 Luma DC gain is unity for CCIR 601 digital input.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 60 OF 96Modified on May/04/2000 Contrast Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x10 CON CON[7:0] CON[7:0] This 8-bit register contains a 2’s compliment number for contrast control. Brightness Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x11 BRT BRT[7:0] BRT[7:0] Brightness control register. The number contained in the register is 2’s compliment.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 61 OF 96Modified on May/04/2000 Chroma Control Register A Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x12 CHROMA ACCFRZ PALM PALN CBW CORE[1:0] CKILL[1:0] CKILL[1:0] Color kill. 0 Auto detect mode. If color burst is too low or no color burst, chroma data is forced to code 128.* 2 Chroma is always ON. 3 Chroma data is always forced to code 128. CORE[1:0] Chroma data coring. 0 No coring. 1 Chroma data within the range 128+/-1, inclusive, will be force to 128. 2 Chroma data within the range 128+/-3, inclusive, will be force to 128.* 3 Chroma data within the range 128+/-7, inclusive, will be force to 128. CBW Chroma bandwidth control. 0 Chroma 3 dB bandwidth is 850 kHz.* 1 Chroma 3 dB bandwidth is 550 kHz. PALN Select color tracking for PAL-N, or NTSC-N when input field rate is 50 Hz and Fsc is 3.58 MHz. 0 Select NTSC-N.* 1 Select PAL-N. PALM Select color tracking for PAL-M or NTSC-M when input field rate is 60 Hz. 0 Select color tracking for NTSC-M.* 1 Select color tracking for PAL-M. ACCFRZ Chroma gain tracking freeze control. 0 Chroma gain tracks the input. Color saturation can be adjusted with SAT.* 1 Chroma gain freezes at the current saturation level.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 62 OF 96Modified on May/04/2000 Chroma Control Register B Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x13 CHROMB CDLY[3:0] SCHCMP[3:0] SCHCMP[3:0] Phase constant compare value for color burst phase relative to sync tip. Each step is 22.5 degrees with the value of 0 equal to 0 degree. CDLY[3:0] Chroma path group delay relative to the luma path (in unit of CK): 0 No delay.* 1 -0.5 2 1 3 0.5 4 2 5 1.5 6 3 7 2.5 8 -4 9 -4.5 A -3 B -3.5 C -2 D -2.5 E -1 F -1.5

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 63 OF 96Modified on May/04/2000 Chroma Demodulation Control and Status Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x14 DEMOD FSCDET SECDET CDMLPF CTRACK MNFSC[1:0] MNSECAM[1:0] MNSECAM[1:0] Enable manual SECAM input detection. 0 Detection of SECAM input is automatic.* 2 Force the chip to assume input is not SECAM. 3 Force the chip to assume input is SECAM. MNFSC[1:0] Enable manual Fsc detection. 0 Detection of Fsc frequency is automatic.* 2 Force chip to assume input Fsc is 4.43 MHz or 4.286 MHz. 3 Force chip to assume input Fsc is 3.58 MHz. CTRACK Chroma frequency tracking mode. 0 Chroma frequency tracking is based on the field rate and Fsc.* 1 Chroma frequency tracking is based on field rate only. CDMLPF Bypass the LPF in the chroma demodulator. 0 Chroma data pass through the LPF for color demodulation.* 1 Chroma data bypass the LPF. This setting is used for component video input. SECDET SECAM detection (read only). 0 Chip did not detect SECAM input. 1 Chip detected SECAM input. FSCDET Color subcarrier detection (read only). 0 Chip detected 4.43 MHz or 4.286 MHz Fsc. 1 Chip detected 3.58 MHz Fsc.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 64 OF 96Modified on May/04/2000 Color Saturation Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x15 SAT SAT[7:0] SAT[7:0] Color saturation control register. Register content is in 2’s compliment if TSTCGN=0. 0 value corresponds to nominal saturation. Hue Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x16 HUE HUE[7:0] HUE[7:0] Hue control register. The register content is in 2’s compliment format. It covers the range from -180° to +178.59° degree. The resolution is 1.41°/LSB.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 65 OF 96Modified on May/04/2000 Vertical Processing Control A Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x17 VERTIA MNYCMB YCMBCO[2:0] VRT2X VCTRL[2:0] VCTRL[2:0] Luminance vertical filter control. 0 Scaler uses LPF path, comb uses HPF.* 1 Scaler uses full bandwidth, comb is disabled. 2 Scaler is disabled, comb uses full bandwidth. 3 Scaler uses LPF, comb is disabled. 4 Scaler is disabled, comb uses HPF. VRT2X 3/5-tap vertical scaler filter select. 0 Select 3-tap vertical scaler filter.* 1 Select 5-tap vertical scaler filter. This option can be used only if horizontally cropped line is less than or equal to 384 pixels. YCMBCO[2:0] Luma comb filter coefficients selection when the MNYCMB is set to “1”. 0 [1/4 1/2 1/4].* 1 [3/8 1/2 1/8]. 2 [1/2 1/2 0]. 3 [1 0 0]. 4 [0 1 0]. 5 [1/2 0 1/2]. 6 [0 1/2 1/2]. 7 [1/8 1/2 3/8]. MNYCMB Select between auto and manual luma comb filter coefficients.

0 Luma comb filter coefficients are automatically selected based on input video

standard.* 1 Luma comb filter coefficients are selected with YCMBCO[2:0].

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 66 OF 96Modified on May/04/2000 Vertical Processing Control B Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x18 VERTIB HYLPF[2:0] HYBWI HYDEC VSCLEN[1:0] 0 VSCLEN[1:0] Vertical scaling enable. 0 Vertical scaling is enabled.* 1 Vertical scaling is disabled. 2 Vertical scaling is disabled. Video is 1-line delayed. 3 Vertical scaling is disabled. Video is 2-line delayed. HYDEC Luma path decimation filter enable. 0 Luma path decimation is enabled.* 1 Luma path decimation is disabled. HYBWI Luma path decimation filter bandwidth select. 0 Normal bandwidth.* 1 Bandwidth is 1 MHz higher. HYLPF[2:0] Horizontal luma LPF bandwidth control. 0 Full bandwidth.* 1 4.5 MHz bandwidth. 2 3.5 MHz bandwidth. 3 2.5 MHz bandwidth. 4 1.5 MHz bandwidth.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 67 OF 96Modified on May/04/2000 Vertical Processing Control C Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x19 VERTIC MNCCMB CCMBCO[2:0] ACMBEN VYBW EVAVEV EVAVOD EVAVOD Enable VAV signal output during ODD field. 0 VAV signal is disabled (always inactive) during ODD field. 1 VAV signal is enabled during ODD field.* EVAVEV Enable VAV signal output during EVEN field. 0 VAV signal is disabled (always inactive) during EVEN field. 1 VAV signal is enabled during EVEN field.* VYBW Luma vertical bandwidth control. 0 Full bandwidth.* 1 Reduced bandwidth. ACMBEN Enable luma active comb for NTSC. 0 Active comb is disabled.* 1 Active comb is enabled. CCMBCO[2:0] Manual chorma comb filter coefficients select. 0 Select the coefficient set [1/2 1/2 0] (if VRT2X = 0).* 1 Select the coefficient set [1/4 1/2 1/4] (if VRT2X = 0). 2 Select the coefficient set [0 1/2 1/2 0 0] (if VRT2X = 1). 3 Select the coefficient set [0 1/4 1/2 1/4 0] (if VRT2X = 1). 4 Select the coefficient set [1 0 0]. 5 Select the coefficient set [0 1 0]. 6 Select the coefficient set [0 0 1]. 7 No output (disabled). MNCCMB Chroma comb filter coefficients are selected automatically or manually.

0 Filter coefficients are automatically selected based on the selected video input

standard. SECAM must use this value.* 1 Filter coefficients are selected manually with CCMBCO[2:0].

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 68 OF 96Modified on May/04/2000 Horizontal Scaling Ratio Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x1A HSCLL HSCL[6:0] CMBMOD 0x1B HSCLH HSCL[14:7] CMBMOD This bit controls when comb is enabled internally. 0 Comb is enabled by the internal signal COMB_EN.* 1 Comb is enabled when VAV is active. HSCL[14:0] The 15-bit register defines a horizontal scaling ratio of HSCL[14:0]/215. Any change to this value will become effective during the next vertical sync. Vertical Scaling Ratio Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x1C VSCLL VSCL[5:0] ACMBCO ACMBRE 0x1D VSCLH VSCL[13:6] ACMBRE Active comb filter threshold select. 0 High threshold.* 1 Low threshold. ACMBCO Active comb filter coefficient set select. 0 Use the set of coefficients for 100% comb.* 1 Use the set of coefficients for 75% comb. VSCL[13:0] The 14-bit register defines a vertical scaling ratio of VSCL[13:0]/214. Any change to this value will become effective during the next vertical sync.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 69 OF 96Modified on May/04/2000 Output Control A Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x1E OFMTA GAMEN[1:0] OENC[1:0] OFMT[3:0] OFMT[3:0] Digital video output format select. 16 and 24 bit data are output at CK2 clock rate. 8 bit data are output at CK clock rate. 0 16-bit YCbCr 4:2:2 output on the Y and C output ports.* 1 12-bit YCbCr 4:1:1 output on the Y and C output ports. 2 8-bit YCbCr 4:2:2 without embedded timing reference codes. 3 8-bit YCbCr 4:2:2 with embedded timing reference codes. 4 24-bit YCbCr 4:4:4. 5 16-bit RGB 565. 6 24-bit RGB 888 with linear bit ordering. 7 24-bit RGB 888, bit ordering is an extension of the 16-bit RGB 565 format.

8 Same as mode 2 with the additional of 8-bit YCbCr 4:2:2 data output on the EXV

port. While the Y port can be scaled down, the EXV port will always be a full size picture. 9 Same as 8 with the addition of SAV and EAV codes. A output Y ADC data all the time (including syncs) on the Y port, C port is non-scaled 656 data with no timing codes. B Output Y ADC data all the time (including syncs) on the Y port, Output C ADC data all the time (including syncs) on the C port, OENC[1:0] When either the OEN pin is low or the OUTHIZ is a “1”, these two bits will determine which output pins are three-stated. 0 All video pins are three-stated.

1 All video pins, plus HAV, VAV, EVAV, EHAV, PID, ODD, HS1, HS2, VS, and SCH are

three-stated. 2 All pins listed above, plus CK and CK2 are three-stated. 3 Always output data. GAMEN[1:0] Gamma correction enable. 0 No gamma correction.* 1 Gamma correction is applied to Y/G data. 2 Gamma correction is applied to U/B and V/R data. 3 Gamma correction is applied to Y/G, U/B, and V/R data.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 70 OF 96Modified on May/04/2000 Output Control B Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x1F OFMTB VSVAV EVAND[1:0] EVHS1 EVHAV EVEHAV EVAVG EVANDL EVAVG Gate EVAV with VAV before sending to output. 0 EVAV is not gated with VAV. EVAV may be active outside of active VAV region.* 1 EVAV is gated with VAV. EVAV can be active only when VAV is active. EVEHAV Additional qualifier for EHAV. 0 No additional qualifier.* 1 EHAV uses qualifier from EVAND[1:0]. EVHAV Additional qualifier for HAV. 0 No additional qualifier.* 1 HAV uses qualifier from EVAND[1:0]. EVHS1 Additional qualifier for HS1. 0 No additional qualifier.* 1 HS1 uses qualifier from EVAND[1:0]. EVAND[1:0], EVANDL Qualifier signal that defines active video lines. This control enables 656 codes, HAV, EHAV and HS1. EVANDL is the EVAND LSB. These three bits are grouped together and explained below 0 Qualifier is active for all lines.* 1 Qualifier is EVAV. -- Any line during vertical active or blank will be output.

2 Qualifier is EVAV and VAV -- All lines during vertical blank (VAV==0) and all lines

when EVAV is active during vertical active will be output. 3 Qualifier is VAV -- All lines during vertical active will be output.

4 Qualifier is EVAV and VAV -- All lines that EVAV is active during vertical active will

be output.

5 Qualifier is EVAV, VAV and VBI_RAW_EN -- All lines as in option 4 plus the VBI

RAW ADC lines.

6 Qualifier is EVAV, VAV, VBI_RAW_EN and VBI_SLC_EN-- All lines as in option 5

plus the VBI Sliced Lines. 7 All VBI sliced and VBI RAW Lines only. VSVAV Enable VAV to be output to VS. 0 Output normal VS.*

1 VS has the same output as VAV

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 71 OF 96Modified on May/04/2000 VBI Decoder Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x20 VBICTL VBCVBS VYFMT[1:0] VBINSRT ODDEN EVENEN ODDOS[1:0] ODDOS[1:0] Line offset for ODD field. See also VBIL[15:0]. 0 ODD field line offset is -1 compared to EVEN field.* 1 No offset. 2 ODD field line offset is 1 compared to EVEN field. 3 ODD field line offset is 2 compared to EVEN field. EVENEN VBI data processing for EVEN field. 0 No processing.* 1 VBI processing is enabled for EVEN field. ODDEN VBI data processing for ODD field. 0 No processing.* 1 VBI processing is enabled for ODD field. VBINSRT Enable VBI data to be output on the Y bus. 0 VBI data is not output on the Y bus.* 1 VBI data is output on the Y bus. VYFMT[1:0] When VBINSRT = 1, these bits control how VBI data are output on the Y bus. 0 1 bit on Y7 per CK2 clock.* 1 1 bit on Y7 plus a “1” on Y3 per CK2 clock. 2 4 bits on Y7..Y4, with first bit on Y7, last bit on Y4, plus a “1” on Y3 per CK2 clock. 3 8 bits on Y7..Y0, with first bit on Y7, last bit on Y0, per CK2 clock. VBCVBS Enable digitized CVBS data from ADC to be output for the selected VBI line instead of sliced VBI data. The new VBIMID bit allows simultaneous output (line by line bases) of sliced data and raw ADC data. 0 Output sliced VBI data for any line whose VBIL value ~= 0.* 1 Output digitized CVBS data for any line whose VBIL value ~=0.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 72 OF 96Modified on May/04/2000 First Decoded Close-Caption Data Byte (Read Only) Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x21 CCDAT1 b0 b1 b2 b3 b4 b5 b6 P1 CCDAT1 This byte contains the first byte of the decoded close-caption data as defined in EIA-608. In order for this register to receive the CC data, VBINSRT must be programmed to a “1”, and VYFMT[1:0] must be programmed with the value 3. The same applies to CCDAT2. For normal NTSC Closed Caption decoding, ODDEN should be set to a “1”, VBIL12 should be programmed with the value 1. Second Decoded Close-Caption Data Byte (Read Only) Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x22 CCDAT2 b0 b1 b2 b3 b4 b5 b6 P2 CCDAT2 This byte contains the second byte of the decoded close-caption data as defined in EIA-608. VBI Data Decoding Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x23 VBIL30 VBIL3 VBIL2 VBIL1 VBIL0 0x24 VBIL74 VBIL7 VBIL6 VBIL5 VBIL4 0x25 VBIL118 VBIL11 VBIL10 VBIL9 VBIL8 0x26 VBIL1512 VBIL15 VBIL14 VBIL13 VBIL12 VBIL0..VBLI15 These 16 2-bit numbers select how the chip should decode the VBI data for each VBI line. For

60 Hz video, VBIL1 through VBIL15 correspond to lines 10 through 24 in the ODD field, and

lines 273 through 286 in the EVEN filed for NTSC (refer to NTSC line numbering convention). For 50 Hz video, VBIL1 corresponds to line 7 in the ODD field, and line 320 in the EVEN field. VBIL0 is used for all other lines not covered by VBIL1 through VBIL15. 0 Decode normal video.* 1 Decode Closed Caption data. 2 Decode Teletext data. 3 Decode WSS data.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 73 OF 96Modified on May/04/2000 Teletext Frame Alignment Pattern Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x27 TTFRAM TTFRAM[7:0] TTFRAM[7:0] User programmable Teletext frame alignment pattern. UV Offset Adjustment Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x29 UVOFFH TSTCLC TSTCGN 0 TSTCFR UOFFST[5:4] VOFFST[5:4] 0x2A UVOFFL UOFFST[3:0] VOFFST[3:0] VOFFST[5:0], UOFFST[5:0] These two 6-bit 2’s compliment values are for offset adjustment to the U and V components of the chroma data. The resolution is 1/4 LSB of the 8-bit U and V. TSTCFR Chroma frequency tracking control. 0 Chroma frequency tracking is enabled.* 1 Chroma frequency tracking is open loop. TSTCGN Chroma gain control. 0 Chroma gain tracks input.* 1 Chroma gain is controlled by SAT only. TSTCLC Cloche filter bypass. 0 Cloche filter is enabled for SECAM input.* 1 DC bypass of the cloche filter.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 74 OF 96Modified on May/04/2000 U Component Gain Adjustment Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x2B UGAIN UGAIN[7:0] UGAIN[7:0] U component gain adjustment. The nominal value is 0. V Component Gain Adjustment Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x2C VGAIN VGAIN[7:0] VGAIN[7:0] V component gain adjustment. The nominal value is 0. VAV Begin Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x2D VAVB VAVB[6:1] VAVOD0 VAVEV0 VAVEV0 The LSB for VAVB and VAVE for the even field. VAVOD0 The LSB for VAVB and VAVE for the odd field. VAVB[6:1] The 6 MSB’s of a 7-bit unsigned number which defines the start of VAV. The value “0” corresponds to line 4. VAV End Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x2E VAVE VAVE[8:1] VAVE[8:1] The 8 MSB’s of a 9-bit unsigned number which defines the end of VAV. The value “0” corresponds to line 4.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 75 OF 96Modified on May/04/2000 Chroma Tracking Control Register Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x2F CTRACK 0 0 DMCTL[1:0] CGTC[1:0] CFTC[1:0] CFTC[1:0] Chroma frequency tracking time constant. 0 Slower.* 1 Slow. 2 Fast. 3 Faster. CGTC[1:0] Chroma gain tracking time constant. 0 Slower.* 1 Slow. 2 Fast. 3 Faster. DMCTL[1:0] Chroma demodulation bypass mode. 0 Chroma demodulation is enabled.* 1 Chroma demodulation is bypassed for digital YCbCr input. 2 Chroma demodulation is bypassed for analog YCbCr input. Cb path is phase delayed by one half of CK2 clock period. 3 Chroma demodulation is bypassed for analog YCbCr input. Cr path is phase delayed by one half of CK2 clock period.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 76 OF 96Modified on May/04/2000 Timing Signal Polarity Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x30 POLCTL EVAVPL VSPL ODDPL HAVPL EHAVPL HS2PL VAVPL HS1PL HS1PL HS1 polarity. 0 Active high.* 1 Active low. VAVPL VAV polarity. 0 Active high.* 1 Active low. HS2PL HS2 polarity. 0 Active high.* 1 Active low.* EHAVPL EHAV polarity. 0 Active high.* 1 Active low. HAVPL HAV polarity. 0 Active high.* 1 Active low. ODDPL ODD polarity (this also affects the F bit in 656 code). 0 Active high.* 1 Active low. VSPL VS polarity (this also affect the V bit in 656 code). 0 Active high.* 1 Active low. EVAVPL EVAV polarity. 0 Active high.* 1 Active low.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 77 OF 96Modified on May/04/2000 Reference Code Insertion Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x31 REFCOD YCRANG 0 0 0 0 0 0 0 YCRANG Digital video output range control. 0 Y and C ranges are limited to 1 - 254; R, G, and B ranges are limited to 1 - 254.*

1 Y range is limited to 16 - 235; C range is limited to 16 - 240; R, G, and B ranges are

limited to 16 - 240. Invalid Y Code Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x32 INVALY INVALY[7:0] INVALY[7:0] User programmed code to be output for Y data when HAV is active but EHAV is inactive. Invalid U Code Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x33 INVALU INVALU[7:0] INVALU[7:0] User programmed code to be output for U data when HAV is active but EHAV is inactive. Invalid V Code Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x34 INVALV INVALV[7:0] INVALV[7:0] User programmed code to be output for V data when HAV is active but EHAV is inactive.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 78 OF 96Modified on May/04/2000 Unused Y Code Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x35 UNUSEY UNUSEY[7:0] UNUSEY[7:0] User programmed code to be output for Y data when HAV is inactive. Unused U Code Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x36 UNUSEU UNUSEU[7:0] UNUSEU[7:0] User programmed code to be output for U data when HAV is inactive. Unused V Code Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x37 UNUSEV UNUSEV[7:0] UNUSEV[7:0] User programmed code to be output for V data when HAV is inactive.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 79 OF 96Modified on May/04/2000 Extra Control Bits for the S5D0127X01 Version Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x38 EXCTRL 0 ENINCST 0 - AUCPWD 0 0 CLEVEL CLEVEL Programmable CKILL burst level select bit. 0 Burst peak level is 11 IRE.* 1 Burst peak level is 5.5 IRE. AUCPWD Auto chroma ADC power down mode enabled when appropriate input format is selected. 0 Chroma ADC powered down only during entire chip power down mode.* 1 Chroma ADC is power downed when CVBS input or case ‘0’ condition. ENINCST Scaler enable control bit during VBI. 0 Scaler on during VBI interval (defined by VAV).* 1 Scaler off during VBI interval.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 80 OF 96Modified on May/04/2000 Tracking Configuration Controls A Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x39 TRACKA STCTRL MAC_DET VCR_DET VCR_LEV[1:0] ATCTRAP VBCTRAP AGCLSB AGCLSB AGC LSB for control of the 9 bit AGC gain value. This bit only write to AGC when AGCFRZ is 0 Write ‘0’ to AGC 9 bit control LSB if AGCFRZ = 1.* 1 Write ‘1’ to AGC 9 bit control LSB if AGCFRZ = 1. VBCTRAP Chroma trap enabled during the VBI. 0 Chroma trap is controlled by CTRAP only.* 1 Chroma trap enabled during VBI. ATCTRAP Auto Chroma Trap on luma path when VCR input is detected. 0 Chroma trap is controlled by CTRAP only.* 1 If VCR type input is detected, then CTRAP is enabled. VCR_LEV Set the Fh variation from nominal for detection of VCR type input. 0 50 PPM.* 1 100 PPM. 2 200 PPM. 3 400 PPM. VCR_DET Status bit. Detect input that is not SCH locked such as consumer type VCR (Read only). 0 SCH locked video. 1 Color burst not locked to Fh (VCR). MAC_DET Status bit. Macrovision Encoded Data detected as input video source (Read only). 0 Standard video detected. 1 Macrovision Encoded data detected. STCTRL State machine transition control. 0 Normal state machine transitions.* 1 Steady state sync level removed as condition for lock.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 81 OF 96Modified on May/04/2000 VBI Control Register B Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x3A VBICTLB VBISWAP TT_SYS[1:0] VBIMID NEW_CC CC_OVFL YOFFENB COFFENB COFFENB Disable control for the C-path clamp control. 0 C-path clamp works as normal.* 1 C-path clamp disabled. YOFFENB Disable control for the Y-path clamp control.* 0 Y-path clamp works as normal.* 1 Y-path clamp disabled. CC_OVFL Defines when the current CCDAT1,2 data has over written previous data that was not read. (Read Only) 0 Current data has not generated an overflow condition. 1 Current data as written over data that was not read. NEW_CC Defines when new Closed Caption data is ready for reading from the CCDAT1,2 bytes. (Read Only) 0 Current data in CCDAT1,2 has already been read. 1 Current data in CCDAT1,2 is new. VBIMID Changes function of WSS enable (per line bases during VBI) to a raw CVBS enable. 0 When VBIL(0-15) = 3, current line is enabled for WSS slicing.* 1 When VBIL(0-15) = 3, current line is enabled for raw ADC output. TT_SYS Select Teletext input system when auto detect is not possible. 0 Auto Teletext Select.* 1 Teletext System B. 2 Teletext System C. 3 Teletext System D. VBISWAP Reverse the bit order for data output from the closed caption or Teletext slicer. 0 Same as S5D0124D01 -- First bit sliced is located in MSB position.* 1 First bit sliced (in time) is located in LSB position.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 82 OF 96Modified on May/04/2000 Tracking Configuration Controls B Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x3B TRACKB ALT656 VBI_PH VBI_FR PH_CTRL VNOISCT AGC_LPG[1:0] AGC_LKG AGC_LKG AGC gain tracking loop time constant for initial tracking mode. 0 Same as steady state time constant.* 1 2X faster than selected steady state time constant. AGC_LPG AGC gain steady state tracking loop time constant. 0 Fastest.* 1 Fast. 2 Slow. 3 Slowest. VNOISCT Vertical sync noise control enable. 0 Vertical sync adjusts with all sync phase changes.* 1 Vertical sync large phase errors must occur for 4 lines to activate a phase change. PH_CTRL Controls phase detector response. 0 Syncs after the “0” point reference have priority.* 1 Syncs prior to “0” point reference have priority. VBI_FR Disables frequency compensation for VCR head switch lines only. 0 Frequency tracking independent of this control.* 1 Frequency tracking disabled for VCR head switch lines. VBI_PH Enables phase compensation for VCR head switch lines only. 0 Phase tracking independent of this control.* 1 Phase tracking enabled for VCR head switch lines only. ALT656 Alternate 656 Vertical blank location for 50 Hz video. 0 Vertical blank size per the ITU 656 Specification (ends at 656 digital line 23).* 1 Vertical blank size same as 60 Hz (ends at 656 digital line (50 Hz) 6).

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 83 OF 96Modified on May/04/2000 RTC Genlock output signal control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x3C RTC RTC_DTO RTC_PID 0 TDMOD 0 0 0 0 TDMOD Test bit for chroma demodulation mode. 0 Normal operation.* 1 Test mode. RTC_PID Polarity control for PAL ID transferred within the RTC data stream. 0 Same polarity as default PID pin.* 1 Inverted polarity. RTC_DTO Enables a DTO reset inside the S5D0127X01 and sends a DTO reset within the RTC data stream. Function is activated on the rising edge of RTC_DTO. 0 Function disabled.* 1 Function enabled one time when set to 1.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 84 OF 96Modified on May/04/2000 Command Register E Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x3D CMDE ODFST VSALG HCORE[1:0] CHIPREVID CHIPREVID Four additional bits for determination of current Revision and differentiation from the S5D0124D01. 0 S5D0124D01. HCORE Luma path horizontal coring. Noise limiter for high frequency portion of luma. 0 Coring function is disabled.* 1 1 bit of coring. 2 2 bits of coring. 3 4 bits of coring. VSALG Vertical scaling line dropping algorithm.

0 Vertical scaling drops the same lines in the Odd and Even fields -- good for fast

motion video.* 1 Vertical scaling drops lines based on the final de-interlaced video. This is a better vertical scaling but may be sensitive to fast motion video. ODFST Alternate the first scaling line between Odd and Even fields. 0 Even field is the first scaled field.* 1 Odd field is the first scaled field.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 85 OF 96Modified on May/04/2000 VS Delay Control Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x3E VSDEL TR_MS NOVIDC VSDEL[5:0] VSDEL[5:0] When the chip is programmed for digital video input operation, this register provides an offset for the internal line counter to align with input video (VS can be either from the VS pin or from embedded timing code). The register content is unsigned. NOVIDC Allows NOVID bit to be output to PORTB (pin 24). 0 Normal operation.* 1 The NOVID bit is output to PORTB if DATAB[2:0]=1 and DIRB=1. TR_MS Enable alternative initial tracking mode state machine. 0 Normal operation - Horizontal tracking mode is controlled by the HFSEL[1:0] bits.* 1 Variable tracking modes during locking time.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 86 OF 96Modified on May/04/2000 Command Register F Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x3F CMDF CTRAPFSC VIPMODE EVAVY UVDLEN UVDLSL REGUD TASKB CBWI CBWI Chroma bandwidth increase. This function should be used for digital video input mode only. 0 Normal chroma bandwidth.* 1 Increased chroma bandwidth. TASKB Select between task A and B as described in “VIP Specification V. 1.0”. 0 Select CCIR 656 timing codes (T-bit is always 1).* 1 Select between task A and B when VBI data is output. If active video is output, T-bit is set to 1(task A). If VBI data is output, T-bit is set to 0 (task B). REGUD Control register update control. 0 Registers are updated immediately after being written to.*

1 The following registers and register bits are updated only during the start of vertical

sync after they are written to: Index 0x02, indices 0x17 through 0x1D, bit 0 of index 0x04, bits [2:0] and [6:4] of index 0x0E. UVDLSL U or V delay control when UVDLEN is set to 1. 0 V is delayed by 1 CK period.* 1 U is delayed by 1 CK period. UVDLEN Enable the function of UVDLSL. 0 UVDLSL is disabled.* 1 UVDLSL is enabled. EVAVY Control the output of INVALY, INVALU, and INVALV codes when EVAV is inactive. 0 Output of these codes are not affected by EVAV.*

1 These codes are output when EVAV is inactive (line is being dropped by the vertical

scaler). VIPMODE Allows transfer of hardware sliced VBI data as ancillary data during the following line’s horizontal blanking period. 0 Standard S5D0124D01 original sliced VBI data transfer.* 1 Optional ancillary sliced VBI data transfer. CTRAPFSC Enable chroma trap location based on Fsc frequency instead of field rate. 0 Chroma trap based on field rate (same as S5D0124D01).* 1 Chroma trap based on detected Fsc frequency.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 87 OF 96Modified on May/04/2000 Gamma Base Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x40 GAMMA0 GAMMA0[7:0] 0x41 GAMMA1 GAMMA1[7:0] : : : : : : 0x5F GAMMA31 GAMMA31[7:0] GAMMA0 -GAMMA31 Gamma correction base. The desired output for 8*N, where N = 0, .., 31, is programmed into GAMMAN. Note that data written into these addresses are simultaneously written into addresses 0xC0 through 0xDF. Gamma Correction Delta Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x60 GAMMAD0 - - GAMMAD0[5:0] 0x61 GAMMAD1 - - GAMMAD1[5:0] : : : : : : : : : : 0x7F GAMMAD31 - - GAMMAD31[5:0] GAMMAD0 ..GAMMAD31 The Nth location of the 32 locations is programmed with a 6-bit unsigned number which represents the gamma correction delta for the gamma bases N and N + 1. The last location will contain the gamma correction delta for gamma base 31 and presumed base 32 which has the value of 256. Note that data written into these addresses are simultaneously written into addresses 0xE0 through 0xFF.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 88 OF 96Modified on May/04/2000 U/V Gamma Base Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0xC0 GAMUV0 GAMUV0[7:0] 0xC1 GAMUV1 GAMUV1[7:0] : : : : : : 0xDF GAMUV31 GAMUV31[7:0] GAMUV0 -GAMUV31 U and V gamma correction base. The desired output for 8*N, where N = 0, .., 31, is programmed into GAMUVN. U/V Gamma Correction Delta Index Mnemonic bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0xE0 GAMUVD0 - - GAMUVD0[5:0] 0xE1 GAMUVD1 - - GAMUVD1[5:0] : : : : : : : : : : 0xFF GAMUVD31 - - GAMUVD31[5:0] GAMUVD0 ..GAMUVD31 U and V gamma correction delta. The Nth location of the 32 locations is programmed with a 6-bit unsigned number which represents the gamma correction delta for the gamma bases N and N + 1. The last location will contain the gamma correction delta for gamma base 31 and presumed base 32 which has the value of 256.

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 89 OF 96Modified on May/04/2000 ABSOLUTE MAXIMUM RATINGS Notes: 1.Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. 2.Functional operation under any of these conditions is not implied. 3.Applied voltage must be current limited to a specified range. OPERATING CONDITIONS Characteristics Symbol Value Units 5-V supply voltage (measured to VSS) VDD -0.5 to + 7.0 V 3.3-V supply voltage (measured to VSS) VDD3 -0.5 to + 4.5 V Voltage on any digital pin VPIN -0.5 to (VDD+0.5) V Ambient operating temperature (case) TA -35 to + 100 °C Storage temperature TS -65 to + 150 °C Junction temperature TJ 150 °C Vapor phase soldering (1 min.) Tvsol 220 °C Characteristics Symbol Min Typ Max Units 5-V supply voltage (measured to VSS) VDD5 4.75 5.0 5.25 V 3.3-V supply voltage (measured to VSS) VDD3 3.0 3.3 3.6 V Ambient operating temperature, still air TA -20 70 °C

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 90 OF 96Modified on May/04/2000

ELECTRICAL CHARACTERISTICS

Characteristics Symbol Min Typ Max Units Supply +5V (VDD, VDDA, VDDA1), normal operation IDD5 150 mA +3.3V (VDD3), normal operation IDD3 141 mA +5V (VDD, VDDA, VDDA1), power down mode IDD5 90 mA +3.3V (VDD3), power down mode IDD3 5 mA Analog Characteristics Integral linearity error (AGC/ADC only) EI-ADC 1.0 3.0 lsb Differential linearity error (AGC/ADC only) ED-ADC 0.5 1.5 lsb Total harmonic distortion (4 MHz full scale) THD 54 dB Signal to noise ratio (4 MHz full scale) SNR 42 dB Analog bandwidth (50 IRE to 3 dB point) BW 4 MHz Input voltage range (peak-peak) 100 IRE input VI(PP) 0.5 1.5 Vpp Input resistance AY0-AY2,AC0-AC2 RIN 200 kΩ Input capacitance for analog video inputs CIN 10 pF Charge current for offset control IOFF ±4 µA Cross talk between analog inputs a -42 -50 dB Video Performance Luminance frequency response (maximum variation to 4.2 MHz - multi burst) FLUMA 1.5 dB Differential gain - complete chip (Modulated 40 IRE ramp) DG 1.5 % Differential phase - complete chip (Modulated

40 IRE ramp)

DP 1.0 degree Chrominance frequency response (3 dB point) - CBWR=0/1 FCHROMA 800/500 kHz Chroma nonlinear gain distortion (NTC-7 Combination) CNGD 1 % Chroma nonlinear phase distortion (NTC-7 Combination) CNPD 1.25 degree Chroma to luma intermodulation (NTC-7 Combination) CLI 1 IRE Chroma luma gain equality (NTC-7 Composite) DELCL ±20 ns Chroma luma delay equality (NTC-7 Composite)AMPCL 98-101 % Noise level for unified weighting 10 kHz-5 MHz (100 IRE unmodulated ramp) NLUMA -58 dB Chroma AM noise (red field) NCAM -60 dB Chroma PM noise (red field) NCPM -54 dB

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 91 OF 96Modified on May/04/2000 Digital I/O Characteristics Input low voltage (other digital I/O) VIL VSS-0.5 0.8 V Input high voltage (other digital I/O) VIH 2.0 VDD+0.5 V Input low voltage (SCLK,SDAT,RST) VILI2C VSS-0.5 0.3VDD V Input high voltage (SCLK,SDAT,RST) VIHI2C 0.7VDD VDD+0.5 V Input low current (VIN = 0.4 V) IIL -1 µA Input high current(VIN=2.4) IIH -1 µA Digital output low voltage (IOL=3.2mA) VOL 0.4 V Digital output high voltage (IOH=400µA) VOH 2.4 V Digital three-state current IOZ 50 µA Digital output capacitance COUT 7 pF Maximum capacitance load for digital data pins CL-DATA 30 pF Maximum capacitance load for CK and CK2 outputs CL-CK 60 pF Timing Characteristics - Digital Inputs XTALI input pulse width low tpwlX 15 20 ns XTALI input pulse width high tpwhX 15 20 ns Clock and Data Timing Analog video input to digital video output delay tdCHIP 120 CK Pulse width high for CK (KS0112 operates at frequencies from 24.5 MHz to 29 MHz) tpwhCK 15 18.5 22 ns Pulse width high for CK2 tpwhCK2 30 37 44 ns Delay from rising edge of CK to CK2 tCK2 4 ns Delay from rising edge CK to data change (including pins Y0-Y7, C0-C7, HAV, VAV, EHAV, EVAV, HS1, HS2, VS, ODD, PID, SCH) tdD (CK is output) 16 23 ns tdD (CK is input) 14 21 ns Minimum hold time from rising edge of CK for data output) thD 7 ns Delay from falling edge of OEN to data bits in 3-state tzD 20 ns Delay from rising edge OEN to data bits enabled tenD 18 ns Timing Characteristics -IIC Host Interface SCLK clock frequency rSCLK 0 400 kHz Capacitive load for each bus line Cb 400 pF Hold time for START condition thSTA 0.6 µs Setup time for STOP condition tsSTO 0.6 µs Rise and fall times for SCLK and SDAT tR, tF 20 300 ns Characteristics Symbol Min Typ Max Units

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 92 OF 96Modified on May/04/2000 SCLK minimum pulse width low tpwlSCLK 1.3 µs SCLK minimum pulse width high tpwhSCLK 0.6 µs SDAT setup time to rising edge of SCLK tsSDAT 100 ns SDAT hold time from rising edge of SCLK thSDAT 0 ns Note: AC/DC characteristics provided are per design specifications. Characteristics Symbol Min Typ Max Units

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 94 OF 96Modified on May/04/2000 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS XTALI XTALO AY0 AY1 AY2 AC0 AC1 AC2 VRT VRB TEST COMP2 VDDA1 VDDA VDDA VDDA VDDA VDD3 VDD3 VDD VDD3 VDD3 VDD VDD3 VDD3 VCC FE. BEAD 10 µF 0.1 µF 0.1 µF 0.1 µF 22 pF 22 pF To Frame Buffer Controller To Frame Buffer Analog Video Input S5D0127X01 HS2 20 k 57TESTEN 3.3V

S5D0127X01 Data Sheet MULTIMEDIA VIDEO PAGE 95 OF 96Modified on May/04/2000 Package Dimension 100-QFP-1420D Dimensions are in Millimeters #100 (0.83) 20.00±0.20 23.90±0.30 17.90±0.30 14.00±0.20 0.10MAX 0.80±0.20 2.65±0.10 3.00MAX 0.00MIN 0.10MAX 0.15 +0.10-0.05 0~8×

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