S5C7212X01 SAMSUNG | Alldatasheet
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Technical content
TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 INTRODUCTION The S5C7212X01 is a CMOS integrated circuit designed for making various timing pulses for B/W CCD camera.
FEATURES
- Compatible with both EIA and CCIR mode ( EIA : S5F325NW02 / S5F325NU02 CCIR : S5F329PW02 / S5F329PU02 )
- Built in auto iris function (Electronic Exposure)
- Mirror mode timing generation
- Field interlace mode only
- Timing and sync one chip IC
- Oscillation frequency EIA : 19.06992MHz, CCIR : 18.93750MHz APPLICATION
- B/W CCD Camera BLOCK DIAGRAM 48-QFP-0707
ORDERING INFORMATION
S5C7212X01-E0R0 48-QFP-0707 -20 °C − 75 °C High/Low Control 2 3 41 127 8 9 10 11 Shutter Speed ROM Shutter Speed Count Shutter Speed Control or Horizontal ROM F/F GATE2 Vertical ROM F/F GATE11/2 38 37 36 35 30 29 28 27 26 25 2433 CL TS1 TS0 PWR TS2 ϕH4 ϕH3 ϕH1 ϕH2 RG XSUB XV2 XV1 XSG1 XV3 XV4 XSG3 SHP SHD CLP1 CLP2 CLP3 DFDO CLEN WIN MD2 MD1 EE1 EE2 FLD PBLK CSYNC CBLK VD HD
S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD PIN DESCRIPTION No Symbol I/O Description Remark
1 MD2 I CCIR/EIA mode selection * Information (1)
2 MD1 I NORMAL/MIRROR mode selection * Information (1)
3 EE1 I EE mode control input 1 * Information (2)
4 EE2 I EE mode control input 2 * Information (2)
5 VSS1 - Ground
6 VDD1 - +5V
7 FLD O Field separation pulse
8 PBLK O Pre - blanking pulse
9 CSYNC O Composite Sync.pulse
10 CBLK O Composite Blanking pulse
11 VD O Vertical driving pulse
12 HD O Horizontal driving pulse
13 WIN O Window pulse
14 CLEN O 1/2 HD frequency pulse
15 DFDO O 1/2 VD frequency pulse
16 CLP3 O Clamp pulse 3 (Dummy black level)
17 CLP2 O Clamp pulse 2 (Optical black level)
18 CLP1 O Clamp pulse 1 (Optical black level)
19 VSS2 - Ground
20 VDD2 - +5V
21 SHD O Data Sample & Hold pulse
22 SHP O Pre - Charge Sample & Hold pulse
23 VSS3 - Ground
24 XV4 O Vertical transfer clock 4
25 XSG3 O Read out Pulse 3
26 V3 O Vertical transfer clock 3
27 XSG1 O Read out Pulse 1
28 XV1 O Vertical transfer clock 1
29 XV2 O Vertical transfer clock 2
30 XSUB O Shutter speed control for auto iris
31 VDD3 - +5V
32 VSS4 - Ground
TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 Information 1) MD2 and MD1 mode selection ( Pull - down ) Information 2 ) EE2 and EE1 shutter speed mode selection ( Pull - up ) No Symbol I/O Description Remark 33 ϕRG O Reset gate pulse
34 VDD4 - +5V
35 ϕH2 O Horizontal transfer pulse 2 ( Mirror mode) 36 ϕH1 O Horizontal transfer pulse 1 ( Normal mode’H1’) 37 ϕH3 O Horizontal transfer pulse 3 ( Normal mode’H2’) 38 ϕH4 O Horizontal transfer pulse 4 ( Mirror mode )
39 VSS5 - Ground
40 X1 I Oscillation clock Input
EIA : 19,069928MHz CCIR : 18.93750MHz
41 X2 O Oscillation clock Output
42 VDD5 O +5V
43 CL O 1/2 Oscillation clock
EIA : 9.53496MHz CCIR : 9.46875MHz
44 VSS6 - Ground
45 TS2 I Test Input 2
46 TS1 I Test Input 1
47 TS0 I Test Input 0
48 PWR - Power On Reset
L L EIA NORMAL H EIA MIRROR H L CCIR NORMAL H CCIR MIRROR EE2 EE1 MODE L L SHUTTER SPEED STOP H SHUTTER SPEED UP H L SHUTTER SPEED DOWN H SHUTTER SPEED STOP
S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V DD =5V, Ta=25 °C, unless otherwise specified) Characteristics Symbol Value Unit Supply Voltage V CC 7 V Input Voltage V I V SS -0.5 − V DD +0.5 V Output Voltage V O V SS -0.5 − V DD +0.5 V Operating Temperature T OPR -20 − +75 °C Storage Temperature T STG -55 − +150 °C Characteristics Symbol Test Condition Min Typ Max Unit Supply Voltage V DD - 4.75 5.0 5.25 V Input Voltage 2 V IH - 0.7V DD - - V V IL - - - 0.3V DD V Output Voltage 1 V OH1 IOH1 = -2mA V DD -0.5 - - V V OL1 IOL1 = 4mA - - 0.6 V Output Voltage 2 V OH2 IOH2 = -4mA V DD -0.5 - - V (CL, RG, SHP, SHD) V OL2 IOL2 = 8mA - - 0.6 V Output Voltage 3 V OH3 IOH3 = -8mA V DD -0.5 - - V (H1, H2, H3, H4) V OL3 IOL3 = 8mA - - 0.6 V
TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 AC CHARACTERISTICS PULSES twh twl tr tf Unit XSG1, XSG3 2.3 2.5 0.5 0.5 us XV1, XV2, XV3, XV4 0.015 0.24 us H1, H2, H3, H4 26 32 26 32 11 12 11 12 ns RG 11 13 51 5 5 ns XSUB 1.5 2.0 0.5 0.5 us SHP, SHD, CLP1, CLP2, CLP3, DFD0, CLEN, WIN, HD, VD, CBLK, CSYNC, FLD 13 14 16 13 14 16 ns twh tr tf twl 0.9V DD 0.1V DD10% 90%
S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD OPERATING PRINCIPLES & METHODS POWER ON RESET S5C7212X01 has two reset methods. The one is power on reset and the other is normal reset. When user wants to use power on reset, which generates an automatic reset signal that is needed to initialize the S5C7212X01 internal system when power is on, user should connect the 1000pF capacitor to the PWR ( pin 48 ) terminal. Power on reset system has an internal 100Kohm pull up resister. So, user can control reset signal timing when user changes the value of the capacitor, which is connected to the PWR terminal. When user wants to use normal reset, user should remove the capacitor from the PWR terminal, and supply the reset signal to the PWR terminal. When using the u-Com system, the reset signal can be supplied three times, and times of 1 signal should be larger than four times of CL clock. 48 48 840ns 1000pF RESET SIGNAL Fig. 1 POWER ON RESET Fig. 2 NORMAL RESET 2.4 ~ 2.6 V KS7212KS7212 S5C7212X01S5C7212X01
TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 APPLICATION CIRCUIT ( EIA , NORMAL MODE ) * Application circuit for normal mode EIA : 19.06992MHz CCIR: 18.93750MHz V DD V DD TO CCD TO VERTICAL DRIVER X-tal 19.0699MHz TO SIGNAL PROCESSOR KS7212 252627282930313233343536 1 2 3 4 5 6 7 8 9 10 11 12 TIMING & SYNC GEN S5C7212X01 TIMING & SYNC GEN.
S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD HIGH SPEED TIMING RELATIONSHIP PG CCD OUT SHP SHD
TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 CCD VERTICAL DRIVING PULSE TIMING DIAGRAM 1.1uS 2.0uS 2.5uS39.5uS 2.5uS43.5uS HD XSG1 XSG2 ODD EVEN
S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD HORIZONTAL TIMING CHART FOR EIA 6.36 10.76 4.89 1.47 2.45 26.89 4.86 Unit : us HD HSYNC EQSYNC VSYNC ODD VD EVEN VD
TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 HORIZONTAL TIMING CHART FOR CCIR MODE 6.41 11.70 4.93 1.48 2.47 27.07 Unit : us HD HSYNC EQSYNC VSYNC ODD VD EVEN VD
S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD HORIZONTAL TIMING CHART FOR MIRROR EIA MODE 1/2H 10.76 2.45 4.86 Unit : us HD HSYNC VSYNC ODD VD CLP1 CLP2 CLP3 EVEN VD
TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 HORIZONTAL TIMING CHART FOR MIRROR CCIR MODE 6.41 11.70 4.93 Unit : us HD EQSYNC VSYNC ODD VD 2.745 CLP1 CLP2 CLP3
S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD H1, H2, H3, H4, PG, SHP, SHD TIMING CHART AT MIRROR MODE OF CCIR H1, H2, H3, H4, PG, SHP, SHD TIMING CHART AT MIRROR MODE OF CCIR OSC1 PG SHP SHD
TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 EIA VERTICAL TIMING CHART EIA VERTICAL TIMING CHART FIELD E FIELD O 20H 80H HD VD CSYNC CBLK FLD WIN FIELD O FIELD E 20H 80.5H HD VD CSYNC CBLK FLD WIN
S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD CCIR VERTICAL TIMING CHART CCIR VERTICAL TIMING CHART FIELD E FIELD O 7.5H 25H 97H HD VD CSYNC CBLK FLD WIN FIELD O FIELD E 7.5H 25H 96.5H HD VD CSYNC CBLK FLD WIN
TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 VERTICAL TIMING CHART FOR EIA 5 2 0 5 2 5 1 0 1 5 2 0 2 5 2 6 0 2 6 5 2 7 0 2 7 5 2 8 0 2 8 5 2 9 0 491 492 492 493 FLD VD BLK HD XSG1 XSG2 CCD OUT CLP1 CLP2 CLP3 PBLK VERTICAL TIMING CHART FOR EIA 4 6 42 6 8 3 5 1 3 5 742 42 6 53 1 3 5
S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD VERTICAL TIMING CHART FOR CCIR 6 2 0 6 2 5 1 0 1 5 2 0 2 5 3 1 0 3 1 5 3 2 0 3 2 5 3 3 0 340 582 581 582 583 FLD VD BLK HD XSG1 XSG2 CCD OUT CLP1 1 3 5 1 3 5 7 CLP2 CLP3 PBLK VERTICAL TIMING CHART FOR CCIR 335 1 3 5 42 6 42 6 1 3 5 4 6 42 6 8
S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD PACKAGE DIMENSION 0~8 0.13 + 0.10 - 0.05 0.10 MAX0.50 + 0.20
0.00 MIN
1.40 + 0.10
1.60 MAX
7.00 + 0.20 ( 0.75 ) 0.18 + 0.10
0.10 MAX
0.50 # 48 # 1 7.00 + 0.20 9.00 + 0.30 9.00 + 0.30 48-QFP-0707 unit : mm