S5335QFAAB

S5335 AMCC | Alldatasheet

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Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 S5335 PCI Bus Controller, 3.3V Data Sheet S5335 PCI BUS CONTROLLER (MATCH MAKER)

S5335 – PCI Bus Controller, 3.3V DS1657 AMCC Confidential and Proprietary Revision 5.01 – November 30, 2005 Data Sheet

FEATURES

• PCI 2.1 Compliant Master/Slave Device
• Full 132 Mbytes/sec Transfer Rate
• PCI Bus Operation DC to 33 MHz
• 8/16/32 Bit Add-On User Bus
• 3.3V Power Supply
• 5V Tolerant I/Os
• Four Definable Pass-Thru Data Channels
• Two 32 Byte Internal FIFOs w/DMA
• Synchronous Add-On Bus Operation
• Mail Box Registers w/Byte Level Status
• Direct Mail Box Data Strobe/Interrupts
• Direct PCI & Add-On Interrupt Pins
• Optional Non-Volatile Memory Boot Loading
• Optional Expansion BIOS/POST Code
• 176 Pin LQFP
• Environmental Friendly Lead-Free Package Option

APPLICATIONS

• High Speed Networking
• Digital Video Applications
• I/O Communications Ports
• High Speed Data Input/Output
• Multimedia Communications
• Memory Interfaces
• High Speed Data Acquisition
• Data Encryption/Decryption
• Intel i960 Interface
• General Purpose PCI Interfacing

DESCRIPTION

The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing system speed and expansion capabili- ties. The PCI Local bus moves high speed peripherals from the I/O bus and places them closer to the sys- tem’s processor bus, providing faster data transfers between the processor and peripherals. The PCI Local bus also addresses the industry’s need for a bus stan- dard which is not directly dependent on the speed, size and type of system processor. It represents the first microprocessor independent bus offering perfor- mance more than adequate for the most demanding applications such as full-motion video. Applied Micro Circuits Corporation (AMCC), the pre- mier supplier of single ch ip solutions, has developed the S5335 to solve the problem of interfacing applica- tions to the PCI Lo cal bus while offering support for newer PCI chipsets and operating systems. The S5335 is a powerful and flexible PCI controller sup- porting several levels of interface sophistication. At the lowest level, it can serve simply as a PCI bus Target with modest transfer requirements. For high-perfor- mance applications, the S5335 can become a Bus Master to attain the PCI Local bus peak transfer capa- bility of 132 MBytes/sec. The S5335 was designed for 3.3V environment but its inputs/outputs are tolerant to 5V signaling. Figure 1. S5335 Block Diagram

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 3 Data Sheet TABLE OF CONTENTS

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 4 Data Sheet

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 5 Data Sheet

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 6 Data Sheet

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 7 Data Sheet

not debugging the PCI interface. expansion BIOS or POST code capability. loading setup information on system power-up. Figure 2. S5335 Pinout register groups and the optional non-volatile interface. group of Configuration Registers for the host system. the S5335 PCI Configuration Registers.

operation and communicates with the PCI Local bus. Registers and Status/Control registers. Table 1. PCI Configuration Registers (Continued) Table 2. PCI Operation Registers

disassembling of 32-bit data. to the byte wide at power up. Table 3. Add-On Bus Operation Registers

Figure 3. PCI and Add-On Local Bus Signal Diagram

Figure 4. PCI Pass-Thru Operation Diagram that is dedicated to transferring data to the other bus. are available for 8-bit or 16-bit Add-Ons. FIFO must be before it requests the PCI Local bus.

Figure 5. FIFO PCI Bus Mastering Operation Diagram

present, the signal is active high. Figure 6. S5335 Signal Pins in Input is a standard input-only signal. out Totem Pole Output is a standard active driver. t/s Tri-State ® is a bidirectional, tristate input/output pin. inactive state until another agent drives it, and must be provided by the central source. o/d Open Drain allows multiple devices to share as a wire-OR.

Table 4. Address and Data Pins — PCI Local Bus control signals IRDY# and TRDY# are both asserted. significant byte) and C/BE[3]# enabling byte 3 (most significant byte).

0000 I n t e r r u p t A c k n o w l e d g e

0010 I / O R E A D

0100 R e s e r v e d

0101 R e s e r v e d

1000 R e s e r v e d

1001 R e s e r v e d

Table 5. System Pins — PCI Local Bus bus interface output signals are not driven (tri-stated), and open drain signals such as SERR# are floated. Table 6. Interface Control Pins — PCI Bus Signal to signify the final data phase. on the AD[31:00] pins. Wait states occur until both TRDY# and IRDY# are asserted together. get by one master at a time. The S5335 cannot lock a target when it is a master. mands are valid. For bus masters, it indicates whether any device has decoded the current bus cycle. Table 7. Arbitration Pins (Bus Masters Only) — PCI Local Bus and each master has its own REQ#. nifies that access to the bus has been granted.

Table 8. Error Reporting Pins — PCI Local Bus mands, or any error condition having a catastrophic system impact. Table 9. Interrupt Pin — PCI Local Bus for any single function device requiring an interrupt capability.

Table 10. Serial nv Devices SCL out Serial Clock. This output is intended to drive a tw o-wire Serial Interface and functions as the bus’s master. EEPROMs. This pin is shared with the byte wide interface signal, ERD#. present. When this pin is low, a byte-wide boot device is present. Table 11. Byte-Wide nv Devices pin is shared with the serial external memory interface signal, SCL. EQ7 become reconfigured to provide signal pins for bus mastering control from the Add-On interface.

mode pins, and general system pins. Table 12. Register Access Pins are used. DQ[31:0] have internal 50k Ohm pull-up resistors. within the controller is desired for a given read or write cycle, as shown in the table below. for write operations they serve as a required enable to perform the modification of each byte lane. BE[2:0]# have internal 50k Ohm pull-up resistors.

ADR[6:2] and the byte enables, BE[3:0]#. ADR[6:2] and the byte enables BE[3:0]#. signal ADR1. MODE has an internal 50k Ohm pull-up resistor. Table 13. FIFO Access Pins transfers with the Add-On system. WRFIFO# has an internal 50k Ohm pull-up resistor. WRFULL out Write FIFO full. This pin indicates whether the Add-On-to-PCI bus FIFO is able to accept more data. output from this pin can be used to represent a DMA write (Add-On to-PCI FIFO) request. RDEMPTY out Read FIFO Empty. This pin indicates whether the read FIFO (PCI-to-Add-On FIFO) contains data. Table 14. Pass-Thru Interface Pins must be read from or written to the Pass-Thru Data Register. sponds to Base Address Register 1, a value of 01 for Base Address Register 2, and so on. Table 12. Register Access Pins (Continued)

operation. They are valid during the presence of signal PTATN# active. signal is valid only when PTATN# is active. Table 15. System Pins software from the PCI host interface. behavioral characteristics of the PCI clock (i.e., DC-to-33 MHz capability). of activity within the PCI controller. RSVD in Reserved. This pin must be left open at all times. Table 14. Pass-Thru Interface Pins (Continued)

vides an explanation of its intended usage. Table 16. Configuration Registers

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 28 Data Sheet PCI Configuration Space Header BIST 31 23 24 16 15 8 7 LATENCY TIMER INTERRUPT PINMIN_GNTMAX_LAT INTERRUPT LINE EXPANSION ROM BASE ADDRESS HEADER TYPE = 0 BASE ADDRESS REGISTER #0 BASE ADDRESS REGISTER #1 BASE ADDRESS REGISTER #2 BASE ADDRESS REGISTER #3 BASE ADDRESS REGISTER #4 BASE ADDRESS REGISTER #5 RESERVED = 0's RESERVED = 0's RESERVED = 0's RESERVED = 0's REV ID CACHE LINE SIZE VENDOR ID COMMAND DEVICE ID CLASS CODE STATUS LEGEND Note: Some registers are a combination of the above. See individual sections for full description. EPROM IS DATA SOURCE (READ ONLY) CONTROL FUNCTION EPROM INITIALIZED RAM (CAN BE ALTERED FROM PCI PORT) EPROM INITIALIZED RAM (CAN BE ALTERED FROM ADD-ON PORT) HARD-WIRED TO ZEROES

dor identification number for this field. Figure 7. Vendor Identification Register Table 17. Vendor Identification Register 15:0 Vendor Identification Number: This is a 16 bit-value assigned to AMCC.

device identification number for this field. Figure 8. Device Identification Register Table 18. Device Identification Register

device; those which are not used are hardwired to 0. Figure 9. PCI Command Register

Table 19. PCI Command Register 15:10 Reserved. Equals all 0’s. never uses stepping, it is hardwired to 0. solely for PCI-based VGA devices. S5335 controller does not support this command when operated as a master and therefore it is hardwired to 0. 3 Special Cycle Enable. Devices which are capable of monitoring special cycles can do so when this bit is set to 1. The S5335 controller does not monitor (or generate) special cycles and this bit is hardwired to 0. initialized to 0 upon the assertion of signal pin RESET#.

device; those which are not used are hardwired to 0. Figure 10. PCI Status Register

Table 20. PCI Status Register Command Register Bit 6. This bit may be cleared by writing a 1 to this location. rently addressed target. This bit can be reset by writing a 1 to this location. reset by writing a 1 to this location. as the master. The Parity Error Enable bit (D6 of the Command Register) must be set in order for this bit to be set. Once set, it can only be cleared by either writing a 1 to this location or by the assertion of the signal RESET#. 6:0 Reserved. Equal all 0’s.

from the PCI interface have no effect on this register. valid) so that another value may be used. Figure 11. Revision Identification Register Table 21. Revision Identification Register

the defined class codes described in Table 22 below. base codes 00h through 0Ch, respectively. Figure 12. Class Code Register Table 22. Defined Base Class Codes

Table 23. Base Class Code 00h: Early, Pre-2.0 Specification Devices Table 24. Base Class Code 01h: Mass Storage Controllers Table 25. Base Class Code 02h: Network Controllers Table 26. Base Class Code 03h: Display Controllers Table 27. Base Class Code 04h: Multimedia Devices Table 28. Base Class Code 05h: Memory Controllers

Table 29. Base Class Code 06h: Bridge Devices Table 30. Base Class Code 07h: Simple Communications Controllers Table 31. Base Class Code 08h: Base System Peripherals Table 32. Base Class Code 09h: Input Devices

Table 33. Base Class Code 0Ah: Docking Stations Table 34. Base Class Code 0Bh: Processors Table 35. Base Class Code 0Ch: Serial Bus Controllers

cache line size in double-word (64-bit) increments. transfers that cross a line boundary. Figure 13. Cache Line Size Register

the use of the bus for data transfers. Figure 14. Latency Timer Register

Figure 15. Header Type Register

implementation of custom, user-specific diagnostics. This register has four fields as depicted in Figure 16. Figure 16. Built-In Self Test Register Table 36. Built-In Self-Test Register should be returned if this self test feature is not desired. This field is read only from the PCI interface. ification requires that this bit be cleared within 2 seconds after being set, or the device will be failed. 5:4 Reserved. These bits are reserved. This field will always return zeros. BIST field (bit 6) changes from 1 to 0. An all-zero value for the completion code indicates successful completion.

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 44 Data Sheet Base Address Registers (BADR) The base address registers provide a mechanism for assigning memory or I/O space for the Add-On func- tion. The actual location(s) the Add-On function is to respond to is determined by first interrogating these registers to ascertain the size or space desired, and then writing the high-order field of each register to place it physically in the system’s address space. Bit zero of each field is used to select whether the space required is to be decoded as memory (bit 0 = 0) or I/O (bit 0 = 1). Since this PCI controller has 16 DWORDs of internal operating registers, the Base Address Reg- ister at offset 10h is assigned to them. The remaining five base address registers can only be used by boot- loading them from the external nvRAM interface. BADR5 register is not im plemented and will return all 0’s. Determining Base Address Size The address space defined by a given base address register is determined by writing all 1s to a given base address register from the PCI bus and then reading that register back. The number of 0s returned starting from D4 for memory space and D2 for I/O space toward the high-order bits reveals the amount of address space desired. Tables 39 and 40 list the pos- sible returned values and their corresponding size for both memory and I/O, respectively. Included in the table are the nvRAM/EPROM boot values which corre- spond to a given assigned size. A register returning all zeros is disabled. Assigning the Base Address After a base address has been sized as described in the preceding paragraph, the region associated with that base address register (the high order one bits) can physically locate it in memory (or I/O) space. For example, if the fi rst base address register returns FFFFFFC1h indicating an I/O space (D0=1) and is then written with the value 00000300h. This means that the controller’s internal registers can be selected for I/O addresses between 00000300h through 0000033Fh, in this example. The base address value must be on a natural binary boundary for the required size (example 300h, 340h, 380h etc.; 338h would not be allowable). Register Name: Base Address Address Offset: 10h, 14h, 18h, 1Ch, 20h, 24h Power-up value: FFFFFFC1h for offset 10h; 00000000h for all others Boot-load: External nvRAM offset 050h, 54h, 58h, 5Ch, 60h (BADR0-4) Attribute: high bits Read/Write; low bits Read Only Size: 32 bits

Table 37. Base Address Register — Memory (Bit 0 = 0) enabled by the contents sourced from the external boot memory. set to 0. This bit is read only from the PCI interface. 0 0 Region is 32 bits wide and can be located anywhere in 32 bit memory space. 0 1 Region is 32 bits wide and must be mapped below the first MByte of memory space. bits in the base address register are defined as shown in Table 38. Table 38. Base Address Register — I/O (Bit 0 = 1) by the contents sourced from the external boot memory (EPROM or nvRAM). location, bits 31 through 0). base address register have the definition as shown in Figure 18.

1. The two most significant bits define bus width for BADR1:4 in Pass-Thru operation).
2. Bits D3, D2 and D1 may be set to indicate other attributes for the memory space. See text for details.
3. BADR5 register is not implemented and will return all 0’s.

Table 39. Read Response (Memory Assigned) to an All-Ones Write Operation to a Base Address Register

1. BADR5 register is not implemented and will return all 0’s.
2. Base Address Register 0 (at offset) 10h powers up as FFFFFFC1h. This default assignment allows usage without an external boot memory.

Should an EPROM or nvRAM be used, the base address can be boot loaded to become a memory space (FFFFFFC0h or FFFFFFC2h). Table 40. Read Response (I/O Assigned) to an All-Ones write Operation to a Base Address Register

Figure 19. Expansion ROM Base Address Register Table 41. Expansion ROM Base Address Register ter also have the memory decode enabled for this bit to have an effect.

110 Bit

Table 42. Read Response to Expansion ROM Base Address Register (after all-ones written)

may be written by the PCI interface. Figure 20. Interrupt Line Register

Figure 21. Interrupt Pin Register

are possible when an external boot memory is used. Figure 22. Minimum Grant Register

are possible when an external boot memory is used. Figure 23. Maximum Latency Register

communication between the PCI and Add-On buses. Table 43. Operation Registers — PCI Bus

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 56 Data Sheet Outgoing Mailbox Registers (OMB) Register Names: Outgoing Mailboxes 1-4 These four DWORD registers provide a method for sending command or parameter data to the Add-On system. PCI bus operations to these regis- ters may be in any width (byte, word, or DWORD). Writing to these regis- ters can be a source for Add-On bus interrupts (if desired) by enabling their interrupt generation through the use of the Add-On’s interrupt con- trol/status register. PCI Address Offset: 00h, 04h, 08h, 0Ch Power-up value: XXXXXXXXh Attribute: Read/Write Size: 32 bits Incoming Mailbox Registers (IMB) Register Names: Incoming Mailboxes 1-4 These four DWORD registers provide a method for receiving user defined data from the Add-On system. PCI bus read operations to these registers may be in any width (byte, word, or DWORD). Only read opera- tions are supported. Reading from these registers can optionally cause an Add-On bus interrupt (if desired) by enabling their interrupt generation through the use of the Add-On’s interrupt control/status register. Mailbox 4, byte 3 only exists as device pins on the S5335 devices when used with a serial nonvolatile memory. PCI Address Offset: 10h, 14h, 18h, 1Ch Power-up value: XXXXXXXXh Attribute: Read Only Size: 32 bits FIFO Register Port (FIFO) Register Name: FIFO Port This location provides access to the bidirectional FIFO. Separate regis- ters are used when reading from or writing to the FIFO. Accordingly, it is not possible to read what was written to this location. The FIFO registers are implicitly involved in all bus master operations and, as such, should not be accessed during active bus master transfers. When operating upon the FIFOs with software program transfers involving word or byte operations, the endian sequence of the FIFO should be established as described under FIFO Endian Conversion Management in order to pre- serve the internal FIFO data ordering and flag management. The FIFO’s fullness may be observed by reading the master control-status register or MCSR register. PCI Address Offset: 20h Power-up value: XXXXXXXXh Attribute: Read/Write Size: 32 bits

the task of PCI bus master data transfers. always be zero when this controller is the bus master. disconnect after the first data phase of this operation. Figure 24. PCI Controlled Bus Master Write Address Register

tion until the transfer count reaches zero. ler are required to begin on a DWORD boundary. Figure 25. PCI Controlled Bus Master Write Transfer Count Register

the task of PCI bus master data transfers. in an Intel 486 or Pentium™ cache line fill sequence. first data phase of this operation. from the Add-On bus instead of the PCI bus. Figure 26. PCI Controlled Bus Master Read Address Register

ler are required to begin on a DWORD boundary. from the Add-On bus instead of the PCI bus. Figure 27. PCI Controlled Bus Master Read Transfer Count Register

bus to the Add-On interface. Figure 28. Mailbox Empty/Full Status Register

Table 44. Mailbox Empty/Full Status Register

• Write Transfer Terminal Count = zero
• Read Transfer Terminal Count = zero
• One of the Outgoing mailboxes (1,2,3 or 4) becomes empty
• One of the Incoming mailboxes (1,2,3 or 4) becomes full.
• Target Abort
• Master Abort

Figure 29. Interrupt Control/Status Register

Figure 30. FIFO Management and Endian Control Byte

0 NO CONVERSION (DEFAULT)

Table 45. Interrupt Control/Status Register 31:24 FIFO and Endian Control. change the state of this bit. data of “zero” will not change the state of this bit. cause this bit to be reset; a write to this bit with the data as “zero” will not change the state of this bit. bit to be reset; a write to this bit with the data of “zero” will not change the state of this bit. reaches zero. This bit is read/write. reaches zero. This bit is read/write. through 8 to produce a PCI interface interrupt. This bit is read/write. [11]b selects mailbox 4. This field is read/write. byte 3. This field is read/write.

bits 3 through 0 to produce a PCI interface interrupt. This bit is read/write. [11]b selects mailbox 4. This field is read/write.

1. This field is read/write.

Table 45. Interrupt Control/Status Register (Continued)

This register provides for overall control of this device.

• Write Priority over Read
• Read Priority over Write
• Write Transfer Enable
• Write master requests on 4 or more FIFO words available (full)
• Read transfer enable
• Read master requests on 4 or more FIFO avail- able (empty)
• Assert reset to Add-On
• Reset Add-On to PCI FIFO flags
• Reset PCI to Add-On FIFO flags
• Reset mailbox empty full status flags
• Write external non-volatile memory The following PCI interface status flags are provided:
• PCI to Add-On FIFO FULL
• PCI to Add-On FIFO has four or more empty locations
• PCI to Add-On FIFO EMPTY
• Add-On to PCI FIFO FULL
• Add-On to PCI FIFO has four or more words loaded
• Add-On to PCI FIFO EMPTY
• PCI to Add-On Transfer Count = Zero
• Add-On to PCI Transfer Count = Zero

Figure 31. Bus Master Control/Status Register

Table 46. Bus Master Control/Status Register

1. The sequence requires that the low-order address, high order address, and then a data byte are loaded in order.

to a 1 before an access can begin, and subsequent accesses must wait for bit D31 to become zero (ready).

0 X X W I n a c t i v e

0 X X R Ready

1 X X R Busy

provide for accurate data retrieval. always produce zeros, this bit is write only. FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFO Four Plus word flag to reset. bit will always produce zeros, this bit is write only. reading of this bit will always produce zeros, this bit is write only. necessary to remove the assertion of reset. This register bit is read/write. sequence for bits 31 through 29 is performed. 15 Enable memory read multiple during S5335 bus mastering mode. a zero to this location will suspend an active transfer. An active transfer is one in which the transfer count is not zero. request the PCI bus if it has at least one vacant FIFO word.

one, this indicates that transfer priorities will alternate equally between read and writes. to this location will suspend an active transfer. An active transfer is one in which the transfer count is not zero. request the PCI bus if it has at least one valid FIFO word. ties will alternate equally between writes and reads. 7 Add-On to PCI Transfer Count Equal Zero (RO). This bit is a one to signify that the write transfer count is all zeros. 6 PCI to Add-On Transfer Count Equals Zero (RO). This bit is a one to signify that the read transfer count is all zeros. 5 Add-On to PCI FIFO Empty. This bit is a one when the Add-On to PCI bus FIFO is completely empty. 3 Add-On to PCI FIFO Full. This bit is a one when the Add-On to PCI bus FIFO is completely full. 2 PCI to Add-On FIFO Empty. This bit is a one wh en the PCI bus to Add-On FIFO is completely empty. 0 PCI to Add-On FIFO Full. This bit is a one when the PCI bus to Add-On FIFO is completely full. Table 46. Bus Master Control/Status Register (Continued)

bus, or to connect with an external FIFO. the Add-On interface registers.

1. See Add-On Initiated Bus Mastering.

Table 47. Operation Registers — Add-On Interface

1 Bus Master Write Address Register

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 71 Data Sheet Add-On Incoming Mailbox Registers (AIMBx) Register Names: Add-On Incoming Mailboxes 1-4 These four DWORD registers provide a method for receiving data, commands, or command parameters from the PCI inter- face. Add-On read operations to these registers may be in any width (byte, word, or DWORD). These registers are read-only. Writes to this address space have no effect. Reading from one of these registers can optionally cause a PCI bus interrupt (if desired) when the PCI interrupt control/status register is prop- erly configured. Add-On Address Offset: 00h, 04h, 08h, 0Ch Power-up value: XXXXXXXXh Attribute: Read Only Size: 32 bits Add-On Outgoing Mailbox Registers (AOMBx) Register Names: Add-On Outgoing Mailboxes 1-4 These four DWORD registers provide a method for sending data, commands, or command parameters or status to the PCI interface. Add-On write operations to these registers may be in any width (byte, word, or DWORD). These registers may also be read. Writing to one of these registers can optionally cause a PCI bus interrupt (if desired) when the PCI interrupt control/sta- tus register is properly configured. Mailbox 4, byte 3 only exists as device pins on the S5335 device when used with a serial nonvolatile memory. This byte is not available if a byte-wide nv memory is used. Add-On Address Offset: 10h, 14h, 18h, 1Ch Power-up value: XXXXXXXXh Attribute: Read/Write Size: 32 bits Add-On FIFO Register Port (AFIFO) Register Name: Add-On FIFO Port This location provides access to the bidirectional FIFO. Separate registers are involved when reading and writing to this location. Accordingly, it is not possible to read what was written to this location. The sequence of filling and emptying this FIFO is established by the PCI interface interrupt con- trol and Status Register. The FIFO’s fullness may be observed by reading the master control/status register or AGCSTS register Additionally, two signal pins are provided which reveal whether data is available (RDEMPTY) or space to write into the FIFO is available (WRFULL). These signals may be used to interface with user supplied DMA logic. Caution must be exercised when using these flags for FIFO transfers involving 64 bit endian conversion since the FIFO must operate on DWORD pairs. Add-On Address Offset: 20h Power-up value: XXXXXXXXh Attribute: Read/Write Size: 32 bits

the task of PCI bus master data transfers. always be zero when this controller is the bus master. disconnect after the first data phase of this operation. Figure 32. Add-On Controlled Bus Master Write Address Register

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 73 Data Sheet Add-On Pass-Thru Address Register (APTA) Register Name: Add-On Pass-Thru Address This register is employed when a response is desired when one of the Base address decode regions is selected during an active PCI bus cycle. When one of the base address decode registers 1-4 encounters a PCI bus cycle which selects the region defined by it, this device latches that current cycle’s active address and asserts the signal PTATN# (Pass-Thru Attention). Wait states are generated on the PCI bus until either data is transferred or the PCI bus cycle is aborted by the initiator. This register provides a method for “live” data (registered) transfers. Intended uses include the emulating of other hard- ware as well as enabling the connection of existing external hardware to interface to the PCI bus through the S5335. Add-On Address Offset: 28h Power-up value: XXXXXXXXh Attribute: Read Only Size: 32 bits Add-On Pass-thru Data Register (APTD) Register Name: Add-On Pass-Thru Data This register, along with APTA described above, is employed when a response is desired should one of the Base address decode regions become selected during an active PCI bus cycle. When one of the base address decode registers 1-4 encounters a PCI bus cycle which selects the region defined by it, the APTA register will contain that current cycle’s active address and the device asserts the signal PTATN# (Pass-Thru ATentioN). Wait states are generated on the PCI bus until this register is read (PCI bus writes) or this reg- ister is written (PCI bus reads). Add-On Address Offset: 2Ch Power-up value: XXXXXXXXh Attribute: Read/Write Size: 32 bits

the task of PCI bus master data transfers. in an Intel 486 or Pentium™ cache line fill sequence. first data phase of this operation. from the Add-On bus instead of the PCI bus. Figure 33. Add-On Controlled Bus Master Read Address Register

Add-On bus to the PCI interface. Figure 34. Add-On Mailbox Empty/Full Status Register

Table 48. Add-On Mailbox Empty/Full Status Register

• One of the Incoming mailboxes (1,2,3 or 4) becomes full.
• One of the Outgoing mailboxes (1,2,3 or 4) becomes empty.
• Built-in self test issued.
• Write Transfer Count = zero
• Read Transfer Count = zero
• Target/Master Abort

Figure 35. Add-On Interrupt Control/Status Register

Table 49. Interrupt Control/Status Register 31:24 Reserved. Always zero. nothing more than the ORing of the interrupt conditions described by bits, 20, 17 and 16 of this register. this bit causes it to be cleared. Writing a zero to this bit does nothing. codes may be passed to the PCI BIST register by writing to the AGCSTS register. bit to be reset; a write to this bit with the data as zero will not change the state of this bit. bit to be reset; a write to this bit with the data as zero will not change the state of this bit. reaches zero. This bit is read/write. reaches zero. This bit is read/write. bits 11 through 8 to produce an Add-On interface interrupt. This bit is read/write. [11]b selects mailbox 4. This field is read/write. byte 3. This field is read/write. fied by bits 3 through 0 to produce an Add-On interface interrupt. This bit is read/write.

[11]b selects mailbox 4. This field is read/write. to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 2, and so on. Table 49. Interrupt Control/Status Register (Continued)

perform software resets of the mailbox and FIFO flags.

• Reset PCI to Add-On FIFO flags
• Reset Add-On to PCI FIFO flags
• Reset mailbox empty full status flags
• Write/read external non-volatile memory. The following status flags are provided to the Add-On:
• Add-On to PCI FIFO FULL
• Add-On to PCI FIFO has four or more empty locations
• Add-On to PCI FIFO EMPTY
• PCI to Add-On FIFO FULL
• PCI to Add-On FIFO has four or more words loaded
• PCI to Add-On FIFO EMPTY

Figure 36. Add-On General Control/Status Register

Table 50. Add-On General Control/Status Register written to a 1 before an access can begin, and subsequent accesses must wait for bit D31 to become zero (ready).

0 X X W Inactive

1 X X R B u s y

vide for accurate data retrieval. transfer counts are ignored. produce zeros, this bit is write only. bit would always produce zeros, this bit is write only. duce zeros, this bit is write only. sequence for bits 31 through 29 is performed. maps with the BIST register bits 3 through 0, respectively. 7 Add-On to PCI Transfer Count Equal Zero (RO). This bit as a one signifies that the write transfer count is all zeros. Only when Add-On initiated bus mastering is enabled.

6 PCI to Add-On Transfer Count Equals Zero (RO). This bit as a one signifies that the read transfer count is all zeros. Only when Add-On initiated bus mastering is enabled. 5 PCI to Add-On FIFO Empty. This bit is a 1 when the PCI to Add-On FIFO is empty. 4 PCI to Add-On FIFO 4+ spaces. This bit is a 1 when there are four or more open spaces in the PCI to Add-On FIFO. 3 PCI to Add-On FIFO Full. This bit is a 1 when the PCI to Add-On FIFO is full. 2 Add-On to PCI FIFO Empty. This bit is a 1 when the Add-On to PCI FIFO is empty. 1 Add-On PCI FIFO 4+ words. This bit is a 1 when there ar e four or more full locations in the Add-On to PCI FIFO. 0 Add-On to PCI FIFO Full. This bit is a 1 when the Add-On to PCI FIFO is full. Table 50. Add-On General Control/Status Register (Continued)

tion until the transfer count reaches zero. ler are required to begin on a DWORD boundary. Figure 37. Add-On Controlled Bus Master Write Transfer Count Register

ler are required to begin on a DWORD boundary. Figure 38. Add-On Controlled Bus Master Read Transfer Count Register

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 85 Data Sheet INITIALIZATION All PCI bus agents and bridges are required to imple- ment PCI Configuration Regi sters. When multiple PCI devices are present, these registers must be unique to each device in the system. The specified PCI proce- dure for uniquely selecting a device’s configuration space involves a dedicated signal, called IDSEL, con- nected to each motherboard PCI bus device and PCI slot. The host executes configurat ion cycles after reset to each device on the PCI bus. The configuration regis- ters provide information on PCI agent operation and memory or I/O space requirements. These allow the PCI BIOS to enable the device and locate it within sys- tem memory or I/O space. After a PCI reset, the S5335 can be configured for a specific application by downloading device setup infor- mation from an external non-volatile memory into the device Configuration Registers. The S5335 can also be used in a default configuration, with no external boot device. When using a non-volatile boot memory to customize operation, 64 bytes are required for S5335 setup infor- mation. The rest of the boot device may be used to implement an Expansion BIOS, if desired. Some of the setup information is used to initialize the S5335 PCI Configuration Registers, other information is not down- loaded into registers, but is used to define S5335 operation (FIFO interface, Pass-Thru operation, etc.). PCI RESET Immediately following the assertion of the PCI RST# signal, the Add-On reset output SYSRST# is asserted. Immediately following the deassertion of RST#, SYSRST# is deasserted. The Add-On reset output may be used to initialize state machines, reset Add-On microprocessors, or reset other Add-On logic devices. All S5335 Operation Registers and Configuration Reg- isters are initialized to their default states at reset. The default values for the Configuration Registers may be overwritten with the contents of an external nv boot memory during device initialization, allowing a custom device configuration. Conf iguration accesses by the host CPU to the S5335 produce PCI bus wait states until one of the following events occurs:

• The S5335 identifies that there is no valid boot memory (and default Configuration Register values are used).
• The S5335 finishes downloading all configura- tion information from a valid boot memory. LOADING FROM BYTE-WIDE NV MEMO- RIES The SNV input on the S5335 indicates what type of external boot-load device is present (if any). If SNV is tied low, a byte-wide nv memory is assumed. In this case, immediately after the PCI bus reset is deas- serted, the address 0040h is presented on the nv memory interface address bus EA[15:0]. Eight PCI clocks later (240 ns at 33 MHz), data is read from the nv memory data bus EQ[7:0] and address 0041h is presented. After an additional eight PCI clocks, data is again read from EQ7:0. If both accesses read are all ones (FFh), it implies an illegal Vendor ID value, and the external nv memory is not valid or not present. In this situation, the AMCC default configuration values are used. If either of the accesses to address 0040h and 0041h contain zeros (not FFh), the next accesses are to loca- tions 0050h, 0051h, 0052h, and 0053h. At these locations, the data must be C0h (or C1h or C2h), FFh, E8h, and 10h, respectively, for the external nv memory to be valid. Once a valid external nv memory has been recognized, it is read, sequentially, from location 0040h to 007Fh. The appropriate data is loaded into the PCI Configuration Registers as described in Chap- ter 4. Some of the boot device data is not downloaded into Configuration Registers, but is used to enable fea- tures and configure S5335 operation. Upon completion of this procedur e, the boot-load sequence terminates and PCI configur ation accesses to the S5335 are acknowledged with the PCI Target Ready (TRDY#) output. Table 51 lists the required nv memory contents for a valid configuration nv memory device.

package size, and economical price. fined as a SCL divide by control pin. This pin should be pulled high. respect to the serial clock. transferred approximately every 0.5 milliseconds. Read accesses may be either random or sequential. Table 51. Valid External Boot Memory Contents space, a value of C2h defines memory space below 1 Mbyte.

memory used to boot-load the S5335 controller. Table 52. PC Compatible Expansion ROM Entry point for INIT function.

may cause a lengthy system delay during initialization. possible, may be unacceptably slow. Byte checksum, location dependent on value for length field at offset 0002h. Table 52. PC Compatible Expansion ROM (Continued) Table 53. PCI Data Structure Signature, the ASCII string ‘PCIR’ where ‘P’ is at offset 0, ‘C’ at offset 1, and so on.

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 92 Data Sheet PCI BUS INTERFACE This section describes the various events which occur on the S5335 PCI bus interface. Since the S5335 con- troller functions as both a target (slave) and an initiator (master), signal timing detail is given for both situa- tions this Section presents the signal relationships involved in performing basic read or write transfers on the PCI bus and also describes the different ways these cycles may complete. PCI BUS TRANSACTIONS Because the PCI bus has multiplexed address/data pins, AD[31:0], each PCI bus transaction consists of two phases: Address and Da ta. An address phase is defined by the clock peri od when the signal FRAME# transitions from inactive (hi gh) to active (low). During the address phase, a bus command is also driven by the initiator on signal pins C/BE[3:0]#. If the command indicates a PCI read, the clock cycle following the address phase is used to perform a “bus turn-around” cycle. A turn-around cycle is a clock period in which the AD bus is not driven by the initiator or the target device. This is used to avoid PCI bus contention. For a write command, a turn-aro und cycle is not needed, and the bus goes directly from the address phase to the data phase. All PCI bus transactions c onsist of an address phase (described above), followed by one or more data phases. The address phase is only one PCI clock long and the bus cycle information (address and command) is latched internally by the S5335. The number of data phases depends on how many data transfers are desired or are possible with a given initiator-target pair. A data phase consists of at least one PCI clock. FRAME# is deasserted to indicate that the final data phase of a PCI cycle is occurring. Wait states may be added to any data phase (each wait state is one PCI clock). The PCI bus command presented on the C/BE[3:0]# pins during the address phase can represent 16 possi- ble states. Table 54 lists the PCI commands and identifies those which are supported by the S5335 controller as a target and those which may be pro- duced by the S5335 controller as an initiator. A “Yes” in the “Supported As Target” column in Table 54 indi- cates the S5335 controller asserts the signal DEVSEL# when that command is issued along with the appropriate PCI address. Two commands are sup- ported by the S5335 controller as an initiator: Memory Read and Memory Write. The completion or termination of a PCI cycle can be signaled in several ways. In most cases, the comple- tion of the final data phase is indicated by the assertion of ready signals from both the target (TRDY#) and initiator (IRDY#) while FRAME# is inac- tive. In some cases, the target is not be able to continue or support a burst transfer and asserts the STOP# signal. This is referred to as a target discon- nect. There are also cases where an addressed device does not exist, and t he signal DEVSEL# never becomes active. When no DEVSEL# is asserted in response to a PCI cycle, the initiator is responsible for ending the cycle. This is referred to as a master abort. The bus is returned to the idle phase when both FRAME# and IRDY# are deasserted.

1. Memory Read Multiple and Read Line are treated as Memory Reads.
2. Memory Write & Invalidate commands are treated as Memory Writes.
3. Must be enabled by bit 15 MCSR.

Table 54. Supported PCI Bus Commands

the target has accepted the data for the PCI write.

• The memory target aborts the transfer
• PCI bus grant (GNT# is removed)
• The Add-On to PCI FIFO becomes empty
• A higher priority (PCI to Add-On) S5335 trans- fer is pending (if programmed for priority)
• The write transfer by te count reaches zero
• Bus mastering is disabled from the Add-On interface Write accesses to the S5335 operation registers (S5335 as a target) are shown in Figure 50. Here, the S5335 asserts the signal STOP# in clock period 3. STOP# is asserted because the S5335 supports fast, zero-wait-state write cycles but does not support burst writes to operation registers. Wait states may be added by the initiator by not asserting the signal IRDY# during clock 2 and beyond. There is only one condition where writes to S5335 operation registers do not return TRDY# (but do assert STOP#). This is called a target-initiated term ination or target discon- nect and occurs when a write attempt is made to a full S5335 FIFO. As with the read transfers, the assertion of STOP# without the assertion of TRDY# indicates the initiator should retry the operation later.

Figure 49. Zero Wait State Burst Write PCI Bus Transfer (S5335 as Initiator)

tus Register, indicating an error condition. disconnect termination completes a data transfer. Figure 54. Master Abort, No Response

of the S5335 when performing a target-initiated retry. ters never respond with a target abort when accessed. Target termination types are summarized in Table 55. Figure 57. Target-Initiated Retry Table 55. Target Termination Types Disconnect on on on Data is transferred. Transaction needs to be reinitiated to complete. Retry on on off Data was not transferred. Transaction should be tried later. Abort off on off Data was not transferred. Fatal error.

connected to the system’s PCI bus arbiter. nal pair is unique to a given PCI agent. S5335 completes the current transaction. ing the components of PCI bus access latency. particular target nor the bus arbitration delay. control the amount of time a master may own the bus. through a target-initiated disconnect. Figure 60. PCI Bus Access Latency Components

of FRAME# and IRDY# with their interpretation. more accurate estimations for bus access latency. sists even while other bus masters control the bus. which originally established the lock. Figure 61. Engaging the LOCK# Signal Table 56. Possible Combinations of FRAME# and IRDY# deasserted asserted The initiator is ready to comp lete the last data transfer of a transaction. asserted asserted An initiator has a transaction in progress and is able to complete a data transfer.

rupts by asserting the PCI bus interrupt signal (INTA#). to the Interrupt Control/Status Register (INTCSR). parity errors that occur during the address phase. through software or a hardware reset. IRDY# and TRDY# are asserted). Figure 64. Error Reporting Signals

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 107 Data Sheet ADD-ON BUS INTERFACE This chapter describes the Add-On bus interface for the S5335. The S5335 is designed to support connec- tion to a variety of mi croprocessor buses and/or peripheral devices. The Add-On interface controls S5335 operation through t he Add-On Operation Reg- isters. These registers act as the Pass-Thru, FIFO, non-volatile memory and mailbox interfaces as well as offering control and status information. Depending on the register being accessed, the inter- face may be synchronous or asynchronous. To enhance performance and simplify Add-On logic design, some registers allow direct access with a sin- gle device input pin. Asynchronous burst read and write FIFO operations are not recommended. The fol- lowing sections describe the various interfaces to the PCI bus and how they are accessed from the Add-On interface. ADD-ON OPERATION REGISTER ACCESSES The S5335 Add-On bus interface is very similar to that of a memory or peripheral device found in a micropro- cessor-based system. A 32-bit data bus with individual read and write strobes, a chip enable and byte enables are provided. Other Add-On interface signals are provided to simplify Add-On logic design. Accesses to the S5335 registers are done primarily synchronously to BPCLK. For S5335 functions that are compatible with an Add-On microprocessor inter- face, it is helpful to allow an asynchronous interface, as the processor may not operate at the PCI bus clock frequency. Add-On Interface Signals The Add-On interface provides a small number of sys- tem signals to allow the Add-On to monitor PCI bus activity, indicate status conditions (interrupts), and allow Add-On bus configuration. A standard bus inter- face is provided for Add-On Operation Register accesses. System Signals BPCLK and SYSRST# allow the Add-On interface to monitor the PCI bus status. BPCLK is a buffered ver- sion of the PCI clock. The PCI clock can operate from 0 MHz to 33 MHz. SYSRST# is a buffered version of the PCI reset signal, and may also be toggled by host application software through bit 24 of the Bus Master Control/Status Register (MCSR). IRQ# is the Add-On interrupt output. This signal is active low and can indicate a number of conditions. Add-On interrupts may be generated from the mailbox or FIFO interfaces. The exact conditions which gener- ate an interrupt are discussed in the mailbox and FIFO chapters. The interrupt output is deasserted when acknowledged by an access to the Add-On Interrupt Control/Status Register (A INT). All interrupt sources are cleared by writing a one to the corresponding inter- rupt bit. The MODE input on the Add- On interface configures the datapath width for the Add-On interface. MODE low indicates a 32-bit data bus. MODE high indicates a 16-bit data bus. For 16-bit operation, BE3# is rede- fined as ADR1, providing an extra address input. ADR1 selects the low or high words of the 32-bit S5335 Add-On Operation Registers. Register Access Signals Simple register accesses to the S5335 Add-On Opera- tion Registers take two forms: synchronous to BPCLK and asynchronous. The following signals are required to complete a register access to the S5335. BE[3:0]# Byte Enable Inputs. These S5335 inputs identify valid byte lanes during Add-On transac- tions. When MODE is set for 16-bit operation, BE2# is not defined and BE3# becomes ADR1. ADR[6:2] Address Inputs. These address pins identify the specific Add-On Operation Register being accessed. When configured for 16-bit operation (MODE=1), an additional input, ADR1 is available to allow the 32-bit operation registers to be accessed with two 16-bit cycles. RD# Read Strobe Input. WR# Write Strobe Input. SELECT# Chip Select Input. Th is input identifies a valid S5335 access. DQ[31:0] Bidirectional Data Bus. These I/O pins are the S5335 data bus. When configured for 16-bit operation, only DQ[15:0] are valid. In addition, there are dedicated signals for FIFO accesses (RDFIFO# and WRFIFO#) and Pass-Thru address accesses (PTADR# ). These are discussed separately in the FIFO and Pass-Thru sections of this chapter. The internal interfaces of the S5335 allow Add-On Operation Registers to be accessed asynchronous to BPCLK (synchronous to the rising edge of the read or write strobe). The exception to this is the Add-On Gen- eral Control/Status Register. This is due to the async nature of FIFO status bits changing as the PCI bus reads data. For Pass-Thru operations, the Pass-Thru Data Register accesses are synchronous to BPCLK to

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 108 Data Sheet support burst transfers. The FIFO port is also accessed synchronous to BPCLK. Asynchronous Register Accesses For many Add-On applications, Add-On logic does not operate at the PCI bus frequency. This is especially true for Add-Ons implementing a microprocessor, which may be operating at a lower (or higher) fre- quency. Figures 46 and 47 show asynchronous Add- On Operation Register ac cesses. Exact AC timings are detailed in the Electrical and AC Characteristics section. For asynchronous reads (Figure 65), data is driven on the data bus when RD# is asserted. When RD# is not asserted, the DQ[31:0] outputs float. A valid address and valid byte enables must be presented before cor- rect data is driven. RD# has both a minimum inactive time and a minimum active time for asynchronous accesses. For asynchronous writes (Figure 66), data is clocked into the S5335 on the rising edge of the WR# input. Address, byte enables, and data must all meet setup and hold times relative to the rising edge or WR#. WR# has both a minimum i nactive time and a mini- mum active time for asynchronous accesses. Synchronous FIFO and Pass-Thru Data Register Accesses To obtain the highest data transfer rates possible, Add- On logic should operate sy nchronously with the PCI clock. The buffered PCI clock (BPCLK) is provided for this purpose. A synchronous interface with Pass-Thru mode or the FIFO allows data to be transferred at the maximum PCI bus bandwidth (132 MBytes/sec) by allowing burst accesses with the Add-On interface. The RD# and WR# inputs become enables, using BPCLK to clock data into and out of registers. This section applies only to syn chronous accesses to the FIFO (AFIFO) and Pass-Thru Data (APTD) registers. Figures 48 and 49 show single-cycle, synchronous FIFO and Pass-Thru Operation Register accesses. Exact AC timings are detailed in the Electrical and AC Characteristics section. For synchronous reads (Figure 67), data is driven onto the data bus when RD# (o r RDFIFO#) is asserted. When RD# is not asserted, the DQ[31:0] outputs float. The address, byte enable, and RD# inputs must meet setup and hold times relative to the rising edge of BPCLK. Burst reads may be performed by holding RD# low. For synchronous writes (Figure 68), data is clocked into the register on the rising edge of BPCLK. Address, byte enables, and data must all meet setup and hold times relative to the rising edge or BPCLK. Burst writes may be performed by holding WR# (or WRFIFO#) low. When holding WR# low, data is clocked in on each BPCLK rising edge. nv Memory Accesses Through the Add-On Gen- eral Control/Status Register To access nv memory contents through the Add-On General Control/Status Register (AGCSTS), special considerations must be made. Internally, all nv mem- ory accesses by the S5335 are synchronized to a divided-down version of the PCI bus clock. Because of this, if nv memory accesses are performed through the AGCSTS register, the regi ster access must be syn- chronized to BPCLK. The rising edge RD# or WR# is still used to clock data, but these inputs along with the address and byte enables are synchronized to BPCLK. Accesses to AGCSTS for monitoring FIFO or mailbox status, etc., may be done asynchronous to BPCLK. MAILBOX BUS INTERFACE The mailbox register names may need some clarifica- tion. For the Add-On interface, an outgoing mailbox refers to a mailbox sending information to the PCI bus. An incoming mailbox refers to a mailbox receiving information from the PCI bu s. An outgoing mailbox on the Add-On interface is, internally, the same as the corresponding incoming mailbox on the PCI interface and vice-versa.

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 111 Data Sheet Mailbox Interrupts Mailboxes can be configured to generate Add-On interrupts (IRQ#) and/or allow the Add-On to generate PCI interrupts (INTA#). Mailbox empty/full status con- ditions be can used to interrupt the Add-On or PCI host to indicate some action is required. An individual mailbox byte is selected to generate an interrupt when accessed. An outgoing mailbox becoming empty or an incoming mailbox becoming full asserts the interrupt output (if enabled). When used with a serial nv memory boot device, the mailboxes also provide a way to generate PCI inter- rupts (INTA#) through hardware. When a serial nv memory boot device is used, the device pin functions EA0 - EA8 are redefined. These pins then provide direct, external access to the Add-On outgoing mail- box 4, byte 3 (which is also PCI incoming mailbox 4, byte 3). FIFO BUS INTERFACE The FIFO register on the Add-On interface may only be accessed synchronously or asynchronously. Asyn- chronous burst read and write FIFO operations are not recommended. Location 45h, bits 6 and 5 in the nv memory boot device must be programmed to a “0” for correct operation. FIFO Direct Access Inputs RDFIFO# and WRFIFO# are referred to as FIFO ‘direct access’ inputs. Asserting RDFIFO# is function- ally identical to accessi ng the FIFO with RD#, SELECT#, BE[3:0]#, and ADR[6:2]. Asserting WRFIFO# is functionally identical to accessing the FIFO with WR#, SELECT#, BE[3:0]#, and ADR[6:2]. RD# and WR# must be deasserted when RDFIFO# or WRFIFO# is asserted, but SELECT# may be asserted. These inputs automatically drive the address (internally) to 20h and assert all byte enables. The ADR[6:2] and BE[3:0]# inputs are ignored when using the FIFO direct access inputs. RDFIFO# and WRFIFO# are useful for Add-On designs which cas- cade an external FIFO into the S5335 FIFO or use dedicated external logic to access the FIFO. Direct access signals always access the FIFO as 16- bits or 32-bits, whatever the MODE pin is configured for. For 16-bit mode, two consecutive accesses fill or empty the 32-bit FIFO register. FIFO Status Signals The FIFO Status signals indicate to the Add-On logic the current state of the S5335 FIFO. A FIFO status change caused by a PCI FIFO access is reflected one PCI clock period after th e PCI access is completed (TRDY# asserted). A FIFO status change caused by an Add-On FIFO access is reflected immediately (after a short propagation delay) after the access occurs. For Add-On accesses, FIFO status is updated after the ris- ing edge of BPCLK for synchronous interfaces or after the rising edge of the read or write strobe for asyn- chronous interfaces. FIFO Control Signals For Add-On initiated PCI bus mastering, the FIFO sta- tus reset controls FWC# (Add-On to PCI FIFO clear) and FRC# (PCI to Add-On FIFO clear) are available. FWC# and FRC# must be asserted for a minimum of one BPCLK period to be recognized. These inputs are sampled at the rising edge of BPCLK. These inputs should not be asserted unless the FIFO is idle. Assert- ing a FIFO status reset input during a PCI or Add-On FIFO access results in indeterminate operation. For Add-On initiated bus master transfers, AMREN (Add-On bus master read enable) and AMWEN (Add- On bus master write enable) are used, in conjunction with the appropriate FIFO status signals, to enable the S5335 to assert its PCI bus request (REQ#). PASS-THRU BUS INTERFACE The S5335 Pass-Thru interface is synchronous. The Add-On Pass-Thru Addres s (APTA) and Add-On Pass-Thru Data (APTD) registers may be accessed pseudo-synchronously. Although BPCLK is used to clock data into and out of the Pass-Thru registers, accesses may be performed asynchronously. For reads, APTA or APTD data remains valid as long as RD# (or PTADR#) is asserted. A new value is not driven until PTRDY# is asserted by Add-On logic. Fo r writes to APTD, data is clocked into the S5335 on every BPCLK rising edge, but is not passed to the PCI bus until PTRDY# is asserted. PTRDY# must by synchronized to BPCLK. Pass-Thru Status Indicators The Pass-Thru status indicators indicate that a Pass- Thru access is in process and what action is required by the Add-On logic to co mplete the access. All Pass- Thru status indicators ar e synchronous with the PCI clock. Pass-Thru Control Inputs Some Pass-Thru implementations may require an address corresponding to the Pass-Thru data. The Add-On Pass-Thru Address Register (APTA) contains the PCI address for the Pass-Thru cycle. To allow access to the Pass-Thru address without generating an Add-On read cycle, PTADR# is provided. PTADR# is a direct access input for the Pass-Thru address.

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 112 Data Sheet Asserting PTADR# is functionally identical to access- ing the Pass-Thru address register with RD#, SELECT#, BE[3:0]#, and ADR[6:2]. RD# and WR# must be deasserted when PTADR# is asserted, but SELECT# may be asserted. These inputs automati- cally drive the address (internally) to 28h and assert all byte enables. The ADR[6:2] and BE[3:0]# are ignored when using the PTADR# direct access input. When PTADR# is asserted, the contents of the APTA register are immediately driven onto the Add-On data bus. The PTADR# direct access signal accesses the Pass- Thru address register as 16-bits or 32-bits, whatever the MODE pin is configured for. For 16-bit mode, PTADR# only presents the lower 16-bits of the APTA register. PTRDY# indicates that the Add-On has completed the current Pass-Thru access. Mu ltiple Add-On reads or writes may occur to the Pass-Thru data (APTD) regis- ter before asserting PTRDY#. This may be required for 8-bit or 16-bit Add-On interfaces using multiple accesses to the 32-bit Pass-Thru data register. In some cases, the Add-On bus may be 32-bits, but logic may require multiple BPCLK periods to read or write data. In this situation, accesses may be extended by holding off PTRDY#. PTRDY# must be synchronized to BPCLK. NON-VOLATILE MEMORY INTERFACE The S5335 allows read and write access to the nv memory device used for configuration. Reads are nec- essary during device initia lization as configuration information is downloaded into the S5335. If an expan- sion BIOS is implemented in the nv memory, the host transfers (shadows) the code into system DRAM. Writes are useful for in-field updates to expansion BIOS code. This allows software to update the nv memory contents without altering hardware. Non-Volatile Memory Interface Signals For serial nv memory devic es, there are only two sig- nals used to interface with nv memory. SCL is the serial clock, and SDA is the serial data line. The func- tionality of these signals is described in-detail in the PIN description Section of this book. The designer does not need to generate the timings for SCL and SDA. The S5335 automatically performs the correct serial access when programmed for serial devices. For byte-wide nv memory devices, there is an 8-bit data bus (EQ7:0), and a 16-bit address bus (EA15:0) dedicated for the nv memory interface. When a serial nv memory is implemented, many of these pins have alternate functions. The S5335 also has read (ERD#) and write (EWR#) outputs to drive the OE# and WR# inputs on a byte-wide nv memory. The designer does not need to generate the timings for these outputs. The S5335 automatically perf orms the read and write accesses when programmed for byte wide devices. Accessing Non-Volatile Memory The nv memory, if implemented, can be accessed through the PCI interface or the Add-On interface. Accesses from both the PCI side and the Add-On side must be synchronous with th e PCI clock (BPCLK for the Add-On). Accesses to the nv memory from the PCI interface are through the Bus Master Control/Status Register (MCSR) PCI Operation Register. Accesses to the nv memory from the Add-On interface are through the Add-On General Control/Status Regis- ter (AGCSTS) Add-On Operation Register. Accesses to the MCSR register are from the PCI bus and are, therefore, automatically synchronous to the PCI clock. Accesses to the AGCSTS register from the Add-On

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 113 Data Sheet Some nv memories may contain Expansion ROM BIOS code for use by the host software. During initial- ization, the Expansion BIOS is located within system memory. The starting location of the nv memory is stored in the Expansion ROM Base Address Register in the S5335 PCI Configurat ion Registers. A PCI read from this region results in the S5335 performing four consecutive byte access to the nv memory device. Writes to the nv memory are not allowed by writing to this region. Writes to the nv memory must be per- formed as described below. The S5335 contains two latches within the MCSR reg- ister to control and access the NVRAM. One is an 8 bit latch called the NVRAM Address/Data Register which is used to hold NVRAM address and data information. The other is a 3 bit latch called the NVRAM Access Control Register which is used to direct the address and data information and to control the NVRAM itself. Reading or writing to the NVRAM is performed through bits D31:29 of this register. These bits are enable and decode controls rather than a command or instruction to be executed. D31 of this register is the primary enable bit which allows all accesses to occur. When written to a ‘1’, D31 enables the decode bits D30 and D29 to direct the data contained in the address/data latch, D23:16, to the low address, high address or data latches. D31 should be thought of as “opening a door” where as long as D31 = 1, then the door is open for address or data information to be altered. The table on page 5-16 of the S5335 data book shows the D31:29 bit combinations for reading, writing, and loading ad- dress/data information. Additionally, D31 doubles as an S5335 status bit. A ‘1’ indicates that the S5335 is currently busy reading or writing to the NVRAM. A ‘0’ indicates a complete or inactive state. For the examples below, we will assume the S5335 is I/O mapped with a base address of FC00h. These examples will read one byte of the Vendor ID and write one byte to the Vendor ID. This example will write 1 byte from NVRAM location 0040h and read it back: In Out Out Out Out Out Out Out In Out In In FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy). FC00h + 3FH an 80h (CMD to load the low address byte). This sets decode bits and opens door for low address latch. FC00h + 3Eh (offset of Address/Data Register) 40h (the low byte of the address desired) 40h goes into latch but is not latched yet. FC00h + 3Fh an A0h (CMD to load the high address byte). This latches the low address through changing the decode bits and opens the door for the high address latch. FC00h + 3Eh a 00h (the high byte of the address desired). 00h goes into the latch but is not latched yet. FC00h + 3Fh an 00h (inactive CMD). This latches the high address through the disabling D31, ‘closes the door’. FC00h + 3Eh DATA (the data byte to be written). DATA byte goes into the latch but is not latched yet. FC00h + 3Fh a C0h (CMD to write the data byte). This latches the data byte through changing the decode bits and begins to write NVRAM data operation. FC00h + 3Fh until D31 = 0 (not busy). FC00h + 3Fh an E0h (CMD to read the address latched). FC00h + 3Fh until D31 = 0 (not busy). FC00h + 3Eh the data.

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 114 Data Sheet Notes: 1. Latched addresses do not automatically increment after a read or write. They must be loaded with new values. 2. Latched addresses remain after reads and writes. It is allowable to only update one address byte for the next access. 3. A processor may perform a one word write to load an address byte and control command simultaneously. This example will read 1 byte from NVRAM location 0040h: In Out Out Out Out Out In In FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy). FC00h + 3Fh an 80h (CMD to load the low address byte). This sets decode bits and opens door for low address latch. FC00h + 3Eh (offset of Address/Data Register) 40h (the low byte of the address desired) 40h goes into latch but is not latched yet. FC00h + 3Fh an A0h (CMD to load the high address byte). This latches the low address through changing the decode bits and opens the door for the high address latch. FC00h + 3Eh a 00h (the high byte of the address desired) 00h goes into latch but is not latched yet. FC00h + 3Fh an E0h (CMD to read NVRAM data). This latches the high address through changing the decode bits and begins to read the NVRAM data operation. FC00h + 3Fh until D31 = 0 (not busy). FC00h + 3Eh the data. This example will read 1 byte from NVRAM location 0041h and contains an extra step to demonstrate D31 operation: In Out Out Out Out Out Out In In FC00h + 3Fh (offset of NVRAM Access Control Register) until D31 = 0 (not busy). FC00h + 3Fh an 80h (CMD to load the low address byte). This sets decode bits and opens the door for low address latch. FC00h + 3Eh (offset of Address/Data Register) 40h (the low byte of the address desired) 40h goes into latch but is not latched yet. FC00h + 3Eh (offset of Address/Data Register) 41h (the low byte of the address desired) 41h goes into latch but is not latched yet. FC00h + 3Fh an A0h (CMD to load the high address byte). This latches the low address through changing the decode bits and opens the door for the high address latch. FC00h + 3Eh 00h (the high byte of the address desired) 00h goes into latch but is not latched yet. FC00h + 3Fh an E0h (CMD to read the address latched). This latches the high address through changing the decode bits and begins the read NVRAM data operation. FC00h + 3Fh until D31 = 0 (not busy). FC00h + 3Eh the data.

frequency is the PCI clock frequency divided by 512. frequency is compatible with the S5335. Figure 69. nv Memory Read Operation

Figure 70. nv Memory Write Operation

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 118 Data Sheet Mailbox Empty/Full Conditions The PCI and Add-On interfaces each have a mailbox status register. The PCI Mailbox Empty/Full Status (MBEF) and Add-On Mailbox Empty/Full Status (AMBEF) Registers indicate the status of all bytes within the mailbox registers. A write to an outgoing mailbox sets the status bits for that mailbox. The byte enables determine which bytes within the mailbox become full (and which status bits are set). An outgoing mailbox for one interface is an incoming mailbox for the other. Therefore, incoming mailbox sta- tus bits on one interface are identical to the corresponding outgoing mailbox status bits on the other interface. The following list shows the relation- ship between the mailbox registers on the PCI and Add-On interfaces. A write to an outgoing mailbox also writes data into the incoming mailbox on the other interface. It also sets the status bits for the outgoing mailbox and the status bits for the incoming mailbox on the other interface. Reading the incoming mailbox clears all correspond- ing status bits in the A dd-On and PCI mailbox status registers (AMBEF and MBEF). For example, a PCI write is performed to the PCI out- going mailbox 2, writing bytes 0 and 1 (BE0# and BE1# asserted). Reading t he PCI Mailbox Empty/Full Status Register (MBEF) indicates that bits 4 and 5 are set. These bits indicate that outgoing mailbox 2, bytes 0 and 1 are full. Reading the Add-On Mailbox Empty/ Full Status Register (AMBEF) shows that bits 4 and 5 in this register are also set, indicating Add-On incom- ing mailbox 2, bytes 0 and 1 are full. An Add-On read of incoming mailbox 2, bytes 0 and 1 clears the status bits in both the MBEF and AMBEF status registers. To reset individual flags in the MBEF and AMBEF reg- isters, the corresponding by te must be read from the incoming mailbox. The PCI and Add-On mailbox sta- tus registers, MBEF and AMBEF, are read-only. Mailbox flags may be globally reset from either the PCI interface or the Add-On interface. The PCI Bus Master Control/Status Register (MCSR) and the Add-On Gen- eral Control/Status Register (AGCSTS) each have a bit to reset all of the mailbox status flags. Mailbox Interrupts The designer has the option to generate interrupts to the PCI and Add-On interfaces when specific mailbox events occur. The PCI and Add-On interfaces can each define two conditions where interrupts may be generated. An interrupt can be generated when an incoming mailbox becomes full and/or when an outgo- ing mailbox becomes empty. A specific byte within a specific mailbox is selected to generate the interrupt. The conditions defined to generate interrupts to the PCI interface do not have to be the same as the condi- tions defined for the Add-On interface. Interrupts are cleared through software. For incoming mailbox interrupts, when the specified byte becomes full, an interrupt is generated. The inter- rupt might be used to indicate command or status information has been provided, and must be read. For PCI incoming mailbox interrupts, the S5335 asserts the PCI interrupt, INTA#. For Add-On incoming mail- box interrupts, the S5335 asserts the Add-On interrupt, IRQ#. For outgoing mailbox interrupts, when the specified byte becomes empty, an interrupt is generated. The interrupt might be used to indicate that the other inter- face has received the last information sent and more may be written. For PCI outgoing mailbox interrupts, the S5335 asserts the PCI interrupt, INTA#. For Add- On outgoing mailbox interrupts, the S5335 asserts the Add-On interrupt, IRQ#. PCI Interface Add-On Interface Outgoing Mailbox1 Outgoing Mailbox 2 Outgoing Mailbox 3 Outgoing Mailbox 4 Incoming Mailbox 1 Incoming Mailbox 2 Incoming Mailbox 3 Incoming Mailbox 4 PCI Mailbox Empty/Full Incoming Mailbox 1 Incoming Mailbox 2 Incoming Mailbox 3 Incoming Mailbox 4 Outgoing Mailbox 1 Outgoing Mailbox 2 Outgoing Mailbox 3 Outgoing Mailbox 4 Add-On Mailbox Empty/ Full

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 119 Data Sheet Add-On Outgoing Mailbox 4, Byte 3 Access PCI incoming mailbox 4, byte 3 (Add-On outgoing mailbox 4, byte 3) does not function exactly like the other mailbox bytes. When an a serial nv memory boot device or no external boot device is used, the S5335 pins EA7:0 are redefined to provide direct external access to Add-On outgoing mailbox 4, byte 3. EA8 is redefined to provide a load clock which may be used to generate a PCI interrupt. The pins are redefined as follows: If the S5335 is programmed to generate a PCI inter- rupt (INTA#), on an Add-On write to outgoing mailbox 4, byte 3, a rising edge on EMBCLK generates a PCI interrupt. The bits EMB7:0 can be read by the PCI bus interface by reading the PCI incoming mailbox 4, byte 3. These bits are useful to indicate various conditions which may have caused the interrupt. When using the S5335 with a byte-wide boot device, the capability to generate PCI interrupts with Add-On hardware does not exist. In this configuration, PCI incoming mailbox 4, byte 3 (Add-On incoming mailbox 4, byte 3) cannot be used to transfer data from the Add-On - it always returns zeros when read from the PCI bus. This mailbox byte is sacrificed to allow the added functionality provided when a byte-wide boot device is not used. BUS INTERFACE The mailboxes appear on the Add-On and PCI bus interfaces as eight operation registers. Four are outgo- ing mailboxes, four are incoming mailboxes. The mailboxes may be used to generate interrupts to each of the interfaces. The following sections describe the Add-On and PCI bus interfaces for the mailbox registers. PCI Bus Interface The mailboxes are only accessible with the S5335 as a PCI target. The mailbox operation registers do not support burst accesses by an initiator. A PCI initiator attempting to burst to the mailbox registers causes the S5335 to respond with a target disconnect with data. PCI writes to full outgoing mailboxes overwrite data currently in that the mail box. PCI reads from empty incoming mailboxes return the data that was previ- ously contained in the mailbox. Neither of these situations cause a target retry or abort. PCI incoming and outgoing mailbox interrupts are enabled in the Interrupt Control/Status Register (INTCSR). The mailboxes can generate a PCI inter- rupt (INTA#) under two conditions (individually enabled). For an incoming mailbox full interrupt, INTA# is asserted on the PCI clock rising edge after the Add- On mailbox write completes. For an outgoing mailbox empty interrupt, INTA# is asserted on the PCI clock rising edge after the Add-On mailbox read completes (the rising edge of RD#). INTA# is deasserted on the next PCI clock rising edge after the PCI access to clear the mailbox interrupt completes (TRDY# deasserted). Add-On Bus Interface The Add-On mailbox interface behaves similar to the PCI bus interface. Add-On writes to full outgoing mail- boxes overwrite data current ly in that mailbox. PCI reads from empty incoming mailboxes return the data that was previously contained in the mailbox. Add-On incoming and outgoing mailbox interrupts are enabled in the Add-On Interrupt Control/Status Regis- ter (AINT). The mailboxes can generate the Add-On IRQ# interrupt under two conditions (individually enabled). For an incoming mailbox full interrupt, IRQ# is asserted one PCI clock period after the PCI mailbox write completes (TRDY# deasserted). For an outgoing mailbox empty interrupt, IRQ# is asserted one PCI clock period after the PCI mailbox read completes (TRDY# deasserted). IRQ# is deasserted immediately when the Add-On clears the mailbox interrupt. When the S5335 is used with a serial nv memory boot device or no external boot device, the device pins EA8:0 are redefined. EA7:0 become EMB7:0 data inputs and EA8 becomes EMBCLK, a load clock. This configuration allows the Add-On to generate PCI inter- rupts with a low-to-high transition on EMBCLK. The PCI incoming mailbox interrupt must be enabled and set for mailbox 4, byte3 in the PCI Interrupt Control/ Status Register (INTCSR). EMBCLK should begin high and be pulsed low, then high to be recognized. The rising edge of EMBCLK generates the interrupt. The rising edge of EMBCLK also latches in the values on EMB7:0. The S5335 interrupt logic must be cleared (INTA# deasserted) through INTCSR before further EMBCLK interrupts are recognized. Signal Pin Add-On Outgoing Mailbox EA0/EMB0 EA1/EMB1 EA2/EMB2 EA3/EMB3 EA4/EMB4 EA5/EMB5 EA6/EMB6 EA7/EMB7 EA8/EMBCLK Mailbox 4, bit 24 Mailbox 4, bit 25 Mailbox 4, bit 26 Mailbox 4, bit 27 Mailbox 4, bit 28 Mailbox 4, bit 29 Mailbox 4, bit 30 Mailbox 4, bit 31 Mailbox 4, byte 3 load clock

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 120 Data Sheet 8-Bit and 16-Bit Add-On Interfaces Some Add-On designs may implement an 8-bit or 16- bit bus interface. The mailboxes do not require a 32-bit Add-On interface. For 8-bit interfaces, the 8-bit data bus may be externally connected to all four bytes of the 32-bit Add-On interface (DQ 31:24, 23:16, 15:8, 7:0 are all connected). The Add-On device reading or writing the mailbox regist ers may access all mailbox bytes by cycling through the Add-On byte enable inputs. A similar solution applies to 16-bit Add-On buses. This solution wor ks for Add-Ons which always use just 8-bit or just 16-b it accesses. If the MODE pin is high, indicating a 16-bit Add-On interface, the previ- ous solution may be modified for an 8-bit interface. The difference is that ADR1 must be toggled after the first two accesses to steer the S5335 internal data bus to the upper 16-bits of the mailboxes. CONFIGURATION The PCI interface and the Add-On interface each have four incoming mailboxes (IMBx or AIBMx) and four outgoing mailboxes (OMBx or AOMBx) along with a single mailbox status register (MBEF or AMBEF). Out- going mailboxes are read/write, incoming mailboxes and the mailbox status registers are read-only. The following sections discuss the registers associ- ated with the mailboxes and accesses required for different modes of mailbox operation. Mailbox Status Every byte in each mailbox has a status bit in the Mail- box Empty/Full Status Registers (MBEF and AMBEF). Writing a particular byte into an outgoing mailbox sets the corresponding status bit in both the MBEF and AMBEF registers. A read of a ‘full’ byte in a mailbox clears the status bit. The MBEF and AMBEF are read- only. Status bits cannot cleared by writes to the status registers. The S5335 allows the mailbox status bits to be reset through software. The Bus Master Control/Status (MCSR) PCI Operation Register and the Add-On Gen- eral Control/Status (AGCSTS) Add-On Operation Register each have a bit to reset mailbox status. Writ- ing a ‘1’ to Mailbox Flag Reset bit in the MCSR or the AGCSTS register immediately clears all bits in the both the MBEF and AMBEF registers. Writing a ‘0’ has no effect. The Mailbox Flag Reset bit is write-only. The flag bits should be monitored when transferring data through the mailboxes. Checking the mailbox sta- tus before performing an operation prevents data from being lost or corrupted. The following sequences are suggested for PCI mailbox operations using status polling (interrupts disabled): Reading a PCI Incoming Mailbox: 1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from the Add- On interface. MBEF Bits 31:16 If a bit is set, valid data is contained in the corresponding mailbox byte. 2. Read Mailbox(es). Read the mailbox bytes which MBEF indicates are full. This automatically resets the status bits in the MBEF and AMBEF registers. IMBx Bits 31:0 Mailbox data. Writing a PCI Outgoing Mailbox: 1. Check Mailbox Status. Read the mailbox stat us register to determine if information previously written to the mailbox has been read by the Add-On interface. Writes to full mailbox bytes overwrite data cu rrently in the mailbox (if not already read by the Add-On interface). Repeat until the byte(s) to be written are empty. MBEF Bits 15:0 If a bit is set, valid data is contained in the corresponding mailbox byte and has not been read by the Add-On. 2. Write Mailbox(es). Write to the outgoing mailbox byte(s). OMBx Bits 31:0 Mailbox data.

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 121 Data Sheet Mailbox operations for the Add-On interface are functi onally identical. The following sequences are suggested for Add-On mailbox operations using status polling (interrupts disabled): Mailbox Interrupts Although polling status is useful, in so me cases, polling requires continuous actions by the processor reading or writing the mailbox. Mailbox interrupt capabilities are pr ovided to avoid much of the processor overhead required by continuously polling status bits. The Add-On and PCI interface can each generate interrupts on an incoming mailbox condition and/or an outgoing mailbox condition. These can be individually enabled/disabl ed. A specific byte in one incoming mailbox and one outgoing mailbox is identified to generate the interrupt(s). The tasks required to setup mailbox interrupts are shown below: Reading an Add-On Incoming Mailbox: 1. Check Mailbox Status. Read the mailbox status register to determine if any information has been passed from the PCI interface. AMBEF Bits 15:0 If a bit is set, valid data is contained in the corre- sponding mailbox byte. 2. Read Mailbox(es). Read the mailbox bytes which AMBEF indicates are full. This automatically resets the status bits in the AMBEF and MBEF registers. AIMBx Bits 31:0 Mailbox data. Writing an Add-On Outgoing Mailbox: 1. Check Mailbox Status. Read the mailbox status register to det ermine if information previously written to the mailbox has been read by the PCI interface. Writes to full mailbox byte s overwrite data currently in the mailbox (if not already read by the PCI interface). Repeat until the byte(s) to be written are empty. AMBEF Bits 31:16 If a bit is set, valid data is contained in the corre- sponding mailbox byte and has not been read by the PCI bus. 2. Write Mailbox(es). Write to the outgoing mailbox byte(s). AOMBx Bits 31:0 Mailbox data. Enabling PCI mailbox interrupts: 1. Enable PCI outgoing mailbox interrupts. A specific byte within one of the outgoing mailbox es is identified to assert INTA# when read by the Add-On interface. INTCSR Bit 4 Enable outgoing mailbox interrupts INTCSR Bits 3:2 Identify mailbox to generate interrupt INTCSR Bits 1:0 Identify mailbox byte to generate interrupt 2. Enable PCI incoming mailbox interrupts. A specific byte wi thin one of the incoming mailboxes is identified to assert INTA# when written by the Add-On interface. INTCSR Bit 12 Enable incoming mailbox interrupts INTCSR Bits 11:10 Identify mailbox to generate interrupt INTCSR Bits 9:8 Identify mailbox byte to generate interrupt

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 122 Data Sheet Once interrupts are enabled, the interrupt service rout ine must access the mailbox es and clear the interrupt source. A particular application may not require all of the steps shown. For instance, a design may only use incom- ing mailbox interrupts and not require support for outgoing mail box interrupts. The interr upt service routine tasks are shown below: Enabling Add-On mailbox interrupts: 1. Enable Add-On outgoing mailbox interrupts. A specific byte within one of the outgoing mailboxes is identified to assert IRQ# when read by the PCI interface. AINT Bit 12 Enable outgoing mailbox interrupts AINT Bits 11:10 Identify mailbox to generate interrupt AINT Bits 9:8 Identify mailbox byte to generate interrupt 2. Enable Add-On incoming mailbox interrupts. A specific byte within one of the incoming mailboxes is identified to assert IRQ# when written by the PCI interface. AINT Bit 4 Enable incoming mailbox interrupts AINT Bits 3:2 Identify mailbox to generate interrupt AINT Bits 1:0 Identify mailbox byte to generate interrupt With either the Add-On or PCI interface, these two steps can be performed with a single access to the appropriate register. They are shown separately here for clarity. Servicing a PCI mailbox interrupt (INTA#): 1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5335. The interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). INTCSR Bit 16 PCI outgoing mailbox interrupt indicator INTCSR Bit 17 PCI incoming mailbox interrupt indicator 2. Check mailbox status. The mailbox status bits indicate which mailbox bytes must be read or written. MBEF Bits 31:16 Full PCI incoming mailbox bytes MBEF Bits 15:0 Empty PCI outgoing mailbox bytes 3. Access the mailbox. Based on the contents of MBEF, mailboxes are read or written. Reading an incoming mailbox byte clears the corresponding status bit in MBEF. OMBx Bits 31:0 PCI outgoing mailboxes IMBx Bits 31:0 PCI incoming mailboxes 4. Clear the interrupt source. The PCI INTA# signal is deassert ed by clearing the interrupt request. The request is cleared by writing a ‘1’ to the appropriate bit. INTCSR Bit 16 Clear PCI outgoing mailbox interrupt INTCSR Bit 17 Clear PCI incoming mailbox interrupt

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 123 Data Sheet Servicing an Add-On mailbox interrupt (IRQ#): 1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5335. The interrupt service routine must verify that a mailbox generated the interrupt (and not some other interrupt source). AINT Bit 16 Add-On incoming mailbox interrupt indicator AINT Bit 17 Add-On outgoing mailbox interrupt indicator 2. Check mailbox status. The mailbox status bits indicate which mailbox bytes must be read or written. AMBEF Bits 31:16 Empty Add-On outgoing mailbox bytes AMBEF Bits 15:0 Full Add-On incoming mailbox bytes 3. Access the mailbox. Based on the cont ents of AMBEF, mailboxes are read or wr itten. Reading an incoming mailbox byte clears the corresponding status bit in AMBEF. AIMBx Bits 31:0 Add-On incoming mailboxes AOMBx Bits 31:0 Add-On outgoing mailboxes 4. Clear the interrupt source. The Add-On IRQ# signal is d easserted by clearing the interrupt request. The request is cleared by writing a ‘1’ to the appropriate bit. AINT Bit 16 Clear Add-On incoming mailbox interrupt AINT Bit 17 Clear Add-On outgoing mailbox interrupt In both cases, step 3 involves accessing the mailbox. To allow the incoming mailbox interrupt logic to be cleared, the mailbox status bit must also be cleared. Reading an incoming mailbox clears the status bits. Another option for clearing the status bits is to use the Mailbox Flag Reset bit in the MCSR and AGCSTS registers, but this clears all status bits, not just for a single mailbox or mailbox byte. For outgoing mailbox interrupts, the read of a mailbox register is what generated the interrupt; this ensures the status bits are already clear.

whether the access is a read or write. The FIFO may be either a PCI target or a PCI initiator. formed on data passing through the FIFO. the Add-On to PCI FIFO directions. Figure 73. INTCSR FIFO Advance and Endian Control Bits

for 64-bit data during operation. Figure 76. 64-bit Endian Conversion

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 127 Data Sheet Add-On FIFO Status Indicators The Add-On interface implements FIFO status pins to indicate the full and empty conditions of the PCI to Add-On and Add-On to PCI FIFOs. These may be used by the Add-On to allow data transfers between the FIFO and memory, a peripheral, or even a cas- caded external FIFO. The RDEMPTY and WRFULL status outputs are always available to the Add-On. Additional status signals are multiplexed with the byte- wide, non-volatile memory interface pins. If the S5335 is configured for Add-On initiated bus mastering, these status signals also become available to the Add-On. FIFO status is also indicated by bits in the Add-On General Control/Status and Bus Master Control/Status Registers. The table below lists all FIFO status outputs and their functions. 1. These signals are only available when a serial non-volatile mem- ory is used and the device is configured for Add-On initiated bus mastering. Add-On FIFO Control Signals The Add-On interface implements FIFO control pins to manipulate the S5335 FIFOs. These may be used by Add-On to control data transfer between the FIFO and memory, a peripheral, or even a cascaded external FIFO. The RDFIFO# and WRFIFO# inputs are always available. These pins allow direct access to the FIFO without generating a standard Add-On register access using RD#, WR#, SELECT#, address pins and the byte enables. Additional control signals are multiplexed with the byte-wide, non-volatile memory interface pins. If a serial non-volatile memory is used and the S5335 is configured for Add-On initia ted bus mastering, these control signals also become available. For PCI initi- ated bus mastering, AMREN, AMWEN, FRC#, and FWC# functionality is always available through bits in the Bus Master Control/Status and Add-On General Control/Status Registers. Th e FIFO control inputs are listed below. 1. These signals are only available when a serial non-volatile mem- ory is used and the S5335 is configured for Add-On initiated bus mastering. PCI Bus Mastering with the FIFO The S5335 may initiate PCI bus cycles through the FIFO interface. The S5335 allows blocks of data to be transferred to and from the Add-On by specifying a source/destination address on the PCI bus and a transfer byte count. This DMA capability allows data to be transferred across the PCI bus without host CPU intervention. Initiating a bus master transfer requires programming the appropriate address registers and transfer byte counts. This can be done from either the PCI interface or the Add-On interface. Initiating bus master transfers from the add-on is advantageous because the host CPU does not have to intervene for the S5335 to become a PCI Initiator. At the end of a transfer the S5335 may generate an interrupt to either the PCI bus (for PCI initiated transfers) or Add-On interface (for Add-On initiated transfers). Add-On Initiated Bus Mastering If bit 7 in location 45h of an external serial non-volatile memory is zero, the Master Read Address Register (MRAR), Master Write Address Register (MWAR), Master Read Transfer Count (MRTC), and Master Write Transfer Count (MWTC) are accessible only from the Add-On interface. Add-On initiated bus mas- tering is not possible when a byte-wide boot device is used due to shared device pins. When configured for Add-On initiated bus mastering, the S5335 transfers data until the transfer count reaches zero, or it may be configured to ignore the transfer count. Signal Function RDEMPTY Indicates empty condition of the PCI to Add-On FIFO WRFULL Indicates full condition of the Add-On to PCI FIFO FRF Indicates full condition of the PCI to Add- On FIFO1 FWE Indicates the empty condition of the Add- On to PCI FIFO1 Signal Function RDFIFO# Reads data from the PCI to Add-On FIFO WRFIFO# Writes data into the Add-On to PCI FIFO FRC# Reset PCI to Add-On FIFO pointers and status indicators1 FWC# Reset Add-On to PCI FIFO pointers and status indicators1 AMREN Enable bus mastering for Add-On initiated PCI reads1 AMWEN Enable bus mastering for Add-On initiated PCI writes1

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 128 Data Sheet For bus master transfers initiated by the Add-On inter- face, some applications may not know the size of the data block to be transferred. To avoid constantly updating the transfer count register, the transfer count may be disabled. Bit 28 in the Add-On General Con- trol/Status Register (AGCSTS) performs this function. Disabling the transfer count also disables the interrupt capabilities. Regardless of whether Add-On transfer count is enabled or disabled, the Add-On Master Read Enable (AMREN) and Add-On Master Write Enable (AMWEN) inputs control when the S5335 asserts or deasserts its request to the PCI bus. When Add-On transfer count is enabled, the S5335 will only request the bus when both the transfer count (read or write) is not zero and the appropriate enable line (AMREN or AMWEN) is active. For Add-On initiated bus master- ing, AMWEN and AMREN override the read and write bus mastering enable bits in the Bus Master Control/ Status Register (MCSR). PCI Initiated Bus Mastering If bit 7 in location 45h of the external non-volatile mem- ory is one, the Master Read Address Register (MRAR), Master Write Address Register (MWAR), Master Read Transfer Count (MRTC), and Master Write Transfer Count (MWT C) are accessible only from the PCI bus interface. In this configuration, the S5335 transfers data until the transfer count reaches zero. The transfer count cannot be disabled for PCI initiated bus mastering. If no external nv memory boot device is used, the S5335 defaults to PCI initiated bus mastering. Address and Transfer Count Registers The S5335 has two sets of registers used for bus mas- ter transfers. There are two operation registers for bus master read operations and two operation registers for bus master write operations. One operation register is for the transfer address (MWAR and MRAR). The other operation register is for the transfer byte count (MWTC and MRTC). The address registers are written with the first address of the transfer before bus mastering is enabled. Once a transfer begins, this register is automatically updated to reflect the address of the current transfer. If a PCI target disconnects from an S5335 initiated cycle, the transfer is retried starting from the current address in the register. If bus grant (GNT#) is removed or bus mastering is disabled (using AMREN or AMWEN), the value in the address register reflects the next address to be accessed. Transfers must begin on DWORD boundaries. The transfer count registers contain the number of bytes to be transferred. The transfer count may be written before or after bus mastering is enabled. If bus mastering is enabled, no transfer occurs until the transfer count is programmed with a non-zero value. Once a transfer begins, this register is automatically updated to reflect the number of bytes remaining to be transferred. If the transfer count registers are disabled (for Add-On initiated bus mastering), transfers begin as soon as bus mastering is enabled. Although transfers must begin on DWORD bound- aries, transfer counts do not have to be multiples of four bytes. For example, if the write transfer count (MWTC) register is programmed with a value of 10 (decimal), the S5335 performs two DWORD writes and a third write with only BE0# and BE1# asserted. Bus Mastering FIFO Management Schemes The S5335 provides flexibility in how the FIFO is man- aged for bus mastering. The FIFO management scheme determines when the S5335 requests the bus to initiate PCI bus cycles. The management scheme is configurable for the PCI to Add-On and Add-On to PCI FIFO (and may be different for each). Bus mastering must be enabled for the management scheme to apply (via the enable bits or AMREN/AMWEN). For the PCI to Add-On FIFO, there are two manage- ment options. The PCI to Add-On FIFO management option is programmed through the Bus Master Control/ Status Register (MCSR). The FIFO can be pro- grammed to request the bus when any DWORD location is empty or only when four or more locations are empty. After the S5335 is granted control of the PCI bus, the management scheme does not apply. The device continues to read as long as there is an open FIFO location. When the PCI to Add-On FIFO is full or bus mastering is di sabled, the PCI bus request is removed by the S5335. For the Add-On to PCI FIFO, there are two manage- ment options. The Add-On to PCI FIFO management option is programmed through the Bus Master Control/ Status Register (MCSR). The FIFO can be pro- grammed to request the bus when any DWORD location is full or only when four or more locations are full. After the S5335 is granted control of the PCI bus, the management scheme does not apply. The device continues to write as long as there is data in the FIFO. When the Add-On to PCI FIFO is empty or bus mas- tering is disabled, the PCI bus request is removed by the S5335. There are two special cases for the Add-On to PCI FIFO management scheme. The first case is when the FIFO is programmed to request the PCI bus only when four or more locations are full, but the transfer count is less than 16 bytes. In this situation, the FIFO ignores

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 129 Data Sheet the management scheme and finishes transferring the data. The second case is when the S5335 is config- ured for Add-On initiated bus mastering with transfer counts disabled. In this si tuation, the FIFO manage- ment scheme must be set to request the PCI bus when one or more locations are full. AMREN and AMWEN may be used to implement a specific FIFO management scheme. FIFO Bus Master Cycle Priority In many applications, the FIFO is used as a PCI initia- tor performing both PCI reads and writes. This requires a priority scheme be implemented. What hap- pens if the FIFO condition for initiating a PCI read and a PCI write are both met? Bits D12 and D8 in the Bus Master Control/Status Register (MCSR) control the read and write cycle pri- ority, respectively. If these bits are both set or both clear, priority alternates, beginning with a read cycle. If the read priority is set and the write priority is clear, read cycles take priority. If the write priority is set and the read priority is clear, write cycles take priority. Pri- ority arbitration is only done when neither FIFO has control of the PCI bus (the PCI to Add-On FIFO would never interrupt an Add-On to PCI FIFO transfer). FIFO Generated Bus Master Interrupts Interrupts may be generated under certain conditions from the FIFO. If PCI initiated bus mastering is used, INTA# is generated to the PCI interface. If Add-On ini- tiated bus mastering is used, IRQ# is generated to the Add-On interface. Interrupts may be disabled. FIFO Interrupts may be generated from one or more of the following during bus mastering: read transfer count reaches zero, write transfer count reaches zero, or an error occurs during bus mastering. Error conditions include a target or master abort on the PCI bus. Inter- rupts on PCI error conditions are only enabled if one or both of the transfer count interrupts are enabled. The Add-On Interrupt Contro l/Status Register (AINT) or the Interrupt Control Status Register (INTCSR) indi- cates the interrupt source. The interrupt service routine may read these registers to determine what action is required. As mail boxes are also capable of generating interrupts, this must also be considered in the service routine. Interrupts are also cleared through these registers. BUS INTERFACE The S5335 FIFO may be accessed from the Add-On interface or the PCI interface. Add-On FIFO control and status signals allow a simple interface to the FIFO with either an Add-On CPU or programmable logic. The following section describes the PCI and Add-On interface behavior and hardware interface. FIFO PCI Interface (Target Mode) The S5335 FIFO may act as a standard PCI target. FIFO empty/full status may be determined by the PCI initiator by reading the status bits in the PCI Bus Mas- ter Control/Status Register (MCSR). The FIFO occupies a single 32-bit register location within the PCI Operation Registers. A PCI initiator may not perform burst accesses to a FIFO as it is a single address. Each data phase of a burst causes the PCI initiator to increment its address counter (even though only the first address is driven at the beginning of the burst). The initiator keeps track of the current address in case a disconnect occurs. This allows the initiator to continue the burst from where the discon- nect occurred. If the S5335 FIFO initiated a disconnect during a PCI burst to the FIFO register, the burst would be resumed at an address other than the FIFO loca- tion (because the initiator address counter has incremented). The S5335 always signals a disconnect if a burst to any PCI Operation Register is attempted. Because the PCI to Add-On FIFO and the Add-On to PCI FIFO occupy a single location within the PCI and Add-On Operation Registers, which FIFO is accessed is determined by whether the access is a read or write. This means that once data is written into the FIFO, the value written cannot be read back. For PCI reads from the A dd-On to PCI FIFO, the S5335 asserts TRDY# and completes the PCI cycle (Figure 77). If the PCI bus attempts to read an empty FIFO, the S5335 immediately issues a disconnect with retry (Figure 78). The Add-On to PCI FIFO status indi- cators change one PCI clock after a PCI read. For PCI writes to the PCI to Add-On, the S5335 asserts TRDY# and completes the PCI cycle (Figure 79). If the PCI bus attempts to write a full FIFO, the S5335 immediately issues a disconnect with retry (Fig- ure 80). The PCI to Add-On FIFO status indicators change one PCI clock after a PCI write.

ble through the FIFO with a synchronous interface. Figure 81. Synchronous FIFO Register Burst Read Access Example

queued for transfer, FIFO is empty. driven high to enable bus master writes. driven high to enable bus master reads. Figure 82. Synchronous FIFO Register Burst RDFIFO# Access Example

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 135 Data Sheet The FRC# and FWC# inputs allow Add-On logic to reset the PCI to Add-On or Add-On to PCI FIFO flags. The FIFO flags can always be reset with software through the Add-On General Control/Status Register (AGCSTS) or the Bus Master Control/Status Register (MCSR), but these hardware inputs are useful for designs which do no implement a CPU on the Add-On card. Asserting the FRC# input resets the PCI to Add- On FIFO. Asserting the FWC# input re-sets the Add- On to PCI FIFO. The AMREN and AMWEN inputs allow Add-On logic to individually enable and disable bus mastering for the PCI to Add-On and Add-On to PCI FIFO. These inputs override the Bus Master Control/Status Register (MCSR) bus master enable bits. The S5335 may re- quest the PCI bus for the PCI to Add-On FIFO when AMREN is asserted and may request the PCI bus for the Add-On to PCI FIFO w hen AMWEN is asserted. If AMREN or AMWEN is deasserted, the S5335 removes its PCI bus request and gives up control of the bus. AMREN and AMWEN are useful for Add-Ons with external FIFOs cascaded into the S5335. For PCI bus master write operations, the entire S5335 Add-On to PCI FIFO and the external FIFO may be filled before enabling bus mastering, providing a single long burst write rather than numerous short bursts. In some applications, the amount of data to be trans- ferred is not known. During read operations, the S5335, attempting to fill it s PCI to Add-On FIFO, may access up to eight memory locations beyond what is required by the Add-On before it stops. In this situa- tion, AMREN can be deasserted to disable PCI reads, and then FRC# can be asserted to flush the unwanted data from the FIFO. FIFO Generated Add-On Interrupts For Add-On initiated bus mastering, the S5335 may be configured to generate interrupts to the Add-On inter- face for the following situations: - Read transfer count reaches zero - Write transfer count reaches zero - An error occurred during the bus master transaction The interrupt is posted to the Add-On interface with the IRQ# output. A high-to-low transition on this output indicates an interrupt condition. Because there is a single interrupt output and multiple interrupt condi- tions, the Add-On Interrupt Control/Status Register (AINT) must be read to determine the interrupt source. This register is also used to clear the interrupt, return- ing IRQ# to its high state. If mailbox interrupts are also used, this must be consider ed in the interrupt service routine. 8-Bit and 16-Bit FIFO Add-On Interfaces The S5335 FIFO may also be used to transfer data between the PCI bus and 8-bit or 16-bit Add-On inter- faces. This can be done using FIFO advance conditions or the S5335 MODE input pin. The FIFO may be used as an 8-bit or 16-bit wide FIFO. To use the FIFO as an 8-bit interface, the advance condition should be set for byte 0 (no data is transferred in the upper 3 bytes). To use the FIFO as a 16-bit interface, the adv ance condition should be set for byte 1 (no data is transferred in the upper 2 bytes). This allows a simple Add-On bus interface, but it has the disadvantage of not efficiently utilizing the PCI bus bandwidth because the host is forced to perform 8-bit or 16-bit accesses to the FIFO on the PCI bus. This is the only way to communicate with an 8-bit Add-On through the FIFO without addi tional logic to steer byte lanes on the Add-On data bus. Pass-Thru mode is more suited to 8-bit Add-On interfaces. Implementing a 16-bit wide FIFO is a reasonable solu- tion, but to avoid wasting PCI bus bandwidth, the best method is to allow the PCI bus and the FIFO to oper- ate with 32-bit data. The S5335 can assemble or disassemble 32-bit quantities for the Add-On interface. This is possible through the MODE pin. When MODE is low, the Add-On data bus is 32-bits. When MODE is high, the Add-On data bus is 16-bits. When MODE is configured for 16-bit operation, BE3# becomes ADR1. With the FIFO direct access signals (RDFIFO# and WRFIFO#), the MODE pin must reflect the actual Add- On data bus width. With MODE = 16-bits, the S5335 automatically takes two cons ecutive, 16-bit Add-On writes to the FIFO and assembles a 32-bit value. FIFO reads operate in the same manner. Two consecutive Add-On reads empty the 32-bit FIFO register. The 16- bit data bus is internally steered to the lower and upper words of the 32-bit FIFO register.

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 136 Data Sheet One consideration needs to be taken when using the FIFO direct access signals and letting the S5335 do byte lane steering internal ly. The default condition used to advance the FIFO is byte 0. This must be changed to byte 2 or 3. When MODE is configured for a 16-bit Add-On bus, the first 16-bit cycle to the FIFO always accesses the low 16-bits. If the FIFO advance condition is left at byte 0, the FIFO advances after the first 16-bit cycle and the data in the upper 16-bits is directed to the next FIFO location, shifting the data. Some applications hold the RDFIFO# and WRFIFO# inputs active for a synchronous interface. In 16-bit mode, designs must avoid wr iting to a full FIFO. The data for the write is lost, but the internal mechanism to direct the 16-bit external data bus to the upper 16-bits of the FIFO register is triggered. This creates a situa- tion where the FIFO is out of step. The next 16-bit FIFO write is directed to the upper 16-bits of the FIFO, and the FIFO advances incorrectly. The WRFULL out- put should be used to gate the WRFIFO# input to avoid this situation. A si milar problem can occur if Add-On logic attempts to read an empty FIFO in 16-bit mode. RDEMPTY should be used to gate the RDFIFO# input to avoid problems with the FIFO get- ting out of step. In 32-bit mode (MODE = low), these situations do not occur. If FIFO accesses are done without the direct access signals with MODE configured for 16-bits (using ADR, SELECT#, etc.), external hardware must toggle ADR1 between consecutive 16-bit bus cycles. The FIFO advance condition must be set to correspond to the order the application accesses the upper and lower words in the FIFO register. CONFIGURATION The FIFO configuration takes place during initialization and during operation. During initialization, the bus master register access rights are defined. During oper- ation, FIFO advance conditions, endian conversion, and bus mastering capabilities are defined. The follow- ing section describes the bits and registers which are involved with controlling and monitoring FIFO operation. FIFO Setup During Initialization Location 45h in an external non-volatile memory may be used to configure the S5335 FIFO during initializa- tion. If no external non-vola tile memory is used, FIFO operation is disabled. The value of bit 7 in location 45h determines if the address and transfer count registers used in bus mas- tering are accessible from the PCI bus or from the Add-On bus. Once the configuration information is downloaded from non-volatile memory after reset, the bus mastering initializat ion method can not be changed. Access to the bus master address and trans- fer count registers cannot be alternated between the PCI bus and the Add-On interface during operation. Bits 6 and 5 in location 45h enable FIFO register accesses using the RDFIFO#, WRFIFO#, RD# and WR# inputs synchronous to BPCLK. For synchronous operation, RDFIFO#, WRFIFO#, RD# and WR# oper- ate as enables, using BPCLK to clock data. FIFO Status and Control Bits The FIFO status can be monitored and the FIFO oper- ation controlled from the PCI Operation Registers and/ or the Add-On Operation Registers. The FIFO register resides at offset 20h in the PCI and Add-On Operation Registers. The Bus Master Control/Status (MCSR) PCI Operation register allows a PCI host to monitor FIFO activity and control FIFO operation. Reset controls allow the PCI to Add-On FIFO and Add-On to PCI FIFO flags to be reset (individually). Status bits indicate if the PCI to Add-On FIFO is empty, has four or more open spaces, or is full. Status bits also indicate if the Add-On to PCI FIFO is empty, has four or more full locations or is full. Finally, FIFO PCI bus mastering is monitored/con- trolled though this register. Location 45h Configuration Bits Bit 7 Bus Master Register Access

0 Address and transfer count registers only accessi-

ble from the Add-On interface

1 Address and transfer count registers only accessi-

ble from the PCI interface (default) Bit 6 RDFIFO#, RD# Operation 0 Enable - RDFIFO# and RD# functions. 1 Not allowed. Must be 0. Bit 5 WRFIFO#, WR# Operation 0 Enable - WRFIFO# and WR# functions. 1 Not allowed. Must be 0. Bit 0 Target Latency Timer Enable

0 Disable PCI Latency Timer Time Out - Will not dis-

connect with retry if cannot issue TRDY in speci- fied time

1 Enable PCI Latency Timer Time Out - Will be PCI

2.1 compliant

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 137 Data Sheet The Add-On General Control/Status (AGCSTS) Add- On Operation Register allows an Add-On CPU to mon- itor FIFO activity and control FIFO operation. Reset controls allow the PCI to Add-On FIFO and Add-On to PCI FIFO flags to be reset (individually). Status bits indicate if the PCI to Add-On FIFO is empty, has four or more open spaces, or is full. Status bits also indi- cate if the Add-On to PCI is empty, has four or more full spaces or is full. FIFO bus mastering status may be monitored through this register, but all bus master configuration is through the MCSR PCI Operation Register. PCI Initiated FIFO Bus Mastering Setup For PCI initiated bus mastering, the PCI host sets up the S5335 to perform bus master transfers. The follow- ing tasks must be completed to setup FIFO bus mastering: 1. Define interrupt capabilit ies. The PCI to Add-On and/or Add-On to PCI FIFO can generate a PCI interrupt to the host when the transfer count reaches zero. 2. Reset FIFO flags. This may not be necessary, but if the state of the FIFO flags is not known, they should be initialized. 3. Define FIFO management scheme. These bits define what FIFO condition must exist for the PCI bus request (REQ#) to be asserted by the S5335. 4. Define PCI to Add-On and Add-On to PCI FIFO priority. These bits determine which FIFO has pri- ority if both meet the defined condition to request the PCI bus. If these bits are the same, priority alternates, with read accesses occurring first. 5. Define transfer source/destination address. These registers are written with the first address that is to be accessed by the S5335. These address registers are updated after each access to indicate the next address to be accessed. Transfers must start on DWORD boundaries. 6. Define transfer byte counts. These registers are written with the number of bytes to be transferred. The transfer count does not have to be a multiple of four bytes. These registers are updated after each transfer to reflect the number of bytes remaining to be transferred. INTCSR Bit 15 Enable Interrupt on read transfer count equal zero INTCSR Bit 14 Enable Interrupt on write transfer count equal zero MCSR Bit 26 Reset Add-On to PCI FIFO flags MCSR Bit 25 Reset PCI to Add-On FIFO flags MCSR Bit 13 PCI to Add-On FIFO management scheme MCSR Bit 9 Add-On to PCI FIFO management scheme MCSR Bit 12 Read vs. write priority MCSR Bit 8 Write vs. read priority MWAR All Bus master write address MRAR All Bus master read address MWTC All Write transfer byte count MRTC All Read transfer byte count

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 138 Data Sheet 7. Enable Bus Mastering. Once steps 1-6 are com- pleted, the FIFO may operate as a PCI bus master. Read and write bus master operation may be independently enabled or disabled. The order of the tasks listed above is not particularly important. It is recommended that bus mastering be enabled as the last step. Some applications may choose to leave bus mastering enabled and start transfers by writing a non-zero value to the transfer count registers. This also works, provided the entire transfer count is written in a single access. As a num- ber of the configuration bits and the two enable bits are all in the MCSR register , it may be most efficient for the FIFO configuration bits to be set with the same register access that enables bus mastering. If interrupts are enabled, a host interrupt service rou- tine is also required. The service routine determines the source of the interrupt and resets the interrupt. As mailbox registers may also be configured to generate interrupts, the exact source of the interrupt is indicated in the PCI Interrupt Control/Status Register (INTCSR). Typically, the interrupt service routine is used to setup the next transfer by writing new addresses and trans- fer counts, but some applications may also require other actions. If read transfer or write transfer com- plete interrupts are enabled, master and target abort interrupts are automatically enabled. These indicate a transfer error has occurred. Writing a one to these bits clears the corresponding interrupt. Add-On Initiated FIFO Bus Mastering Setup For Add- On initiated bus mastering, the Add-On sets up the S5335 to perform bus master transfers. The following tasks must be completed to setup FIFO bus mastering: 1. Define transfer count ab ilities. For Add-On initi- ated bus mastering, transfer counts may be either enabled or disabled. Transfer counts for read and write operations cannot be individually enabled. 2. Define interrup t capabilities. T he PCI to Add-On and/or Add-On to PCI FIFO can generate an interrupt to the Add-On when the transfer count reaches zero (if transfer counts are enabled). 3. Reset FIFO flags. This may not be necessary, but if the state of the FIFO flags is not known, they should be initialized. 4. Define FIFO management scheme. These bits define what FIFO condition must exist for the PCI bus request (REQ#) to be asserted by the S5335. This must be programmed through the PCI interface. MCSR Bit 14 Enable PCI to Add-On FIFO bus mas- tering MCSR Bit 10 Enable Add-On to PCI FIFO bus mas- tering INTCSR Bit 21 Target abort caused interrupt INTCSR Bit 20 Master abort caused interrupt INTCSR Bit 19 Read transfer complete caused inter- rupt INTCSR Bit 18 Write transfer complete caused inter- rupt AGCSTS Bit 28 Enable transfer count for read and write bus master transfers AINT Bit 15 Enable interrupt on read transfer count equal zero AINT Bit 14 Enable interrupt on write transfer count equal zero AGCSTS Bit 25 Reset Add-On to PCI FIFO flags AGCSTS Bit 26 Reset PCI to Add-On FIFO flags MCSR Bit 13 PCI to Add-On FIFO management scheme MCSR Bit 9 Add-On to PCI FIFO management scheme

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 139 Data Sheet 5. Define PCI to Add-On an d Add-On to PCI FIFO priority. These bits determine which FIFO has pri- ority if both meet the defined condition to request the PCI bus. If these bits are the same, priority alternates, with read ac cesses occurring first. This must be programmed through the PCI interface. 6. Define transfer source/destination address. These registers are writt en with the first address that is to be accessed by the S5335. These address registers are updated after each access to indicate the next address to be accessed. Transfers must start on DWORD boundaries. MWAR All Bus master write address MRAR All Bus master read address 7. Define transfer byte counts. These registers are written with the number of bytes to be transferred. The transfer count does not have to be a multiple of four bytes. These registers are updated after each transfer to reflect the number of bytes remaining to be transferred. If transfer counts are disabled, these registers do not need to be programmed. 8. Enable Bus Mastering. Once steps 1-7 are com- pleted, the FIFO may operate as a PCI bus master. Read and write bus master operation may be independently enabled or disabled. The AMREN and AMWEN inputs control bus master enabling for Add-On initiated bus mastering. The MCSR bus master enable bits are ignored for Add-On initiated bus mastering. It is recommended that bus mastering be enabled as the last step. Some applications may choose to leave bus mastering enabled (AMREN and AMWEN asserted) and start transfers by writing a non-zero value to the transfer count registers (if they are enabled). If interrupts are enabled, an Add-On CPU interrupt service routine is also required. The service routine determines the source of the interrupt and resets the interrupt. As mailbox registers may also be configured to generate interrupts, the exact source of the interrupt is indicated in the Add-On Interrupt Control Register (AINT). Typically, the interrupt service routine is used to setup the next transfer by writing new addresses and transfer counts (if enabled), but some applications may also require other actions. If read transfer or write transfer complete interrupts are enabled, the master/ target abort interrupt is automatically enabled. These indicate a transfer error has occurred. Writing a one to these bits clears the corresponding interrupt. MCSR Bit 12 Read vs. write priority MCSR Bit 8 Write vs. read priority MWTC All Write transfer byte count MRTC All Read transfer byte count AINT Bit 21 Master/target abort caused interrupt AINT Bit 19 Read transfer complete caused interrupt AINT Bit 18 Write transfer complete caused interrupt

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 140 Data Sheet PASS-THRU OVERVIEW The S5335 provides a simple registered access port to the PCI bus. Using a handshak ing protocol with Add- On card logic, the PCI bus directly accesses resources on the Add-On. The Pass-Thru data transfer method is very useful for direct Add-On memory access, or accessing registers within peripherals on an Add-On board. Pass-Thru operation requires an external nv memory boot device to define and configure the S5335 Pass-Thru regions. The S5335 provides four user-configurable Pass-Thru regions. Each region corresponds to a PCI Configura- tion Base Address Register (BADR1-4). A region represents a block of address space (the block size is user-defined). Each block can be mapped into mem- ory or I/O space. Memory mapped regions can request to be located below 1 MByte (Real Mode address space for a PC). Each regi on also has a configurable bus width for the Add-On bus interface. An 8-, 16-, or 32-bit Add-On interface may be selected, for use with a variety of Add-On memory or peripheral devices. Pass-Thru features can be used only when the S5335 is a PCI target. As a target, the S5335 Pass-Thru mode supports single data transfers as well as burst transfers. When accessed with burst transfers, the S5335 supports data transfers at the full PCI band- width. The data transfer rate is only limited by the PCI initiator performing the access and the speed of the Add-On logic. FUNCTIONAL DESCRIPTION To provide the PCI bus Add-On with direct access to Add-On resources, the S5335 has an internal Pass- Thru Address Register (APTA), and a Pass-Thru Data Register (APTD). These registers are connected to both the PCI bus interface and the Add-On bus inter- face. This allows a PCI init iator to perform Pass-Thru writes (data transferred from the PCI bus to the Add- On bus) or Pass-Thru reads (PCI bus requests data from the Add-On bus). The S5335 Pass-Thru interface supports both single cycle (one data phase) and burst accesses (multiple data phases). Pass-Thru Transfers Data transfers between t he PCI bus and the Add-On using the Pass-Thru interface are implemented with a handshaking scheme. If the PCI bus writes to an S5335 Pass-Thru region, Add-On logic must read the data from the S5335 and store it on the Add-On. If the PCI bus reads from a Pass-Thru region, Add-On logic must write data to the S5335. Some applications may require that an address be passed to the Add-On for Pass-Thru accesses. For example, a 4 Kbyte Pass-Thru region on the PCI bus may correspond to a 4 Kbyte block of SRAM on the Add-On card. If a PCI initiator accessed this region, the Add-On would need to know the offset within the memory device to access. The Pass-Thru Address Register (APTA) allows the Add-On to access address information for the current PCI cycle. When the PCI bus performs burst accesses, the APTA register is updated by the S5335 to reflect the address of the cur- rent data phase. For PCI writes to the Add-On, the S5335 transfers the data from the PCI bus into the Pass-Thru Data Regis- ter (APTD). The S5335 captures the data from the PCI bus when TRDY# is asserted. The PCI bus then becomes available for other transfers. When the Pass- Thru data register becomes full, the S5335 asserts the Pass-Thru status signals to indicate to the Add-On that data is present. The Add-On logic may read the data register and assert PTRDY# to indicate the current access is complete. Until the current access com- pletes, the S5335 responds to further Pass-Thru accesses with retries. For PCI reads from the Add-On, the S5335 asserts the Pass-Thru status signals to indicate to the Add-On that data is required. The Add-On logic should write to the Pass-Thru Data Register and assert PTRDY# to com- plete the access. The S5335 does not assert TRDY# to the PCI bus until PTRDY# is asserted by Add-On logic. If the Add-On cannot provide data quickly enough, the S5335 signals a retry to the PCI bus. This allows the PCI bus to perform other tasks, rather than waiting for a slow target.

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 141 Data Sheet Pass-Thru Status/Control Signals The S5335 Pass-Thru regi sters are accessed using the standard Add-On register access pins. The Pass- Thru Address Register (APTA) can, optionally, be accessed using a single, direct access input, PTADR#. Pass-Thru cycle status indicators are provided to con- trol Add-On logic based on the type of Pass-Thru access occurring (single cycle, burst, etc.). The follow- ing signals are provided for Pass-Thru operation: Pass-Thru Add-On Data Bus Sizing Many applications require an 8-bit or 16-bit Add-On bus interface. Pass-Thru regions can be configured to support bus widths other than 32-bits. Each Pass-Thru region can be defined, during initialization, as 8, 16-, or 32-bits. All of the regions do not need to be the same. This feature allows a simple interface to 8-and 16-bit Add-On devices. To support alternate Add-On bus widths, the S5335 performs internal data bus steering. This allows the Add-On interface to assemble and disassemble 32-bit PCI data using multiple Add-On accesses to the Pass- Thru Data Register (APTD). The Add-On byte enable inputs (BE[3:0]#) are used to access the individual bytes or words within APTD. BUS INTERFACE The Pass-Thru interface on the S5335 is a PCI target- only function. Pass-Thru op eration allows PCI initia- tors to read or write resources on the Add-On card. A PCI initiator may access the Add-On with single data phase cycles or multiple data phase bursts. The Add-On interface implements Pass-Thru status and control signals used by logic to complete data transfers initiated by the PCI bus. The Pass-Thru inter- face is designed to allow Add-On logic to function with- out knowledge of PCI bus ac tivity. Add-On logic only needs to react to the Pass-Thru status outputs. The S5335 PCI interface independently interacts with the PCI initiator to control data flow between the devices. The following sections describe the PCI and Add-On bus interfaces. The PCI interface description provides a basic overview of how the S5335 interacts with the PCI bus, and may be useful in system debugging. The Add-On interface description indicates functions required by Add-On logic and details the Pass-Thru handshaking protocol. PCI Bus Interface The S5335 decodes all PCI bus cycle addresses. If the address associated with the current cycle is to one of S5335 Pass-Thru regions, DEVSEL# is asserted. If the Pass-Thru logic is currently idle (not busy finishing a previous Pass-Thru operation), the bus cycle type is decoded and the Add-On Pass-Thru status outputs are set to initiate a transfer on the Add-On side. If the Pass-Thru logic is currently busy completing a previ- ous access, the S5335 signals a retry to PCI initiator. The following sections describe the behavior of the PCI interface for Pass-Thru accesses to the S5335. Single cycle accesses, burst accesses, and target-ini- tiated retries are detailed. PCI Pass-Thru Single Cycle Accesses Single cycle transfers are the simplest PCI bus trans- action. Single cycle transfers have an address phase and a single data phase. The PCI bus transaction starts when an initiator drives address and command information onto the PCI bus and asserts FRAME#. The initiator always deasserts frame before the last data phase. For single cycle transfers, FRAME# is only asserted during the address phase (indicating the first data phase is also the last). Signal Function PTATN# This output indica tes a Pass-Thru access is occurring PTBURST# This output indicates the Pass-Thru access is a PCI burst access PTNUM[1:0] These outputs indicate which Pass-Thru region decoded the PCI address PTBE[3:0]# These outputs indicate which data bytes are valid (PCI writes), or requested (PCI reads) PTWR This output indicates if the Pass-Thru access is a PCI read or a write PTADR# When asserted, this input drives the Pass-Thru Address Register contents onto the Add-On data bus PTRDY# When asserted, this input indicates the current Pass-Thru transfer has been com- pleted by the Add-On BPCLK Buffered PCI bus clock output (to syn- chronize Pass-Thru data register accesses)

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 142 Data Sheet When the S5335 sees FRAM E# asserted, it samples the address and command information to determine if the bus transaction is intended for it. If the address is within one of the defined Pass-Thru regions, the S5335 accepts the transfer (assert DEVSEL#), and stores the PCI address in the Pass-Thru Address Reg- ister (APTA). For Pass-Thru writes, the S5335 responds immedi- ately (asserting TRDY#) and transfers the data from the PCI bus into the Pass-Thru Data Register (APTD). The S5335 then indicates to the Add-On interface that a Pass-Thru write is taking place and waits for Add-On logic to read the APTD register and complete the transfer (assert PTRDY#). Once the S5335 has cap- tured the data from the PCI bus, the transfer is finished from the PCI bus perspective, and the PCI bus becomes available for other transfers. For Pass-Thru reads, the S5335 indicates to the Add- On interface that a Pass-Thru read is taking place and waits for Add-On logic to write the Pass-Thru Data Register and complete the transfer (assert PTRDY#). The S5335 completes the cycle when data is written into the data register. If the Add-On cannot complete the write quickly enough, the S5335 requests a retry from the initiator. See target-requested disconnect information. PCI Pass-Thru Burst Accesses For PCI Pass-Thru burst accesses, the S5335 cap- tures the PCI address and determines if it falls into one of the defined Pass-Thru r egions. Accesses that fall into a Pass-Thru region are accepted by asserting DEVSEL#. The S5335 monitors FRAME# and IRDY# on the PCI bus to identify burst accesses. If the PCI initiator is performing a burst access, the Pass-Thru status indicators notify Add-On logic. For Pass-Thru burst writes, the S5335 responds immediately (asserting TRDY#). The S5335 transfers the first data phase of the burst into the Pass-Thru Data Register (APTD), and stores the PCI address in the Pass-Thru Address Register (APTA). The Add-On interface completes the transfer and asserts PTRDY#. Every time PTRDY# is asserted by the Add-On, the S5335 begins the next data phase. The next data phase is latched into the data register. For burst accesses, APTA is automatically incremented by the S5335 for each data phase. For Pass-Thru burst reads, the S5335 claims the PCI cycle (asserting DEVSEL#). The request for data is passed on to Add-On logic and the PCI address is stored in the APTA register. The Add-On interface completes the transfer and asserts PTRDY#. The S5335 then drives the requested data on the PCI bus and asserts TRDY# to begin the next data phase. The APTA register is automat ically incremented by the S5335 for each data phase. PCI Retry Conditions In some applications, Add-On logic may not be able to respond to Pass-Thru accesse s quickly. In this situa- tion, the S5335 disconnects from the PCI bus, signaling a retry. This indicates that the initiator should try the access again at a later time. This allows other PCI cycles to be run while the logic on the slow target completes the Pass-Thru access. Ideally, when the ini- tiator retries the access, the target has completed the access and can respond to the initiator. With many devices, particularly memories, the first access takes longer than subsequent accesses (assuming they are sequential and not random). For this reason, the PCI specification allows 16 clocks to respond to the first data phase of a PCI cycle and 8 clocks for subsequent data phas es (in the case of a burst) before a retry must be requested by the S5335. The S5335 also requests a retry if an initiator attempts to burst past the end of a Pass-Thru region. The S5335 updates the Pass-Thru Address Register (APTA) for each data phase during bursts, and if the updated address is not within the current Pass-Thru region, a retry is requested. For example, a PCI system may map a 512 byte Pass- Thru memory region to 0DC000h to 0DC1FFh. A PCI initiator attempts a four DW ORD burst with a starting address of 0DC1F8h. The first and second data phases complete (filling the DWORDs at 0DC1F8h and 0DC1FCh), but the third data phase causes the S5335 to request a retry. This forces the initiator to present the address 0DC200h on the PCI bus. If this address is part of another S5335 Pass-Thru region, the device accepts the access. PCI Write Retries When the S5335 requests a retry for a PCI Pass-Thru write, it indicates that the Add-On is still completing a previous Pass-Thru write access. The Pass-Thru Address and Data Register contents (APTA and APTD) are still required for the previous Pass-Thru operation and cannot be updated by the PCI interface until the access completes (the Add-On asserts PTRDY#).

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 143 Data Sheet When the Add-On is busy completing a Pass-Thru write, the S5335 requests an immediate retry for all Pass-Thru region accesses, allowing the PCI bus to perform other operations. PCI Operation Registers may be accessed while the Ad d-On is still completing a Pass-Thru access. Only Pass-Thru region accesses receive retry requests. PCI Read Retries When the S5335 requests a retry for a PCI Pass-Thru read, it indicates that the Add-On could not complete the read in the required time. The Pass-Thru data can- not be read by the PCI interface until the Add-On asserts PTRDY#, indicating the access is complete. If the retry occurs after the Add-On has completed the Pass-Thru operation by writing the appropriate data into the Pass-Thru data register and asserting PTRDY#, the S5335 asserts DEVSEL# and TRDY# to complete the PCI read. If the Add-On still has not com- pleted the Pass-Thru read, the S5335 waits for the required 16 clocks. If th e Add-On completes the access during this time, TRDY# is asserted and the access is finished. If the A dd-On cannot complete the access within 16 clocks, another retry is requested. When the Add-On is busy completing a Pass-Thru read, the S5335 requests an immediate retry for all Pass-Thru region accesses, except the region cur- rently completing the previous access. This allows the PCI bus to perform other ope rations. The next access to the Pass-Thru region which initiated the retry must be to the same address which caused the retry. Another initiator accessing the same Pass-Thru region causes the S5335 to respond with the original initia- tor’s data (for reads). S5335 PCI Operation Registers may be accessed while the Add- On is still completing a Pass-Thru access. Only other Pass-Thru region accesses receive retry requests. Add-On Bus Interface The Pass-Thru address and data registers can be accessed as Add-On operation registers. The inter- face to the Pass-Thru regi sters is described in. The Pass-Thru data register is updated on the rising edge of BPCLK. For this reason, all Pass-Thru inputs must be synchronous to BPCLK. In the following sections the Add-On Pass-Thru interface is described for Pass- Thru single cycle accesses, burst accesses, target- requested retries, and when using 8-bit and 16-bit Add-On data buses. Single Cycle Pass-Thru Writes A single cycle Pass-Thru write operation occurs when a PCI initiator writes a si ngle value to a Pass-Thru region. PCI single cycle tr ansfers consists of an address phase and one data phase. During the address phase of the PCI transfer, the S5335 stores the PCI address into the Pass-Thru Address Register (APTA). If the S5335 determines that the address is within one of its defined Pass-Thru regions, it captures the PCI data into the Pass-Thru Data Register (APTD). Figure 83 shows a single cycle Pass-Thru write access (Add-On read). The Add-On must read the data stored in the APTD register and transfer it to its destination. Note: RD# ma y be asserted for multiple clocks to allow interfacing with slow Add-On devices. Data remains valid until PTRDY# is asserted.

Figure 83. Single Cycle Pass-Thru Write For all Add-On accesses using PTADR for address data when in 16 bit mode, ADR[1] must be held low to get the low address word.

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 146 Data Sheet The Add-On PTADR# input directly accesses the Pass-Thru Address Register and drives the contents onto the data bus (no BPCLK rising edge is required). The byte enables, address, and SELECT# inputs are ignored when PTADR# is asserted. RD# and WR# must not be asserted when PTADR# is asserted. Clock 0: The PCI bus cycle address is stored in the S5335 Pass-Thru Address Register. Clock 1: The PCI address is recognized as an access to Pass-Thru region 1. PCI data is stored in the S5335 Pass-Thru Data Register. PTATN# is asserted to indicate a Pass-Thru access is occurring. Clock 2: Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2. PTBURST# Deasserted. The acce ss has a single data phase. PTNUM[1:0] 01. Indicates the PCI a ccess is to Pass-Thru region 1. PTWR Asserted. The Pass-Th ru access is a write. PTBE[3:0]# 0h. Indicate the Pass-Thru access is 32-bits. The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3. Clock 3: SELECT#, byte enable, and the address inputs remain valid to read the Pass-Thru Data Register at offset 2Ch. RD# is asserted to drive data register contents onto the DQ bus. Clock 4: If PTRDY# is asserted at the rising edge of clock 4, PTATN# is immediately deasserted and the Pass-Thru access is completed at clock 5. Clock 5: If Add-On logic requires more time to read the Pass-Thru Data Register (slower memory or peripherals), PTRDY# can be delayed, extending the cycle. PTRDY# asserted at the rising edge of clock 5 causes PTATN# to be immediately deasserted. Clock 6: PTATN# and PTBURST# deasserted at the rising edge of clock 6 indicates the Pass-Thru access is complete. The S5335 can accept new Pass-Thru accesses from the PCI bus at clock 7.

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 148 Data Sheet Clock 0: PCI address information is stored in the S5335 Pass-Thru Address Register. Clock 1: The PCI address is recognized as an access to Pass-Thru region 1. PCI data for the first data phase is stored in the S5335 Pass-Thru Data Register. PTATN# is asserted by the S5335 to indicate a Pass-Thru access is occur- ring. Clock 2: Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2. PTBURST# Asserted. The access has a multiple data phases. PTNUM[1:0] 01. Indicates the PCI access was to Pass-Thru region 1. PTWR Asserted. The Pass-Thru access is a write. PTBE[3:0]# 0h. Indicate the Pass-Thru access is 32-bits. The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3. Clock 3: SELECT#, byte enables, and the address inputs remain driven to read the Pass-Thru Data Register at offset 2Ch. RD# is asserted to drive data register contents onto the DQ bus. Clock 4: Add-On logic uses the rising edge of clock 4 to store DATA 1 from the S5335. PTRDY# asserted at the rising edge of clock 4 completes the current data phase. DATA 2 is driven on the Add-On bus. Clock 5: Add-On logic uses the rising edge of clock 5 to store DATA 2 from the S5335. PTRDY# asserted at the rising edge of clock 5 completes the current data phase. DATA 3 is driven on the Add-On bus. Clock 6: Add-On logic uses the rising edge of clock 6 to store DATA 3 from the S5335. PTRDY# asserted at the rising edge of clock 6 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to be deasserted. This is how a PCI initiator adds wait states, if it cannot provide data quickly enough. Data on the Add-On bus is not valid. Clock 7: Because PTATN# remains deasserted, Add-On logic cannot store data at the rising edge of clock 7. PTATN# is reasserted, indicating the PCI initiator is no longer adding wait states. DATA 4 is driven on the Add-On bus. Clock 8: Add-On logic uses the rising edge of clock 8 to store DATA 4 from the S5335. PTRDY# asserted at the rising edge of clock 8 completes the current data phase. On the PCI bus, IRDY# has been deasserted again, causing PTATN# to be deasserted. Data on the Add-On bus is not valid. Clock 9: The PCI initiator is still adding wait states. Add-On logic cannot store data while PTATN# is deasserted. Clock 10: Because PTATN# remains deasserted, Add-On logic cannot read data at the rising edge of clock 10. PTATN# is reasserted, indicating the PCI initiator is no longer adding wait states. DATA 5 is driven on the Add-On bus. Clock 11: Add-On logic uses the rising edge of clock 11 to store DATA 5 from the S5335. PTRDY# asserted at the rising edge of clock 11 completes the current data phase. DATA 6 is driven on the Add-On bus. Clock 12: Add-On logic uses the rising edge of clock 12 to store DATA 6 from the S5335. PTRDY# asserted at the rising edge of clock 12 completes the final data phase. Clock 13: PTATN# and PTBURST# deasserted at the rising edge of clock 13 indicates the Pass-Thru access is complete. The S5335 can accept new Pass-Thru accesses from the PCI bus at clock 15.

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 151 Data Sheet Clock 0: PCI address information is stored in the S5335 Pass-Thru Address Register. Clock 1: The PCI address is recognized as an access to Pass-Thru region 1. PCI data for the first data phase is stored in the S5335 Pass-Thru Data Register. PTATN# is asserted by the S5335 to indicate a Pass-Thru access is occurring. Clock 2: Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2. PTBURST# Asserted. The access has multiple data phases. PTNUM[1:0] 01. Indicates the PCI access is to Pass-Thru region 1. PTWR Asserted. The Pass-Th ru access is a write. PTBE[3:0]# 0h. Indicate the Pass-Thru access is 32-bits. The PTADR# input is asserted to read the Pass-Thru Address Register. The byte en-able, address, and SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3. Clock 3: SELECT#, byte enable, and the address inputs remain driven to read the Pass-Thru Data Register at offset 2Ch. RD# is asserted to drive data register contents onto the Add-On data bus. Clock 4: Add-On logic uses the rising edge of clock 4 to store DATA 1 from the S5335. PTRDY# asserted at the rising edge of clock 4 completes the current data phase. DATA 2 is driven on the Add-On bus. Clock 5: Add-On logic is not fast enough to store DATA 2 by the rising edge of clock 5. PTRDY# deasserted at the ris- ing edge of clock 5 extends the current data phase and DATA 2 remains driven on the Add-On bus. Clock 6: Add-On logic uses the rising edge of clock 6 to store DATA 2 from the S5335. PTRDY# asserted at the rising edge of clock 6 completes the current data phase. DATA 3 is driven on the Add-On bus. Clock 7: Add-On logic is not fast enough to store DATA 3 by the rising edge of clock 7. PTRDY# deasserted at the ris- ing edge of clock 7 extends the current data phase is and DATA 3 remains driven on the Add-On bus. Clock 8: Add-On logic uses the rising edge of clock 8 to store DATA 3 from the S5335. PTRDY# asserted at the rising edge of clock 8 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to be deasserted. Data on the Add-On bus is not valid. Clock 9: Because PTATN# remains deasserted, Add-On logic cannot store data at the rising edge of clock 9. PTATN# is reasserted, indicating the PCI initiator is no longer adding wait states. DATA 4 is driven on the Add-On bus. Clock 10: Add-On logic uses the rising edge of clock 10 to store DATA 4 from the S5335. PTRDY# asserted at the rising edge of clock 10 completes the current data phase. DATA 5 is driven on the Add-On bus. PTBURST# is deas- serted, indicating that on the PCI bus, the burst is complete except for the last data phase. Since the data is double buffered, there may be one or two pieces of data available to the Add-On when PTBURST# becomes inactive. This example shows the single data available case. If another piece of data was available, then PTATN# would remain active instead of going inactive at clock 12. Clock 11: Add-On logic is not fast enough to store DATA 5 by the rising edge of clock 11. PTRDY# deasserted at the ris- ing edge of clock 11 extends the data phase and DATA 5 remains driven on the Add-On bus. Clock 12: Add-On logic uses the rising edge of clock 12 to store DATA 5 from the S5335. PTRDY# asserted at the rising edge of clock 12 completes the final data phase. Clock 13: PTATN# deasserted at the rising edge of clock 13 indicates the Pass-Thru access is complete. The S5335 can accept new Pass-Thru accesses from the PCI bus at clock 14.

burst read access (Add-On write) using PTADR#. Figure 88. Pass-Thru Burst Read

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 153 Data Sheet Clock 0: PCI address information is stored in the S5335 Pass-Thru Address Register. The PCI address is recognized as an access to Pass-Thru region 1. PTATN# is asserted by the S5335 to indicate a Pass-Thru access is occurring. PTBURST# is asserted by the S5335, indicating the current Pass-Thru read is a burst. Clock 1: Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2. PTBURST# Deasserted, the S5335 does not yet recognize a PCI burst. PTNUM[1:0] 01. Indicates the PCI a ccess is to Pass-Thru region 1. PTWR Deasserted. The Pass-Thru access is a read. PTBE[3:0]# 0h. Indicate the Pass-T hru access is 32-bits. The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3. Clock 2: SELECT#, byte enables, and the address inputs remain driven to read the Pass-Thru Data Register at offset 2Ch. Clock 3: WR# asserted at the rising edge of clock 3 writes DATA 1 into the S5335. PTRDY# asserted at the rising edge of clock 3 completes the current data phase. Clock 4: WR# asserted at the rising edge of clock 4 writes DATA 2 into the S5335. PTRDY# asserted at the rising edge of clock 4 completes the current data phase. Clock 5: WR# asserted at the rising edge of clock 5 writes DATA 3 into the S5335. PTRDY# asserted at the rising edge of clock 5 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to be deasserted. This is how a PCI initiator adds wait states, if it cannot read data quickly enough. Clock 6: PTATN# remains deasserted at the rising edge of clock 6. The Add-On cannot write DATA 4 until PTATN# is asserted. PTATN# is reasserted during the cycle, indicating the PCI initiator is no longer adding wait states. Add-On logic continues to drive DATA 4 on the Add-On bus. Clock 7: WR# asserted at the rising edge of clock 7 writes DATA 4 into the S5335. PTRDY# asserted at the rising edge of clock 7 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to be deasserted. The PCI initiator is adding wait states. Clock 8: PTATN# remains deasserted at the rising edge of clock 8. The Add-On cannot write DATA 5 until PTATN# is asserted. Add-On logic continues to drive DATA 5 on the Add-On bus. Clock 9: PTATN# remains deasserted at the rising edge of clock 9. The Add-On cannot write DATA 5 until PTATN# is asserted. Add-On logic continues to drive DATA 5 on the Add-On bus. PTATN# is reasserted during the cycle, indicating the PCI initiator is done adding wait states. Clock 10: WR# asserted at the rising edge of clock 10 writes DATA 5 into the S5335. PTRDY# asserted at the rising edge of clock 10 completes the current data phase. Clock 11: WR# asserted at the rising edge of clock 11 writes DATA 6 into the S5335. PTRDY# asserted at the rising edge of clock 11 completes the final data phase. Clock 12: PTBURST# is deasserted at the rising edge of clock 12 indicating the Pass-Thru burst is complete. The S5335 can accept new Pass-Thru accesses from the PCI bus at clock 14. Any data written into the Pass-Thru data reg- ister is not required and is never passed to the PCI interface (as PTRDY# is not asserted at the rising edge of clock 13).

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 155 Data Sheet Clock 0: PCI address information is stored in the S5335 Pass-Thru Address Register. The PCI address is recognized as an access to Pass-Thru region 1. PTATN# is asserted by the S5335 to indicate a Pass-Thru access is occurring. PTBURST# is asserted by the S5335, indicating the current Pass-Thru read is a burst. Clock 1: Pass-Thru status signals indicate what action is required by Add-On logic. Pass-Thru status outputs are valid when PTATN# is active and are sampled by the Add-On at the rising edge of clock 2. PTBURST# Deasserted, the S5335 does not yet recognize a PCI burst. PTNUM[1:0] 01. Indicates the PCI ac cess is to Pass-Thru region 1. PTWR Deasserted. The Pass-Thru access is a read. PTBE[3:0]# 0h. Indicate the Pass-Thru access is 32-bits. The PTADR# input is asserted to read the Pass-Thru Address Register. The byte enable, address, and SELECT# inputs are changed during this clock to select the Pass-Thru Data Register during clock cycle 3. Clock 2: SELECT#, byte enable, and the address inputs remain driven to read the Pass-Thru Data Register at offset 2Ch. Clock 3: WR# asserted at the rising edge of clock 3 writes DATA 1 into the S5335. PTRDY# asserted at the rising edge of clock 3 completes the current data phase. Clock 4: Add-On logic drives DATA 2 on the Add-On bus, but PTRDY# deasserted at the rising edge of clock 4 extends the current data phase. Clock 5: WR# asserted at the rising edge of clock 5 writes DATA 2 into the S5335. PTRDY# asserted at the rising edge of clock 5 completes the current data phase. Clock 6: Add-On logic drives DATA 3 on the Add-On bus, but PTRDY# deasserted at the rising edge of clock 6 extends the current data phase. Clock 7: WR# asserted at the rising edge of clock 7 writes DATA 3 into the S5335. PTRDY# asserted at the rising edge of clock 7 completes the current data phase. On the PCI bus, IRDY# has been deasserted, causing PTATN# to be deasserted. This is how a PCI initiator adds wait states, if it cannot read data quickly enough. Clock 8: PTATN# remains deasserted at the rising edge of clock 8. The Add-On cannot write DATA 4 until PTATN# is asserted. Add-On logic continues to drive DATA 4 on the Add-On bus. PTATN# is reasserted during the cycle, indicating the PCI initiator is done adding wait states. Clock 9: WR# asserted at the rising edge of clock 9 writes DATA 4 into the S5335. PTRDY# asserted at the rising edge of clock 9 completes the current data phase. Clock 10: Add-On logic drives DATA 5 on the Add-On bus, but PTRDY# deasserted at the rising edge of clock 10 extends the current data phase. Clock 11: PTATN# remains deasserted at the rising edge of clock 11. The Add-On does not have to write DATA 5 until PTATN# is asserted. Add-On logic continues to drive DATA 5 on the Add-On bus. PTATN# is reasserted during the cycle, indicating the PCI initiator is done adding wait states. Clock 12: PTRDY# asserted at the rising edge of clock 12 completes the final data phase. Any data written into the Pass- Thru data register is not required and is never passed to the PCI interface (as PTRDY# is not asserted at the ris- ing edge of clock 13). Clock 13: PTATN# and PTBURST# deasserted at the rising edge of clock 13 indicates the Pass-Thru access is complete. The S5335 can accept new Pass-Thru accesses from the PCI bus at clock 14.

Figure 91. Target Requested Retry after the First Data Phase of a Burst Operation 8, completing the data phase with requiring a retry. bus interface signals after the S5335 requests a retry.

Table 57. Byte Lane Steering for Pass-Thru Data Register Read (PCI Write) Table 58. Byte Lane Steering for Pass-Thru Data Register Write (PCI Read)

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 161 Data Sheet CONFIGURATION The S5335 Pass-Thru interface utilizes four Base Address Registers (BADR1:4 ). Each Base Address Register corresponds to a Pass-Thru region. The con- tents of these registers during initialization determine the characteristics of that particular Pass-Thru region. Each region can be mapped to memory or I/O space. Memory mapped devices can, optionally, be mapped below 1 Mbyte and can be identified as prefetchable. Both memory and I/O regions can be configured as 8-, 16-, or 32-bits wide. The designer has the option to use 1, 2, 3, 4 or none of the Pass-Thru regions. Base Address Registers are loaded during initialization from the external non-vola- tile boot device. Without an external boot device, the default value for the BADR r egisters is zero (region disabled). The Base Address Registers are the only registers that define Pass-Thru operation. S5335 Base Address Register Definition Some bits in the Base Address Registers have specific functions. The following bits have special functions: BADR1:4 bits D31:30 are used only by the S5335. When the host reads the Base Address Registers dur- ing configuration cy cles, they always return the same value as D29. If D29 is zero, D31:30 return zero, indi- cating the region is disabled. If D29 is one, D31:30 return one. This operat ion limits each Pass-Thru region to a maximum size of 512 Mbytes of memory. For I/O mapped regions, the PCI specification allows no more than 256 bytes per region. The S5335 allows larger regions to be requested by the Add-On, but a PCI BIOS will not allocate the I/O space and will prob- ably disable the region. Creating a Pass-Thru Region Page 3-40 describes the values that must be pro- grammed into the non-volatile boot device to request various block sizes and char acteristics for Pass-Thru regions. After reset, the S5335 downloads the con- tents of the boot device lo cations 54h, 58h, 5Ch, and 60h into “masks” for the correspondi ng Base Address Registers. The following are some examples for vari- ous Pass-Thru region definitions: During the PCI bus configuration, the host CPU writes all ones to each Base Address Register, and then reads the contents of the registers back. The mask downloaded from the boot device determines which bits are read back as zeros and which are read back D0 Memory or I/O mapping. If this bit is clear, the region should be memory mapped. If this bit is set, the region should be I/O mapped. D2:1 Location of a memory region. These bits request that the region be mapped in a particu- lar part of memory. These bit definitions are only used for memory mapped regions. D3 Prefetchable. For memory mapped regions, the region can be defined as cacheable. If set, the region is cacheable. If this bit is clear, the region is not. D31:30 Pass-Thru region bus width. These two bits are used by the S5335 to define the data bus width for a Pass-Thru region. Regardless of the pro- gramming of other bits in the BADR register, if D31:30 are zeros, the Pass-Thru region is dis- abled. D2 D1 Location 0 0 Anywhere in 32-bit memory space 0 1 Below 1 Mbyte in memory space (Real Mode address space) 1 0 Anywhere in 64-bit memory space (not valid for the S5335)

11 R e s e r v e d

Contents Pass-Thru Region Definition 54h = BFFFF002h Pass-Thru region 1 is a 4Kbyte region, mapped below 1 Mbyte in memory space with a 16-bit Add-On data bus. This memory region is not cacheable. 58h = 3xxxxxxxh Pass-Thru region 2 is disabled. (D31:30 = 00.) 60h = FFFFFF81h Pass-Thru region 3 is a 32-bit, 128 byte I/O-mapped region. 64h = 00000000h Pass-Thru region 4 is disabled.

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 162 Data Sheet as ones. The number of zeros read back indicates the amount of memory or I/O space a particular S5335 Pass-Thru region is requesting. After the host reads all Base Address Registers in the system (as every PCI device implements from one to six), the PCI BIOS allocates memory and I/O space to each Base Address region. The host then writes the start address of each region back into the Base Address Registers. The start address of a region is always an integer multiple of the region size. For example, a 64 Kbyte memory region is always mapped to begin on a 64K boundary in memory. It is important to note that no PCI device can xbe abso- lutely located in system me mory or I/O space. All mapping is determined by the system, not the application. Accessing a Pass-Thru Region After the system is finished defining all Base Address Regions within a system, each Base Address Register contains a physical address. The application software must now find the location in memory or I/O space of its hardware. PCI systems provide BIOS or operating system function calls for application software to find particular devices on the PCI bus based on Vendor ID and Device ID values. This allows application software to access the device’s Configuration Registers. The Base Address Register values in the S5335’s Configuration Space may then be read and stored for use by the program to access application hardware. The value in the Base Address Registers is the physi- cal address of the first lo cation of that Pass-Thru region. Some processor architectures allow this address to be used directly to access the PCI device. For Intel Architecture systems, the physical address must be changed into a Segment/Offset combination. For Real Mode operation in an Intel Architecture sys- tem (device mapped below 1 Mbyte in memory), creating a Segment/Offset pair is relatively simple. To calculate a physical address, the CPU shifts the seg- ment register 4 bits to the left and adds the offset (resulting in a 20 bit physical address). The value in the Base Address Register must be read and shifted 4 bits to the right. This is the segment value and should be stored in one of the Segment registers. An offset of zero (stored in SI, DI or another offset register) accesses the first location in the Pass-Thru region.

beyond those indicated in the DC Characteristics section of this specification is not implied.

1. Input leakage applies to all inputs and bi-directional buffers.
2. PCI Bus signals without pull-up resistors will provide the 3 mA output current. Signals which require a pull-up resistor will provide 6 mA out-

Table 59. Absolute Maximum Ratings Table 60. Recommended Operating Conditions and DC Electrical Characteristics

1. The PCI specification limits all PCI inputs not located on the motherboard to 10 pf (the clock is allowed to be 12 pf).

Table 61. PCI Bus Signals

Table 62. Add-On Bus Signals

1. Minimum times are for unloaded outputs, maximum times are for 10 pF equivalent loads.

Figure 94. PCI Clock Timing Table 63. PCI Bus Timing

1. Valid applies after first access. First access is async with following as sync accesses.
2. State change of RDEMPTY shown below is reference only.

Figure 99. Synchronous RDFIFO# Timing Table 64. Synchronous RDFIFO# Timing

1. State change of WRFULL shown below is reference only. Actual change would indicate no Data 3 written.

Figure 100. Synchronous WRFIFO# Timing Table 65. Synchronous WRFIFO Timing

Figure 101. Asynchronous RD# FIFO Timing Table 66. Asynchronous RD# Register Access Timing

Figure 102. Asynchronous WR# FIFO Timing Table 67. Asynchronous WR# Register Access Timing

1. RD# and SELECT# must both be asserted to drive DQ[31:0] - delay is from the last one asserted.
2. When increasing Setup times, ADR[6:2], BE[3:0]#, SELECT#, and RD# timing relations remain relative to each other as shown.

Figure 103. Synchronous RD# FIFO Timing Table 68. Synchronous RD# FIFO Timing

Figure 104. Synchronous RD# FIFO Timing

Figure 105. Synchronous WR# FIFO Timing Table 69. Synchronous WR# FIFO Timing

Figure 106. Synchronous Multiple WR# FIFO Timing

1. This timing also applies to the use of BE[3:0]# to control DQ[31:0] drive.

Table 70. Pass-Thru Interface Timing

Figure 109. Pass-Thru Status Indicator Timing

1. T represents the clock period for the PCI bus clock (30ns @ 33 MHz).
2. The write cycle time is controlled by both the PCI bus clock and software operations to initiate the write operation of nv memory. This param-

eter is the result of several software operations to the Bus Master Control/Status Register (MCSR). Table 71. Target Byte-Wide Memory Interface Timing

Figure 114. S5335 Pinout and Pin Assignment - 176 LQFP (Low Profile Quad Flat Package)

Figure 115. S5335 – 176 LQFP Package Marking Drawing (Top View) guaranteed to meet the specifications in this document.

Figure 116. Package Physical Dimensions - 176 LQFP Standard Package: Pin Composition - 85Sn/15Pb.

Table 74. S5335 Numerical Pin Assignment - 176 LQFP

1 AD27 t/s 32 PAR t/s 63 DQ28 t/s

2 GND V 33 C/BE1# t/s 64 EQ6/AMREN t/s

3 AD26 t/s 34 GND V 65 VCC V

4 AD25 t/s 35 AD15 t/s 66 DQ27 t/s

5 AD24 t/s 36 AD14 t/s 67 EQ7/AMWEN t/s

6 VCC V 37 AD13 t/s 68 DQ26 t/s

7 C/BE3# t/s 38 VCC V 69 EA0 t/s

8 IDSEL in 39 AD12 t/s 70 MODE in

9 AD23 t/s 40 AD11 t/s 71 BE3#/ADR1 in

10 GND V 41 AD10 t/s 72 GND V

11 AD22 t/s 42 GND V 73 EA1 t/s

12 AD21 t/s 43 AD9 t/s 74 BE2# in

13 AD20 t/s 44 AD8 t/s 75 BE1# in

14 VCC V 45 C/BE0# t/s 76 ADR5 in

15 AD19 t/s 46 VCC V 77 DQ25 t/s

16 AD18 t/s 47 AD7 t/s 78 ADR4 in

17 AD17 t/s 48 AD6 t/s 79 ADR3 in

18 GND V 49 AD5 t/s 80 ADR2 in

19 AD16 t/s 50 GND V 81 EA2 t/s

20 C/BE2# t/s 51 AD4 t/s 82 VCC V

21 FRAME# t/s 52 AD3 t/s 83 RD# in

22 VCC V 53 AD2 t/s 84 EA3 t/s

23 IRDY# t/s 54 VCC V 85 WR# in

24 TRDY# t/s 55 AD1 t/s 86 SELECT# in

25 DEVSEL# t/s 56 AD0 t/s 87 DQ15 t/s

26 GND V 57 DQ31 t/s 88 DQ24 t/s

27 STOP# t/s 58 DQ30 t/s 89 DQ14 t/s

28 LOCK# in 59 DQ29 t/s 90 GND V

29 PERR# t/s 60 GND V 91 DQ13 t/s

30 VCC V 61 EQ4/FWC# t/s 92 DQ12 t/s

31 SERR# o/d 62 EQ5/FRC# t/s 93 EA4 t/s

Table 74. S5335 Numerical Pin Assignment - 176 LQFP (Continued)

94 DQ11 t/s 125 EA8 t/s 156 EA14/FWE out

95 VCC V 126 PTBURST# out 157 EA15/FRF out

96 DQ10 t/s 127 EA9 t/s 158 GND V

97 DQ9 t/s 128 VCC V 159 DQ16 t/s

98 DQ23 t/s 129 PTATN# out 160 EQ0 t/s

99 DQ8 t/s 130 PTRDY in 161 VCC V

100 GND V 131 PTBE0# out 162 EQ1 t/s

101 BE0# in 132 DQ20 t/s 163 EQ2 t/s

102 DQ7 t/s 133 PTBE1# out 164 EQ3 t/s

103 EA5 t/s 134 PTBE2# out 165 INTA# out

104 DQ6 t/s 135 GND V 166 RSVD in

105 DQ22 t/s 136 PTBE3# out 167 RST# in

106 VCC V 137 EA10 out 168 CLK in

107 DQ5 t/s 138 PTNUM1 out 169 GNT# in

108 DQ4 t/s 139 PTNUM0 out 170 REQ# out

109 DQ3 t/s 140 IRQ# out 171 GND V

110 EA6 t/s 141 DQ19 t/s 172 AD31 t/s

111 GND V 142 VCC V 173 AD30 t/s

112 DQ2 t/s 143 SYSRST# out 174 VCC V

113 DQ1 t/s 144 EWR#/SDA t/s 175 AD29 t/s

114 DQ0 t/s 145 GND V 176 AD28 t/s

115 EA7 t/s 146 ERD#/SCL out

116 WRFIFO# in 147 EA11 out

117 VCC V 148 VCC V

118 WRFULL out 149 ADR6 in

119 RDFIFO# in 150 DQ18 t/s

120 DQ21 t/s 151 SNV in

121 RDEMPTY out 152 EA12 out

122 PTADR# in 153 EA13 out

123 GND V 154 BPCLK out

124 PTWR# out 155 DQ17 t/s

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 187 Data Sheet DOCUMENT REVISION HISTORY Revision Date Description 5.01 11/30/05 • Page 23, Removed Figure 6

• Page 183, Added Figure 115, S5335 – 176 LQFP Package Marking Drawing (Top View)
• Page 184, Added Note to below Figure 116 5.00 01/31/05 • Page 107, Updated second paragraph of ADD-ON Bus Interface
• Page 111, Updated first paragraph of FIFO Bus Interface
• Page 163, Table 60, updated Icc
• Page 171, Table 66, added foot note
• Page 172, Table 67, updated t134a and added foot note
• Page 173, Table 68, updated t116 and t120
• Page 177, Table 70, updated t30 4.00 12/16/04 • Page 200, added Development Kit ordering information 3.10 8/26/04 • Page 3, updated feature list.
• Page 29, Table 10 updated SCL signal type
• Page 29, Table 11 updated EA[15:0] signal type
• Page 176, Table 61 updated DEVSEL current
• Page 177, Table 62 corrected BPCLK signal name
• Page 178, Table 63 updated output load and t10
• Page 181, Table 64 updated t144, t146, t148, t149, and t165
• Page 182, Table 65 updated t150, t150a, t151, and t167
• Page 183, Table 66 updated t110a, t114, t118, t133, t133a, and t152
• Page 184, Table 67 updated t111, t119, t134, and t134a
• Page 185, Table 68 updated t112, t112a, t116, t116a, 120, t120a, t125, t156, t124, t124a, and t127
• Page 187, Table 69 updated t113, t117, t123, t123a, t122, t159, and t160
• Page 189, Table 70 updated t10a, t11a, t13, t14, t24, t26, t27, t29, t30, t31, and t32
• Page 195, Figure 115, added signal name to pin 25
• Page 196, updated signal type for pin 130, 137, 146, 147,149, 152, 153, 156, 157, and 166 3.00 5/29/04 • (Page 175, Table 59) Updated T J
• (Page 175, Table 60) Added T J
• (page 175, Table 60) Updated IIL and IIH
• page 198 Updated Ordering part number

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 188 Data Sheet 2.00 4/27/04 • Page 3, updated package information.

• (Page 175, Table 59) Deleted Power Dissipation, added T J and ESD rating
• (Page 175, Table 59) Added T A , Icc, updated VIH, VIL, VOH, VOL, IIL, IIH
• (page 178, Table 63) updated t7
• (page 181, Table 64) updated t144 and t148
• (page 181 Figure 100) updated RDFIFO# timing diagram
• (page 182, Table 65) updated t151 and t151a
• (page 182, Figure 101) updated timing diagram
• (page 183, Table 66) updated t110a, t114a, t129
• (page 184, Table 67) deleted t131
• (page 184, Figure 103) updated t134a labeling
• (page 185, Table 68) updated t112, t116, t120, t125, t124
• (page 185, Figure 104) updated SELECT# timing diagram
• (page 189, Table 70) deleted t28
• (page 191, Table 71) deleted t42
• (page 195, Figure 115) Replace NANDOUT (#148) with Vcc
• (page 196, Figure 116) updated package spec, added thermal management data
• page 197 Updated pin 148
• page 199 added document revision history Revision Date Description

S5335 – PCI Bus Controller, 3.3V Revision 5.01 – November 30, 2005 AMCC Confidential and Proprietary DS1657 189 Data Sheet

Ordering Information

Applied Micro Circuits Corporation 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the la test available datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service wit hout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia- bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the ri ght to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2005 Applied Micro Circuits Corporation. Dev ice S5335 QF = 176 Pin LQFP Blank = Standard AAB = Lead Free Package OptionsPackage P/N S5335DK The Kit includes : Development Kit Manual Evaluation Board Schematic, PCB, CPLD, BOM, NVRAM Tool, Application Software Device Ordering Part Number Development Kit Ordering Part Number Dev ice SXXXX Package/T ype XX Option XXX