PPC440SP-RNC533C

440SP AMCC | Alldatasheet

Document overview

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Technical content

Datasheet sections

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Features

• P o w e r P C‚ 440 processor core operating at up to 667MHz with 32-KB I- and D-caches (with parity checking)
• On-chip 256-KB SRAM configurable as L2 Cache or Ethernet Packet/Code store memory
• Selectable Processor:Bus clock ratios (Refer to the Clocking chapter in the PPC440SP Embedded Processor User’s Manual for details)
• Supports up to 4 GB (2 Chip Selects) of 64-bit/32- bit SDRAM with ECC – DDR1 266-333-400 – DDR2 400-533-667
• Three DDR PCI-X interfaces (32-bit or 64-bit) up to 133 MHz (DDR 266) with support for conventional PCI
• XOR Accelerator with DMA controller
• Optional: High throughput RAID 6 hardware acceleration, performs XOR and Galois Field P & Q parity computations, supports up to 255 drives
• I2O Messaging Unit with two DMA controllers
• External Peripheral Bus (24-bit Address, 8-bit Data) for up to three devices
• One Ethernet 10/100/1000 Mbps half- or full- duplex interface. Operational modes supported are MII and GMII.
• Programmable Interrupt Controller supports interrupts from a variety of sources.
• Programmable General Purpose Timers (GPT)
• Three serial ports (16750 compatible UART)
• Two IIC interfaces
• General Purpose I/O (GPIO) interface available
• JTAG interface for board level testing
• Processor can boot from PCI memory

Description

Designed specifically to address high-end embedded applications for storage, the PowerPC 440SP Embedded Processor (PPC440SP) provides a high- performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation. This chip contains a high-performance RISC processor core, a DDR2 SDRAM controller, configurable 256KB SRAM to be used as L2 cache or software-controlled on-chip memory, three DDR PCI-X bus interfaces, an Ethernet interface, an I2O/DMA controller, control for external ROM and peripherals, optional RAID 6 acceleration, an XOR DMA unit, serial ports, IIC interfaces, and general purpose I/O. Technology: CMOS Cu-11, 0.13mm Package: 29mm, 783-ball, 1mm pitch, Flip Chip- Plastic Ball Grid Array (FC-PBGA) Power (estimated): Less than 6W @533MHz Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5V

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For information about the availability of the following parts, contact your local AMCC sales office. number for identification purposes only. about accessing these registers. Note: Raid-enabled versions (Product Feature = R) require a RAID key license. Figure 1. Order Part Number Key

1. C = Chip Revision Level C
2. fff = Processor Frequency
3. C = Case Temperature Range of -40°C to +100°C

Level C, capable of running at 667 MHz, and is shipped in tray packaging.

Figure 2. PPC440SP Functional Block Diagram The PPC440SP is a System on a chip, which uses IBM® CoreConnect Bus™ Architecture.

• 128-bit Data, 64-bit Address PLB interfaces up to 16 6.66MHz, 2.6GB/s on both the Read and Write data paths (10.6GB/sec total)
• 32-bit OPB interfaces up to 83.33MHz, 333MB/s Address Maps The PPC440SP incorporates two address maps. The first is a fixed processor system memory address map. This address map defines the possible contents of various processor accessible address regions. The second address map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the PPC440SP processor through the use of mtdcr and mfdcr instructions. UART2 UART1IIC1 Processor Core DCR Bus 32KB On-chip Peripheral Bus (OPB) GPIO Accelerator Bridge DDR2 SDRAM External Bus Controller Controller Clock, Control, Reset Power Mgmt JTAG Timers MMU Unit OPB Interrupt Controller Universal I-Cache 32KB D-Cache XOR/DMA PPC440 DDR PCI-X MAL Ethernet DCRs GPT L2 Cache/SRAM 10/100/Low Latency (LL) Segment High Bandwidth (HB) Segment Controller Processor Local Bus (PLB) Trace Arbiter PLB I2O/DMA Host Local 64 bits64 bits Local 32 bits Memory PCI0 PCI1 PCI2 1000 MII, GMII (EBC) (DMA0 and DMA1) (DMA2) Queue IIC0 UART0 (EMAC)

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Table 1. System Memory Address Map (Sheet 1 of 2)

on-chip SRAM can be located anywhere in the Local Memory area of the memory map.

1. The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While locating

volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.

1. When the optional boot from PCI-X memory is selected, t he PCI-X Boot ROM address space begins at 9 FFE0 0000 (128 KB).
2. Unpredictable results on Read and Write operations.
3. Accessed by means of EBC Peripher al Bank Configuration Registers

Table 1. System Memory Address Map (Sheet 2 of 2)

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Table 2. DCR Address Map (4KB of Device Configuration Registers)

1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a sin-

gle 32-bit (word) register. One KW (1024W) equals 4KB (4096 bytes).

PowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006 AMCC Proprietary 9 Data Sheet PowerPC 440 Processor Core The PowerPC 440 processor core is designed for high-end applications such as RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, and so on. It is the first processor core to implement the Book E PowerPC embedded architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture. Features include:

• Up to 667MHz operation
• PowerPC Book E architecture
• 32KB I-cache, 32KB D-cache – Parity on Data and Tag address - checking of parity with error injection
• Three logical regions in D-cache: Locked, Transient, and Normal
• D-cache full-line flush capability
• 41-bit virtual address, 36-bit (64GB) physical address
• Superscalar, out-of-order execution
• Seven-stage pipeline
• Three execution pipelines
• Dynamic branch prediction
• Memory management unit – 64-entry, full associative, unified TLB with parity – Separate instruction and data micro-TLBs – Storage attributes for write-through, cache- inhibited, guarded, and big or little endian
• Debug facilities – Multiple instruction and data range breakpoints – Data value compare – Single step, branch, and trap events – Non-invasive real-time trace interface
• 24 DSP instructions – Single cycle multiply and multiply-accumulate – 32 x 32 integer multiply Internal Buses The PowerPC 440SP Embedded Processor features three standard on-chip buses: the Processor Local Bus (PLB), the On-Chip Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the DDR PCI-X bridge connect to the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for passing status and control information between the processor core and the other on-chip cores. The PLB has a Crossbar arbiter that supports data transfer between the PLB master and two slave segments identified as the Low Latency (LL) and High Bandwidth (HB) segments. The LL segment allows PLB masters CPU and I2O, that are adversely affected by latency, to communicate with slave devices with minimal latency. The HB segment allows PLB masters DMA, XOR, and PCI to exchange large blocks of data with SDRAM and PCI without interfering with the low latency PLB masters. Bus features include:
• P L B – 128-bit Data implementation of the PLB architecture – Separate and simultaneous read and write data paths – 64-bit address – Simultaneous control, address, and data phases – Four levels of pipelining – Byte enable capability suppor ting unaligned transfers

PowerPC 440SP Embedded Processor

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Revision 1.23 - Sept 26, 2006 Data Sheet – 32- and 64-byte burst transfers – 166MHz, maximum 5.2GB/s (simultaneous read and write) – Processor:Bus clock ratios of N:1 and N:2

• O P B – Dynamic bus sizing: 32-, 16-, and 8-bit data path – 32-bit address – 83.33MHz, maximum 333MB/s
• DCR – 32-bit data path – 10-bit address On-Chip SRAM/L2 Cache Features include:
• Four banks of 64KB each for a total of 256KB
• Configurable as either L2 cache or SRAM
• Memory cycles supported: – Single beat read and write, 1 to 16 bytes – Quadword Read and Write burst for 12-bit master – Guarded memory accesses on 4KB boundaries
• Sustainable 2.6GB/s peak bandwidth at 166MHz
• Use as an L2 cache improves proces sor performance and reduces the PLB load – Cache coherency maintained by a hardware snoop mechanism on the Low Latency (LL) PLB or by software – Data Array and Tag Array parity – Unified data and instruction cache – Four-way set associative – 36-bit addressing – Full LRU replacement algorithm – Write through, look aside
• Use as Ethernet packet store a llows Ethernet packets to be held for processing by the Ethernet core DDR PCI-X Interface The DDR PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local memory. There are three separate interfaces supporting 32- and 64-bit PCI-X buses in DDR mode. All three interfaces can be configured for either host or adapter mode. PCI 32/64-bit legacy mode, compatible with PCI Version 2.3, is also supported. Features include:
• P C I - X 2 . 0 – Split transactions – Frequency to 266MHz – 32- and 64-bit address/data bus – ECC supported for 266MHz Mode 2 only
• PCI 2.3 backwar d compatibility – Frequency to 66MHz – 32- and 64-bit bus
• Can be the PCI Host Bus Bridge or an Adapter Device PCI interface
• Optional PCI arbitration function with PCI and PCI-X mode 1, supporting up to four external devices, that can be disabled for use with an external arbiter
• Support for Message Signaled Interrupts (MSI) on both in- and out-bound interrupts
• Simple message passing capability
• Asynchronous to the PLB

PowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006 AMCC Proprietary 11 Data Sheet

• PCI Power Management Version 1.1
• PCI arbitration function with PCI-X Mode 2 support (optional)
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI-X bus memory
• Error tracking/status
• Supports initiation of transfer to the following address spaces: – Single beat I/O reads and writes – Single beat and burst memory reads and writes – Single beat configuration reads and writes (Type 0 and Type 1) – Single beat special cycles
• PCI-X initialization sequence suppor t (frequency & mode determination)
• Support for unexpected split completions
• Outbound transaction split discard timers
• Vital Product Data (VPD) support
• PCI-to-PCI opaque bridge DDR1/DDR2 SDRAM Memory Controller The DDR2 SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, and other discrete devices. Global memory timings, address and bank sizes, and memory addressing modes are programmable. The DDR2 SDRAM controller interfaces to the PLB through a Memory Queue (MQ) function that includes six high- speed 1KB FIFO buffers. Features include:
• Registered and non-registered industry standard DIMMs
• DDR1 266-333-400
• DDR2 400-533-667
• 64-and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)
• 5.32GB/s peak bandwidth for the 64-bit interface
• 2.66GB/s peak bandwidth for the 32-bit interface
• Two chip (bank) select signals supporting two external banks
• CAS latencies of 2, 3, 4, 5, 6, and 7 supported
• Page mode accesses (up to 32 open pages) with configurable paging policy
• Look-ahead request queue with programmable depth of four commands.
• Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current bank)
• Up to 4GB in two external banks
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Sync DRAM configuration by means of mode register and extended mode register set commands
• Power management (self-refresh, suspend, sleep)
• Low Latency & High Bandwidth PLB ports
• Selectable PLB read response (immediate or deferred)
• Programmable Low Latency & High Bandwidth arbitration schemes
• High Bandwidth port has four 1KB read buffers and two1KB write buffers
• Low Latency port has four 128B read buffers and two 128B write buffers External Peripheral Bus Controller (EBC) Features include:
• Support 2MB Boot ROM
• Up to three ROM, EPROM, SRAM, Flash memory, and slave peripherals supported
• Burst and non-burst devices
• 8-bit data bus

PowerPC 440SP Embedded Processor

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Revision 1.23 - Sept 26, 2006 Data Sheet

• 24-bit address, 16MB address space
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device – 256 Wait States for non-burst – 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses – Programmable CSon, CSoff relative to address – Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
• Programmable address mapping Ethernet Controller Interface The Ethernet support interfaces to the physical layer, but the PHY is not included on the chip. Features include:
• One 10/100/1000 interface running in full- and half-duplex modes – One full Media Independent Interface (MII) with 4-bit parallel data transfer – One Gigabit Media Independent Interface (GMII) I2O/DMA Controller The I20/DMA controller provides support for I20 messaging and two DMA controllers (DMA0 and DMA1). I2O manages message frame address (MFA) FIFOs or queues in memory in response to I2O register reads and writes and transfers message frames. The DMAs provide normal memory access support to ease the CPU burden. I2O features include:
• I2O pull- and push-messaging methods
• Dynamic message frame size
• Programmable FIFO size (4096 64-bit MFAs maximum)
• 64-bit and 32-bit MFA sizes
• Three interrupt gathering methods
• Registered MFA prefetch and posting
• 32-bit inbound and outbound doorbell registers
• Four 32-bit scratch pad registers DMA features include:
• Programmable Command Pointer FIFO and Completion FIFO size (up to 2048 DMA operations queued)
• 512-byte/1KB buffering for DMA0/DMA1
• Simultaneous fill and drain (PLB read/write pipelining)
• Any source PLB address to any destination address
• No memory alignment restrictio ns on source or destination
• 32-byte command descriptor block
• Maximum transfer size of 16MB
• 64-bit addressing
• Prefetch indicators for PCI-X buffer management (DMA1 only) Optional RAID 5 and RAID 6 Acceleration Hardware The 440SP provides integrated acceleration hardware that implements high throughput RAID 5 and RAID 6 algorithms to compute the single parity P for RAID 5, and dual parity P & Q for RAID 6. RAID 5 is used to recover data in the case of a single disk drive failure, and RAID 6 provides for data recovery if two disk drives fail. The 440SP offers a choice of two XOR engines for computing the P parity. The first choice is available with the XOR/DMA2 acceleration unit and is used for RAID 5. The second choice for XOR parity computation, along with the RAID 6 Galois Field GF(28)-based polynomial computations, resides inside the Memory Queue functional block

PowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006 AMCC Proprietary 13 Data Sheet of the Memory Controller unit. The RAID 5 and RAID 6 parity computations performed in the Memory Queue are assisted by the two-channel DMA engine of the I2O/DMA controller unit, designated as DMA0 and DMA1. The RAID acceleration hardware also provides various alternatives for balancing load and performance, depending on customer-specific application firmware. The two-way crossbar bus architecture can perform data read and write operations simultaneously, resulting in extremely high throughput. RAID 6 capability is available only with the RAID-enabled part numbers (PPC440SP-RpCfffC) as indicated in the ordering information section of this data sheet. For more information about the RAID 6 implementation, description, and configuration of the acceleration hardware, refer to the following AMCC documents:

• PowerPC 440SP/440SPe RAID Support Application Note
• PowerPC 440SP RAID Addendum to the User’s Manual XOR/DMA2 Controller The XOR/DMA2 controller performs the XOR functions needed to support RAID 5 applications including parity generation and check functions used across data stripes in a RAID 5 system. Features include:
• Computes a bit-wise XOR on up to 16 data str eams with result stored in designated target
• Performs XOR check on up to 16 data streams
• Driven by a linked list Command Bloc k structure specifying control information, source operands, target operand, status information, and link
• Source and target streams may reside anywhere in PLB address space.
• Provides completion status per Command Block to be handled by software at a later time
• 96-byte and 160-byte Command Block formats are supported
• No memory alignment restrictions on operands or target
• Internal register arrays and data buffers are parity protected
• Can be used as a DMA controller (DMA2) with single source and target addresses Serial Port The serial port is compatible with the NS‚ 16570 UART interface. Features include:
• One 8-pin, one 4-pin, and one 2-pin interfaces are provided
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with 16750 register set
• Complete status reporting capability
• Fully programmable serial-i nterface characteristics IIC Bus Interface

PowerPC 440SP Embedded Processor

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Revision 1.23 - Sept 26, 2006 Data Sheet Features include:

• Two IIC interfaces provided
• Support for Philips ‚ Semiconductors I2C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8 - b i t d a t a
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed V DD IIC interface
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully prog rammable configuration registers
• One programmable interrupt request signal
• Full management of all IIC bus protocols
• Programmable error recovery
• Port 0 supports serial Bootstrap ROM with default parameters override at initialization General Purpose Timers (GPT) Provides a time base counter and system timers additional to those defined in the processor core.
• 32-bit time base counter driven by the OPB bus clock
• Seven 32-bit compare timers General Purpose IO (GPIO) Controller
• Controller functions and GPIO registers are progra mmed and accessed by means of memory-mapped OPB bus master accesses.
• The 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose.
• Each GPIO output is a separately programmable tri-state driver (pull-up, pull-down, or open-drain).

PowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006 AMCC Proprietary 15 Data Sheet Universal Interrupt Controller (UIC) Two cascaded Universal Interrupt Controllers (UIC) process internal on-chip and external processor interrupts. Note: Processor specific interrupts (for example, page faults) do not use UIC resources. Features include:

• 6 external interrupts
• 56 internal interrupts
• Edge-triggered or level-sensitive
• Positive- or negative-active
• Non-critical or critical interrupt to the on-chip processor core
• Programmable interrupt priority ordering
• Programmable critical interrupt ve ctor for faster vector processing JTAG Features include:
• IEEE 1149.1 Test Access Port
• IBM RISCWatch Debugger support
• JTAG Boundary Scan Description Language (BSDL)

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Figure 3. 29mm, 783-Ball FC-PBGA Core Package Note: All dimensions are in mm.

1.00 TYP

3.27 MAX

0.4 MIN

This section contains two tables that list external signals. signal or signals in brackets. Table 4 on page 47 lists all the external signals in order by ball (pin) number. Table 3. Signals Listed Alphabetically (Sheet 1 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 2 of 30)

Table 3. Signals Listed Alphabetically (Sheet 3 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 4 of 30)

Table 3. Signals Listed Alphabetically (Sheet 5 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 6 of 30)

Table 3. Signals Listed Alphabetically (Sheet 7 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 8 of 30)

Table 3. Signals Listed Alphabetically (Sheet 9 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 10 of 30)

Table 3. Signals Listed Alphabetically (Sheet 11 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 12 of 30)

Table 3. Signals Listed Alphabetically (Sheet 13 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 14 of 30)

Table 3. Signals Listed Alphabetically (Sheet 15 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 16 of 30)

Table 3. Signals Listed Alphabetically (Sheet 17 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 18 of 30)

Table 3. Signals Listed Alphabetically (Sheet 19 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 20 of 30)

Table 3. Signals Listed Alphabetically (Sheet 21 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 22 of 30)

Table 3. Signals Listed Alphabetically (Sheet 23 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 24 of 30)

Table 3. Signals Listed Alphabetically (Sheet 25 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 26 of 30)

Table 3. Signals Listed Alphabetically (Sheet 27 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 28 of 30)

Table 3. Signals Listed Alphabetically (Sheet 29 of 30)

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Table 3. Signals Listed Alphabetically (Sheet 30 of 30)

Table 4. Signals Listed by Ball Assignment (Sheet 1 of 7)

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Table 4. Signals Listed by Ball Assignment (Sheet 2 of 7)

Table 4. Signals Listed by Ball Assignment (Sheet 3 of 7)

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Table 4. Signals Listed by Ball Assignment (Sheet 4 of 7)

Table 4. Signals Listed by Ball Assignment (Sheet 5 of 7)

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Table 4. Signals Listed by Ball Assignment (Sheet 6 of 7)

Table 4. Signals Listed by Ball Assignment (Sheet 7 of 7)

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following table describes the package level pinout. Alphabetically” on page 17 for the pin (ball) number to which each signal is assigned. Table 5. Pin Summary

PowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006 AMCC Proprietary 55 Data Sheet Multiplexed Signals Some signals are multiplexed on the same pin so that the pin can be used for different functions. The signal names shown in Signal Functional Description are not accompanied by signal names that might be multiplexed on the same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in “Signals Listed Alphabetically” on page 17. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. Strapping Pins One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see “Strapping” on page 83). Note that these are not multiplexed pins since the function of the pins is not programmable. Multipurpose Signals In addition to multiplexing, some pins are also multi-purpose. For example, the PCIX0Ack can function instead as PCIX0ECC1 depending on the PCI interface mode of operation.

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Table 6. Signal Functional Description (Sheet 1 of 7)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

transfer data using 64 bits. Used as ECC1 for PCI-X mode 2. Address/Data bus (bidirectional) for PCI-X0 and PCI-X1. PCI-X Byte Enables for PCI-X0 and PCI-X1. Provides timing to the PCI interface for PCI transactions. Note:See PCIX0:2Par for ECC0. connect the external arbiter's Grant line to this signal.

Even parity indicator or ECC0. Used as ECC0 for PCIX0:2 mode 2. Even parity indicator or ECC7. PCIAD63:32 and BE7:4 for PCI0 and PCI1. Used as ECC7 for PCIX0:1 mode 2. Request line to this signal. Request 64-bit transfer or ECC6. Used as ECC6 for PCIX2 mode 2. Table 6. Signal Functional Description (Sheet 2 of 7)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

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Note:MemAddr14 is the most significant bit (msb). Note:MemData63 is the most significant bit (msb). Table 6. Signal Functional Description (Sheet 3 of 7)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

Note:PerAddr00 is the most significant bit (msb). Note:PerData0 is the most significant bit (msb). Table 6. Signal Functional Description (Sheet 4 of 7)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

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Table 6. Signal Functional Description (Sheet 5 of 7)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

Table 6. Signal Functional Description (Sheet 6 of 7)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

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Filtered voltages input for PCI PLLs (analog circuits). Filtered voltages input for system PLLs (analog circuits). Note:PCI-X operates at 3.3V. DDR SDRAM I/O voltage supply. Performance Screen Ring Oscillator. Table 6. Signal Functional Description (Sheet 7 of 7)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

Table 7. Absolute Maximum Ratings operating at these maximum ratings.

1. The analog voltages used for the on-chip P LLs can be derived from the logic voltage, but must be filtered before entering the
2. This value is not a specificatio n of the operational temperature range, it is a stress rating only.

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Table 8. Package Thermal Specifications

1. Case temperature, T C, is measured at top center of case surface with device soldered to circuit board. For this part the junction

temperature and the case temperature are essentially identical.

1. The case-to-ambient thermal resistance is measured in a JEDEC JESD51-6 standard environment; and may not accurately

predict thermal performance in production equipment environments. The operational case temperature must be maintained.

1. 6.5 °C/W is the theoretical θJB using an infinite heat sink. The larger number applies to the module mounted on a 1.8mm thick,

2P card using 1oz. copper power planes, with an effective heat transfer area of 75mm 2. Table 9. Recommended DC Operating Conditions (Sheet 1 of 3) conditions can affect device reliability.

Table 9. Recommended DC Operating Conditions (Sheet 2 of 3) conditions can affect device reliability.

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1. PCI-X drivers meet PCI-X specifications.
2. The analog voltages used for the on-chip PLLs can be derived fr om the logic voltage, but must be filtered before entering the

PPC440SP. See “Absolute Maximum Ratings” on page 63.

1. Power supply sequencing: It is recommended that the 1.5V Vdd of the core reach its nominal value before applying power to the

complete (0Vdd and Vdd are below 0.4V) before a new power up cycle is started.

1. LPDL is least positive down level; MPUL is most positive up level.
2. Case temperature, T C, is measured at top center of case surface with device soldered to circuit board.

Table 10. Input Capacitance Table 9. Recommended DC Operating Conditions (Sheet 3 of 3) conditions can affect device reliability.

shown in the figure to the right. Table 11. DC Power Supply Loads

1. See “Absolute Maximum Ratings” on page 63 for filter recommendations.

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Figure 4. Clock Timing Waveform Table 12. Clocking Specifications

PowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006 AMCC Proprietary 69 Data Sheet Spread Spectrum Clocking Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440SP. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the PPC440SP the following conditions must be met:

• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC440SP with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency.
• The maximum frequency deviation c annot exceed -1%, and the modulation frequency cannot exceed 40 kHz. In some cases, on-board PPC440SP peripherals impose more stringent requirements.
• Use the Peripheral Bus Clock for logic that is synchron ous to the peripheral bus since this clock tracks the modulation.
• Use the DDR SDRAM MemClkOut sinc e it also tracks the modulation.
• For PCI-X and PCI 66 the maximum spread spectrum is -1% modulated between 30kHz and 33kHz. Notes: 1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. 2. Ethernet operation is unaffected. 3. IIC operation is unaffected. Important: It is up to the system designer to ensure that any SSCG used with the PPC440SP meets the above requirements and does not adversely affect other aspects of the system.

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Table 13. Peripheral Interface Clock Timings Embedded Processor User’s Manual for details.

1. When the PCI-X interface is used to support a legacy PCI interface, the maximum PCIXClk frequency is 66.66MHz.

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Table 14. I/O Specifications—All Speeds

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.

1. These are DDR signals that can change on both the positive and negative clock transitions.

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.

1. These are DDR signals that can change on both the positive and negative clock transitions.

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1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.

1. These are DDR signals that can change on both the positive and negative clock transitions.

Table 15. I/O Specifications—533MHz

1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.

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same frequency as the PLB clock signal and is in phase with the PLB clock signal. SDRAM controller chapter in the PPC440SP Embedded Processor User’s Manual). MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal. The following DDR data is generated by means of simulation and includes logic, driver, package RLC, and lengths. conditions and maximum values are measured under worst case conditions. The signals are terminated as indicated in the figure below for the DDR timing data in the following sections. Figure 7. DDR SDRAM Simulation Signal Termination Model Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data. factors, including the type of memory used and the board layout.

Table 16. DDR SDRAM Output Driver Specifications

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The following timing chart shows the relationship between the signals involved in a DDR write operation. Figure 8. DDR SDRAM Write Cycle Timing Note 1: Clock speed is 333 MHz. TSA and THA are referenced to MemClkOut. Note 2: Memory clock signal is shifted by 90° from the internal clock. Table 17. DDR SDRAM Read and Write I/O Timing—T SA and THA

Note 1: All of the DQS signals are referenced to MemClkOut. Note 2: Clock speed is 333 MHz. Note 3: The TDS values in the table include 1.5 × 3ns cycle at 333 MHz (3 ns × 1.5 = 4.5 ns). and add × 1.5 of the cycle time for the lower clock frequency (TDS - 4.5 + 1.5 TCYC). Note 1: TSD and THD are measured under worst-case conditions. Note 2: Clock speed for the values in the following table is 333 MHz. Table 18. DDR SDRAM Clock to Write DQS Timing—T DS Table 19. DDR SDRAM Write Data to DQS Timing—T SD and THD

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signal. The data must be centered on these edges for correct operation. MCIF0_RODC[RQFD] register field. latency. The data is stored in the eight Flip Flops of Stage 1, so that it can be transferred later, within an 8X period. Figure 9. DDR SDRAM Read Data Path.

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Figure 11. DDR SDRAM Read Cycle Timing Example

reset they are used for normal functions. on the IIC0 port and sets the SDR0_SDSTP0 - SDR0_SDSTP7 registers accordingly. Table 21. Strapping Pin Assignments Serial Bootstrap ROM is disabled (Bit 0 off). Serial Bootstrap ROM is enabled (Bit 0 on). reading 128 bits from the Bootstrap ROM. Serial Bootstrap ROM is enabled (Bit 0 on). reading 256 bits from the Bootstrap ROM.

PowerPC 440SP Embedded Processor

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Revision 1.23 - Sept 26, 2006 Data Sheet Document Revision History Revision Date Description 1.23 Sept 26, 2006 Corrected Package Thermal Specifications table where the letter q appeared instead of the symbol for theta. 1.22 Sept 22, 2006 Updated Recommended DC Operating Conditions table. 1.21 Sept 12, 2006 Updated Processor Clock va lues in Clocking Specifications table.

1.20 June 27, 2006 Updated Recommended DC Op Conditions and Signal Functional Description tables for PCI-X

DDR mode 2. 1.19 June 14, 2006 Updated signal lists. 1.18 May 23, 2006 Fixed doc issue for PEROE signal in Signal Functional Description table. Updated Clocking Specifications table and Serial Bootstrap ROM paragraph. 1.17 May 1, 2006 Updated core package graphic in Figure 3. Added RAID acceleration section to Features, Description, and functional details sections. 1.16 March 8, 2006 Updated ordering and PVR information, part number list, and package diagram. GJG 1.15 March 7, 2006 Removed DMA statement from Serial Port feature statement. Removed reference to notes from PERBLAST entry in signal functional description table. GJG 1.14 March 6, 2006 Updated description of On-Chip SRAM/L2 Cache in Introduction. GJG 1.13 February 9, 2006 Updated Signal Function Description table per JB, updated mailing address and copyright date in disclaimer. GJG

1.12 Nov 15, 2005

Clarified information about DDR SDRAM I/O specifications, updated note in system memory address map table per GB, updated ordering and PVR information, part number list, and package diagram, deleted Preliminary from running head. GJG 1.11 July 12, 2005 Updated leakage current info, case te mp range, DDR SDRAM Signal Termination graphic. GJG 1.10 May 23, 2005 Changed PVR numbers for pass 2. Corrected functional block diagram. Updated Write timing diagrams. GJG 1.09 Mar 8, 2005 Changed part numbers in Ordering and PVR Information section to reflect pass 2. Removed text for unsupported COLA component. GJG

1.08 Feb 16, 2005

Added table to document muxed usage of GPIO signals. Removed additional references to unsupported COLA serial interface. Reformatted LOF and LOT to comply with AMCC style. Updated Description information on first page, sections on DC power supply loads and recommended DC operating conditions. GJG 1.07 Jan 19, 2005 Remove references to unsupported COLA serial interface. GJG

1.06 Dec 21, 2004 Update max case temp in Recommended DC Op Conditions table to match Ordering and PVR

Information table. GJG

1.05 Dec 14, 2004 Update Order Part Number Key information, DDR SDRAM Read data Path block diagram, and

DDR SDRAM Read Cycle Timing example diagram per GB. GJG 1.04 Dec 01, 2004 Update Ordering and PVR information. GJG 1.03 Oct 19, 2004 Update table in Recommended DC Operating Conditions section per Docs Issue Database ID #12. GJG 1.02 Oct 12, 2004 Update functional block diagram and text, signal functional description table, and recommended DC operating conditions section with GB’s comments. GJG 1.01 Sept 08, 2004 First official draft. GJG 1.00 Dec 31, 2003 Create initial data sheet.

PowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006 AMCC Proprietary 85 Data Sheet Applied Micro Circuits Corporation 215 Moffett Park Dr., Sunnyvale, CA 94089 Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the latest available datasheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia- bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the ri ght to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED , INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2006 Applied Micro Circuits Corporation.