S524C20D10 SAMSUNG | Alldatasheet

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S524C20D10/20D20/80D40/80D80 1K/2K/4K/8K-bit Serial EEPROM with software write protect Data Sheet 4 - 1 OVERVIEW The S524C20D10/20D20/80D40/80D80 serial EEPROM has a 1,024/2,048/4,096/8,192 - bit (128/256/512/1,024 - byte) capacity, supporting the standard I 2 C™ - bus serial interface. It is fabricated using Samsung’s most advanced CMOS technology. Important featur es are a hardware - based write protection circuit for the entire memory area and software - based write protection logic for the lower 128 bytes. Hardware - based write protection is controlled by the state of the write - protect (WP) pin. The software - based method is one - time programmable and permanent. Using one - page write mode, you can load up to 16 bytes of data into the EEPROM in a single write operation. Another significant feature of the S524C20D10/20D20/80D40/80D80 is its support for fast mode and standard mode.

FEATURES

  • Two - wire serial interface
  • Automatic word address increment EEPROM storage area
  • 16 - byte page buffer
  • Typical 3.5 ms write cycle time with auto - erase function
  • Hardware - based write protection for the entire EEPROM (using the WP pin)
  • Software - based write protection for the lower 128 - byte EEPROM
  • EEPROM programming voltage generated on chip
  • 1,000,000 erase/write cycles
  • 100 years data retention Operating Character istics
  • Operating voltage — 2.5 V to 5.5 V (write) — 2.2 V to 5.5 V (read)
  • Operating current — Maximum write current: < 3 mA at 5.5 V — Maximum read current: < 200 µA at 5.5 V — Maximum stand - by current: < 5 µA at 3.3 V
  • Operating temperature range — – 25°C to + 70°C (commercial) — – 40°C to + 85°C (industrial)
  • Operating clock frequencies — 100 kHz at standard mode — 400 kHz at fast mode
  • Electrostatic discharge (ESD) — 3,000 V (HBM) — 300 V (MM) Packages
  • 8 - pin DIP, SOP, and TSSOP

S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM DA TA SHEET 4 - 2 Start/Stop Logic Slave Address Comparator Word Address Pointer Row decoder EEPROM Cell Array 128 x 8 bits 256 x 8 bits 512 x 8 bits 1024 x 8 bits HV Generation Timing Control Control Logic Column Decoder Data Register D OUT and ACK SCL WP SDA Figure 4 - 1. S524C20D10/20D20/80D40/80D80 Block Diagram

DATA SHEET S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM 4 - 3 S524C20D10/20D20/ 80D40/80D80 V CC WP SCL SDA A0 A1 A2 V SS NOTE: The S524C20D10/20D20/80D40/80D80 is available in 8-pin DIP, SOP, and TSSOP package. Figure 4 - 2. Pin Assignment Diagram Table 4 - 1. S524C20D10/20D20/80D40/80D80 Pin Descriptions Name Type Description Circuit Type A0, A1, A2 Input Input pins for device address selection. To configure a device address, these pins should be connected to the V CC or V SS of the device. V SS – Ground pin. – SDA I/O Bi - directional data pin for the I 2 C - bus serial data interface. Schmitt trigger input and open - drain output. An external pull - up resistor must be connected to V CC. Typical values for this pull - up resistor are 4.7 k Ω (100 kHz) and 1 k Ω (400 kHz). SCL Input Schmitt trigger input pin for serial clock input. 2 WP Input Input pin for hardware write protection control. If you tie this pin to V CC, the write function is disabled to protect previously written data in the entire memory; if you tie it to V SS , t he write function is enabled. V CC – Single power supply. – NOTE : See the following page for diagrams of pin circuit types 1, 2, and 3.

DATA SHEET S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM 4 - 5 FUNCTION DESCRIPTION I2 C - BUS INTERFACE The S524C20D10/20D20/80D40/80D80 supports the I 2 C - bus serial interface data transmission protocol. The two - wire bus consists of a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to V CC by a pul l- up resistor that is located somewhere on the bus. Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to eight S524C20D10/20D20 (four for S524C80D40, two for S524C80D80) devices can be connected to the same I 2 C - bus as slaves (see Figure 4 - 6). Both the master and sl aves can operate as transmitter or receiver, but the master device determines which bus operating mode would be active. SDA Bus Master (Transmitter/ Receiver) MCU S524C20D20 Tx/Rx A0 A1 A2 Slave 1 To V CC or V SS S524C20D20 Tx/Rx A0 A1 A2 Slave 2 To V CC or V SS S524C20D20 Tx/Rx A0 A1 A2 Slave 3 To V CC or V SS S524C20D20 Tx/Rx A0 A1 A2 Slave 8 To V CC or V SS R V CC R V CC SCL NOTES: 1. The A0 does not affect the device address of the S524C80D40. 2. The A0, A1 do not affect the device address of the S524C80D80. Figure 4 - 6. Typical Configuration (16 Kbits of Memory on the I 2 C - Bus)

S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM DA TA SHEET 4 - 6 I2 C - BUS PROTOCOLS Here are several rules for I 2 C - bus transfers: — A new data transfer can be initiated only when the bus is currently not busy. — MSB is always transferred first in transmitting data. — During a data transfer, the data line (SDA) must remain stable whenever the clock line (S CL) is High. The I 2 C - bus interface supports the following communication protocols:

  • Bus not busy : The SDA and the SCL lines remain High level when the bus is not active.
  • Start condition : Start condition is initiated by a High - to - Low transition of the SDA line while SCL remains High level. All bus commands must be preceded by a start condition.
  • Stop condition : A stop condition is initiated by a Low - to - High transition of the SDA line while SCL remains High level. All bus operations must be completed by a stop condition (see Figure 4 - 7). SCL SDA Start Condition Data or ACK Valid Data Change ~~~~ Stop Condition Figure 4 - 7. Data Transmission Sequence
  • Data valid : Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimite d.
  • ACK (Acknowledge) : An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it successfully received the eight bits of data (see Figure 4 - 8). But the slave does not send an ACK if an internal write cycle is still in progress. In data read operations, the slave releases the SDA line after tran smitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand - by mode.

DATA SHEET S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM 4 - 7 Master SCL Line Data from Transmitter ACK ACK from Receiver Bit 9Bit 1 Figure 4 - 8. Acknowledge Response From Receiver

  • Slave Address : After the master initiates a Start condition, it must output the address of the device to b e accessed. The most significant four bits of the slave address are called the “device identifier”. The identifier for the S524C20D10/20D20/80D40/80D80 is “1010B”. The next three bits comprise the address of a specific device. The device address is defined by the state of the A0, A1 and A2 pins. Using this addressing scheme, you can cascade up to eight S524C20D10/20D20 or four S524C80D40 or two for S524C80D80 on the bus (see Table 4 - 2 below). The b1 for S524C80D40 or the b1, b2 for S524C80D80 are used by t he master to select which of the blocks of internal memory (1 block = 256 words) are to be accessed. The bits are in effect the most significant bit of the word address.
  • Read/Write : The final (eighth) bit of the slave address defines the type of operation to be performed. If the R /W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed. Table 4 - 2. Slave Device Addressing Function Device Identifier Device Address R/ W Bit b7 b6 b5 b4 b3 b2 (note) b1 (note) b0 Read 1 0 1 0 A 2 A1 A0 1 Write 1 0 1 0 A2 A1 A0 0 Write - protect 0 1 1 0 A2 A1 A0 0 NOTE: The b1 for the S524C80D40 or the b2, b1 for the S524C80D80 correspond to the MSB of the memory array address word.

S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM DA TA SHEET 4 - 8 BYTE WRITE OPERATION In a complete byte write operation, the master transmits the slave address, word address, and one data byte to the S524C20D10/20D20/80D40/80D80 slave device (see Figure 4 - 9). Slave AddressStart Word Address Data Stop A C K A C K A C K Figure 4 - 9. Byte Write Operation Following the Start condition, the master sends the devic e identifier (4 bits), the device address (3 bits), and an R /W bit set to “0” onto the bus. Then the addressed S524C20D10/20D20/80D40/80D80 generates an ACK and waits for the next byte. The next byte to be transmitted by the master is the word address. This 8 - bit address is written into the word address pointer of the S524C20D10/20D20/80D40/80D80. When the S524C20D10/20D20/80D40/80D80 receives the word address, it responds by issuing an ACK and then waits for the next 8 - bit data. When it receives the data byte, the S524C20D10/20D20/80D40/80D80 again responds with an ACK. The master terminates the transfer by generating a Stop condition, at which time the S524C20D10/20D20/80D40/80D80 begins the internal write cycle. While the internal write cycle is in progress, all S524C20D10/20D20/80D40/80D80 inputs are disabled and the S524C20D10/20D20/80D40/80D80 does not respond to additional requests from the master.

S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM DA TA SHEET 4 - 10 POLLING FOR AN ACK S IGNAL When the master issues a stop condition to initiate a write cycle, the S524C20D10/20D20/80D40/80D80 starts an internal write cycle. The master can then immediately begin polling for an ACK from the slave device. To poll for an ACK signal in a write operation, the maste r issues a start condition followed by the slave address. As long as the S524C20D10/20D20/80D40/80D80 remains busy with the write operation, no ACK is returned. When the S524C20D10/20D20/80D40/80D80 completes the write operation, it returns an ACK and the master can then proceed with the next read or write operation (see Figure 4 - 11). Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Condition Send Slave Address with R/ W bit = "0" Start Next Operation ACK = "0" ? Yes No Figure 4 - 11. Master Polling for an ACK Signal from a Slave Device

DATA SHEET S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM 4 - 11 SOFTWARE - BASED WRITE PROTECTION You can write - protect the lower 128 bytes of the EEPROM, locations 00H – 7FH, in one operation. To do this, you simply write a value to a one - time, write - only register. Once you have applied this write protection, any write attempt to access the lower 128 - byte area is ignored. In other words, the write protection is permanent. The effect of such a failed attempt is processed in the same way as an invalid I 2 C - bus protocol. To enable write protection, you must execute a write operation to the write protection register. To access the write protection reg ister, you use the device address “0110”. The word address and data in this write operation can be any value and the timing and wave form characteristics are identical to a normal byte write operation (see Figure 4 - 12). Slave AddressStart Word Address (Ignored) Stop A C K A C K A C K Data (Ignored) Figure 4 - 12. Write Protection Operation HARDWARE - BASED WRITE PROTECTION You can also write - protect the entire memory area of the S524C20D10/20D20/80D40/80D80. This method of write protection is controlled by the state of the Write Protect (WP) pin. When the WP p in is connected to V CC , any attempt to write a value to the memory is ignored. The S524C20D10/20D20/80D40/80D80 will acknowledge slave and word address, but it will not generate an acknowledge after receiving the first byte of the data. Thus the write cycle will not be started when the stop condition is generated. By connecting the WP pin to V SS , t he write function is allowed for the entire memory. These write protection features effectively change the EEPROM to a ROM in order to prevent data from being o verwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on the bus, but data bytes are not acknowledged.

S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM DA TA SHEET 4 - 12 CURRENT ADDRESS BYTE READ OPERATION The internal word address pointer maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access data at address “n+1”. When the S524C20D10/20D20/80D40/80D80 receives a slave address with the R /W bit set to “1”, it issues an ACK and sends the eight bits of data. The master does not acknowledge the transfer but it does generate a Stop condition. In this way, the S524C20D10/20D20/80D40/80D80 effectively stops the transmission (see Figure 4 - 13). Slave Address DataStart A C K Stop N O A C K Figure 4 - 13. Current Address Byte Read Operation

DATA SHEET S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM 4 - 13 RANDOM ADDRESS BYTE READ OPERATION Using random read operations, the master can access any memory location at any time. Before it issues the slave address with the R /W bit set to “1”, th e master must first perform a “dummy” write operation. This operation is performed in the following steps: 1. The master first issues a Start condition, the slave address, and the word address to be read. (This step sets the internal word address pointer of the S524C20D10/20D20/80D40/80D80 to the desired address.) 2. When the master receives an ACK for the word address, it immediately re - issues a start condition followed by another slave address, with the R /W bit set to “1”. 3. The S524C20D10/20D20/80D40/ 80D80 then sends an ACK and the 8 - bit data stored at the desired address. 4. At this point, the master does not acknowledge the transmission, but generates a stop condition instead. 5. In response, the S524C20D10/20D20/80D40/80D80 stops transmitting data and reverts to its stand - by mode (see Figure 4 - 14). Slave Address Word AddressStart A C K A C K Slave Address A C K N O A C K StopStart Data (n) Figure 4 - 14. Random Address Byte Read Operation

DATA SHEET S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM 4 - 15 ELECTRICAL DATA Table 4 - 3. Absolute Maximum Ratings (T A = 25 °C) Parameter Symbol Conditio ns Rating Unit Supply voltage V CC – – 0.3 to + 7.0 V Input voltage V IN – – 0.3 to + 7.0 V Output voltage V O – – 0.3 to + 7.0 V Operating temperature T A – – 40 to + 85 °C Storage temperature T STG – – 65 to + 150 °C Electrostatic discharge V ESD HBM 3000 V MM 300 Table 4 - 4. D.C. Electrical Characteristics (T A = – 25 °C to + 70 °C (C), – 40 °C to + 85 °C (I), V CC = 2.2 V to 5.5 V when reading, 2.5 V to 5.5 V when writing) Parameter Symbol Conditions Min Typ Max Unit Input low voltage V IL SCL, SDA, A0, A1, A2 – – 0.3 V CC V Input high voltage V IH 0.7 V CC – – V Input leakage current ILI V IN = 0 to V CC – – 10 µA Output leakage current ILO V O = 0 to V CC – – 10 µA Output low voltage V OL IOL = 3 mA, V CC = 2.5 V – – 0.4 V Supply current ICC1 (write) V CC = 5.5 V, 400 kHz – – 3 mA ICC2 (write) V CC = 3.3 V, 100 kHz – – 1.5 ICC3 (read) V CC = 5.5 V, 400 kHz – – 0.2 ICC4 (read) V CC = 3.3 V, 100 kHz – – 0.1 Stand - by current ICC5 V CC = SDA = SCL = 5.5 V, all other inputs = 0 V – – 10 µA ICC6 V CC = SDA = SCL = 3.3 V, all other inputs = 0 V – – 5

S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM DA TA SHEET 4 - 16 Table 4 - 4. D.C. Electrical Characteristics (Continued) (T A = – 25 °C to + 70 °C (C), – 40 °C to + 85 °C (I), V CC = 2.2 V to 5.5 V when reading, 2.5 V to 5.5 V when writing) Parameter Symbol Conditions Min Typ Max Unit Input capacitance C IN 25 °C, 1MHz, V CC = 5 V, V IN = 0 V, A0, A1, A2, SCL and WP pin – – 10 pF Input/output capacitance C I/O 25 °C, 1MHz, V CC = 5 V, V I/O = 0 V, SDA pin – – 10 Table 4 - 5. A.C. Electrical Characteristics (T A = – 25 °C to + 70 °C (C), – 40 °C to + 85 °C (I), V CC = 2.2 V to 5.5 V when reading, 2.5 V to 5.5 V when writing) Parameter Symbol Conditions V CC = 2.2 to 5.5 V (Standard Mode) V CC = 4.5 to 5.5 V (Fast Mode) Unit Min Max Min Max External clock frequency F CLK – 0 100 0 400 kHz Clock high time tHIGH – 4 – 0.6 – µs Clock low time tLOW – 4.7 – 1.3 – Rising time tR SDA, SCL – 1 – 0.3 Falling time tF SDA, SCL – 0.3 – 0.3 Start condition hold time tHD:STA – 4 – 0.6 – Start condition setup time tSU:STA – 4.7 – 0.6 – Data input hold time tHD:DAT – 0 – 0 – Data input setup time tSU:DAT – 0.25 – 0.1 – Stop condition setup time tSU:STO – 4 – 0.6 – Bus free time tBUF Before new transmission 4.7 – 1.3 – Data output valid from clock low (note) Noise spike width tSP – – 100 – 50 ns Write cycle time tWR – – 10 – 10 ms NOTE : When acting as a transmitter, the S524C20D10/20D20/80D40/80D80 must provide an internal minimum delay time to bridge the undefined period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop condition.

S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM DA TA SHEET 4 - 18 CHARACTERISTIC CURVE S NOTE The characteristic values shown in the following graphs are based on actual test measurements. They do not, however, represent guaranteed operating values. (Frequency = 100 kHz) V C C (V) 2 3 4 5 6 IC C (mA) 0.4 0.8 1.2 1.6 2.0 Temp = - 40 °C Temp = - 25 °C Temp = 0 °C Temp = 25 °C Temp = 70 °C Temp = 85 °C Figure 4 - 18. I CC (Write C urrent) vs. V CC

DATA SHEET S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM 4 - 19 (Frequency = 100 kHz) V C C (V) 2 3 4 5 6 IC C ( µA) 120 Temp = - 40 °C Temp = - 25 °C Temp = 0 °C Temp = 25 °C Temp = 70 °C Temp = 85 °C 100 Figure 4 - 19. I CC (Read Current) vs. V CC

S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM DA TA SHEET 4 - 20 (Frequency = 100 kHz) V C C (V) 2 3 4 5 6 IC C ( µA) Temp = - 40 °C Temp = - 25 °C Temp = 0 °C Temp = 25 °C Temp = 70 °C Temp = 85 °C Figure 4 - 20. I CC (Stand - by Current) vs. V CC

DATA SHEET S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM 4 - 21 (T A = 25 °C) V O L (V) 0 3 4 5 6 IO L ( m A) 1 2 V DD = 5.5 V V DD = 3.0 V V DD = 5.0 V V DD = 4.5 V V DD = 4.0 V V DD = 3.5 V Figure 4 - 21. I OL (Output Low Voltage) vs. V OL

S524C20 D 10/20 D 20/80 D 40/80 D 80 SERIAL EEPROM DA TA SHEET 4 - 22 NOTES