S4261P2.7P

S4242 SUMMIT | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131  Campbell, CA 95008  Telephone 408-378-6461  Fax 408-378-6586  www.summitmicro.com © SUMMIT MICROELECTRONICS, Inc. 2000 2025 6.0 4/17/00 Characteristics subject to change without notice

FEATURES

• Precision Dual Voltage Monitor –V CC Supply Monitor - Dual reset outputs for complex microcontroller systems - Integrated memory write lockout function - No external components required  Second Voltage Monitor Output – Separate VLOW output – Generates interrupt to MCU – Generates RESET for dual supply systems - Guaranteed output assertion to V CC - 1V  Watchdog Timer (S42WD42, S42WD61) –1 . 6 s  Memory Internally Organized 2 x8  Extended Programmable Functions Available on SMS24 Dual Voltage Supervisory Circuit With Watchdog Timer(S42WD61) (S42WD42) S4242/S42WD42/S4261/S42WD61  High Reliability – Endurance: 100,000 erase/write cycles – Data retention: 100 years OVERVIEW The S42xxx are a precision power supervisory circuit. It automatically monitors the device’s VCC level and will generate a reset output on two complementary open drain outputs. In addition to the V CC monitoring, the S42xxx also provides a second voltage comparator input. This input has an independent open drain output that can be wire- OR’ed with the RESET I/O or it can be used as a system interrupt. The S42xxx also has an integrated 4k/16k-bit nonvolatile memory. The memory conforms to the industry standard two-wire serial interface. In addition to the reset circuitry, the S42WD42/S42WD61 also has a watchdog timer. BLOCK DIAGRAM PROGRAMMABLE WATCHDOG TIMER GND VCC RESET#2 VTRIP RESET CONTROL RESET7 1.26V SCL 6 SDA 5 2025 T BD 2.0 WRITE CONTROL NONVOLATILE MEMORY ARRAY PROGRAMMABLE RESET PULSE GENERATOR VLOW# UV OV VSENSE 3 (S42WD42, S42WD61)

S4242/S42WD42/S4261/S42WD61 2025 6.0 4/17/00 ABSOLUTE MAXIMUM RATINGS NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability. 2.7V to 4.5V 4.5V to 5.5V Symbol Parameter Conditions Min Max Min Max Units fSCL SCL Clock Frequency 0 100 400 KHz tLOW Clock Low Period 4.7 1.3 µs tHIGH Clock High Period 4.0 0.6 µs tBUF Bus Free Time Before New Transmission 4.7 1.3 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs tHD:STA Start Condition Hold Time 4.0 0.6 µs tSU:STO Stop Condition Setup Time 4.7 0.6 µs tAA Clock to Output SCL Low to SDA Data Out Valid 0.3 3.5 0.2 0.9 µs tDH Data Out Hold Time SCL Low to SDA Data Out Change 0.3 0.2 µs tR SCL and SDA Rise Time 1000 300 ns tF SCL and SDA Fall Time 300 300 ns tSU:DAT Data In Setup Time 250 100 ns tHD:DAT Data In Hold Time 0 0 ns TI Noise Spike Width Noise Suppression Time Constant 100 100 ns @ SCL, SDA Inputs tWR Write Cycle Time 10 10 ms AC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) 2025 PGM T3.0 2025 PGM T2.0 DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol Parameter Conditions Min Max Units SCL = CMOS Levels @ 100KHz V CC =5.5V 3 mA ICC Supply Current (CMOS) SDA = Open All other inputs = GND or VCC VCC =3.3V 2 mA ISB Standby Current (CMOS) SCL = SDA = V CC VCC =5.5V 50 µA All other inputs = GND ILI Input Leakage V IN = 0 To VCC 10 µA ILO Output Leakage V OUT = 0 To VCC 10 µA VIL Input Low Voltage SCL, SDA, RESET# (pin 2) 0.3xV CC V VIH Input High Voltage SCL, SDA, RESET (pin7) 0.7xV CC V VOL Output Low Voltage I OL = 3mA SDA 0.4 V VCC =3.3V 25 µA Temperature Min Max Commercial 0 °C +70 °C Industrial -40 °C +85 °C RECOMMENDED OPERATING CONDITIONS 2025 PGM T1.0

FIGURE 3. RESET OUTPUT TIMING

FIGURE 6. TYPICAL SYSTEM CONFIGURATION USING A PUSH BUTTON RESET AND BATTERY MONITOR CIRCUIT FIGURE 7. TYPICAL SYSTEM CONFIGURATION FOR DUAL RESET WITH V CC MONITOR AND 3.3VOLT MONITOR

8051 Type

S4242/S42WD42/S4261/S42WD61 2025 6.0 4/17/00 ENDURANCE AND DATA RETENTION The S42xxx is designed for applications requiring 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. Reset Controller Description The S42xxx provides a precision RESET controller that ensures correct system operation during brown-out and power-up/-down conditions. It is configured with two open drain RESET outputs; pin 7 is an active high output and pin 2 is an active low output. For proper operation pin 7 should be tied low through a pull-down resistor while pin 2 should be tied high through a resistor connected to V CC . During power-up, the RESET outputs remain active until VCC reaches the VTRIP threshold and will continue driving the outputs for tPURST (200 msec)after reaching VTRIP. The RESET outputs will be valid so long as VCC is > 1.0V. During power-down, the RESET outputs will begin driving active when V CC falls below VTRIP. The RESET pins are I/Os; therefore, the S42xxx can act as a signal conditioning circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset timeout after detecting a low to high transition and the RESET# input will initiate a reset timeout after detecting a high to low transition. Refer to the applications information section for more details on de- vice operation as a reset conditioning circuit. Voltage Sensor Description V SENSE is an auxiliary voltage detection circuit. Its thresh- old is set at 1.25V and it generates a VLOW # output for an under-voltage condition. Because the VLOW # output is open-drain, it can be wire-ORed with the RESET# output or tied directly to an IRQ input on a microcontroller. PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wire- ORed with any number of open-drain or open-collector outputs. RESET# - RESET# is an active low open-drain output. It should be tied high through a pull-up resistor connected to V CC . RESET# is an I/O, therefore it may also be used to condition a RESET# signal generated by another device; it can also be used to debounce a pushbutton input. RESET - RESET is an active high open drain (PFET) output. It should be tied low through a pull-down resistor connected to ground. RESET is an I/O, therefore it may also be used to condition a RESET signal generated by another device. V SENSE - The VSENSE input is used as a second voltage sensing input. The pin is tied to a comparator that uses the precision internal 1.25V reference. VLOW # - VLOW # is an active low open drain output driven low whenever VSENSE is below 1.25V. It is not a timed output and only responds to the state of VSENSE .

FIGURE 10. PAGE/BYTE WRITE MODE address, ACKnowledge and data transfer sequence. The S42xxx is capable of a 16-byte page write operation. respond with an ACKnowledge. all inputs are disabled during the internal write cycle.

FIGURE 13. RANDOM ADDRESS BYTE READ MODE WRITE) followed by the address of the word it is to read. S42xxx to the desired address. the address, acknowledge and data transfer sequence.

FIGURE 14. SEQUENTIAL READ OPERATION (starting with a Random Address READ) ACKnowledge, and issues a STOP conditions. address, acknowledge and data transfer sequence.

S4242/S42WD42/S4261/S42WD61 2025 6.0 4/17/00 .228 (5.80) .035 (.90) .020 (.50) .010 (.25) x45° .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .275 (6.99) TYP. .030 (.762) TYP.

8 Places

.050 (1.27) TYP. .050 (1.270) TYP. .157 (4.00) .150 (3.80) .196 (5.00)1 .189 (4.80) FOOTPRINT 8pn JEDEC SOIC ILL.2

8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

8 Pin PDIP (Type P) Package

.375 (9.525) PIN 1 INDICATOR .015 (.381) Min. .130 (3.302) .100 (2.54) TYP. .018 (.457) TYP. .060 ± .005 (1.524) ± .127 TYP. .130 (3.302) SEATING PLANE .070 (1.778) .0375 (0.952) .300 (7.620) 5°-7°TYP. (4 PLCS) .350 (8.89) .009 ± .002 (.229 ± .051) 0°-15° .250 (6.350) 8pn PDIP/P ILL.3

S4242/S42WD42/S4261/S42WD61 2025 6.0 4/17/00

ORDERING INFORMATION

P = PDIP S = SOIC Package S42 xxx P A Base Part Number Suffix 42 = 4k Bits 61 = 16k Bits WD42 = 4k, Watchdog timer WD61 = 16k, Watchdog timer VTRIP A = 4.5V B = 4.75V 2.7 = 2.7V Blank = 4.5V Prefix

S4242/S42WD42/S4261/S42WD61 2025 6.0 4/17/00 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. I 2C is a trademark of Philips Corporation. © Copyright 2000 SUMMIT Microelectronics, Inc.