Microcontroller

S3P826A

Samsung semiconductor

8-Bit CMOS Microcontroller

Manufacturer: Samsung semiconductor

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2 1 - S3 - C826A/P826A-112002 USER'S MANUAL S3C826A/P826A 8-Bit CMOS Microcontroller Revision 1

S3C826A/P826A PRODUCT OVERVIEW 1- 1

1 PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels. S3C826A MICROCONTROLLER The S3C826A single-chip microcontroller are fabricated using the highly advanced CMOS process. Its design is based on the powerful SAM88RC CPU core. Stop and idle (power-down) modes were implemented to reduce power consumption. The S3C826A is a microcontroller with a 48K-byte mask-programmable ROM embedded. The S3P826A is a microcontroller with a 48K-byte one-time-programmable ROM embedded. Using the SAM88RC modular design approach, the following peripherals were integrated with the SAM88RC CPU core: — Large number of programmable I/O ports (Total 128 pins) — Sync hronous SIO module — Three 8-bit timer/counters — One 16-bit timer/counter — LCD controller/driver — A/D converter with 4 selectable input pins OTP The S3C826A microcontroller is also available in OTP (One Time Programmable) version, S3P826A. The S3P826A microcontroller has an on-chip 48K-byte one-time-programmable EPROM instead of masked ROM. The S3P826A is comparable to S3C826A, both in function and in pin configuration.

PRODUCT OVERVIEW S3 C826A/P826 A 1- 2

FEATURES

SAM88RC CPU core Memory
2064-byte internal register file (includin g LCD display RAM)
48K-byte internal program memory area Instruction Set
78 instructions
Idle and Stop instructions

128 I/O Pins

32 normal I/O pins
96 pins sharing with LCD signals Interrupts
8 interrupt levels and 21 internal sources
Fast interrupt processing feature 8-Bit Basic Timer
Watchdog timer function
4 kinds of clock source Timer/Counter 0
Programmable 8-bit internal timer
External event counter function
PWM and capture function Timer/Counter 1
One 16-bit timer/counter mod e
Two 8-bit timer/counters A/B mode
External event counter function Timer/Counter 2
Programmable 8-bit interval timer
External event counter function Timer/Counter 3
Programmable 8-bit interval timer
External event counter function
PWM and capture function Watch Timer
Interval Time: 3.19ms, 0.25s, 0.5s, 1.0s at 32.768 kHz
0.5/1/2/4 kHz buzzer output selectable Analog to Digital Converter
4-channel analog input
8-bit conversion resolution
25 µs conversion time Serial I/O Interface
8-bit transmit/receive mode
8-bit receive mode
Selectable baud rate or external clock source LCD Controller/Driver
80 segments and 16 common terminals
8, 12, and 16 common selectable
Internal resistor circuit for LCD bias Two Power-Down Modes
Idle mode: only CPU clock stops
Stop mode: system clock and CPU clock stop Oscillation Source
Crystal, ceramic, or RC for main clock
Crystal for sub clock (32.768 kHz) Instruction Execution Time
400 ns at fx=10 MHz (minimum, main clock)
122 µs at fxt=32.768 kHz (sub clock) Operating Temperature Range
–25 °C to +85 °C Operating Voltage Range
2.0 V to 5.5 V at 4 MHz (main clock)
2.4 V to 5.5 V at 8 MHz (main clock)
2.7 V to 5.5 V at 10 MHz (main clock)
2.0 V to 5.5 V at 32.768 kHz (sub clock) Package Type
Pellet only

S3C826A/P826A PRODUCT OVERVIEW 1- 3 BLOCK DIAGRAM I/O Port and Interrupt Control SAM88RC Core 48K-byte ROM 2064-byte Register File TEST V DD1 /V DD2 RESET P0.0-P0.7/ INT0-INT7 P3.4-P3.7/ INT8-INT11 V SS1 /V SS2 LCD Driver/ Controller 8-Bit Timer/Counter0 SIO Basic TimerWatchdog Timer Watch TimerP1.7/BUZ Main OSC Sub OSC Timer 1 P2.0/T0CLK P2.1/T0CAP P2.1/T0OUT/T0PWM X IN X OUT XT IN XT OUT 8-bit Timer A 8-bit Timer B P2.2/T1CLK P2.3/TAOUT P2.4/TBOUT 8-Bit Timer/Counter3 8-Bit Timer/Counter2 P3.0/T2CLK P3.1/T2OUT P3.2/T3CLK P3.3/T3CAP P3.3/T3OUT/T3PWM P1.4/SCK P1.6/SI P1.5/SO 8-Bit ADCAVDD P1.0-P1.3/AD0-AD3 P15.7-P15.0/ COM0-COM7 P13.7-P4.0/ SEG0-SEG79 V LC1 -V LC5 P14.7-P14.0/ COM8-COM15/ SEG87-SEG80 P3.0/T2CLK P3.1/T2OUT P3.2/T3CLK P3.4-P3.7/INT8-INT11 P2.0/T0CLK P2.2/T1CLK P2.3/TAOUT P2.4/TBOUT P0.0-P0.7/ INT0-INT7 P2.5 P2.6 P2.7 Port 2 Port 0 Port 3 Port 1 P1.0/AD0 P1.1/AD1 P1.2/AD2 P1.3/AD3 P1.4/SCK P1.5/SO P1.6/SI P1.7/BUZ Port 8 Port 9 Port 11 Port 13 Port 14 Port 15 P3.3/T3OUT/ T3PWM/T3CAP P2.1/T0OUT/ T0PWM/T0CAP Port 10 Port 12 Port 7 Port 6 Port 5 Port 4 P4.0-P4.7/ SEG79-SEG72 P5.0-P5.7/ SEG71-SEG64 P6.0-P6.7/ SEG63-SEG56 P7.0-P7.7/ SEG55-SEG48 P8.0-P8.7/ SEG47-SEG40 P9.0-P9.7/ SEG39-SEG32 P10.0-P10.7/ SEG31-SEG24 P11.0-P11.7/ SEG23-SEG16 P12.0-P12.7/ SEG15-SEG8 P13.0-P13.7/ SEG7-SEG0 P14.0-P14.7/COM15-COM8/ SEG80-SEG87 P15.0-P15.7/ COM7-COM0 Figure 1-1. Block Diagram

PRODUCT OVERVIEW S3 C826A/P826 A 1- 4 PIN ASSIGNMENT COM0/P15.7 P2.0/T0CLK P2.1/T0OUT/T0PWM/T0CAP P2.2/T1CLK P2.3/TAOUT P2.4/TBOUT P2.5 P2.6 P2.7 P3.0/T2CLK P3.1/T2OUT P3.2/T3CLK P3.3/T3OUT/T3PWM/T3CAP INT8/P3.4 INT9/P3.5 INT10/P3.6 INT11/P3.7 V DD1 V SS1 X OUT X IN TEST XT IN XT OUT RESET P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 P0.4/INT4 P0.5/INT5 P0.6/INT6 P0.7/INT7 P1.0/AD0 P1.1/AD1 P1.2/AD2 COM1/P15.6 COM2/P15.5 COM3/P15.4 COM4/P15.3 COM5/P15.2 COM6/P15.1 COM7/P15.0 SEG87/COM8/P14.7 SEG86/COM9/P14.6 SEG85/COM10/P14.5 SEG84/COM11/P14.4 SEG83/COM12/P14.3 SEG82/COM13/P14.2 SEG81/COM14/P14.1 SEG80/COM15/P14.0 SEG0/P13.7 SEG1/P13.6 SEG2/P13.5 SEG3/P13.4 SEG4/P13.3 SEG5/P13.2 SEG6/P13.1 SEG7/P13.0 SEG8/P12.7 SEG9/P12.6 SEG10/P12.5 SEG11/P12.4 SEG12/P12.3 SEG13/P12.2 SEG14/P12.1 SEG15/P12.0 SEG16/P11.7 SEG17/P11.6 SEG18/P11.5 SEG19/P11.4 SEG20/P11.3 P1.3/AD3 P1.4/SCK P1.5/SO P1.6/SI P1.7/BUZ V LC1 V LC2 V LC3 V LC4 V LC5 AVDD SEG79/P4.0 SEG78/P4.1 SEG77/P4.2 SEG76/P4.3 SEG75/P4.4 SEG74/P4.5 SEG73/P4.6 SEG72/P4.7 SEG71/P5.0 SEG70/P5.1 SEG69/P5.2 SEG68/P5.3 SEG67/P5.4 SEG66/P5.5 SEG65/P5.6 SEG64/P5.7 SEG63/P6.0 SEG62/P6.1 SEG61/P6.2 SEG60/P6.3 SEG59/P6.4 SEG58/P6.5 SEG57/P6.6 SEG56/P6.7 SEG55/P7.0 SEG21/P11.2 SEG22/P11.1 SEG23/P11.0 SEG24/P10.7 SEG25/P10.6 SEG26/P10.5 SEG27/P10.4 SEG28/P10.3 SEG29/P10.2 SEG30/P10.1 SEG31/P10.0 SEG32/P9.7 SEG33/P9.6 SEG34/P9.5 SEG35/P9.4 SEG36/P9.3 SEG37/P9.2 SEG38/P9.1 V DD2 V SS2 SEG39/P9.0 SEG40/P8.7 SEG41/P8.6 SEG42/P8.5 SEG43/P8.4 SEG44/P8.3 SEG45/P8.2 SEG46/P8.1 SEG47/P8.0 SEG48/P7.7 SEG49/P7.6 SEG50/P7.5 SEG51/P7.4 SEG52/P7.3 SEG53/P7.2 SEG54/P7.1 S3C826A (144-QFP-2828-AN) 108 107 106 105 104 103 102 101 100 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 NOTE: The package of S3C826A is only for engineer sample. Figure 1-2. S3C826A Pin Assignments (144-QFP-2828-AN)

S3C826A/P826A PRODUCT OVERVIEW 1- 5 PIN DESCRIPTIONS Table 1-1. S3C826A Pin Descriptions Pin Names Pin Type Pin

Description

P0.0-P0.7 I/O 1-bit-programmable I/O port. Schmitt trigger input or push-pull, open- drain output and software assignable pull- ups. E-4 26-33 INT0-INT7 P1.0-1.3 I/O F-16A 34-37 AD0-AD3 P1.4 P1.5 P1.6 P1.7 E-4 38-41 SCK SO SI BUZ P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 I/O 1-bit-programmable I/O port. Schmitt trigger input or push-pull, open- drain output and software assignable pull- ups. E-4 2 T0CLK T0OUT/T0PWM/T0CAP T1CLK TAOUT TBOUT P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 I/O 1-bit-programmable I/O port. Schmitt trigger input or push-pull, open- drain output and software assignable pull- ups. E-4 10 T2CLK T2OUT T3CLK T3OUT/T3PWM/T3CAP INT8 INT9 INT10 INT11 P4.0–P4.7 I/O 4-bit-programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. H-32 48-55 SEG79-72 P5.0–P5.7 I/O Same as Port 4 H-32 56-63 SEG71-64 P6.0–P6.7 I/O Same as Port 4 H-32 64-71 SEG63-56 P7.0–P7.7 I/O Same as Port 4 H-32 72-79 SEG55-48 P8.0–P8.7 I/O Same as Port 4 H-32 80-87 SEG47-40 P9.0–P9.7 I/O Same as Port 4 H-32 88, 91-97 SEG39-32 P10.0-P10.7 I/O Same as Port 4 H-32 98-105 SEG31-24 P11.0-P11.7 I/O Same as Port 4 H-32 106-113 SEG23-16 P12.0-P12.7 I/O 8-bit-programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. H-32 114-121 SEG15-8 P13.0-P13.7 I/O Same as Port 12 H-32 122-129 SEG7-0 P14.0-P14.7 I/O Same as Port 12 H-32 130-137 SEG80-87/COM15-8 P15.0-P15.7 I/O Same as Port 12 H-32 138-144, 1 COM7-0 1-bit-programmable I/O port. Schmitt trigger input or push-pull, open- drain output and software assignable pull-ups.

PRODUCT OVERVIEW S3 C826A/P826 A 1- 6 Table 1-1. S3C826A Pin Descriptions (Continued) Pin Names Pin Type Pin V SS1 , V DD1 – Power input pins for core block – 19, 18 – V SS2 , V DD2 – Power input pins for peripheral block – 89, 90 – AV DD – Power input pins for AD Converter – 47 – X IN , X OUT – Main oscillator pins – 21, 20 – XT IN , XT OUT – Sub oscillator pins – 23, 24 – TEST – Chip test input pin Hold GND when the device is operating – 22 – RESET I RESET signal input pin. Schmitt trigger input with internal pull-up resistor. B 25 – INT0-INT7, INT8-INT11 I/O External interrupts input with noise filter. E-4 26-33 14-17 P0.0-P0.7, P3.4-P3.7 T0CLK I/O Timer 0 external clock input. E-4 2 P2.0 T0OUT I/O Timer 0 clock output E-4 3 P2.1 T0PWM I/O Timer 0 PWM output E-4 3 P2.1 T0CAP I/O Timer 0 capture input E-4 3 P2.1 T1CLK I/O Timer 1/A external clock input. E-4 4 P2.2 TAOUT I/O Timer 1/A clock output E-4 5 P2.3 TBOUT I/O Timer B clock output E-4 6 P2.4 T2CLK I/O Timer 2 external clock input. E-4 10 P3.0 T2OUT I/O Timer 2 clock output E-4 11 P3.1 T3CLK I/O Timer 3 external clock input. E-4 12 P3.2 T3OUT I/O Timer 3 clock output E-4 13 P3.3 T3PWM I/O Timer 3 PWM output E-4 13 P3.3 T3CAP I/O Timer 3 capture input E-4 13 P3.3 AD0-AD3 I/O AD Converter input F-16A 34-37 P1.0-P1.3 BUZ I/O Buzzer signal output E-4 41 P1.7 SCK, SO, SI I/O Serial clock, serial data output, serial data input V LC1 - V LC5 – LCD bias voltage input pins – 42-46 – COM0-COM7 I/O LCD Common signal output H-32 1, 144-138 P15.7-P15.0 COM8-COM15 I/O LCD Common signal output H-32 137-130 P14.7-P14.0 SEG87-SEG80 SEG0-SEG79 I/O LCD Segment signal output H-32 129-48 P13.7-P4.0 SEG80-SEG87 I/O LCD Segment signal output H-32 130-137 P14.0-P14.7 COM15-COM8

S3C826A/P826A ADDRESS SPACES 2- 1

2 ADDRESS SPACES

The S3C826A microcontroller has two types of address space: — Internal program memory (ROM) — Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3C826A has an internal 48-Kbyte mask-programmable ROM. The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing modes. An 176-byte LCD display register file is implemented. There are 2,141 mapped registers in the internal register file. Of these, 2,064 are for general-purpose. (This number includes a 16-byte working register common area used as a "scratch area" for data operations, eight 192-byte prime register areas, and eight 64-byte areas (Set 2)). Thirteen 8-bit registers are used for the CPU and the system control, and 64 registers are mapped for peripheral controls and data registers. Three register locations are not mapped.

ADDRESS SPACES S3C8 26A/P826A 2- 2 PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S3C826A has 48K bytes internal mask- programmable program memory. The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory. If you use the vector address area to store a program code, be careful not to overwrite the vector addresses stored in these locations. The ROM address at which a program execution starts after a reset is 0100H. (Decimal) 49,151 (HEX) BFFFH 48K-bytes Internal Program Memory Area FFH255 Interrupt Vector Area 0H0 Figure 2-1. Program Memory Address Space

S3C826A/P826A ADDRESS SPACES 2- 3 REGISTER ARCHITECTURE In the S3C826A implementation, the upper 64-byte area of register files is expanded two 64 -byte areas, called set 1 and set 2 . The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. In case of S3C826A the total number of addressable 8-bit registers is 2,141. Of these 2,141 registers, 13 bytes are for CPU and system control registers, 64 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers, and 2048 registers are for general-purpose use, page 0-page 7 (including 176 bytes for LCD display registers). You can always address set 1 register locations, regardless of which of the eight register pages is currently selected. Set 1 locations, however, can only be addressed using register addressing modes. The extension of register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer (PP). Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2–1. Table 2-1. S3C826A Register Type Summary Register Type Number of Bytes General-purpose registers (including the 16-byte common working register area, eight 192-byte prime register area (including LCD data registers), and eight 64-byte set 2 area). CPU and system control registers Mapped clock, peripheral, I/O control, and data registers 2,064 Total Addressable Bytes 2,141

ADDRESS SPACES S3C8 26A/P826A 2- 4 System Registers (Register Addressing Mode) Working Registers (Working Register Addressing Only) Bank 1 System and Peripheral Control Registers Bank 0 System and Peripheral Control Registers (Register Addressing Mode) Set 1 FFH Bytes E0H DFH D0H CFH C0H Prime Data Registers (All Addressing Modes) LCD Display Register ~ ~ Page 7AFH 00H 176 Bytes Page 1 Page 7 Page 1 Page 0 Prime Data Registers (All Addressing Modes) Page 0 Set 2 Registers (Indirect Register, Indexed Mode, and Stack Operations) ~ ~ C0H BFH 00H FFH FFH FFH FFH 192 Bytes Bytes 256 Bytes FFH Figure 2-2. Internal Register File Organization

S3C826A/P826A ADDRESS SPACES 2- 5 REGISTER PAGE POINTER (PP) The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3C826A microcontroller, a paged register file expansion is implemented for LCD data registers, and the register page pointer must be changed to address other pages. After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always "0000", automatically selecting page 0 as the source and destination page for register addressing. Register Page Pointer (PP) DFH ,Set 1, R/W Destination register page selection bits:

0000 Destination: Page 0

Source register page selection bits:

0000 Source: Page 0

NOTE: A hardware reset operation writes the 4-bit destination and source values shown above to the register page pointer. These values should be modified to address other pages. Figure 2-3. Register Page Pointer (PP) FF PROGRAMMING TIP — Using the Page Pointer for RAM clear (Page 0, Page 1) LD PP,#00H ; Destination ← 0, Source ← 0 SRP #0C0H LD R0,#0FFH ; Page 0 RAM clear starts RAMCL0 CLR @R0 DJNZ R0,RAMCL0 CLR @R0 ; R0 = 00H LD PP,#10H ; Destination ← 1, Source ← 0 LD R0,#0FFH ; Page 1 RAM clear starts RAMCL1 CLR @R0 DJNZ R 0,RAMCL1 CLR @R0 ; R0 = 00H NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.

ADDRESS SPACES S3C8 26A/P826A 2- 6 REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and bank 1 . The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing. The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H–FFH) contains 61 mapped system and peripheral control registers. The lower 32-byte area contains 16 system registers (D0H–DFH) and a 16-byte common working register area (C0H–CFH). You can use the common working register area as a “scratch” area for data operations being performed in other areas of the register file. Registers in set 1 locations are directly accessible at all times using Register addressing mode. The 16-byte working register area can only be accessed using working register addressing (For more information about working register addressing, please refer to Chapter 3, "Addressing Modes.") REGISTER SET 2 The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another 64 bytes of register space. This expanded area of the register file is called set 2 . For the S3C826A, the set 2 address range (C0H–FFH) is accessible on pages 0-7. The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only Register addressing mode to access set 1 locations. In order to access registers in set 2, you must use Register Indirect addressing mode or Indexed addressing mode. The set 2 register area of page 0 is commonly used for stack operations.

S3C826A/P826A ADDRESS SPACES 2- 7 PRIME REGISTER SPACE The lower 192 bytes (00H–BFH) of the S3C826A's eight 256 -byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is immediately addressable following a reset. In order to address prime registers on pages 0, 1, 2, 3, 4, 5, 6, or 7, you must set the register page pointer (PP) to the appropriate source and destination values. FFH Page 7 FFH Page 6 FFH Page 5 FFH C0H 00H BFH Page 4 Page 0 Prime Space FFH FCH E0H D0H C0H Set 1 Bank 0 Peripheral and I/O General-purpose CPU and system control LCD data register Bank 1 FFH Page 3 Set 2 FFH Page 2 Set 2 FFH Page 1 Set 2 FFH C0H 00H BFH Page 0 Set 2 Page 0 Prime Space LCD Data Register Area Page 7 00H AFH Figure 2-4. Set 1, Set 2, Prime Area Register, and LCD Data Register Map

ADDRESS SPACES S3C8 26A/P826A 2- 8 WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers. Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except the set 2 area. The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: — One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15) — One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15) All the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1. After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH). Each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block. 1 1 1 1 1 X X X RP1 (Registers R8-R15) RP0 (Registers R0-R7) Slice 32 Slice 31 ~ ~ CFH C0H FFH F8H F7H F0H FH Slice 2 Slice 1 10H Set 1 Only 0 0 0 0 0 X X X Figure 2-5. 8-Byte Working Register Areas (Slices)

S3C826A/P826A ADDRESS SPACES 2- 9 USING THE REGISTER POINTS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8 -byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH. To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction. (see Figures 2-6 and 2-7). With working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing modes. The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see Figure 2-6). In some cases, it may be necessary to define working register areas in different (non- contiguous) areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice. Because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area to support program requirements. FF PROGRAMMING TIP — Setting the Register Pointers SRP #70H ; RP0 ← 70H, RP1 ← 78H SRP1 #48H ; RP0 ← no change, RP1 ← 48H, SRP0 #0A0H ; RP0 ← A0H, RP1 ← no change CLR RP0 ; RP0 ← 00H, RP1 ← no change LD RP1,#0F8H ; RP0 ← no change, RP1 ← 0F8H FH (R15) 0H (R0) 16-Byte Contiguous Working Register block Register File Contains 32 8-Byte Slices RP0 RP1 8H 0 0 0 0 1 X X X 0 0 0 0 0 X X X 8-Byte Slice 8-Byte Slice Figure 2-6. Contiguous 16-Byte Working Register Block

ADDRESS SPACES S3C8 26A/P826A 2- 10 16-Byte Contiguous working Register block Register File Contains 32 8-Byte Slices 0 0 0 0 0 X X X RP1 1 1 1 1 0 X X X RP0 0H (R0) 7H (R15) F0H (R0) F7H (R7) 8-Byte Slice 8-Byte Slice Figure 2-7. Non-Contiguous 16-Byte Working Register Block FF PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H–85H using the register pointer. The register addresses from 80H through 85H contain the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively: SRP0 #80H ; RP0 ← 80H ADD R0,R1 ; R0 ← R0 + R1 ADC R0,R2 ; R0 ← R0 + R2 + C ADC R0,R3 ; R0 ← R0 + R3 + C ADC R0,R4 ; R0 ← R0 + R4 + C ADC R0,R5 ; R0 ← R0 + R5 + C The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used: ADD 80H,81H ; 80H ← (80H) + (81H) ADC 80H,82H ; 80H ← (80H) + (82H) + C ADC 80H,83H ; 80H ← (80H) + (83H) + C ADC 80H,84H ; 80H ← (80H) + (84H) + C ADC 80H,85H ; 80H ← (80H) + (85H) + C Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.

S3C826A/P826A ADDRESS SPACES 2- 11 REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2. With working register addressing, you use a register pointer to specify an 8 -byte working register space in the register file and an 8-bit register within that space. Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and the least significant byte is always stored in the next (+1) odd-numbered register. Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 -byte working register space in the internal register file and a specific 8-bit register within that space. MSB Rn LSB Rn+1 n = Even address Figure 2-8. 16-Bit Register Pair

ADDRESS SPACES S3C8 26A/P826A 2- 12 RP1 RP0 Register Pointers 00H All Addressing Modes Page 0 Indirect Register, Indexed Addressing Modes Page 0 Register Addressing Only Can be Pointed by Register Pointer FFH E0H BFH Control Registers System Registers Special-Purpose Registers D0H C0H Bank 1 Bank 0 NOTE: In the S3C826A microcontroller, pages 0-7 are implemented. Pages 0-7 contain all of the addressable registers in the internal register file. Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area). FFH C0H Set 2 Prime Registers CFH General-Purpose Register All Addressing Modes Can be Pointed by register Pointer LCD Data Registers Figure 2-9. Register File Addressing

S3C826A/P826A ADDRESS SPACES 2- 13 COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 → C0H–C7H RP1 → C8H–CFH This 16-byte address range is called common area . That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages. FFH Page 7 FFH Page 6 FFH Page 5 FFH C0H BFH Page 4 Page 0 Prime Space FFH FCH E0H D0H C0H Set 1 Following a hardware reset, register pointers RP0 and RP1 point to the common working register area, locations C0H-CFH. RP0 = RP1 = 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 LCD Data Registers Page 7 00H AFH FFH Page 3 Set 2 FFH Page 2 Set 2 FFH Page 1 Set 2 FFH C0H 00H BFH Page 0 Set 2 Page 0 Prime Space~ ~ Figure 2-10. Common Working Register Area

ADDRESS SPACES S3C8 26A/P826A 2- 14 FF PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Examples 1. LD 0C2H,40H ; Invalid addressing mode! Use working regi ster addressing instead: SRP #0C0H LD R2,40H ; R2 (C2H) ← the value in location 40H 2. ADD 0C3H,#45H ; Invalid addressing mode! Use working register addressing instead: SRP #0C0H ADD R3,#45H ; R3 (C3H) ← R3 + 45H 4-BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: — The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1). — The five high-order bits in the register pointer select an 8-byte slice of the register space. — The three low-order bits of the 4-bit address select one of the eight registers in the slice. As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. As long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction "INC R6" is "0 ", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

S3C826A/P826A ADDRESS SPACES 2- 17 8-bit address form instruction 'LD R11, R2' RP0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 Selects RP1 R11 Register address (0ABH) RP1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Specifies working register addressing Figure 2-14. 8-Bit Working Register Addressing Example

ADDRESS SPACES S3C8 26A/P826A 2- 18 SYSTEM AND USER STACK The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3C826A architecture supports stack operations in the internal register file. Stack Operations Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction . When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address value is always decreased by one before a push operation and increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-15. Stack contents after a call instruction Stack contents after an interrupt Top of stack Flags PCH PCL PCL PCHTop of stack Low Address High Address Figure 2-15. Stack Operations User-Defined Stacks You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI, PUSHUD, POPUI, and POPUD support user-defined stack operations. Stack Pointers (SPL, SPH) Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations. The most significant byte of the SP address, SP15–SP8, is stored in the SPH register (D8H), and the least significant byte, SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C826A, the SPL must be initialized to an 8-bit value in the range 00H–FFH. The SPH register is not needed and can be used as a general-purpose register, if necessary. When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the register file), you can use the SPH register as a general-purpose data register. However, if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register, overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can initialize the SPL value to "FFH" instead of "00H".

S3C826A/P826A ADDRESS SPACES 2- 19 FF PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SPL,#0FFH ; SPL ← FFH ; (Normally, the SPL is set to 0FFH by the initialization ; routine) PUSH PP ; Stack address 0FEH ← PP PUSH RP0 ; Stack address 0FDH ← RP0 PUSH RP1 ; Stack address 0FCH ← RP1 PUSH R3 ; Stack address 0FBH ← R3 POP R3 ; R3 ← Stack address 0FBH POP RP1 ; RP1 ← Stack address 0FCH POP RP0 ; RP0 ← Stack address 0FDH POP PP ; PP ← Stack address 0FEH

ADDRESS SPACES S3C8 26A/P826A 2- 20 NOTES

S3C826A/P826A ADDR ESSING MODES 3- 1

3 ADDRESSING MODES

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RC instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction. The seven addressing modes and their symbols are: — Register (R) — Indirect Register (IR) — Indexed (X) — Direct Address (DA) — Indirect Address (IA) — Relative Address (RA) — Immediate (IM)

S3C826A/P826A ADDR ESSING MODES 3- 3 INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3- 6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Please note, however, that you cannot access locations C0H–FFH in set 1 using the Indirect Register addressing mode. dst Address of Operand used by Instruction OPCODE ADDRESS 8-bit Register File Address Point to One Register in Register FileOne-Operand Instruction (Example) Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-bit register address Program Memory Register File Value used in Instruction Execution OPERAND Figure 3-3. Indirect Register Addressing to Register File

ADDRESSING MODES S3 C826A/P826A 3- 4 INDIRECT REGISTER ADDRESSING MODE (C ontinued ) dst OPCODE PAIR Points to Register Pair Example Instruction References Program Memory Sample Instructions: CALL @RR2 JP @RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program Memory 16-Bit Address Points to Program Memory Figure 3-4. Indirect Register Addressing to Program Memory

S3C826A/P826A ADDR ESSING MODES 3- 5 INDIRECT REGISTER ADDRESSING MODE (C ontinued ) dst OPCODE ADDRESS 4-bit Working Register Address Point to the Working Register (1 of 8) Sample Instruction: OR R3, @R6 Program Memory Register File src 3 LSBs Value used in Instruction OPERAND Selected RP points to start fo working register block RP0 or RP1 MSB Points to RP0 or RP1 ~ ~ ~ ~ Figure 3-5. Indirect Working Register Addressing to Register File

ADDRESSING MODES S3 C826A/P826A 3- 6 INDIRECT REGISTER ADDRESSING MODE (C oncluded ) dst OPCODE 4-bit Working Register Address Sample Instructions: LDC R5,@RR6 ; Program memory access LDE R3,@RR14 ; External data memory access LDE @RR4, R8 ; External data memory access Program Memory Register File src Value used in Instruction OPERAND Example Instruction References either Program Memory or Data Memory Program Memory or Data Memory Next 2-bit Point to Working Register Pair (1 of 4) LSB Selects Register Pair 16-Bit address points to program memory or data memory RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

S3C826A/P826A ADDR ESSING MODES 3- 7 INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. Please note, however, that you cannot access locations C0H–FFH in set 1 using Indexed addressing mode. In short offset Indexed addressing mode, the 8 -bit displacement is treated as a signed integer in the range –128 to +127. This applies to external memory accesses only (see Figure 3-8.) For register file addressing, an 8 -bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory, when implemented. dst/src OPCODE Two-Operand Instruction Example Point to One of the Woking Register (1 of 8) Sample Instruction: LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value Program Memory Register File x 3 LSBs Value used in Instruction OPERAND INDEX Base Address RP0 or RP1 Selected RP points to start of working register block ~ ~ ~ ~ Figure 3-7. Indexed Addressing to Register File

ADDRESSING MODES S3 C826A/P826A 3- 8 INDEXED ADDRESSING MODE (C ontinued ) Register File OPERAND Program Memory or Data Memory Point to Working Register Pair (1 of 4) LSB Selects 16-Bit address added to offset RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block dst/src OPCODE Program Memory x OFFSET 4-bit Working Register Address Sample Instructions: LDC R4, #04H[RR2] ; The values in the program address (RR2 + 04H) are loaded into register R4. LDE R4,#04H[RR2] ; Identical operation to LDC example, except that external program memory is accessed. NEXT 2 Bits Register Pair Value used in Instruction 8-Bits 16-Bits 16-Bits ~ ~ Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

S3C826A/P826A ADDR ESSING MODES 3- 9 INDEXED ADDRESSING MODE (C oncluded ) Register File OPERAND Program Memory or Data Memory Point to Working Register Pair LSB Selects 16-Bit address added to offset RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block Sample Instructions: LDC R4, #1000H[RR2] ; The values in the program address (RR2 + 1000H) are loaded into register R4. LDE R4,#1000H[RR2] ; Identical operation to LDC example, except that external program memory is accessed. NEXT 2 Bits Register Pair Value used in Instruction 8-Bits 16-Bits 16-Bits dst/src OPCODE Program Memory src OFFSET 4-bit Working Register Address OFFSET ~ ~ Figure 3-9. Indexed Addressing to Program or Data Memory

ADDRESSING MODES S3 C826A/P826A 3- 10 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented. Sample Instructions: LDC R5,1234H ; The values in the program address (1234H) are loaded into register R5. LDE R5,1234H ; Identical operation to LDC example, except that external program memory is accessed. dst/src OPCODE Program Memory "0" or "1" Lower Address Byte LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory Memory Address Used Upper Address Byte Program or Data Memory Figure 3-10. Direct Addressing for Load Instructions

S3C826A/P826A ADDR ESSING MODES 3- 11 DIRECT ADDRESS MODE (C ontinued ) OPCODE Program Memory Lower Address Byte Memory Address Used Upper Address Byte Sample Instructions: JP C,JOB1 ; Where JOB1 is a 16-bit immediate address CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address Next OPCODE Figure 3-11. Direct Addressing for Call and Jump Instructions

ADDRESSING MODES S3 C826A/P826A 3- 12 INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed. Only the CALL instruction can use the Indirect Address mode. Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros. Current Instruction Program Memory Locations 0-255 Program Memory OPCODE dst Lower Address Byte Upper Address Byte Next Instruction LSB Must be Zero Sample Instruction: CALL #40H ; The 16-bit value in program memory addresses 40H and 41H is the subroutine start address. Figure 3-12. Indirect Addressing

S3C826A/P826A ADDR ESSING MODES 3- 13 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR. OPCODE Program Memory Displacement Program Memory Address Used Sample Instructions: JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128 Next OPCODE Signed Displacement Value Current Instruction Current PC Value Figure 3-13. Relative Addressing

ADDRESSING MODES S3 C826A/P826A 3- 14 IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers. (The Operand value is in the instruction) OPCODE Sample Instruction: LD R0,#0AAH Program Memory OPERAND Figure 3-14. Immediate Addressing

S3C826A/P826A CONTR OL REGISTER 4- 1

4 CONTROL REGISTERS

In this chapter , deta iled descriptions of the S3C826A control registers are presented in an easy-to-read format. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual. Data and counter registers are not described in detail in this reference chapter . More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual. The locations and read/write characteristics of all mapped registers in the S3C826A register file are listed in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, RESET and Power- Down ." Table 4-1. Set 1 Registers Register Name Mnemonic Address R/W RESETRESET Values (bit) Decimal Hex 7 6 5 4 3 2 1 0 Interrupt pending register INTPND 208 D0H R/W – – – – 0 0 0 0 STOP control register STPCON 209 D1H R/W 0 0 0 0 0 0 0 0 Oscillator control register OSCCON 210 D2H R/W – – – – 0 0 – 0 Basic timer control register BTCON 211 D3H R/W 0 0 0 0 0 0 0 0 System clock control register CLKCON 212 D4H R/W 0 – – 0 0 – – – System flags register FLAGS 213 D5H R/W x x x x x x 0 0 Register pointer 0 RP0 214 D6H R/W 1 1 0 0 0 – – – Register pointer 1 RP1 215 D7H R/W 1 1 0 0 1 – – – Stack pointer (high byte) SPH 216 D8H R/W x x x x x x x x Stack pointer (low byte) SPL 217 D9H R/W x x x x x x x x Instruction pointer (high byte) IPH 218 DAH R/W x x x x x x x x Instruction pointer (low byte) IPL 219 DBH R/W x x x x x x x x Interrupt request register IRQ 220 DCH R 0 0 0 0 0 0 0 0 Interrupt mask register IMR 221 DDH R/W x x x x x x x x System mode register SYM 222 DEH R/W 0 – – x x x 0 0 Register page pointer PP 223 DFH R/W 0 0 0 0 0 0 0 0

CONTROL REGISTERS S 3C826A/P826A 4- 2 T able 4- 2 . Set 1, Bank 0 Registers Register Name Mnemonic Address R/W RESETRESET Value(bit) Decimal Hex 7 6 5 4 3 2 1 0 SIO Control Register SIOCON 224 E0H R/W 0 0 0 0 0 0 0 0 SIO Data Register SIODATA 225 E1H R/W 0 0 0 0 0 0 0 0 SIO Prescaler Register SIOPS 226 E2H R/W 0 0 0 0 0 0 0 0 Timer 0 Counter Register T0CNT 227 E3H R 0 0 0 0 0 0 0 0 Timer 0 Data Register T0DATA 228 E4H R/W 1 1 1 1 1 1 1 1 Timer 0 Control Register T0CON 229 E5H R/W 0 0 0 0 0 0 0 0 Timer B Counter Register TBCNT 230 E6H R 0 0 0 0 0 0 0 0 Timer A Counter Register TACNT 231 E7H R 0 0 0 0 0 0 0 0 Timer B Data Register TBDATA 232 E8H R/W 1 1 1 1 1 1 1 1 Timer A Data Register TADATA 233 E9H R/W 1 1 1 1 1 1 1 1 Timer B Control Register TBCON 234 EAH R/W – – 0 0 0 0 0 0 Timer 1/A Control Register TACON 235 EBH R/W 0 0 0 0 0 0 0 0 Timer 2 Counter Register T2CNT 236 ECH R 0 0 0 0 0 0 0 0 Timer 2 Data Register T2DATA 237 EDH R/W 1 1 1 1 1 1 1 1 Timer 2 Control Register T2CON 238 EEH R/W 0 0 0 0 0 0 0 0 A/D Converter Control Register ADCON 239 EFH R/W – – 0 0 0 0 0 0 A/D Converter Data Register ADDATA 240 F0H R/W x x x x x x x x Timer 3 Control Register T3CON 241 F1H R/W 0 0 0 0 0 0 0 0 Timer 3 Counter T3CNT 242 F2H R 0 0 0 0 0 0 0 0 Timer 3 Data Register T3DATA 243 F3H R/W 1 1 1 1 1 1 1 1 LCD Control Register LCON 244 F4H R/W 0 0 0 0 0 0 0 0 LCD Mode Register LMOD 245 F5H R/W 0 0 – 0 0 0 0 0 Watch Timer Control Register WTCON 246 F6H R/W 0 0 0 0 0 0 0 0 Port Group 0 Control Register PG0CON 247 F7H R/W 0 0 0 0 0 0 0 0 Port Group 1 Control Register PG1CON 248 F8H R/W 0 0 0 0 0 0 0 0 Port Group 2 Control Register PG2CON 249 F9H R/W 0 0 0 0 0 0 0 0 Port Group 3 Control Register PG3CON 250 FAH R/W 0 0 0 0 0 0 0 0 Port Group 4 Control Register PG4CON 251 FBH R/W 0 0 0 0 0 0 0 0 Location FCH is not mapped. Basic Timer Counter BTCNT 253 FDH R 0 0 0 0 0 0 0 0 Location FEH is not mapped. Interrupt Priority Register IPR 255 FFH R/W x x x x x x x x

S3C826A/P826A CONTR OL REGISTER 4- 3 Table 4- 3 . Set 1, Bank 1 Registers Register Name Mnemonic Address R/W RESETRESET Value(bit) Decimal Hex 7 6 5 4 3 2 1 0 Port 0 Control Register(High Byte) P0CONH 224 E0H R/W 0 0 0 0 0 0 0 0 Port 0 Control Register(Low Byte) P0CONL 225 E1H R/W 0 0 0 0 0 0 0 0 Port 0 Interrupt Edge Selection Register P0EDGE 226 E2H R/W 0 0 0 0 0 0 0 0 Port 0 Interrupt Control Register P0INT 227 E3H R/W 0 0 0 0 0 0 0 0 Port 0 Interrupt Pending Register P0PND 228 E4H R/W 0 0 0 0 0 0 0 0 Port 1 Pull-up Resistors E nable Register P1PUR 229 E5H R/W 0 0 0 0 0 0 0 0 Port 1 Control Register(High Byte) P1CONH 230 E6H R/W 0 0 0 0 0 0 0 0 Port 1 Control Register(Low Byte) P1CONL 231 E7H R/W 0 0 0 0 0 0 0 0 Port 2 Control Register(High Byte) P2CONH 232 E8H R/W 0 0 0 0 0 0 0 0 Port 2 Control Register(Low Byte) P2CONL 233 E9H R/W 0 0 0 0 0 0 0 0 Port 2 Pull-up Resistors E nable Register P2PUR 234 EAH R/W 0 0 0 0 0 0 0 0 Port 3 Pull-up Resistors E nable Register P3PUR 235 EBH R/W 0 0 0 0 0 0 0 0 Port 3 Control Register(High Byte) P3CONH 236 ECH R/W 0 0 0 0 0 0 0 0 Port 3 Control Register(Low Byte) P3CONL 237 EDH R/W 0 0 0 0 0 0 0 0 Port 3 Interrupt Control Register P3INT 238 EEH R/W 0 0 0 0 0 0 0 0 Location EFH is not mapped. Port 0 Data Register P0 240 F0H R/W 0 0 0 0 0 0 0 0 Port 1 Data Register P1 241 F1H R/W 0 0 0 0 0 0 0 0 Port 2 Data Register P2 242 F2H R/W 0 0 0 0 0 0 0 0 Port 3 Data Register P3 243 F3H R/W 0 0 0 0 0 0 0 0 Port 4 Data Register P4 244 F4H R/W 0 0 0 0 0 0 0 0 Port 5 Data Register P5 245 F5H R/W 0 0 0 0 0 0 0 0 Port 6 Data Register P6 246 F6H R/W 0 0 0 0 0 0 0 0 Port 7 Data Register P7 247 F7H R/W 0 0 0 0 0 0 0 0 Port 8 Data Register P8 248 F8H R/W 0 0 0 0 0 0 0 0 Port 9 Data Register P9 249 F9H R/W 0 0 0 0 0 0 0 0 Port 10 Data Register P10 250 FAH R/W 0 0 0 0 0 0 0 0 Port 11 Data Register P11 251 FBH R/W 0 0 0 0 0 0 0 0 Port 12 Data Register P12 252 FCH R/W 0 0 0 0 0 0 0 0 Port 13 Data Register P13 253 FDH R/W 0 0 0 0 0 0 0 0 Port 14 Data Register P14 254 FEH R/W 0 0 0 0 0 0 0 0 Port 15 Data Register P15 255 FFH R/W 0 0 0 0 0 0 0 0

CONTROL REGISTERS S 3C826A/P826A 4- 4 FLAGS −− System Flags Register .7 Carry Flag (C) .6 Zero Flag (Z) Bit Identifier RESETRESET Value Read/Write Bit Addressing Mode R = Read-only W = Write-only R/W = Read/write '-' = Not used Type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) RESET value notation: '-' = Not used 'x' = Undetermined value '0' = Logic zero '1' = Logic one Bit number(s) that is/are appended to the register name for bit addressing Name of individual bit or related bits Register nameRegister ID Sign Flag (S)

0 Operation does not generate a carry or borrow condition

0 Operation generates carry-out or borrow into high-order bit 7

0 Operation result is a non-zero value

0 Operation result is zero

0 Operation generates positive number (MSB = "0")

0 Operation generates negative number (MSB = "1")

(hexadecimal) .7 .6 .5 x x x R/W R/W R/W Register addressing mode only x R/W x R/W x R/W x R/W R/W Bit number: MSB = Bit 7 LSB = Bit 0 Figure 4-1. Register Description Format

S3C826A/P826A CONTR OL REGISTER 4- 5 AD CON — A/D Converter Control Register EF H Set 1 , Bank 0 RESETRESET Value – – 0 0 0 0 0 0 Read/Write – – R/W R/W R R/W R/W R/W Addressing Mode Register addressing mode only .7 –.6 Not used for the S3C826A .5– .4 A/D Input Pin Selection Bits 0 0 AD0 (P1.0) 0 1 AD1 (P1.1) 1 0 AD2 (P1.2) 1 1 AD3 (P1.3) .3 End-of-Conversion Bit (read-only)

0 Conversion not complete

1 Conversion complete

.2– .1 Clock Source Selection Bits 0 0 fxx/16 0 1 fxx/8 1 0 fxx/4 1 1 fxx .0 Start or Enable Bit

0 Disable operation

1 Start operation (automatically disable operation after conversion complete).

CONTROL REGISTERS S 3C826A/P826A 4- 6 BTCON — Basic Timer Control Register D3H Set 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.4 Watchdog Timer Function Disable Code (for System Reset) 1 0 1 0 Disable watchdog timer function Others Enable watchdog timer function .3– .2 Basic Timer Input Clock Selection Bits 0 0 fxx /4096 ( 3 ) 0 1 fxx /1024 1 0 fxx /128 1 1 fxx /16 .1 Basic Timer Counter Clear Bit (1)

0 No effect

1 Clear the basic timer counter value

.0 Clock Frequency Divider Clear Bit for all Timers (2)

1 Clear both clock frequency dividers

NOTES : 1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to “ 00H ” . Immediately following the write operation, the BTCON.1 value is automatically cleared to “ 0 ” . 2. When you write a “ 1 ” to BTCON.0, the corresponding frequency divider is cleared to “ 00H ” . Immediately following the write operation, the BTCON.0 value is automatically cleared to “ 0 ” . 3. The fxx is selected clock for system.

S3C826A/P826A CONTR OL REGISTER 4- 7 CLKCON — System Clock Control Register D4H Set 1 RESETRESET Value 0 – – 0 0 – – – Read/Write R/W – – R/W R/W – – – Addressing Mode Register addressing mode only .7 Oscillator IRQ Wake-up Function Bit

0 Enable IRQ for main wake-up in power down mode

1 Disable IRQ for main wake-up in power down mode

.6 – .5 Not used for the S3C826A. .4– .3 CPU Clock (System Clock) Selection Bits (note) 0 0 fxx/16 0 1 fxx/8 1 0 fxx/2 1 1 fxx .2–.0 Not used for the S3C826A. NOTE : After a reset, the slowest clock (divided by 16) is selected as the system clock. To s elect faster clock speeds, load the appropriate v alues to CLKCON.3 and CLKCON.4.

CONTROL REGISTERS S 3C826A/P826A 4- 8 FLAGS — System Flags Register D5H Set 1 RESETRESET Value x x x x x x 0 0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Addressing Mode Register addressing mode only .7 Carry Flag (C)

1 Operation generates a carry-out or borrow into high-order bit 7

.6 Zero Flag (Z)

1 Operation result is zero

.5 Sign Flag (S)

0 Operation generates a positive number (MSB = "0")

1 Operation generates a negative number (MSB = "1")

.4 Overflow Flag (V)

0 Operation result is ≤ +127 or ≥ –128

1 Operation result is > +127 or < –128

.3 Decimal Adjust Flag (D)

0 Add operation completed

1 Subtraction operation completed

.2 Half-Carry Flag (H)

0 No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction

1 Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3

.1 Fast Interrupt Status Flag (FIS)

0 Interrupt return (IRET) in progress (when read)

1 Fast interrupt service routine in progress (when read)

.0 Bank Address Selection Flag (BA)

0 Bank 0 is selected

1 Bank 1 is selected

S3C826A/P826A CONTR OL REGISTER 4- 9 IMR — Interrupt Mask Register DDH Set 1 RESETRESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Interrupt Level 7 (IRQ 7 ) Enable Bit; P0.0-P0.3

0 Disable (mask)

1 Enable (unmask)

.6 Interrupt Level 6 (IRQ6) Enable Bit; P0.4-P0.7 .5 Interrupt Level 5 (IRQ5) Enable Bit; P3.4-P3.7 .4 Interrupt Level 4 (IRQ4) Enable Bit; Watch Timer .3 Interrupt Level 3 (IRQ 3 ) Enable Bit; SIO .2 Interrupt Level 2 (IRQ 2) Enable Bit;Timer 2, Timer 3 match/capture or overflow .1 Interrupt Level 1 (IRQ1) Enable Bit; Timer B, Timer 1/A .0 Interrupt Level 0 (IRQ0 ) Enable Bit; Timer 0 Match/Capture or Overflow NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.

CONTROL REGISTERS S 3C826A/P826A 4- 10 INTPND — Interrupt Pending Register D0 H Set 1 RESETRESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.4 Not used for the S3C826A. .3 Timer 3 Match/Capture Interrupt Pending Bit

0 Interrupt request is not pending (when read), pending bit clear (when write 0)

1 Interrupt request is pending

.2 Timer 3 Overflow Interrupt Pending bit .1 Timer 0 Match/Capture Interrupt Pending Bit .0 Timer 0 Overflow Interrupt Pending bit NOTE: Refer to P age 5-15 for clearing any pending bits.

S3C826A/P826A CONTR OL REGISTER 4- 11 IPH — Instruction Pointer (High Byte ) DAH Set 1 RESETRESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL register (DBH). IPL — Instruction Pointer (Low Byte ) DBH Set 1 RESETRESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (Low Byte) The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (IP7 – IP0). The upper byte of the IP address is located in the IPH register (DAH).

CONTROL REGISTERS S 3C826A/P826A 4- 12 IPR — Interrupt Priority Register FFH Set 1 , Bank 0 RESETRESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C (note) 0 0 0 Group priority undefined 0 0 1 B > C > A 0 1 0 A > B > C 0 1 1 B > A > C 1 0 0 C > A > B 1 0 1 C > B > A 1 1 0 A > C > B 1 1 1 Group priority undefined .6 Interrupt Subgroup C Priority Control Bit

0 IRQ6 > IRQ7

1 IRQ7 > IRQ6

.5 Interrupt Group C Priority Control Bit

0 IRQ5 > ( IRQ6 , IRQ7)

1 ( IRQ6 , IRQ7) > IRQ5 .3 Interrupt Subgroup B Priority Control Bit

0 IRQ3 > IRQ4

1 IRQ4 > IRQ3

.2 Interrupt Group B Priority Control Bit

0 IRQ2 > (IRQ3, IRQ4)

1 (IRQ3, IRQ4) > IRQ2 .0 Interrupt Group A Priority Control Bit

0 IRQ0 > IRQ1

1 IRQ1 > IRQ0

NOTE: Interrupt Group A - IRQ0, IRQ1 Interrupt Group B - IRQ2, IRQ3, IRQ4 Interrupt Group C - IRQ5, IRQ6, IRQ7

S3C826A/P826A CONTR OL REGISTER 4- 13 IRQ — Interrupt Request Register DCH Set 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Addressing Mode Register addressing mode only .7 Level 7 (IRQ 7 ) Request Pending Bit; External Interrupt P0.0-P0.3

0 Not pending

1 Pending

.6 Level 6 (IRQ6) Request Pending Bit; External Interrupt P0.4-P0.7 .5 Level 5 (IRQ5) Request Pending Bit; External Interrupt P3.4-P3.7 .4 Level 4 (IRQ4) Request Pending Bit; Watch Timer .3 Level 3 (IRQ 3 ) Request Pending Bit; SIO .2 Level 2 (IRQ 2 ) Request Pending Bit; Timer 2, Timer 3 Match/Capture or Overflow .1 Level 1 (IRQ1) Request Pending Bit; Timer B, Timer 1/A .0 Level 0 (IRQ0 ) Request Pending Bit; Timer 0 Match/Capture or Overflow

CONTROL REGISTERS S 3C826A/P826A 4- 14 LCON — LCD Control Register F4 H Set 1 , Bank 0 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only LCON.7–.4 LCD Contrast Level Control Bits (16 steps) 0 0 0 0 1/16 step (The dimmest level) 0 0 0 1 2/16 step 0 0 1 0 3/16 step 1 1 1 1 16/16 step (The brightest level) NOTE: V LCD = V DD x (n+17)/32, where n = 0 – 15 LCON.3 Enable/Disable LCD Contrast Control Bit

0 Disable LCD contrast control

1 Enable LCD contrast control

LCON.2–.1 LCD Duty Selection Bits 0 0 1/8 duty (COM0–COM7, SEG0–SEG87) 0 1 1/12 duty (COM0–COM11, SEG0–SEG83) 1 0 1/16 duty (COM0–COM15, SEG0–SEG79) LCON.0 LCD Bias Resistor On/Off Bit

0 LCD bias resistors off

1 LCD bias resistors on

S3C826A/P826A CONTR OL REGISTER 4- 15 LMOD — LCD Mode Control Register F5H Set 1, Bank 0 RESETRESET Value 0 0 – 0 0 0 0 0 Read/Write R/W R/W – R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only LMOD.7–.6 LCD Clock (LCDCK) Frequency Selection Bits 0 0 When 1/8 duty: fw/2 7 (256 Hz); when 1/12,1/16 duty: fw/2 6 (512 Hz) 0 1 When 1/8 duty: fw/2 6 (512 Hz); when 1/12,1/16 duty: fw/2 5 (1024 Hz) 1 0 When 1/8 duty: fw/2 5 (1024 Hz); when 1/12,1/16 duty: fw/2 4 (2048 Hz) 1 1 When 1/8 duty: fw/2 4 (2048 Hz); when 1/12,1/16 duty: fw/2 3 (4096 Hz) NOTE: LCDCK is supplied only when the watch timer operates. To use the LCD controller, bit 2 in the watch timer mode register WMOD should be set to 1. LMOD.4-.0 LCD Port Selection Bits LMOD.4-.0 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH 10H 11H 12H 13H 14H SEG79-76 P4.0-P4.3 L P P P P P P P P P P P P P P P P P P P P SEG75-72 P4.4-P4.7 L L P P P P P P P P P P P P P P P P P P P SEG71-68 P5.0-P5.3 L L L P P P P P P P P P P P P P P P P P P SEG67-64 P5.4-P5.7 L L L L P P P P P P P P P P P P P P P P P SEG63-60 P6.0-P6.3 L L L L L P P P P P P P P P P P P P P P P SEG59-56 P6.4-P6.7 L L L L L L P P P P P P P P P P P P P P P SEG55-52 P7.0-P7.3 L L L L L L L P P P P P P P P P P P P P P SEG51-48 P7.4-P7.7 L L L L L L L L P P P P P P P P P P P P P SEG47-44 P8.0-P8.3 L L L L L L L L L P P P P P P P P P P P P SEG43-40 P8.4-P8.7 L L L L L L L L L L P P P P P P P P P P P SEG39-36 P9.0-P9.3 L L L L L L L L L L L P P P P P P P P P P SEG35-32 P9.4-P9.7 L L L L L L L L L L L L P P P P P P P P P SEG31-28 P10.0-P10.3 L L L L L L L L L L L L L P P P P P P P P SEG27-24 P10.4-P10.7 L L L L L L L L L L L L L L P P P P P P P SEG23-20 P11.0-P11.3 L L L L L L L L L L L L L L L P P P P P P SEG19-16 P11.4-P11.7 L L L L L L L L L L L L L L L L P P P P P SEG15-8 P12.0-P12.7 L L L L L L L L L L L L L L L L L P P P P SEG7-0 P13.0-P13.7 L L L L L L L L L L L L L L L L L L P P P COM15-8/ SEG80-87 P14.0-P14.7 L L L L L L L L L L L L L L L L L L L P P COM7-0 P15.0-P15.7 L L L L L L L L L L L L L L L L L L L L P NOTE: "P" means port, "L" means LCD output.

CONTROL REGISTERS S 3C826A/P826A 4- 16 OSCCON — Oscillator Control Register D2H Set 1 RESETRESET Value – – – – 0 0 – 0 Read/Write – – – – R/W R/W – R/W Addressing Mode Register addressing mode only .7–.4 Not used for S3C826A. .3 Main Oscillator Control Bit

0 Main oscillator RUN

1 Main oscillator STOP

.2 Sub Oscillator Control Bit

0 Sub oscillator RUN

1 Sub oscillator STOP

.1 Not used for S3C826A. .0 System Clock Selection Bit

0 Select main oscillator for system clock

1 Select sub oscillator for system clock

S3C826A/P826A CONTR OL REGISTER 4- 17 P0CONH — Port 0 Control Register (High Byte) E0H Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P0.7/INT7 Mode Selection Bits 0 0 Input mode 0 1 Input, pull-up mode 1 0 Open-drain output mode 1 1 Push-pull output mode .5–.4 P0.6/INT6 Mode Selection Bits 0 0 Input mode 0 1 Input, pull-up mode 1 0 Open-drain output mode 1 1 Push-pull output mode .3–.2 P0.5/INT5 Mode Selection Bits 0 0 Input mode 0 1 Input, pull-up mode 1 0 Open-drain output mode 1 1 Push-pull output mode .1–.0 P0.4/INT4 Mode Selection Bits 0 0 Input mode 0 1 Input, pull-up mode 1 0 Open-drain output mode 1 1 Push-pull output mode NOTE: Pins configured as input can be used as interrupt input with noise filter.

CONTROL REGISTERS S 3C826A/P826A 4- 18 P0CONL — Port 0 Control Register (Low Byte) E1H Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P0.3/INT3 Mode Selection Bits 0 0 Input mode 0 1 Input, pull-up mode 1 0 Open-drain output mode 1 1 Push-pull output mode .5–.4 P0.2/INT2 Mode Selection Bits 0 0 Input mode 0 1 Input, pull-up mode 1 0 Open-drain output mode 1 1 Push-pull output mode .3–.2 P0.1/INT1 Mode Selection Bits 0 0 Input mode 0 1 Input, pull-up mode 1 0 Open-drain output mode 1 1 Push-pull output mode .1–.0 P0.0/INT0 Mode Selection Bits 0 0 Input mode 0 1 Input, pull-up mode 1 0 Open-drain output mode 1 1 Push-pull output mode NOTE: Pins configured as input can be used as interrupt input with noise filter.

S3C826A/P826A CONTR OL REGISTER 4- 19 P0INT — Port 0 Interrupt Control Register E3H Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7 External Interrupt (INT7) Enable Bit

0 Disable interrupt

1 Enable interrupt

.6 P0.6 External Interrupt (INT6) Enable Bit .5 P0.5 External Interrupt (INT5) Enable Bit .4 P0.4 External Interrupt (INT4) Enable Bit .3 P0.3 External Interrupt (INT3) Enable Bit .2 P0.2 External Interrupt (INT2) Enable Bit .1 P0.1 External Interrupt (INT1) Enable Bit .0 P0.0 External Interrupt (INT0) Enable Bit

CONTROL REGISTERS S 3C826A/P826A 4- 20 P0PND — Port 0 Interrupt Pending Register E4H Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7 External Interrupt (INT7) Pending Bit

0 Clear pending bit (when write)

1 P0.7 interrupt request is pending (when read) .6 P0.6 External Interrupt (INT6) Pending Bit 1 P0.6 interrupt request is pending (when read) .5 P0.5 External Interrupt (INT5) Pending Bit 1 P0.5 interrupt request is pending (when read) .4 P0.4 External Interrupt (INT4) Pending Bit 1 P0.4 interrupt request is pending (when read) .3 P0.3 External Interrupt (INT3) Pending Bit 1 P0.3 interrupt request is pending (when read) .2 P0.2 External Interrupt (INT2) Pending Bit 1 P0.2 interrupt request is pending (when read) .1 P0.1 External Interrupt (INT1) Pending Bit 1 P0.1 interrupt request is pending (when read) .0 P0.0 External Interrupt (INT0) Pending Bit 1 P0.0 interrupt request is pending (when read) NOTE: Refer to Page 5-15 for clearing any pending bits.

S3C826A/P826A CONTR OL REGISTER 4- 21 P0EDGE — Port 0 Interrupt Edge Selection Register E2H Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7 External Interrupt (INT7) State Bit

0 Falling edge detection

1 Rising edge detection

.6 P0.6 External Interrupt (INT6) State Bit .5 P0.5 External Interrupt (INT5) State Bit .4 P0.4 External Interrupt (INT4) State Bit .3 P0.3 External Interrupt (INT3) State Bit .2 P0.2 External Interrupt (INT2) State Bit .1 P0.1 External Interrupt (INT1) State Bit .0 P0.0 External Interrupt (INT0) State Bit

CONTROL REGISTERS S 3C826A/P826A 4- 22 P1CONH — Port 1 Control Register (High Byte) E6H Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P1.7/BUZ 0 0 Input mode 0 1 Output mode, open-drain 1 0 Alternative function (BUZ) 1 1 Output mode, push-pull .5–.4 P1.6/SI 0 0 Input mode (SI) 0 1 Output mode, open-drain 1 0 Not available 1 1 Output mode, push-pull .3–.2 P1.5/SO 0 0 Input mode 0 1 Output mode, open-drain 1 0 Alternative function (SO) 1 1 Output mode, push-pull .1–.0 P1.4/SCK 0 0 Input mode (SCK) 0 1 Output mode, open-drain 1 0 Alternative function (SCK) 1 1 Output mode, push-pull

S3C826A/P826A CONTR OL REGISTER 4- 23 P1CONL — Port 1 Control Register (Low Byte) E7H Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P1.3/AD3 0 0 Input mode 0 1 Output mode, open-drain 1 0 Alternative function (ADC mode) 1 1 Output mode, push-pull .5–.4 P1.2/AD2 0 0 Input mode 0 1 Output mode, open-drain 1 0 Alternative function (ADC mode) 1 1 Output mode, push-pull .3–.2 P1.1/AD1 0 0 Input mode 0 1 Output mode, open-drain 1 0 Alternative function (ADC mode) 1 1 Output mode, push-pull .1–.0 P1.0/AD0 0 0 Input mode 0 1 Output mode, open-drain 1 0 Alternative function (ADC mode) 1 1 Output mode, push-pull

CONTROL REGISTERS S 3C826A/P826A 4- 24 P1PUR — Port 1 Pull-up Control Register E5H Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P1.7 Pull-up Resistor Enable Bit

0 Pull-up disable

1 Pull-up enable

.6 P1.6 Pull-up Resistor Enable Bit .5 P1.5 Pull-up Resistor Enable Bit .4 P1.4 Pull-up Resistor Enable Bit .3 P1.3 Pull-up Resistor Enable Bit .2 P1.2 Pull-up Resistor Enable Bit .1 P1.1 Pull-up Resistor Enable Bit .0 P1.0 Pull-up Resistor Enable Bit

S3C826A/P826A CONTR OL REGISTER 4- 25 P2CONH — Port 2 Control Register (High Byte) E8H Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P2.7 0 0 Input mode 0 1 Output mode, open-drain 1 0 Not available 1 1 Output mode, push-pull .5–.4 P2.6 0 0 Input mode 0 1 Output mode, open-drain 1 0 Not available 1 1 Output mode, push-pull .3–.2 P2.5 0 0 Input mode 0 1 Output mode, open-drain 1 0 Not available 1 1 Output mode, push-pull .1–.0 P2.4/TBOUT 0 0 Input mode 0 1 Output mode, open-drain 1 0 Alternative function (TBOUT) 1 1 Output mode, push-pull

CONTROL REGISTERS S 3C826A/P826A 4- 26 P2CONL — Port 2 Control Register (Low Byte) E9H Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P2.3/TAOUT 0 0 Input mode 0 1 Output mode, open-drain 1 0 Alternative function (TAOUT) 1 1 Output mode, push-pull .5–.4 P2.2/T1CLK 0 0 Input mode (T1CLK) 0 1 Output mode, open-drain 1 0 Not available 1 1 Output mode, push-pull .3–.2 P2.1/T0OUT/T0PWM/T0CAP 0 0 Input mode (T0CAP input) 0 1 Output mode, open-drain 1 0 Alternative function (T0OUT/T0PWM) 1 1 Output mode, push-pull .1–.0 P2.0/T0CLK 0 0 Input mode (T0CLK) 0 1 Output mode, open-drain 1 0 Not available 1 1 Output mode, push-pull

S3C826A/P826A CONTR OL REGISTER 4- 27 P2PUR — Port 2 Pull-up Control Register EAH Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P2.7 Pull-up Resistor Enable Bit .6 P2.6 Pull-up Resistor Enable Bit .5 P2.5 Pull-up Resistor Enable Bit .4 P2.4 Pull-up Resistor Enable Bit .3 P2.3 Pull-up Resistor Enable Bit .2 P2.2 Pull-up Resistor Enable Bit .1 P2.1 Pull-up Resistor Enable Bit .0 P2.0 Pull-up Resistor Enable Bit

CONTROL REGISTERS S 3C826A/P826A 4- 28 P3CONH — Port 3 Control Register (High Byte) ECH Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P3.7/INT11 0 0 Input mode 0 1 Output mode, open-drain 1 0 Not available 1 1 Output mode, push-pull .5–.4 P3.6/NT10 0 0 Input mode 0 1 Output mode, open-drain 1 0 Not available 1 1 Output mode, push-pull .3–.2 P3.5/INT9 0 0 Input mode 0 1 Output mode, open-drain 1 0 Not available 1 1 Output mode, push-pull .1–.0 P3.4/INT8 0 0 Input mode 0 1 Output mode, open-drain 1 0 Not available 1 1 Output mode, push-pull

S3C826A/P826A CONTR OL REGISTER 4- 29 P3CONL — Port 3 Control Register (Low Byte) EDH Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P3.3/T3OUT/T3PWM/T3CAP 0 0 Input mode (T3CAP input) 0 1 Output mode, open-drain 1 0 Alternative function (T3OUT/T3PWM) 1 1 Output mode, push-pull .5–.4 P3.2/T3CLK 0 0 Input mode (T3CLK) 0 1 Output mode, open-drain 1 0 Not available 1 1 Output mode, push-pull .3–.2 P3.1/T2OUT 0 0 Input mode 0 1 Output mode, open-drain 1 0 Alternative function (T2OUT) 1 1 Output mode, push-pull .1–.0 P3.0/T2CLK 0 0 Input mode (T2CLK) 0 1 Output mode, open-drain 1 0 Not available 1 1 Output mode, push-pull

CONTROL REGISTERS S 3C826A/P826A 4- 30 P3INT — Port 3 Interrupt Control Register EEH Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Port 3 Interrupt Request Pending Bit (P3.7/INT11)

0 No interrupt request pending

.6 Interrupt Control Settings (P3.7/INT11) 0 Disable interrupt on P3.7 1 Enable interrupt at falling edge on P3.7 .5 Port 3 Interrupt Request Pending Bit (P3.6/INT10) .4 Interrupt Control Settings (P3.6/INT10) 0 Disable interrupt on P3.6 1 Enable interrupt at falling edge on P3.6 .3 Port 3 Interrupt Request Pending Bit (P3.5/INT9) .2 Interrupt Control Settings (P3.5/INT9) 0 Disable interrupt on P3.5 1 Enable interrupt at falling edge on P3.5 .1 Port 3 Interrupt Request Pending Bit (P3.4/INT8) .0 Interrupt Control Settings (P3.4/INT8) 0 Disable interrupt on P3.4 1 Enable interrupt at falling edge on P3.4 NOTE: Refer to Page 5-15 for clearing any interrupt pending bits.

S3C826A/P826A CONTR OL REGISTER 4- 31 P3PUR — Port 3 Pull-up Control Register EBH Set 1, Bank 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P3.7 Pull-up Resistor Enable Bit .6 P3.6 Pull-up Resistor Enable Bit .5 P3.5 Pull-up Resistor Enable Bit .4 P3.4 Pull-up Resistor Enable Bit .3 P3.3 Pull-up Resistor Enable Bit .2 P3.2 Pull-up Resistor Enable Bit .1 P3.1 Pull-up Resistor Enable Bit .0 P3.0 Pull-up Resistor Enable Bit

CONTROL REGISTERS S 3C826A/P826A 4- 32 PG0CON — Port Group 0 Control Register F7H Set 1, Bank 0 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P5.4-5.7/SEG67-64 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .5–.4 P5.0-5.3/SEG71-68 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .3–.2 P4.4-4.7/SEG75-72 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .1–.0 P4.0-4.3/SEG79-76 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode

S3C826A/P826A CONTR OL REGISTER 4- 33 PG1CON — Port Group 1 Control Register F8H Set 1, Bank 0 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P7.4-7.7/SEG51-48 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .5–.4 P7.0-7.3/SEG55-52 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .3–.2 P6.4-6.7/SEG59-56 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .1–.0 P6.0-6.3/SEG63-60 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode

CONTROL REGISTERS S 3C826A/P826A 4- 34 PG2CON — Port Group 2 Control Register F9H Set 1, Bank 0 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P9.4-9.7/SEG35-32 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .5–.4 P9.0-9.3/SEG39-36 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .3–.2 P8.4-8.7/SEG43-40 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .1–.0 P8.0-8.3/SEG47-44 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode

S3C826A/P826A CONTR OL REGISTER 4- 35 PG3CON — Port Group 3 Control Register FAH Set 1, Bank 0 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P11.4-11.7/SEG19-16 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .5–.4 P11.0-11.3/SEG23-20 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .3–.2 P10.4-10.7/SEG27-24 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .1–.0 P10.0-10.3/SEG31-28 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode

CONTROL REGISTERS S 3C826A/P826A 4- 36 PG4CON — Port Group 4 Control Register FBH Set 1, Bank 0 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P15.0-15.7/COM7-0 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .5–.4 P14.0-14.7/COM15-8/SEG80-87 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .3–.2 P13.0-13.7/SEG7-0 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode .1–.0 P12.0-12.7/SEG15-8 Mode Selection Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Open-drain output mode 1 1 Push-pull output mode

S3C826A/P826A CONTR OL REGISTER 4- 37 PP — Register Page Pointer DFH Set 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .4 Destination Register Page Selection Bits 0 0 0 0 Destination: page 0 0 0 0 1 Destination: page 1 0 0 1 0 Destination: page 2 0 0 1 1 Destination: page 3 0 1 0 0 Destination: page 4 0 1 0 1 Destination: page 5 0 1 1 0 Destination: page 6 0 1 1 1 Destination: page 7 .3 – .0 Source Register Page Selection Bits 0 0 0 0 Source: page 0 0 0 0 1 Source: page 1 0 0 1 0 Source: page 2 0 0 1 1 Source: page 3 0 1 0 0 Source: page 4 0 1 0 1 Source: page 5 0 1 1 0 Source: page 6 0 1 1 1 Source: page 7 NOTE: In the S3C826A microcontroller, the internal register file is configured as eight pages (Pages 0-7). The pages 0-6 are used for general purpose register file, and page 7 is used for LCD data register or general purpose registers.

CONTROL REGISTERS S 3C826A/P826A 4- 38 RP0 — Register Pointer 0 D6H Set 1 RESETRESET Value 1 1 0 0 0 – – – Read/Write R/W R/W R/W R/W R/W – – – Addressing Mode Register addressing only .7 – .3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 -byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1, selecting the 8-byte working register slice C0H – C7H. .2 – .0 Not used for the S3C826A RP1 — Register Pointer 1 D7H Set 1 RESETRESET Value 1 1 0 0 1 – – – Read/Write R/W R/W R/W R/W R/W – – – Addressing Mode Register addressing only .7 – .3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 -byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP1 points to address C8H in register set 1, selecting the 8-byte working register slice C8H–CFH. .2 – .0 Not used for the S3C826A

S3C826A/P826A CONTR OL REGISTER 4- 39 SIOCON — SIO Control Register E0 H Set 1 , Bank 0 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 SIO Shift Clock Selection Bit 0 Internal clock ( P.S clock)

1 External clock (SCK)

.6 Data Direction Control Bit

0 MSB-first mode

1 LSB-first mode

.5 SIO Mode Selection Bit

0 Receive-only mode

1 Transmit/receive mode

.4 Shift Clock Edge Selection Bit

0 Tx at falling edges, Rx at rising edges

1 Tx at rising edges, Rx at falling edges

.3 SIO Counter Clear and Shift Start Bit

0 No action

1 Clear 3-bit counter and start shifting

.2 SIO Shift Operation Enable Bit

0 Disable shifter and clock counter

1 Enable shifter and clock counter

.1 SIO Interrupt Enable Bit

0 Disable SIO Interrupt

1 Enable SIO Interrupt

.0 SIO Interrupt Pending Bit

0 No interrupt pending

0 Clear pending condition (when write)

1 Interrupt is pending

CONTROL REGISTERS S 3C826A/P826A 4- 40 SPH — Stack Pointer (High Byte ) D8H Set 1 RESETRESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .0 Stack Pointer Address (High Byte) The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (SP15–SP8). The lower byte of the stack pointer value is located in register SPL (D9H). The SP value is undefined following a reset. SPL — Stack Pointer (Low Byte ) D9H Set 1 RESETRESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 – .0 Stack Pointer Address (Low Byte) The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer address (SP7–SP0). The upper byte of the stack pointer value is located in register SPH (D8H). The SP value is undefined following a reset.

S3C826A/P826A CONTR OL REGISTER 4- 41 STPCON — Stop Control Register D1 H Set 1 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 –.0 STOP Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Other values Disable stop instruction NOTE: Before execute the STOP instruction, set this STPCON register as “10100101b”. Otherwise the STOP instruction will not execute as well as reset will be generated.

CONTROL REGISTERS S 3C826A/P826A 4- 42 SYM — System Mode Register DE H Set 1 RESETRESET Value 0 – – x x x 0 0 Read/Write R/W – – R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Not used, But you must keep "0" .6– .5 Not used for the S3C826A .4 – .2 Fast Interrupt Level Selection Bits ( 1 ) 0 0 0 IRQ0 0 0 1 IRQ1 0 1 0 IRQ2 0 1 1 IRQ3 1 0 0 IRQ4 1 0 1 IRQ5 1 1 0 IRQ6 1 1 1 IRQ7 .1 Fast Interrupt Enable Bit ( 2 )

0 Disable fast interrupt processing

1 Enable fast interrupt processing

.0 Global Interrupt Enable Bit ( 3 )

0 Disable all interrupt processing

1 Enable all interrupt processing

NOTES : 1 . You can select only one interrupt level at a time for fast interrupt processing. 3 . Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1" to SYM.0).

S3C826A/P826A CONTR OL REGISTER 4- 43 T0CON — Timer 0 Control Register E5 H Set 1 , Bank 0 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.5 Timer 0 Input Clock Selection Bits 0 0 0 fxx/1024 0 0 1 fxx/256 0 1 0 fxx/64 0 1 1 fxx/8 1 0 0 fxx 1 0 1 External clock (T0CLK) falling edge 1 1 0 External clock (T0CLK) rising edge 1 1 1 Counter stop .4 –.3 Timer 0 Operating Mode Selection Bits 0 0 Interval mode 0 1 Capture mode (capture on rising edge, counter running, OVF can occur) 1 0 Capture mode (capture on falling edge, counter running, OVF can occur) 1 1 PWM mode (OVF & match interrupt can occur) .2 Timer 0 Counter Clear Bit (note)

1 Clear the timer 0 counter (when write)

.1 Timer 0 Match/Capture Interrupt Enable Bit .0 Timer 0 Overflow Interrupt Enable

0 Disable overflow interrupt

1 Enable overflow interrupt

NOTE: When you write a "1" to T0CON.2, the timer 0 counter value is cleared to "00H". Immediately following the write operation, the T0CON.2 value is automatically cleared to "0".

CONTROL REGISTERS S 3C826A/P826A 4- 44 TACON — Timer 1/A Control Register EB H Set 1 , Bank 0 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Timer 1 Operating Mode Selection Bit

0 Two 8-bit timers mode (Timer A/B)

1 One 16-bit timer mode (Timer 1)

.6–.4 Timer 1/A Clock Selection Bits 0 0 0 fxx/256 0 0 1 fxx/64 0 1 0 fxx/8 0 1 1 fxx 1 1 1 External clock (T1CLK) rising edge .3 Timer 1/A Counter Clear Bit (NOTE)

1 Clear the timer 1/A counter (when write)

.2 Timer 1/A Counter Run Enable Bit

0 Disable Counter Running

1 Enable Counter Running

.1 Timer 1/A Interrupt Enable Bit .0 Timer 1/A Interrupt Pending Bit

0 No interrupt pending (when read)

1 Interrupt is pending (when read)

NOTE: When you write a "1" to TACON.3, the Timer 1/A counter value is cleared to "00H". Immediately following the write operation, the TACON.3 value is automatically cleared to "0".

S3C826A/P826A CONTR OL REGISTER 4- 45 TBCON — Timer B Control Register EAH Set 1, Bank0 RESETRESET Value – – 0 0 0 0 0 0 Read/Write – – R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 and .6 Not used for the S3C826A .5 and .4 Timer B Clock Selection Bits 0 0 fxx/256 0 1 fxx/64 1 0 fxx/8 1 1 fxx .3 Timer B Counter Clear Bit (NOTE)

1 Clear the timer B counter (when write)

.2 Timer B Counter Run Enable Bit .1 Timer B Interrupt Enable Bit .0 Timer B Interrupt Pending Bit NOTE: When you write a "1" to TBCON.3, the Timer B counter value is cleared to "00H". Immediately following the write operation, the TBCON.3 value is automatically cleared to "0".

CONTROL REGISTERS S 3C826A/P826A 4- 46 T 2 CON — Timer 2 Control Register EE H Set 1 , Bank 0 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.5 Timer 2 Input Clock Selection Bits 0 0 0 fxx/256 0 0 1 fxx/64 0 1 0 fxx/8 0 1 1 fxx 1 1 1 External clock (T2CLK) input .4 Not used for the S3C826A .3 Timer 2 Counter Clear Bit (Note)

1 Clear the timer 2 counter (when write)

.2 Timer 2 Counter Enable Bit

0 Disable counting operation

1 Enable counting operation

.1 Timer 2 Interrupt Enable Bit

0 Disable timer 2 interrupt

1 Enable timer 2 interrupt

.0 Timer 2 Interrupt Pending Bit

0 No timer 2 interrupt pending (when read)

0 Clear timer 2 interrupt pending bit (when write)

1 T2 interrupt is pending

NOTE: When you write a "1" to T2CON.3, the timer 2 counter value is cleared to "00H". Immediately following the write operation, the T2CON.3 value is automatically cleared to "0".

S3C826A/P826A CONTR OL REGISTER 4- 47 T3CON — Timer 3 Control Register F1H Set 1, Bank0 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.5 Timer 3 Input Clock Selection Bits 0 0 0 fxx/1024 0 0 1 fxx/256 0 1 0 fxx/64 0 1 1 fxx/8 1 0 0 fxx 1 0 1 External clock (T3CLK) falling edge 1 1 0 External clock (T3CLK) rising edge 1 1 1 Counter stop .4 - .3 Timer 3 Operating Mode Selection Bits 0 0 Interval mode 0 1 Capture mode (capture on rising edge, counter running, OVF can occur) 1 0 Capture mode (capture on falling edge, counter running, OVF can occur) 1 1 PWM mode (OVF & match interrupt can occur) .2 Timer 3 Counter Clear Bit (NOTE)

1 Clear the timer 3 counter (when write)

.1 Timer 3 match/capture interrupt enable bit .0 Timer 3 overflow interrupt enable NOTE: When you write a "1" T3CON.2, the timer 3 counter value is cleared to "00H". Immediately following the write operation, the T3CON.2 value is automatically cleared to "0".

CONTROL REGISTERS S 3C826A/P826A 4- 48 WTCON — Watch Timer Control Register F6H Set 1, Bank0 RESETRESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Watch Timer Clock Selection Bit

0 Select main clock divided by 2 7 (fx/128)

1 Select sub clock( fxt)

.6 Watch Timer Interrupt Enable Bit

0 Disable watch timer interrupt

1 Enable watch timer interrupt

.5-.4 Buzzer Signal Selection Bits 0 0 0.5 kHz 0 1 1 kHz 1 0 2 kHz 1 1 4 kHz .3-.2 Watch Timer Speed Selection Bits 0 0 Set watch timer interrupt to 1s 0 1 Set watch timer interrupt to 0.5s 1 0 Set watch timer interrupt to 0.25s 1 1 Set watch timer interrupt to 3.91ms .1 Watch Timer Enable Bit

0 Disable watch timer; Clear frequency dividing circuits

1 Enable watch timer

.0 Watch Timer Interrupt Pending Bit

S3C826A/P826A INTERRUPT STRUCTURE 5 - 1

5 INTERRUPT STRUCTURE

The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM88RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vec tor address, the vector priorities are established in hardware . A vector address can be assigned to one or more sources. Levels Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight possible interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies fr om device to device. The S3C826A interrupt structure recognizes eight interrupt levels. The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels. Vectors Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for S3C8 -series devices is always much smaller) . If an interrupt level has more than one vector address, the vector priorities are set in hardware. S3C826A uses twenty one vectors . Sources A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow . Each vector can have several interrupt sources. In the S3C826A interrupt structure, there are twenty one possible interrupt sources. When a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually" by program software. The characteristics of the source's pending mechanism determine which method would be used to clear its respective pending bit.

INTERRUPT STRUCTURE S3C826A/P826A 5- 2 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1): Type 1: One level (IRQn) + one vector (V 1 ) + one source (S 1 ) Type 2: One level (IRQn) + one vector (V 1 ) + multiple sources (S 1 – S n ) Type 3: One level (IRQn) + multiple vectors (V 1 – V n ) + multiple sources (S 1 – S n , S n+1 – S n+m ) In the S3C826A microcontroller, two interrupt types are implemented. Vectors SourcesLevels S 1 V 1 S 2Type 2: IRQn S 3 S n V 1 S 1 V 2 S 2Type 3: IRQn V 3 S 3 V 1 S 1Type 1: IRQn V n S n + 1 S n S n + 2 S n + m NOTES: 1. The number of S n and V n value is expandable. 2. In the S3C826A implementation, interrupt types 1 and 3 are used. Figure 5-1. S 3C8 -Series Interrupt Types

S3C826A/P826A INTERRUPT STRUCTURE 5 - 3 S3C826A INTERRUPT STRUCTURE The S3C826A microcontroller supports twenty one interrupt sources. All twenty three of the interrupt source s ha ve a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device- specific interrupt structure, as shown in Figure 5-2. When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single level are fixed in hardware) . When the CPU grants an interrupt request, interrupt processing starts . All other interrupts are disabled and the program counter value and status flags are pushed to stack. The starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed.

INTERRUPT STRUCTURE S3C826A/P826A 5- 4 Vectors SourcesLevels Reset/Clear IRQ2 E8H Timer 2 match EAH Timer 3 match/capture Timer B matchE4H Timer 1/A matchE6H IRQ1 S/W Watch timerD2HIRQ4 E0H Timer 0 match/capture IRQ0 E2H Timer 0 overflow S/W H/W,S/W S/W S/W S/W S/W NOTES: 1. Within a given interrupt level, the low vector address has high priority. For example, E0H has higher priority than E2H within the level IRQ0 the priorities within each level are set at the factory. 2. External interrupts are triggered by a rising or falling edge, depending on the corresponding control register setting. P3.4 external interrupt P3.5 external interrupt P3.6 external interrupt P3.7 external interrupt IRQ5 D4H D6H D8H DAH P0.4 external interrupt P0.5 external interrupt P0.6 external interrupt P0.7 external interrupt IRQ6 C0H C2H C4H C6H S/W S/W S/W S/W S/W S/W S/W S/W Basic timer overflow100HRESET H/W ECH Timer 3 overflow H/W, S/W IRQ3 D0H SIO interrupt S/W P0.0 external interrupt P0.1 external interrupt P0.2 external interrupt P0.3 external interrupt IRQ7 C8H CAH CCH CEH S/W S/W S/W S/W Figure 5-2. S3C826A Interrupt Structure

S3C826A/P826A INTERRUPT STRUCTURE 5 - 5 INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C826A interrupt structure are stored in the vector address area of the first 256 bytes of the program memory (ROM). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses) . The program reset address in the ROM is 0100H. 49,151 (Decimal) 255 48K-byte Program Memory Area 00H 100H FFH BFFFH (HEX) RESET Address Interrupt Vector Address Area Figure 5-3. ROM Vector Address Area

INTERRUPT STRUCTURE S3C826A/P826A 5- 6 Table 5-1. I nterrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Value Hex Value Interrupt Level Priority in Level H/W S/W 256 100H Basic timer overflow RESET – √

226 E2 H Timer 0 overflow IRQ0 1 √ √

224 E0 H Timer 0 match/capture 0 √

230 E6 H Timer 1/A match IRQ1 1 √

228 E4 H Timer B match 0 √

236 ECH Timer 3 overflow IRQ 2 2 √ √

234 EAH Timer 3 match/capture 1 √

232 E8H Timer 2 match 0 √

208 D0H SIO interrupt IRQ3 – √

210 D2H Watch timer IRQ4 – √

218 DAH P3.7 external interrupt IRQ 5 3 √ 216 D8H P3.6 external interrupt 2 √ 214 D6H P3.5 external interrupt 1 √ 212 D4H P3.4 external interrupt 0 √ 198 C6H P0.7 external interrupt IRQ6 3 √ 196 C4H P0.6 external interrupt 2 √ 194 C2H P0.5 external interrupt 1 √ 192 C0H P0.4 external interrupt 0 √ 206 CEH P0.3 external interrupt IRQ7 3 √ 204 CCH P0.2 external interrupt 2 √ 202 CAH P0.1 external interrupt 1 √ 200 C8H P0.0 external interrupt 0 √ NOTES: 1. Interrupt priorities are identified in inverse order: " 0 " is the highest priority, " 1 " is the next highest, and so on. 2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. The priorities within a given level are fixed in hardware.

S3C826A/P826A INTERRUPT STRUCTURE 5 - 7 ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI ) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities. NOTE The system initialization routine executed after a reset must always contain an EI instruction to globally enable the interrupt structure. During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing: — The interrupt m ask register, IMR, enables (un-masks) or disables (masks) interrupt levels. — The interrupt priority register, IPR, controls the relative priorities of interrupt levels. — The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source). — The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable fast interrupts and control the activity of external interface, if implemented) . Table 5-2. Interrupt Control Register Overview Control Register ID R/W Function Description Interrupt mask register IMR R/W Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels: IRQ0–IRQ7. Interrupt priority register IPR R/W Controls the relative processing priorities of the interrupt levels. The eight levels of S3C826A are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2, IRQ3 and IRQ4, and group C is IRQ5 , IRQ6 , and IRQ7 . Interrupt request register IRQ R This register contains a request pending bit for each interrupt level. System mode register SYM R/W This register enable s/ disable s fast interrupt processing, and d yna mic global interrupt processing. NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended.

INTERRUPT STRUCTURE S3C826A/P826A 5- 8 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. T he system-level control points in the interr upt structure are : — Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0 ) — Interrupt level enable/disable settings (IMR register) — Interrupt level priority settings (IPR register) — Interrupt source enable/disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information. Interrupt Request Register (Read-only) IRQ0-IRQ7, Interrupts Interrupt Mask Register Polling Cycle Interrupt Priority Register Global Interrupt Control (EI, DI or SYM.0 manipulation) S R Q RESET EI Vector Interrupt Cycle Figure 5-4. Interrupt Function Diagram

S3C826A/P826A INTERRUPT STRUCTURE 5 - 9 PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-3). Table 5-3. Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register(s) Location(s) in Set 1 Timer 0 overflow Timer 0 match/capture IRQ0 T0CON T0CNT T0DATA INTPND E5H, bank 0 E3H, bank 0 E4H, bank 0 D0H Timer 1/A match IRQ1 TACON TACNT TADATA EBH, bank 0 E7H, bank 0 E9H, bank0 Timer B match TBCON TBCNT TBDATA EAH, bank 0 E6H, bank 0 E8H, bank 0 Timer 3 overflow Timer 3 match/capture IRQ2 T3CON T3CNT T3DATA INTPND F1H, bank 0 F2H, bank 0 F3H, bank 0 D0H Timer 2 match T2CON T2CNT T2DATA EEH, bank 0 ECH, bank 0 EDH, bank 0 SIO interrupt IRQ3 SIOCON SIODATA SIOPS E0H, bank 0 E1H, bank 0 E2H, bank 0 Watch timer IRQ4 WTCON F6H, bank 0 P3.7 external interrupt P3.6 external interrupt P3.5 external interrupt P3.4 external interrupt IRQ5 P3CONH P3INT ECH, bank 1 EEH, bank 1 P0.7 external interrupt P0.6 external interrupt P0.5 external interrupt P0.4 external interrupt IRQ6 P0CONH P0INT P0PND P0EDGE E0H, bank 1 E3H, bank 1 E4H, bank 1 E2H, bank 1 P0.3 external interrupt P0.2 external interrupt P0.1 external interrupt P0.0 external interrupt IRQ 7 P0CONL P0INT P0PND P0EDGE E1H, bank 1 E3H, bank 1 E4H, bank 1 E2H, bank 1

INTERRUPT STRUCTURE S3C826A/P826A 5- 10 SYSTEM MODE REGISTER (SYM ) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see Figure 5-5). undetermined. The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the SYM register. In order to enable interrupt processing a n Enable Interrupt (EI) instruction must be included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions for this purpose. System Mode Register (SYM) DEH, Set 1, R/W Global interrupt enable bit: 0 = Disable all interrupts processing 1 = Enable all interrupts processing Fast interrupt enable bit: 0 = Disable fast interrupts processing 1 = Enable fast interrupts processing Fast interrupt level selection bits: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Not used for the S3C826A Always logic "0" Figure 5-5. System Mode Register (SYM )

S3C826A/P826A INTERRUPT STRUCTURE 5 - 11 INTERRUPT MASK REGISTER (IMR ) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine. Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's IMR bit to "1", interrupt processing for the level is enabled (not masked). The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions using the Register addressing mode. Interrupt Mask Register (IMR) DDH, Set 1, R/W IRQ1IRQ2 IRQ4IRQ5IRQ6IRQ7 IRQ0 Interrupt level enable bits 0 = Disable (mask) interrupt level 1 = Enable (un-mask) interrupt level IRQ3 NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended. Figure 5-6. Interrupt Mask Register (IMR )

INTERRUPT STRUCTURE S3C826A/P826A 5- 12 INTERRUPT PRIORITY REGISTER (IPR ) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine. When more than one interrupt source s are active, the source with the highest priority level is serviced first. If two sources belong to the same interrupt level, the source with the lowe r vector address usually has the priority (This priority is fixed in hardware) . To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register priority definitions (see Figure 5-7): Group A IRQ0, IRQ1 Gr oup B IRQ 2, IRQ3, IRQ3 Group C IRQ5, IRQ6 , IRQ7 IPR Group B IPR Group C IRQ2 IRQ4 IRQ3 B22B21 IRQ5 IRQ7 IRQ6 C22C21 IPR Group A IRQ1 IRQ0 Figure 5-7. Interrupt Request Priority Groups As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C. For example, the setting " 001B " for these bits would select the group relationship B > C > A . T he setting " 101B " would select the relationship C > B > A. The functions of the other IPR bit settings are as follows: — IPR.5 controls the relative priorities of group C inte rrupts. — Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 , — IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.

S3C826A/P826A INTERRUPT STRUCTURE 5 - 13 Interrupt Priority Register (IPR) FFH, Set 1, Bank 0, R/W Group A 0 = IRQ0 > IRQ1 1 = IRQ1 > IRQ0 Subgroup B 0 = IRQ3 > IRQ4 1 = IRQ4 > IRQ3 Group C 0 = IRQ5 > (IRQ6, IRQ7) 1 = (IRQ6, IRQ7) > IRQ5 Subgroup C 0 = IRQ6 > IRQ7 1 = IRQ7 > IRQ6 Group B 0 = IRQ2 > (IRQ3, IRQ4) 1 = (IRQ3, IRQ4) > IRQ2 Group priority: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 = Undefined = B > C > A = A > B > C = B > A > C = C > A > B = C > B > A = A > C > B = Undefined D7 D4 D1 Figure 5-8. Interrupt Priority Register (IPR )

INTERRUPT STRUCTURE S3C826A/P826A 5- 14 INTERRUPT REQUEST REGISTER (IRQ ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level . A "1" indicates that an interrupt request has been generated for that level. IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. After a reset, all IRQ status bits are cleared to “0”. You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can, however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events occurred while the interrupt structure was globally disabled. Interrupt Request Register (IRQ) DCH, Set 1, Read-only IRQ1IRQ2IRQ3IRQ4IRQ5IRQ6IRQ7 IRQ0 Interrupt level request pending bits: 0 = Interrupt level is not pending 1 = Interrupt level is pending Figure 5-9. Interrupt Request Register (IRQ )

S3C826A/P826A INTERRUPT STRUCTURE 5 - 15 INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: o ne type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine. Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software. In the S3C826A interrupt structure, the timer 0 overflow interrupt (IRQ0 ) and Timer 3 overflow interrupt (IRQ2) belongs to this category of interrupts in which pending condition is cleared automatically by hardware. Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software. The service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written to the corresponding pending bit location in the source’s mode or control register. FF PROGRAMMING TIP — How to Clear an Interrupt Pending Bit As the following examples are shown, a load instruction should be used to clear an interrupt pending bit. Examples: 1. LD INTPND,#00001011B ; Clear timer 3 overflow interrupt pending bit IRET 2. LD P 0PND,#11101111B ; Clear external interrupt INT4 pending bit IRET

INTERRUPT STRUCTURE S3C826A/P826A 5- 16 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source. 3. The CPU checks the source's interrupt level. 4. The CPU generates an interrupt acknowledge signal. 5. Interrupt logic determines the interrupt's vector address. 6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software). 7. The CPU continues polling for interrupt requests. INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced, the following conditions must be met: — Interrupt processing must be globally enabled (EI, SYM.0 = "1") — The interrupt level must be enabled (IMR register) — The interrupt level must have the highest priority if more than one level s are currently requesting service — The interrupt must be enabled at the interrupt's source (peripheral control register) When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts. 2. Save the program counter (PC) and status flags to the system stack. 3. Branch to the interrupt vector to fetch the address of the service routine. 4. Pass control to the interrupt service routine. When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores the PC and status flags , set ting SYM.0 to "1" . It allows the CPU to process the next interrupt request.

S3C826A/P826A INTERRUPT STRUCTURE 5 - 17 GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack. 2. Push the program counter's high-byte value to the stack. 3. Push the FLAG register values to the stack. 4. Fetch the service routine's high-byte address from the vector location. 5. Fetch the service routine's low-byte address from the vector location. 6. Branch to the service routine specified by the concatenated 16-bit vector address. NOTE A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H–FFH. NESTING OF VECTORED INTERRUPTS It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this, you must follow these steps: 1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR). 2. Load the IMR register with a new mask value that enables only the higher priority interrupt. 3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). 4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the previous mask value from the stack (POP IMR). 5. Execute an IRET. Depending on the application, you may be able to simplify the procedure above to some extent. INSTRUCTION POINTER (IP ) The instruction pointer (IP) is adopted by all the S3C8 -series microcontrollers to control the optional high-speed interrupt processing feature called fast interrupts . The IP consists of register pair DAH and DBH. The names of IP register s are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0). FAST INTERRUPT PROCESSING The feature called fast interrupt processing allows an interrupt within a given level to be completed in approxim ately 6 clock cycles rather than the usual 16 clock cycles. To select a specific interrupt level for fast interrupt processing, you write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt processing for the selected level, you set SYM.1 to “1”.

INTERRUPT STRUCTURE S3C826A/P826A 5- 18 FAST INTERRUPT PROCESSING ( Continued) Two other system registers support fast interrupt processing: — The instruction pointer (IP) contains the st arting address of the service routine (and is later used to swap the program counter values), and — When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register called FLAGS' ( " FLAGS prime " ). NOTE For the S3C826A microcontroller, the service routine for any one of the eight interrupt levels: IRQ0– IRQ7 , can be selected for fast interrupt processing. Procedure for Initiating Fast Interrupts To initiate fast interrupt processing, follow these steps: 1. Load the start address of the service routine into the instruction pointer (IP). 2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4 –SYM.2) 3. Write a "1" to the fast interrupt enable bit in the SYM register. Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing, the following events occur: 1. The contents of the instruction pointer and the PC are swapped. 2. The FLAG register values are written to the FLAGS' ( “FLAGS prime”) register. 3. The fast interrupt status bit in the FLAGS register is set. 4. The interrupt is serviced. 5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and PC values are swapped back. 6. The content of FLAGS' ( " FLAGS prime " ) is copied automatically back to the FLAGS register. 7. The fast interrupt status bit in FLAGS is cleared automatically. Relationship to Interrupt Pending Bit Types As described previously, there are two types of interrupt pending bits: One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed ; the other that must be cleared by the application program's interrupt service routine. You can select fast interrupt processing for interrupts with either type of pending condition clear function — by hardware or by software. Programming Guidelines Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing, including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast interrupt service routine ends.

S3C826A/P826A INSTR UCTION SET 6- 1

6 INSTRUCTION SET

The SAM88RC instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: — A full complement of 8-bit arithmetic and logic operations, including multiply and divide — No special I/O instructions (I/O control/data registers are mapped directly into the register file) — Decimal adjustment included in binary-coded decimal (BCD) operations — 16-bit (word) data can be incremented and decremented — Flexible instructions for bit addressing, rotate, and shift operations DATA TYPES The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. REGISTER ADDRESSING To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces." ADDRESSING MODES There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to Section 3, "Addressing Modes."

INSTRUCTION SET S3C826A/ P826A 6- 2 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst,src Load LDB dst,src Load bit LDE dst,src Load external data memory LDC dst,src Load program memory LDED dst,src Load external data memory and decrement LDCD dst,src Load program memory and decrement LDEI dst,src Load external data memory and increment LDCI dst,src Load program memory and increment LDEPD dst,src Load external data memory with pre-decrement LDCPD dst,src Load program memory with pre-decrement LDEPI dst,src Load external data memory with pre-increment LDCPI dst,src Load program memory with pre-increment LDW dst,src Load word POP dst Pop from stack POPUD dst,src Pop user stack (decrementing) POPUI dst,src Pop user stack (incrementing) PUSH src Push to stack PUSHUD dst,src Push user stack (decrementing) PUSHUI dst,src Push user stack (incrementing)

S3C826A/P826A INSTR UCTION SET 6- 3 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions ADC dst,src Add with carry ADD dst,src Add CP dst,src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst,src Divide INC dst Increment INCW dst Increment word MULT dst,src Multiply SBC dst,src Subtract with carry SUB dst,src Subtract Logic Instructions AND dst,src Logical AND COM dst Complement OR dst,src Logical OR XOR dst,src Logical exclusive OR

INSTRUCTION SET S3C826A/ P826A 6- 4 Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump relative on false BTJRT dst,src Bit test and jump relative on true CALL dst Call procedure CPIJE dst,src Compare, increment and jump on equal CPIJNE dst,src Compare, increment and jump on non-equal DJNZ r,dst Decrement register and jump on non-zero ENTER Enter EXIT Exit IRET Interrupt return JP cc,dst Jump on condition code JP dst Jump unconditional JR cc,dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst,src Bit AND BCP dst,src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst,src Bit OR BXOR dst,src Bit XOR TCM dst,src Test complement under mask TM dst,src Test under mask

S3C826A/P826A INSTR UCTION SET 6- 5 Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through carry RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SB0 Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP src Set register pointers SRP0 src Set register pointer 0 SRP1 src Set register pointer 1 STOP Enter Stop mode

INSTRUCTION SET S3C826A/ P826A 6- 6 FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic. The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result. System Flags Register (FLAGS) D5H, Set 1, R/W Bank address status flag (BA) Fast interrupt status flag (FIS) Half-carry flag (H) Decimal adjust flag (D) Carry flag (C) Zero flag (Z) Sign flag (S) Overflow flag (V) Figure 6-1. System Flags Register (FLAGS)

S3C826A/P826A INSTR UCTION SET 6- 7 FLAG DESCRIPTIONS C Carry Fl ag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag. Z Zero Flag (FLAGS.6) For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero. S Sign Flag (FLAGS.5) Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number. V Overflow Flag (FLAGS.4) The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than – 128. It is also cleared to "0" following logic operations. D Decimal Adjust Flag (FLAGS.3) The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by programmers, and cannot be used as a test condition. H Half-Carry Flag (FLAGS.2) The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a program. FIS Fast Interrupt Status Flag (FLAGS.1) The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing. When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed. BA Bank Address Flag (FLAGS.0) The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and is set to "1" (select bank 1) when you execute the SB1 instruction.

INSTRUCTION SET S3C826A/ P826A 6- 8 INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag D Decimal-adjust flag H Half-carry flag

0 Cleared to logic zero

1 Set to logic one

Set or cleared according to operation – Value is unaffected x Value is undefined Table 6-3. Instruction Set Symbols Symbol Description dst Destination operand src Source operand @ Indirect register address prefix PC Program counter IP Instruction pointer FLAGS Flags register (D5H) RP Register pointer # Immediate operand or register address prefix H Hexadecimal number suffix D Decimal number suffix B Binary number suffix opc Opcode

S3C826A/P826A INSTR UCTION SET 6- 9 Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6-6. r Working register only Rn (n = 0–15) rb Bit (b) of working register Rn.b (n = 0–15, b = 0–7) r0 Bit 0 (LSB) of working register Rn (n = 0–15) rr Working register pair RRp (p = 0, 2, 4, ..., 14) R Register or working register reg or Rn (reg = 0–255, n = 0–15) Rb Bit 'b' of register or working register reg.b (reg = 0–255, b = 0–7) RR Register pair or working register pair reg or RRp (reg = 0–254, even number only, where p = 0, 2, ..., 14) IA Indirect addressing mode addr (addr = 0–254, even number only) Ir Indirect working register only @Rn (n = 0–15) IR Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15) Irr Indirect working register pair only @RRp (p = 0, 2, ..., 14) IRR Indirect register pair or indirect working register pair @RRp or @reg (reg = 0–254, even only, where p = 0, 2, ..., 14) X Indexed addressing mode #reg [Rn] (reg = 0–255, n = 0–15) XS Indexed (short offset) addressing mode #addr [RRp] (addr = range –128 to +127, where p = 0, 2, ..., 14) xl Indexed (long offset) addressing mode #addr [RRp] (addr = range 0–65535, where p = 0, 2, ..., 14) da Direct addressing mode addr (addr = range 0–65535) ra Relative addressing mode addr (addr = number in the range +127 to –128 that is an offset relative to the address of the next instruction) im Immediate addressing mode #data (data = 0–255) iml Immediate (long) addressing mode #data (data = range 0–65535)

INSTRUCTION SET S3C826A/ P826A 6- 10 Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0 1 2 3 4 5 6 7 U 0 DEC DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM BOR r0–Rb P 1 RLC RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM BCP r1.b, R2 P 2 INC INC IR1 SUB r1,r2 SUB r1,Ir2 SUB R2,R1 SUB IR2,R1 SUB R1,IM BXOR r0–Rb E 3 JP IRR1 SRP/0/1 IM SBC r1,r2 SBC r1,Ir2 SBC R2,R1 SBC IR2,R1 SBC R1,IM BTJR r2.b, RA R 4 DA DA IR1 OR r1,r2 OR r1,Ir2 OR R2,R1 OR IR2,R1 OR R1,IM LDB r0–Rb

5 POP

r1,r2 AND r1,Ir2 AND R2,R1 AND IR2,R1 AND R1,IM BITC r1.b N 6 COM COM IR1 TCM r1,r2 TCM r1,Ir2 TCM R2,R1 TCM IR2,R1 TCM R1,IM BAND r0–Rb I 7 PUSH PUSH IR2 TM r1,r2 TM r1,Ir2 TM R2,R1 TM IR2,R1 TM R1,IM BIT r1.b B 8 DECW RR1 DECW IR1 PUSHUD IR1,R2 PUSHUI IR1,R2 MULT R2,RR1 MULT IR2,RR1 MULT IM,RR1 LD r1, x, r2 B 9 RL RL IR1 POPUD IR2,R1 POPUI IR2,R1 DIV R2,RR1 DIV IR2,RR1 DIV IM,RR1 LD r2, x, r1 L A INCW RR1 INCW IR1 CP r1,r2 CP r1,Ir2 CP R2,R1 CP IR2,R1 CP R1,IM LDC r1, Irr2, xL E B CLR CLR IR1 XOR r1,r2 XOR r1,Ir2 XOR R2,R1 XOR IR2,R1 XOR R1,IM LDC r2, Irr2, xL C RRC RRC IR1 CPIJE Ir,r2,RA LDC r1,Irr2 LDW RR2,RR1 LDW IR2,RR1 LDW RR1,IML LD r1, Ir2 H D SRA SRA IR1 CPIJNE Irr,r2,RA LDC r2,Irr1 CALL IA1 LD IR1,IM LD Ir1, r2 E E RR RR IR1 LDCD r1,Irr2 LDCI r1,Irr2 LD R2,R1 LD R2,IR1 LD R1,IM LDC r1, Irr2, xs X F SWAP SWAP IR1 LDCPD r2,Irr1 LDCPI r2,Irr1 CALL IRR1 LD IR2,R1 CALL DA1 LDC r2, Irr1, xs

S3C826A/P826A INSTR UCTION SET 6- 11 Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – 8 9 A B C D E F U 0 LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA INC NEXT P 2 EXIT E 3 WFI R 4 SB0

5 SB1

r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA INC NOP

INSTRUCTION SET S3C826A/ P826A 6- 12 CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6. The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions. Table 6-6. Condition Codes Binary Mnemonic Description Flags Set

0000 F Always false –

1000 T Always true –

0111 (note) C Carry C = 1 1111 (note) NC No carry C = 0 0110 (note) Z Zero Z = 1 1110 (note) NZ Not zero Z = 0

1101 PL Plus S = 0

0101 MI Minus S = 1

0100 OV Overflow V = 1

1100 NOV No overflow V = 0

0110 (note) EQ Equal Z = 1 1110 (note) NE Not equal Z = 0

1001 GE Greater than or equal (S XOR V) = 0

0001 LT Less than (S XOR V) = 1

1010 GT Greater than (Z OR (S XOR V)) = 0

0010 LE Less than or equal (Z OR (S XOR V)) = 1

1111 (note) UGE Unsigned greater than or equal C = 0 0111 (note) ULT Unsigned less than C = 1

1011 UGT Unsigned greater than (C = 0 AND Z = 0) = 1

0011 ULE Unsigned less than or equal (C OR Z) = 1

NOTES: 1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag ( Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used. 2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

S3C826A/P826A INSTR UCTION SET 6- 13 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: — Instruction name (mnemonic) — Full instruction name — Source/destination format of the instruction operand — Shorthand notation of the instruction's operation — Textual description of the instruction's effect — Specific flag settings affected by the instruction — Detailed description of the instruction's format, execution time, and addressing mode(s) — Programming example(s) explaining how to use the instruction

INSTRUCTION SET S3C826A/ P826A 6- 14 ADC — Add with carry ADC dst,src Operation: dst ← dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's- complement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. Flags: C: Set if there is a carry from the most significant bit of the result; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Examples: Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: ADC R1,R2 → R1 = 14H, R2 = 03H ADC R1,@R2 → R1 = 1BH, R2 = 03H ADC 01H,02H → Register 01H = 24H, register 02H = 03H ADC 01H,@02H → Register 01H = 2BH, register 02H = 03H ADC 01H,#11H → Register 01H = 32H In the first example, de stination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.

S3C826A/P826A INSTR UCTION SET 6- 15 ADD — Add ADD dst,src Operation: dst ← dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Set if there is a carry from the most significant bit of the result; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if a carry from the low-order nibble occurred. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 R R 6 05 R IR opc dst src 3 6 06 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: ADD R1,R2 → R1 = 15H, R2 = 03H ADD R1,@R2 → R1 = 1CH, R2 = 03H ADD 01H,02H → Register 01H = 24H, register 02H = 03H ADD 01H,@02H → Register 01H = 2BH, register 02H = 03H ADD 01H,#25H → Register 01H = 46H In the first example, destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1.

INSTRUCTION SET S3C826A/ P826A 6- 16 AND — Logical AND AND dst,src Operation: dst ← dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always cleared to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 R R 6 55 R IR opc dst src 3 6 56 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H , register 03H = 0AH: AND R1,R2 → R1 = 02H, R2 = 03H AND R1,@R2 → R1 = 02H, R2 = 03H AND 01H,02H → Register 01H = 01H, register 02H = 03H AND 01H,@02H → Register 01H = 00H, register 02H = 03H AND 01H,#25H → Register 01H = 21H In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1.

S3C826A/P826A INSTR UCTION SET 6- 17 BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) ← dst(0) AND src(b) or dst(b) ← dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | b | 0 src 3 6 67 r0 Rb opc src | b | 1 dst 3 6 67 Rb r0 NOTE : In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R1 = 07H and register 01H = 05H: BAND R1,01H.1 → R1 = 06H, register 01H = 05H BAND 01H. 1,R1 → Register 01H = 05H, R1 = 07H In the first example, source register 01H contains the value 05H (00000101B) and destination working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1 value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the value 06H (00000110B) in register R1.

INSTRUCTION SET S3C826A/ P826A 6- 18 BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison. Flags: C: Unaffected. Z: Set if the two bits are the same; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | b | 0 src 3 6 17 r0 Rb NOTE : In the second byte of the instruction format, the destination address is four bits, the bit ad dress 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H and register 01H = 01H: BCP R1,01H.1 → R1 = 07H, register 01H = 01H If destination working register R1 contains the value 07H (00000111B) and the source register 01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of the source register (01H) and bit zero of the destination register (R1). Because the bit values are not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).

S3C826A/P826A INSTR UCTION SET 6- 19 BITC — Bit Complement BITC dst.b Operation: dst(b) ← NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst | b | 0 2 4 57 rb NOTE : In the second byte of the instruction format, the d estination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H BITC R1.1 → R1 = 05H If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1" complements bit one of the destination and leaves the value 05H (00000101B) in register R1. Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is cleared.

INSTRUCTION SET S3C826A/ P826A 6- 20 BITR — Bit Reset BITR dst.b Operation: d st(b) ← 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst | b | 0 2 4 77 rb NOTE : In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BITR R1.1 → R1 = 05H If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one of the destination register R1, leaving the value 05H (00000101B).

S3C826A/P826A INSTR UCTION SET 6- 21 BITS — Bit Set BITS dst.b Operation: dst(b) ← 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst | b | 1 2 4 77 rb NOTE : In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BITS R1.3 → R1 = 0FH If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit three of the destination register R1 to "1", leaving the value 0FH (00001111B).

INSTRUCTION SET S3C826A/ P826A 6- 22 BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) ← dst(0) OR src(b) or dst(b) ← dst(b) OR src(0) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | b | 0 src 3 6 07 r0 Rb opc src | b | 1 dst 3 6 07 Rb r0 NOTE : In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit. Examples: Given: R1 = 07H and register 01H = 03H: BOR R1, 01H.1 → R1 = 07H, register 01H = 03H BOR 01H.2, R1 → Register 01H = 07H, R1 = 07H In the first example, destination working register R1 contains the value 07H (00000111B) and source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value (07H) in working register R1. In the second example, destination register 01H contains the value 03H (00000011B) and the source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in register 01H.

S3C826A/P826A INSTR UCTION SET 6- 23 BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRF instruction is executed. Flags: No flags are affected. Format: (Note 1) Bytes Cycles Opcode (Hex) Addr Mode dst src opc src | b | 0 dst 3 10 37 RA rb NOTE: In the second byte of the instruction format, the so urce address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BTJRF SKIP,R1.3 → PC jumps to SKIP location If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3" tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to – 128.)

INSTRUCTION SET S3C826A/ P826A 6- 24 BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC ← PC + dst The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRT instruction is executed. Flags: No flags are affected. Format: (Note 1) Bytes Cycles Opcode (Hex) Addr Mode dst src opc src | b | 1 dst 3 10 37 RA rb NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BTJRT SKIP,R1.1 If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1" tests bit one in the source register (R1). Because it is a "1", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to – 128.)

S3C826A/P826A INSTR UCTION SET 6- 25 BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) ← dst(0) XOR src(b) or dst(b) ← dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | b | 0 src 3 6 27 r0 Rb opc src | b | 1 dst 3 6 27 Rb r0 NOTE : In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R1 = 07H (00000111B) and registe r 01H = 03H (00000011B): BXOR R1,01H.1 → R1 = 06H, register 01H = 03H BXOR 01H.2,R1 → Register 01H = 07H, R1 = 07H In the first example, destination working register R1 has the value 07H (00000111B) and source register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is unaffected.

INSTRUCTION SET S3C826A/ P826A 6- 26 CALL — Call Procedure CALL dst Operation: SP ← SP – 1 @SP ← PCL SP ← SP –1 @SP ← PCH PC ← dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 IA Examples: Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H: CALL 3521H → SP = 0000H (Memory locations 0000H = 1AH, 0001H = 4AH, where 4AH is the address that follows the instruction.) CALL @RR0 → SP = 0000H (0000H = 1AH, 0001H = 49H) CALL #40H → SP = 0000H (0000H = 1AH, 0001H = 49H) In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed. If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 0001H (because the two-byte instruction format was used). The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed. Assuming that the contents of the program counter and stack pointer are the same as in the first example, if program address 0040H contains 35H and program address 0041H contains 21H, the statement "CALL #40H" produces the same result as in the second example.

S3C826A/P826A INSTR UCTION SET 6- 27 CCF — Complement Carry Flag CCF Operation: C ← NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 EF Example: Given: The carry flag = "0": CCF If the carry flag = "0", the CCF instructio n complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one.

INSTRUCTION SET S3C826A/ P826A 6- 28 CLR — Clear CLR dst Operation: dst ← "0" The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 B0 R

4 B1 IR

Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR 00H → Register 00H = 00H CLR @01H → Register 01H = 02H, register 02H = 00H In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H.

S3C826A/P826A INSTR UCTION SET 6- 29 COM — Complement COM dst Operation: dst ← NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the r esult bit 7 is set; cleared otherwise. V: Always reset to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 60 R 4 61 IR Examples: Given: R1 = 07H and register 07H = 0F1H: COM R1 → R1 = 0F8H COM @R1 → R1 = 07H, register 07H = 0EH In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B). In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B).

INSTRUCTION SET S3C826A/ P826A 6- 30 CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred (src > dst); cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | src 2 4 A2 r r

6 A3 r lr

6 A5 R IR

Examples: 1. Given: R1 = 02H and R2 = 03H: CP R1,R2 → Set the C an d S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1". 2. Given: R1 = 05H and R2 = 0AH: CP R1,R2 JP UGE,SKIP INC R1 SKIP LD R3,R1 In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3.

S3C826A/P826A INSTR UCTION SET 6- 31 CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst – src = "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise, the instruction immediately following the CPIJE instruction is executed. In either case, the source pointer is incremented by one before the next instruction is executed. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src dst RA 3 12 C2 r Ir NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 02H, R2 = 03H, and register 03H = 02H: CPIJE R1,@R2,SKIP → R2 = 04H, PC jumps to SKIP location In this example, working register R1 contains the value 02H, working register R2 the value 03H, and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value 02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal , the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to – 128.)

INSTRUCTION SET S3C826A/ P826A 6- 32 CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA Operation: If dst – src "0", PC ← PC + RA Ir ← Ir + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the CPIJNE instruction is executed. In either case the source pointer is incremented by one before the next instruction. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src dst RA 3 12 D2 r Ir NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 02H, R2 = 03H, and register 03H = 04H: CPIJNE R1,@R2,SKIP → R2 = 04H, PC jumps to SKIP location Working registe r R1 contains the value 02H, working register R2 (the source pointer) the value 03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts 04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal , the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to – 128.)

S3C826A/P826A INSTR UCTION SET 6- 33 DA — Decimal Adjust DA dst Operation: dst ← DA dst The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits): Instruction Carry Before DA Bits 4–7 Value (Hex) H Flag Before DA Bits 0–3 Value (Hex) Number Added to Byte Carry After DA 0 0–9 0 0–9 00 0 0 0–8 0 A–F 06 0 0 0–9 1 0–3 06 0 ADD 0 A–F 0 0–9 60 1 ADC 0 9–F 0 A–F 66 1

0 A–F 1 0–3 66 1

1 0–2 0 0–9 60 1 1 0–2 0 A–F 66 1 1 0–3 1 0–3 66 1 0 0–9 0 0–9 00 = – 00 0 SUB 0 0–8 1 6–F FA = – 06 0 SBC 1 7–F 0 0–9 A0 = – 60 1 1 6–F 1 6–F 9A = – 66 1 Flags: C: Set if there was a carry from the most significant bit; cleared otherwise (see table). Z: Set if result is "0"; cleared otherwise. S: Set if result b it 7 is set; cleared otherwise. V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 40 R 4 41 IR

INSTRUCTION SET S3C826A/ P826A 6- 34 DA — Decimal Adjust DA (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): ADD R1,R0 ; C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH DA R1 ; R1 ← 3CH + 06 If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic: 0 0 0 1 0 1 0 1 15 + 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 = 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained: 0 0 1 1 1 1 0 0 + 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 = 42 Assuming the same values given above, the statements SUB 27H,R0 ; C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = 1 leave the value 31 (BCD) in address 27H (@R1).

S3C826A/P826A INSTR UCTION SET 6- 35 DEC — Decrement DEC dst Operation: dst ← dst – 1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 00 R 4 01 IR Examples: Given: R1 = 03H and register 03H = 10H: DEC R1 → R1 = 02H DEC @R1 → Register 03H = 0FH In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH.

INSTRUCTION SET S3C826A/ P826A 6- 36 DECW — Decrement Word DECW dst Operation: dst ← dst – 1 The contents of the destination location (w hich must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 8 80 RR 8 81 IR Examples: Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H: DECW RR0 → R0 = 12H, R1 = 33H DECW @R2 → Register 30H = 0FH, register 31H = 20H In the first example, destination register R0 contains the value 12H and register R1 the value 34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word and decrements the value of R1 by one, leaving the value 33H. NOTE: A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW instruction. To avoid this problem, we recommend that you use DECW as shown in the following example: LOOP: DECW RR0 LD R2,R1 OR R2,R0 JR NZ,LOOP

S3C826A/P826A INSTR UCTION SET 6- 37 DI — Disable Interrupts DI Operation: SYM (0) ← 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 8F Example: Given: SYM = 01H: DI If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the register and clears SYM.0 to "0", disabling interrupt processing. Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.

INSTRUCTION SET S3C826A/ P826A 6- 38 DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) ← REMAINDER dst (LOWER) ← QUOTIENT The destination operand (16 bits ) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination. When the quotient is ≥ 2 8 , the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. Both operands are treated as unsigned integers. Flags: C: Set if the V flag is set and quotient is between 2 8 and 2 9 –1; cleared otherwise. Z: Set if divisor or quotient = "0"; cleared o therwise. S: Set if MSB of quotient = "1"; cleared otherwise. V: Set if quotient is ≥ 2 8 or if divisor = "0"; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src dst 3 26/10 94 RR R 26/10 95 RR IR 26/10 96 RR IM NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles. Examples: Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H: DIV RR0,R2 → R0 = 03H, R1 = 40H DIV RR0,@R2 → R0 = 03H, R1 = 20H DIV RR0,#20H → R0 = 03H, R1 = 80H In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H (R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination register RR0 (R0) and the quotient in the lower half (R1).

S3C826A/P826A INSTR UCTION SET 6- 39 DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r ← r – 1 If r ≠ 0, PC ← PC + dst The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC. The range of the relative address is +127 to –128, and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement. NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst r | opc dst 2 8 (jump taken) rA RA 8 (no jump) r = 0 to F Example: Given: R1 = 02H and LOOP is the label of a relative address: SRP #0C0H DJNZ R1,LOOP DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the destination operand instead of a numeric relative address value. In the example, working register R1 contains the value 02H, and LOOP is the label for a relative address. The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H. Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative address specified by the LOOP label.

INSTRUCTION SET S3C826A/ P826A 6- 40 EI — Enable Interrupts EI Operation: SYM (0) ← 1 An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 9F Example: Given: SYM = 00H: EI If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for global interrupt processing.)

S3C826A/P826A INSTR UCTION SET 6- 41 ENTER — Enter ENTER Operation: SP ← SP – 2 @SP ← IP IP ← PC PC ← @IP IP ← IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 14 1F Example: The diagram below shows one example of how to use an ENTER statement. 0050IP 0022SP

22 Data

110 Routine

INSTRUCTION SET S3C826A/ P826A 6- 42 EXIT — Exit EXIT Operation: IP ← @SP SP ← SP + 2 PC ← @IP IP ← IP + 2 This instruction is useful when im plementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 14 (internal stack) 2F 16 (internal stack) Example: The diagram below shows one example of how to use an EXIT statement. 0050IP 0022SP Address Data 0040PC Address Data Memory 0052IP 0022SP Address Data 0060PC Address Data Memory Stack Stack Before After

60 Main

S3C826A/P826A INSTR UCTION SET 6- 43 IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. In application programs, a IDLE instruction must be immediately followed by at least three NOP instructions. This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructons are not used after IDLE instruction, leakage current could be flown because of the floating state in the internal bus. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc 1 4 6F – – Example: The instruction IDLE ; stops the CPU clock but not the system clock NOP NOP NOP

INSTRUCTION SET S3C826A/ P826A 6- 44 INC — Increment INC dst Operation: dst ← dst + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwis e. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst dst | opc 1 4 rE r r = 0 to F opc dst 2 4 20 R 4 21 IR Examples: Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH: INC R0 → R0 = 1CH INC 00H → Register 00H = 0DH INC @R0 → R0 = 1BH, register 01H = 10H In the first example, if de stination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register. The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH. In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H.

S3C826A/P826A INSTR UCTION SET 6- 45 INCW — Increment Word INCW dst Operation: dst ← dst + 1 The contents of the destination (which must be an even addre ss) and the byte following that location are treated as a single 16-bit value that is incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 8 A0 RR

8 A1 IR

Examples: Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH: INCW RR0 → R0 = 1AH, R1 = 03H INCW @R1 → Register 02H = 10H, register 03H = 00H In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to 00H and register 02H from 0FH to 10H. NOTE: A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the following example: LOOP: INCW RR0 LD R2,R1 OR R2,R0 JR NZ,LOOP

INSTRUCTION SET S3C826A/ P826A 6- 46 IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) Operation: FLAGS ← @SP PC ↔ IP SP ← SP + 1 FLAGS ← FLAGS' PC ← @SP FIS ← 0 SP ← SP + 2 SYM(0) ← 1 This instruction is used at the end of an interrupt service routine. It r estores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine. Flags: All flags are restored to their original settings (that is, the settings before the interrupt occurred). Format: IRET (Normal) Bytes Cycles Opcode (Hex) opc 1 10 (internal stack) BF 12 (internal stack) IRET (Fast) Bytes Cycles Opcode (Hex) opc 1 6 BF Example: In the figure below, the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are swapped. This causes the PC to jump to address 100H and the IP to keep the return address. The last instruction in the service routine normally is a jump to IRET at address FFH. This causes the instruction pointer to be loaded with 100H "again" and the program counter to jump back to the main program. Now, the next interrupt can occur and the IP is still correct at 100H. IRET Interrupt Service Routine JP to FFH FFH 100H FFFFH NOTE: In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay attention to the order of the last two instructions. The IRET cannot be immediately proceeded by a clearing of the interrupt status (as with a reset of the IPR register).

S3C826A/P826A INSTR UCTION SET 6- 47 JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ← dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC. Flags: No flags are affected. Format: (1) (2) Bytes Cycles Opcode (Hex) Addr Mode dst cc | opc dst 3 8 ccD DA cc = 0 to F opc dst 2 8 30 IRR NOTES : 1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits. Examples: Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H: JP C,LABEL_W → LABEL_W = 1000H, PC = 1000H JP @00H → PC = 0120H The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement "JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction. The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

INSTRUCTION SET S3C826A/ P826A 6- 48 JR — Jump Relative JR cc,dst Operation: If cc is true, PC ← PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed. (See list of condition codes). The range of the relative address is +127, –128, and t he original value of the program counter is taken to be the address of the first instruction byte following the JR statement. Flags: No flags are affected. Format: (1) Bytes Cycles Opcode (Hex) Addr Mode dst cc | opc dst 2 6 ccB RA cc = 0 to F NOTE : In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits. Example: Given: The carry flag = "1" and LABEL_X = 1FF7H: JR C,LABEL_X → PC = 1FF7H If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed.

S3C826A/P826A INSTR UCTION SET 6- 49 LD — Load LD dst,src Operation: dst ← src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src dst | opc src 2 4 rC r IM 4 r8 r R src | opc dst 2 4 r9 R r r = 0 to F opc dst | src 2 4 C7 r lr

4 D7 Ir r

6 E5 R IR

6 D6 IR IM

opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r

INSTRUCTION SET S3C826A/ P826A 6- 50 LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD R0,#10H → R0 = 10H LD R0,01H → R0 = 20H, register 01H = 20H LD 01H,R0 → Register 01H = 01H, R0 = 01H LD R1,@R0 → R1 = 20H, R0 = 01H LD @R0,R1 → R0 = 01H, R1 = 0AH, register 01H = 0AH LD 00H,01H → Register 00H = 20H, register 01H = 20H LD 02H,@00H → Register 02H = 20H, register 00H = 01H LD 00H,#0AH → Register 00H = 0AH LD @00H,#10H → Register 00H = 01H, register 01H = 10H LD @00H,02H → Register 00H = 01H, register 01H = 02, r egister 02H = 02H LD R0,#LOOP[R1] → R0 = 0FFH, R1 = 0AH LD #LOOP[R0],R1 → Register 31H = 0AH, R0 = 01H, R1 = 0AH

S3C826A/P826A INSTR UCTION SET 6- 51 LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) ← src(b) or dst(b) ← src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | b | 0 src 3 6 47 r0 Rb opc src | b | 1 dst 3 6 47 Rb r0 NOTE : In the second byte of the instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R0 = 06H and general register 00H = 05H: LDB R0,00H.2 → R0 = 07H, register 00H = 05H LDB 00H.0,R0 → R0 = 06H, register 00H = 04H In the first example, destination working register R0 contains the value 06H and the source general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the 00H register into bit zero of the R0 register, leaving the value 07H in register R0. In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in general register 00H.

INSTRUCTION SET S3C826A/ P826A 6- 52 LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ← src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src 1. opc dst | src 2 10 C3 r Irr 2. opc src | dst 2 10 D3 Irr r 3. opc dst | src XS 3 12 E7 r XS [rr] 4. opc src | dst XS 3 12 F7 XS [rr] r 5. opc dst | src XL L XL H 4 14 A7 r XL [rr] 6. opc src | dst XL L XL H 4 14 B7 XL [rr] r 7. opc dst | 0000 DA L DA H 4 14 A7 r DA 8. opc src | 0000 DA L DA H 4 14 B7 DA r 9. opc dst | 0001 DA L DA H 4 14 A7 r DA 10. opc src | 0001 DA L DA H 4 14 B7 DA r NOTES : 1. The source (src) or working register pair [rr] for for mats 5 and 6 cannot use register pair 0–1. 2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one byte. 3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes. 4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.

S3C826A/P826A INSTR UCTION SET 6- 53 LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC R0,@RR2 ; R0 ← contents of program memory location 0104H ; R0 = 1AH, R2 = 01H, R3 = 04H LDE R0,@RR2 ; R0 ← contents of external data memory location 0104H ; R0 = 2AH, R2 = 01H, R3 = 04H LDC (note) @RR2,R0 ; 11H (contents of R0) is loaded into program memory ; location 0104H (RR2), ; working registers R0, R2, R3 → no change LDE @RR2,R0 ; 11H (contents of R0) is loaded into external data memory ; location 0104H (RR2), ; working registers R0, R2, R3 → no change LDC R0,#01H[RR2] ; R0 ← contents of program memory location 0105H ; (01H + RR2), ; R0 = 6DH, R2 = 01H, R3 = 04H LDE R0,#01H[RR2] ; R0 ← contents of external data memory location 0105H ; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H LDC (note) #01H[RR2],R0 ; 11H (contents of R0) is loaded into program memory location ; 0105H (01H + 0104H) LDE #01H[RR2],R0 ; 11H (contents of R0) is loaded into external data memory ; location 0105H (01H + 0104H) LDC R0,#1000H[RR2] ; R0 ← contents of program memory location 1104H ; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H LDE R0,#1000H[RR2] ; R0 ← contents of external data memory location 1104H ; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H LDC R0,1104H ; R0 ← contents of program memory location 1104H, R0 = 88H LDE R 0,1104H ; R0 ← contents of external data memory location 1104H, ; R0 = 98H LDC (note) 1105H,R0 ; 11H (contents of R0) is loaded into program memory location ; 1105H, (1105H) ← 11H LDE 1105H,R0 ; 11H (contents of R0) is loaded into external data memory ; location 1105H, (1105H) ← 11H NOTE: These instructions are not supported by masked ROM type devices.

INSTRUCTION SET S3C826A/ P826A 6- 54 LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst ← src rr ← rr – 1 These instructions a re used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD references program memory and LDED references external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | src 2 10 E2 r Irr Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH: LDCD R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is decremented by one ; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 ← RR6 – 1) LDED R8,@RR6 ; 0DDH (contents of data memory location 1033H ) is loaded ; into R8 and RR6 is decremented by one (RR6 ← RR6 – 1) ; R8 = 0DDH, R6 = 10H, R7 = 32H

S3C826A/P826A INSTR UCTION SET 6- 55 LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst ← src rr ← rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected. LDCI refers to program memory and LDEI refers to external data memory. The assembler makes 'Irr' even for program memory and odd for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | src 2 10 E3 r Irr Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H = 0C5H; external data memory locat ions 1033H = 0DDH and 1034H = 0D5H: LDCI R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 ← RR6 + 1) ; R8 = 0CDH, R6 = 10H, R7 = 34H LDEI R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 ← RR6 + 1) ; R8 = 0DDH, R6 = 10H, R7 = 34H

INSTRUCTION SET S3C826A/ P826A 6- 56 LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src Operation: rr ← rr – 1 dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location. The contents of the source are unaffected. LDCPD refers to program memory and LDEPD refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for external data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src | dst 2 14 F2 Irr r Examples: Given: R0 = 77H, R6 = 30H, and R7 = 00H: LDCPD @RR6,R0 ; (RR6 ← RR6 – 1) ; 77H (contents of R0) is loaded into program memory location ; 2FFFH (3000H – 1H) ; R0 = 77H, R6 = 2FH, R7 = 0FFH LDEPD @RR6,R0 ; (RR6 ← RR6 – 1) ; 77H (contents of R0) is loaded into external data memory ; location 2FFFH (3000H – 1H) ; R0 = 77H, R6 = 2FH, R7 = 0FFH

S3C826A/P826A INSTR UCTION SET 6- 57 LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src Operation: rr ← rr + 1 dst ← src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected. LDCPI refers to program memo ry and LDEPI refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src | dst 2 14 F3 Irr r Examples: Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH: LDCPI @RR6,R0 ; (RR6 ← RR6 + 1) ; 7FH (contents of R0) is loaded into program memory ; location 2200H (21FFH + 1H) ; R0 = 7FH, R6 = 22H, R7 = 00H LDEPI @RR6,R0 ; (RR6 ← RR6 + 1) ; 7FH (contents of R0) is loaded into external data memory ; location 2200H (21FFH + 1H) ; R0 = 7FH, R6 = 22H, R7 = 00H

INSTRUCTION SET S3C826A/ P826A 6- 58 LDW — Load Word LDW dst,src Operation: dst ← src The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src dst 3 8 C4 RR RR

8 C5 RR IR

Examples: Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH, register 01H = 02H, register 02H = 03H, and register 03H = 0FH: LDW RR6,RR4 → R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH LDW 00H,02H → Register 00H = 03H, register 01H = 0FH, register 02H = 03H, register 03H = 0FH LDW RR2,@R7 → R2 = 03H, R3 = 0FH, LDW 04H,@01H → Register 04H = 03H, register 05H = 0FH LDW RR6,#1234H → R6 = 12H, R7 = 34H LDW 02H,#0FEDH → Register 02H = 0FH, register 03H = 0EDH In the second example, please note that the statement "LDW 00H,02H" loads the contents of the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in general register 00H and the value 0FH in register 01H. The other examples show how to use the LDW instruction with various addressing modes and formats.

S3C826A/P826A INSTR UCTION SET 6- 59 MULT — Multiply (Unsigned) MULT dst,src Operation: dst ← dst × src The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers. Flags: C: Set if result is > 255; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if MSB of the result is a "1"; cleared otherwise. V: Cleared. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples: Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H: MULT 00H, 02H → Register 00H = 01H, register 01H = 20H, register 02H = 09H MULT 00H, @01H → Register 00H = 00H, register 01H = 0C0H MULT 00H, #30H → Register 00H = 06H, register 01H = 00H In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The 16 -bit pro duct, 0120H, is stored in the register pair 00H, 01H.

INSTRUCTION SET S3C826A/ P826A 6- 60 NEXT — Next NEXT Operation: PC ← @ IP IP ← IP + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 10 0F Example: The following diagram shows one example of how to use the NEXT instruction. Data Before After 0045IP Address Data 0130PC 43 Address H Address L Address H Address Data Memory

130 Routine

120 Next

S3C826A/P826A INSTR UCTION SET 6- 61 NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 FF Example: When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.

INSTRUCTION SET S3C826A/ P826A 6- 62 OR — Logical OR OR dst,src Operation: dst ← dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always c leared to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 R R 6 45 R IR opc dst src 3 6 46 R IM Examples: Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH: OR R0,R1 → R0 = 3FH, R1 = 2AH OR R0,@R2 → R0 = 37H, R2 = 01H, register 01H = 37H OR 00H,01H → Register 00H = 3FH, regi ster 01H = 37H OR 01H,@00H → Register 00H = 08H, register 01H = 0BFH OR 00H,#02H → Register 00H = 0AH In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0. The other examples show the use of the logical OR instruction with the various addressing modes and formats.

S3C826A/P826A INSTR UCTION SET 6- 63 POP — Pop From Stack POP dst Operation: dst ← @SP SP ← SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 8 50 R 8 51 IR Examples: Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH, and stack register 0FBH = 55H: POP 00H → Register 00H = 55H, SP = 00FCH POP @00H → Register 00H = 01H, register 01H = 55H, SP = 00FCH In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 00FBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location 00FCH.

INSTRUCTION SET S3C826A/ P826A 6- 64 POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst ← src IR ← IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the reg ister file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src dst 3 8 92 R IR Example: Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and register 02H = 70H: POPUD 02H,@00H → Register 00H = 41H, register 02H = 6FH, register 42H = 6FH If general register 00H contains the value 42H and re gister 42H the value 6FH, the statement "POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The user stack pointer is then decremented by one, leaving the value 41H.

S3C826A/P826A INSTR UCTION SET 6- 65 POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst ← src IR ← IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc src dst 3 8 93 R IR Example: Given: Register 00H = 01H and register 01H = 70H: POPUI 02H,@00H → Register 00H = 02H, register 01H = 70H, register 02H = 70H If general register 00H contains the value 01H and register 01H the value 70H, the statement "POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.

INSTRUCTION SET S3C826A/ P826A 6- 66 PUSH — Push To Stack PUSH src Operation: SP ← SP – 1 @SP ← src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc src 2 8 (internal clock) 70 R 8 (external clock) 8 (internal clock) 8 (external clock) 71 IR Examples: Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H: PUSH 40H → Register 40H = 4FH, stack register 0FFH = 4FH, SPH = 0FFH, SPL = 0FFH PUSH @40H → Register 40H = 4FH, register 4FH = 0AAH, stack register 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH In the first example, if the stack pointer contains the value 0000H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It then loads the contents of register 40H into location 0FFFFH and adds this new value to the top of the stack.

S3C826A/P826A INSTR UCTION SET 6- 67 PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR ← IR – 1 dst ← src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst src 3 8 82 IR R Example: Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH: PUSHUD @00H,01H → Register 00H = 02H, register 01H = 05H, register 02H = 05H If the user stack pointer (register 00H, for example) contains the value 03H, the statement "PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The 01H register value, 05H, is then loaded into the register addressed by the decremented user stack pointer.

INSTRUCTION SET S3C826A/ P826A 6- 68 PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR ← IR + 1 dst ← src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst src 3 8 83 IR R Example: Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH: PUSHUI @00H,01H → Register 00H = 04H, register 01H = 05H, register 04H = 05H If the user stack pointer (register 00H, for example) contains the value 03H, the statement "PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H register value, 05H, is then loaded into the location addressed by the incremented user stack pointer.

S3C826A/P826A INSTR UCTION SET 6- 69 RCF — Reset Carry Flag RCF RCF Operation: C ← 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 CF Example: Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.

INSTRUCTION SET S3C826A/ P826A 6- 70 RET — Return RET Operation: PC ← @SP SP ← SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 8 (internal stack) AF 10 (internal stack) Example: Given: SP = 00FCH, (SP) = 101AH, and PC = 1234: RET → PC = 101AH, SP = 00FEH The statement "RET" pops the contents of stack point er location 00FCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 00FEH.

S3C826A/P826A INSTR UCTION SET 6- 71 RL — Rotate Left RL dst Operation: C ← dst (7) dst (0) ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. 7 0 C Flags: C: Set if the bit rotated from the most significant bit position (bit 7) was "1". Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 90 R 4 91 IR Examples: Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H: RL 00H → Register 00H = 55H, C = "1" RL @01H → Register 01H = 02H, register 02H = 2EH, C = "0" In the first example, if general register 00H contains the value 0AAH (10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags.

INSTRUCTION SET S3C826A/ P826A 6- 72 RLC — Rotate Left Through Carry RLC dst Operation: dst (0) ← C C ← dst (7) dst (n + 1) ← dst (n), n = 0–6 The co ntents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero. 7 0 C Flags: C: Set if the bit rotated from the most significant bit position (bit 7) was "1". Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed d uring rotation; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 10 R 4 11 IR Examples: Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0": RLC 00H → Register 00H = 54H, C = "1" RLC @01H → Register 01H = 02H, register 02H = 2EH, C = "0" In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.

S3C826A/P826A INSTR UCTION SET 6- 73 RR — Rotate Right RR dst Operation: C ← dst (0) dst (7) ← dst (0) dst (n ) ← dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). 7 0 C Flags: C: Set if the bit rotated from the least significant bit position (bit zero) was "1". Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 E0 R

4 E1 IR

Examples: Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H: RR 00H → Register 00H = 98H, C = "1" RR @01H → Register 01H = 02H, register 02H = 8BH, C = "1" In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1".

INSTRUCTION SET S3C826A/ P826A 6- 74 RRC — Rotate Right Through Carry RRC dst Operation: dst (7) ← C C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB). 7 0 C Flags: C: Set if the bit rotated from the least significant bit position (bit zero) was "1". Z: Set if the result is "0" cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 C0 R

4 C1 IR

Examples: Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0": RRC 00H → Register 00H = 2AH, C = "1" RRC @01H → Register 01H = 02H, register 02H = 0BH, C = "1" In the first example, if general register 00H contains the value 55H (01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".

S3C826A/P826A INSTR UCTION SET 6- 75 SB0 — Select Bank 0 SB0 Operation: BANK ← 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 4F Example: The statement SB0 clears FLAGS.0 to "0", selecting bank 0 register addressing.

INSTRUCTION SET S3C826A/ P826A 6- 76 SB1 — Select Bank 1 SB1 Operation: BANK ← 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to log ic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some S3C8-series microcontrollers.) Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 5F Example: The statement SB1 sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.

S3C826A/P826A INSTR UCTION SET 6- 77 SBC — Subtract with Carry SBC dst,src Operation: dst ← dst – src – c The source operand, along with the current value of the carry flag, is subtr acted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. Flags: C: Set if a borrow occurred (src > dst); cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 R R 6 35 R IR opc dst src 3 6 36 R IM Examples: Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: SBC R1,R2 → R1 = 0CH, R2 = 03H SBC R1,@R2 → R1 = 05H, R2 = 03H, register 03H = 0AH SBC 01H,02H → Register 01H = 1CH, register 02H = 03H SBC 01H,@02H → Register 01H = 15H,register 02H = 03H, register 03H = 0AH SBC 01H,#8AH → Register 01H = 95H; C, S, an d V = "1" In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1.

INSTRUCTION SET S3C826A/ P826A 6- 78 SCF — Set Carry Flag SCF Operation: C ← 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 DF Example: The statement SCF sets the carry flag to logic one.

S3C826A/P826A INSTR UCTION SET 6- 79 SRA — Shift Right Arithmetic SRA dst Operation: dst (7) ← dst (7) C ← dst (0) dst (n) ← dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. 7 0 C Flags: C: Set if the bit shifted from the LSB position (bit zero) was "1". Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Always cleared to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 D0 R

4 D1 IR

Examples: Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1": SRA 00H → Register 00H = 0CD, C = "0" SRA @02H → Register 02H = 03H, register 03H = 0DEH, C = "0" In the first example, if genera l register 00H contains the value 9AH (10011010B), the statement "SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in destination register 00H.

INSTRUCTION SET S3C826A/ P826A 6- 80 SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 1 then: RP1 (3–7) ← src (3–7) If src (1) = 0 and src (0) = 0 then: RP0 (4–7) ← src (4–7), RP0 (3) ← 0 RP1 (3) ← 1 The source data bits one and zero (LSB) determine whether to write one or both of the register pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode src opc src 2 4 31 IM Examples: The statement SRP #40H sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location 0D7H to 48H. The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to 68H.

S3C826A/P826A INSTR UCTION SET 6- 81 STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts. For the reset operation, the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed. In application programs, a STOP instruction must be immediately followed by at least three NOP instructions. This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructons are not used after STOP instruction, leakage current could be flown because of the floating state in the internal bus. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc 1 4 7F – – Example: The statement STOP ; halts all microcontroller operations NOP NOP NOP

INSTRUCTION SET S3C826A/ P826A 6- 82 SUB — Subtract SUB dst,src Operation: dst ← dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Flags: C: Set if a "borrow" occurred; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. D: Alw ays set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow". Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 R R 6 25 R IR opc dst src 3 6 26 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: SUB R1,R2 → R1 = 0FH, R2 = 03H SUB R1,@R2 → R1 = 08H, R2 = 03H SUB 01H,02H → Register 01H = 1EH, register 02H = 03H SUB 01H,@02H → Register 01H = 17H, register 02H = 03H SUB 01H,#90H → Register 01H = 91H; C, S, and V = "1" SUB 01H,#65H → Register 01H = 0BCH; C and S = "1", V = "0" In the first example, if working register R1 contains the value 12H and if register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in destination register R1.

S3C826A/P826A INSTR UCTION SET 6- 83 SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) ↔ dst (4 – 7) The contents of the lower four bits and upper four bits of the destination operand are swapped. 7 04 3 Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 F0 R

4 F1 IR

Examples: Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H: SWAP 00H → Register 00H = 0E3H SWAP @02H → Register 02H = 03H, register 03H = 4AH In the first example, if general register 00H contains the value 3EH (00111110B), the statement "SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value 0E3H (11100011B).

INSTRUCTION SET S3C826A/ P826A 6- 84 TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits i n the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Alwa ys cleared to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 R R 6 65 R IR opc dst src 3 6 66 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TCM R0,R1 → R0 = 0C7H, R1 = 02H, Z = "1" TCM R0,@R1 → R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" TCM 00H, 01H → Register 00H = 2BH, register 01H = 02H, Z = "1" TCM 00H,@01H → Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1" TCM 00H,#34 → Register 00H = 2BH, Z = "0" In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation.

S3C826A/P826A INSTR UCTION SET 6- 85 TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 R R 6 75 R IR opc dst src 3 6 76 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TM R0,R1 → R0 = 0 C7H, R1 = 02H, Z = "0" TM R0,@R1 → R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" TM 00H,01H → Register 00H = 2BH, register 01H = 02H, Z = "0" TM 00H,@01H → Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0" TM 00H,#54H → Register 00H = 2BH, Z = "1" In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation.

INSTRUCTION SET S3C826A/ P826A 6- 86 WFI — Wait for Interrupt WFI Operation: The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt . Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4n 3F ( n = 1, 2, 3, … ) Example: The following sample program structure shows the sequence of operations that follow a "WFI" statement: EI WFI (Next instruction) Main program ... ... Interrupt occurs Interrupt service routine ... Clear interrupt flag IRET Service routine completed (Enable global interrupt) (Wait for interrupt)

S3C826A/P826A INSTR UCTION SET 6- 87 XOR — Logical Exclusive OR XOR dst,src Operation: dst ← dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src opc dst | src 2 4 B2 r r

6 B3 r lr

6 B5 R IR

Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: XOR R0,R1 → R0 = 0C5H, R1 = 02H XOR R0,@R1 → R0 = 0E4H, R1 = 02H, register 02H = 23H XOR 00H,01H → Register 00H = 29H, register 01H = 02H XOR 00H,@01H → Register 00H = 08H, register 01H = 02H, register 02H = 23H XOR 00H,#54H → Register 00H = 7FH In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0.

INSTRUCTION SET S3C826A/ P826A 6- 88 NOTES

S3C826A/P826A CLOCK CIRCUIT 7- 1

7 CLOCK CIRCUIT

The S3C826A microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency of S3C826A is determined by CLKCON register settings. SYSTEM CLOCK CIRCUIT The system clock circuit has the following components: — External crystal , ceramic resonator, RC oscillation source, or an external clock source — Oscillator stop and wake-up functions — Programmable frequency divider for the CPU clock ( f xx divided by 1, 2, 8, or 16) — System clock control register, CLKCON — STOP control register, STPCON CPU Clock Notation In this document, the following notation is used for descriptions of the CPU clock; fx: main clock fxt: sub clock fxx: selected system clock

S3C826A/P826A CLOCK CIRCUIT 7- 3 C LOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset operation or an external interrupt (with RC delay noise filter) . — In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers, timer/ counters, and watch timer. Idle mode is released by a reset or by an external or internal interrupt. CPU Clock IDLE Instruction Selector 2CLKCON.4-.3 System Clock 1/8-1/4096 Frequency Dividing Circuit Stop Release Main-System Oscillator Circuit Selector 1 fx fx t Stop Sub-system Oscillator Circuit INT OSCCON.0 OSCCON.3 OSCCON.2 STPCON STOP OSC inst. fXX Stop Basic Timer Timer/Counters Watch Timer 1/1 1/161/2 1/8 LCD Controller SIO A/D Converter Watch Timer LCD Controller Figure 7- 6 . System Clock Circuit Diagram

CLOCK CIRCUIT S3C826A/P826A 7- 4 SYSTEM CLOCK CONTROL REGISTER (CLKCON ) The system clock control register, CLKCON , is located in the set 1, address D4H. It is read/write addressable and has the following functions: — Oscillator frequency divide-by value After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1. System Clock Control Register (CLKCON) D4H, Set 1, R/W Not used (must keep always 0) Not used (must keep always 0) Divide-by selection bits for CPU clock frequency: 00 = f XX /16 01 = f XX /8 10 = f XX /2 11 = f XX /1 (non-divided) Oscillator IRQ wake-up function bit: 0 = Enable IRQ for main wake-up in power down mode 1 = Disable IRQ for main wake-up in power down mode Figure 7- 7 . System Clock Control Register (CLKCON )

S3C826A/P826A CLOCK CIRCUIT 7- 5 OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in set 1, at address D2H. It is read/write addressable and has the following functions: — System clock selection — Main oscillator control — Sub oscillator control OSCCON.0 register settings select Main clock or Sub clock as system clock. After a reset, Main clock is selected for system clock because the reset value of OSCCON.0 is "0". The main oscillator can be stopped or run by setting OSCCON.3. The sub oscillator can be stopped or run by setting OSCCON.2. Oscillator Control Register (OSCCON) D2H, Set 1, R/W Main system oscillator control bit: 0 = Main oscillator RUN 1 = Main oscillator STOP Sub system oscillator control bit: 0 = Sub oscillator RUN 1 = Sub oscillator STOP Not used for S3C826A System clock selection bit: 0 = Main select 1 = Sub select Not used for S3C826A Figure 7-8. Oscillator Control Register (OSCCON)

CLOCK CIRCUIT S3C826A/P826A 7- 6 SWITCHING THE CPU CLOCK Data loading in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies. OSCCON.0 select the main clock ( fx) or the sub clock ( fxt) for the CPU clock. OSCCON .3 start or stop main clock oscillation, and OSCCON.2 start or stop sub clock oscillation. CLKCON.4–.3 control the frequency divider circuit, and divide the selected fxx clock by 1, 2, 8, 16. If fxt is selected for system clock, the CLKCON.4–.3 must be set to “11”. For example, you are using the default CPU clock (normal operating mode and a main clock of fx/16) and you want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set and stops main clock oscillation. The following steps must be taken to switch from a sub clock to the main clock: first, set OSCCON.3 to "0" to enable main clock oscillation. Then, after a certain number of machine cycles has elapsed, select the main clock by setting OSCCON.0 to "0". FF PROGRAMMING TIP — Switching the CPU clock 1. This example shows how to change from the main clock to the sub clock: MA2SUB OR CLKC ON,#18H ; Non-divided clock for system clock LD OSCCON,#01H ; Switches to the sub clock CALL DLY16 ; Delay 16ms OR OSCCON,#08H ; Stop the main clock oscillation RET 2. This example shows how to change from sub clock to main clock: SUB2MA AND OSCCON,#07H ; Start the main clock oscillation CALL DLY16 ; Delay 16 ms AND OSCCON,#06H ; Switch to the main clock RET DLY16 SRP #0C0H LD R0,#20H DEL NOP DJNZ R0,DEL RET

S3C826A/P826A CLOCK CIRCUIT 7- 7 NOTE: Before execute the STOP instruction, set this STPCON register as "10100101B". Otherwise the STOP instruction will not execute as well as reset will be generated. STOP Control Register (STPCON) D1H, Set 1, R/W STOP Control bits: Other values = Disable STOP instruction 10100101 = Enable STOP instructionFigure 7-9. STOP Control Register (STPCON)

CLOCK CIRCUIT S3C826A/P826A 7- 8 NOTES

S3C826A/P826A RESETRESET and POWER-DOWN 8- 1

8 RESETRESET and POWER-DOWN

During a power-on reset, the voltage at V DD goes to High level and the RESET pin is forced to Low level. The RESET signal is input through a s chmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings the S3C826A into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance. The minimum required time of a reset operation for oscillation stabilization is 1 millisecond. Whenever a reset occurs during normal operation (that is, when both V DD and RESET are High level), the RESET pin is forced Low level and the reset operation starts. All system and peripheral control registers are then reset to their default hardware values In summary, the following sequence of events occurs during a reset operation: — All interrupt is disabled. — The watchdog function (basic timer) is enabled. — Ports 0 -15 are set to input mode , and all pull-up resistors are disabled for the I/O port. — Perip heral control and data register settings are disabled and reset to the ir default hardware values . — The program counter (PC) is loaded with the program reset address in the ROM, 0100H. — When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 0100H (and 0101H) is fetched and executed. NORMAL MODE RESET OPERATION In normal (masked ROM) mode, the Test pin is tied to V SS . A reset enables access to the 48-Kbyte on-chip ROM. NOTE To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing " 1010B " to the upper nibble of BTCON.

RESETRESET and POWER-DOWN S3C826A/P826A 8- 2 HARDWARE RESET VALUES Table 8-1 , 8-2, 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: — A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively . — An " x " means that the bit value is undefined after a reset. — A dash ( " – " ) means that the bit is either not used or not mapped , but read 0 is the bit value. Table 8-1. S3C826A Set 1 Register and Values after RESETRESET Register Name Mnemonic Address Bit Values a fter RRESETESET Dec Hex 7 6 5 4 3 2 1 0 Interrupt P ending R egister INTPND 208 D0H – – – – 0 0 0 0 STOP Control Register STPCON 209 D1H 0 0 0 0 0 0 0 0 Oscillator Control Register OSCCON 210 D2H – – – – 0 0 – 0 Basic Timer Control Register BTCON 211 D3H 0 0 0 0 0 0 0 0 Clock Control Register CLKCON 212 D4H 0 – – 0 0 – – – System Flags Register FLAGS 213 D5H x x x x x x 0 0 Register Pointer (High Byte) RP0 214 D6H 1 1 0 0 0 – – – Register Pointer (Low Byte) RP1 215 D7H 1 1 0 0 1 – – – Stack Pointer (High Byte) SPH 216 D8H x x x x x x x x Stack Pointer (Low Byte) SPL 217 D9H x x x x x x x x Instruction Pointer (High Byte) IPH 218 DAH x x x x x x x x Instruction Pointer (Low Byte) IPL 219 DBH x x x x x x x x Interrupt Request Register IRQ 220 DCH 0 0 0 0 0 0 0 0 Interrupt Mask Register IMR 221 DDH x x x x x x x x System Mode Register SYM 222 DEH 0 – – x x x 0 0 Register Page Pointer PP 223 DFH 0 0 0 0 0 0 0 0

S3C826A/P826A RESETRESET and POWER-DOWN 8- 3 Table 8 - 2 . S3C826A Set 1, Bank 0 Register Values after RESETRESET Register Name Mnemonic Address Bit Values a fter RRESETESET Dec Hex 7 6 5 4 3 2 1 0 SIO Control Register SIOCON 224 E0H 0 0 0 0 0 0 0 0 SIO Data Register SIODATA 225 E1H 0 0 0 0 0 0 0 0 SIO Prescaler Register SIOPS 226 E2H 0 0 0 0 0 0 0 0 Timer 0 Counter Register T0CNT 227 E3H 0 0 0 0 0 0 0 0 Timer 0 Data Register T0DATA 228 E4H 1 1 1 1 1 1 1 1 Timer 0 Control Register T0CON 229 E5H 0 0 0 0 0 0 0 0 Timer B Counter Register TBCNT 230 E6H 0 0 0 0 0 0 0 0 Timer A Counter Register TACNT 231 E7H 0 0 0 0 0 0 0 0 Timer B Data Register TBDATA 232 E8H 1 1 1 1 1 1 1 1 Timer A Data Register TADATA 233 E9H 1 1 1 1 1 1 1 1 Timer B Control Register TBCON 234 EAH – – 0 0 0 0 0 0 Timer 1/A Control Register TACON 235 EBH 0 0 0 0 0 0 0 0 Timer 2 Counter Register T2CNT 236 ECH 0 0 0 0 0 0 0 0 Timer 2 Data Register T2DATA 237 EDH 1 1 1 1 1 1 1 1 Timer 2 Control Register T2CON 238 EEH 0 0 0 0 0 0 0 0 A/D Converter Control Register ADCON 239 EFH – – 0 0 0 0 0 0 A/D Converter Data Register ADDATA 240 F0H x x x x x x x x Timer 3 Control Register T3CON 241 F1H 0 0 0 0 0 0 0 0 Timer 3 Counter T3CNT 242 F2H 0 0 0 0 0 0 0 0 Timer 3 Data Register T3DATA 243 F3H 1 1 1 1 1 1 1 1 LCD Control Register LCON 244 F4H 0 0 0 0 0 0 0 0 LCD Mode Register LMOD 245 F5H 0 0 – 0 0 0 0 0 Watch Timer Control Register WTCON 246 F6H 0 0 0 0 0 0 0 0 Port Group 0 Control Register PG0CON 247 F7H 0 0 0 0 0 0 0 0 Port Group 1 Control Register PG1CON 248 F8H 0 0 0 0 0 0 0 0 Port Group 2 Control Register PG2CON 249 F9H 0 0 0 0 0 0 0 0 Port Group 3 Control Register PG3CON 250 FAH 0 0 0 0 0 0 0 0 Port Group 4 Control Register PG4CON 251 FBH 0 0 0 0 0 0 0 0 Location FCH is not mapped. Basic Timer Counter BTCNT 253 FDH 0 0 0 0 0 0 0 0 Location FEH is not mapped. Interrupt Priority Register IPR 255 FFH x x x x x x x x

RESETRESET and POWER-DOWN S3C826A/P826A 8- 4 Table 8 - 3 . S3C826A Set 1, Bank 1 Register Values after RESETRESET Register Name Mnemonic Address Bit Values a fter RRESETESET Dec Hex 7 6 5 4 3 2 1 0 Port 0 Control Register(High Byte) P0CONH 224 E0H 0 0 0 0 0 0 0 0 Port 0 Control Register(Low Byte) P0CONL 225 E1H 0 0 0 0 0 0 0 0 Port 0 Interrupt Edge Selection Register P0EDGE 226 E2H 0 0 0 0 0 0 0 0 Port 0 Interrupt Control Register P0INT 227 E3H 0 0 0 0 0 0 0 0 Port 0 Interrupt Pending Register P0PND 228 E4H 0 0 0 0 0 0 0 0 Port 1 Pull-up Resistors E nable Register P1PUR 229 E5H 0 0 0 0 0 0 0 0 Port 1 Control Register(High Byte) P1CONH 230 E6H 0 0 0 0 0 0 0 0 Port 1 Control Register(Low Byte) P1CONL 231 E7H 0 0 0 0 0 0 0 0 Port 2 Control Register(High Byte) P2CONH 232 E8H 0 0 0 0 0 0 0 0 Port 2 Control Register(Low Byte) P2CONL 233 E9H 0 0 0 0 0 0 0 0 Port 2 Pull-up Resistors E nable Register P2PUR 234 EAH 0 0 0 0 0 0 0 0 Port 3 Pull-up Resistors E nable Register P3PUR 235 EBH 0 0 0 0 0 0 0 0 Port 3 Control Register(High Byte) P3CONH 236 ECH 0 0 0 0 0 0 0 0 Port 3 Control Register(Low Byte) P3CONL 237 EDH 0 0 0 0 0 0 0 0 Port 3 Interrupt Control Register P3INT 238 EEH 0 0 0 0 0 0 0 0 Location EFH is not mapped. Port 0 Data Register P0 240 F0H 0 0 0 0 0 0 0 0 Port 1 Data Register P1 241 F1H 0 0 0 0 0 0 0 0 Port 2 Data Register P2 242 F2H 0 0 0 0 0 0 0 0 Port 3 Data Register P3 243 F3H 0 0 0 0 0 0 0 0 Port 4 Data Register P4 244 F4H 0 0 0 0 0 0 0 0 Port 5 Data Register P5 245 F5H 0 0 0 0 0 0 0 0 Port 6 Data Register P6 246 F6H 0 0 0 0 0 0 0 0 Port 7 Data Register P7 247 F7H 0 0 0 0 0 0 0 0 Port 8 Data Register P8 248 F8H 0 0 0 0 0 0 0 0 Port 9 Data Register P9 249 F9H 0 0 0 0 0 0 0 0 Port 10 Data Register P10 250 FAH 0 0 0 0 0 0 0 0 Port 11 Data Register P11 251 FBH 0 0 0 0 0 0 0 0 Port 12 Data Register P12 252 FCH 0 0 0 0 0 0 0 0 Port 13 Data Register P13 253 FDH 0 0 0 0 0 0 0 0 Port 14 Data Register P14 254 FEH 0 0 0 0 0 0 0 0 Port 15 Data Register P15 255 FFH 0 0 0 0 0 0 0 0

S3C826A/P826A RESETRESET and POWER-DOWN 8- 5 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP ( opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip oscillator for system clock stops and the supply current is reduced to less than 3 µA. All system functions stop when the clock “freezes”, but data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a reset or by external interrupts, for more details see Figure 7-3. NOTE Do not use stop mode if you are using an external clock source because X IN or XT IN input must be restricted internally to V SS to reduce current leakage. Using RESETRESET to Release Stop Mode Stop mode is released when the RESET signal is released and returns to high level: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. A reset operation automatically selects a slow clock fxx/16 because CLKCON.3 and CLKCON.4 are cleared to '00B'. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H. Using an External Interrupt to Release Stop Mode E xternal interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller’s current internal operating mode. The external interrupts in the S3C826A interrupt structure that can be used to release Stop mode are: — E xternal interrupts P0.0–P0.7 (INT0–INT7) and P3.4–P3.7 (INT8–INT11) Please note the following conditions for Stop mode release: — If you release S top mode using an external interrupt, the current values in system and peripheral control registers are unchanged except STPCON register. — If you use an internal or external interrupt for s top mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering s top mode. — When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting remains unchanged and the currently selected clock value is used. — The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated Stop mode is executed. How to Enter into Stop Mode Handling STPCON register then writing Stop instruction (keep the order). LD STPCON, #10100101B STOP NOP NOP NOP

RESETRESET and POWER-DOWN S3C826A/P826A 8- 6 IDLE MODE Idle mode is i nvoked by the instruction IDLE ( opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals remain active. Port pins retain the mode (input or output) they had at the time idle mode was entered. There are two ways to release idle mode : 1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatica lly selects the slow clock fxx/16 because CLKCON.4 and CLKCON.3 are cleared to ‘00B’. If interrupts are masked, a reset is the only way to release idle mode. 2. Activate any enabled interrupt , causing idle mode to be released. When you use an interrupt to release idle mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction immediately following the one that initiated idle mode is executed.

9 I/O PORTS

The S3C826A microcontroller has four bit-programmable, eight nibble-programmable, and four byte- programmable I/O ports , P0–P15. All ports are 8-bit ports. This gives a total of 128 I/O pins . Each port can be flexibly configured to meet a pplication design requirements. The CPU accesses ports by directly wri ting or reading port registers. No special I/O instructions are required. All ports of the S3C826A can be configured to input or output mode and P4–P15 are shared with LCD signals. Table 9-1 gives y ou a general overview of the S3C826A I/O port functions. Table 9-1. S3C826A Port Configuration Overview Port Configuration Options 0 1-bit programmable I/O port . Schmitt trigger input or push-pull, open-drain output mode selected by software; software assignable pull-ups. P0.0–P0.7 can alternately be used as inputs for external interrupts INT0–INT7 (with noise filter and interrupt control). 1 1-bit programmable I/O port . Schmitt trigger input or push-pull, open-drain output mode selected by software; software assignable pull-ups. P1.0–P1.7 can alternately be used as AD0–AD3, SCK, SO, SI, and BUZ. 2 1-bit programmable I/O port . Schmitt trigger input or push-pull, open-drain output mode selected by software; software assignable pull-ups. P2.0–P2.4 can alternately be used as T0CLK, T0OUT, T0PWM, T0CAP, T1CLK, TAOUT, and TBOUT. 3 1-bit programmable I/O port . Schmitt trigger input or push-pull, open-drain output mode selected by software; software assignable pull-ups. Alternately P3.0–P3.3 can be used as T2CLK, T2OUT, T3CLK, and T3OUT/T3PWM/T3CAP. P3.4–P3.7 can alternately be used as inputs for external interrupts INT8– INT11 (with noise filter and interrupt control). 4–11 4-bit programmable I/O port . Input or push-pull, open-drain output mode selected by software; software assignable pull-ups. P4.0–P11.7 can alternately be used as outputs for LCD signals. 12–15 8-bit programmable I/O port . Input or push-pull, open-drain output mode selected by software; software assignable pull-ups. P12.0–P15.7 can alternately be used as outputs for LCD signals.

Table 9-2 gives you an overview of t he register locations of all nine S3C826A I/O port data registers. Data registers for ports 0 –15 have the general format shown in Figure 9-1 . Table 9-2. Port Data Register Summary Register Name Mnemonic Decimal Hex Location R/W Port 0 data register P0 240 F0H Set 1 , Bank 1 R/W Port 1 data register P1 241 F1H Set 1 , Bank 1 R/W Port 2 data register P2 242 F2H Set 1 , Bank 1 R/W Port 3 data register P3 243 F3H Set 1 , Bank 1 R/W Port 4 data register P 4 244 F4H Set 1 , Bank 1 R/W Port 5 data register P 5 245 F5H Set 1 , Bank 1 R/W Port 6 data register P6 246 F6H Set 1 , Bank 1 R/W Port 7 data register P7 247 F7H Set 1 , Bank 1 R/W Port 8 data register P8 248 F8H Set 1 , Bank 1 R/W Port 9 data register P9 249 F9H Set 1 , Bank 1 R/W Port 10 data register P10 250 FAH Set 1 , Bank 1 R/W Port 11 data register P11 251 FBH Set 1 , Bank 1 R/W Port 12 data register P12 252 FCH Set 1 , Bank 1 R/W Port 13 data register P13 253 FDH Set 1 , Bank 1 R/W Port 14 data register P14 254 FEH Set 1 , Bank 1 R/W Port 15 data register P15 255 FFH Set 1 , Bank 1 R/W

Port 0 is an 8-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location F0H in set 1, bank 1. P0.0–P0.7 can serve as inputs (with or without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions. — Low-nibble pins (P0.0–P0.3): INT0–INT3 — High-nibble pins (P0.4–P0.7): INT4–INT7 Port 0 Control Registers (P0CONH, P0CONL) P0CONH and P0CONL registers to "00H", configuring pins to input mode. You use control registers setting to select input or output mode(push-pull or open-drain). Port 0 Interrupt Enable, Pending, and Edge Selection Registers (P0INT, P0PND, P0EDGE) To process external interrupts at the port 0 pins, three additional control registers are provided: the port 0 interrupt enable register P0INT (E3H, set 1, bank 1), the port 0 interrupt pending register P0PND (E4H, set1, bank 1), and the port 0 interrupt edge selection register P0EDGE (E2H, set 1, bank 1). The port 0 interrupt pending register P0PND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the P0PND register at regular intervals. When the interrupt enable bit of any port 0 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding P0PND bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding P0PND bit. Port 0 Control Register, High Byte (P0CONH) E0H, Set 1, Bank 1, R/W P0.7 (INT7) P0.6 (INT6) P0.5 (INT5) P0.4 (INT4) P0CONH bit-pair pin configuration Schmitt trigger input mode Schmitt trigger input mode, pull-up resistor Output mode, open-drain Output mode, push-pull Figure 9-1. Port 0 High-Byte Control Register (P0CONH)

Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the Port 1 data register, P1 at location F1H in set 1, bank 1. P1.0–P1.7 can serve as inputs, as outputs (push pull or open-drain) or you can configure the following alternative functions: — Low-nibble pins (P1.0-P1.3): AD0–AD3 — High-nibble pins (P1.4-P1.7): SCK, SI , SO, BUZ Port 1 Control Registers (P1CONH, P1CONL) P1CONH and P1CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to select input or output mode (push-pull or open drain) and enable the alternative functions. When programming the port, please remember that any alternative peripheral I/O function you configure using the port 1 control registers must also be enabled in the associated peripheral module. Port 1 Pull-up Resistor Control Register (P1PUR) Using the port 1 pull-up resistor control register, P1PUR (E5H, set 1, bank 1), you can configure pull-up resistors to individual port 1 pins. Port 1 Control Register, High Byte E6H, Set 1, Bank 1, R/W P1.7/BUZ P1CONH bit-pair pin configuration settings Alternative function (SCK, SO, BUZ) Output mode, push-pull P1.6/SI P1.5/SO P1.4/SCK Output mode, open-drain Schmitt trigger input mode (SCK, SI) Figure 9- 6. Port 1 High-Byte Control Register (P1CONH)

Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the Port 2 data register, P2 at location F2H in set 1, bank 1. P2.0–P2.7 can serve as inputs, as outputs (push pull or open-drain) or you can configure the following alternative functions: — Low-nibble pins (P2.0-P2.3): T0CLK, T0OUT/T0PWM/T0CAP. T1CLK, TAOUT — High-nibble pins (P2.4-P2.7): TBOUT Port 2 Control Registers (P2CONH, P2CONL) P2CONH and P2CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to select input or output mode (push-pull or open drain) and enable the alternative functions. When programming the port, please remember that any alternative peripheral I/O function you configure using the port 2 control registers must also be enabled in the associated peripheral module. Port 2 Pull-up Resistor Control Register (P2PUR) Using the port 2 pull-up resistor control register, P2PUR (EAH, set 1, bank 1), you can configure pull-up resistors to individual port 2 pins. Port 2 Control Register, High Byte E8H, Set 1, Bank 1, R/W P2.7 P2CONH bit-pair pin configuration settings Alternative function (TBOUT) Output mode, push-pull P2.6 P2.5 P2.4/TBOUT Output mode, open-drain Schmitt trigger input mode Figure 9- 9. Port 2 High-Byte Control Register (P2CONH)

Port 3 is an 8-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location F3H in set 1, bank 1. P3.0–P3.7 can serve as inputs, as outputs (push-pull or open-drain) or it can be configured the following functions. — Low-nibble pins (P3.0–P3.3): T2CLK, T2OUT, T3CLK, T3OUT/T3PWM/T3CAP — High-nibble pins (P3.4–P3.7): INT8–INT11 Port 3 Control Registers (P3CONH, P3CONL) P3CONH and P3CONL registers to "00H", configuring P3.0–P3.7 pins to input mode. You use control registers setting to select input or output mode(push-pull or open-drain) and enable the alternative functions. When programming the port, please remember that any alternative peripheral I/O function you configure using the port 3 control registers must also be enabled in the associated peripheral module. Port 3 Pull-Up Resistor Control Register (P3PUR) Using the port 3 pull-up resistor control register, P3PUR (EBH, set 1, bank 1), you can configure pull-up resistors to individual port 3 pins. Port 3 Interrupt Control Registers (P3INT) To process external interrupts at the port 3 pins, an additional control register is provided: the port 3 interrupt control register P3INT (EEH, set 1, bank 1). The port 3 interrupt control register P3INT lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the P3INT register at regular intervals. When the interrupt enable bit of any port 3 pin is “1”, a falling edge at that pin will generate an interrupt request. The corresponding pending bit is then automatically set to “1” and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a “0” to the corresponding P3INT bit.

PORT 4, 5 Port 4 and 5 are 8-bit I/O ports with nibble configurable pins, respectively. Port 4 and 5 pins are accessed directly by writing or reading the Port 4 and 5 data registers, P4 at location F4H and P5 at location F5H in set 1, bank 1. they can serve as segment pins for LCD, also. Port Group 0 Control Register (PG0CON) clears the PG0CON register to “00H”, configuring all pins to input mode. Output mode, push-pull Port Group 0 Control Register F7H, Set 1, Bank 0, R/W P5.0-P5.3 /SEG71-SEG68 P4.4-P4.7 /SEG75-SEG72 P4.0-P4.3 /SEG79-SEG76 PG0CON bit-pair pin configuration settings Input mode, pull-up P5.4-P5.7 /SEG67-SEG64 Input mode Output mode, open-drain NOTE: The shared I/O ports with LCD segments should be selected as one of two by LMOD.4-.0. Figure 9-16. Port Group 0 Control Register (PG0CON)

PORT 6, 7 Port 6 and 7 are 8-bit I/O ports with nibble configurable pins, respectively. Port 6 and 7 pins are accessed directly by writing or reading the Port 6 and 7 data registers, P6 at location F6H and P7 at location F7H in set 1, bank 1. they can serve as segment pins for LCD, also. Port Group 1 Control Register (PG1CON) clears the PG1CON register to “00H”, configuring all pins to input mode. Output mode, push-pull Port Group 1 Control Register F8H, Set 1, Bank 0, R/W P7.0-P7.3 /SEG55-SEG52 P6.4-P6.7 /SEG59-SEG56 P6.0-P6.3 /SEG63-SEG60 PG1CON bit-pair pin configuration settings Input mode, pull-up P7.4-P7.7 /SEG51-SEG48 Input mode Output mode, open-drain NOTE: The shared I/O ports with LCD segments should be selected as one of two by LMOD.4-.0. Figure 9-17. Port Group 1 Control Register (PG1CON)

PORT 8, 9 Port 8 and 9 are 8-bit I/O ports with nibble configurable pins, respectively. Port 8 and 9 pins are accessed directly by writing or reading the Port 8 and 9 data registers, P8 at location F8H and P9 at location F9H in set 1, bank 1. they can serve as segment pins for LCD, also. Port Group 2 Control Register (PG2CON) clears the PG2CON register to “00H”, configuring all pins to input mode. Output mode, push-pull Port Group 2 Control Register F9H, Set 1, Bank 0, R/W P9.0-P9.3 /SEG39-SEG36 P8.4-P8.7 /SEG43-SEG40 P8.0-P8.3 /SEG47-SEG44 PG2CON bit-pair pin configuration settings Input mode, pull-up P9.4-P9.7 /SEG35-SEG32 Input mode Output mode, open-drain NOTE: The shared I/O ports with LCD segments should be selected as one of two by LMOD.4-.0. Figure 9-18. Port Group 2 Control Register (PG2CON)

PORT 10, 11 Port 10 and 11 are 8-bit I/O ports with nibble configurable pins, respectively. Port 10 and 11 pins are accessed directly by writing or reading the Port 10 and 11 data registers, P10 at location FAH and P11 at location FBH in or push-pull). And they can serve as segment pins for LCD, also. Port Group 3 Control Register (PG3CON) A reset clears the PG3CON register to “00H”, configuring all pins to input mode. Output mode, push-pull Port Group 3 Control Register FAH, Set 1, Bank 0, R/W P11.0-P11.3 /SEG23-SEG20 P10.4-P10.7 /SEG27-SEG24 P10.0-P10.3 /SEG31-SEG28 PG3CON bit-pair pin configuration settings Input mode, pull-up P11.4-P11.7 /SEG19-SEG16 Input mode Output mode, open-drain NOTE: The shared I/O ports with LCD segments should be selected as one of two by LMOD.4-.0. Figure 9-19. Port Group 3 Control Register (PG3CON)

PORT 12, 13, 14, 15 Port 12,13,14 and 15 are 8-bit I/O port with byte configurable pins, respectively. Port 12,13,14 and 15 pins are accessed directly by writing or reading the Port 12,13,14 and 15 data registers, P12 at location FCH, P13 at P14.7, and P15.0–P15.7 can serve as inputs (with or without pull-ups), as output (open drain or push-pull). And they can serve as segment or common pins for LCD also. Port Group 4 Control Register (PG4CON) to “00H”, configuring all pins to input mode. Output mode, push-pull Port Group 4 Control Register FBH, Set 1, Bank 0, R/W P714.0-P14.7 /SEG80-SEG87 /COM15-COM8 P13.0-P13.7 /SEG7-SEG0 P12.0-P12.7 /SEG15-SEG8 PG4CON bit-pair pin configuration settings Input mode, pull-up P15.0-P15.7 /COM7-COM0 Input mode Output mode, open-drain NOTE: Refer to LCD mode control register (LMOD). Figure 9-20. Port Group 4 Control Register (PG4CON)

S3C826A/P826A BASIC TIMER and TIMER 0 10- 1

10 BASIC TIMER and TIMER 0

The S3C826A has two default timers: an 8-bit basic timer and one 8-bit general-purpose timer/counter. The 8 -bit timer/counter is called timer 0. BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabilization interval after a reset or a stop mode release. The functional components of the basic timer block are: — Clock frequency divider ( f xx divided by 4096, 1024, 128, or 16) with multiplexer — 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH, read-only) — Basic timer control register, BTCON (set 1, D3H, read/write)

BASIC TIMER and TIMER 0 S3C826A/P8 26A 10- 2 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1, address D3H, and is read/write addressable using Register addressing mode. A reset clears BTCON to “00H”. This enables the watchdog function and selects a basic timer clock frequency of f xx /4096. To disable the watchdog function, you must write the signature code “1010B” to the basic timer register control bits BTCON.7–BTCON.4. The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers for all timers input clock, you write a "1" to BTCON.0. Basic TImer Control Register (BTCON) D3H, Set 1, R/W Divider clear bit for all timers: 0 = No effect 1= Clear divider Basic timer counter clear bit: 0 = No effect 1= Clear BTCNT Basic timer input clock selection bits: 00 = f XX /4096 01 = f XX /1024 10 = f XX /128 11 = f XX /16 Watchdog timer enable bits: 1010B = Disable watchdog function Other value = Enable watchdog function Figure 10-1. Basic Timer Control Register (BTCON)

S3C826A/P826A BASIC TIMER and TIMER 0 10- 3 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than “1010B”. (The “1010B” value disables the watchdog function.) A reset clears BTCON to “00H”, automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock. A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically. Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. In stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an internal and an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation. In summary, the following events occur when stop mode is released: 1. During stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts. 2. If a power-on reset occurred, the basic timer counter will increase at the rate of fx x /4096. If an internal and an external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock source. 3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows. 4. When a BTCNT.3 overflow occurs, normal CPU operation resumes.

BASIC TIMER and TIMER 0 S3C826A/P8 26A 10- 4 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). MUX fXX /4096 DIV fXX /1024 fXX /128 fXX /16 fXX Bits 3, 2 Bit 0 Basic Timer Control Register (Write '1010xxxxB' to Disable) Clear Bit 1 RESET or STOP Data Bus 8-Bit Up Counter (BTCNT, Read-Only) Start the CPU (note) OVF RESET R Figure 10-2. Basic Timer Block Diagram

S3C826A/P826A BASIC TIMER and TIMER 0 10- 5 8-BIT TIMER/COUNTER 0 Timer/counter 0 has three operating modes, one of which you select using the appropriate T0CON setting: — Interval timer mode — Capture input mode with a risin g or falling edge trigger at the P2.1 pin — PWM mode Timer/counter 0 has the following functional components: — Clock frequency divider ( fxx divided by 1024, 256, 64, 8, or 1) with multiplexer — External clock input (P2.0, T0CLK) — 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA) — I/O pins for capture input, match output, or PWM output (P2.1/T0CAP, P2.1/T0OUT, P2.1/T0PWM) — Timer 0 overflow interrupt (IRQ0, vector E2H) and match/capture interrupt (IRQ0, vector E0H) genera tion — Timer 0 control register, T0CON (set 1, E5H, bank 0, read/write) TIMER/COUNTER 0 CONTROL REGISTER (T0CON) You use the timer 0 control register, T0CON, to — Select the timer 0 operating mode (interval timer, capture mode, or PWM mode) — Select the timer 0 input clock frequency — Clear the timer 0 counter, T0CNT — Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt — Clear timer 0 match/capture interrupt pending condition

BASIC TIMER and TIMER 0 S3C826A/P8 26A 10- 6 T0CON is located in set 1, bank 0, at address E5H, and is read/write addressable using Register addressing mode. A reset clears T0CON to “00H”. This sets timer 0 to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during normal operation by writing a "1" to T0CON.2. The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address E2H. When a timer 0 overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware or must be cleared by software. To enable the timer 0 match/capture interrupt (IRQ0, vector E0H), you must write T0CON.1 to "1". To detect a match/capture interrupt pending condition, the application program polls INTPND.1. When a "1" is detected, a timer 0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 match/capture interrupt pending bit, INTPND.1. Timer 0 Control Register (T0CON) E5H, Set 1, Bank 0, R/W Timer 0 counter clear bit: 0 = No effect 1 = Clear the timer 0 counter (when write) Timer 0 input clock selection bits: 000 = fxx/1024 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = External clock (P2.0/T0CLK) falling edge 110 = External clock (P2.0/T0CLK) rising edge 111 = Counter stop Timer 0 operating mode selection bits: 00 = Interval mode (P2.1/T0OUT) 01 = Capture mode (capture on rising edge, counter running, OVF can occur) 10 = Capture mode (capture on falling edge, counter running, OVF can occur) 11 = PWM mode (OVF and match interrupt can occur) Timer 0 overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrupt Timer 0 match/capture interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Figure 10-3. Timer 0 Control Register (T0CON)

S3C826A/P826A BASIC TIMER and TIMER 0 10- 7 Interrupt Pending Register (INTPND) D0H, Set 1, R/W Not used Timer 0 overflow interrupt pending bit Timer 0 match/capture interrupt pending bit Timer 3 overflow interrupt pending bit Timer 3 match/capture interrupt pending bit 0 = Interrupt request is not pending, pending bit clear when write "0". 1 = Interrupt request is pending Figure 10-4. Interrupt Pending Register (INTPND)

BASIC TIMER and TIMER 0 S3C826A/P8 26A 10- 8 TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts (IRQ0, Vectors E0H and E2H) The timer 0 can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/ capture interrupt (T0INT). T0OVF is belongs to interrupt level IRQ0, vector E2H. T0INT also belongs to interrupt level IRQ0, but is assigned the separate vector address, E0H. A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a “0” to the INTPND.0 interrupt pending bit. However, the timer 0 match/capture interrupt pending condition must be cleared by the application’s interrupt service routine by writing a "0" to the INTPND.1 interrupt pending bit. Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector E0H) and clears the counter. If, for example, you write the value "10H" to T0DATA, the counter will increment until it reaches “10H”. At this point, the timer 0 interrupt request is generated, the counter value is reset, and counting resumes. With each match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-5). Match Signal M U X 8-Bit Up Counter Timer 0 Buffer Register 8-Bit Comparator Timer 0 Data Register T0CON.2 T0CON.4-.3 INTPND.1 Capture Signal T0CON.1 T0INT (IRQ0) T0OUT (P2.1) Pending Interrupt Enable/Disable Match R (Clear) CLK (Match INT) T0OVF Figure 10-5. Simplified Timer 0 Function Diagram: Interval Timer Mode

S3C826A/P826A BASIC TIMER and TIMER 0 10- 9 Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0PWM (P2.1) pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H". Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in PWM-type applications. Instead, the pulse at the T0PWM (P2.1) pin is held to Low level as long as the reference data value is less than or equal to ( ≤ ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to t CLK × 256 (see Figure 10-6). Match Signal M U X 8-Bit Up Counter Timer 0 Buffer Register 8-Bit Comparator Timer 0 Data Register T0CON.2 T0CON.4-.3 INTPND.1 Capture Signal T0CON.1 T0INT (IRQ0) T0PWM Output (P2.1) Pending Interrupt Enable/Disable Match T0OVF(IRQ0) CLK T0OVF High level when data > counter, Lower level when data < counter (Match INT) INTPND.0 T0CON.0 (Overflow INT) Figure 10-6. Simplified Timer 0 Function Diagram: PWM Mode

BASIC TIMER and TIMER 0 S3C826A/P8 26A 10- 10 Capture Mode In capture mode, a signal edge that is detected at the T0CAP (P2.1) pin opens a gate and loads the current counter value into the timer 0 data register. You can select rising or falling edges to trigger this operation. Timer 0 also gives you capture input source: the signal edge at the T0CAP (P2.1) pin. You select the capture input by setting the values of the timer 0 capture input selection bits in the port 2 control register, P2CONL.3–.2, (set 1, bank 1, E9H). When P2CONL.3–.2 is "00", the T0CAP input is selected. Both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated whenever a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter value is loaded into the timer 0 data register. By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (see Figure 10-7). M U X T0CON.4-.3 INTPND.1 T0CON.1 T0INT (IRQ0) Pending Interrupt Enable/Disable Match Signal 8-Bit Up Counter Timer 0 Data Register CLK T0CON.4-.3 T0CAP input (P2.1) (Capture INT) T0OVF(IRQ0) INTPND.0 T0CON.0 (Overflow INT) Figure 10-7. Simplified Timer 0 Function Diagram: Capture Mode

S3C826A/P826A BASIC TIMER and TIMER 0 10- 11 T0OUT T0PWM T0CON.7-.5 M U X T0CON.4-.3 INTPND.1 T0CON.1 T0INT M U X T0CON.4-.3 T0CAP Timer 0 Buffer Register 8-Bit Comparator Timer 0 Data Register 8-Bit Up Counter (Read-Only) R Data BUS 8 T0CON.2 INTPND.0 T0CON.0 T0OVF Data BUS (IRQ0)OVF Match MUX fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 Clear (IRQ0) T0CLK Match signal T0CON.2 T0OVF Figure 10-8. Timer 0 Block Diagram

BASIC TIMER and TIMER 0 S3C826A/P8 26A 10- 12 NOTES

11 TIMER 1

ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. When TACON.7 is set to "1", it is in one 16-bit timer mode. When TACON.7 is set to "0", the timer 1 is used as two 8-bit timers. — One 16-bi t timer mode (Timer 1) — Two 8-bit timers mode (Timer A and B) OVERVIEW The 16-bit timer 1 is an 16-bit general-purpose timer. Timer 1 includes interval timer mode using appropriate TACON setting. Timer 1 has the following functional components: — Clock frequency divider ( fxx divided by 256, 64, 8, or 1 and T1CLK: External clock) with multiplexer — 16-bit counter (TACNT, TBCNT), 16-bit comparator, and 16-bit reference data register (TADATA, TBDATA) — Timer 1 match interrupt (IRQ1, vector E6H) generation — Timer 1 control register, TACON (set 1, bank 0,EBH, read/write) FUNCTION DESCRIPTION Interval Timer Function The timer 1 module can generate an interrupt, the timer 1 match interrupt (T1INT). T1INT belongs to the interrupt level IRQ1, and is assigned a separate vector address, E6H. The T1INT pending condition should be cleared by software after IRQ1 is serviced. The T1INT pending bit must be cleared by the application sub-routine by writing a "0" to the TACON.0 pending bit. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the T1 reference data registers, TADATA and TBDATA. The match signal generates a timer 1 match interrupt (T1INT, vector E6H) and clears the counter. If, for example, you write the value 10H and 32H to TADATA and TBDATA, respectively, and 8EH to TACON, the counter will increment until it reaches 3210H. At this point, the T1 interrupt request is generated, the counter value is reset, and counting resumes.

Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to — Enable the timer 1 operating (interval timer) — Select the timer 1 input clock frequency — Clear the timer 1 counter, TACNT and TBCNT — Enable the timer 1 interrupt — Clear timer 1 interrupt pending conditions TACON is located in set 1, bank 0, at address EBH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency of fxx/256, and disables timer 1 interrupt. You can clear the timer 1 counter at any time during the normal operation by writing a "1" to TACON.3. To enable the timer 1 interrupt (IRQ1, vector E6H), you must write TACON.7, TACON.2, and TACON.1 to "1". To generate the exact time interval, you should set TACON.3 and TACON.0 to “10B”, which clear counter and interrupt pending bit. When the T1INT sub-routine is serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit, TACON.0. Timer 1 Control Register (TACON) EBH, Set 1, Bank 0, R/W Timer 1 interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer 1 interrupt pending bit: 0 = No interrupt pending 0 = Clear pending bit (when write) 1 = Interrupt is pending (when read) 1 = No effect (when write) Timer 1 counter run enable bit: 0 = Disable counter running 1 = Enable counter running Timer 1 counter clear bit: 0 = No affect 1 = Clear the timer 1 counter (when write) Timer 1 operation mode selection bit: 0 = Two 8-bit timers mode (Timer A/B) 1 = One 16-bit timer mode (Timer 1) Timer 1 clock selection bits: 000 = fxx/256 001 = fxx/64 010 = fxx/8 011 = fxx 111 = T1CLK (external clock rising edge) Figure 11-1. Timer 1 Control Register (TACON)

Bit 6, 5, 4 Bit 2 16-Bit Up-Counter (Read Only) <TBCNT/TACNT> Data Bus Bit 3 16-Bit Comparator Timer 1 Buffer Register (16-bit) Timer 1 Data Register (Read/Write) <TBDATA/TADATA> Counter Clear Signal Match Signal Bit 0 Bit 1 Pending T1INT IRQ1 TAOUT MSB LSB Clear Match MSB LSB NOTE: When TACON.7 is "1", 16-bit timer 1. Figure 11-2. Timer 1 Functional Block Diagram

TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B support interval timer mode using appropriate TACON and TBCON setting, respectively. Timer A and B have the following functional components: — Clock frequency divider with multiplexer – fxx divided by 256, 64, 8, or 1 and T1CLK (External clock) for timer A – fxx divided by 256, 64, 8, or 1 for timer B — 8-bit counter (TACNT, TBCNT), 8-bit comparator, and 8-bit reference data register (TADATA, TBDATA) — Timer A match interrupt (IRQ1, vector E6H) generation — Timer A control register, TACON (set 1, bank 0, EBH, read/write) — Timer B match interrupt (IRQ1, vector E4H) generation — Timer B control register, TBCON (set 1, bank 0, EAH, read/write) FUNCTION DESCRIPTION Interval Timer Function The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match interrupt (TBINT). TAINT belongs to the interrupt level IRQ1, and is assigned a separate vector address, E6H. TBINT belongs to the interrupt level IRQ1 and is assigned a separate vector address, E4H. The TAINT and TBINT pending condition should be cleared by software after they are serviced. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the TA or TB reference data registers, TADATA or TBDATA. The match signal generates corresponding match interrupt (TAINT, vector E6H; TBINT, vector E4H) and clears the counter. If, for example, you write the value 10H to TBDATA, "0" to TACON.7, and 0EH to TBCON, the counter will increment until it reaches 10H. At this point, the TB interrupt request is generated, the counter value is reset, and counting resumes. Timer A and B Control Register (TACON, TBCON) You use the timer A and B control register, TACON and TBCON, to — Enable th e timer A and B operating (interval timer) — Select the timer A and B input clock frequency — Clear the timer A and B counter, TACNT and TBCNT — Enable the timer A and B interrupt — Clear timer A and B interrupt pending conditions

TACON and TBCON are located in set 1, bank 0, at address EBH and EAH, and is read/write addressable using register addressing mode. A reset clears TACON and TBCON to "00H". This sets timer A and B to disable interval timer mode, selects an input clock frequency of fxx/256, and disables timer A and B interrupt. You can clear the timer A and B counter at any time during normal operation by writing a "1" to TACON.3 and TBCON.3. To enable the timer A and B interrupt (IRQ1, vector E6H, E4H), you must write TACON.7 to "0", TACON.2 (TBCON.3) and TACON.0 (TBCON.0) to “10B”, which clear counter and interrupt pending bit, respectively. When the TAINT or TBINT sub-routine is serviced, the pending condition must be cleared by software by writing a "0" to the timer A or B interrupt pending bits, TACON.0 or TBCON.0. Timer A Control Register (TACON) EBH, Set 1, Bank 0, R/W Timer A interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer A interrupt pending bit: 0 = No interrupt pending 0 = Clear pending bit (when write) 1 = Interrupt is pending (when read) 1 = No effect (when write) Timer A counter run enable bit: 0 = Disable counter running 1 = Enable counter running Timer A counter clear bit: 0 = No affect 1 = Clear the timer A counter (when write) Timer 1 operation mode selection bit: 0 = Two 8-bit timers mode (Timer A/B) 1 = One 16-bit timer mode (Timer 1) Timer A clock selection bits: 000 = fxx/256 001 = fxx/64 010 = fxx/8 011 = fxx 111 = T1CLK (external clock rising edge) Figure 11-3. Timer A Control Register (TACON)

Timer B Control Register (TBCON) EAH, Set 1, Bank 0, R/W Timer B interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer B interrupt pending bit: 0 = No interrupt pending 0 = Clear pending bit (when write) 1 = Interrupt is pending (when read) 1 = No effect (when write) Timer B counter run enable bit: 0 = Disable counter running 1 = Enable counter running Timer B counter clear bit: 0 = No affect 1 = Clear the timer B counter (when write) Not used the S3C826A. Timer B clock selection bits: 00 = fxx/256 01 = fxx/64 10 = fxx/8 11 = fxx Figure 11-4. Timer B Control Register (TBCON)

TACON.6-.4 MUX fxx/256 fxx/64 fxx/8 fxx T1CLK TACON.2 Comparator TA Buffer Register TADATA TBDATA TB Buffer Register TACNT R Comparator TBCNT R TA Counter Clear Signal, TA Match Signal TB Counter Clear Signal, TB Match Signal Clear TACON.3 Match IRQ1 TACON.0 Pending TACON.1 TBCON.1 PendingTBCON.0 TBOUT TBCON.3 Match Clear MUX fxx/256 fxx/64 fxx/8 fxx TBCON.2 TBCON.5-.4 NOTE: When TACON.7 is "0", two 8-bit timer A/B. TAOUT Figure 11-5. Timer A and B Function Block Diagram

S3C826A/P826A 8-BIT TIMER 2 12- 1 12 8-BIT TIMER 2 OVERVIEW The 8-bit timer 2 is an 8-bit general-purpose timer. Timer 2 has the interval timer mode by using the appropriate T2CON setting. Timer 2 has the following functional components: — Clock frequency divider ( fxx divided by 256, 64, 8 or 1) with multiplexer — External clock input (P3.0/T2CLK) — 8-bit counter (T2CNT), 8-bit comparator, and 8-bit reference data register (T2DATA) — Timer 2 interrupt (IRQ2, vector E8H) generation — Timer 2 control register, T2CON (set 1, Bank 0, EEH, read/write) FUNCTION DESCRIPTION Interval Timer Function The timer 2 can generate an interrupt, the timer 2 match interrupt (T2INT). T2INT belongs to interrupt level IRQ2, and is assigned the separate vector address, E8H. The T2INT pending condition should be cleared by software when it has been serviced. Even though T2INT is disabled, the application’s service routine can detect a pending condition of T2INT by the software and execute it’s sub-routine. When this case is used, the T2INT pending bit must be cleared by the application subroutine by writing a “0” to the T2CON.0 pending bit. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the Timer 2 reference data registers, T2DATA. The match signal generates a timer 2 match interrupt (T2INT, vector E8H) and clears the counter. If, for example, you write the value 10H to T2DATA and 0EH to T2CON, the counter will increment until it reaches 10H. At this point, the Timer 2 interrupt request is generated, the counter value is reset, and counting resumes.

8-BIT TIMER 2 S3C826A/P82 6A 12- 2 TIMER 2 CONTROL REGISTER (T2CON) You use the timer 2 control register, T2CON, to — Enable the timer 2 operating (interval timer) — Select the timer 2 input clock frequency — Clear the timer 2 counter, T2CNT — Enable the timer 2 interrupt and clear timer 2 interrupt pending condition T2CON is located in set 1, bank 0, at address EEH, and is read/write addressable using register addressing mode. A reset clears T2CON to "00H". This sets timer 2 to disable interval timer mode, and disables timer 2 interrupt. You can clear the timer 2 counter at any time during normal operation by writing a “1” to T2CON.3 To enable the timer 2 interrupt (IRQ2, vector E8H), you must write T2CON.2, and T2CON.1 to "1". To detect an interrupt pending condition when T2INT is disabled, the application program polls pending bit, T2CON.0. When a "1" is detected, a timer 2 interrupt is pending. When the T2INT sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 2 interrupt pending bit, T2CON.0. Timer 2 Control Register EEH, Set 1, Bank 0, R/W Timer 2 interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer 2 interrupt pending bit: 0 = No interrupt pending 0 = Clear pending bit (when write) 1 = Interrupt is pending Timer 2 count enable bit: 0 = Disable counting operation 1 = Enable counting operation Timer 2 counter clear bit: 0 = No affect 1 = Clear the timer 2 counter (when write) Timer 2 input clock selection bits: 000 = fxx/256 001 = fxx/64 010 = fxx/8 011 = fxx 111= External clock (T2CLK) input Not used Figure 12-1. Timer 2 Control Register (T2CON)

S3C826A/P826A 8-BIT TIMER 2 12- 3 BLOCK DIAGRAM Timer 2 Data Register (Read/Write) Timer 2 Buffer Register 8-bit Comparator 8-bit up-Counter (Read Only) Match Bit 3 T2INT Counter clear signal (T2CON.3), Match signal Bits 7, 6, 5 M U X fxx/256 fxx/64 fxx/8 fxx/1 T2CLK (P3.0) Bit 2 Clear Bit 0 Bit 1 IRQ2 Pending R Data Bus Data Bus Figure 12-2. Timer 2 Functional Block Diagram

8-BIT TIMER 2 S3C826A/P82 6A 12- 4 NOTES

S3C826A/P826A 8-BIT TIMER 3 13- 1 13 8-BIT TIMER 3 OVERVIEW Timer/counter 3 has three operating modes, one of which you select using the appropriate T3CON setting: — Interval timer mode — Capture input mode with a rising or falling edge trigger at the P3.3 pin — PWM mode Timer/counter 3 has the following functional components: — Clock frequency divider ( fxx divided by 1024, 256, 64, 8, or 1) with multiplexer — External clock input (P3.2, T3CLK) — 8-bit counter(T3CNT), 8-bit comparator, and 8-bit reference data register(T3DATA) — I/O pins for capture input, match output, or PWM output (P3.3/T3CAP, P3.3/T3OUT, P3.3/T3PWM) — Timer 3 overflow interrupt (IRQ2, vector ECH) and match/capture interrupt (IRQ2, vector EAH) generation — Timer 3 control register, T3CON (set 1, F1H, bank 0, read/write) TIMER/COUNTER 3 CONTROL REGISTER (T3CON) You use the timer 3 control register, T3CON, to — Select the timer 3 operating mode (interval timer, capture mode, or PWM mode) — Select the timer 3 input clock frequency — Clear the timer 3 counter, T3CNT — Enable the timer 3 overflow interrupt or timer 3 match/capture interrupt — Clear timer 3 match/capture interrupt pending condition

8-BIT TIMER 3 S3C82 6A/P826A 13- 2 T3CON is located in set 1, bank 0, at address F1H, and is read/write addressable using Register addressing mode. A reset clears T3CON to “00H”. This sets timer 3 to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer 3 interrupts. You can clear the timer 3 counter at any time during normal operation by writing a "1" to T3CON.2. The timer 3 overflow interrupt (T3OVF) is interrupt level IRQ2 and has the vector address ECH. When a timer 3 overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware or must be cleared by software. To enable the timer 3 match/capture interrupt (IRQ2, vector EAH), you must write T3CON.1 to "1". To detect a match/capture interrupt pending condition, the application program polls INTPND.3. When a "1" is detected, a timer 3 match or capture interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 3 match/capture interrupt pending bit, INTPND.3. Timer 3 Control Register (T3CON) F1H, Set 1, Bank 0, R/W Timer 3 counter clear bit: 0 = No effect 1 = Clear the timer 3 counter (when write) Timer 3 input clock selection bits: 000 = fxx/1024 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = External clock (P3.2/T3CLK) falling edge 110 = External clock (P3.2/T3CLK) rising edge 111 = Counter stop Timer 3 operating mode selection bits: 00 = Interval mode 01 = Capture mode (capture on rising edge, counter running, OVF can occur) 10 = Capture mode (capture on falling edge, counter running, OVF can occur) 11 = PWM mode (OVF and match interrupt can occur) Timer 3 overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrupt Timer 3 match/capture interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Figure 13-1. Timer 3 Control Register (T3CON)

S3C826A/P826A 8-BIT TIMER 3 13- 3 Interrupt Pending Register (INTPND) D0H, Set 1, R/W Not used Timer 0 overflow interrupt pending bit Timer 0 match/capture interrupt pending bit Timer 3 overflow interrupt pending bit Timer 3 match/capture interrupt pending bit 0 = Interrupt request is not pending, pending bit clear when write "0". 1 = Interrupt request is pending Figure 13-2. Interrupt Pending Register (INTPND)

8-BIT TIMER 3 S3C82 6A/P826A 13- 4 TIMER 3 FUNCTION DESCRIPTION Timer 3 Interrupts (IRQ2, Vectors EAH and ECH) The timer 3 can generate two interrupts: the timer 3 overflow interrupt (T3OVF), and the timer 3 match/ capture interrupt (T3INT). T3OVF is belongs to interrupt level IRQ2, vector ECH. T3INT also belongs to interrupt level IRQ2, but is assigned the separate vector address, EAH. A timer 3 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a “0” to the INTPND.2 interrupt pending bit. However, the timer 3 match/capture interrupt pending condition must be cleared by the application’s interrupt service routine by writing a "0" to the INTPND.3 interrupt pending bit. Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 3 reference data register, T3DATA. The match signal generates a timer 3 match interrupt (T3INT, vector EAH) and clears the counter. If, for example, you write the value "10H" to T3DATA, the counter will increment until it reaches “10H”. At this point, the timer 3 interrupt request is generated, the counter value is reset, and counting resumes. With each match, the level of the signal at the timer 3 output pin is inverted (see Figure 13-3). Match Signal M U X 8-Bit Up Counter Timer 3 Buffer Register 8-Bit Comparator Timer 3 Data Register T3CON.2 T3CON.4-.3 INTPND.3 Capture Signal T3CON.1 T3INT (IRQ2) T3OUT (P3.3) Pending Interrupt Enable/Disable Match R (Clear) CLK (Match INT) T3OVF Figure 13-3. Simplified Timer 3 Function Diagram: Interval Timer Mode

S3C826A/P826A 8-BIT TIMER 3 13- 5 Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T3PWM (P3.3) pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 3 data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H". Although you can use the match signal to generate a timer 3 overflow interrupt, interrupts are not typically used in PWM-type applications. Instead, the pulse at the T3PWM (P3.3) pin is held to Low level as long as the reference data value is less than or equal to ( ≤ ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to t CLK × 256 (see Figure 13-4). Match Signal M U X 8-Bit Up Counter Timer 3 Buffer Register 8-Bit Comparator Timer 3 Data Register T3CON.2 T3CON.4-.3 INTPND.3 Capture Signal T3CON.1 T3INT (IRQ2) T3PWM Output (P3.3) Pending Interrupt Enable/Disable Match T3OVF(IRQ2) CLK T3OVF High level when data > counter, Lower level when data < counter (Match INT) INTPND.2 T3CON.0 (Overflow INT) Figure 13-4. Simplified Timer 3 Function Diagram: PWM Mode

8-BIT TIMER 3 S3C82 6A/P826A 13- 6 Capture Mode In capture mode, a signal edge that is detected at the T3CAP (P3.3) pin opens a gate and loads the current counter value into the timer 3 data register. You can select rising or falling edges to trigger this operation. Timer 3 also gives you capture input source: the signal edge at the T3CAP (P3.3) pin. You select the capture input by setting the values of the timer 3 capture input selection bits in the port 3 control register, P3CONL.7–.6, (set 1, bank 1, EDH). When P3CONL.7–.6 is "00", the T3CAP input is selected. Both kinds of timer 3 interrupts can be used in capture mode: the timer 3 overflow interrupt is generated whenever a counter overflow occurs; the timer 3 match/capture interrupt is generated whenever the counter value is loaded into the timer 3 data register. By reading the captured data value in T3DATA, and assuming a specific value for the timer 3 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T3CAP pin (see Figure 13-5). M U X T3CON.4-.3 INTPND.3 T3CON.1 T3INT (IRQ2) Pending Interrupt Enable/Disable Match Signal 8-Bit Up Counter Timer 3 Data Register CLK T3CON.4-.3 T3CAP input (P3.3) (Capture INT) T3OVF(IRQ2) INTPND.2 T3CON.0 (Overflow INT) Figure 13-5. Simplified Timer 3 Function Diagram: Capture Mode

S3C826A/P826A 8-BIT TIMER 3 13- 7 T3OUT T3PWM T3CON.7-.5 M U X T3CON.4-.3 INTPND.3 T3CON.1 T3INT M U X T3CON.4-.3 T3CAP Timer 3 Buffer Register 8-Bit Comparator Timer 3 Data Register 8-Bit Up Counter (Read-Only) R Data BUS 8 T3CON.2 INTPND.2 T3CON.0 T3OVF Data BUS (IRQ2)OVF Match MUX fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 Clear (IRQ2) T3CLK Match signal T3CON.2 T3OVF Figure 13-6. Timer 3 Block Diagram

8-BIT TIMER 3 S3C82 6A/P826A 13- 8 NOTES

14 WATCH TIMER

Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt (IRQ4, vector D2H), then set the WTCON.6 to “1”. The watch timer overflow interrupt pending condition (WTCON.0) must be cleared by software in the application’s interrupt service routine by means of writing a "0" to the WTCON.0 interrupt pending bit. After the watch timer starts and elapses a time, the watch timer interrupt pending bit (WTCON.0) is automatically set to "1", and interrupt requests commence in 3.91 ms, 0.25, 0.5 and 1-second intervals by setting Watch timer speed selection bits (WTCON.3 – .2). The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to BUZ output pin for Buzzer. By setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences. The watch timer supplies the clock frequency for the LCD controller (f LCD ). Therefore, if the watch timer is disabled, the LCD controller does not operate. Watch timer has the following functional components: — Real Time and Watch-Time Measurement — Using a Main Clock Source or Sub clock — Clock Source Generation for LCD Controller (f LCD ) — I/O pin for Buzzer Output Frequency Generator (P1.7, BUZ) — Timing Tests in High-Speed Mode — Watch timer overflow interrupt (IRQ4, vector D2H) generation — Watch timer control register, WTCON (set 1, bank 0, F6H, read/write)

WATCH TIMER S3C826 A/P826A 14- 2 WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in set 1, bank 0 at address F6H, and is read/write addressable using register addressing mode. A reset clears WTCON to "00H". This disable the watch timer. So, if you want to use the watch timer, you must write appropriate value to WTCON. Buzzer signal selection bits: 00 = 0.5 kHz 01 = 1 kHz 10 = 2 kHz 11 = 4 kHz Watch Timer Control Register (WTCON) F6H, Set 1, Bank 0, R/W Watch timer INT Enable/Disable bit: 0 = Disable watch timer INT 1 = Enable watch timer INT Watch timer interrupt pending bit: 0 = Interrupt request is not pending (Clear pending bit when write"0") 1 = Interrupt request is pending Watch timer speed selection bits: 00 = Set watch timer interrupt to 1 s 01 = Set watch timer interrupt to 0.5 s 10 = Set watch timer interrupt to 0.25 s 11 = Set watch timer interrupt to 3.91 ms Watch timer Enable/Disable bit: 0 = Disable watch timer 1 = Enable watch timer Watch timer clock selection bit: 0 = Select main clock divided by 2 7 (fx/128) 1 = Select Sub clock (fxt) Figure 14-1. Watch Timer Control Register (WTCON)

WATCH TIMER CIRCUIT DIAGRAM WT INT Enable WTCON.1 WTCON.2 WTCON.3 WTCON.4 WTCON.5 WTCON.6 Enable/Disable Selector Circuit MUX WTCON.0 WTINT WTCON.6 fW /2 15 fW /2 14 fW /2 13 fW /2 7 fW /64 (0.5 kHz) fW /32 (1 kHz) fW /16 (2 kHz) fW /8 (4 kHz) (1 Hz) fX = Main clock (where fx = 4.19 MHz) fxt = Sub clock (32.768 kHz) fW = Watch timer frequency Clock Selector Frequency Dividing Circuit fW 32.768 kHz fxt fX /128 fLCD = 4096 Hz WTCON.7 WTCON.0(Pending Bit) BUZ (P1.7) Figure 14-2. Watch Timer Circuit Diagram

WATCH TIMER S3C826 A/P826A 14- 4 NOTES

S3C826A/P826A LCD C ONTROLLER/DRIVER 15- 1

15 LCD CONTROLLER/DRIV ER

The S3C826A microcontroller can directly drive an up-to-1280-dot (80 segments x 16 commons) LCD panel. Its LCD block has the following components: — LCD controller/dri ver — Display RAM for storing display data — 80 segment output pins (SEG0–SEG79) — 16 common output pins (COM0–COM15) — Five LCD operating power supply pins (V LC1 –V LC5 ) — Internal resistors circuit for LCD bias — LCD contrast control circuit by software (16 steps) To use the LCD controller/driver, the watch timer must be enabled by setting WMOD.1 to "1" because fLCD for LCD controller/driver clock source is supplied by the watch timer. When a sub clock is selected as the watch timer clock source and watch timer is enabled, the LCD display can be enabled even during main clock stop and idle modes. The LCD duty, LCD contrast level, and LCD display on or off, are determined by bit settings in the LCD control register, LCON, at address F4H of bank 0 in set 1. The LCD clock source speed and selecting LCD signal or normal I/O are determined by the LCD mode control register, LMOD, at address F5H of bank 0 in set 1. Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control. LCD Controller/ Driver8 8-Bit Data Bus 5 V LC1- V LC5 COM0-COM7/P15.7-P15.0 COM8-COM15/P14.7-P14.0/SEG87-SEG80 SEG0-SEG79/P13.7-P4.0 Figure 15-1. LCD Function Diagram

LCD CONTROLLER/DRIVER S3C826A/P826A 15- 2 LCD CIRCUIT DIAGRAM SEG79/P4.0 SEG78/P4.1 SEG1/P13.6 SEG0/P13.7 Selector fLCD LMOD LCON Port Latch Display RAM (Page 7) 1408 MUX COM Control or Selector COM15/SEG80/P14.0 COM14/SEG81/P14.1 COM8/SEG87/P14.7 Timing Controller COM Control or Selector COM7/P15.0 COM6/P15.1 COM0/P15.7 LCD Voltage Control V LC5 V LC1 LCD Contrast Controller Data Bus Figure 15-2. LCD Circuit Diagram

S3C826A/P826A LCD C ONTROLLER/DRIVER 15- 3 LCD RAM ADDRESS AREA Ram addresses of page 7 is used as LCD data memory. These locations can be addressed by 1-bit or 8-bit instructions. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0-SEG87 using a direct memory access (DMA) method that is synchronized with the f LCD signal. RAM addresses in this location that are not used for LCD display can be allocated to general-purpose use. S E G S E G COM0 COM1 COM2 COM3 COM13 COM12 COM11 COM10 COM15 COM14 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G COM7 COM6 COM5 COM4 COM9 COM8 710H 712H 711H 713H 700H 702H 704H 706H 708H 70AH 70CH 70EH 701H 703H 705H 707H 709H 70BH 70DH 70FH 7A2H 7A4H 7A6H 7A8H 7AAH 7ACH 7AEH 7A3H 7A5H 7A7H 7A9H 7ABH 7ADH 7AFH Figure 15-3. LCD Display Data RAM Organization

LCD CONTROLLER/DRIVER S3C826A/P826A 15- 4 LCD CONTROL REGISTER (LCON) The LCD control register for the LCD controller/driver is called LCON, F4H of bank 0 in set 1, and is read/write addressable using register addressing mode. It has the following control functions: — LCD duty selection — LCD display control — LCD contrast control and contrast level control The LCD control register, LCON is used to turn the LCD display on/off, to select duty, and to select LCD contrast level. Following a RESET, all LCON values are cleared to "0". This turns off the LCD display, select 1/8 duty, and disable LCD contrast control. LCD Control Register (LCON) F4H, Set 1, Bank 0, R/W LCD bias resistor on/off bit: 0 = Turn off LCD bias resistors 1 = Turn on LCD bias resistors LCD duty selection bits: 00 = 1/8 duty (COM0-COM7) 01 = 1/12 duty (COM0-COM11) 10 = 1/16 duty (COM0-COM15) LCD Contrast level control bits: 0000 = 1/16 step (The dimmest level) 0001 = 2/16 step 0010 = 3/16 step 1111 = 16/16 step (The brightest level) (V LCD = V DD x (n+17)/32, where n = 0-15) LCD contrast enable/disable bit: 0 = Diable LCD contrast control 1 = Enable LCD contrast control Figure 15-4. LCD Control Register (LCON)

S3C826A/P826A LCD C ONTROLLER/DRIVER 15- 5 LCD MODE CONTROL REGISTER (LMOD) The LCD mode control register, LMOD, is located at address F5H of bank 0 in set 1 and is read/write addressable using register addressing mode. The LMOD is used to select LCD clock speed and to select LCD signal pins or normal I/O pins. Following a RESET, all LMOD values are cleared to "0". This select 256Hz LCD clock for 1/8 duty or 512Hz LCD clock for the other duty and select all LCD signal pins (SEG0–SEG79, SEG80– SEG87/COM15–COM8). The LCD clock signal determines the frequency of COM signal scanning of each segment output. This is also referred as the frame frequency. Since the LCD clock signal is generated by the watch timer clock ( fw), the watch timer must be enabled when the LCD display is turned on. LCD Mode Control Register (LMOD) F5H, Set 1, Bank 0, R/W LCD clock frequency selection bits: 00 = fw/2 7 (256Hz) when 1/8 duty, fw/2 6 (512Hz) when 1/12, 1/16 duty 01 = fw/2 6 (512Hz) when 1/8 duty, fw/2 5 (1024Hz) when 1/12, 1/16 duty 10 = fw/2 5 (1024Hz) when 1/8 duty, fw/2 4 (2048Hz) when 1/12, 1/16 duty 11 = fw/2 4 (2048Hz) when 1/8 duty, fw/2 3 (4096Hz) when 1/12, 1/16 duty Not used LMOD.4-.0 SEG79-76 P4.0-P4.3 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH 10H 11H 12H 13H 14H L P P P P P P P P P P P P P P P P P P P P SEG75-72 P4.4-P4.7 L L P P P P P P P P P P P P P P P P P P P SEG71-68 P5.0-P5.3 L L L P P P P P P P P P P P P P P P P P P SEG67-64 P5.4-P5.7 L L L L P P P P P P P P P P P P P P P P P SEG63-60 P6.0-P6.3 L L L L L P P P P P P P P P P P P P P P P SEG59-56 P6.4-P6.7 L L L L L L P P P P P P P P P P P P P P P SEG55-52 P7.0-P7.3 L L L L L L L P P P P P P P P P P P P P P SEG51-48 P7.4-P7.7 L L L L L L L L P P P P P P P P P P P P P SEG47-44 P8.0-P8.3 L L L L L L L L L P P P P P P P P P P P P SEG43-40 P8.4-P8.7 L L L L L L L L L L P P P P P P P P P P P SEG39-36 P9.0-P9.3 L L L L L L L L L L L P P P P P P P P P P SEG35-32 P9.4-P9.7 L L L L L L L L L L L L P P P P P P P P P SEG31-28 P10.0-P10.3 L L L L L L L L L L L L L P P P P P P P P SEG27-24 P10.4-P10.7 L L L L L L L L L L L L L L P P P P P P P SEG23-20 P11.0-P11.3 L L L L L L L L L L L L L L L P P P P P P SEG19-16 P11.4-P11.7 L L L L L L L L L L L L L L L L P P P P P SEG15-8 P12.0-P12.7 L L L L L L L L L L L L L L L L L P P P P SEG7-0 P13.0-P13.7 L L L L L L L L L L L L L L L L L L P P P COM15-8/ SEG80-87 COM7-0 P15.0-P15.7 L L L L L L L L L L L L L L L L L L L L P P14.0-P14.7 L L L L L L L L L L L L L L L L L L L P P NOTE : "P" means port, "L" means LCD output. Figure 15-5. LCD Mode Control Register (LMOD)

LCD CONTROLLER/DRIVER S3C826A/P826A 15- 6 COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle. — In 1/8 duty mode, COM0 –COM7 pins are selected. — In 1/12 duty mode, COM0–COM11 pins are selected. — In 1/16 duty mode, COM0–COM15 pins are selected. When 1/8 duty is selected by setting LCON.2–.1 to "00", COM8–COM15 (P14.7–P14.0/SEG87–SEG80) can be used for LCD segment signal or I/O ports, and when 1/12 duty is selected by setting LCON.2–.1 to "01", COM12– COM15 (P14.3–P14.0/SEG83–SEG80) can be used for LCD segment signals or I/O ports. SEGMENT (SEG) SIGNALS The 88 LCD segment signal pins are connected to corresponding display RAM locations at page 7. Bits of the display RAM are synchronized with the common signal output pins. When the bit value of a display RAM location is "1", a 'select' signal (Display ON) is sent to the corresponding segment pin. When the display bit is "0", a 'non-select' signal (Display Off) is sent to the corresponding segment pin.

LCD CONTROLLER/DRIVER S3C826A/P826A 15- 8

1 Frame

S E G S E G S E G S E G S E G V SS V LC1 V LC2 V LC3 V LC4 V LC5 V SS V LC1 V LC2 V LC3 V LC4 V LC5 V SS V LC1 V LC2 V LC3 V LC4 V LC5 V SS V LC1 V LC2 V LC3 V LC4 V LC5 Figure 15-8. LCD Signal Waveforms (1/16 Duty, 1/5 Bias)

S3C826A/P826A LCD C ONTROLLER/DRIVER 15- 9

15 V LC1

-V LC4 -V LC3 -V LC1 V LC5 -V LC2 -V LC5 V SS V LC1 V LC2 V LC3 V LC4 V LC5 V LC1 V LC2 V LC3 V LC4 -V LC4 -V LC3 -V LC1 V LC5 -V LC2 -V LC5 Figure 15-8. LCD Signal Waveforms (1/16 Duty, 1/5 Bias) (Continued)

LCD CONTROLLER/DRIVER S3C826A/P826A 15- 10 S E G S E G S E G S E G S E G COM1 SEG0 COM2 COM0 SEG0-COM0 0 1 2 3 74 65 0 1 2 3 74 65 V LC3 ( V LC4 ) V LC5 V SS V LC1 V LC2 V LC3 ( V LC4 ) V LC5 V SS V LC1 V LC2 V LC3 ( V LC4 ) V LC5 V SS V LC1 V LC2 V LC3 ( V LC4 ) V LC5 V SS V LC1 V LC2 0 V V LC3 ( V LC4 ) V LC5 V LC1 V LC2 -V LC3 (- V LC4 ) -V LC5 -V LC1 -V LC2 Figure 15-9. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)

S3C826A/P826A 8-BIT A/D CONVERTE R 16- 1 16 8-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 8-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 8 -bit digital values. The analo g input level must lie between the AV DD and V SS values. The A/D converter has the following components: — Analog comparator with successive approximation logic — D/A converter logic (resistor string type) — ADC control register (ADCON) — Four multiplexed analog data input pins (AD0–AD3) — 8-bit A/D conversion data output register (ADDATA) — 4 -bit digital input port (Alternately, I/O port) FUNCTION DESCRIPTION To initiate an analog-to-digital conversion procedure, at first you must set with alternative function for ADC input enable at port 1, the pin set with alternative function can be used for ADC analog input. And you write the channel selection data in the A/D converter control register ADCON.4–.5 to select one of the four analog input pins (AD0–3) and set the conversion start or enable bit, ADCON.0. The read-write ADCON register is located in set 1, bank 0, at address EFH. The pins which are not used for ADC can be used for normal I/O. During a normal conversion, ADC logic initially sets the successive approximation register to 80H (the approximate half-way point of an 8 -bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 8-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.5–4) in the ADCON register. To start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion is completed, ADCON.3, the end-of-conversion(EOC) bit is automatically set to 1 and the result is dumped into the ADDATA register where it can be read. The A/D converter then enters an idle state. Remember to read the contents of ADDATA before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. NOTE Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the AD0–AD3 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in conversion process, there will be a leakage current path in A/D block. You must use STOP or IDLE mode after ADC operation is finished.

8-BIT A/D CONVERTER S3C826A/P826A 16- 2 CONVERSION TIMING The A/D conversion process requires 5 steps (5 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 8-bit conversion: When fxx/8 is selected for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is 1.78 us. Each bit conversion requires 5 clocks, the conversion rate is calculated as follows: 5 clocks/bit × 8-bit + set-up time = 50 clocks, 50 clock × 1.78 us = 89 us at 0.56 MHz (4.5 MHz/8) Note that A/D converter needs at least 25 µs for conversion time. A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address EFH in set 1, bank 0. It has three functions: — Analog input pin selection (bits 4 and 5) — End-of-conversion status detection (bit 3) — ADC clock selection (bits 2 and 1) — A/D operation start or enable (bit 0 ) After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input pins (AD0–AD3) can be selected dynamically by manipulating the ADCON.4–5 bits. And the pins not used for analog input can be used for normal I/O function. Start or enable bit 0 = Disable operation 1 = Start operation (Automatically disable operation after conversion complete) A/D Converter Control Register (ADCON) EFH, Set 1, Bank 0, R/W (EOC bit is read-only) End-of-conversion bit 0 = Not complete Conversion 1 = complete Conversion Always logic zero A/D input pin selection bits: 00 = AD0 01 = AD1 10 = AD2 11 = AD3 Clock Selection bits: 00 = fxx/16 01 = fxx/8 10 = fxx/4 11 = fxx/1 Figure 16-1. A/D Converter Control Register (ADCON)

8-BIT A/D CONVERTER S3C826A/P826A 16- 4 V SS S3C826A AD0-AD3 AV DD Reference Voltage Input Analog Input Pin V DD V DD 10 µF 103C 101C -(AV DD ≤ V DD ) Figure 16-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy

S3C826A/P826A SERIAL I/O INTERFACE 1 7- 1 1 7 SERIAL I/O INTERFAC E OVERVIEW Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The components of SIO function block are: — 8-bit control register (S IOCON ) — Clock selector logic — 8-bit data buffer (SIODATA) — 8-bit prescaler (SIOPS) — 3-bit serial clock counter — Serial data I/O pins (SI, SO) — External clock input/output pin (SCK) The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source. PROGRAMMING PROCEDURE To program the SIO module, follow these basic steps: 1. Configure the I/O pins at port (SCK/SI/SO) by loading the appropriate value to the P1CONH register if necessary. 2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation, SIOCON.2 must be set to "1" to enable the data shifter. 3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON) to "1". 4. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation starts. 5. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.0) are set to "1" and SIO interrupt request is generated.

SERIAL I/O INTERFACE S3C826A/P826A 17- 2 SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E0H in set 1, bank 0. It has the control setting for SIO module. — Clock source selection (internal or external) for shift clock — Interrupt enable — Edge selection for shift operation — Clear 3-bit counter and start shift operation — Shift operation (transmit) enable — Mode selection (transmit/receive or receive-only) — Data direction selection (MSB first or LSB first) A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock source at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation and the interrupt are disabled. The selected data direction is MSB-first. Serial I/O Module Control Register (SIOCON) E0H, Set 1, Bank 0, R/W SIO interrupt enable bit: 0 = Disable SIO interrupt 1 = Enable SIO interrupt SIO interrupt pending bit: 0 = No interrupt pending 0 = Clear pending condition (when write) 1 = Interrupt is pending SIO shift operation enable bit: 0 = Disable shifter and clock counter 1 = Enable shifter and clock counter Shift clock edge selection bit: 0 = t X at falling edeges, rx at rising edges. 1 = t X at rising edeges, rx at falling edges. Data direction control bit: 0 = MSB-first mode 1 = LSB-first mode SIO mode selection bit: 0 = Receive only mode 1 = Transmit/receive mode SIO counter clear and shift start bit: 0 = No action 1 = Clear 3-bit counter and start shifting SIO shift clock selection bit: 0 = Internal clock (P.S Clock) 1 = External clock (SCK) Figure 17- 1. Serial I/O Module Control Register (SIOCON)

S3C826A/P826A ELECT RICAL DATA 18- 1

18 ELECTRICAL DATA

In this chapter, S3C826A electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — A.C. electrical characteristics — Input/output capacitance — Oscillation characteristics — Oscillation stabilization time — Data retention supply voltage in stop mode — Serial I/O timing characteristics — A/D converter electrical characteristics

ELECTRICAL DATA S3C 826A/P826A 18- 2 Table 18-1. Absolute Maximum Ratings (T A = 25 °C) Parameter Symbol Conditions Rating Unit Supply voltage V DD – – 0.3 to +6.5 V Input voltage V I Ports 0 – 15 – 0.3 to V DD + 0.3 Output voltage V O – – 0.3 to V DD + 0.3 Output current high IOH One I/O pin active – 15 mA All I/O pins active – 60 Output current low IOL One I/O pin active + 30 Total pin current for port + 100 Operating temperature T A – 25 to + 85 °C Storage temperature T STG – 65 to + 150 Table 18-2. D.C. Electrical Characteristics (T A = –25 °C to + 85 °C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min. Typ. Max. Unit Operating voltage V DD fx = 0.4–4 MHz, 32.8 kHz 2.0 – 5.5 V fx = 0.4–8 MHz 2.4 – 5.5 fx = 0.4–10MHz 2.7 – 5.5 Input high voltage V IH1 Ports 0–15 0.8 V DD V DD V IH2 RESET 0.8 V DD – V DD V IH3 X IN , X OUT , XT IN , XT OUT V DD –0.1 V DD Input low voltage V IL1 Ports 0–15 0.2 V DD V IL2 RESET – – 0.2 V DD V IL3 X IN , X OUT , XT IN , XT OUT 0.1 Output high voltage V OH V DD = 4.5 V to 5.5 V All output ports; IOH = –1 mA V DD – 1.0 – V DD Output low voltage V OL1 V DD = 4.5 V to 5.5 V All output except ports 2,3; IOL1 = 10 mA – – 2.0 V OL2 V DD = 3.0 V to 5.5 V Ports 2,3; IOL2 = 10 mA – – 1.0

S3C826A/P826A ELECT RICAL DATA 18- 3 Table 18-2. D.C. Electrical Characteristics (Continued) (T A = -25 °C to + 85 °C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min. Typ. Max. Unit Input high leakage current ILIH1 V IN = V DD All input pins except X IN , X OUT, XT IN , XT OUT – – 3 uA ILIH2 V IN = V DD, X IN , X OUT, XT IN , XT OUT 20 Input low leakage current ILIL1 V IN = 0 V All input pins except RESET, X IN , X OUT, XT IN , XT OUT – – -3 ILIL2 V IN = 0 V, X IN , X OUT, XT IN , XT OUT -20 Output high leakage current ILOH V OUT = V DD All output pins – – 3 Output low leakage current ILOL V OUT = 0 V All output pins – – -3 Pull-up resistor R L1 V IN = 0 V T A = 25 °C V DD = 5 V 25 47 100 k Ω Port 0–15 V DD = 3 V 50 90 150 R L2 V IN = 0 V T A = 25 °C V DD = 5 V 150 250 400 RESET V DD = 3 V 300 500 700 Oscillator feed back resistors R OSC1 V DD = 5 V, T A = 25 °C X IN = V DD , X OUT = 0 V 300 600 1500 k Ω R OSC2 V DD = 5 V, T A = 25 °C XT IN = V DD , XT OUT = 0 V 1500 3000 4500 LCD voltage dividing resistor R LCD T A = 25 °C 40 60 80 k Ω |V LCD – COMi| voltage drop (I = 0–15) V DC V DD = 2.7 V to 5.5 V – 15 µA per common pin – – 120 mV |V LCD – SEGx| voltage drop (x = 0–79) V DS V DD = 2.7 V to 5.5 V – 15 µA per common pin – – 120 mV

ELECTRICAL DATA S3C 826A/P826A 18- 4 Table 18-2. D.C. Electrical Characteristics (Concluded) (T A = -25 °C to + 85 °C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Units Supply Current (1) IDD1 Run mode : V DD = 5 V ± 10% Crystal oscillator 10.0 MHz – 7.0 14.0 mA C1 = C2 = 22pF 4.19 MHz 3.0 6.0 V DD = 3 V ± 10% 10.0 MHz 3.5 7.0 4.19 MHz 1.6 3.2 IDD2 Idle mode : V DD = 5 V ± 10% Crystal oscillator 10.0 MHz 1.5 3.0 C1 = C2 = 22pF 4.19 MHz 1.0 2.0 V DD = 3 V ± 10% 10.0 MHz 1.0 2.0 4.19 MHz 0.4 0.8 IDD3 Run mode : V DD = 3 V ± 10% 32kHz Crystal oscillator 15 30 uA IDD4 Idle mode : V DD = 3 V ± 10% 32kHz Crystal oscillator 6 15 IDD5 Stop mode : V DD = 5 V ± 10% T A = 25 °C 0.5 3 Stop mode : V DD = 3 V ± 10% T A = 25 °C 0.3 2 NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and ADC. 2. IDD1 and I DD2 include power consumption for sub clock oscillation. 3. IDD3 and I DD4 are current when main clock oscillation stops and the sub clock is used. 4. IDD5 is current when main clock and sub clock oscillation stops. 5. Every values in this table is measured when bits 4–3 of the system clock control register (CLKCON.4–.3) is set to “11B”.

S3C826A/P826A ELECT RICAL DATA 18- 5 Table 18-3. A.C. Electrical Characteristics (T A = -25 °C to +85 °C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Interrupt input high, low width tINTH , tINTL V DD = 5 V 200 – – ns RESET input low width tRSL V DD = 5 V 10 – – us tTIHtTIL

0.8 V DD

0.2 V DD0.2 V DD Figure 18-1. Input Timing for External Interrupts (P0, P3.4–P3.7) tRSL

0.2 V DD

Figure 18-2. Input Timing for RESETRESET

ELECTRICAL DATA S3C 826A/P826A 18- 6 Table 18-4. Input/Output Capacitance (T A = -25 °C to +85 °C, V DD = 0 V ) Parameter Symbol Conditions Min Typ Max Unit Input capacitance C IN f = 1 MHz; unmeasured pins are returned to V SS – – 10 pF Output capacitance C OUT I/O capacitance C IO Table 18-5. Data Retention Supply Voltage in Stop Mode Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage V DDDR 2.0 – 5.5 V Data retention supply current IDDDR V DDDR = 2 V (TA = 25 °C) Stop mode – – 1 uA Execution of STOP Instrction RESET Occurs V DDDR Stop Mode Oscillation Stabilization Time Normal Operating ModeData Retention Mode tWAIT RESET V DD NOTE: tWAIT is the same as 4096 x 16 x 1/fxx Figure 18-3. Stop Mode Release Timing Initiated by RESETRESET

S3C826A/P826A ELECT RICAL DATA 18- 7 Execution of STOP Instruction V DDDR Stop Mode Idle Mode Data Retention Mode tWAIT V DD Interrupt Normal Operating Mode Oscillation Stabilization Time NOTE: tWAIT is the same as 16 x 1/BT clock Figure 18-4. Stop Mode Release Timing Initiated by Interrupts

ELECTRICAL DATA S3C 826A/P826A 18- 8 Table 18-6. A/D Converter Electrical Characteristics (T A = -25 °C to + 85 °C, V DD = 2.7 V to 5.5 V, V SS = 0 V) Parameter Symbol Conditions Min Typ Max Unit Resolution – 8 – bit Total A ccuracy V DD = 5.12V, fxx = 8MHz f CON = fxx/4 – – ± 2 LSB Conversion Time (1) tCON 8-bit resolution 50 x fxx/4, fxx = 8 MHz 25 – – µS Analog Input Voltage V IAN – V SS – AV DD V Analog Input Impedance R AN – 2 1000 – M Ω Analog Input Current IADIN AV DD = V DD = 5V – 10 µA Analog Block Current (2) IADC AV DD = V DD = 5V – 1 3 mA AV DD = V DD = 3V 0.5 1.5 AV DD = V DD = 5V When power down mode 100 500 nA NOTES: 1. 'Conversion tim e' is the time required from the moment a conversion operation starts until it ends. 2. IADC is an operating current of A/D converter. Table 18-7. LCD Contrast Controller Electrical Characteristics (T A = -25 °C to + 85 °C, V DD = 2.7 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Resolution – – – – 4 Bits Linearity R LIN V DD = 5.0V – – ± 150 mV Max Output Voltage V LPP V LC1 = V DD = 5V (LCON = #0FDH) 4.9 – V LC1 V

S3C826A/P826A ELECT RICAL DATA 18- 9 Table 18-8. Synchronous SIO Electrical Characteristics (T A = –25 °C to +85 °C, V DD = 2.0 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit SCK cycle time tCKY External SCK source 1000 – – ns Internal SCK source 1000 SCK high, low width tKH , t KL External SCK source 500 – – Internal SCK source tKCY /2– SI setup time to tSIK External SCK source 250 – – SCK high Internal SCK source 250 SI hold time to tKSI External SCK source 400 – – SCK high Internal SCK source 400 Output delay for tKSO External SCK source – – 300 SCK to SO Internal SCK source 250 Output Data Input Data SCK tKH tCKY tKL Figure 18-5. Serial Data Transfer Timing

ELECTRICAL DATA S3C 826A/P826A 18- 10 Table 18-9. Main Oscillator Characteristics Oscillator Clock Circuit Parameter Condition (V DD ) Min Typ Max Unit Crystal Main oscillation frequency 2.7 V – 5.5 V 0.4 – 10 MHz 2.4 V – 5.5 V 0.4 – 8 2.0 V – 5.5 V 0.4 – 4 Ceramic Main oscillation frequency 2.7 V – 5.5 V 0.4 – 10 2.4 V – 5.5 V 0.4 – 8 2.0 V – 5.5 V 0.4 – 4 External clock X IN input frequency 2.7 V – 5.5 V 0.4 – 10 2.4 V – 5.5 V 0.4 – 8 2.0 V – 5.5 V 0.4 – 4 RC X IN X OUT R Frequency 5.0 V 0.4 – 2 MHz Frequency 3.0 V 0.4 – 1 Table 18-10. Sub Oscillator Characteristics Oscillator Clock Circuit Parameter Condition (V DD ) Min Typ Max Unit Crystal XT IN XT OUT C1 Sub oscillation frequency 2.0 V–5.5 V 32 32.768 35 kHz External clock XT IN XT OUT XT IN input frequency 2.0 V–5.5 V 32 – 100 kHz X IN X OUT X IN X OUT X IN X OUT

ELECTRICAL DATA S3C 826A/P826A 18- 12 Instruction Clock 6.25 kHz(main)/8.2 kHz(sub) 1 2 3 4 5 6 7 Supply Voltage (V)

2.5 MHZ

fx (Main/Sub Oscillator Frequency) 400 kHz(main)/32.8 kHz(sub) Instruction Clock = 1/4n x oscillator frequency (n = 1,2,8,16)

8.0 MHZ

2.4

4.0 MHZ

2.7 5.5

2.0 MHZ

1.0 MHZ

10 MHZ

Figure 18-8. Operating Voltage Range

S3C826A/P826A MECHANICAL D ATA 19- 1

19 MECHANICAL DATA

The S3C826A micr ocontroller is currently available in 144 - pin QFP-2828-AN package. 144-QFP-2828-AN #144 28.00 ± 0.20 32.00 ± 0.30 28.00 ± 0.20 32.00 ± 0.30

0.10 MAX

0.15 + 0.10 - 0.05 0-10 NOTES : 1. Dimensions are in millimeters. 2. The package of S3C826A is only for engineer sample. 0.65 0.30 + 0.10 - 0.05 (2.63) 0.80 ± 0.20

0.05 MIN

3.75 ± 0.10

4.00 MAX

Figure 19-1. Package Dimensions (144-QF P -2828-AN)

MECHANICAL DATA S3C826A/P826A 19- 2 NOTES

S3C826A/P826A S3P826 A OTP 20- 1

20 S3P826A OTP

The S3P826A single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C826A microcontroller. It has an on-chip OTP ROM instead of a masked ROM. The EPROM is accessed by serial data format. The S3P826A is fully compatible with the S3C826A, both in function in D.C. electrical characteristics and in pin configuration. Because of its simple programming requirements, the S3P826A is ideal as an evaluation chip for the S3C826A.

S3P826A OTP S3C826A/ P826A 20- 2 COM0/P15.7 P2.0/T0CLK P2.1/T0OUT/T0PWM/T0CAP P2.2/T1CLK P2.3/TAOUT P2.4/TBOUT P2.5 P2.6 P2.7 P3.0/T2CLK P3.1/T2OUT P3.2/T3CLK P3.3/T3OUT/T3PWM/T3CAP INT8/P3.4 INT9/P3.5 SDAT /INT10/P3.6 SCLK /INT11/P3.7 V DD /V DD1 V SS /V SS1 X OUT X IN V PP /TEST XT IN XT OUT RESETRESET/RESET P0.0/INT0 P0.1/INT1 P0.2/INT2 P0.3/INT3 P0.4/INT4 P0.5/INT5 P0.6/INT6 P0.7/INT7 P1.0/AD0 P1.1/AD1 P1.2/AD2 COM1/P15.6 COM2/P15.5 COM3/P15.4 COM4/P15.3 COM5/P15.2 COM6/P15.1 COM7/P15.0 SEG87/COM8/P14.7 SEG86/COM9/P14.6 SEG85/COM10/P14.5 SEG84/COM11/P14.4 SEG83/COM12/P14.3 SEG82/COM13/P14.2 SEG81/COM14/P14.1 SEG80/COM15/P14.0 SEG0/P13.7 SEG1/P13.6 SEG2/P13.5 SEG3/P13.4 SEG4/P13.3 SEG5/P13.2 SEG6/P13.1 SEG7/P13.0 SEG8/P12.7 SEG9/P12.6 SEG10/P12.5 SEG11/P12.4 SEG12/P12.3 SEG13/P12.2 SEG14/P12.1 SEG15/P12.0 SEG16/P11.7 SEG17/P11.6 SEG18/P11.5 SEG19/P11.4 SEG20/P11.3 P1.3/AD3 P1.4/SCK P1.5/SO P1.6/SI P1.7/BUZ V LC1 V LC2 V LC3 V LC4 V LC5 AVDD SEG79/P4.0 SEG78/P4.1 SEG77/P4.2 SEG76/P4.3 SEG75/P4.4 SEG74/P4.5 SEG73/P4.6 SEG72/P4.7 SEG71/P5.0 SEG70/P5.1 SEG69/P5.2 SEG68/P5.3 SEG67/P5.4 SEG66/P5.5 SEG65/P5.6 SEG64/P5.7 SEG63/P6.0 SEG62/P6.1 SEG61/P6.2 SEG60/P6.3 SEG59/P6.4 SEG58/P6.5 SEG57/P6.6 SEG56/P6.7 SEG55/P7.0 SEG21/P11.2 SEG22/P11.1 SEG23/P11.0 SEG24/P10.7 SEG25/P10.6 SEG26/P10.5 SEG27/P10.4 SEG28/P10.3 SEG29/P10.2 SEG30/P10.1 SEG31/P10.0 SEG32/P9.7 SEG33/P9.6 SEG34/P9.5 SEG35/P9.4 SEG36/P9.3 SEG37/P9.2 SEG38/P9.1 V DD2 V SS2 SEG39/P9.0 SEG40/P8.7 SEG41/P8.6 SEG42/P8.5 SEG43/P8.4 SEG44/P8.3 SEG45/P8.2 SEG46/P8.1 SEG47/P8.0 SEG48/P7.7 SEG49/P7.6 SEG50/P7.5 SEG51/P7.4 SEG52/P7.3 SEG53/P7.2 SEG54/P7.1 S3P826A (144-QFP-2828-AN) 108 107 106 105 104 103 102 101 100 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 NOTE: The package of S3P826A is only for engineer sample. Figure 20-1. S3P826A Pin Assignments (144-Pin QFP-2828-AN Package)

S3C826A/P826A S3P826 A OTP 20- 3 Table 20-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P3.6 SDAT 16 I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. P3.7 SCLK 17 I Serial clock pin. Input only pin. TEST V PP 22 I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) RESET RESET 25 I Chip Initialization V DD1 /V SS1 V DD /V SS 18/19 – Logic power supply pin. V DD should be tied to +5 V during programming. Table 20-2. Comparison of S3P826A and S3C826A Features Characteristic S3P826A S3C826A Program Memory 48-Kbyte EPROM 48-Kbyte mask ROM Operating Voltage (V DD ) 2.0 V to 5.5 V 2.0 V to 5.5 V OTP Programming Mode V DD = 5 V, V PP (TEST) = 12.5 V Pin Configuration Pellet only Pellet only EPROM Programmability User Program 1 time Programmed at the factory

S3P826A OTP S3C826A/ P826A 20- 4 OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the V PP (TEST) pin of the S3P826A, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 20-3 below. Table 20-3. Operating Mode Selection Criteria V DD V PP (TEST) REG/ MEMMEM Address(A15–A0) R/W Mode

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level. Instruction Clock 6.25 kHz(main)/8.2 kHz(sub) 1 2 3 4 5 6 7 Supply Voltage (V) fx (Main/Sub Oscillator Frequency) 400 kHz(main)/32.8 kHz(sub) Instruction Clock = 1/4n x oscillator frequency (n = 1,2,8,16) 2.4 2.7 5.5 Figure 20-2. Operating Voltage Range

S3C826A/P826A DEVELOPMENT TOOLS 21- 1

21 DEVELOPMENT TOOLS

Samsung provides a powerful and easy-to-use development support system in turnkey form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7 , S3C 6, S3C 8 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, as s embler, and a program for setting options. SHINE Samsung Host Interface for In - C ircuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM88 The SASM88 is a relocatable assembler for Samsung's S3C 8-series microcontrollers. The SASM88 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM88 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value " FF " is filled into the unused ROM area up to the maximum ROM size of the target device automatically. TARGET BOARDS Target boards are available for all S3C 8-series microcontrollers. All required target system cables and adapters are included with the device-specific target board.

DEVELOPMENT TOOLS S3C826A/P826A 21- 2 SMDS2+RS-232C POD Probe Adapter TB826A Target Board IBM-PC AT or Compatible PROM/OTP Writer Unit Bus RAM Break/Display Unit Trace/Timer Unit SAM8 Base Unit Power Supply Unit Target Application System Eva Chip Figure 21-1. SMDS Product Configuration (SMDS2+)

S3C826A/P826A DEVELOPMENT TOOLS 21- 3 TB826A TARGET BOARD The TB826A target board is used for the S3C826A microcontroller. It is supported with the SMDS2+. TB826A SM1348A GND V CC RESET

208 QFP

To User_V CC Off On J102 50-Pin Connector 49 50 50-Pin Connector 49 50 J103 SMDS2 SMDS2+ 52 1 104 105 156 157 208 C11 Idle Stop C14 J101 50-Pin Connector 49 50 100-Pin Connector R5 R4 JP1 T24-T20 T1-T4 C10 T19 C15 SMDS2 SMDS2+ NOTES: 1. J1 is AD0-AD3 pins from right side. 2. JP1 is V LC1 -V LC5 pins from right side. Figure 21-2 . TB826A Target Board Configuration

DEVELOPMENT TOOLS S3C826A/P826A 21- 4 Table 21-1. Power Selection Settings for TB826A " To User_V CC " Settings Operating Mode Comments To User_V CC Off On Target System SMDS2/SMDS2+ TB826A V CC V SS V CC The SMDS2 /SMDS2+ supplies V CC to the target board (evaluation chip) and the target system. To User_V CC Off On Target System SMDS2/SMDS2+ External V CC V SS V CC TB826A The SMDS2 /SMDS2+ supplies V CC only to the target board (evaluation chip). The target system must have its own power supply. NOTE : The following symbol in the " To User_Vcc " Setting column indicates the electrical short (off) configuration: SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 21-2 . The SMDS2+ Tool Selection Setting "SW1" Setting Operating Mode SMDS2 SMDS2+ Target Board R/W R/W SMDS2+ IDLE LED The Yellow LED is ON when the evaluation chip ( S3E8260 ) is in idle mode. STOP LED The Red LED is ON when the evaluation chip ( S3E8260 ) is in stop mode.

S3C826A/P826A DEVELOPMENT TOOLS 21- 5 SEG76/P4.3 SEG74/P4.5 SEG72/P4.7 SEG70/P5.1 SEG68/P5.3 SEG66/P5.5 SEG64/P5.7 SEG62/P6.1 SEG60/P6.3 SEG58/P6.5 SEG56/P6.7 SEG54/P7.1 SEG52/P7.3 SEG50/P7.5 SEG48/P7.7 SEG46/P8.1 SEG44/P8.3 SEG42/P8.5 SEG40/P8.7 V SS2 SEG38/P9.1 SEG36/P9.3 SEG34/P9.5 SEG32/P9.7 SEG30/P10.1 J102 SEG75/P4.4 SEG73/P4.6 SEG71/P5.0 SEG69/P5.2 SEG67/P5.4 SEG65/P5.6 SEG63/P6.0 SEG61/P6.2 SEG59/P6.4 SEG57/P6.6 SEG55/P7.0 SEG53/P7.2 SEG51/P7.4 SEG49/P7.6 SEG47/P8.0 SEG45/P8.2 SEG43/P8.4 SEG41/P8.6 SEG39/P9.0 V DD2 SEG37/P9.2 SEG35/P9.4 SEG33/P9.6 SEG31/P10.0 SEG29/P10.2 50-Pin DIP Connector J103 SEG28/P10.3 SEG26/P10.5 SEG24/P10.7 SEG22/P11.1 SEG20/P11.3 SEG18/P11.5 SEG16/P11.7 SEG14/P12.1 SEG12/P12.3 SEG10/P12.5 SEG8/P12.7 SEG6/P13.1 SEG4/P13.3 SEG2/P13.5 SEG0/P13.7 SEG81/COM14/P14.1 SEG83/COM12/P14.3 SEG85/SOM10/P14.5 SEG87/COM8/P14.7 COM6/P15.1 COM4/P15.3 COM2/P15.5 N.C N.C N.C SEG27/P10.3 SEG25/P10.5 SEG23/P10.7 SEG21/P11.1 SEG19/P11.3 SEG17/P11.5 SEG15/P11.7 SEG13/P12.1 SEG11/P12.3 SEG9/P12.5 SEG7/P12.7 SEG5/P13.1 SEG3/P13.3 SEG1/P13.5 SEG80/COM15/P14.0 SEG82/COM13/P14.2 SEG84/COM11/P14.4 SEG86/COM9/P14.6 COM7/P15.0 COM5/P15.2 COM3/P15.4 COM1/P15.6 N.C N.C N.C 50-Pin DIP Connector J101 50-Pin DIP Connector COM0/P15.7 P2.1/T0OUT/T0PWM/T0CAP P2.3/TAOUT P2.5 P2.7 P3.1/T2OUT P3.3/T3OUT/T3PWM/T3CAP INT9/P3.5 INT11/P3.7 V SS1 X IN XT IN RESET P0.1/INT1 P0.3/INT3 P0.5/INT5 P0.7/INT7 P1.1/AD1 P1.3/AD3 P1.5/AO P1.7/BUZ V LC2 V LC4 AVDD SEG78/P4.1 P2.0/T0CLK P2.2/T1CLK P2.4/TBOUT P2.6 P3.0/T2CLK P3.2/T3CLK INT8/P3.4 INT10/P3.6 V DD1 X OUT TEST XT OUT P0.0/INT0 P0.2/INT2 P0.4/INT4 P0.6/INT6 P1.0/AD0 P1.2/AD2 P1.4/SCK P1.6/SI V LC1 V LC3 V LC5 SEG79/P4.0 SEG77/P4.2 Figure 21-3 . 50 -Pin Connector s (J101, J102, J103) for TB826A

DEVELOPMENT TOOLS S3C826A/P826A 21- 6 Target Board Target System 50-Pin DIP Connector Target Cable for 50-Pin Connector Part Name: AS50D-A Order Code: SM6305 50-Pin DIP ConnectorsJ103 1 2 49 50 J102 1 2 49 50 J103 1 2 49 50 J102 1 2 49 50 Target Board Target System 50-Pin DIP Connector Target Cable for 50-Pin Connector Part Name: AS50D-A Order Code: SM6305 50-Pin DIP ConnectorsJ101 1 2 49 50 J101 1 2 49 50 Figure 21-4 . S3C826A Cables for 144 - QF P Package

Product Information

S3P826A specifications and overview.

Summary

8-Bit CMOS Microcontroller

Description

8-Bit CMOS Microcontroller

Source title S3P826A Datasheet(PDF) - Samsung semiconductor

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