S3C9648

S3C9644 SAMSUNG | Alldatasheet

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S3C9644/C9648/P9648 PRODUCT OVERVIEW 1- 1

1 PRODUCT OVERVIEW

Samsung's SAM87RI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. Many SAM87RI microcontrollers have an external interface that provides access to external memory and other peripheral devices. S3C9644/C9648/P9648 Microcontroller The S3C9644/C9648/P9648 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM87RI CPU core. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The S3C9644 has 4K-bytes of program memory on-chip and S3C9648 has 8K-bytes. Using the SAM87RI design approach, the following peripherals were integrated with the SAM87RI core: — Five configurable I/O ports (32 pins) — 20 bit-programmable pins for external interrupts — 8-bit timer/counter with three operating modes — Low speed USB function The S3C9644/C9648/P9648 is a versatile microcontroller that can be used in a wide range of low speed USB support general purpose applications. It is especially suitable for use as a keyboard controller and is available in a 42 -pin SDIP and a 44-pin QFP package. OTP The S3C9644/C9648 microcontroller is also available in OTP (One Time Programmable) version, S3P9648. S3P9648 microcontroller has an on-chip 8K-byte one-time-programmable EPROM instead of masked ROM. The S3P9648 is comparable to S3C9644/C9648, both in function and in pin configuration.

PRODUCT OVERVIEW S3 C9644/C9648/P9648 1- 2

FEATURES

• SAM87RI CPU core Memory
• 4/8K-byte internal program memory (ROM)
• 208-byte RAM Instruction Set
• 41 instructions
• IDLE and STOP instructions added for power- down modes Instruction Execution Time
• 1.0 µs at 6 MHz f OSC Interrupts
• 25 interrupt sources with one vector, each source has its pending bit
• One level, one vector interrupt structure Oscillation Circuit
• 6 MHz crystal/ceramic oscillator
• External clock source (6 MHz) General I/O
• Bit programmable five I/O ports (34 pins total) — (D+/PS2, D-/PS2 Included) Timer/Counter
• One 8-bit basic timer for watchdog function and programmable oscillation stabilization interval generation function
• One 8-bit timer/counter with Compare/Overflow USB Serial Bus
• Compatible to USB low speed (1.5 Mbps) device 1.0 specification.
• 1 Control endpoint and 2 Data endpoint
• Serial bus interface engine (SIE) — Packet decoding/generation — CRC generation and checking — NRZI encod ing/decoding and bit-stuffing
• 8 bytes each receive/transmit USB buffer Operating Temperature Range
• – 40 _C to + 85 _C Operating Voltage Range
• 4.0 V to 5.25 V Package Types
• 42-pin SDIP
• 44-pin QFP

S3C9644/C9648/P9648 PRODUCT OVERVIEW 1- 3 BLOCK DIAGRAM Port 0 Port 3 SAM87RI CPU P0.0-P0.7/INT2 4/8-KB ROM P3.0 P3.1 P3.2 P3.3/CLO OSC 208-Byte Register Port 4 P4.0 / INT1 P4.1 / INT1 P4.2 / INT1 P4.3 / INT1 TIMER 0 Port 1 Port 2 P2.0-P2.7 / INT0P1.0-P1.7 X IN X OUT SAM87RI BUS Basic Timer I/O Port And Interrupt Control USB D+/PS2 D-/PS2

3.3 V OUT

Figure 1-1. Block Diagram

PRODUCT OVERVIEW S3 C9644/C9648/P9648 1- 4 PIN ASSIGNMENTS P3.1 P3.0 INT0 / P2.0 INT0 / P2.1 INT0 / P2.2 INT0 / P2.3 INT0 / P2.4 INT0 / P2.5 INT0 / P2.6 INT0 / P2.7 V DD V SS X OUT X IN TEST INT1 / P4.0 INT1 / P4.1 RESET INT1 / P4.2 INT1 / P4.3 P1/7 S3C9644 S3C9648 42-SDIP (Top View) P3.2 P3.3/CLO D+/PS2 D-/PS2 P0.0 / INT P0.1 / INT P0.2 / INT P0.3 / INT P0.4 / INT P0.5 / INT P0.6 / INT P0.7 / INT P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)

S3C9644/C9648/P9648 PRODUCT OVERVIEW 1- 5 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P4.3/INT1 P4.2/INT1 RESET P3.3/CLO P3.2 P3.1 P3.0 P2.0/INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 NC NC NC P0.0/INT2 P0.1/INT2 P0.2/INT2 P0.3/INT2 P0.4 /INT2 P0.5/INT2 P0.6/INT2 P0.7/INT2 INT0 / P2.4 INT0 / P2.5 INT0 / P2.6 INT0 / P2.7 V DD V SS X OUT X IN TEST P4.0/INT1 P4.1/INT1 S3C9644 S3C9648 44-QFP (Top View) Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)

PRODUCT OVERVIEW S3 C9644/C9648/P9648 1- 6 PIN DESCRIPTIONS Table 1-1. S3C9644/C9648/P6408 Pin Descriptions Pin Names Pin Type Pin

Description

P0.0-P0.7 I/O Bit-programmable I/O port for Schmitt trigger input or open-drain output. Port0 can be individually configured as external interrupt inputs. Pull-up resistors are assignable by software. B 36-29 (30-23) INT2 P1.0-P1.7 I/O Bit-programmable I/O port for Schmitt trigger input or open-drain output. Pull-up resistors are assignable by software. B 28-21 (22-15) P2.0-P2.7 I/O Bit-programmable I/O port for Schmitt trigger input or open-drain output. Port2 can be individually configured as external interrupt inputs. Pull-up resistors are assignable by software. B 3-10 (41-44, 1-4) INT0 P3.0-P3.3 I/O Bit-programmable I/O port for Schmitt trigger input, open-drain or push-pull output. P3.3 can be used to system clock output(CLO) pin. C 2, 1, 42, 41 (40-37) P3.3/CL O P4.0-P4.3 I/O Bit-programmable I/O port for Schmitt trigger input or open-drain output or push-pull output. Port4 can be individually configured as external interrupt inputs. In output mode, pull-up resistors are assignable by software. But in input mode, pull-up resistors are fixed. D 16, 17, 19, 20 (10, 11, 13, 14) INT1 D+/PS2 D-/PS2 I/O Programmable port for USB interface or PS2 interface. – 40-39 (36-35) – 3.3 V OUT – 3.3 V output from internal voltage regulator – 38 (34) – X IN , X OUT – System clock input and output pin (crystal/ceramic oscillator, or external clock source) – 14, 13 (8, 7) INT0 INT1 INT2 I External interrupt for bit-programmable port0, port2 and port4 pins when set to input mode. – 3-10, 16,17, 19, 20, 29-36 (30-23, 41-44, 1-4, 10, 11, 13, 14) PORT2/ PORT4/ PORT0 RESET I RESET signal input pin. Input with internal pull-up resistor. A 18 (12) – TEST I Test signal input pin (for factory use only; connected to V SS ) – 15 (9) – V DD – Power input pin – 11 (5) – V SS – Ground input pin – 12, (6) – NC – No connection – 37 (31,32, 33) NOTE: Pin numbers shown in parenthesis '( )' are for the 44-QFP package; others are for the 42-SDIP package.

PRODUCT OVERVIEW S3 C9644/C9648/P9648 1- 8 V DD Open Drain Output Disable In put Data Mode In put Data In put Out put D0 I/O Output Data V SS MUX D0 Figure 1-6. Pin Circuit Type C (Port 3)

S3C9644/C9648/P9648 PRODUCT OVERVIEW 1- 9 V DD Open Drain Output Disable In put Data Mode In put Data In put Out put D0 I/O Output Data V SS Pull-Up Enable V DD Pull-Up Resistor MUX Figure 1-7. Pin Circuit Type D (Port 4)

PRODUCT OVERVIEW S3 C9644/C9648/P9648 1- 10 APPLICATION CIRCUIT X OUT KEYBOARD MATRIX X IN V SS1 V DD Port 3 Port 0Port 1Port 2 RESET H O S T DP DM S3C9644 S3C9648 S3P9648 Port 4 D+/PS2 D-/PS2 NOTE : Port4 can use expend keyboard MATRIX. D+/PS2, D-/PS2 can use PS2 keyboard interface (see PS2CONINT, page 4-25). Port 4.2, 4.3 can use PS2 mouse interface. Port 3 can use LED direct drive. Figure 1-8. Keyboard Application Circuit Diagram

S3C9644/C9648/P9648 ELECTRICAL DATA 12- 1

12 ELECTRICAL DATA

In this section, the following S3C9644/C9648/P9648 electrical characteristics are presented in tables and graphs: — Absolute maximum ratings — D.C. electrical characteristics — Inp ut/Output capacitance — A.C. electrical characteristics — Input timing for external interrupt (Ports 0, 2 and 4) D+/PS2, D-/PS2 : PS2 Mode Only — Input timing for RESET — Oscillator characteristics — Oscillation stabilization time — Clock timing measurement points at X IN — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by a reset — Stop mode release timing when initiated by an external interrupt — Characteristic curves

ELECTRICAL DATA S3C 9644/C9648/P9648 12- 2 Table 12-1. Absolute Maximum Ratings (T A = 25 °C ) Parameter Symbol Conditions Rating Unit Supply Voltage V DD – – 0.3 to + 6.5 V Input Voltage V IN All input ports – 0.3 to V DD + 0.3 V Output Voltage V O All output ports – 0.3 to V DD + 0.3 V Output Current High IOH One I/O pin active – 18 mA All I/O pins active – 60 Output Current Low IOL One I/O pin active + 30 mA Total pin current for ports 3 + 100 Total pin current for ports 0, 1, 2, 4 + 100 Operating Temperature T A – – 40 to + 85 °C Storage Temperature T STG – – 65 to + 150 °C

S3C9644/C9648/P9648 ELECTRICAL DATA 12- 3 Table 12-2. D.C. Electrical Characteristics (T A = – 40 °C to + 85 °C , V DD = 4.0 V to 5.25 V) Parameter Symbol Conditions Min Typ Max Unit Operating Voltage V DD f OSC = 6 MHz (instruction clock = 1 MHz) 4.0 5.0 5.25 V Input High Voltage V IH1 All input pins except V IH2 0.8 V DD – V DD V V IH2 X IN V DD – 0.5 V DD V IH3 RESET 0.5V DD Input Low Voltage V IL1 All input pins except V IL2 – – 0.2 V DD V V IL2 X IN 0.4 V IL2 RESET 0.5V DD Output High Voltage V OH IOH = – 200 µA; All output ports except ports 0, 1 and 2, D+, D– V DD – 1.0 – – V Output Low Voltage V OL IOL = 1 mA All output port except D+, D– – – 0.4 V Output Low Current IOL V OL = 3V Port 3 only 8 15 23 mA Input High Leakage Current ILIH1 (3) V IN = V DD All inputs except I LIH2 except D+, D– – – 3 µA ILIH2 (3) V IN = V DD X IN, X OUT, RESET – – 20 µA Input Low Leakage Current ILIL1 (3) V IN = 0 V All inputs except I LIL2 except D+, D– – – – 3 µA ILIL2 (3) V IN = 0 V X IN, X OUT, RESET – – – 20 µA

ELECTRICAL DATA S3C 9644/C9648/P9648 12- 4 Table 12-2. D.C. Electrical Characteristics (continued) (T A = – 40 °C to + 85 °C , V DD = 4.0 V to 5.25 V) Parameter Symbol Conditions Min Typ Max Unit Output High Leakage Current ILOH (1) V OUT = V DD All I/O pins and output pins except D+, D– – – 3 µA Output Low Leakage Current ILOL (1) V OUT = 0 V All I/O pins and output pins except D+, D– – – – 3 µA Pull-up Resistors R L1 V IN = 0 V Ports 0, 1, 2, 4.2-3, Reset 25 50 100 k Ω R L2 V IN = 0 V; P4.0-1 2.4 Supply Current (2) IDD1 Normal operation mode

6 MHz CPU clock

– 5.5 12 mA IDD2 Idle mode; 6 MHz oscillator 2.2 5 mA IDD3 Stop mode 180 300 µA NOTES: 1. Except X IN and X OUT . 2. Supply current does not include current drawn through internal pull-up resistors or external output current loads.

S3C9644/C9648/P9648 ELECTRICAL DATA 12- 5 Table 12-3. Input/Output Capacitance (T A = – 40 °C to + 85 °C , V DD = 0 V) Parameter Symbol Conditions Min Typ Max Unit Input Capacitance C IN f = 1 MHz; Unmeasured pins are connected to V SS – – 10 pF Output Capacitance C OUT I/O Capacitance C IO Table 12-4. A.C. Electrical Characteristics (T A = – 40 °C to + 85 °C , V DD = 4.0 V to 5.25 V) Parameter Symbol Conditions Min Typ Max Unit Interrupt Input High, Low Width tINTH , t INTL P0, P2 and P4 – 200 – ns RESET Input Low Width tRSL RESET 10 – – µs t INTL t INTH

0.8 V DD

0.2 V DD

Figure 12-1. Input timing for external interrupt (Ports 0, 2, and 4) RESET t RSL 0.5V DD Figure 12-2. Input Timing for RESET

ELECTRICAL DATA S3C 9644/C9648/P9648 12- 6 Table 12-5. Oscillator Characteristics (T A = – 40 °C + 85 °C , V DD = 4.0 V to 5.25 V) Oscillator Clock Circuit Test Condition Min Typ Max Unit Main crystal Main ceramic (f OSC ) XIN XOUT Oscillation frequency – 6.0 – MHz External clock XIN XOUT Oscillation frequency – 6.0 – Table 12-6. Oscillation Stabilization Time (T A = – 40 °C + 85 °C , V DD = 4.0 V to 5.25 V) Oscillator Test Condition Min Typ Max Unit Main Crystal f OSC = 6.0 MHz – – 10 ms Main Ceramic (Oscillation stabilization occurs when V DD is equal to the minimum oscillator voltage range.) Oscillator Stabilization Wait Time tWAIT stop mode release time by a reset – 2 16 / f OSC tWAIT stop mode release time by an interrupt – (note) – NOTE: The oscillator stabilization wait time, t WAIT , is determined by the setting in the basic timer control register, BTCON.

S3C9644/C9648/P9648 ELECTRICAL DATA 12- 7 Table 12-7. Data Retention Supply Voltage in Stop Mode Parameter Symbol Conditions Min Typ Max Unit Data Retention Supply Voltage V DDDR Stop mode 2.0 – 6 V Data Retention Supply Current IDDDR Stop mode; V DDDR = 2.0 V – – 300 µA t XL t XH V DD 0.5V 0.4V X IN 1/f OSC Figure 12-3. Clock Timing Measurement Points at X IN

ELECTRICAL DATA S3C 9644/C9648/P9648 12- 8 t WAIT V DD RESET Execution Of Stop Instruction V DDDR Data Retention Mode Stop Mode Internal Reset Oper a tion Idle Mode (Basic Timer Active)0.5 V DD

0.5 V DD

Figure 12-4. Stop Mode Release Timing When Initiated by a Reset tWAIT V DD External Interrupt Execution Of Stop Instruction V DDDR Data Retention Mode Stop Mode Idle Mode (Basic Timer Active)0.8 V DD Figure 12-5. Stop Mode Release Timing When Initiated by an External Interrupt

S3C9644/C9648/P9648 MECHANICAL DATA 13- 1

13 MECHANICAL DATA

The S3C9644/C9648/P9648 is available in a 42-pin SDIP package (Samsung: 42-SDIP-600) and a 44-pin QFP package (44 -QFP-1010B). Package dimensions are shown in Figures 13-1 and 13-2. 0-15 ° 15.24 0.25 +0.1 – 0.05 0.51MIN 3.50 ± 0.2 3.30 ± 0.3 5.08MAX 39.10 ± 0.2

39.50 MAX

1.00 ± 0.1 0.50 ± 0.1 (1.77) 1.778 14.00 ³ 0.2 #1 #21 #42 #22 40-SDIP-600 Figure 13-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600 )

MECHANICAL DATA S3C 9644/C9648/P9648 13- 2 NOTE : Dimensions are in millimeters. 44-QFP-1010B 13.20 ± 0.3 #44 (1.00) 13.20 ± 0.3 10.00 ± 0.2 0.35 +0.10 - 0.05

0.10 MAX

0.15 +0.10 - 0.05 0 −8°

0.05 MIN

2.05 ± 0.10

2.30 MAX

0.80 ±0.20 0.80 10.00 ± 0.2 Figure 13-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)

S3C9644/C9648/P9648 S3P9648 OTP 14- 1

14 S3P9648 OTP

The S3P9648 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9644/C9648 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P9648 is fully compatible with the S3C9644/C9648, both in function and in pin configuration. Because of its simple programming requirements, the S3P9648 is ideal for use as an evaluation chip for the S3C9644/C9648. P3.1 P3.0 INT0 / P2.0 INT0 / P2.1 INT0 / P2.2 INT0 / P2.3 INT0 / P2.4 INT0 / P2.5 SDAT /INT0 / P2.6 SCLK / INT0 / P2.7 V DD / V DD V SS /V SS X OUT / X OUT X IN /X IN TEST /TEST INT1 / P4.0 INT1 / P4.1 RESETRESET / RESET INT1 / P4.2 INT1 / P4.3 P1/7 S3P9648 42-SDIP (Top View) P3.2 P3.3/CLO P0.0 / INT2 P0.1 / INT2 P0.2 / INT2 P0.3 / INT2 P0.4 / INT2 P0.5 / INT2 P0.6 / INT2 P0.7 / INT2 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 Figure 14-1. S3P9648 Pin Assignments (42-SDIP Package)

S3P9648 OTP S3C9644/C9648/P9648 14- 2 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P4.3/INT1 P4.2/INT1 RESET/RESETRESET P3.3/CLO P3.2 P3.1 P3.0 P2.0/INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 NC NC NC P0.0/INT2 P0.1/INT2 P0.2/INT2 P0.3/INT2 P0.4 /INT2 P0.5/INT2 P0.6/INT2 P0.7/INT2 P2.4/INT0 P2.5/INT0 P2.6/INT0/ SDAT P2.7/INT0/ SCLK V DD/ V DD V SS/ V SS X OUT/ X OUT X IN/ X IN TEST/ TEST P4.0/INT1 P4.1/INT1 S3C9648 44-QFP (Top View) Figure 14-2. S3P9648 Pin Assignments (44-QFP Package)

S3C9644/C9648/P9648 S3P9648 OTP 14- 3 Table 14-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P2.6 SDAT 9 (3) I/O Serial DATa Pin (Output when reading, Input when writing) Input and Push-pull Output Port can be assigned P2.7 SCLK 10 (4) I/O Serial CLocK Pin (Input Only Pin) TEST TEST 15 (9) I Chip Initialization and EPROM Cell Writing Power Supply Pin (Indicates OTP Mode Entering) When writing 12.5 V is applied and when reading. RESET RESET 18 (12) I 0 V: OTP write and test mode

5 V: Operating mode

V DD / V SS V DD / V SS 11 (5) /12 (6) – Logic Power Supply Pin. NOTE: ( ) means 44 QFP package. Table 14-2. Comparison of S3P9648 and S3C9644/C9648 Features Characteristic S3P9648 S3C9644/C9648 Program Memory 8-Kbyte EPROM 8-Kbyte mask ROM Operating Voltage (V DD ) 4.0 V to 5.25 V 4.0 V to 5.25 V OTP Programming Mode V DD = 5 V, V PP (RESET) = 12.5 V Pin Configuration 42 SDIP/44 QFP 42 SDIP/44 QFP EPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the V PP (RESET) pin of the S3P9648, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 14-3 below. Table 14-3. Operating Mode Selection Criteria V DD VPP ( RESET ) REG/ MEM ADDRESS (A15-A0) R/ W MODE

5 V 5 V 0 0000H 1 EPROM read

12.5 V 0 0000H 0 EPROM program

12.5 V 0 0000H 1 EPROM verify

12.5 V 1 0E3FH 0 EPROM read protection

NOTE: "0" means Low level; "1" means High level.

S3P9648 OTP S3C9644/C9648/P9648 14- 4 START Address= First Location V DD =5V, V PP =12.5V x = 0 Program One 1ms Pulse Increment X x = 10 Verify 1 Byte Last Address V DD = V PP = 5 V Compare All Byte Device Passed Increment Address Verify Byte Device Failed PASS FAIL NO FAIL YES FAIL NO Figure 14-3. OTP Programming Algorithm

S3C9644/C9648/P9648 S3P9648 OTP 14- 5 Table 14-4. D.C. Electrical Characteristics (T A = – 40 _ C to + 85 _ C, V DD = 4.0 V to 5.25 V) Parameter Symbol Conditions Min Typ Max Unit Supply Current (note) IDD1 Normal mode; – 5.5 12 mA IDD2 Idle mode; 2.2 5 IDD3 Stop mode 180 300 µA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.