S39421

S39421 SUMMIT | Alldatasheet

Document overview

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Technical content

© SUMMIT MICROELECTRONICS, Inc. 1999 2024 9.0 8/8/00 Characteristics subject to change without notice SUMMIT MICROELECTRONICS, Inc. SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131  Campbell, CA 95008  Telephone 408-378-6461  Fax 408-378-6586  www.summitmicro.com

FEATURES

• Full Voltage Control for Hot Swap Applications – Card Insertion Detection – Platform Voltage Detection – Card Voltage Sequencing – 5 Volt, 12 Volt and 3.3 Volt  12 Volt FET Enable Outputs – Allows use of Low On-resistance N-Channel FETS  Card Reset Generation Based on Out of Spec Voltages – Host Reset  Programmable Slew Rate Control [250V/Sec Default Rate]  Supports 5 Volt, 3.3 Volt and Mixed Voltage Cards  Integrated 1K Bit E 2PROM Memory  Data Download™ Mode [Simplifies Downloading of Configuration Memory into Interface ASIC or MCU] Hot Swap Voltage Controller S39421

DESCRIPTION

The S39421 is a fully integrated hot swap controller intended for use on add-in cards that may be inserted into or removed from powered-on host platforms. The S39421 performs a variety of tasks starting with the validation of proper card insertion and the presence of “in-spec” volt- ages at the host platform interface. Once power is switched on, the S39421 continues to monitor the back-end power to the add-in card and the host power supply. If either the 5V or 3.3V supplies drop below Vtrip the S39421 will immediately assert the RE- SET outputs and power-down the add-in card. In addition to the power control for the add-in card, the S39421 provides status signals that can be employed by the host and for the control of bus interface components. The on board E 2PROM can be used as configuration memory for the individual card or as general purpose memory. The proprietary DataDownload mode provides a more direct interface to the E 2PROM for simplified access by the add-in card’s controller or ASIC. FUNCTIONAL BLOCK DIAGRAM EEPROM Memory Array Slew Rate Control VGATE3 VGATE5 CS SK DI DO CARD_3V CARD_5V ISLEW PND1 PND2 DRVREN SGNL_VLD RESET RESET VCC5 VCC3 HST_PWRVSEL VCC12 DD Filter RESET Timer Sequencing Logic HST_RST 2024 ILL2.1 CARD_V_VLD ASSOCIATE MEMBER

2024 9.0 8/8/00 PIN CONFIGURATION Symbol Pin Description VCC12 1 12 Volt Input DRVREN 2 High Side Driver Enable (L) ISLEW 3 Slew Rate Control VSEL 4 Voltage Select DD 5 Data Download Enable CS 6 Microwire Chip Select SK 7 Microwire Serial Clock DI 8 Microwire Data In DO 9 Microwire Data Out PND2 10 Pin Detect 2 (Active Low) PND1 11 Pin Detect 1 (Active Low) GND 12 Ground CARD_V_VLD 13 Card Voltage Valid SGNL_VLD 14 Signals Valid (Active Low) HST_PWR 15 Host Power Up Enable HST_RST 16 Host Reset (Active Low) RESET 17 RESET(Active Low) RESET 18 RESET CARD_3V 19 Card ’s 3 Volt Monitor Input VGATE3 20 3 Volt Gate Output VCC3 21 3 Volt Input CARD_5V 22 Card ’s 5 Volt Monitor Input VGATE5 23 5 Volt Gate Output VCC5 24 5 Volt Input VCC5 VGATE5 CARD_5V VCC3 VGATE3 CARD_3V RESET RESET HST_PWR SGNL_VLD GND PND1 PND2 VCC12 DRVREN ISLEW VSEL DD CS SK DI DO HST_RST 2024 ILL1.1 CARD_V_VLD 2024 PGM T1.1 Condition Min Max Temperature -40 °C +85 °C VCC 2.7V 5.5V RECOMMENDED OPERATING CONDITIONS

2024 9.0 8/8/00 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias -55 °C to +125°C Storage Temperature -65 °C to +150°C Voltage on : DRVREN VCC12 15V VCC3 7V CARD_5V 7V CARD_3V 7V SGNL_VLD, CARD_V_VLD & RESET 12V RESET V CC +.7V All Others V CC +.7V Output Short Circuit Current 100mA Lead Solder Temperature (10 secs) 300 °C COMMENT Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. 2024 PGM T2.3 Symbol Parameter Conditions Min Typ Max Units ICC1 Power Supply Current Resets Active, VGATES Ramping .6 1 mA ICC2 Power Supply Current Quiesent - Resets released, VGATES On 250 500 µA ICC3 Power Supply Current Quiesent - EEPROM Access .8 1.5 mA VTRIP VTRIP Sense Levels VCC5 and CARD_5V 4.5 4.6 4.75 V Low to High VCC3 and CARD_3V 2.8 2.9 3.0 V High to Low VCC5 and CARD_5V 4.5 4.70 V VCC3 and CARD_3V 2.8 2.95 V VTRHST Trip Point Hysteresis 7 mV ILI Input Leakage Current 1 2 µA ILO Output Leakage Current 2 10 µA VIL Input Low Voltage -0.1 0.8 V VIH Input High Voltage 2 VCC+1 V VOL Output Low Voltage V CC = 5.0V, IOL = 2.1mA 0.4 V VOH Output High Voltage V CC = 5.0V, IOH = -400µA 2.4 V VOLRS RESET Output Low Voltage I OL = 3.2mA 0.4 V VOHRS RESET Output High Voltage I OH = -800 µA V CC -.75V V DC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions)

2024 9.0 8/8/00 Symbol Parameter Conditions Min Max Units tCSS CS Setup Time 50 ns tCSH CS Hold Time 0 ns tDIS DI Setup Time 100 ns tDIH DI Hold Time 100 ns tPD1 Output Delay to 1 250 ns tPD0 Output Delay to 0 250 ns tHZ Output Delay to Hi-Z 100 ns tEW Program/Erase Time 10 ms tCSMIN Minimum CS Low Time 250 ns tSKHI Minimum SK Low Time 250 ns tSV Output Delay to Status Valid 250 ns SK MAX Maximum Clock Frequency 1 MHz MEMORY AC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions) 2024 PGM T3.1 Symbol Parameter Notes Min Typ Max Units TSLEW Slew Rate 250 280 V/Sec THSE High Side Enable Delay Card Insertion Noise Filter 100 140 200 ms VTRHST Trip Point Hysteresis 7 mV tPURST Power-up Reset Timeout 105 130 200 ms VRVALID RESET Output Valid 1 .9 V tGLTICH Glitch Reject Pulse Width 40 ns tLVVG Loss of Voltage to VGATE off w. 100 pf load 2 µs tLVSV Loss of Voltage to Signal Valid off 5 µs tLVDE Loss of Voltage to Drive Enable off 20 µs tRPD VTRIP to RESET output Delay 5 µs tCRVG Card Removal to VGATE off w. 100 pf load 2 µs tCRSV Card Removal to Signal Valid off 5 µs tCRDE Card Removal to Drive Enable off 20 µs SEQUENCER AC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions) 2024 PGM T4.4

FIGURE 1. CARD INSERTION AND HOST RESET TIMING DIAGRAM

2024 9.0 8/8/00 PIN DESCRIPTIONS PIN NAME [CompactPCI name] (pin #) VCC12 (Pin 1): Supplies the 12 volts required for power- ing the high-side drivers. DRVREN (Pin 2): Open drain, active low output indicates the status of the 3 volt and 5 volt high side driver outputs (VGATE5 and VGATE3). This signal may also be used as a switching signal for the 12 volt supply. ISLEW (Pin 3): Diode-connected NFET input may be used to adjust the 250V/s default slew rate of the high-side driver outputs. One quarter of the current injected into this pin will be mirrored into each of the high-side driver outputs. VSEL (Pin 4): TTL level input used to determine which of the Host power supply inputs will be monitored for valid voltage and reset generation. VSEL-Voltage Host Voltage Select Monitored Low 5 Volt or Mixed-Mode High 3.3 Volt Only DD (Pin 5): A high going edge on this input will place the embedded memory into Data Download mode. This mode allows the entire contents of the E 2PROM array to be read out of the device by selecting the device (CS high) and providing clock cycles on the SK input. Data Down- load mode is exited when Chip Select is brought low. CS (Pin 6): E 2PROM memory chip select, active high. SK (Pin 7): E2PROM memory serial clock input. DI (Pin 8): E2PROM memory data input. DO (Pin 9): E2PROM memory data output. PND2 [BD_SEL2#] (Pin 10): Active low TTL level input with internal pull-up to VCC5. In conjunction with PND1, this signal indicates proper card insertion. This pin must be connected to ground on the host side of the connector. PND1 and PND2 must be placed on opposite corners of the connector and will preferably be staggered shorter than the power connector pins. Board insertion is as- sumed when PND1 and PND2 are low. PND1 [BD_SEL1#] (Pin 11): Active low TTL level input with internal pull-up to VCC5. In conjunction with PND2, this signal indicates proper card insertion. GND (Pin 12): Ground. CARD_V_VLD (pin13): CARD_V_VLD is an open drain output, indicating the card side voltages are at or above V TRIP. SGNL_VLD (Pin 14): Signals valid (SGNL_VLD) is an open drain active low signal indicating the card side power is valid and that the reset signals have been released. This signal can be used by the host as an indication that the bus interface is active and all signals are valid. HST_PWR (pin15): The host power (HST_PWR) input is an active high input. It provides the host system active control over the sequencing of the power up operation. When low, the S39421 will hold the add-in card in reset and block all power to the backend logic. When HST_PWR is high the power sequencing will begin imme- diately and the reset outputs will be driven active after t PURST . HST_RST [PCI_RST#] (Pin 16): TTL level input used as a reset input signal from the host interface. An active low level longer than 40 nsec will cause a reset sequence to be performed on the card. The power switching logic will not be affected. RESET (Pin 17): RESET is an active low open-drain output. It should be tied high through a pull-up resistor connected to V CC . RESET (Pin 18): RESET is an active high open drain (PFET) output. It should be tied low through a pull-down resistor connected to ground. CARD_3V (Pin 19): 3.3 volt card side supply input. This input is monitored for power integrity. If it falls below the 3.3V sense threshold, the PWR_VLD signal is de-as- serted and a RESET sequence initiates. VGATE3 (Pin 20): Slew rate limited high side driver output for the 3.3V external Power FET gate. VCC3 (Pin 21): 3.3 volt host side supply input. This input is monitored for power integrity. If it falls below the 3.3V sense threshold, the SGNL_VLD signal is de-asserted and the high side drivers disabled. CARD_5V (Pin 22): 5 volt card side supply input. This input is monitored for power integrity. If it falls below the 5V sense threshold and the VSEL input is low, the PWR_VLD signal is de-asserted and a RESET sequence initiates. VGATE5 (Pin 23): Slew rate limited high side driver output for the 5V external Power FET gate. VCC5 (Pin 24): Power to the S39421 and 5 volt host side supply input. This input is monitored for power integrity. If it falls below the 5V sense threshold and the VSEL input is low, the SGNL_VLD signal is de-asserted and the high side drivers disabled.

2024 9.0 8/8/00 DEVICE OPERATION Power-Up Sequence A sequencing operation is initiated by the physical inser- tion of the card into the platform’s connector. The S39421’s VCC5 pin should be connected to the early power pins of the connector. As soon as power is applied, the S39421 will drive the reset outputs active and clamp the VGATE outputs to ground. Proper card insertion is insured by detecting the presence of a low level on the pin detect (PND1, PND2) inputs, which should be located on opposite ends of the bus connector. These pin detect inputs have internal pull-up resistors and the connection on the host platform side must be connected directly to ground. [In a CompactPCI application these are the BD_SEL# signals]. The PND inputs have an internal noise filter nominally set at 150ms. Once the proper card insertion has been detected, the S39421 will check the status of the HST_PWR signal from the host. Implementation of HST_PWR is optional; e.g. it can be used to power down individual cards on the bus via software control. If it is not used by the host system the input must be held high in order for the S39421 to enable power sequencing to the card. Once these basic conditions are met the S39421 will begin the power-up portion of the sequence. First, the host platform supplies are checked for compliance. Based on the state of the VSEL input the S39421 will monitor the +5V and +3.3V supplies. If these are above the VTRIP thresholds the sequencing next begins the backend logic power-on operation. The S39421 will drive the VGATE3 and VGATE5 outputs to the 12V rail to turn on the external 3 volt and 5 volt power FETs. The slew rate of these outputs defaults to 250V/s. Different slew rates can be accommodated by either adding an additional capacitor between the FET gate and ground or by injecting current into the ISLEW input. RESET CONTROL In order to provide positive control to an add-in-card’s bakckend logic, the reset control function of the S39421 begins operation as soon as a voltage is applied to VCC5. The conditions that affect the reset outputs are the VCC5, VCC3, CARD_5V and CARD_3V input levels and the state of the HST_RST input. Assume HST_RST has been released and is pulled high. The S39421 reset ouputs will be valid as long as VCC5 is  1V. If any one of VCC5, VCC3, CARD_5V or CARD_3V input levels is below its respective Vtrip level the reset outputs and CARD_V_VLD output will be driven active. (In the case of the CARD_V_VLD output, the active condition is low but its logical true condition is a release of its open drain output pulled high by an external pull-up) As soon as the VCC5, VCC3, CARD_5V and CARD_3V inputs are above their Vtrip levels CARD_V_VLD will be released and the internal tPURST timer will be started. The reset outputs will be held active until tPURST has expired and then be released. The HST_RST input is also used to control the reset outputs. A high to low transition on HST_RST will initiate a reset cycle with a duration of tPURST. The reset outputs will remain active for a minimum period tPURST or for the duration of HST_RST active low, whichever is longer. A HST_RST activated reset will not affect the power se- quencing logic. During normal operation, the supply voltages are continu- ously monitored. If the cardside supplies fall below the VTRIP levels the reset outputs will be driven active. If the host platform supplies fall below VTRIP, the S39421 will immediately assert the reset outputs and disable the highside drivers. Power Configurations The S39421 can be used in 5V-only, 3.3V-only and mixed voltage systems. For mixed voltage systems, simply connect the appropriate bus and card power inputs as indicated. The VSEL pin should be grounded. For systems with a single power supply, connect VCC5 and VCC3 together to the platform host early power line (long pin power supply). Also connect CARD5V and CARD3V together to the cardside power output of the FET. The state of VSEL determines the reset level that will be used to signal CARD_V_VLD. For 3.3V systems, tie VSEL to the supply; for 5V systems, tie VSEL to ground.

2024 9.0 8/8/00 FIGURE 4. VCC5 ≥ 1V SHUT OFF VGTE5 VGTE3 DRVREN PWR_VLD SGNL-VLD NO YES NO YES YES NO TURN ON PWR_VLD tPURST TIMEOUT? RELEASE RESETS TURN ON NO YES PND1 PND2? VSEL HI ? ASSERT RESET OUTPUTS YESHOST 3VOLT OK? NO YES HOST 5V & 3V OK? TURN-ON VGTE5 VGTE3 DRVREN NO SGNL_VLD CARD 5V & 3V OK? START RESET TIMER 2024 ILL6.2

intended for use with industry standard microprocessors. status after a write operation. ready for the next instruction. bits and either six address or instruction bits. by selecting the device and polling the DO pin. operation will occur until CS is brought low. cleared location returns to a logical “1” state. FIGURE 5. SYCHRONOUS DATA TIMING

FIGURE 11. DATA DOWNLOADER SEQUENCE OF OPERATION the complex signals needed for the microwire interface. transition of the Chip Select input.

but this will decrease the 250V/s turn-on slew-rate. FIGURE 20. POWER-DOWN RAMP RATE CONTROL

rate increases to >50V/µs. See diagrams below. FIGURE 21. RESET CURRENT BOOST CIRCUIT

FIGURE 22. TYPICAL INTERFACE SCHEMATIC

• 10 ohm resistors must be located as close as possible to the MOSFETs.

FIGURE 23. +12V AND -12V CONTROL

• 10 ohm resistors must be located as close as possible to the MOSFETs.

2024 9.0 8/8/00 Using the S39421 as the Primary Control Circuit on a VME Live Insertion Card High availability is a key feature of many types of systems today. Whether the system is a central office switch, a private branch exchange or a server it is important the system stay up and running while adding new services (add-in cards) or replacing faulty boards. Therefore, a means for inserting and removing cards while the entire system is powered-on (live) is a necessity. Live insertion poses a number of challenges for the add- in card designer. For live insertion to be trouble free we first need to prevent damage to components on the add- in card due to improper supply sequencing. Secondly, voltage drop on the system power busses must be pre- vented in order to avoid unwanted system reset condition. Lastly, the integrity of the system’s signals needs to be maintained when additional circuitry is connected to the bus. Based upon the proposed Live Insertion System Require- ments the S39421 is an ideal candidate as the add-in card’s live insertion controller. Sequencing the Voltages The proposed live insertion specification (see references) outlines 26 operational steps during the insertion of a card. These are broken down into two major categories; the “Insertion Process” and the “Typical Board Recogni- tion Process.” The first 6 steps have to do with the insertion of the card and sequencing the discharge of any voltage potentials so that by the time the board is ready to make contact with the backplane no ESD discharges will occur. Even though the balance of the actions tend to overlap they can be viewed as two operations: the add-in card/backend logic sequencing and the backplane/add-in card interface se- quencing. Add-in Card/Backend Logic Sequencing The process of electrical insertion begins with the contact of special ground and voltage pins. These are longer than the signal and power pins and they are physically located at opposite ends of the connector. The voltage pins are labeled Vpc (pre-charge Voltage), this is the backplane’s 5 volt supply and the intent is for this voltage to be used to power the sequencing circuitry, any ASICs that inter- face to the bus and to pre-charge the ‘bus-side’ lines of the signal transceivers. The PC board should be laid out so that ground is routed to all circuits, i.e. grounds should not be linked via the PCB connector. Vpc should be tied directly to the VCC5 pin on the S39421 and the device will immediately begin driving its backend circuit control signals [SGNL_VLD, CARD_V_VLD, RESET and RESET] and it will place the voltage ramp control signals [VGATE3, VGATE5 and DRVREN] in the off state. The next step is for the controller to recognize that the board is properly seated in the connector. VME has an optional feature that lends itself ideally to this step of the operation; the ejector handles can be used to activate a switch when they are fully rotated and locked. Switch closure can be used as the PND1 and PND2 inputs on the S39421. The pull-up resistor used for this implementation must be tied to Vpc because the backend voltages will not yet have been switched on by the S39421. FIGURE 24: ILLUSTRATION OF CARD INJECTOR/EJECTOR SWITCH CIRCUIT PND1 Vpc S39421 Ejector and Switch Open PND1 Pulled High Vpc PND1 S39421 Card Seated Ejector Locked and PND1 Driven to Gnd 2024 ILL27.0

2024 9.0 8/8/00 The board’s pins should now be mated with the backplane connector which in turn will bring the host LI/I* and RESET* signals to the S39421. These signals should be tied to the device’s HST_PWR and HST_RST inputs respectively. Whenever HST_PWR is low the outputs controlling the backend power on sequencing will be inhibited; it does not impact the reset outputs or reset timer. When low, the HST_RST input will force the reset outputs active; once it is released the reset timer will be started and it will keep the reset outputs active for t PURST . At the same time the signal pins are making contact, the backend voltages are applied to the card (3.3V, 5V, +12V and -12V on short pins), but, they are blocked by FETs under the control of the S39421 (see figure 3 ). Depending upon the state of the VSEL pin, the S39421 will monitor either the bussed +5V only, the bussed +3.3V only or both the bussed +5V and +3.3V. Once the S39421 has deter- mined these supply voltages are at or above Vtrip, (and LI/ I* has released HST_PWR) it will release the VGATE outputs and effectively turn them on at a rate equivalent to 250V/second. At the same time it will force DRVREN active thus providing power to the backend circuits. FIGURE 25: GENERAL BLOCK DIAGRAM OF S39421 HOST BUS INTERFACE AND BACKEND SIGNAL INTERFACE VGATE3 VGATE5 DRVREN RESET RESET PND1 Gnd Gnd Vpc Vpc SGNL_VLD HST_RST HST_PWR CARD3V CARD5V LI/O* IL/I* RESET* Backend Power Circuits See Figure Backend Voltage to S39421 Monitor Circuits Reset Control of Backend Circuits Ejector Switch Circuit S39421 System Vcc VCC5 2024 ILL28.0

2024 9.0 8/8/00 Pre-bias The switching capacitance of the individual signal lines at the interface must be charged to the instantaneous volt- age on the corresponding bus line. These currents distort the signal that is being transmitted at that instant. To address this issue the proposed VME Live Insertion Spec states: “All VME system drivers and receivers SHALL be pre-biased to 1.7 =/-0.2 Vdc with a resistive network powered by the pre-charge +5V. . . before the board signal pins contact the backplane VME64 bus connector(s).” The ABTE logic addresses this issue head-on by provid- ing a separate VCCBias pin that is internally connected to a pre-charge resistor network. CARD REMOVAL A clean transition for card removal can be performed either by the opening of the injector/ejector levers which in turn opens the switches that force the PND inputs to ground or by the host driving LI/I* low. Both actions will tell the S39421 to disable the high side drivers and force the reset outputs active. RECAP As the board is first inserted into the backplane voltage potentials on are shunted to ground thru the use of various bleed resistors and physical contact with the chassis frame. These are make then break processes so that by the time the card is ready to make contact with the backplane connector the board is electrically isolated from the frame. The first pins of the connector to make contact with the backplane are ground and Vpc (pre-charge VCC). Vpc should be tied directly to the S39421 and the transceiver BiasVcc input. Once the S39421 detects the presence of Vpc it will begin driving the reset outputs active, shut off all the control signals to the power FETs and begin driving the LI/O* low. The injector/ejector levers will close the switches grounding the PND inputs allowing the S39421 to check the state of the VSEL pin and determine what bus voltages should be monitored. If the bus voltages are at or greater than Vtrip AND LI/I* has been released the S39421 will turn on the high side driver outputs VGATE3 and VGATE5 and the DRVREN output. The voltages to the backend logic are applied with a nominal slew rate of VGATE3 and VGATE5 set at 250V/ sec. The backend voltages should also be fed back to the S39421 and as soon as they are at or above their Vtrip level, the CARD_V_VLD will be released. If the host has released its RESET input and LI/I* input, the S39421 will release the timer for its reset circuit. After tPURST the reset outputs to the backend logic will be released and the SGNL_VLD output will be driven active [backplane signal LI/O]. This is the final step in activating a board for live insertion.

2024 9.0 8/8/00 FIGURE 27: A BUS INTERFACE SOLUTION Vpc Vcc5Gnd Gnd HST_PWR LI/I* RESET Vpc Gnd VccBias Gnd Vcc SGNL_VLD LI/O* DRVREN VGATE3 VGATE5 CARD_5V CARD_3V HST_RST OE ABTE245 S39421 To Add-in Card Back-end Voltage Ramp Circuits Add-in Card Backend Circuitry CARD-OE d-1 d-2 d-32 d-31 2024 ILL30.1

2024 9.0 8/8/00 Appendix A MOSFETs suitable for use with the S39421 Hot-Swap Controller N-Channel MOSFETs Part Number Manufacturer V(BR) DSS R DS(on) @ VGS =10V I D cont. Package IRF7603 Int. Rectifier 30V 35 milliohms max 4.5A Micro-8 IRF7413 Int. Rectifier 30V 11 milliohms max 9.2A SO-8 MTSF3N03HD Motorola 30V 40 milliohms max 3A Micro-8 MMSF7N03HD Motorola 30V 28 milliohms max 8A SO-8 MTD20N03HDL2 Motorola 30V 35 milliohms max 20A DPAK Si6434DQ Temic 30V 28 milliohms max 5.6A TSSOP-8 Si6410DQ Temic 30V 14 milliohms max 7.8A TSSOP-8 Si4412DY Temic 30V 28 milliohms max 7A SO-8 Si4416DY Temic 30V 18 milliohms max 9A SO-8 P-Channel MOSFETs Part Number Manufacturer V(BR) DSS R DS(on) @ VGS =10V I D cont. Package IRF7606 Int. Rectifier -30V 90 milliohms max 2.9A Micro-8 IRF7416 Int. Rectifier -30V 20 milliohms max 7.1A SO-8 MTSF2P03HD Motorola -30V 90 milliohms max 2.4A Micro-8 MMSF3P02HD Motorola -20V 75 milliohms max 3A SO-8 MTD20P03HDL2 Motorola -30V 99 milliohms max 19A DPAK Si6435DQ Temic -30V 90 milliohms max 4.5A TSSOP-8 Si6415DQ Temic -30V 19 milliohms max 6.5A TSSOP-8 Si4431DY Temic -30V 40 milliohms max 5.8A SO-8 Si4435DY Temic -30V 20 milliohms max 8A SO-8 References: VITA Standards Organization, November 1997, VME64x Live Insertion System Requirements Draft Standard Summit Microelectronics, Inc. S39421 Data Sheet Texas Instruments Application Note SDYA012, October 1996, Live Insertion

2024 9.0 8/8/00 24--Lead Small Outline Package (SOIC)

ORDERING INFORMATION

0.014 - 0.019 (0.356 - 0.482) 0.004 - 0.012 (0.102 - 0.305) 0.037 - 0.045 (0.940 - 1.143 0.596 - 0.612* (15.20 - 15.49) 0.394 - 0.419 (10.00 - 10.65) 0.093 - 0.104 (2.362 - 2.642) 0.016 - 0.050 (0.406 - 1.270) 0.050 (1.270) 0.009 - 0.013 (0.229 - 0.330) 0.010 - 0.029 (0.254 - 0.737) 0.291 - 0.299 (7.391 - 7.595) 24pn SOIC ILL.0 x45° 0° to 8° typ Package S = 24 Lead SOIC Base Part Number S39421 S 2024 ILL18.0

2024 9.0 8/8/00 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2000 SUMMIT Microelectronics, Inc.