S380F7

S380F7 SAMSUNG | Alldatasheet

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S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW 1-1 PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupt — Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels. S3C80F7/C80F9/C80G7/C80G9 Microcontroller The S3C80F7/C80F9/C80G7/C80G9 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung's newest CPU architecture. The S3C80F9/C80G9 is the microcontroller which has 32-Kbyte mask-programmable ROM and S3C80F7/C80G7 is the microcontroller which has 24-Kbyte mask-programmable ROM. The S3P80F9/P80G9 is the microcontroller which has 32-Kbyte one-time-programmable EPROM and S3P80F7/P80G7 is the microcontroller which has 24-Kbyte one-time-programmable EPROM. Using a proven modular design approach, Samsung engineers developed S3C80F7/C80F9/C80G7/C80G9 by integrating the following peripheral modules with the powerful SAM87 RC core: — Internal LVD circuit and 16 bit-programmable pins for external interrupts. — One 8-bit basic timer for oscillation stabilization and watchdog function (system reset). — One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. — One 8-bit counter with auto-reload function and one-shot or repeat control. The S3C80F7/C80F9/C80G7/C80G9 is a versatile general-purpose microcontroller which is especially suitable for use as remote transmitter controller. It is currently available in a 32-pin SOP, 42-pin SDIP and 44-pin QFP package.

PRODUCT OVERVIEW S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 1-2

FEATURES

32-Kbyte internal ROM (S3C80F9/C80G9) : 0000H–7FFFH 24-Kbyte internal ROM (S3C80F7/C80G7) : 0000H–5FFFH Data memory: 272-byte RAM (318 register) Instruction Set 78 instructions IDLE and STOP instructions added for power- down modes Instruction Execution Time 500 ns at 8-MHz fOSC (minimum) Interrupts 22 interrupt sources with 16 vector and 7 level. I/O Ports Three 8-bit I/O ports (P0–P2), one 8-bit output port(P4) and 6-bit port (P3) for a total of 38 bit- programmable pins.(44-QFP) Three 8-bit I/O ports (P0–P2), one 8-bit output port(P4) and 4-bit port (P3) for a total of 36 bit- programmable pins.(42-SDIP) Three 8-bit I/O ports (P0–P2) and one 2-bit I/O port (P3) for a total of 26-bit programmable pins. (32-SOP) Timers and Timer/Counters One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer (software reset) function One 8-bit timer/counter (Timer 0) with three operating modes; Interval mode, Capture and PWM mode. One 16-bit timer/counter (Timer1) with two operating modes; Interval mode and Capture. Carrier Frequency Generator One 8-bit counter with auto-reload function and one-shot or repeat control (Counter A) Back-up mode When VDD is lower than VLVD, the chip enters Back-up mode to block oscillation and reduce the current consumption. In S3C80G7/C80G9, this function is disabled when operating state is “STOP mode”. When RESET pin is lower than Input Low Voltage (VIL), the chip enters Back-up mode to block oscillation and reduce the current consumption. Low Voltage Detect Circuit Low voltage detect to get into Back-up mode. Low level detect voltage − S3C80F7/C80F9: 2.20 V (Typ) ± 200mV − S3C80G7/C80G9: 1.90 V (Typ) ± 200mV Operating Temperature Range –40 °C to + 85 °C Operating Voltage Range 1.7V to 5.0V at 4 MHz fOSC (S3C80G7/C80G9) 2.0V to 5.0V at 8 MHz fOSC (S3C80F7/C80F9) Package Type 44-pin QFP-1010B 42-pin SDIP 32-pin SOP

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW 1-3 BLOCK DIAGRAM Port 0 P0.0-0.3 (INT0-INT3) P0.4-P0.7 (INT4) I/O Port and Interrupt Control 32K-Bytes ROM 317-Bytes Register File SAM87RC CPU Port 1 P2.0-2.3 (INT5-INT8) Port 4 P4.0-4.7 LVD P1.0-P1.7 TEST RESET MAIN OSC 8-Bit Basic Timer 8-Bit Timer/ Counter 16-Bit Timer/ Counter VDD Carrier Registor (Counter A) XOUT XIN Port 3 Port 2 P2.4-2.7 (INT9) P3.0-T0PWM/ T0CAP/(T1CAP) P3.1-REM/(T0CK) P3.2/(T0CK) P3.3/(T1CAP) P3.4-3.5 Figure 1-1. Block Diagram

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 1-4 PIN ASSIGNMENTS P4.2 P4.1 P4.0 P2.0/INT5 P2.1/INT6 P2.2/INT7 P2.3/INT8 P2.4/INT9 P3.0/T0PWM/T0CAP/SDAT R3.1/REM/SCLK VDD VSS XOUT XIN TEST P2.5/INT9 P2.6/INT9 RESET P2.7/INT9 P1.0 P3.2/T0CK P4.3 P0.7/INT4 P0.6/INT4 P0.5/INT4 P0.4/INT4 P0.3/INT3 P0.2/INT2 P0.1/INT1 P0.0/INT0 P4.4 P4.5 P4.6 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P4.7 P3.3/T1CAP S3C80F7/C80F9 /C80G7/C80G9 (Top View) 42-SDIP Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW 1-5 P0.3/INT3 P0.2/INT2 P0.1/INT1 P0.0/INT0 P4.4 P4.5 P4.6 P1.7 P1.6 P1.5 P1.4 P0.4/INT4 P0.5/INT4 P0.6/INT4 P0.7/INT4 P4.3 P4.2 P4.1 P4.0 P2.0/INT5 P2.1/INT6 P2.2/INT7 S3C80F7/C80F9 /C80G7/C80G9 (Top View) (44-QFP) P1.3 P1.2 P1.1 P4.7 P3.3/T1CAP P3.2/T0CK P1.0 P2.7/INT9 P3.5 P3.4 RESET P2.3/INT8 P2.4/INT9 P3.0/T0PWM/T0CAP/SDAT P3.1/REM/SCLK VDD VSS XOUT XIN TEST P2.5/INT9 P2.6/INT9 Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 1-6 VSS XIN XOUT TEST P2.5/INT9 P2.6/INT9 RESET P2.7/INT9 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 S3C80F7/C80F9 /C80G7/C80G9 (Top View) 32-SOP VDD P3.1/REM/T0CK/SCLK P3.0/T0PWM/T0CAP/T1CAP/SDAT P2.4/INT9 P2.3/INT8 P2.2/INT7 P2.1/INT6 P2.0/INT5 P0.7/INT4 P0.6/INT4 P0.5/INT4 P0.4/INT4 P0.3/INT3 P0.2/INT2 P0.1/INT1 P0.0/INT0 Figure 1-4. Pin Assignment Diagram (32-Pin SOP Package)

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW 1-7 Table 1-1. Pin Descriptions of 44-QFP and 42-SDIP Pin Names Pin Type Pin Description Circuit Type

42 Pin

No.

44 Pin

No. Shared Functions P0.0–P0.7 I/O I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED & R circuit built in P0 for STOP releasing. 34–41 30–37 Ext. INT (INT0 - 4) P1.0–P1.7 I/O I/O port with bit-programmable pins. Configurable to input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type. 24–30 20–26 P2.0–P2.3 P2.4–P2.7 I/O I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED & R circuit built in P2 for STOP releasing. 4–8, 16, 17 42–44 1,2, 10,11, Ext. INT (INT5–9) P3.0 P3.1 I/O 2-bit I/O port with bit-programmable pins. Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with pull-up resistors can be assigned by software. The two port 3 pins have high current drive capability 9–10 3–4 T0PWM/ T0CAP REM P3.2–P3.3 I C-MOS Input port with pull-up resistors (T0CK) (T1CAP) P3.4–P3.5 O Open drain output port for high current drive None 13–14 P4.0–P4.7 O 8- bit-programmable output pins. Configurable to open drain output port or push-pull output port. 1–3 42,23 31-33 41–38 27–29 XIN, XOUT System clock input and output pins 13,14 7,8 RESET I System reset signal input pin and back- up mode input. TEST I Test signal input pin (for factory use only; must be connected to VSS.) VDD Power supply input pin VSS Ground pin

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 1-8 Table 1-2. Pin Descriptions of 32-SOP Pin Names Pin Type Pin Description Circuit Type

32 Pin

No. Shared Functions P0.0–P0.7 I/O I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors are assignable by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/ disable, and interrupt pending control. SED & R circuit built in P0 for STOP releasing. 17–24 Ext. INT P1.0–P1.7 I/O I/O port with bit-programmable pins. Configurable to input mode or output mode. Pin circuits are either push-pull or n-channel open-drain type. 9–16 P2.0–P2.3 P2.4–P2.7 I/O I/O port with bit-programmable pins. Configurable to input or push-pull output mode. Pull-up resistors can be assigned by software. Pins can be assigned individually as external interrupt inputs with noise filters, interrupt enable/disable, and interrupt pending control. SED & R circuit built in P2 for STOP releasing. 25–28 29,5, 6,8 Ext. INT P3.0 P3.1 I/O 2-bit I/O port with bit-programmable pins. Configurable to input mode, push-pull output mode, or n-channel open-drain output mode. Input mode with pull-up resistors can be assigned by software. The two port 3 pins have high current drive capability. 30,31 T0PWM/ T0CAP/T1CAP REM/T0CK XIN, XOUT System clock input and output pins 2,3 RESET I System reset signal input pin and back-up mode input. TEST I Test signal input pin (for factory use only; must be connected to VSS). VDD Power supply input pin VSS Ground pin

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW 1-9 PIN CIRCUITS VDD Pull-up Resistor VDD VSS Noise Filter Input/ Output Stop release Pull-up Enable Data Output Disable External Interrupt Stop Figure 1-5. Pin Circuit Type 1 (Port 0 and Port2)

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 1-10 PIN CIRCUITS (Continued) VDD Pull-up Resistor VDD VSS Noise Filter Input/ Output Pull-up Enable Data Output Disable Normal Input Open-Drain Figure 1-6. Pin Circuit Type 2 (Port 1)

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) PRODUCT OVERVIEW 1-11 PIN CIRCUITS (Continued) VDD Pull-up Enable VDD P3.0/T0PWM T0CAP/(T1CAP) Pull-up Resistor Open-Drain Port 3.0 Data VSS P3.0 Input M U X P3CON.2 Data Output Disable T0CAP/(T1CAP) T0_PWM Noise filter M U X P3CON.2,6,7 Figure 1-7. Pin Circuit Type 3 (P3.0)

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA 14-1 ELECTRICAL DATA 1 (S3C80F7/C80F9) OVERVIEW In this section, S3C80F7/C80F9 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by an external interrupt — Stop mode release timing when initiated by a Reset — I/O capacitance — A.C. electrical characteristics — Input timing for external interrupts — Input timing for RESET — Oscillation characteristics — Oscillation stabilization time

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 14-2 Table 14-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating Unit Supply voltage VDD – 0.3 to + 6.5 V Input voltage VIN – 0.3 to VDD + 0.3 V Output voltage VO All output pins – 0.3 to VDD + 0.3 V Output current High IOH One I/O pin active – 18 mA All I/O pins active – 60 Output current Low IOL One I/O pin active + 30 mA Total pin current for ports 0, 1, and 2 + 100 Total pin current for port 3 + 40 Operating temperature TA – 40 to + 85 Storage temperature TSTG – 65 to + 150 Table 14-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.0 V) Parameter Symbol Conditions Min Typ Max Unit Operating Voltage VDD FOSC = 8 MHz (Instruction clock = 2 MHz) 2.0 5.0 V Input High voltage VIH1 All input pins except VIH2 and VIH3

0.8 VDD

V VIH2 RESET

0.85 VDD

VDD – 0.3 VDD Input Low voltage VIL1 All input pins except VIL2 and VIL3

0.2 VDD

V VIL2 RESET 0.3 Output High voltage VOH1 VDD = 2.4 V IOH = – 6 mA Port 3.1 only, TA = 25°C VDD – 0.7 V VOH2 VDD = 2.4 V, IOH = – 2.2mA P3.0, P2.0–2.3 TA = 25°C VDD – 0.7

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA 14-3 Table 14-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.0 V) Parameter Symbol Conditions Min Typ Max Unit Output High voltage VOH3 VDD = 2.4 V,IOH = – 1 mA Port0, Port1, P2.4-2.7 and Port4 TA = 25°C VDD – 1.0 V Output Low voltage VOL1 VDD = 2.4 V, IOL = 12 mA, port 3.1 only, TA = 25°C 0.4 0.5 V VOL2 VDD = 2.4 V, IOL = 5 mA TA = 25°C 0.4 0.5 VOL3 IOL = 2mA Port 0, Port1, P2.4-2.7 and Port4 TA = 25°C 0.4 Input High leakage current ILIH1 VIN = VDD All input pins except XIN and XOUT µA ILIH2 VIN = VDD, XIN and XOUT Input Low leakage current ILIL1 VIN = 0 V All input pins except XIN, XOUT, and RESET – 1 µA ILIL2 VIN = 0 V XIN and XOUT – 20 Output High leakage current ILOH VOUT = VDD All output pins µA Output Low leakage current ILOL VOUT = 0 V All output pins – 1 µA Pull-up resistors RL1 VIN = 0 V, VDD = 2.4 V TA = 25°C, Ports 0–2, P3.2–3.3 kΩ

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 14-4 Table 14-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.0 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (note) IDD1 Operating mode VDD = 5.0 V

8 MHz crystal

4 MHz crystal

4.5 IDD2 Idle mode VDD = 5.0 V 1.8 3.5 1.6 3.0 IDD3 Stop mode; VDD = 5.0 V uA VDD = 3.6 V VDD = 2.4 V 4.5 VDD = 0.7 V 1.5 NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. Table 14-3. Characteristics of Low Voltage Detect circuit Parameter Symbol Conditions Min Typ Max Unit Hysteresys Voltage of LVD (Slew Rate of LVD) 100 300 mV Low level detect voltage VLVD 2.00 2.20 2.40 V Table 14-4. Data Retention Supply Voltage in Stop Mode Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR 1.0 5.0 V Data retention supply current IDDDR VDDDR = 1.0 V Stop mode µA

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 14-6 Normal Operating Mode Stop Mode Oscillation Stabilization Time Reset Occur Execution of STOP Instrction VDD NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. VLVD Data Retention Time VDDDR Back-up Mode tWAIT Figure 14-3. Stop Mode Release Timing When Initiated by a LVD Table 14-5. Input/Output Capacitance (TA = – 40 °C to + 85 °C , VDD = 0 V) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN f = 1 MHz; unmeasured pins are connected to VSS pF Output capacitance COUT I/O capacitance CIO Table 14-6. A.C. Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit Interrupt input, High, Low width tINTH, tINTL VDD = 5.0 V 200 300 ns RESET input Low width tRSL Input VDD = 5.0 V 1000

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA 14-7 tINTH tINTL NOTE: The unit tCPU means one CPU clock period. Figure 14-4. Input Timing for External Interrupts (Port 0, P2.3–P2.0) Normal Operating Mode Oscillation Stabilization Time Reset Occur VDD NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. RESET tWAIT Normal Operating Mode Back-up Mode (Stop Mode) Figure 14-5. Input Timing for RESET

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 14-8 Table 14-7. Oscillation Characteristics Oscillator Clock Circuit Conditions Min Typ Max Unit Crystal XIN XOUT CPU clock oscillation frequency MHz Ceramic XIN XOUT CPU clock oscillation frequency MHz External clock XIN XOUT S3C80F9 External Clock Open Pin XIN input frequency MHz Table 14-8. Oscillation Stabilization Time (TA = – 40 °C + 85 °C, VDD = 4.5 V to 5.0 V) Oscillator Test Condition Min Typ Max Unit Main crystal fOSC > 400 kHz ms Main ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. ms External clock (main system) XIN input High and Low width (tXH, tXL) 500 ns Oscillator stabilization wait time tWAIT when released by a reset (1) 16/fOSC ms tWAIT when released by an interrupt (2) ms NOTES: fOSC is the oscillator frequency. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON.

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA 14-9 Instruction Clock 100 kHz fOSC (Main Oscillator Frequency) Supply Voltage (V) Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, or 16) A: 2.0 V, 8 MHz 250 kHz 500 kHz

1.0 MHz

1.25 MHz

2 MHz

A

8 MHz

6 MHz

4 MHz

Figure 14-6. Operating Voltage Range of S3C80F9

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA 15-1 ELECTRICAL DATA 2 (S3C80G7/C80G9) OVERVIEW In this section, S3C80G7/C80G9 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by an external interrupt — Stop mode release timing when initiated by a Reset — I/O capacitance — A.C. electrical characteristics — Input timing for external interrupts — Input timing for RESET — Oscillation characteristics — Oscillation stabilization time

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 15-2 Table 15-1. Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Rating Unit Supply voltage VDD – 0.3 to + 6.5 V Input voltage VIN – 0.3 to VDD + 0.3 V Output voltage VO All output pins – 0.3 to VDD + 0.3 V Output current High IOH One I/O pin active – 18 mA All I/O pins active – 60 Output current Low IOL One I/O pin active + 30 mA Total pin current for ports 0, 1, and 2 + 100 Total pin current for port 3 + 40 Operating temperature TA – 40 to + 85 Storage temperature TSTG – 65 to + 150 Table 15-2. D.C. Electrical Characteristics (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.0 V) Parameter Symbol Conditions Min Typ Max Unit Operating Voltage VDD FOSC = 4 MHz (Instruction clock = 1 MHz) 1.7 5.0 V Input High voltage VIH1 All input pins except VIH2 and VIH3 V VIH2 RESET VDD – 0.3 VDD Input Low voltage VIL1 All input pins except VIL2 and VIL3 V VIL2 RESET 0.3 Output High voltage VOH1 VDD = 2.4 V IOH = – 6 mA Port 3.1 only, TA = 25°C VDD – 0.7 V VOH2 VDD = 2.4 V, IOH = – 2.2mA P3.0, P2.0–2.3 TA = 25°C VDD– 0.7

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA 15-3 Table 15-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.0 V) Parameter Symbol Conditions Min Typ Max Unit Output High voltage VOH3 VDD = 2.4 V,IOH = – 1 mA Port0, Port1, P2.4–2.7 and Port4 TA = 25°C VDD – 1.0 V Output Low voltage VOL1 VDD = 2.4 V, IOL = 12 mA, port 3.1 only, TA = 25°C 0.4 0.5 V VOL2 VDD = 2.4 V, IOL = 5 mA TA = 25°C 0.4 0.5 VOL3 IOL = 2mA Port 0, Port1, P2.4–2.7 and Port4 TA = 25°C 0.4 Input High leakage current ILIH1 VIN = VDD All input pins except XIN and XOUT µA ILIH2 VIN = VDD, XIN and XOUT Input Low leakage current ILIL1 VIN = 0 V All input pins except XIN, XOUT, and RESET – 1 µA ILIL2 VIN = 0 V XIN and XOUT – 20 Output High leakage current ILOH VOUT = VDD All output pins µA Output Low leakage current ILOL VOUT = 0 V All output pins – 1 µA Pull-up resistors RL1 VIN = 0 V, VDD = 2.4 V TA = 25°C, Ports 0–2, P3.2–3.3 kΩ

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 15-4 Table 15-2. D.C. Electrical Characteristics (Continued) (TA = – 40 °C to + 85 °C, VDD = 2.0 V to 5.0 V) Parameter Symbol Conditions Min Typ Max Unit Supply current (note) IDD1 Operating mode VDD = 5.0 V 4.5 mA IDD2 Idle mode VDD = 5.0 V 1.6 3.0 IDD3 Stop mode; VDD = 5.0 V uA NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads. Table 15-3. Characteristics of Low Voltage Detect circuit Parameter Symbol Conditions Min Typ Max Unit Hysteresys Voltage of LVD (Slew Rate of LVD) 100 300 mV Low level detect voltage VLVD 1.70 1.90 2.10 V Table 15-4. Data Retention Supply Voltage in Stop Mode Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR 1.0 5.0 V Data retention supply current IDDDR VDDDR = 1.0 V Stop mode µA

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 15-6 Table 15-5. Input/Output Capacitance (TA = – 40 °C to + 85 °C , VDD = 0 V) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN f = 1 MHz; unmeasured pins are connected to VSS pF Output capacitance COUT I/O capacitance CIO Table 15-6. A.C. Electrical Characteristics Parameter Symbol Conditions Min Typ Max Unit Interrupt input, High, Low width tINTH, tINTL VDD = 5.0 V 200 300 ns RESET input Low width tRSL Input VDD = 5.0 V 1000

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA 15-7 tINTH tINTL NOTE: The unit tCPU means one CPU clock period. Figure 15-3. Input Timing for External Interrupts (Port 0, P2.3–P2.0) Normal Operating Mode Oscillation Stabilization Time Reset Occur VDD NOTE: tWAIT is the same as 4096 x 16 x 1/fOSC. RESET tWAIT Normal Operating Mode Back-up Mode (Stop Mode) Figure 15-4. Input Timing for RESET

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 15-8 Table 15-7. Oscillation Characteristics Oscillator Clock Circuit Conditions Min Typ Max Unit Crystal XIN XOUT CPU clock oscillation frequency MHz Ceramic XIN XOUT CPU clock oscillation frequency MHz External clock XIN XOUT S3C80G9 External Clock Open Pin XIN input frequency MHz Table 15-8. Oscillation Stabilization Time (TA = – 40 °C + 85 °C, VDD = 4.5 V to 5.0 V) Oscillator Test Condition Min Typ Max Unit Main crystal fOSC > 400 kHz ms Main ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. ms External clock (main system) XIN input High and Low width (tXH, tXL) 500 ns Oscillator stabilization wait time tWAIT when released by a reset (1) 16/fOSC ms tWAIT when released by an interrupt (2) ms NOTES: fOSC is the oscillator frequency. The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON.

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) ELECTRICAL DATA 15-9 Instruction Clock 100 kHz fOSC (Main Oscillator Frequency) Supply Voltage (V) Instruction Clock = 1/6n x oscillator frequency (n = 1, 2, 8, or 16) A: 1.7 V, 4 MHz 250 kHz 500 kHz A Figure 15-6. Operating Voltage Range of S3C80G9

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) MECHANICAL DATA 16-1 MECHANICAL DATA OVERVIEW The S3C80F7/C80F9/C80G7/C80G9 microcontroller is currently available in a 32-pin SOP, 42-pin SDIP and 44- pin QFP package. 32-SOP-450A

20.30 MAX

19.90 ± 0.20 #17 #16 0-8 0.25 + 0.10 - 0.05 11.43 8.34 ± 0.20 0.90 ± 0.20

0.05 MIN

2.00 ± 0.10

2.20 MAX

0.10 MAX

1.27 NOTE: Dimensions are in millimeters. 12.00 ± 0.30 #32 (0.43) 0.40 ± 0.10 Figure 16-1. 32-Pin SOP Package Dimension

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) 16-2 NOTE: Dimensions are in millimeters.

39.50 MAX

39.10 ± 0.20 0.50 ± 0.10 1.78 (1.77)

0.51 MIN

3.30 ± 0.30 3.50 ± 0.20

5.08 MAX

1.00 ± 0.10 0.25 + 0.10 - 0.05 15.24 14.00 ± 0.20 #42 #22 #21 Figure 16-2. 42-Pin SDIP Package Dimension

S3C80F7/C80F9/C80G7/C80G9 (KS88C01524/C01532/C01624/C01632) MECHANICAL DATA 16-3 44-QFP-1010B #44 NOTE: Dimensions are in millimeters. 10.00 ± 0.20 13.20 ± 0.30 10.00 ± 0.20 13.20 ± 0.30 0.35 + 0.10 - 0.05 0.80 0.80 ± 0.20 2.05 ± 0.10

2.30 MAX

0.15 + 0.10 - 0.05 0-8

0.15 MAX

(1.00) Figure 16-3. 44-Pin SQFP Package Dimension