S3031B AMCC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 26
Technical content
E4/STM-1/OC-3 ATM TRANSCEIVER S3031B 1August 19, 1999 / Revision D E4/STM-1/OC-3 ATM TRANSCEIVER S3031B
FEATURES
- Complies with Bellcore and ITU-T specifications
- On-chip high-frequency PLLs for clock generation and clock recovery
- On-chip analog circuitry for transformer driver and equalization
- Supports 139.264 Mbps (E4) and 155.52 Mbps (OC-3) transmission rates
- Supports 139.264 Mbps and 155.52 Mbps Coded Mark Inversion (CMI) interfaces
- TTL Reference frequencies of 19.44 and 38.88 MHz (OC-3) or 17.408 and 34.816 MHz (E4)
- Interface to both PECL and TTL logic
- Lock detect on clock recovery function — monitors run length and frequency
- Serial and 4 bit (nibble) system interfaces
- Low jitter PECL interface
- +5V operation
- 100 PQFP/TEP package
- Supports both electrical and optical interfaces
APPLICATIONS
- ATM over SONET/SDH
- OC-3/STM-1 or E4-based transmission systems
- OC-3/STM-1 or E4 modules
- OC-3/STM-1 or E4 test equipment
- Section repeaters
- Add Drop Multiplexers (ADM)
- Broadband cross-connects
- Fiber optic terminators
- Fiber optic test equipment Figure 1a. Electrical Interface Figure 1b. Optical Interface E4/STM-1/OC-3 OVERHEAD PROCESSOR OSC S3031B XCVR XFMR 139.264/155.52 Mbps NRZ 139.264/155.52 Mbps NRZ 139.264/155.52 Mbps CMI 139.264/155.52 Mbps CMI COAX 17.408/19.44 MHz XFMR COAX DEVICE SPECIFICATION GENERAL DESCRIPTION The S3031B transceiver chip is a fully integrated CMI encoding transmitter and CMI decoding receiver. The chip derives high speed timing and data signals for SONET/SDH or PDH-based equipment. The circuit is implemented using AMCC’s proven Phase Locked Loop (PLL) technology. Figures 1a and 1b show typical network applications. The S3031B has two independent VCOs which are synchronized to the local NRZ transmitted data and the received CMI data respectively. The chip can be used with either a 19.44 MHz or a 38.88 MHz reference clock when operated in the SONET/SDH OC-3 mode. In E4 mode the chip can be operated with a 17.408 MHz or a
34.816 MHz reference in support of existing system
clocking schemes. On-chip coded-mark-inversion (CMI) encoding and decoding is provided for 139.264 Mbps and 155.52 Mbps interfaces. The low jitter PECL interface for the serial data inputs and the PECL nibble clock interface guarantee com- pliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3031B is packaged in a 0.65 mm pitch 100-pin PQFP/TEP. The S3031B provides the major active components on- chip for a coaxial cable interface, including analog transformer driver circuitry and equalization interface circuitry. Discrete controls permit separate selection of CMI or NRZ operation and analog (coaxial copper) or PECL (optical module) media interfaces. Both line loopback and diagnostic local loopback operation are supported. E4/STM-1/OC-3 OVERHEAD PROCESSOR OSC S3031B XCVR 139.264/155.52 Mbps NRZ 139.264/155.52 Mbps NRZ 139.264/155.52 Mbps 139.264/155.52 Mbps 17.408/19.44 MHz OTX ORX
of transmission rates and applications.
- Photonic
- Section
- Line
- Path Figure 2 shows the layers and their functions. Each of the layers has overhead bandwidth dedicated to administration and maintenance. The photonic layer simply handles the conversion from electrical to opti- cal and back with no overhead. It is responsible for transmitting the electrical signals in optical form over the physical media. The section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. Key functions of this layer are framing, scrambling, and error moni- toring. The line layer is responsible for the reliable transmission of the path layer information stream carrying voice, data, and video signals. Its main func- tions are synchronization, multiplexing, and reliable transport. The path layer is responsible for the actual transport of services at the appropriate signaling rates. Data Rates and Signal Hierarchy Table 1 contains the data rates and signal designa- tions of the SONET hierarchy. The lowest level is the basic SONET signal referred to as the synchronous transport signal level-1 (STS-1). An STS- N signal is made up of N byte-interleaved STS-1 signals. The optical counterpart of each STS-N signal is an optical carrier level-N signal (OC-N ). The S3031B supports OC-3 rates (155.52 Mbps). Frame and Byte Boundary Detection The SONET/SDH fundamental frame format for STS-3 consists of nine transport overhead bytes followed by Synchronous Payload Envelope (SPE) bytes. This pat- tern of 9 overhead and 261 SPE bytes is repeated nine times in each frame. Frame and byte boundaries are detected using the A1 and A2 bytes found in the transport overhead. (See Figure 3.) For more details on SONET operations, refer to the Bellcore SONET standard document. Elec. ITU-T Optical Data Rate (Mbps) STS-1 OC-1 51.84 STS-3 STM-1 OC-3 155.52 STS-12 STM-4 OC-12 622.08 STS-24 OC-24 1244.16 STS-48 STM-16 OC-48 2488.32
Table 1. SONET Signal Hierarchy
9 Columns 261 Columns
Figure 3. STS-3/OC Frame FormatFigure 2. SONET Structure
576 Kbps
192 Kbps
E4/STM-1/OC-3 ATM TRANSCEIVER S3031B 3August 19, 1999 / Revision D S3031B OVERVIEW The S3031B transceiver can be used to implement the front end of STS-3, OC-3 or E4 equipment. The block diagram in Figure 9 shows the basic operation of the chip. When the S3031B is operating in the nibble parallel mode, the transmitter VCO is synchronized to the 38.88 MHz nibble clock as both the reference clock and the data transfer clock. If the serial input is selected as the transmitter data source the VCO will be synchronized directly to the incoming data. Serial operation of the S3031B transmitter section is possible with either the 38.88 MHz or 19.44 MHz reference oscillator. In the absence of incoming serial data the transmitter section will operate as a clock synthesizer. The receiver section performs clock recovery by synchronizing its on-chip VCO directly to the incoming data stream. In E4 operation, the 34.816 MHz REFCLK is used as the nibble clock. Thus in Nibble parallel mode, the S3031B transmitter section supports unscrambled E4 operation. If serial mode is selected, the NRZ E4 data must be scrambled to allow the PLL to lock onto the data transi- tions. The S3031B provides a PECL output for an optical interface and two transformer driver outputs for an electrical interface. One of these drivers is a monitor output. The S3031B provides a PECL input for an optical interface and an analog input for an electrical interface. The transformer driver outputs are separately enabled. Status outputs detect the disabled, stuck at 1, stuck at 0, and non-CMI states to qualify the transformer driver outputs. The CMI outputs, analog equalizer input section, and PLL sections are independently powered for isolation and for power savings when the device is used in single function applications. S3031B TRANSMITTER ARCHITECTURE/FUNCTIONAL DESIGN Transmitter Operation The S3031B chip’s transmitter section performs the last stages of digital processing of a transmit SONET STS-3 or ITU-T E4 serial or 4-bit nibble parallel data stream. Clock Recovery If the serial input data has been selected, and serial data is present at the TSDATIP/N inputs, the clock is recovered from the serial data stream at 139.264 MHz or 155.52 MHz and synthesized to 278.528 MHz or 311.04 MHz to CMI encode the incoming data. In clock recovery mode, the transmitter PLL continues to monitor the reference clock with respect to the VCO and the activity of the serial data input. The transmitter PLL will re-lock to the reference clock under the follow- ing conditions: 1. If the serial data inputs contains insufficient transition density (run length greater than 100 to 200 bit times). 2. If the VCO drifts away from the local reference clock by more than 1000 ppm. If either XFRMENA or XFRMENB are enabled (logic Low) the density or frequency error defined above will set the appropriate status (XFRMSTATA and/or XFRMSTATB) to the low or fault state. The selected drive status bits will return to the High or clear state and the PLL will again lock to the data if the serial data contains sufficient transition density (less than 100 to 200 bit times between rising edges), and the serial clock is within 250 ppm of the reference clock determined frequency. Optical and Electrical Interfaces The digital data outputs (TSDATOP/N) are the PECL outputs for an optical interface and are to be con- nected to an electrical to optical converter, as shown in Figure 17. This data is also routed to two on-chip transformer drivers and sent out on XFRMDRVA and XFRMDRVB to drive the transformers of the electri- cal interface, as shown in Figure 19. These outputs are shut off when the reset is active, XFRMEN is active, or when the chip is in NRZ mode and the data inputs are in the logic zero state. The electrical characteristics for the transformer drivers are shown in Table 9.
Figure 9. S3031B OC-3/STM-1/E4 Transceiver
E4/STM-1/OC-3 ATM TRANSCEIVER S3031B 7August 19, 1999 / Revision D S3031B RECEIVER OPERATION The S3031B transceiver chip provides the first stage of the digital process of a receive SONET STS-3 or ITU- T E4 serial bit stream. A Coded Mark Inversion (CMI) decoder can be enabled for decoding STS-3 electrical and E4 signal. The recovered and decoded signal is output as both retimed bit-serial 155.52 or 139.264 Mbps NRZ data and as a 38.88 or 34.816 Mbyte/s 4-bit nibble parallel outputs. Clock recovery is performed on the incoming scrambled NRZ or CMI-coded data stream. A reference clock is required for phase locked loop start-up and proper operation under loss of signal conditions. An integral prescaler and phase locked loop circuit is used to multiply this reference frequency to the nominal bit rate. Clock Recovery The clock recovery function, as shown in the block diagram in Figure 9, generates a clock that is fre- quency matched to the incoming data baud rate at the RSDATIP/N differential inputs. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency discriminator. Out- put pulses from the discriminator indicate the required direction of phase corrections. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Con- trolled Oscillator (VCO), which generates the recov- ered clock. Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) to which the PLL locks when data is lost. When the Test Clock Enable (TSTCLKEN) input is set high, the clock recovery block is disabled. The Test Clock (TESTCLK) is used as the bit rate clock input in place of the recovered clock. This feature is used for functional testing of the device. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET or E4 data signal. This transfer function yields a typical capture time of 16 µs for random incoming NRZ data. The total loop dynamics of the clock recovery PLL yield a jitter tolerance which exceeds the minimum tolerance proposed for OC-3/STM-1/E4 equipment by the Bellcore and ITU-T documents, shown in Figure 12. Optical and Electrical Interfaces The digital data inputs (RSDATIP/N) are the PECL inputs from an optical to electrical converter, as shown in Figure 16. The data input for the coaxial interface is ANDATIN, which is the serial data input from the equal- izer circuit and should be connected as shown in Figure 19. The EQUALSEL input is used to select either RSDATIP/N or ANDATIN. CMI Decoding The CMI decoder block on the S3031B accepts serial data from the TSDATIP/N input at the rate of 139.264 or 155.52 Mbps. The incoming CMI data, which has tran- sitions that represent this data rate (the clock associ- ated with this data would be running at twice this rate), is then decoded from CMI to NRZ format. Loss of Signal The clock recovery circuit monitors the incoming data stream for loss of signal. If the incoming encoded data stream has had no transitions continuously for 100 to 200 recovered clock cycles, loss of signal is declared and the PLL will switch from locking onto the incoming data to locking onto the reference clock per the require- ments of G.775. Alternatively, the loss-of signal (LOSIN) input can force a loss-of-signal condition. This signal is compared internally against the LOSREF input refer- ence voltage. This input can be set to meet the condi- tions shown in Figure 10. If the zero to peak signal level drops below the LOSREF/20 voltage level for more than 100 to 200 bit intervals, a loss of signal condition will be indicated on the LOSOUT pin and the PLL will change its reference from the serial data stream to the reference clock. When the peak input voltage is greater than LOSREF/10, the loss of signal condition will be deasserted and the PLL will recover the clock from the serial data inputs. In clock recovery mode, the receiver PLL also moni- tors the reference clock with respect to the VCO. If the VCO drifts away from the local reference clock by more than 1000 ppm the PLL will re-lock to the refer- ence clock and the LOSOUT will be set to the active low condition. The LOSOUT will return to the High or inactive state and the PLL will again lock to the data if the serial data contains sufficient transition density (less than 100 to 200 bit times between rising edges), and the serial clock is within 250 ppm of the reference clock deter- mined frequency.
Table 2. Transmitter Input Pin Assignment and Description
Table 3. Transmitter Output Pin Assignment and Description
Table 4. Receiver Input Pin Assignment and Description
Table 4. Receiver Input Pin Assignment and Description (Continued) 15ebdluohssrotsiserehT.cirtceleidR7X,ecnarelot%01 Ω eeS.
Table 5. Receiver Output Pin Assignment and Description
Table 6. Common Pin Assignment and Description
Table 6. Common Pin Assignment and Description (Continued)
Figure 13. 100-Pin PQFP/TEP Package
- Max ambient temperature permitted in still air to maintain Tj < 130˚C.
Figure 14. Heat Sink Drawing DW0045-28
Figure 15. S3031B Pinout
100 PQFP/TEP
Table 7. S3031B Clock Recovery Mode Performance Specifications Table 9. Electrical Characteristics for Transformer Driver1
- For output waveform characteristics, see Figures 7 and 8. The S3031B is compliant with these masks on an individual waveform basis. The
total cycle-to-cycle wideband jitter is less than 350 ps peak-to-peak. Total transmitted jitter per ITU G.825 is less than 0.075 UI peak-to-peak. Table 8. S3031B Clock Synthesis Mode Performance Specifications
- Specification based on design values. Not tested.
Table 10. Electrical Characteristics for ANDATIN Input
- Signal is undefined if left floating.
Table 11. Electrical Characteristics for LOSIN Input
- LOS detected and LOS cleared will maintain 2:1 ratio ±5%.
Table 12. Typical Operating Conditions
Table 13. Electrical Characteristics for BUFIN, BUFOUT Table 14. Absolute Maximum Ratings Table 15. Recommended Operating Conditions
- These input levels provide zero noise immunity and should only be tested in a static, noise-free environment.
Table 16. TTL Input/Output DC Characteristics Table 17. PECL Input/Output DC Characteristics1,2
- These conditions will be met with no airflow.
- When not used, tie the positive differential PECL pin to VCC and the negative
differential ECL pin to ground via a 3.9 kΩ resistor.
Figure 19. S3031B Transformer Input and Output Application
19.44 MHz
155.52 MHZ
Figure 20. OC-3 Application Figure 21. STM-1 CMI, E4 Application
S3031B E4/STM-1/OC-3 ATM TRANSCEIVER August 19, 1999 / Revision D Processor Interface PMC PM5345 SUNI Saturn User Network Interface PMC PM5346 SUNI-Lite Saturn User Network Interface PMC PM5347 SUNI-Plus Saturn User Network Interface IGT WAC-013-A SONET LAN ATM Processor TRANSWITCH SYN155 155 Mbps Synchronizer TI SABRE TDC 1500 155 Mbps Processor Electrical Interface Motorola MMBD352 Dual Diode Mini-Circuits MCL TXI-R5 Wideband RF Transformer (Surface Mount) Mini-Circuits MCL TO-75 Wideband RF Transformer (Through-Hole) Optical Interface HP HFBR-520x 155 Mbps Fiber Optic Transceiver CTS ODL-1408X 155 Mbps Fiber Optic Transceiver Sumitomo SDM4123-XC 155 Mbps Fiber Optic Transceiver AMP 269039-1 155 Mbps Fiber Optic Transceiver Table 18. Suggested Interface Devices
Ordering Information
GRADE RECEIVER PACKAGE OPTION 3031S – industrial X XXXX X / XX Grade Part number Package H0 for no heatsink (identifier not marked on part) B – 100 PQFP/TEP w/DW0045-28 heatsink unattached H0 – No Heatsink AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright ® 1999 Applied Micro Circuits Corporation AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885 http://www.amcc.com C ER T I F I ED ISO 9001