S25HL512TDPMHI010 INFINEON | Alldatasheet
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S25HS256T/S25HS512T/S25HS01GT S25HL256T/S25HL512T/S25HL01GT 256-Mb (32-MB)/512-Mb (64-MB)/ 1-Gb (128-MB), HS-T (1.8-V)/HL-T (3.0-V), Semper® Flash with Quad SPI Cypress Semiconductor Corporation• 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-23880 Rev. *A Revised July 09, 2019 S25HS512T / S25HS01GT/ S25HL512T / S25HL01GT, 512-Mb (64-MB), 1 -Gb (128-MB), HS-T (1.8-V), HL-T (3.0-V), Semper® Flash with Qu ad SP Device Overview Architecture ■ Cypress 45-nm MirrorBit® technology that stores two data bits in each memory array cell Sector Architecture options ❐ Uniform: Address space consists of all 256 KB Sectors ❐ Hybrid
- Configuration 1: Address space consists of thirty-two 4 KB sectors grouped either on the top or the bottom while the remaining sectors are all 256 KB
- Configuration 2: Address space consists of thirty-two 4 KB sectors equally split between top and bottom while the remaining sectors are all 256 KB Page Programming buffer of 256 or 512 bytes OTP Secure Silicon array of 1024 bytes (32 32 bytes) Interface Quad SPI ❐ Supports 1S-1S-4S, 1S-4S-4S, 1S-4D-4D, 4S-4S-4S, 4S- 4D-4D protocols ❐ SDR option runs up to 83 MBps (166 MHz clock speed) ❐ DDR option runs up to 102 MBps (102 MHz clock speed) Dual SPI ❐ Supports 1S-2S-2S protocol ❐ SDR option runs up to 41.5 MBps (166 MHz clock speed) SPI ❐ Supports 1S-1S-1S protocol ❐ SDR option runs up to 21 MBps (166 MHz clock speed) Highlights Safety Features ❐ Functional Safety with the Industry’s first ISO26262 ASIL B compliant and ASIL D ready NOR flash ❐ EnduraFlex Architecture provides High-Endurance and Long Retention Partitions ❐ Data Integrity CRC detects errors in memory array ❐ SafeBoot reports device initialization failures, detects config- uration corruption, and provides recovery options ❐ Built-in Error Correcting Code (ECC) corrects Single-bit Error and detects Double-bit Error (SECDED) on memory array data ❐ Sector Erase Status indicator for power loss during erase Protection Features ❐ Legacy Block Protection for memory array and device configuration ❐ Advanced Sector Protection for individual memory array sector based protection A u t o B o o t e n a b l e s i m m e d i a t e a c c e s s t o t h e m e m o r y a r r a y following power-on Hardware Reset through CS# Signaling method (JEDEC) / individual RESET# pin / DQ3_RESET# pin Identification Serial Flash Discoverable Pa rameters (SFDP) describing device functions and features Device Identification, Manufactu rer Identification and Unique Identification Data Integrity 256 Mb Devices ❐ Minimum 640,000 Program-Erase Cycles for the Main array 512 Mb Devices ❐ Minimum 1,280,000 Program-Erase Cycles for the Main array 1 Gb Devices ❐ Minimum 2,560,000 Program-Erase Cycles for the Main array All Devices ❐ Minimum 300,000 Program-Erase Cycles for the 4 KB Sectors ❐ Minimum 25 Years Data Retention Supply Voltage 1.7-V to 2.0-V (HS-T) 2.7-V to 3.6-V (HL-T) Grade/Temperature Range Industrial (40 °C to +85 °C) Industrial Plus (40 °C to +105 °C) Automotive AEC-Q100 Grade 3 (40 °C to +85 °C) Automotive AEC-Q100 Grade 2 (40 °C to +105 °C) Automotive AEC-Q100 Grade 1 (40 °C to +125 °C) Packages 256 Mb and 512 Mb: ❐ 24-ball BGA 6 8 mm ❐ 16-lead SOIC (300 mil) ❐ 8-contact WSON 6 8 mm 1 Gb: ❐ 24-ball BGA 8 8 mm ❐ 16-lead SOIC (300 mil)
Document Number: 002-23880 Rev. *A Page 2 of 9 S25HS256T/S25HS512T/S25HS01GT S25HL256T/S25HL512T/S25HL01GT Performance Summary Maximum Read Rates Transaction Initial Access Latency (Cycles) Clock Rate (MHz) MBps SPI Read 0 50 6.25 SPI Fast Read 9 166 20.75 Dual Read SDR 7 166 41.5 Quad Read SDR 10 166 83 Quad Read DDR 7 102 102 Typical Program and Erase Rates Operation KBps 256B Page Programming (4 KB Sector / 256 KB Sector) 595 / 533 512B Page Programming (4 KB Sector / 256 KB Sector) 753 / 898
256 KB Sector Erase 331
4 KB Sector Erase 95
Typical Current Consumption Operation Current (mA) SDR Read 50 MHz 10 SDR Read 166 MHz 53 DDR Read 102 MHz 50 Program 50 Erase 50 Standby (HS-T) 0.011 Standby (HL-T) 0.014 Deep Power Down (HS-T) 0.0013 Deep Power Down (HL-T) 0.0022
Figure 3. 8-Connector Package (WSON 6 X 8), Top View Table 1. Signal Description of the clock, and data is output on both edges of the clock. when CS# is HIGH or Quad SPI protocol is disabled. be pulled up to the HIGH state on its own.
QIO and QPI that transfer address and read data on both edges of the clock. Read operations from the device are burst oriented. Read transa ctions can be configured to use either a wrapped or linear burs t. Wrapped bursts read from a single page whereas linear bursts can read the whole memory array. can change a memory bit from a 0 to a 1. An erase operation must be performed on a complete sector (4 KBs or 256 KBs). the remaining sectors are all 256 KB. 512 byte option provides the highest programming throughput. Figure 4. Logic Block Diagram The Semper Flash with Quad SPI family consists of multiple densities with, 1.8V and 3.0V core and I/O voltage options. performs the related Embedded Algorithms. Changing the nonvolatile data in the memory array requires a se quence of operations that are pa rt of Embedded Algorithms (EA). steps to complete the transaction, and provides status information during the progress of an EA.
Document Number: 002-23880 Rev. *A Page 6 of 9 S25HS256T/S25HS512T/S25HS01GT S25HL256T/S25HL512T/S25HL01GT Executing code directly from Flash memory is often called Execu te-In-Place (XIP). By using XIP with Semper Flash devices at th e higher clock rates with Quad or DDR Quad SPI transactions, the data transfer rate can match or exceed traditional parallel or asynchronous NOR flash memories while reducing signal count dramatically. EnduraFlex Architecture provides system designers the ability to customize the NOR Flash endurance and retention for their specific application. The host defines partitions for high endurance or long retention, providing up to 1+ million cycles or 25 years o f data retention. The Semper Flash with Quad SPI device supports error detection and correction by generating an embedded Hamming error correction code during memory array programming. This ECC code is then used for single-bit and double-bit error detection and single- bit correction during read. The Semper Flash with Quad SPI device has built-in diagnostic features providing the host system with the device status. ■ Program and Erase Operation: Reporting of program or erase success, failure and suspend status ■ Error Detection and Correction: 1-bit and/or 2-bit error status with address trapping and error count ■ Data Integrity Check: Error detection over memory array contents ■ SafeBoot: Reporting of proper flash device initialization and configuration corruption recovery ■ Sector Erase Status: Reporting of erase success or failure status per sector ■ Sector Erase Counter: Counts the number of erase cycles per sector
Document Number: 002-23880 Rev. *A Page 7 of 9 S25HS256T/S25HS512T/S25HS01GT S25HL256T/S25HL512T/S25HL01GT
Ordering Information
The ordering part number is formed by a valid combination of the following: Register for the Semper Access Program and get access to datash eets, application notes, models, software, and evaluation kits. S25HL S25HS 512 T FA M H I 00 1 Packing Type[2] 0 = Tray 1 = Tube 3 = 13” Tape and Reel Model Number (Additional Ordering Options) 01 = BGA / WSON 6 8 mm, SOIC -16 package 03 = BGA 8 8 mm package Grade / Temperature Range I = Industrial (–40 °C to + 85 °C) V = Industrial Plus (–40 °C to + 105 °C) A = Automotive, AEC-Q100 Grade 3 (–40 °C to +85 °C) B = Automotive, AEC-Q100 Grade 2 (–40 °C to +105 °C) M = Automotive, AEC-Q100 Grade 1 (–40 °C to +125 °C) Package Materials H = Low-Halogen, Lead (Pb)-free Package Type M = 16-pin SOIC N = 8-contact WSON 6 8 mm B = 24-ball 5 5 BGA, 1.00 mm pitch Speed DP = 133 MHz SDR / 66 MHz DDR DS = 166 MHz SDR / 83 MHz DDR FA = 166 MHz SDR / 102 MHz DDR Device Technology T = 45-nm MirrorBit Process Technology Density 256 = 256 Mb 512 = 512 Mb 01G = 1 Gb Device Family S25HS Quad SPI High Performance 1.8V S25HL Quad SPI High Performance 3.0V Note 2. See Packing and Packaging Handbook on www.cypress.com for further information.
Document Number: 002-23880 Rev. *A Page 8 of 9 S25HS256T/S25HS512T/S25HS01GT S25HL256T/S25HL512T/S25HL01GT Document History Page Document Title: S25HS256T/S25HS512T/S25HS01GT/S25HL256T/S25HL512T/S25HL01GT, 256-Mb (32-MB)/512-Mb (64-MB)/ 1-Gb (128-MB), HS-T (1.8-V)/HL-T (3.0-V), Semper® Flash with Quad SPI Document Number: 002-23880 Rev. ECN No. Submission Date Description of Change ** 6169693 05/09/2018 New data sheet. *A 6616129 07/09/2019 Changed status from Preliminary to Final. Updated Document Title to read as “S25HS256T/S25HS512T/S25HS01GT/S25HL256T/S25HL512T/S25HL01GT, 256-Mb (32-MB)/512-Mb (64-MB)/1-G b (128-MB), HS-T (1.8-V)/HL-T (3.0-V), Semper Flash with Quad SPI”. Added S25HS256T, S25HL256T parts related information in all ins tances across the document. Updated to new template.
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