S24042 SUMMIT | Alldatasheet

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SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131  Campbell, CA 95008  Telephone 408-378-6461  Fax 408-378-6586  www.summitmicro.com © SUMMIT MICROELECTRONICS, Inc. 2000 2011 2.1 8/2/00 Characteristics subject to change without notice SUMMIT MICROELECTRONICS, Inc.

FEATURES

  • Precision Supply Voltage Monitor — Dual reset outputs for complex microcontroller systems — Integrated memory write lockout  Guaranteed RESET (RESET#) assertion to VCC =1V  Power-Fail Accuracy Guaranteed  No External Components  3 and 5 Volt system versions  Low Power CMOS — Active current less than 3mA — Standby current less than 25µA  Memory Internally Organized 512 X 8 — Two Wire Serial Interface (I 2C™) – Bidirectional data transfer protocol – Standard 100KHz and Fast 400KHz Precision RESET Controller and 4K I2C Memory With Both RESET and RESETRESETRESETRESETRESET Outputs S24042/S24043  High Reliability — Endurance: 100,000 erase/write cycles — Data retention: 100 years  8-Pin SOIC Packages OVERVIEW The S24042 and S24043 are power supervisory devices with 4,096 bits of serial E2PROM. They are fabricated using SUMMIT’s advanced CMOS E2PROM technology and are suitable for both 3 and 5 volt systems. The memory is internally organized as 512 x 8. It features the I2C serial interface and software protocol allowing operation on a simple two-wire bus. The S24042 provides a precision VCC sense circuit and two open drain outputs: one (RESET) drives high and the other (RESET#) drives low whenever VCC falls below VTRIP. The S24043 is identical to the S24042 with the exception being RESET is not bonded out on pin 7. BLOCK DIAGRAM 3 and 5 Volt Systems GND VCC RESET# VTRIP RESET PULSE GENERATOR 5kHz OSCILLATOR RESET CONTROL MODE DECODE ADDRESS DECODER WRITE CONTROL DATA I/O E2PROM MEMORY ARRAY RESET 1.26V SCL 6 SDA 5 2011 T -BD 1.0

2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. RESET #- RESET# is an active low open drain output. It is driven low whenever VCC is below VTRIP. It is also an input and can be used to debounce a switch input or perform signal conditioning. The pin has an internal pull- up and should be left unconnected if the signal is not used in the system. However, when the pin is tied to a system RESET# line an external pull-up resistor should be employed. RESET - RESET is an active high open drain output. It is driven high whenever V CC is below VTRIP. RESET is also an input and can be used to debounce a switch input or perform signal conditioning. The RESET pin does have an internal pull-down and should be left unconnected if the signal is not used in the system. However, when the pin is tied to a system reset line an external pull-down resistor should be employed. ENDURANCE AND DATA RETENTION The S24042/43 is designed for applications requiring 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles.

APPLICATIONS

Reset Controller Description The S24042/43 provides a precision RESET controller that ensures correct system operation during brown-out and power-up/-down conditions. It is configured with two open drain RESET outputs; pin 7 is an active high output and pin 2 is an active low output. During power-up, the RESET outputs remain active until V CC reaches the VTRIP threshold and will continue driving the outputs for approximately 200ms after reaching V TRIP. The RESET outputs will be valid so long as VCC is > 1.0V. During power-down, the RESET outputs will begin driving active when V CC falls below VTRIP. The RESET pins are I/Os; therefore, the S24042/43 can act as a signal conditioning circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset timeout after detecting a low to high transition and the RESET# input will initiate a reset timeout after detecting a high to low transition. Refer to the applications Information section for more details on device operation as a reset conditioning circuit. PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wire- ORed with any number of open-drain or open-collector outputs. No Connects (NC) the no connect pins may be left floating or tied to ground. They cannot be tied high. PIN NAMES SDA Serial Data I/O SCL Serial Clock Input RESET & RESET# Reset Output VSS Ground VCC Supply Voltage NC No Connect PIN CONFIGURATIONS NC RESET# NC VSS VCC NC SCL SDA NC RESET# NC V SS VCC RESET SCL SDA S24043 S24042 2011 PCon 2.0

2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. FIGURE 1. TYPICAL SYSTEM CONFIGURATION FOR DUAL RESET FIGURE 2. START AND STOP CONDITIONS

8051 Type MCU

2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. FIGURE 8. RANDOM ADDRESS BYTE READ MODE WRITE) followed by the address of the word it is to read. S24042/43 to the desired address.

2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. ACKnowledge, and issues a STOP conditions. address, acknowledge and data transfer sequence. FIGURE 9. SEQUENTIAL READ OPERATION (starting with a Random Address READ)

2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. ABSOLUTE MAXIMUM RATINGS NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability. 2.7V to 4.5V 4.5V to 5.5V Symbol Parameter Conditions Min Max Min Max Units fSCL SCL Clock Frequency 0 100 400 KHz tLOW Clock Low Period 4.7 1.3 µs tHIGH Clock High Period 4.0 0.6 µs tBUF Bus Free Time Before New Transmission 4.7 1.3 µs tSU:STA Start Condition Setup Time 4.7 0.6 µs tHD:STA Start Condition Hold Time 4.0 0.6 µs tSU:STO Stop Condition Setup Time 4.7 0.6 µs tAA Clock to Output SCL Low to SDA Data Out Valid 0.3 3.5 0.2 0.9 µs tDH Data Out Hold Time SCL Low to SDA Data Out Change 0.3 0.2 µs tR SCL and SDA Rise Time 1000 300 ns tF SCL and SDA Fall Time 300 300 ns tSU:DAT Data In Setup Time 250 100 ns tHD:DAT Data In Hold Time 0 0 ns TI Noise Spike Width Noise Suppression Time Constant 100 100 ns @ SCL, SDA Inputs tWR Write Cycle Time 10 10 ms AC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) 2011 PGM T2 1.0 2011 PGM T1 1.0 DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol Parameter Conditions Min Max Units SCL = CMOS Levels @ 100KHz V CC =5.5V 3 mA ICC Supply Current (CMOS) SDA = Open All other inputs = GND or VCC VCC =3.3V 2 mA ISB Standby Current (CMOS) SCL = SDA = V CC VCC =5.5V 50 µA All other inputs = GND ILI Input Leakage V IN = 0 To VCC 10 µA ILO Output Leakage V OUT = 0 To VCC 10 µA VIL Input Low Voltage SCL, SDA, RESET 0.3xV CC V VIH Input High Voltage SCL, SDA 0.7xV CC V VOL Output Low Voltage I OL = 3mA SDA 0.4 V VCC =3.3V 25 µA Characteristic Min Max VCC 2.7V 5.5V Operating Temperature Range –40°C8 5 °C RECOMMENDED OPERATING CONDITIONS 2011 PGM T6 1.0

2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. FIGURE 10. BUS TIMING

2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. FIGURE 11. RESET OUTPUT TIMING

2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. Frequently the reset controller will be deployed on a PC board that provides a peripheral function to a system. Examples might be modem or network cards in a PC or a PCMCIA card in a laptop. In instances like this the peripheral card may have a requirement for a clean reset function to insure proper operation. The system may or may not provide a reset pulse of sufficient duration to clear the peripheral or to protect data stored in a nonvolatile memory. The I/O capability of the RESET pins can provide a solution. The system’s reset signal to the peripheral can be fed into the S24042/43 and it in turn can clean up the signal and provide a known entity to the peripheral’s circuits. The figure below shows the basic timing characteristics under the assumption the reset input is shorter in duration than t PURST . The same reset output affect can be attained by using the active high reset input. When planning your resistor pull-up and pull-down values, use the following chart to help determine min. resistances. Condition Min Typ Max Units VCC = 1.0V, IOL =100µA 0.3 V VCC = 1.2V, IOL =100µA 0.3 V VCC = 3.0V, IOL =500µA 0.3 V VCC = 3.6V, IOL =500µA 0.3 V VCC = 4.5V, IOL =750µA 0.3 V VCC = 1.0V, IOL =100µA 0.4 V VCC = 1.2V, IOL =150µA 0.4 V VCC = 3.0V, IOL =750µA 0.4 V VCC = 3.6V, IOL =1mA 0.4 V VCC = 4.5V, IOL =1mA 0.4 V VCC = 1.0V, IOH =400µA V CC -0.75 V VCC = 1.2V, IOH =800µA V CC -0.75 V VCC = 3.0V, IOH =800µA V CC -0.5 V VCC = 3.6V, IOH =800µA V CC -0.5 V VCC = 4.5V, IOH =800µA V CC -0.5 V Worst Case RESET Sink/Source Capabilities at Various VCC Levels Parameter Symbol RESET# Output V OL Voltage RESET# Output V OL Voltage RESET Output V OH Voltage 2011 PGM T5 1.0 RESET# Input RESET# Output RESET Output 2011 T fig12 2.0 tPURST

2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc. .228 (5.80) .035 (.90) .020 (.50) .010 (.25) x45° .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .275 (6.99) TYP. .030 (.762) TYP.

8 Places

.050 (1.27) TYP. .050 (1.270) TYP. .157 (4.00) .150 (3.80) .196 (5.00)1 .189 (4.80) FOOTPRINT 8pn JEDEC SOIC ILL.2

8 Pin SOIC (Type S) Package JEDEC (150 mil body width)

2011 2.1 8/2/00 SUMMIT MICROELECTRONICS, Inc.

ORDERING INFORMATION

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2000 SUMMIT Microelectronics, Inc. I2C is a trademark of Philips Corporation. S24022 S A T Base Part Number Tape & Reel Option Operating Voltage RangePackage S = 8 Lead 150mil SOIC Blank = Tube T = Tape & Reel A = 4.5V to 5.5V VTRIP min. @ 4.25V B = 4.5V to 5.5V VTRIP min. @ 4.50V S24022 = Reset Active High & Low S24023 = Reset Active Low 2011 Tree 2.0