S2070 AMCC | Alldatasheet

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S2070FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER March 7, 2001 / Revision G S2070 DEVICE SPECIFICATION FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER

FEATURES

  • 1062 Mbps (Fibre Channel) line rates
  • 1250 Mbps (Gigabit Ethernet) line rates
  • Half and full VCO output rates
  • Functionally compliant to IEEE 802.3z Gigabit Ethernet Specification and the ANSI X3T11 Fibre Channel Specification
  • Transmitter incorporating phase-locked loop (PLL) clock synthesis from low speed reference
  • Receiver PLL provides clock and data recovery
  • 10-bit parallel TTL compatible interface
  • Low-jitter serial LVPECL compatible interface
  • Local loopback
  • Single +3.3 V supply, 620 mW power dissipation
  • 64 PQFP package
  • Continuous downstream clocking from receiver
  • Drives 30 m of Twinax cable directly

APPLICATIONS

  • Workstation
  • Frame buffer
  • Switched networks
  • Data broadcast environments
  • Proprietary extended backplanes GENERAL DESCRIPTION The S2070 transmitter and receiver chip facilitates high speed serial transmission of data over fiber op- tic, coax, or twinax interfaces. The device conforms to the requirements of the IEEE 802.3z Gigabit Ethernet Specification and the ANSI X3T11 Fibre Channel specification, and runs at 1062 Mbps or

1250 Mbps data rates with an associated 10-bit data

word. The chip provides parallel-to-serial and serial-to-par- allel conversion, clock generation/recovery, and framing for block encoded data. The on-chip transmit PLL synthesizes the high-speed clock from a low- speed reference. The on-chip receive PLL performs clock recovery and data re-timing on the serial bit stream. The transmitter and receiver each support differential LVPECL compatible I/O for copper or fi- ber optic component interfaces with excellent signal integrity. Local loopback mode allows for system di- agnostics. The chip requires a +3.3 V power supply and dissipates approximately 620 mW under typical conditions. The S2070 can be used for a variety of applications including Fibre Channel, serial backplanes, and pro- prietary point-to-point links. Figure 1 shows a typical configuration incorporating the chip. Figure 1. System Block Diagram

  1. Parallel-to-serial conversion
  2. Clock and data recoverery from serial input
  3. Serial-to-parallel conversion
  4. For reference, Table 1 shows the

mapping of the parallel data to the 8B/10B codes. Figure 2. Functional Block Diagram Table 1. Data Mapping to 8B/10B

operates in either full rate or half rate mode. The average transmit latency is 4 parallel clocks. Table 2. Operating Rates

tempt to lock to the incoming data. the integrity of downstream clocking. clock to ensure reliable locking of the receiver PLL. chronize on any particular incoming character. ter is present on the RX[0:9] parallel data outputs. Table 3. Lock to Reference Frequency Criteria

Table 5. Pin Description and Assignment Note: All TTL inputs have internal 15KΩ pull-up networks.

Table 5. Pin Description and Assignment (Continued)

Table 6. Power and Ground Signals

Figure 4. S2070 Pinout

Figure 5. 14mm x 14mm 64 PQFP Package

Figure 6. 10mm x 10mm 64 PQFP with Heat Spreader Package

Table 7. Power and Ground Application Information

Figure 7. Power and Ground Connection Diagram

Figure 8. Transmitter Timing Table 8. S2070 Transmitter Timing

  1. All AC measurements are made from the reference voltage level of the clock (+1.4 V) to the valid input or output data

Table 9. S2070 Receiver Timing

Table 10. Absolute Maximum Ratings Table 11. Recommended Operating Conditions Table 12. Reference Clock Requirements those indicated in the Recommended Operating Conditions of the document are not inferred. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

1 Human body model

Table 13. DC Characteristics

S2070 FIBRE CHANNEL/GIGABIT ETHERNET TRANSCEIVER March 7, 2001 / Revision G AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright ® 2001 Applied Micro Circuits Corporation D49/R475 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885 http://www.amcc.com C ER T I F I ED ISO 9001

Ordering Information

EDARG. ONTRAPE GAKCAP laicremmoC-S0 702 )mm01redaerpStaeH/wPFQP46(–A )mm41PFQP46(–B X X Grade Part No. Package XXXX