S2060 AMCC | Alldatasheet

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S2060GIGABIT ETHERNET TRANSCEIVER March 7, 2001 / Revision H S2060 DEVICE SPECIFICATION GIGABIT ETHERNET TRANSCEIVER

FEATURES

  • Operating rate
  • 1250 MHz (Gigabit Ethernet) line rates
  • Half and full VCO output rates
  • Functionally compliant IEEE 802.3z Gigabit Ethernet standard
  • Transmitter incorporating Phase-Locked Loop (PLL) clock synthesis from low speed reference
  • Receiver PLL provides clock and data recovery
  • 10-bit parallel TTL compatible interface
  • Low-jitter serial LVPECL compatible interface
  • Local loopback
  • Single +3.3 V supply, 620 mW power dissipation
  • 64 PQFP or TQFP package
  • Continuous downstream clocking from receiver
  • Drives 30 m of Twinax cable directly

APPLICATIONS

  • Workstation
  • Frame buffer
  • Switched networks
  • Data broadcast environments
  • Proprietary extended backplanes GENERAL DESCRIPTION The S2060 transmitter and receiver chip facilitates high speed serial transmission of data over fiber op- tic, coax, or twinax interfaces. The device conforms to the requirements of the IEEE 802.3z Gigabit Ethernet specification, and runs at 1250.0 Mbps data rates with an associated 10-bit data word. The chip provides parallel-to-serial and serial-to-par- allel conversion, clock generation/recovery, and framing for block encoded data. The on-chip transmit PLL synthesizes the high-speed clock from a low- speed reference. The on-chip receive PLL performs clock recovery and data re-timing on the serial bit stream. The transmitter and receiver each support differential LVPECL compatible I/O for copper or fi- ber optic component interfaces with excellent signal integrity. Local loopback mode allows for system di- agnostics. The chip requires a +3.3 V power supply and dissipates typically 620 mW. The S2060 can be used for a variety of applications including Gigabit Ethernet, serial backplanes, and proprietary point-to-point links. Figure 1 shows a typical configuration incorporating the chip.

Figure 1. System Block Diagram

  1. Parallel-to-serial conversion
  2. Clock and data recovery from serial input
  3. Serial-to-parallel conversion
  4. For reference, Table 1 shows the

mapping of the parallel data to the 8B/10B codes. Figure 2. Functional Block Diagram Table 1. Data Mapping to 8B/10B

frequency locked to TBC (125.00 MHz). The average transmit latency is 4 byte times. Table 2. Operating Rates

tempt to lock to the incoming data. the integrity of downstream clocking. clock to ensure reliable locking of the receiver PLL. layed by a maximum of 3 byte times. Table 3. Lock to Reference Frequency Criteria

ter is present on the RX[0:9] parallel data outputs. RBC0 and RBC1. See Figures 11 and 12. Table 4. Operating Rates clock operates without glitches or loss of cycles. The average receive latency is 8 byte times.

Table 5. Pin Description and Assignment

Note: All TTL inputs have internal 15 KΩ pull-up networks. Table 5. Pin Description and Assignment (Continued)

Table 6. Power and Ground Signals

Figure 3. S2060 Pinout (S2060A, S2060B, S2060D)

Figure 4. S2060 Pinout (S2060C)

Figure 5. 10mm x 10mm 64 PQFP Package (S2060A)

Figure 6. 14 mm x 14 mm 64 PQFP Package (S2060B)

Figure 7. 10mm x 10mm 64 TQFP Package (S2060C)

Figure 8. 14 mm x 14 mm 64 PQFP Package (S2060D)

Table 7. Power and Ground Application Information

Figure 9. Power and Ground Connection Diagram

Table 11. Recommended Operating Conditions

  1. Commercial temperature range S2060A, S2060B, S2060C.
  2. Industrial temperature range S2060D.

Table 10. Absolute Maximum Ratings

Table 13. DC Characteristics Table 12. Reference Clock Requirements

S2060 GIGABIT ETHERNET TRANSCEIVER March 7, 2001 / Revision H AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright ® 2001 Applied Micro Circuits Corporation D50/R476 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 • (800) 755-2622 • Fax: (858) 450-9885 http://www.amcc.com C ER T I F I ED ISO 9001

Ordering Information

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