S2043

S2042 AMCC | Alldatasheet

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Technical content

TCLK/TCLKN clock frequencies. Table 1. Transmitter Operating Modes transmitter on the positive going edge of REFCLK. controlled by the output enable pins, OE0 and OE1. of the parallel data to the 8B/10B codes. Table 2. Data Mapping to 8b/10b Alphabetic Representation Figure 4. S2043 Functional Block Diagram

Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-93334 HIGH PERFORMANCE SERIAL INTERFACE CIRCUITSS2042/S2043 S2043 RECEIVER FUNCTIONAL

DESCRIPTION

The S2043 receiver is designed to implement the ANSI X3T11 Fibre Channel specification receiver functions. A block diagram showing the basic chip function is provided in Figure 4. Whenever a signal is present, the S2043 attempts to achieve synchronization on both bit and transmis- sion-word boundaries of the received encoded bit stream. Received data from the incoming bit stream is provided on the device’s parallel data outputs. The S2043 accepts serial encoded data from a fiber optic or coaxial cable interface. The serial input stream is the result of the serialization of 8B/10B encoded data by an FC compatible transmitter. Clock recov- ery is performed on-chip, with the output data presented to the Fibre Channel transmission layer as 10- or 20-bit parallel data. The chip is program- mable to operate at the Fibre Channel specified operating frequencies of 1062, 531 and 266 Mbit/s. Serial/Parallel Conversion Serial data is received on the RX, RY pins. The PLL clock recovery circuit will lock to the data stream if the clock to be recovered is within ±100 PPM of the inter- nally generated bit rate clock. The recovered clock is used to retime the input data stream. The data is then clocked into the serial to parallel output regis- ters on the low going edge of RCLK. In 1062 Mbit/ sec, 10-bit mode, data is clocked out on the falling edge of RCLK and RCLKN.The parallel data out can be either 10 or 20 bits wide determined by the state of the DWS pin. The word clock (RCLK) is synchro- nized to the incoming data stream word boundary by the detection of the fiber channel K28.5 synchroniza- tion pattern (0011111010, positive running disparity). 10-Bit/20-Bit Mode The S2043 will operate with either 10-bit or 20-bit parallel data outputs. This option is selectable via the DWS pin. See Table 4. In 10-bit mode, D10-D19 are used and D0-D9 are driven to the logic high state. Reference Clock Input The reference clock input must be supplied with a single- ended AC coupled crystal clock source at ±100 PPM tolerance. See Table 4 for reference clock frequencies. Framing The S2043 provides SYNC character recognition and data word alignment of the TTL level compatible output data bus. In systems where the SYNC detect function is undesired, a LOW on the SYNCEN input disables the SYNC function and the data will be “un-framed”. First Data Byte Second Data Byte 19181716151413121110 jhgfiedcba 9876543210TX[00:19] or RX[00:19] 8b/10b alphabetic representation jhgfiedcba First bit received in 20-bit mode First bit received in 10-bit mode Table 3. Data Mapping to 8b/10b Alphabetic Representation Figure 5. Functional Waveform

SYNCEN input should be static during operation (i.e. transitions from the active to inactive state. clocked with the RCLKN output. downstream clocking will be maintained. rity of downstream clocking. Table 4. Receiver Operating Modes dure to correctly achieve lock on the serial data inputs. cent for a minimum of 10 ms after power-up. mission medium. It also allows system diagnostics. the Fibre Channel rates of 266, 531 and 1062 Mbit/s. sible if the rate falls within ±10% of the nominal rate. the desired byte or word clock rate. Figure 6. Loopback Interface Diagram

Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-93336 HIGH PERFORMANCE SERIAL INTERFACE CIRCUITSS2042/S2043 S2042 Pin Assignment and Descriptions emaNniPl eveLO /I# niPn oitpircseD 91D 81D 71D 61D 51D 41D 31D 21D 11D 01D LTTI0 5 egdegnisirehtnonidekcolcsiataD.atadtupnilellarapstpeccA tib-01nI.tsrifdettimsnartsi0D,edomtib-02nI.KLCFERfo si01Ddna,derongiera9D-0D,desuera91-01D,edom .tsrifdettimsnart TSETc itatS -itluM leveL LTT I0 2, detcennoctonnehW.gnitsetyrotcafrofdesutupnilevelitluM yrotcafetatilicafotkcolctiblanretniehtsecalperKLCFER .dnuorgotderiwsitupnisiht,esulamronnI.gnitset SWD LTT I9 1n ehW.htdiwsubatadlellarapehtstcelesnipsihtnolevelehT era)91-0(Ddna,detcelessihtdiwsublellaraptib-02a,WOL -01(D,detcelessisubatadlellaraptib-01a,HGIHnehW.evitca gnisirA).1elbaTeeS(.desutonera)9-0(Ddnaevitcaera)91 .)tsetrofdesu(trapehtteserlliwegde KLCFERL CEPI 6 1e cnereferdellortnoc-latsyrcA).delpuocyleviticapacyllanretxE( siKLCFERfoycneuqerfehT.reilpitlumkcolcLLPehtrofkcolc ).1elbaTeeS(.nipLESFERehtybtes KLCT NKLCT .ffiD LTT O2 1 eeS.tnemelpmocdnaeurtkcolcetardrowLTTlaitnereffiD .ycneuqerfrof1elbaT YT XT .ffiD LCEP evirddnaatadlairesehttimsnarttahtstuptuoLCEPlaitnereffiD 57W 0 5roW e htsiXT.0EOybdelbanE.V2-ccVotnoitanimret .tuptuoevitagenehtsiYTdna,tuptuoevitisop XLT YLT .ffiD LCEP XTottnelaviuqeyllanoitcnuferatahtstuptuoLCEPlaitnereffiD .gnitsetkcabpoolrofdesuebotdednetnierayehT.YTdna .1EOybdelbanE

Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 7 HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS S2042/S2043 S2042 Pin Assignment and Descriptions (Continued) emaNniPl eveLO /I# niPn oitpircseD 0EOc itatS LTT I2 l liwYT/XT.stuptuoYT/XTroflortnocelbane-tuptuowolevitcA .delbasidnehwetatswolcigolehtotog 1EO LTT I1 Y LT/XLT.stuptuoYLT/XLTroflortnocelbane-tuptuowolevitcA .delbasidnehwetatswolcigolehtotoglliw LESFERc itatS -itluM LTT I8 1. ycneuqerfkcolcecnereferehttcelesotdesutupnilevelitluM ).1elbaTeeS( LESETAR LTT I5 1e htfodeepsgnitarepoehttcelesotdesutupnilevelitluM ).1elbaTeeS(.rettimsnart CCVLCEV 3.3+– , 93,12 V3.3+eroC DNGLTTD NG–4 1d nuorGLTT CCVLTT/ V3.3+ V5+ –7 1) LTTfiV5+(ylppuSrewoPLTT CCVOILCEV 3.3+– 0 1,3y lppuSrewoPO/ILCEP EEVOILCED NG– 7 ,6y lppuSrewoPO/ILCEP CCVAV 3.3+– 2 3,72y lppuSrewoPgolanA EEVAD NG– 3 3,62d nuorGgolanA EEVLCED NG– , 43,31 ,64,04 25,15 dnuorGeroC

Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-93338 HIGH PERFORMANCE SERIAL INTERFACE CIRCUITSS2042/S2043 S2043 Pin Assignment and Descriptions emaNniPl eveLO /I# niPn oitpircseD 91D 81D 71D 61D 51D 41D 31D 21D 11D 01D LTTO 5 4 sisubatadlellarapehtfohtdiwehT.stuptuoatadlellaraP sisubsihtnoatadlellaraP.nipSWDehtfoetatsehtybdetceles nodnaedomtib-02niKLCRfoegdegnillafehtnotuodekcolc ,ces/tibM5.2601niNKLCRdnaKLCRfosegdegnillafehthtob tib-01nI.deviecertibtsrifehtsi0D,edomtib-02nI.edomtib-01 hgihehtotnevirdera9D-0Ddnadesuera91D-01D,edom .deviecertibtsrifehtsi01D,edomtib-01nI.etats NTEDKCOLL TTO 2 5e htotdekcolsiLLPehttahtsetacidniNTEDKCOL,WOLnehW galfmetsysasedivorpti,HGIHnehW.maertsatadgnimocni .kcolcecnereferlacolehtotdekcolsiLLPehttahtgnitacidni NEPLL TTI8 t upnilaireslaitnereffidkcabpoolehtstcelesNEPL,HGIHnehW .)noitarepolamron(YRdnaXRstcelesNEPL,WOLnehW.snip SWDc itatS LTT I4 n ehW.htdiwsubatadlellarapehtstcelesnipsihtnolevelehT era)91-0(Ddna,detcelessihtdiwsublellaraptib-02a,WOL -01(D,detcelessisubatadlellaraptib-01a,HGIHnehW.evitca gnisirA).4elbaTeeS(.HGIHoglliw)9-0(Ddnaevitcaera)91 .)tsetrofdesu(sretnuoclanretniehtteserlliwegde KLCR NKLCR .ffiD LTT O9 4 NKLCR/KLCRfoegdegnillafehtnotuodekcolcsiatadlellaraP sidrowcnysaretfA.)81-51serugiFnismargaiDgnimiTees( siNKLCRdnaKLCRtnerrucehtfodoirepeht,detceted rof4elbaTeeS(.yradnuobdrowehthtiwngilaotdehcterts ).ycneuqerf KLCFERg olanAI 2 - latsyrcgninnur-eerfA).delpuocyleviticapacyllanretxE( ehT.reilpitlumkcolcLLPehtrofkcolcecnereferdellortnoc ).4elbaTeeS(.nipLESFERehtybtessiKLCFERfoycneuqerf CNYSL TTO 1 5r ofhgihseogtuptuosiht,lobmyscnysdilavafonoitcetednopU ebllahslobmyscnyseht,evitcasicnysnehW.doirepKLCReno dnaedomtib-02ni9D-0Dstibsubatadlellarapehtnotneserp .edomtib-01ni91D-01D XLR YLR .ffiD LCEP I1 1 atadkcabpoollairesehT).delpuocyleviticapacyllanretxE( .tupnievitagenehtsiYLRdna,tupnievitisopehtsiXLR.stupni XR YR .ffiD LCEP atadlairesdeviecerehT).delpuocyleviticapacyllanretxE( .tupnievitagenehtsiYRdna,tupnievitisopehtsiXR.stupni

Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 9 HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS S2042/S2043 S2043 Pin Assignment and Descriptions (Continued) emaNniPl eveLO /I# niPn oitpircseD NECNYSc itatS -itluM leveL LTT I3 f onoitceteD.noitcetedcnysselbane,HGIHnehW).levelitluM( )ytirapsidgninnurevitisop,0101111100:5.82K(nrettapcnyseht neponehW.wollofotatadehtrofyradnuobdrowehtelbanelliw etatilicafotkcolctiblanretnisecalperKLCFER,)detcennocton( sinoitcetedcnys,noitarepofoedomsihtnI.gnitsetyrotcaf .ataddemarfnusadetaertsiatad,WOLnehW.delbanesyawla LESFERc itatS -itluM leveL LTT I0 3. ycneuqerfkcolcecnereferehttcelesotdesutupnI).levelitluM( ).4elbaTeeS( LESETARc itatS -itluM leveL LTT I0 2e htfodeepsgnitarepoehttcelesotdesutupnI).levelitluM( ).4elbaTeeS(.reviecer FER_KCOLL TTI 0 5d natupniKLCFERehtotkcolotLLPehtsecrof,WOLnehW .stupniatadlairesehterongi CCVLCEV 3.3+– , 72,31 ylppuSrewoPeroC DNGLTTD NG– , 33,61 64,14 dnuorGLTT CCVLTT/ V3.3+ V5+ –, 32,91 44,63 )LTTfiV5+(ylppuSrewoPLTT CCVAV 3.3+– 7 y lppuSrewoPgolanA EEVAD NG– 6 ,5d nuorGgolanA EEVLCED NG– 7 4,62,1d nuorGeroC

Figure 7. 52 PQFP Pinouts

Figure 8. 52 PQFP Package

Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-933312 HIGH PERFORMANCE SERIAL INTERFACE CIRCUITSS2042/S2043 PARAMETER MIN TYP MAX UNIT Case Temperature under Bias -55 125 °C Junction Temperature under Bias -55 150 °C Storage Temperature -65 150 °C Voltage on VCC with Repect to GND -0.5 +7.0 V Voltage on any TTL Input Pin -0.5 +5.5V V Voltage on any PECL Input Pin 0 VCC V TTL Output Sink Current 8 mA TTL Output Source Current 8 mA High Speed PECL Output Source Current 50 mA Static Discharge Voltage 500 V Absolute Maximum Ratings Recommended Operating Conditions PARAMETER MIN TYP MAX UNIT Ambient Temperature under Bias 0 70 °C Junction Temperature under Bias 130 °C Voltage on TTLVCC with Respect to GND 5V Operation 3.3V Operation 4.75 3.13 5.0 3.3 5.25 3.47 V V Voltage on any TTL Input Pin 0 TTLVCC V Voltage on ECLVCC with respect to GND 3.13 3.3 3.47 V Voltage on any PECL Input Pin ECLVCC -2.0V ECLVCC V Reference Clock Requirements Parameters Description Min Max Units Conditions FT FT TD 1-2 TRCR , TRCF Frequency Tolerance S2042 Frequency Tolerance S2043 Symmetry REFCLK Rise and Fall Time Random Jitter -100 -100 +100 +100 ppm ppm ns ps Duty Cycle at 50% pt. 20 – 80% Peak-to-Peak

Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333 13 HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS S2042/S2043 Parameters Description Min Typ Units Conditions VOH Output HIGH Voltage (TTL) – 3.3V Power Supply – 3.3V Power Supply – 5V Power Supply 2.1 2.2 2.7 2.0 -500 Max V V V VCC = min, IOH = -2.4mA VCC = min, IOH = -.1mA VCC = min, IOH = -1mA ICC Supply Current 123 160 mA Outputs open, VCC = VCC max PD Power Dissipation .406 .554 W Outputs open, VCC = VCC max VOL Output LOW Voltage (TTL) – 3.3V Power Supply – 5V Power Supply V V VCC = min, IOL = 2.4mA VCC = min, IOL = 4mA VIH VIL IIH IIL Input HIGH Voltage (TTL) Input LOW Voltage (TTL) Input HIGH Current (TTL) Input LOW Current (TTL) 5.5 0.8 -50 V V µA µA IH ≤ 1mA at VIH = 5.5V VIN = 2.4V VIN = 0.5V 440 600 ΔVINCLK ΔVOUT Single-ended REFCLK input swing Serial Output Voltage Swing 1300 1600 mV mV AC coupled 50Ω to VCC -2.0V S2042 DC Characteristics Parameters Description Min Typ Units Conditions VOH Output HIGH Voltage (TTL) – 3.3V Power Supply – 3.3V Power Supply – 5V Power Supply 2.1 2.2 2.7 2.0 -500 Max V V V VCC = min, IOH = -2.4mA VCC = min, IOH = -.1mA VCC = min, IOH = -1mA ICC Supply Current – 10-Bit Mode – 20-Bit Mode 187 194 256 267 mA mA Outputs open, VCC = VCC max Outputs open, VCC = VCC max PD Power Dissipation – 3.3V Supply, 10-Bit Mode – 3.3V Supply, 20-Bit Mode – 5V Supply, 10-Bit Mode – 5V Supply, 20-Bit Mode .617 .640 .728 .778 .887 .925 1.08 1.142 W W W W Outputs open, VCC = VCC max Outputs open, VCC = VCC max Outputs open, VCC = VCC max Outputs open, VCC = VCC max VOL Output LOW Voltage (TTL) – 3.3V Power Supply – 5V Power Supply V V VCC = min, IOL = 2.4mA VCC = min, IOL = 8mA VIH VIL IIH IIL Input HIGH Voltage (TTL) Input LOW Voltage (TTL) Input HIGH Current (TTL) Input LOW Current (TTL) 5.5 0.8 -50 V V µA µA IH ≤ 1mA at VIH = 5.5V VIN = 2.4V VIN = 0.5V 440 100 1300 —ΔVINCLK VDIFF Single-ended REFCLK input swing 1300 mV mV AC coupled Min. differential input voltage swing for differential PECL inputs S2043 DC Characteristics

10% to 90%, tested on a sample basis. 20% to 80%, tested on a sample basis. — 20 ps RMS, tested on a sample basis. — 100 ps Peak-to-peak, tested on a sample basis. Table 5. AC Characteristics Table 6. S2043 Receiver Timing 531, 266 Mbit/sec, 20-bit mode. 531, 266 Mbit/sec, 20-bit mode. 10% to 90%, tested on a sample basis. 10% to 90%, tested on a sample basis. standard eye diagram jitter mask. 2.0V). All TTL AC measurements are assumed to have the output load of 10pF. data levels (.8V or 2.0V). All TTL AC measurements are assumed to have the output load of 10pF.

Figure 9. Transmitter Timing Diagram (531, 266 Mbits/sec, 10-bit mode)

10 BIT DATA (D10-D19)

Figure 10. Transmitter Timing Diagram (531, 266 Mbits/sec, 20-bit mode)

20 BIT DATA

Figure 11. Transmitter Timing Diagram (1062 Mbits/sec, 10-bit mode)

10 BIT DATA

Figure 12. Transmitter Timing Diagram (1062 Mbits/sec, 20-bit mode)

Figure 13. Receiver Timing Diagram (531, 266 Mbits/sec, 10-bit mode) Figure 14. Receiver Timing Diagram (531 Mbits/sec, 20-bit mode)

Figure 15. Receiver Timing Diagram (1062 Mbits/sec, 10-bit mode) Figure 16. Receiver Timing Diagram (1062 Mbits/sec, 20-bit mode)

Applied Micro Circuits Corporation 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-933320 HIGH PERFORMANCE SERIAL INTERFACE CIRCUITSS2042/S2043 TRANSMITTER 2042 GRADE PACKAGE SPEED GRADE S – commercial

Ordering Information

10 – 1062, 531, 266 Mbit/s PACKAGE 2043 RECEIVERGRADE SPEED GRADE S – commercial B – 52 PQFP 10 – 1062, 531, 266 Mbit/s X XXXX X – XX Grade Part number Package Speed Grade B – 52 PQFP Example: S2042B-05 — S2042 in a 52 PQFP package operating at 531 or 266 Mbit/sec rates. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright ® 1997 Applied Micro Circuits Corporation June 2, 1997 AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Applied Micro Circuits Corporation • 6195 Lusk Blvd., San Diego, CA 92121 Phone: (619) 450-9333 Fax: (619) 450-9885 http://www.amcc.com