S1M8662A

S1M8662A SAMSUNG | Alldatasheet

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RX IF/BBA WITH GPS S1M8662A ( Preliminary) INTRODUCTION S1M8662A is CDMA/PCS/GPS Triple Mode IF/ baseband IC which is divided into three main parts - IF frequency processing, basband processing , and digital interface. The receiver IC (S1M8662A)and transmitter IC (S1M8657) are provided as a KIT. S1M8662A is a receiver IC, installed with a Rx AGC, Baseband Converter, Baseband analog filter, and A-D Converter. It can send a digital baseband signal to the digital baseband IC. S1M8662A is fabricated on the Samsung's 0.5um high-speed, high frequency BICMOS processing and can achieve superior high frequency and low power digital operations. Its operating voltage is 2.7 to 3.3V, and operating temperature -30 to +85 °C .

FEATURES

• Cellular CDMA/PCS/GPS Triple Mode
• AGC input signal range : 90dB
• QPSK Baseband Converter
• Built-in I ,Q Baseband signal extractor LPF
• Built-in 4-bit ADC for converting I and Q CDMA analog baseband signals to digital baseband signals
• Built-in VCO for baseband conversion
• Built-in Modem PDM control circuit to compensate the I and Q offsets
• Built-in TCXO output ON/OFF
• 3-Line Serial Port Interface (SPI)
• Operating Voltage : 2.7 to 3.3V
• 32BCC++(5mm * 5mm * 0.8mm) Package

ORDERING INFORMATION

Device Package Operating Temperature ++ S1M8662AX01-F0T0 32-BCC++-5.0 × 5.0 -30 to +85 °C ++ : Under Development 32-BCC++-5.0 × 5.0

S1M8662A ( Preliminary) RX IF/BBA WITH GPS BLOCK DIAGRAM SW CRX_IF1 CRX_IF2 RAGC_CONT GRX_IF1 GRX_IF2 RXVCO_OUT1,2 Q_OFS CHIPX8 RXQD[0] - [3] RXID[0] - [3] I_OFS RXVCO_T1 RXVCO_T2 TCXO_in CLOCK DATA STROBE N=2,3,4,6 TCXO_out VCO Div. N CDMA LPF GPS LPF CDMA LPF GPS LPF Offset Control SPI Control 4-Bit ADC 4-Bit ADC

RX IF/BBA WITH GPS S1M8662A ( Preliminary) PIN CONFIGURATION CRX_IF2 TCXO_out SPI_DATA SPI_STB RXVCO_OUT1 RXID[0] VDDD VDDA RXID[1] RAGC_CONT GRX_IF1 GRX_IF2 CRX_IF1 VDDA VDDA VDDA Q_OFS I_OFS RXVCO_T1 RXVCO_T2 RXVCO_OUT2 SPI_CLK TCXO_in CHIPX8 RXQD[3] RXQD[2] RXQD[1] RXQD[0] VDDM RXID[3] RXID[2] VDDA S1M8662A (Top View) GND SLUG 8 9 19 17

S1M8662A ( Preliminary) RX IF/BBA WITH GPS PIN DESCRIPTION Pin No Symbol I/O Description 1 VDDD P Power for the digital logic. 2 VDDA P Power input terminal for the analog circuit. 3 RAGC_CONT AI AGC gain control input. The input voltage is allowed up to VDDA. It remains at High impedance during SLEEP. GRX_IF1 GRX_IF2 AI GPS IF input terminals, which have an input impedance of about 865W; generally, the GPS IF SAW filter is connected to them. When these terminals are not used, they remain at High impedance. CRX_IF1 CRX_IF2 AI CDMA IF input terminals, which have an input impedance of about 865 Ω ; generally, the CDMA IF SAW filter is connected to them. When these terminals are not used, they remain at High impedance. 8 VDDA P Power input terminal for the analog circuit. 9 TCXO_out DO TCXO Clock output. division ratio : 1 10 VDDA P Power input terminal for the analog circuit. 11 VDDA P Power input terminal for the analog circuit. Q_OFS I_OFS AI Control DC input for removing the DC offset generated in the S1M8662A and system during CDMA and GPS Mode. The control DC is generated in the modem in PDM form, passes through the R-C filter and is converted to DC, which is sent to this input terminal. RXVCO_T1 RXVCO_T2 AI Very sensitive terminal, which is connected to the oscillation L-C resonance circuit. Their impedance are about 2k Ω 16 VDDA P Power input terminal for the analog circuit. RXVCO_OUT1 RXVCO_OUT2 AO Output for the PLL, able to output about -12dBm. When this is not used, it remains at high impedance. 19 SPI_STB DI 3-Line serial control. Strobe input port. If this pin is opened, it remains at Low. 20 SPI_DATA BI 3-Line serial control. DATA input/output port. If this pin is opened, it remains at Low. 21 SPI_CLK DI 3-Line serial control. CLOCK input/output port. If this pin is opened, it remains at Low. 22 TCXO_in AI/DI Reference frequency input terminal connected to the VCTCXO output. When this pin stops, only DC bias is delivered to maintain the DC charge value of the capacitor connected externally 23 CHIPx8 DI CHIPx8 Clock input port. CDMA/GPS ADC sampling clock from the MSM.

edge, the data are latched at the falling edge in the modem.

28 VDDM DI Power source for a logic circuit ,related to the digital input /output,

connected to an external digital logic such as the modem. data are latched at the falling edge in the modem. Table 1. S1M8660A and S1M8662A Function & Control Content Comparison

S1M8662A ( Preliminary) RX IF/BBA WITH GPS ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Power supply V CC -0.5 to 3.6V Storage temperature T STG -55 to +125 °C Operating temperature T OPR -30 to +85 °C Storage temperature HBM TBD Electrostatic discharge rating MM TBD RECOMMENDED OPERATING CONDITIONS Characteristic Symbol Value Power supply V DDA , V DDD 2.7 to 3.3V V DDM 2.4 to 3.3V Ambient operating temperature Ta -30 to +85 °C

ELECTRICAL CHARACTERISTICS

Electrical Characteristics(V CC = 3.3V, Ta = 25 °°C) Characteristic Test Conditions Symbol Min Typ Max Units Current consumption CDMA idle mode ICRX - 23 30 mA Current consumption CDMA sleep mode ICSLP - 300 650 uA Current consumption CDMA slot mode ICSLT - 5 7 mA Current consumption GPS idle mode IGPS - 24 31 mA Logic high input V IH V DDM -0.4 - - V Logic low input V IL - - 0.4 V Logic high output V OH V DDM -0.4 - - V Logic low output V OL - - 0.4 V Digital input capacitance C DI - - 5 pF Digital output load capacitance C DOL - - 10 pF TCXO input impedance Attach C = 2pF Z TCXO 10 - - k Ω VCO input resistance IF VCO differential R VCO - 2.0 - k Ω VCO input capacitance IF VCO differential C VCO - - 2 pF

RX IF/BBA WITH GPS S1M8662A ( Preliminary) AC Characteristics Characteristic Test Conditions Symbol Min Typ Max Unit CDMA Performance Input sensitivity Maximum AGC gain. Control input signal so that output corresponding to 3LSB is output from ADC. VCSEN -102 - - dBm Maximum input signal Minimum AGC gain. Control input signal so that output corresponding to 3LSB is output from ADC. VCMAX - - -12 dBm AGC gain slope PDM 3.3V Mode GS LOPE 43 50 57 dB/V AGC gain error over temperature -30 to +85 °C. GVAR -3 - 3 dB IF input frequency range Cin < 2pF Fin - - 250 MHz IF input Impedance Zin 0.8 1.0 1.2 k Ω Input power = -102dBm NFmin - - 7 dB Noise figure Input power = -75dBm NFmid - - 20 dB Input power = -25dBm NFmax - - 72 dB IIP3 AGC gain Max. IIP3max -53 - - dBm AGC gain Min. IIP3min -10 - - dBm Spurious contents ADC generated harmonic frequency component. Two signals in the in-band are each mixed with signals which will allow ADC to produce -7dB output signals. The harmonic and non-harmonic components of the ADC output signals between 1kHz to 20MHz are extracted and added. The AGC control voltage is controlled so that ADC output is full scale when the input signal is -80dBm. TSpur - - -25 dBc Spurious content related to jammer In-band spurious peak value produced by IMD based on 2 jammer signals. One in-band signal(@50kHz,0.5*F/S) and two jammers(@900kHz, 22dB*F/S and @1.7MHz, 21dB*F/S)are simultaneously input. AGC control voltage is controlled so that ADC output is F/S when the input signal is -80dBm. Jspur - - -18.4 dBc

S1M8662A ( Preliminary) RX IF/BBA WITH GPS AC Characteristics (Continued) Characteristic Test Conditions Symbol Min Typ Max Unit Single-tone jammer desense Overall gain reduction due to one jammer. The in-band signal at -97dBm (control the AGC control voltage to 0.5*F/S)and the jammer signal at 900kHz and -57dBm are simultaneously input. Jdsen - - 1.0 dB Residual Sideband RSB k k k k= + + + −20 1 2 1 2 2log cos cos q q k : Linear Gain Mismatch q : Phase Mismatch in Deg. RSB 22 dB Offset gain slope Amount of code change of the voltage ADC output at the I/Q offset control GOFS - 250 - %FS/V Offset adjust input impedance - Zoff 100 - - k Ω Out-band ≥ 900kHz ATC9 46 - - dB attenuation ≥ 1.2MHz ATC12 48 - - dB Gain flatness Amount of gain change along I and Q paths between 1kHz to 615kHz Gft -1 1 dB IF VCO pertormance VCO and buffered output Frequency range VCO external time constant and PLL value Fvco - 170 500 MHz VCO phase noise Tank LC's Q value should be above 20. Measure @100kHz away from the mid- frequency. Pvco - - 104 dBc/Hz RXVCO_OUT output power Select a VCO buffer output value reduced by -2dB. Connect output load to 50 Ω . Ovco -15 - - dBm

RX IF/BBA WITH GPS S1M8662A ( Preliminary) AC Characteristics (Continued) Characteristic Test Conditions Symbol Min Typ Max Unit GPS Performance Input sensitivity Maximum AGC gain. Control input signal so that ADC outputs 0.5*F/S. VCSEN -102 - - dBm Maximum input signal Minimum AGC gain Control input signal so that ADC outputs 0.5*F/S. VCMAX - - -12 dBm AGC gain slope PDM 3.3V Mode GSLOPE 43 50 57 dB/V AGC gain error over temperature -30 °C to +85 °C. GVAR -3 - 3 dB IF input frequency range Cin < 2pF Fin - - 250 MHz IF input Impedance Zin 0.8 1.0 1.2 k Ω Input power = -98dBm NFmin - - 7 dB Noise figure Input power = -75dBm NFmid - - 12 dB Input power = -25dBm NFmax - - 58 dB IIP3 AGC gain Max. IIP3max -53 - - dBm AGC gain Min. IIP3min -25 - - dBm Offset gain slope Amount of code change of the voltage ADC output at the I/Q offset control GOFS 250 %FS/ V Offset adjust input impedance - Zoff 100 - - k Ω Out-band ≥ 1.3MHz ATC13 46 - - dB attenuation ≥ 1.7MHz ATC17 48 - - dB Residual Sideband RSB k k k k= + + + −20 1 2 1 2 2log cos cos q q k : Linear Gain Mismatch q : Phase Mismatch in Deg. RSB 22 - - dB Gain flatness Amount of gain change along I and Q paths between 1kHz to 800kHz Gft -1.5 - 1.5 dB

analog baseband signal it receives. An on-chip VCO creates a multiple frequency(x2, x3, x4, x6) LO signal. temperature between -30 to +85 °C. independent PLL device is used to generate its exact oscillation mid-frequency. Figure 4. Received I/Q Phase in S1M8662A

The difference of the S1M8662A from the S1M8656A is that S1M8662A provides GPS receiving operation. is the same as depicted in Figure 5. GPS lowpass filter of S1M8662A has its cut off frequency at around 800kHz. A-D converter, as output of GPS path, is the 4bit parallel converter which is the same one used in CDMA path. of A-D converter should be supplied from the modem. TCXO control ( TCXO_cont) at the same time. Figure 5. TCXO Clock Generating (floating), S1M8662A can be pin to pin compatible with IFR3500 of Qualcomm.

500MHz, suggesting that the maximum input IF frequency is 250MHz. the modem is the master and S1M8662A the slave. Each pin which uses the SPI bus has the following common functions.

• The STB(STROBE) for the serial bus start signal is used to initialize serial data transmission.
• Serial BUS DATA is used for the bi-direction data input /output at serial data transmission. Because it is an open drain type pin, it requires the pull-up resistance of approx. 8k Ω .
• Serial BUS CLK is used to synchronize the data input/output at serial data transmission. Serial Port Interface Operation The modem, the master, controls slaves such as S1M8662A using the SPI bus. The STB falling edge indicates the start of the serial I/F data transmission. The STB becomes high to mark the end of the data transmission. (Data sent after the STB turns high are not valid.) Serial line data is captured and stored as soon as the BBA or the MODEM places the clock on the falling edge. The SPI 3-line must remain high for at least 1-clock cycle in order to sent new data. The MSB always outputs the data line data. After 9-clocks, which is required to send data, the data line driver opens the data line, at which time the data line becomes high because of the external pull-up resistance. Serial Data Transfer format S1M8662A and S1M8657 are all slave devices with the SPI bus. What differentiate them from one another is their different device IDs. Each company has its own characteristic SPI bus configuration , but normally the 3-line bus is most often used and sometimes the 2-line bus such as the IIC bus.

Figure 7. shows the serial data transfer format.

Figure 6. Serial Data Transfer Format (2) The following 6-bit data specifies the slave device, which is connected to the SPI bus and has its own ID. master will drive , but if '0' the slave will drive the data line. 128 register addresses for slaves. (6) The following high 1-BIT data is a dummy data. (7) The following 8-BIT data is the data in the device to be driven. beginning of the next data to be sent. master will drive , but if '0' the slave will drive the data line. (10) The following 7-bit data is the register address of the specified slave device. (11) The following high 1-BIT data is a dummy data. (12) The following 8-BIT data is the data in the device to be driven. (15) and the STB becomes high as soon as the clock becomes high and this marks the end of data transmission.

S1M8662A can be controlled by the SPI bus. Table 2 shows the various modes. Table 2. Mode control in the DC control mode

function which are described below. Table 3. S1M8660A Control Registers FILTER_SEL. 0x05 R/W 0x1C. FILTER_SEL. VCO_CTL 0x06 R/W 0x0B VCO_CTL. Controls the VCO operation and VCO output. Table 4. Description of Control Registers when there are many slaves connected to the SPI bus.

Table 4. Description Of Control Registers (Continued)

Figure 9. S1M8662A IF VCO Open Loop Phase Noise

Figure 12. Test Circuit

S1M8662A ( Preliminary) RX IF/BBA WITH GPS PACKAGE DIMENSION 32BCC+ Package Outline #25 #17 #1 #9 #1 Index Laser Mark 5.00 + 0.10 5.00 + 0.10 5.00 + 0.10 0.075 + 0.025

0.80 MAX

0.30 + 0.1 0.50 + 0.1 0.45 + 0.1 3.10 + 0.1 3.50 + 0.1 5.0 + 0.1