FOA3251B1 INFINEON | Alldatasheet
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Data Sheet, V1.0, Aug. 1999 Never stop thinking. FOA3251B1 High Speed Clock and Data Recovery for Fiber Optic Applications ICs for Communications
Published by Infineon Technologies AG, St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2002. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life-support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com. ABM , AOP , ARCOFI , ARCOFI -BA, ARCOFI -SP, DigiTape , EPIC -1, EPIC -S, ELIC , FALC 54, FALC 56, FALC -E1, FALC -LH, IDEC , IOM , IOM -1, IOM -2, IPAT -2, ISAC -P, ISAC -S, ISAC -S TE, ISAC -P TE, ITAC , IWE , MUSAC -A, OCTAT -P, QUAT -S, SICAT , SICOFI , SICOFI -2, SICOFI -4, SICOFI -4µC, SLICOFI are registered trademarks of Infineon Technologies AG. ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG. FOA3251B1 S1028C1 Revision History: 1999-08 V1.0 Previous Version: Page Subjects (major changes since last revision) Document’s layout has been changed: 2002-Sep.
Data Sheet 3 V1.0, 1999-08 Preface The transceiver IC FOA3251 is designed for fibre optic application in the data bit range of 2.5 GBit. The FOA3251 fulfills the jitter requirements specified in ITU G958 and Bellcore GR253. Organization of this Document This Data Sheet is divided into 8 chapters. It is organized as follows: Chapter 1, Overview Gives a general description of the product , lists the key features, and presents some typical applications. Chapter 2, Functional Description Lists pin locations with associated signals, categorizes signals according to function, and describes signals. Blockdiagram and block description. Chapter 3, Operational Description Chapter 4, Electrical Characteristics DC and AC Characteristics, Power consumption, interface specification. Chapter 5, External Components Application notes and recommended suppliers Chapter 6, Measurement Results Chapter 7, Package Outlines
Data Sheet 4 V1.0, 1999-08
Data Sheet 5 V1.0, 1999-08 High Speed Clock and Data Recovery for Fiber Optic Applications FOA3251B1 S1028C1 BIPOLAR P-LQFP-48-1P-LQFP-48-1 Type Ordering Code Package FOA3251B1 P-LQFP-48-1
1 Overview
The transceiver IC FOA3251 is designed for fibre optic application in the data bit range of 2.5 GBit. The FOA3251 fulfills the jitter requirements specified in ITU G958 and Bellcore GR253.
1.1 Features
Data rate up to 2.633 Gb/s All jitter data meet ITU-T G958 and GR-253-Core requirements Supply range from +3.0 V to 5.0 V Supply current < 210 mA Input sensitivity < 5 mVpp differential (BER = 10 -12 Loss of signal (LOS) detection Programmable delay element to adjust clock- to data output Lock indication
1.2 Applications
Fibre optic communication systems SDH / SONET / ATM applications
Data Sheet 6 V1.0, 1999-08
2 Functional Description
The FOA3251 consists of a clock and data recovery block (CDR), a clock multiplier unit (CMU) and a programmable delay line.
2.1 Pin Configuration (top view)
Figure 1 Pin Configuration VCC ITP11416TESTCLK V EE VCC DELAY0V CC alarm LOLLOSRESETXTAL INXTAL OUTV CC V CC DELAY1DELAY2 N2V5 LLOS P-LQFP-48-1 DATA IN VCC DATA IN VCC VCC PLL1 UP PLL1 DN TEST V CC TESTLOS V CC V CC V CC V CC PLL2 DNPLL2 UP V CCLC V EELC VCC VCC CLK TR CLK TR VCC DATA TR DATA TR VCC VCC VEE VEE 11 2 36 25 23456789 1 0 1 1 26272829303132333435 V F02 VF01
Data Sheet 7 V1.0, 1999-08
2.2 Pin Definition and Function
Table 1 Pin Definition and Function Pin Symbol Input (I) Output (O) Function
1 TESTCLK In Clock signal for test mode only
3 VCC
4 VCC Can be open. 5 VCC Can be open.
6 VCC
7 VCC In Can be open.
8 PLL2 DN Out Inverted down signal from PLL2
9 PLL2 UP Out Inverted up signal from PLL2
10 VF02 In Control voltage for VCO2
11 VCCLC VCC VCO2
12 VEELC VEE VCO2
13 VEE
14 VEE
15 VCC
16 VCC
17 DATA TR Out Inverted recovered data signal
18 DATA TR Out Recovered data signal
19 VCC
20 CLK TR Out Recovered clock signal
21 CLK TR Out Inverted recovered clock signal
22 VCC
23 VCC
24 VCC
25 DELAY0 In Delay select bit 0. (See Table 2) 26 DELAY1 In Delay select bit 1. (See Table 2) 27 DELAY2 In Delay select bit 2. (See Table 2)
28 VCC
Data Sheet 8 V1.0, 1999-08
29 VCC
30 XTAL OUT Out Crystal
31 XTAL IN In Crystal
32 RESET In Reset for test mode only
33 LOS Out Loss of signal (ESD only to VEE)
34 LOL Out Loss of Lock
35 VCC alarm VCC alarm supply. Max. 5 V, Min 0 V = VCC (no ESD)
36 VEE
37 LLOS In Adjustment for Level LOS
38 N2V5 In Negative supply voltage for VCO1
39 VCC
40 DATA IN In Inverted data input (no ESD)
41 VCC
42 DATA IN In Data input (no ESD)
43 VCC
44 VF01 In Control voltage VCO1
45 VCC
46 PLL1 UP Inverted up signal PLL1
47 PLL1 DN Inverted down signal PLL1
48 TEST In Test mode on/off
Table 1 Pin Definition and Function (cont’d) Pin Symbol Input (I) Output (O) Function
Data Sheet 9 V1.0, 1999-08
2.3 Functional Block Diagram
2.4 Functional Block Description
The clock and data recovery block (CDR) consists of a bang-bang phase detector (PD), a frequency window detector (FWD) and a VCO. The PD also provides a kind of statistical BER signal that is used to generate a loss of signal (LOS) signal. The FWD moves the VCO in the right frequency range. The frequency window is about 10000 ppm of the center frequency. When the frequency is out of range a los of lock signal (LOL) is generated. The center frequency is given by a reference clock signal which is (signal frequency)/128. The VCO is a 3 stage ring oscillator type. The clock multiplier unit (CMU) consist of a phase frequency detector (PFD), a VCO and a retiming Flip-Flop. The PFD is type 4 phase and frequency detector. The low pass filtered PFD signal as a function of the phase error is shown in Figure 3. ITB11417 FWD VCO PD Loop Filter CDR D C PFD Loop Filter VCO CMU Delay Line DATA REFCLK TRDATA TRCLK Recovered DATA Recovered Clock LOS LOL Postamp
Data Sheet 11 V1.0, 1999-08
3 Operational Description
3.1 Operating States of Delay Line
For clock to data output adjustment a adjustable delay line is available. The clock output signal is adjustable by the signals DELAY0..2. Table 2 Truth Table Delay Line DELAY0 DELAY1 DELAY2 Delta LOW LOW LOW 0 ps LOW HIGH LOW 50 ps LOW LOW HIGH 100 ps LOW HIGH HIGH 150 ps HIGH LOW LOW 200 ps HIGH HIGH LOW 250 ps HIGH LOW HIGH 300 ps HIGH HIGH HIGH 350 ps
Electrical Characteristics
Data Sheet 12 V1.0, 1999-08
4 Electrical Characteristics
4.1 Absolute Maximum Ratings
The RF Pin 40, 42 are not ESD protected. The high frequency performance prohibits the use of a adequate protective structure. Pin 33 is only protected to VEE.
4.2 Operating Range
Table 3 Absolute Maximum Ratings Parameter Symbol Limit Values Unit min. max. IC supply voltage (VCC - VEE)6 V Voltage on any pin VS -0.4 VDDP + 0.4 Maximum junction temperature 125 °C Storage temperature Tstg -40 150 Protection supply voltage VDDP VEE - 0.5 VCC V ESD robustness HBM: 1.5 kΩ, 100 pF VESD,HBM 500 Lead temperature range Package Table 4 Operating Range Parameter Symbol Limit Values Unit min. max. Ambient temperature TA -40 85 °C Supply voltage VDD 3.0 5 V
Data Sheet 13 V1.0, 1999-08
4.3 DC Characteristics
4.4 AC Characteristics
Table 5 DC Characteristics Parameter Symbol Limit Values Unit min. max. Control and Test inputs VIL VIH VCC - 1 VCC V Output current CML Pin 17, 18, 20, 21 Ioc 80 . 4 5 m A Supply current IEE (AV) 200 TBD mA Table 6 Electrical Characteristics Parameter Condition Limit Values Unit min. typ. max. Quantisizer DC Characteristics Pin or Nin VEE +2.5 VCC V Input Voltage Range Pin-Nin, BER < 10 -12 10 mV Input Sensitivity, Vsense Pin-Nin, BER < 10 -12 V Input Overdrive, Vod 2m V Input Offset Voltage 10 µA Input Current Input RMS Noise BER < 10 -12 TBD µV Input Pk-Pk Noise BER < 10 -12 TBD Quantisizer AC Characteristics 2.5 GHz Upper -3 dB Bandwidth extern) 50 Ω Input Resistance Package 0.8 pF Input Capacitance Pulse Width Distortion VSWR 2.5
Data Sheet 14 V1.0, 1999-08 Level Detect Response Time AC coupled 95 µs Hysteresis (Electrical) 13 d b ALM Output Logic High VCC alarm = 5 V 4.5 V ALM Output Logic Low VEE alarm = GND 1 ALM Output Logic High VCC alarm = GND -0.5 ALM Output Logic Low VEE alarm = -5 V -4 Phase-Locked Loop Nominal Center Frequency f0 2.48832 GHz Capture Range -0.2% x f0 +0.2% x f0 GHz Tracking Range -0.2% x f0 +0.2% x f0 Static Phase Error -3.6 +3.6 deg. Phase drift
100 Bit
Jitter SONET STS-48 Frame (with Scrambler 2E7-1) and 2E23-1 PRN Sequence ITU-T G958 and Gr-253-Core objective < 0.005 UIrms (2ps) Jitter Tolerance SONET STS-48 Frame (with Scrambler 2E7-1) and 2E23-1 PRN Sequence ITU-T G958 and Gr-253-Core Jitter Transfer SONET STS-48 Frame (with Scrambler 2E7-1) and 2E23-1 PRN Sequence ITU-T G958 and Gr-253-Core Open collector output Referenced to VCC Voltage levels Output logic High, Voh 0V Output logic Low, Vol 400 V Symmetry (Duty Cycle) Recovered Clock Output 46 54 Table 6 Electrical Characteristics (cont’d) Parameter Condition Limit Values Unit min. typ. max.
Data Sheet 15 V1.0, 1999-08 Output Rise/Fall Times Clock Output Rise Time 20% - 80%, 50 Ω 100 ps Fall Time 20% - 80%, 50 Ω 100 ps Data Output Rise Time 20% - 80%, 50 Ω 120 ps Fall Time 20% - 80%, 50 Ω 120 ps Control and test inputs Referenced to VCC Input logic High, Vih 0V Input logic Low, Vil -1 V Control and test outputs Referenced to VCC Output logic High, Vih 0V Output logic Low, Vil -1 V Power Supply Voltage 3 5 5.8 V Power Supply Current 210 mA Operating Temperature Package Ambient -40 +85 °C Bare Chip Ambient -40 +100 °C Bare Chip Size < 3.0 mm x 3.0 mm Min value Pin, Nin: VCC-Pin, Nin < 800 mV Voltage (Pin-Nin) = 4 mVpp @Pin = -23 dBm Hysteresis can be installed by a combination of Signal LOS and LLOS. Open Collector Output type, I = 2 mA. Datarate depends on output load. Termination with pullup resistor > 4.7 kΩ No skipping clock cycles allowed down to < 10 BER External adjustable. Clock drift with no input 25 MHz The alarm shall be asserted before 500 ns of phase shift on the RX clock is realized. Consecutive identical bits 72 bits. Supply current = IEE ( current without ECL output current). Table 6 Electrical Characteristics (cont’d) Parameter Condition Limit Values Unit min. typ. max.
Data Sheet 16 V1.0, 1999-08
5 External Components
Figure 5 External Components Required for Operation of FOA3251B1 The external circuits are shown in Figure 6, Figure 7, Figure 8 and Figure 9. Table 7 External Devices Device Number Recommended Types Remark Reference Voltage 1 - 2 TL 431 2.5 V VCO Supply Operational Amplifier 1 Burr Brown OPA2353 Burr Brown OPA2350 Integrator Capacitor 10 Integrator, Blocking Resistor 14 Integrator, Reference voltage Crystal Oscillator 1 Toyocom TSX-2 19.44 MHz Ferrite Bead Inductor 2 muRata BLM11B601S VEE blocking to GND (VCC) ITS11420 IntegratorCrystal Data IN Integrator Data OUT Reference Voltage Clock OUT Infineon - FOA3251B1
2.488 Gb/s Transceiver and Clock/Data Recovery
Data Sheet 17 V1.0, 1999-08 Figure 6 Reference Voltage for VCO (Ring Oscillator). Figure 7 Loop Filter PLL1 (CDR) ITS11421 VCC 100 nF TL431 2, 3 6, 7 10 µF N2V5 VEE Resistor has to be adapted to supply voltage.
3.3 V 56
5.0 V 80
2.5 V Referenz Voltage
Data Sheet 19 V1.0, 1999-08
6 Measurement Results
All measurements were done with 50 mVpp input swing and a 2E23 bit sequence. Temperature was 25°C, supply voltage was 3.3 V. Figure 10 STM 16 Jitter Tolerance Figure 11 STM 16 Jitter Transfer ITD11425 101 10-1 102 103 104 105 106 107 100 101 102 Modulation Frequency Hz ITD11426 101 -30 102 103 104 105 106 107 Modulation Frequency Hz -20 -10
Data Sheet 20 V1.0, 1999-08 Figure 12 Gitter Generation Results ITD11427 Jitter Generation Results Cutoff Frequency = 12.000 kHz 16.281 mUI p-p 2.516 mUI rms
Data Sheet 21 V1.0, 1999-08
7 Package Outlines
0.22 0.08 A ±0.05 D 71) 0.5 5.5 A-B A-B0.21) B A-BM 0.2 D 4xDH 48x D C 48x 0.08 1.6 MAX. C 0.1 1.4 ±0.05 ±0.05 Heatslug 7˚ MAX. ±0.053.96 1.76 x 45˚ H 0.6 +0.075 -0.0350.125 ±0.15 Does not include dambar protrusion of 0.08 max. per side Does not include plastic or metal protrusion of 0.25 max. per side P-LQFP-48-1 (Plastic Low Profile Quad Flat Package) GPP09269 You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm
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Data Sheet 23 V1.0, 1999-08 Variables Target Specification Variable Name Variable Definition Description Business Unit ICs for Communications Dev_NameLong1 High Speed Clock and Data Recovery for Fiber Optic Applications Long product name Dev_NameLong2 Dev_NameLong3 Dev_NameLong4 <Dev_NameLong4> Dev_NameShort1 FOA3251B1 Short product name Dev_NameShort2 <Dev_NameShort2> Dev_NameShort3 <Dev_NameShort3> Dev_NameShort4 <Dev_NameShort4> Dev_Package1 P-LQFP-48-1 Package type Dev_Package2 <Dev_Package2> Dev_Package3 <Dev_Package3> Dev_Package4 <Dev_Package4> Dev_Version1 <Dev_Version1> Device version Dev_Version2 <Dev_Version2> Dev_Version3 <Dev_Version3> Dev_Version4 <Dev_Version4> Device1 FOA3251B1 Marketing/sales name Device2 <Device2> Device3 <Device3> Device4 <Device4> Doc_Author <Author> Author of the document Doc_ConfidentialStatus „CONFIDENTIAL“, “PRELIMINARY” or left blank
Data Sheet 24 V1.0, 1999-08 Doc_Distribution "Distribution with NDA" or "Distribution by marketing only" or "Distribution with NDA by marketing only" or left blank Doc_IssueDate 1999-08 Complete date of releasing the document Doc_State V1.0 Revision state of the document Doc_TopRight1 FOA3251B1 Defines the expression appearing on the top right of the page layout Document type Doc_TopRight2 S1028C1 Doc_Type Data Sheet Document type Doc_Type_Cover Data Sheet Document type Modification Date Short Status Technologie BIPOLAR Title_IssueDate Aug. 1999 Issue date of the document appearing on the upper right corner of the 1st cover page Variable Name Variable Definition Description
Data Sheet 25 V1.0, 1999-08 Instructions Defining all variables 1. Double-Click on the Variable Definiton that you want to define. 2. Choose “Edit Definition” 3. In the variable dialog box redefine the user variable in the “Definition” box. If this variable should not be defined, enter a blank. 4. Click on “Change”. 5. Click “Done” to return to the variable dialog box. 6. Click “Done” again. Importing the variables into the FrameMaker document/book 1. Make certain that both documents (your FrameMaker file/book and file variables.fm) are open. 2. From the “File” menu, click on “Import”. 3. Select “Format”. 4. From the “Import from File” (document) pop-up list, choose “variables.fm”. 5. From the “Import and Update” box, make sure that only the “Variable Definition” check box is selected. Click on “Import” to finish.