RP510L

RP510L NISSHINBO | Alldatasheet

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Technical content

4 A Forced PWM Step-down DC/DC Converter with Synchronous Rectifier

No. EA-366-190515 The RP510L is a low input voltage step-down DC/DC converter that operates from 2.5 V to 5.5 V and provides up to 4 A of output current (1). It is suitable for power supply of SoC (System-on-a-chip). It is also available in a foldback type overcurrent protection which automatically recovers to the normal state after the cause of overcurrent is removed.

• The realization of the high-density mounting by the adoption of a small package DFN3030-12.
• A simplification of the power sequencing by power-good and adjustable soft-start functions.
• Selectable overcurrent protection: Latch type or Foldback type.
• Operating Temperature Range: −40°C to 85°C
• Output Voltage Range(2): 0.8 V to 3.3 V
• Output Voltage Accuracy(3) : ±1% (VSET ≥ 1.2 V), ±12 mV (VSET < 1.2 V)
• Feedback Voltage Accuracy(4) : ±6 mV (VFB = 0.6 V)
• Output/Feedback Voltage Temperature Coefficient: ±100 ppm/°C
• Standby Current: Typ.0.35 µA (RP510LxxN) Typ.0.01 µA or less (RP510LxxG/H/J)
• Oscillator Frequency: Typ. 2.3 MHz
• Maximum Duty Cycle: Min. 100%
• Minimum On Time: Typ. 55 ns
• Protection Features: UVLO, LX Peak Current Limit, Overcurrent protection (Latch/Foldback type), and Thermal shutdown. VOUT = 1.2 V, VIN = 3.3 V/5.0 V (Ta = 25°C) DFN3030-12 3.0 x 3.0 x 0.8(1) mm (1) maximum dimension RP510L001G/1H/4G/4H (Adjustable Output Voltage Type)
• POL (Point of Load) Converter, and Micro-processor Power Supply with using Battery
• Server, Networking Equipment, FPGA, and DSP (1) The maximum allowable output current is 4 A but it is a criterion and can be affected by conditions and external parts. (2) Refer to the section SELECTION GUIDE for details of VSET. (3) Fixed Output Voltage Type (4) Adjustable Output Voltage Type OVERVIEW KEY SPECIFICATIONS TYPICAL CHARACTERISTICS TYPICAL APPLICATION CIRCUIT PACKAGE

APPLICATIONS

C P V IN PG L X L X AGND P GND V IN V OUT L µ H RP5 L CE V FB TSS C IN µ F PV IN A V IN P GND R R C OUT µ F C OUT µ F R AVIN Ω C AVI N 0.01µF

No. EA-366-190515 SELECTION GUIDE The set output voltage, the output voltage type, the auto-discharge function(1), and the protection type are user- selectable options. Selection Guide Product Name Package Quantity per Reel Pb Free Halogen Free RP510Lxx$$-TR DFN3030−12 3,000 pcs Yes Yes xx: Set Output Voltage (VSET). Adjustable Output Voltage Type: 00 (0.8 V to 3.3 V) $$: Other Functions Version Output Voltage Type Auto-discharge Function Oscillator Frequency Protection Type RP510Lxx1G Fixed No

2.3 MHz

(1) Auto-discharge function quickly lowers the output voltage to 0 V, when the chip enable signal is switched from the active mode to the standby mode, by releasing the electrical charge accumulated in the external capacitor.

No. EA -366-190515 BLOCK DIAGRAM RP510Lxx1G/4G/1H/4H (Fixed Output Voltage Type) CE PVIN AGND LX Chip Enable Ramp Compensation Current Feedback Current Detector Switching Control UVLO OSC Vref VOUT Soft Start PGND Thermal Protection AVIN TSS (“L” during Soft Start) PG Over /Under Voltage Detection OVD UVD RP510Lxx1G/ 4G Block Diagram CE PVIN AGND LX Chip Enable Ramp Compensation Current Feedback Current Detector Switching Control UVLO OSC Vref VOUT Soft Start PGND Thermal Protection AVIN TSS (“L” during Soft Start) PG Over /Under Voltage Detection OVD UVD RP510Lxx1H/ 4H Block Diagram

No. EA-366-190515 RP510L001J/4J/1N/4N (Adjustable Output Voltage Type) CE PVIN AGND LX Chip Enable Ramp Compensation Current Feedback Current Detector Switching Control UVLO OSC Vref VFB Soft Start PGND Thermal Protection AVIN TSS (“L” during Soft Start) PG Over /Under Voltage Detection OVD UVD RP510L001J/ 4J Block Diagram CE PVIN AGND LX Chip Enable Ramp Compensation Current Feedback Current Detector Switching Control UVLO OSC Vref VFB Soft Start PGND Thermal Protection AVIN TSS (“L” during Soft Start) PG Over /Under Voltage Detection OVD UVD RP510L001N/ 4N Block Diagram

No. EA -366-190515 PIN DESCRIPTION DFN3030-12 Pin Configurations DFN3030-12 Pin Description Pin No. Pin Name Description

1 PVIN (1) Input Voltage Pin

2 PVIN (1) Input Voltage Pin

3 AVIN (2) Input Voltage Pin

4 PG Power Good Pin, NMOS Open-drain

5 CE Chip Enable Pin, Active-high

6 TSS Soft-start Pin

7 VOUT/ VFB Output Voltage Pin / Feedback Voltage Pin

8 AGND (3) Analog Ground Pin

9 PGND (3) Power Ground Pin

10 PGND (3) Power Ground Pin

11 LX Switching Pin

12 LX Switching Pin

∗ The tab on the bottom of the package must be connected to the ground plane on the board to enhance thermal performance. (1) No.1 pin and No.2 pin must be wired to the VIN plane when mounting on boards. (2) No.3 pin must be wired to No.1 and No.2 pins via a low-pass filter (LPF: 1 Ω, 10 nF) when mounting on boards. (3) No.8 pin, No.9 pin and No.10 pin must be wired to the GND plane when mounting on boards. Top View Bottom View

No. EA-366-190515 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings (AGND = PGND = 0 V) Symbol Parameter Rating Unit VIN A/PVIN Pin Voltage −0.3 to 6.5 V VLX LX Pin Voltage −0.3 to VIN + 0.3 V VCE CE Pin Voltage −0.3 to 6.5 V VOUT/ VFB Output Voltage / Feedback Voltage −0.3 to 6.5 V VPG PG Pin Voltage −0.3 to 6.5 V VTSS TSS Pin Voltage −0.3 to VIN + 0.3 V PD Power Dissipation (1) DFN3030-12 JEDEC STD. 51-7 3400 mW Tj Junction Temperature Range −40 to 125 °C Tstg Storage Temperature Range −55 to 125 °C ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause permanent damage and may degrade the life time and safety for both device and system using the device in the field. The functional operation at or over these absolute maximum ratings are not assured. RECOMMENDED OPERATING CONDITIONS Recommended Operating Conditions Symbol Parameter Rating Unit VIN Input Voltage 2.5 to 5.5 V Ta Operating Temperature Range −40 to 85 °C RECOMMENDED OPERATING CONDITIONS All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating condition s. The semiconductor devices cannot operate normally over the recommended operating conditions, even if they are used over such conditions by momentary electronic noise or surge. And the semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions. (1) Refer to POWER DISSIPATION for detailed information.

No. EA -366-190515

ELECTRICAL CHARACTERISTICS

The specifications surrounded by are guaranteed by design engineering at −40°C ≤ Ta ≤ 85°C. RP510Lxx1/4 Electrical Caharacteristics (Ta = 25°C) Symbol Parameter Test Conditions/Comments Min. Typ. Max. Unit ISTANDBY Standby Current VIN = 5.5 V, VCE = 0 V RP510LxxxN 0.35 15.5 µA RP510LxxxG/H/J 0.01 7.5 RCE CE Pin Pull-down Resistance 1 MΩ ICEL CE Pin Input Current, Low VIN = 5.5 V, VCE = 0 V −1 0 1 µA ILXLEAKH LX Pin Leakage Current, High VIN = VLX = 5.5 V, VCE = 0 V −1 0 3 µA ILXLEAKL LX Pin Leakage Current, Low VIN = 5.5 V, VCE = VLX = 0 V -10 0 1 µA VCEH CE Pin Input Voltage, High VIN = 5.5 V 1.0 V VCEL CE Pin Input Voltage, Low VIN = 2.5 V 0.4 V tSTART1 Soft-start Time1 VIN = VCE = 3.6 V or VSET + 1 V, TSS = OPEN 75 150 300 µs tSTART2 Soft-start Time2 VIN = VCE = 3.6 V or VSET + 1 V, CSS = 0.1 µF 15 30 45 ms ILXLIM LX Current Limit VIN = VCE = 3.6 V or VSET + 1 V 5000 6500 mA tPROT Protection Delay Time VIN = VCE = 3.6 V or VSET + 1 V 0.5 1.5 5 ms VUVLO1 UVLO Threshold Voltage VIN = VCE,, Falling 2.1 2.2 2.3 V VUVLO2 VIN = VCE, Rising 2.2 2.3 2.4 V TTSD Thermal Shutdown Threshold Temperature, Detection Tj, Rising 165 °C TTSR Thermal Shutdown Threshold Temperature, Release Tj, Falling 115 °C RPGDIS PG Pin Low Output ON Resistance VIN = 3.6 V, VOUT = 0 V or VFB = 0 V 45 Ω fOSC Oscillation Frequency VIN = VCE = 3.6 V or VSET + 1 V 2.00 2.3 2.50 MHz All test items listed under Electrical Characteristics are done under the pulse load condition (Tj ≈ Ta = 25°C).

No. EA-366-190515 The specifications surrounded by are guaranteed by design engineering at −40°C ≤ Ta ≤ 85°C. RP510Lxx1G/1H/4G/4H Electrical Characteristics: Fixed Output Voltage Type (Ta = 25°C) Symbol Parameter Test Conditions/Comments Min. Typ. Max. Unit VOUT Output Voltage VIN = VCE = 3.6 V or VSET + 1 V VSET ≥ 1.2 V x0.99 x1.01 V x0.98 x1.02 VSET < 1.2 V −0.012 0.012 −0.024 0.024 ISS Supply Current VIN = VCE = 5.5 V 800 µA IVOUTL VOUT Pin Current, Low VIN = 5.5 V, VCE = VOUT = 0 V −1 0 1 µA VOVD OVD Voltage VIN = 3.6 V VSET × 1.2 V VUVD UVD Voltage VIN = 3.6 V VSET × 0.8 V RP510Lxx1G/4G: Auto-discharge Function Not Included IVOUTH VOUT Pin Current, High VIN = VOUT = 5.5 V, VCE = 0 V −1 0 1 µA RP510Lxx1H/4H: Auto-discharge Function Included RVOUTDIS VOUT Pin Discharge NMOS ON-resistance VIN = 2.5 V, VCE = 0 V, VOUT = 0.5 V 45 Ω RP510L001J/1N/4J/4N Electrical Characteristics: Adjustable Output Voltage Type Symbol Parameter Test Conditions/Comments Min. Typ. Max. Unit VFB Feedback Voltage VIN = VCE = 3.6 V 0.594 0.600 0.606 V 0.588 0.600 0.612 ISS Supply Current VIN = VCE = 5.5 V 800 µA IVFBH VFB Pin Current, High VIN = VFB = 5.5 V, VCE = 0 V −1 0 1 µA IVFBL VFB Pin Current, Low VIN = 5.5 V, VCE = VFB = 0 V −1 0 1 µA VOVD OVD Voltage VIN = 3.6 V 0.72 V VUVD UVD Voltage VIN = 3.6 V 0.48 V RP510L001N/4N: Auto-discharge Function Included RLXDIS LX Pin Discharge NMOS ON-resistance VIN = 2.5 V, VCE = 0 V, LX = 0.5 V 65 Ω All test items listed under Electrical Characteristics are done under the pulse load condition (Tj ≈ Ta = 25°C).

No. EA -366-190515 The specifications surrounded by are guaranteed by design engineering at −40°C ≤ Ta ≤ 85°C. RP510Lxx1G/1H/4G/4H Electrical Characteristics: Fixed Output Voltage Type Product Name VOUT [V] Ta = 25°C −40°C ≤ Ta ≤ 85°C

No. EA-366-190515 THEORY OF OPERATION Soft-start Starting-up with CE Pin The device starts to operate when the CE pin voltage (VCE) exceeds the threshold voltage. The threshold voltage is preset between CE “High” input voltage (VCEH) and CE “Low” input voltage (VCEL). The soft-start circuit also starts to operate after the device start-up. Then, after a certain period of time, the reference voltage (VREF) in the device gradually increases up to the specified value. Notes: Soft-start time (t START)(1) might not be always equ al to an actual turn- on speed of the output voltage. Please note that the turn-on speed could be affected by the power supply capacity, the output current, the inductance value, and the COUT value. VCEH Soft-start Time (tSTART) Internal Reference Voltage VCEL Threshold Level LX Voltage (VCE) (VREF) Soft-start Circuit operation starts. (VLX) Depending on Power Supply, Load Current, External Components (VOUT) Output Voltage CE Pin Input Voltage Timing Chart when Starting-up with CE Pin Starting-up with Power Supply After the power-on, the device starts to operate when V IN exceeds the UVLO released voltage (V UVLO2). The soft-start circuit also starts to operate. Then after a certain period of time, V REF gradually increases up to the specified value. Please note that the turn-on speed of VOUT could be affected by the following conditions. 1. Power supply capacity and Turn-on speed of VIN determined by CIN 2. Values of Inductor, Capacitor and Output current Output Voltage (VOUT) Input Voltage (VIN) VUVLO2 Internal Reference Voltage (VREF) VUVLO1 LX Voltage (VLX) VSET VOUT Depending on Power Supply, Load Current, External Components Soft-start Time (tSTART) Timing Chart when Starting-up with Power Supply (1) Soft-start time (tSTART) indicates the duration until the reference voltage (VREF) reaches the specified voltage after soft- start circuit’s activation.

No. EA -366-190515 Soft-start Time Adjustment Soft-start time (tSTART) of the RP510L is adjustable by connecting a soft-start time adjustment capacitor (C SS) between the TSS pin and GND. tSTART can be set from Typ. 0.15 ms as a lower limit. As the figure below shows, the TSS pin open. The capacitance value for required soft-start time (tSTART) can be calculated by the following equation. CSS [nF] = 3.5 × tSTART [ms] CSS vs. tSTART (Typ.) tSTART 30ms 15ms 3ms 0.15ms 0 470pF 0.01μF 0.047μF 0.1μF CSS Soft-start Time (tSTART) vs. Soft-start Time Adjustment Capacitor (CSS) Power Good Function If any condition as follows is detected, power good function with using Nch. open drain turns Nch. transistor ON and switches the PG pin to “Low”. After the condition is removed, the power good function turns Nch . transistor OFF and switches the PG pin back to “High”. The time until the Nch. transistor is turned OFF includes the release delay time of 0.05 ms (Typ.).

• CE = ”L” (Shutdown)
• UVLO
• Thermal Shutdown
• Over Voltage Detection (Typ.): VOUT > VSET x 1.2 V (RP510Lxx1G/1H/4G/4H) or VFB > 0.72 V (RP510L001J/1N/4J/4N)
• Under Voltage Detection (Typ.): VOUT < VSET x 0.8 V (RP510Lxx1G/1H/4G/4H) or VFB < 0.48 V (RP510L001J/1N/4J/4N)
• During the Latch Type Protecting operation Notes: When using the power good function, the resistance of PG p in (R PG) should be between 10 kΩ to 100 kΩ. The PG pin must be open or connected to GND if the power good function is not used.

No. EA-366-190515 Under Voltage Lockout (UVLO) If VIN becomes lower than V SET, the step-down DC/DC converter st ops the switching operation and ON duty becomes 100%, and then VOUT gradually drops according to VIN. If the VIN drops more and becomes lower than the UVLO detector threshold (V UVLO1), the UVLO circuit starts to operate, VREF stops, and Pch. and Nch. built-in transistors become the OFF state. As a result, V OUT drops according to the COUT capacitance value and the load. To restart the operation, V IN is required to be higher than V UVLO2. The timing chart below shows the voltage shifts of VREF, VLX and VOUT in response to variation of the VIN value. Notes: Falling edge (operating) and rising edge (releasing) waveforms of V OUT might be affected by the initial voltage of COUT and the output current of VOUT. Output Voltage (VOUT) Input Voltage (VIN) VUVLO2 Internal Reference Voltage (VREF) VUVLO1 LX Voltage (VLX) VSET VOUT Depending on Power Supply, Load Current, External Components Soft-start Time (tSTART) Timing Chart with Variations in Input Voltage (VIN) Current limit Function Current limit circuit supervises the inductor current flowing through the Pch. transistor in each switching cycle. If the current exceeds the LX current limit (I LXLIM, Typ.6.5 A), a Pch. transistor is turned off and the upper limit of the inductor peak current is imposed.

No. EA -366-190515 Latch Type Protection (RP510Lxx1G/1H, RP510L001J/1N) Latch type protection circuit latches Pch. and Nch. transistors in the OFF state and stops the operation of the step-down DC/DC converter when the over current status or the output voltage ( VOUT) / the feedback voltage (VFB) being dropped to the half of the setting voltage due to shorting continues for the protection delay time (tPROT). To release the latch type protection circuit, restart the device by inputting "Low" signal to the CE pin or making the supply voltage lower than VUVLO1. Protection Delay Time (tPROT) Lx Limit Current (ILXLIM) IL flowing through L Current flowing through Pch Tr. Lx Voltage (VLX) Protection Delay Time The timing chart below shows the voltage shift of VCE, VLX and VOUT when the device status is changed by the following orders: VIN rising → stable operation → high load → CE reset → stable operation → VIN falling → VIN recovering (UVLO reset) → stable operation. (1)(2) If the overcurrent flows through the circuit or the device goes into low VOUT condition due to short-circuit or other reasons, the latch type protection circuit latches Pch. and Nch. transistors in the OFF state after tPROT. Then, VLX becomes "Low" and VOUT turns OFF. (3) The latch type protection circuit is released by CE reset, which puts the device into "Low" once with the CE pin and back into "High". (4) The latch type protection circuit is released by UVLO reset, which makes VIN lower than VUVLO1. Input Voltage (VIN) VSET UVLO Detector Threshold (VUVLO1) CE Pin Input Voltage (VCE) VSET Threshold Level Lx Voltage (VLX) VSET Output Voltage (VOUT) UVLO Released Voltage (VUVLO2) (1) (2) Soft-start Time VSET Soft-start Time Soft-start Time Stable Operation Stable Operation Stable Operation Protection Delay Time Protection Delay Time UVLO Reset CE Reset Latch-type Protection Latch-type Protection (3) (4) Timing Chart

No. EA-366-190515 Foldback Protection (RP510Lxx4G/4H, RP510L004J/4N) If the device is in a state where an overcurrent is detected during protection delay time (tPROT) or a state where the output voltage (VOUT) or the feedback voltage (VFB) becomes lower than UVD detector threshold (VUVD) over about 20 µsec while the overcurrent is caused by an output short -circuit, the foldback protection is enabled. During the foldback protection, the inductor current is set to the upper limit of 1/2 of LX limit current (ILXLIM) and the lower limit of 0mA. During the foldback protection, the device alternately operates the following Pch. and Nch. transistor as follows: the Pch. transistor is turned ON until the inductor current reach the upper limit and the Nch. transistor is turned ON until the inductor current reach 0mA. Therefore, the switching frequency is decreased and the upper limit of the output current (IOUT_SHORT) during the foldback protection is limited to a current value calculated by the following equation. IOUT_SHORT = ILXLIM / 4 When the short-circuit and the overcurrent states are released and the output current (IOUT) becomes less than IOUT_SHORT, the output voltage reaches the set output voltage. Then, the foldback protection is released. And also, the foldback protection is released when the device is reset by inputting CE pin to “Low” or by decreasing the input voltage to less than the UVLO detector threshold (VUVLO1). If the foldback protection occurs by the short-circuit and the overcurrent states when IOUT exceed IOUT_SHORT, the device might not return to a normal state even if their states are released. Release of the foldback protection is required to reduce I OUT less than IOUT_SHORT or reset the device. Delay Time:Typ.20µsec LX limit Current (ILXLIM) Inductor Current Current for Pch. transistor LX Voltage (VLX) VOUT Voltage (VOUT) ILXLIM / 2 UVD Detector Threshold (VUVD) 0V Foldback Duration Foldback Protection Timing Chart at Low Output Voltage Note: The current limit function and the overcurrent limit protection of the latch / foldback type, as described above, becomes possible to provide a high degree of safety to the device, not to secure reliability. And, ILXLIM and tPROT could be easily affected by self -heating or ambient environment. If the V IN drops dramatically or becomes unstable due to short-circuit, protection operation and tPROT could be affected.

No. EA -366-190515 Reverse Current Limit Function The reverse current limit function supervises the current on the Nch. transistor in every switching. When an overcurrent more than the threshold current (Typ. -2.0 A) occur, the Nch. transistor is turned off to limit a lower of the inductor current. On the heavy-to-light load transient, the reverse current limit function may occur by the overcurrent. If this limit function occur, the reduction of the output voltage overshoot by reverse current will be limited.

No. EA-366-190515

APPLICATION INFORMATION

Conditions: Power Good enabled, Soft-start time of 30 ms PVIN PG LX LX AGND PGND VIN COUT1 22µF VOUT L 1µH RP510L CE VOUT TSS RPG 100kΩ CIN 22µF PG PVIN CSS 0.1µF AVIN PGND COUT2 22µF RAVIN CAVIN 0.01µF RP510Lxx1G/1H/4G/4H (Fixed Output Voltage Type) Typical Application Circuit Conditions: Power Good disabled, Soft-start time of 150 µs PVIN PG LX LX AGND PGND VIN VOUT L 1µH RP510L CE VFB TSS CIN 22µF PVIN AVIN PGND COUT2 22µF COUT1 22µF RAVIN CAVIN 0.01µF RP510L001J/1N/4J/4N (Adjustable Output Voltage Type) Typical Application Circuit Recommended External Components Symbol Descriptions CIN 22 μF, Ceramic Capacitor, CGA5L1X7R0J226M160AC (TDK) / C2012X6S0J226M125AB (TDK) COUT 22 µF x 2, Ceramic Capacitor, CGA5L1X7R0J226M160AC (TDK) / C2012X6S0J226M125AB (TDK) L 1.0 µH, Inductor, CLF7045NIT-1R0N-D (TDK) / SPM4012T-1R0M-LR (TDK) / VLS3012HBX-1R0M (TDK)

No. EA -366-190515 Cautions in selecting external components

• Choose a low ESR ceramic capacitor. The input capacitor (CIN) between PVIN and PGND should be more than 22 µF, and the output capacitor (COUT) should be used by two or more parallel connection with ceramic capacitor of 22 µF.
• The phase compensation of this device is designed according to the C OUT and L values. The inductance value of an inductor should be 1.0µH to gain stability.
• Choose an inductor that has small DC resistance, has enough permissible current and is hard to cause magnetic saturation. If the inductance value of the inductor becomes extremely small under the load conditions, the peak current of LX may increase along with the load current. As a result, the overcurrent protection circuit may start to operate when the peak current of LX reaches to LX limit current. Therefore, choose an inductor with consideration for the value of I LXMAX. See the following page of Calculation Conditions of LX Pin Maximum Output Current (ILXMAX).
• As for the adjustable output voltage type (RP510L001J/1N/4J/4N) , the output voltage ( VOUT) is adjustable by changing the resistance values of R1 and R2. VSET(1)= VFB × (R1 + R2) / R2, (0.8 V ≤ VSET ≤ 3.3 V) If R2 are too large, the impedance of VFB also become large, as a result, the device could be easily affected by noise. For this reason, R2 should be 30kΩ or less. If the operation becomes unstable dues to the high impedances, the impedances should be decreased. C1 can be calculated by the following equation. Please use the value close to the calculation result. The recommended component values for R1, R2, and C1 are as follows. Set Output Voltage (VSET) vs. Resistor (R1, R2), Capacitor (C1) Set Output Voltage VSET [V] Resistor [kΩ] Capacitor [pF] R1 R2 C1 0.8 10 30 16 1.2 20 20 25 1.8 40 20 25 2.5 95 30 16 3.3 90 20 25 (1) VSET: set output voltage

No. EA-366-190515 Calculation Conditions of LX Pin Maximum Output Current (ILXMAX) The following equations explain the relationship to determine I LXMAX at the ideal operation of the device in continuous mode. IRP：Ripple Current P-P value RONP / RONN：ON resistance of Pch. / Nch. transistor RL：DC resistance of the inductor First, when the Pch. transistor is “ON”, Equation 1 is satisfied. Second, when the Pch. transistor is "OFF" (the Nch. transistor is "ON"), Equation 2 is satisfied. Put Equation 2 into Equation 1 to solve ON duty of the Pch. transistor (DON = tON / (tOFF + tON)): Ripple Current is described as follows: I Peak current that flows through L, and Pch.and Nch. transistors is described as follows: I

No. EA -366-190515 Example applications: Control sequencer Sequencer control can establishes by using the soft-start time adjustment and the power good functions of the RP510L. The following figure indicates an application circuit example with using two RP510L (DCDC1 and DCDC2). DCDC1 starts up prior to DCDC2. After DCDC1 reaches the output voltage of typ.1.44 V (VSET x 0.8), CE pin of DCDC2 receives "High" signal from PG pin of DCDC1, and the DCDC2's soft-start starts. DCDC1 (RP510L001J/1N): VIN = 5.0 V, VOUT = 1.8 V, tSTART = 30 ms, CSS = 0.1 μF DCDC2 (RP510L001J/1N): VIN = 5.0 V, VOUT = 1.2 V, tSTART = 30 ms, CSS = 0.1 μF 25pF PVIN PG LX LX AGND PGND VIN=5.0V COUT11 22µF VOUT1 1.8V 1µH RP510L001J/N CE VFB TSS CIN1 22µF PVIN AVIN PGND 40kΩ 20kΩ PVIN PG LX LX AGND PGND COUT21 22µF VOUT2 1.2V 1µH RP510L001J/N CE VFB TSS CIN2 22µF PVIN AVIN PGND DCDC1 DCDC2 CSS1 0.1µF 20kΩ 20kΩ 25pF CSS2 0.1µF RPG1 100kΩ COUT22 22µF COUT12 22µF RAVIN1 CAVIN1 0.01µF RAVIN2 CAVIN2 0.01µF Sequence Control Application Circuit Example

No. EA-366-190515 TECHNICAL NOTES The performance of a power source circuit using this device is highly dependent on a peripheral circuit. A peripheral component or the device mounted on PCB should not exceed a rated voltage, a rated current or a rated power. When designing a peripheral circuit, please be fully aware of the following points.  AGND and PGND must be wired to the GND plane when mounting on boards.  AVIN must be connected to between an input capacitor (CIN) and PVIN via a low-pass filter (Recommended LPF: 1 Ω, 10 nF). Place a capacitor between AVIN and AGND as close as possible to the IC.  Set the external components as close as possible to the IC and minimize the wiring between the components and the IC. Especially, place CIN as close as possible to PVIN pin and PGND.  Use the VIN and the GND lines as wide and short as possible to make low impedance, since noise pickup or unstable operation occurs when their impedance are too high.  The VIN line, the GND line, the VOUT line, an inductor, and LX should make special considerations for the large switching current flows.  For the feedback of output voltage, the wiring to the VOUT pin (RP510Lxx1G/1H/4G/4H) or to a resistor for setting output voltage (R1) (RP510L001J/1N/4J/4N) must be taken from the connection with the output capacitor, and also the wiring should be separated from the wiring between the output capacitor and Load.  Overcurrent protection circuit and latch / foldback type protection circuit may be affected by self-heating or power dissipation environment.  When not using the soft-start time adjustment, always make TSS pin open.  When not using the power good function, PG pin should be Open or connected to GND.

No. EA -366-190515 PCB Layout Example RP510L001J/1N/4J/4N (Adjustable Output Voltage Type) Layer 1 (Top) Layer 2 Layer 3 Layer 4 (Bottom) ∗ The LPF between PVIN and AVIN is recommended to place to the layer 1 (Top) is recommended. ∗∗ R11 and R12 are arranged as a substitute for R1 so that two resistors can be connected in series.

No. EA-366-190515 RP510Lxx1G/1H/4G/4H (Fixed Output Voltage Type) Layer 1 (Top) Layer 2 Layer 3 Layer 4 (Bottom) ∗ LPF between PVIN and AVIN is recommended to place to Layer 1 (Top) is recommended.

No. EA -366-190515 TYPICAL CHARACTERISTICS Typical Characteristics are intended to be used as reference data, they are not guaranteed. 1) Output Voltage vs. Output Current VOUT = 0.8 V VOUT = 1.2 V 2) Output Voltage vs. Input Voltage VOUT = 3.3 V VOUT = 1.2 V 3) Feedback Voltage vs. Temperature 4) Output Voltage vs. Temperature RP510L001J/1N/4J/4N/ RP510Lxx1G/1H/4G/4H VOUT = 1.2 V

No. EA-366-190515 5) Efficiency vs. Output Current VOUT = 0.8 V VOUT = 1.2 V 6) Current Consumption vs. Temperature VOUT = 3.3 V VIN = 5.5 V 7) Current Consumption vs. Input Voltage

No. EA -366-190515 8) Output Voltage Waveform VOUT = 1.2 V, IOUT = 0mA VOUT = 1.2 V, IOUT = 4000mA 9) Oscillation Frequency vs. Temperature 10) Oscillation Frequency vs. Input Voltage 11) Soft-start time vs. Temperature CSS = open CSS = 0.1µF

No. EA-366-190515 12) UVLO vs. Temperature UVLO detection voltage UVLO release voltage 13) CE Input Voltage vs. Temperature CE "H" input voltage CE "L" input voltage VIN = 5.5 V VIN = 2.5 V 14) LX Limit Current vs. Temperature

No. EA -366-190515 15) PG Detection Voltage vs. Temperature Over Voltage Detection Under Voltage Detection 16) Soft-start Waveform VOUT = 1.2 V, CSS = open VOUT = 1.2 V, CSS = 0.1µF 17) Load Transient Response VIN = 3.3 V, VOUT = 1.2 V VIN = 5.0 V, VOUT = 1.2 V IOUT = 0.5 A ↔ 3.5 A IOUT = 0.5 A ↔ 3.5 A

No. EA-366-190515 18) Output Short-circuit Waveform RP510Lxx1G/1H/1J/1N (Latch Type) RP510Lxx4G/4H/4J/4N (Foldback Type) VIN = 5.0 V, VOUT = 0.8 V VIN = 5.0 V, VOUT = 0.8 V 19) Output Short-circuit Release Waveform RP510Lxx4G/4H/4J/4N (Foldback Type) VIN = 5.0 V, VOUT = 0.8 V

POWER DISSIPATION DFN3030-12 Ver. A i The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following measurement conditions are based on JEDEC STD. 51-7. Measurement Conditions Item Measurement Conditions Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Four-Layer Board) Board Dimensions 76.2 mm × 114.3 mm × 0.8 mm Copper Ratio Outer Layer (First Layer): Less than 95% of 50 mm Square Inner Layers (Second and Third Layers): Approx. 100% of 50 mm Square Outer Layer (Fourth Layer): Approx. 100% of 50 mm Square Through-holes φ 0.3 mm × 32 pcs Measurement Result (Ta = 25°C, Tjmax = 125°C) Item Measurement Result Power Dissipation 3400 mW Thermal Resistance (θja) θja = 29°C/W Thermal Characterization Parameter (ψjt) ψjt = 3.1°C/W θja: Junction-to-Ambient Thermal Resistance ψjt: Junction-to-Top Thermal Characterization Parameter Power Dissipation vs. Ambient Temperature Measurement Board Pattern 500 1000 1500 2000 2500 3000 3500 4000 0 25 50 75 100 125 Power Dissipation (mW) Ambient Temperature (°C) 3400

PACKAGE DIMENSIONS DFN3030-12 Ver. A i 3.0 3.0 A B 0.1 INDEX 0.203 typ S 0.8 max. 0.25±0.05 0.5

0.05 M AB

1.7±0.1 6 1 C 0.35 2.5±0.1 Bottom View 0.05 S 0.40±0.05

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