RMS132AF-10E

RMS132AW EMLSI | Alldatasheet

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-25°C to 85°C Temperature WaferLVCMOS 3.0V/3.0V or 3.3V/3.3V

133 MHzRMS132AW-75E

PackageInterfaceVDD/VDDQClock Freq.Part No. Emerging Memory & Logic Solutions Inc. 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717 Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Figure1: Bond Pad Layout (TOP View)

• Deep Trench Process
• 3 Metal Layers including Local Inter-connection
• T o p M e t a l : A l - C u
• Typical Pad Size : 70um X 70um
• Wafer Diameter : 8 inch (0,0) X Y Pad Pad 103.5um 70um 70um 75um 217um (2332.4, 5826.8)

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Table3: Pin Descriptions No connection.No ConnectionNC Power supply for output buffers.Data Output Power/GroundVDDQ/VSSQ Power supply for internal circuits and input buffers.Power Supply/GroundVDD/VSS Multiplexed data input/output pin.Data Input/OutputDQ0~DQ31 Controls output buffers in read mode and masks input data in write mode.Data Input/Output MaskDQM0~DQM3 RAS, CAS and WE define the operation. Refer function truth table for details. Row Address Strobe, Column Address Strobe, Write Enable /RAS, /CAS, /WE Row Address : RA0~RA10 Column Address : CA0~CA7 Auto Precharge : A10 AddressA0~A10 Selects bank to be activated during RAS activity. Selects bank to be read/written during CAS activity.Bank AddressBA Enable or disable all inputs except CLK, CKE and DQM.Chip Select/CS Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. Clock EnableCKE The system clock input. All other inputs are registered to the SDRAM on the rising edge CLK.System ClockCLK DescriptionsPin NamePin

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW TCSR PASR Figure2: Functional Block Diagram CONTROL LOGIC COMMAND DECODER COLUMN ADDRESS BUFFER & BURST COUNTER CLOCK GENERATOR CLK CKE ROW ADDRESS BUFFER & REFRESH COUNTER /CS /RAS /CAS /WE MODE REGISTER BANK B ROW DECODER BANK A ROW DECODER SENSE AMPLIFIER COLUMN DECODER & LATCH CIRCUIT DQ DQM ADDRESS DATA CONTROL CIRCUIT LATCH CIRCUIT INPUT & OUTPUT BUFFER EXTENDED MODE REGISTER

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW CKE ↓ CKE IDLE ROW ACTIVE SELF REFRESH CBR REFRESH POWER DOWN ACTIVE POWER DOWN READWRITE READ AWRITE A PRE- CHARGE READ SUSPEND READ A SUSPEND WRITE SUSPEND WRITE A SUSPEND POWER ON MODE REGISTER SET PRECHARGE CKE ↓ CKE CKE ↓ CKE CKE ↓ CKE READWRITE CKE ↓ CKE READ WRITE AUTO PRECHARGE WRI TE WITH AUTO PRECHARGE WRITE WITH PRE BST BST ACT CKE ↓ CKE REF SELF SELF EXIT MRS PR E(Pr echarge termination)PRE(Precharge termination) Automatic Sequence Manual Input Figure3: Simplified State Diagram EXTENDED MODE REGISTER SET EMRS DEEP POWER DOWN DPD EXIT DPD

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW WB Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type a nd is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 4. Table 4: Burst Definition Burst Read and Single Write1 Burst Read and Burst Write0 Write Burst ModeM9 Interleave1 Sequential0 Burst TypeM3 Reserved001 Reserved101 2010 -100 3110 Reserved011 Reserved111 Reserved000 CAS LatencyM4M5M6 Full Page Reserved Reserved Reserved M3 = 0 Burst Length Reserved001 Reserved101 4010 2100 8110 Reserved011 Reserved111 1000 M3 = 1 M0M1M2 A0A1A2 1-0-3-21-2-3-0 2-3-0-12-3-0-1 3-2-1-03-0-1-2 0-1-2-30-1-2-3 0-10-1 1-01-0 Not Supported Cn, Cn+1. Cn+2, Cn+3, Cn+4… …C n-1, Cn... n=A0-7 (Location 0-256) Full Page InterleavedSequential Order of Access Within a BurstStarting Column AddressBurst Length Note : 1. For full-page accesses: y = 256 2. For a burst length of two, A1-A7 select the block- of-two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A7 select the block- of-four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A7 select the block-of-eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A7 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A7 select the unique column to be accessed, and mode register bit M3 is ignored.

0 CAS Latency BT Burst Length

Mode Register (Mx) 000 Figure4: Mode Register Definition Note: M11(BA) must be set to “0” to select Mode Register (vs. the Extended Mode Register)

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW

1 PASR

Figure5: Extended Mode Register Address Bus Extended Mode Register (Ex) 01234561 0 98711 A0A1A2A3A4A5A6A7A8A9A10BA Reserved001 Half of One Bank (BA=0, Row Address MSB=0)101 Reserved110 Quarter of One Bank (BA=0, Row Address 2 MSB=0)011 One Bank (BA=0)100 Reserved010 Reserved111 All Banks000 Self Refresh CoverageE0E1E2 Note: E11(BA) must be set to “1” to select Extend Mode Register (vs. the base Mode Register) 1/2 Strength 10 1/4 Strength 01 Reserved11 Full Strength 00 Driver StrengthE5E6 0 000 D S TCSR 70°10 45°01 Auto11 85°00 Maximum Case Temp.E3E4

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW In general, this 32Mb SDRAM (512K x 32Bits x 2banks) is a dual-bank DRAM that operates at 3.0V/3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CL K). Each of the 16,777,216-bit banks is organ ized as 2,048 rows by 256 columns by 32-bits Read and write accesses to the SDRAM are burst oriented; accesse s start at a selected location and continue for a programmed number of locations in a programmed sequence . Accesses begin with the regi stration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincide nt with the ACTIVE command are used to select the bank and row to be accessed (BA select the bank, A0-A 10 select the row). The address bits (BA select the bank, A0-A7 select the column) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. Power up and Initialization SDRAMs must be powered up and initialized in a predefined manne r. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ(simultaneously) and th e clock is stable(stable clock is defined as a signal cycling within timing constraints specified for the cloc k pin), the SDRAM requires a 100µs delay prior to issuing any com mand other than a COMMAND INHIBIT or NOP. CKE must be held high during the entire initialization period until the RECHARGE command has been issued. Starting at some point du ring this 100µs period and continuing at le ast through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP co mmand having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unkno wn state, it should be loaded prior to applying any operational command. And a exte nded mode register set command will be i ssued to program specific mode of self refresh operation(PASR). The following these cycles, the Low Power SDRAM is ready for normal operation. Register Definition Mode Register The mode register is used to define the specific mode of operat ion of the SDRAM. This definition includes the selection of a bu rst length, a burst type, a CAS latency, an op erating mode and a write burst mode. The mo de register is programmed via the LOAD MODE REGISTER command and will retain the stored informatio n until it is programmed again or the device loses power. Mode register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify th e CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 should be set to zero. M11 should be set to zero to prevent extended mode register. The mode register must be loaded when al l banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Functional Description Extended Mode Register The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are special features of the BATRAM device. They include Temperature Compensated Self Refresh (TCSR) Control, and Partial Array Self Refresh (PASR) and Driver Strength (DS). The Extended Mode Register is programmed via the Mode Register Set command (BA=1) and retains the stored information until it i s programmed again or the device loses power. The Extended Mode Register must be programmed with M7 through M 10 set to “0”. The Extended Mode Register must be loaded when all banks are idle and no bursts are in pr ogress, and the controller must wait the specified time before initiating any subseque nt operation. Violating either of these requirements results in unspecified operation.

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Burst Length Read and write accesses to the SDRAM are burst oriented, with th e burst length being programmable, as shown in Figure 1. The bu rst length determines the maximum number of column locations th at can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are ava ilable for both the sequential and the inte rleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or inco mpatibility with future versions may result. When a READ or WRI TE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two; by A2-A7 when the burst length is set to four; and by A3-A7 when the burst length is set to eig ht. The remaining (least significant) address bit(s) is (are) used to select the starting loca tion within the block. Full-page bursts w rap within the page if the boundary is reached. Bank(Row) Active The Bank Active command is used to activate a row in a specifie d bank of the device. This command is initiated by activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA selects the bank, and the value on the A0-A10 selects the row. This row remains active for column access until a precharge comman d is issued to that bank. Read and write operations can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command. Read The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS at the positive edge of the clock. BA input select the bank, A0-A7 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. The length of burst and t he CAS latency will be determined by the values programmed during the MRS command. Write The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserti ng RAS at the positive edge of the clock. BA input select the bank, A0-A7 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses.

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW CAS Latency The CAS latency is the delay, in clock cycl es, between the registration of a READ command and the availability of the first pie ce of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is progra mmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. CLK COMMAND DQ NOP NOP Dout T0 T1 T2 tLZ tOH tAC CAS Latency=2 READ CLK COMMAND DQ NOP NOP Dout T0 T1 T2 tLZ tOH tAC CAS Latency=3 NOP READ DON’T CARE UNDEFINED Figure6: CAS Latency

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Table5: Command Truth Table X X X X X X X X X X X X L/H L/H L/H L/H X X X X X DQM L XHHHLXHNo Operation (NOP) XXXXHXHCommand Inhinit (NOP) VVVL HHHL HHHL HHHL XXHLDeep Power Down Exit 6XHHLLHDeep Power Down Entry XXHLClock Suspend Exit X XXXH LHClock Suspend Entry X XXXH HLPrecharge Down Exit X XXXH LHPrecharge Power Down Entry XXXH HLSelf Refresh Exit 3XHLLLLHSelf Refresh Entry 3XHLLLHHAuto Refresh XLHHLHHBurst Stop LBankLHLLXHPrecharge Selected Bank HXLHLLXHPrecharge All Banks 5HBank/ColLLHLXHWrite with Autoprecharge 5LBank/ColLLHLXHWrite 5HBank/ColHLHLXHRead with Autoprecharge 5LBank/ColHLHLXHRead Bank/RowHHLLXHActive (select bank and activate row) 4OP CODELLLLXHExtended Mode Register Set 4OP CODELLLLXHMode Register Set NoteA10ADDR/WE/CAS/RAS/CSCKEnCKEn-1Function Note : 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. H: High Level, L: Low Level, X: Don't Care, V: Valid 2. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high and will put the device in the all banks idle state once tXSR is met. Command Inhibit or NOP commands should be issued on any clock edges occuring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 3. During refresh operation, internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 4. A0-A10 define OP CODE written to the mode register, and BA must be issued 0 in the mode register set, and 1 in the extended mode register set. 5. DQM “L” means the data Write/Ouput Enable and “H” means the Write inhibit/Output High-Z. Write DQM Latency is 0 CLK and Read DQM Latency is 2 CLK. 6. Standard SDRAM parts assign this command sequence as Burs t Terminate. For Bat Ram parts, the Burst Terminate command is assigned to the Deep Power Down function.

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Table6: Function Truth Table Continue the BurstDevice DeselectXXXXXH X Col Add./A10 Col Add./A10 X X BA BA BA H H L L 8Terimination Burst : Start Read(AP)Read/Read APLHL 8,9Termination Burst : Start Write(AP)Write/WriteAPLHL Continue the Burst ILLEGAL Termination Burst : Start the Precharge ILLEGAL ILLEGAL No Operation No Operation Start Read : Optional AP(A10=H) Start Write : Optional AP(A10=H) ILLEGAL ILLEGAL Activate the Specified Bank and Row No Operation Start Auto or Self Refresh Set the Mode Register DescriptionA0-A10BA/WE/CAS/RAS/CS No OperationHHL 4Bank ActivateRow Add.BAHHLL PrechargeHLL 13Auto or Self RefreshXXHLLL 13,14Mode Register SetOP CODELLLL Read Device DeselectXXXXXH No OperationXXHHHL 6Read/Read APCol Add./A10BAHLHL 6Write/Write APCol Add./A10BALLHL 4Bank ActivateRow Add.BAHHLL 7PrechargePrechargeXBALHLL 13ILLEGALAuto or Self RefreshXXHLLL 13,14ILLEGALMode Register SetOP CODELLLL Row Active 3No Operation or Power DownDevice DeselectXXXXXH 3No OperationNo OperationXXHHHL 4ILLEGALRead/ReadAPCol Add./ A10BAHLHL 4Write/WriteAPCol Add./ A10BALLHL Bank ActivateRow Add.BAHHLL PrechargeXBALHLL 5Auto or Self RefreshXXHLLL 14Mode Register SetOP CODELLLL Idle NoteAction CommandCurrent State

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Table6: Function Truth Table X X Col Add./A10 Col Add./A10 Row Add. X X 13,14ILLEGALMode Register SetOP CODELLLL Write with Auto Precharge 13ILLEGALAuto or Self RefreshXHLLL 4,12ILLEGALPrechargeBALHLL 4,12ILLEGALBank ActivateBAHHLL 12ILLEGALWrite/WriteAPBALLHL 12ILLEGALRead/ReadAPBAHLHL Continue the BurstNo OperationXHHHL Continue the BurstDevice DeselectXXXXH Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL Termination Burst : Start Write(AP) ILLEGAL Termination Burst : Start the Precharge ILLEGAL ILLEGAL DescriptionA0-A10BA/WE/CAS/RAS/CS Device DeselectXXXXXH No OperationXXHHHL 12Read/ReadAPCol Add./A10BAHLHL 12Write/WriteAPCol Add./A10BALLHL 4,12Bank ActivateRow Add.BAHHLL 4,12ILLEGALPrechargeXBALHLL 13ILLEGALAuto or Self RefreshXXHLLL 13,14ILLEGALMode Register SetOP CODELLLL Read with Auto Precharge Continue the BurstDevice DeselectXXXXXH Continue the BurstNo OperationXXHHHL 8,9Terimination Burst : Start READ(AP)Read/ReadAPCol Add./A10BAHLHL 8Write/WriteAPCol Add./A10BALLHL 4Bank ActivateRow Add.BAHHLL 10PrechargeXBALHLL 13Auto or Self RefreshXXHLLL 13,14Mode Register SetOP CODELLLL Write NoteAction CommandCurrent State

The specifications of this device are subject to change without notice. For latest documentation see http://www.emsli.com. RMS132AW Table6: Function Truth Table No Operation : Row Active after tDPLDevice DeselectXXXXXH X Col Add./A10 Col Add./A10 X X BA BA BA H H L L 9Start Write : Optional AP(A10=H)Read/Read APLHL Start Write : Optional AP(A10=H)Write/WriteAPLHL No Operation : Row Active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation : ROw Active after tRCD No Operation : ROw Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation : Bank(s) Idle after tRP ILLEGAL ILLEGAL DescriptionA0-A10BA/WE/CAS/RAS/CS No OperationHHL 4,12Bank ActivateRow Add.BAHHLL 4,13PrechargeHLL 13Auto or Self RefreshXXHLLL 13,14Mode Register SetOP CODELLLL Write Recovering Device DeselectXXXXXH No OperationXXHHHL 4,12Read/Read APCol Add./A10BAHLHL 4,12Write/Write APCol Add./A10BALLHL 4,11,12Bank ActivateRow Add.BAHHLL 4,12ILLEGALPrechargeXBALHLL 13ILLEGALAuto or Self RefreshXXHLLL 13,14ILLEGALMode Register SetOP CODELLLL Row Activating No Operation : Bank(s) Idle after tRPDevice DeselectXXXXXH No Operation : Bank(s) Idle after tRPNo OperationXXHHHL 4,12ILLEGALRead/ReadAPCol Add./ A10BAHLHL 4,12Write/WriteAPCol Add./ A10BALLHL 4,12Bank ActivateRow Add.BAHHLL PrechargeXBALHLL 13Auto or Self RefreshXXHLLL 13,14Mode Register SetOP CODELLLL Precharging NoteAction CommandCurrent State

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Table6: Function Truth Table No Operation : Idle after 2 Clock CycleDevice DeselectXXXXXH X Col Add./A10 Col Add./A10 X X BA BA BA H H L L 13ILLEGALRead/Read APLHL 13ILLEGALWrite/WriteAPLHL No Operation : Idle after 2 Clock Cycle ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation : Idle after tRC No Operation : Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL DescriptionA0-A10BA/WE/CAS/RAS/CS No OperationHHL 13Bank ActivateRow Add.BAHHLL 13PrechargeHLL 13Auto or Self RefreshXXHLLL 13,14Mode Register SetOP CODELLLL Mode Register Accessing Device DeselectXXXXXH No OperationXXHHHL 13Read/Read APCol Add./A10BAHLHL 13Write/Write APCol Add./A10BALLHL 13Bank ActivateRow Add.BAHHLL 13ILLEGALPrechargeXBALHLL 13ILLEGALAuto or Self RefreshXXHLLL 13,14ILLEGALMode Register SetOP CODELLLL Refreshing No Operation : Precharge after tDPLDevice DeselectXXXXXH No Operation : Precharge after tDPLNo OperationXXHHHL 4,9,12ILLEGALRead/ReadAPCol Add./ A10BAHLHL 4,12Write/WriteAPCol Add./ A10BALLHL 4,12Bank ActivateRow Add.BAHHLL 4,13PrechargeXBALHLL 13Auto or Self RefreshXXHLLL 13,14Mode Register SetOP CODELLLL Write Recovering with Auto Precharge NoteAction CommandCurrent State

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Note : 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. 14. Mode Register Set and Extended Mode Register Set is same command truth table except BA.

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Table7: CKE Truth Table 4Refer to the Idle State section of the Current State Truth Table XXXHHH All Banks Idle 4XXHLHH 4XHLLHH Auto RefreshXXHLLLHH 5Mode Register SetOP CODELLLLHH 4Refer to the Idle State section of the Current State Truth Table XXXHLH 4XXHLLH 4XHLLLH 5Entry Self RefreshXXHLLLLH Mode Register SetOP CODELLLLLH 5Power DownXXXXXXXL Refer to Operations of the Current State Truth Table XX XXXXHH Any State other than listed above Begin Clock Suspend next cycle XXXXXXLH Exit Clock Suspend next cycle XXXXXXHL Maintain Clock SuspendXXXXXXLL XXLXX XXXLX XXHHHL Maintain Deep Power Down Mode Deep Power Down Mode Set INVALID ILLEGAL Exit Self Refresh with No Operation Exit Self Refresh with Device Deselect INVALID X X X X X X X X A0-A10BA/WE/CAS/RAS/CSCurrent Cycle Prev Cycle XXXXXLL 6XXXXXHL 2XXXXXXH Deep Power Down Maintain Power Down ModeXXXXXXLL ILLEGALXXXXL LHL Power Down Mode Exit, All Banks Idle XXXXXH HL 2INVALIDXXXXXXXH Power Down Maintain Self RefreshXXXXXXLL 3ILLEGALXXXXLLHL 3ILLEGALXXLHLHL 3XLHHLHL 3XHHHLHL 3XXXXHHL 2XXXXXXH Self Refresh NoteAction CommandCKE Current State

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Note : 1. H: Logic High, L: Logic Low, X: Don't care 2. For the given current state CKE must be low in the previous cycle. 3. When CKE has a low to high transition, the clock and other in puts are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on th e first positive edge of clock after CKE goes high. 4. The address inputs depend on the command that is issued. 5. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 6. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 100usec.

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Table8: Absolute Maximum Rating 0 ~ 70Ambient Temperature (Commercial) -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ 150 -25 ~ 85 Rating WPDPower Dissipation mAIOSShort Circuit Output Current VVDD, VDDQVoltage on VDD relative to VSS VVIN, VOUTVoltage on Any Pin relative to VSS °CTSTGStorage Temperature °CTA Ambient Temperature (Industrial) UnitSymbolParameter Note : Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational s ections of this specification is not implied. Exposure to absolute maximu m rating conditions for extended periods may affect reliability. Table9: Capacitance (TA=25 °C, f=1MHz, VDD=3.0V or 3.3V) DQ0~DQ31 A0~A10, BA, CKE, /CS, /RAS, /CAS, /WE, DQM0~DQM3 CLK Pin Min Max pFCIOData Input/Output Capacitance pFCI2 pFCI1 Input Capacitance UnitSymbolParameter Table10: DC Operating Condition (Voltage referenced to VSS=0V, TA= -25 ~ 85 °C) V3.63.02.7VDD IOL= +0.1mAV0.4--VOLOutput Low Voltage 4uA1--1ILIInput Leakage Current 2VVDDQ+0.3-2.2VIHInput High Voltage 3V0.50-0.3VILInput Low Voltage IOH= -0.1mAV--2.4VOHOutput High Voltage uA V Unit 3.0 Typ -1.5 2.7 Min 1.5 3.6 Max 5ILOOutput Leakage Current 1VDDQ Power Supply Voltage NoteSymbolParameter Note : 1. VDDQ must not exceed the level of VDD 2. VIH(max) = 5.3V AC. The overshoot voltage duration is ≤ 3ns. 3. VIL(min) = -2.0V AC. The overshoot voltage duration is ≤ 3ns. 4. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 5. DOUT is disabled, 0V ≤ VOUT ≤ VDDQ.

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Table11: AC Operating Condition (TA= -25 ~ 85 °C, VDD = 3.0V or 3.3V ± 0.3V, VSS=0V) V0.5 x VDDQVTRIPInput Timing Measurement Reference Level Voltage ns1 / 1tR / tFInput Rise / Fall Time V0.5 x VDDQVOUTREFOutput Timing Measurement Reference Level Voltage pF30CLOutput Load Capacitance for Access Time Measurement V Unit 2.4 / 0.4 Typ VIH / VILAC Input High/Low Level Voltage SymbolParameter Output 870Ω 1200Ω VDDQ 30pF Output 30pF 50Ω VTT=0.5 x VDDQ Z0=50Ω DC Output Load Circuit A C Output Load Circuit

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Table12: DC Characteristic (DC operating conditions unless otherwise noted) -75 0.5 0.5 -10-60 TCSRPASR uACKE ≤ 0.2VICC6 Self Refresh Current 80~10045~85°C

2 Banks

60~80-25~45°C 70~9045~85°C

1 Bank

50~70-25~45°C uA10ICC7Deep Power Down Mode Current 2mA40tRC ≥ tRFC(min), All Banks ActiveICC5Auto Refresh Current (4K Cycle) CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞ Input signals are stable.ICC3NS 1mA80tCK>tCK(min), IOL = 0 mA, Page Burst All Banks Activated, tCCD = 1 clkICC4Burst Mode Operating Current CKE & CLK ≤ VIL(max), tCK = ∞ICC3PS mA CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = 10ns Input signals are changed one time during 2 clks.ICC3N Active Standby Current in Non Power Down Mode mA CKE ≤ VIL(max), tCK = 10nsICC3PActive Standby Current in Power Down Mode uA CKE & CLK ≤ VIL(max), tCK = ∞ICC2PS Speed CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞ Input signals are stable. CKE ≥ VIH(min), /CS ≥ VIH(min), tCK = 10ns Input signals are changed one time during 2 clks. CKE ≤ VIL(max), tCK = 10ns Burst Length=1, One Bank Active, tRC ≥ tRC(min) IOL = 0 mA Test Condition ICC2PPrecharge Standby Current in Power Down Mode mA ICC2N Precharge Standby Current in Non Power Down Mode ICC2NS Note mA Unit ICC1Operating Current SymParameter Note : 1. Measured with outputs open. 2. Refresh period is 64ms.

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Table13: AC Characteristic (AC operation conditions unless otherwise noted) 57067.566tXSRExit SELF REFRESH to ACTIVE command ns 7067.566tRFCAUTO REFRESH period ms646464tREFRefresh period (4,096 rows) 9111tPEDCKE to clock enable or power-down exit setup mode CLK 111tCKEDCKE to clock disable or power-down entry mode 37.5 22.5 67.5 22.5 1.8 2.5 1.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 2.0 2.5 2.5 7.5 Min -75 100K 1000 Max 611tBDLLast data-in to burst STOP command 611tCDLLast data-in to new READ/WRITE command CL = 2 CL = 3 22tROH2 822tMRDLOAD MODE REGISTER command to ACTIVE or REFRESH command 600tDQMDQM to data mask during WRITEs CLK 22tDQZDQM to data high-impedance during READs 7ns2012tDPLData-in to PRECHARGE command 730tDALData-in to ACTIVE command 600tDWDWRITE command to input data delay CLK 11tCCDREAD/WRITE command to READ/WRITE command 2012tRRDACTIVE bank a to ACTIVE bank b command 2418tRPPRECHARGE command period 2.01.5tDSData-In Setup Time 2.01.5tASAddress Setup Time 2.01.5tCMS/CS, /RAS, /CAS, /WE, DQM Setup Time 2.01.5tCKSCKE Setup Time 1.01.0tCMH/CS, /RAS, /CAS, /WE, DQM Hold Time 1.01.0tCKHCKE Hold Time 32.52.5tCHCLK High-Level Width 32.52.5tCLCLK Low-Level Width 1.8 2.5 1.0 1.0 1.0 6.0 Min -60 100K 5.5 5.5 1000 Max MaxMin ns 100010tCK3CL = 3CLK Cycle Time 10tCK2CL = 2 20tRCDACTIVE to READ or WRITE delay 63tROH3Data-out to high-impedance from PRECHARGE command 564tRCACTIVE bank a to ACTIVE bank a command 8CL = 2 CL = 3 8tHZ3Data-Out High-Impedance Time from CLK (pos.edge) tHZ2 1.0tLZData-Out Low-Impedance Time 2.5tOHData-Out Hold Time (load) 1.8tOHNData-Out Hold Time (no load) 1.0tDHData-In Hold Time 100K40tRASACTIVE to PRECHARGE command 1.0tAHAddress Hold Time 8tAC2CL = 2 CL = 3 28tAC3Access time from CLK (pos. edge) -10 NoteUnitSymParameter

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Note : 1. The clock frequency must remain constant (stable clock is de fined as a signal cycling within timing constraints specified fo rt h e clock pin) during access or precharge states (READ, WRITE, including tDPL, and PRECHARGE commands). CKE may be used to reduce the data rate. 2. tAC at CL = 3 with no load is 5.5ns and is guaranteed by design. Access time to be measured with input signals of 1V/ns edge 3. AC characteristics assume tT = 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 4. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 5. Parameter guaranteed by design. A. Target values listed with alternative values in parentheses. B. tRFC must be less than or equal to tRC+1CLK tXSR must be less than or equal to tRC+1CLK 6. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 7. Timing actually specified by tDPL plus tRP; clock(s) specified as a reference only at minimum cycle rate 8. JEDEC and PC100 specify three clocks. 9. Timing actually specified by tCKs; clock(s) specified as a reference only at minimum cycle rate. 10. A new command can be given tRC after self refresh exit.

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Temperature Compensated Self Refresh Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to the case temperature of the Low Power SDRAM device. This allows great power savings during SELF REFRESH during most operating temperature ranges. Only during extreme temperatures would the co ntroller have to select a TCSR level that will guarantee data during SELF REFRESH. Every cell in the DRAM requires refreshing due to the capacitor l osing its charge over time. The refresh rate is dependent on temperature. At higher temperat ures a capacitor loses charge quicker than at lo wer temperatures, requiring the cells to be refr eshed more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperat ure range expected. Thus, during ambient temperatures, the power consumed during re fresh was unnecessarily high, beca use the refresh rate was set t o accommodate the higher temperatures. Setting M4 and M3, allow the DRAM to accommodate more specific temperature regions during SELF REFRESH. There are four temperature settings, which will vary the SELF REFRESH current according to the selected temperatu re. This selectable refresh rate will save power when the DRAM is operating at normal temperatures. Partial Array Self Refresh For further power savings during SELF REFRESH, the PASR feature allo ws the controller to select the amount of memory that will b e refreshed during SELF REFRESH. The refresh options are Two Bank ;all two banks, One Bank;bank 0. WRITE and READ commands can still occur during standard operation, but only the selected banks will be refreshed during SELF REFRESH. Data in banks that ar e disabled will be lost. Deep Power Down Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock, while CKE is low. This mode is exited by asserting CKE high. Special Operation for Low Power Consumption

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW Figure7: Deep Power Down Mode Entry Figure8: Deep Power Down Mode Exit CLK CKE /CS /RAS /CAS /WE 100 µ s tRP tRFC Deep Power Down Exit All Banks Precharge Auto Refresh Mode Register Set Extended Mode Register Set New Command Auto Refresh CLK CKE /CS /RAS Precharge if needed Deep Power Down Entry tRP

The specifications of this device are subject to change without notice. For latest documentation see http://www.emlsi.com. RMS132AW

Ordering Information

Revision History

Initial ADVANCE ReleaseJanuary 12th, 2006A Change DescriptionDateRevision R M XX XXXX X X X X XX–X X X MEMORY PRODUCT FAMILY S: S D R A M CONFIGURATION / DENSITY 132 : 1Mx32, 32M bits F: F B G A W : Wafer PACKAGE TYPE SPEED 6: 6 n s 75 : 7.5ns 10 : 10ns VERSION A : 1st Ver. MODE BLANK : DRAM EMLSI BLANK : VDD=3.3V & VDDQ=3.3V POWER SUPPLY TEMP E : Extended (-25’C ~ +85’C) Blank : Normal PACKAGE MATERIAL © 2004 EMLSI All rights reserved. EMLSI reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. EMLSI does not convey any license under its patent rights nor the rights of others. C harts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon spe cific applications. EMLSI makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does EMLSI assume any liability arising out of the application or use of any product or circuit described herein. EMLSI does not authorize use of its products as critical components in any application in which the failure of the EMLSI product may be expected to result in significant injury or death, including life support systems and critical medical instrument.