RMLD232UAW

RMLD232UAW EMLSI | Alldatasheet

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1 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Document Title 2M x 32 bit Low Power DDR SDRAM ( RMLD232UAW-7E ) Specification

Revision History

Revision No. History Draft Date Remark 0.0 Initial Draft Apr. 12 , 2006 Draft 0.1 Advanced spec. release Jul. 21 , 2006 Advanced 0.2 AC/DC Values are modified. Wafer spec & PAD allocations are atteahed. PAD coordinates are not fixed (TBD). Sep. 2 , 2006 Advanced 0.3 Pad allocation changed (NC Pad added to right bottom) Sep. 21 , 2006 Advanced 0.4 AC (tDSS,tDSH) spec items are added. DC(Icc0,Icc2NS,Icc4R,Icc4W) spec value changed. Nov. 14 , 2006 Advanced 0.5 PAD coordinates updated. Dec. 6 , 2006 Advanced 0.6 PAD allocation changed. (BA0,BA1) Dec. 19 , 2006 Advanced 0.7 tDS & tDH value changed. (@DDR266 : 0.8n -> 0.9n) tAC(CL=3), tDQSCK, tHZ value changed. (6.0n -> 7.0n) TCSR ICC6 Values updated. Nov. 27 , 2007 Preliminary Emerging Memory & Logic Solutions Inc. 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-717 Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office.

2 Rev 0.7 64Mb Low Power DDR SDRAM Advanced 2M x 32 Low Power DDR SDRAM

Features

1.8V power supply, 1.8V I/O power Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe(DQS) Four banks operation Differential clock inputs(CK and CK) MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) - Partial Self Refresh Type ( Full, 1/2, 1/4 array ) - Internal Temperature Compensated Self Refresh - Driver strength ( 1, 1/2, 1/4, 1/8 ) Deep Power Down Mode All inputs except data & DM are sampled at the positive going edge of the system clock(CK). Data I/O transactions on both edges of data strobe, DM for masking. Edge aligned data output, center aligned data input. No DLL; CK to DQS is not synchronized. DM0 - DM3 for write masking only. 15.6 auto refresh duty cycle. Opreating Frequency *CL : CAS Latency Column Address Configuration DM is internally loaded to match DQ and DQS identically. DDR266 DDR222 Speed @CL2 83 66 Speed @CL3 133 111 Organization Row Address Column Address 2M 32 A0 ~ A10 A0-A7 General Wafer Specifications Process Technology : 0.125um Trench DRAM Process Wafer thickness : 725 +/- 25um Wafer Diameter : 8-inch

3 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Input/Output Function Description SYMBOL TYPE DESCRIPTION CK, CK Input Clock : CK and CK are differential clock inputs. All address and control input signals are sam- pled on the crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK. CKE Input Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER- DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all funtions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE , are disabled during power-down and self refresh mode which are contrived for low standby power consumption. CS Input Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. *1DM0, DM1 DM2, DM3 Input Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load- ing. For the x32, DM0 corresponds to the data on DQ0-DQ7 ; DM1 corresponds to the data on DQ8-DQ15 ;DM2 corresponds to the data on DQ16-DQ23 ; DM3 corresponds to the data on DQ24-DQ31 . BA0,BA1 Input Bank Address Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE- CHARGE command is being applied. A [n : 0] Input Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command deter- mines wherther the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0,BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 determines which mode register( mode register or extended mode register ) is loaded during the MODE REGISTER SET command. *1DQ I/O Data Input/Output : Data bus *1DQS0, DQS1 DQS2, DQS3 I/O Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen- tered in write data. It is used to fetch write data. For the x32, DQS0 corresponds to the data on DQ0-DQ7 ; DQS1 corresponds to the data on DQ8-DQ15 ;DQS2 corresponds to the data on DQ16-DQ23 ; DQS3 corresponds to the data on DQ24-DQ31. NC - No Connect : No internal electrical connection is present. VDDQ Supply DQ Power Supply : 1.7V to 1.95V. VSSQ Supply DQ Ground. VDD Supply Power Supply : 1.7V to 1.95V. VSS Supply Ground.

4 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Functional Description DEEP IDLE PRECHARGE POWER ON PRECHARGE MRS AUTO PARTIAL SELF REFRESH REFRESH SELF POWER ROW ACTIVE READ READA WRITE WRITEA WRITEA READA READA WRITEA READA READWRITE PRE PRE PRE READ BURST STOP ALL BANKS PRECHARGED ACT DOWN CKEL CKEH REFRESH REFA REFS REFSX POWER DOWN DEEP POWER DOWN EMRS MRS CKEH ALL BANKS POWER APPLIED POWER DOWN CKEL CKEH PREALL PRE Automatic Sequence Command Sequence Figure.1 State diagram

5 Rev 0.7 64Mb Low Power DDR SDRAM Advanced NOTE : 1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. -Apply VDD before or at the same time as VDDQ. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 . 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. 6. Issue a extended mode register set command to define PASR or DS operating type of the device after normal MRS. EMRS cycle is not mandatory and the EMRS command needs to be issued only when either PASR or DS is used. The default state without EMRS command issued is half driver strength, and Full array refreshed. The device is now ready for the operation selected by EMRS. For operating with PASR or DS, set PASR of DS mode in EMRS setting stage. In order to adjust another mode in the state of PASR or DS mode, additional EMRS set is required but power up sequence is not needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 5 16 17 18 19 20 Hi-Z Hi-Z High CK CK CKE CS RAS CAS ADDR BA0 BA1 A10/AP DQ WE DQS tRP tARFC Precharge tARFC (All Bank) Auto Normal MRSRefresh Auto Refresh Extended Row Active (A-Bank) MRS Key Key RAa RAa Hi-Z Hi-Z Power Up Sequence for Low Power DDR SDRAM : Don’t Care

6 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Mode Register Definition Mode Register Set (MRS) The mode register is designed to support the various operating modes of DDR SDRAM. It includes CAS latency, addressing mode, burst length, test mode and vendor specific options to make DDR SDRAM useful for variety of applications. The default value of the mode register is not defined, therefore the mode register must be written in the power up sequence of DDR SDRAM. The mode reg- ister is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0~A10 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Two clock cycles are required to complete the write operation in the mode register. Even if the power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed with the same command and four clock cycles. This command must be issued only when all banks are in the idle state. If mode reg- ister is changed, extended mode register automatically is reset and come into default state. So extended mode register must be set again. The mode register is divided into various fields depending on funtionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 ~ A10 are used for test mode. BA0 and BA1 must be set to low for normal DDR SDRAM operation. BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 CAS Latency BT Burst Length A6 A5 A4 CAS Latency 0 0 0 Reserve 0 0 1 Reserve 0 1 0 2 0 1 1 3 1 0 0 Reserve 1 0 1 Reserve 1 1 0 Reserve 1 1 1 Reserve A3 Burst Type

0 Sequential

1 Interleave

Figure.2 Mode Register Set Address Bus Mode Register

7 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Burst address ordering for burst length Burst Length Starting Address (A3, A2, A1, A0) Sequential Mode Interleave Mode xxx0 0, 1 0, 1 xxx1 1, 0 1, 0 xx00 0, 1, 2, 3 0, 1, 2, 3 xx01 1, 2, 3, 0 1, 0, 3, 2 xx10 2, 3, 0, 1 2, 3, 0, 1 xx11 3, 0, 1, 2 3, 2, 1, 0

8 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Extended Mode Register Set (EMRS) The extended mode register is designed to support partial array self refresh or driver strength. EMRS cycle is not mandatory and the EMRS command needs to be issued only when either PASR or DS is used. The defalt state without EMRS command issued is +85 , all 4 banks refreshed and the half size of driver strength. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA1, low on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A10 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed with the same command and four clock cycles. But this command must be issued only when all banks are in the idle state. A0 ~ A2 are used for partial array self refresh and A5 ~ A6 are used for driver strength. “High” on BA1 and “Low” on BA0 are used for EMRS. All the other address pins except A0, A1, A2, A5, A6, BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. Extended MRS for PASR(Partial Array Self Refresh) & DS & TCSR(Internal Temperature Compensated Self Refresh) BA1 BA0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 0 0 0 DS 0 0 PASR Driver Strength A6 A5 Driver Strength 0 0 Full 0 1 1/2 (default) 1 0 1/4 1 1 1/8 Address Bus Mode Register Inernal TCSR Self refresh cycle is controlled automatically by internal tem- perature sensor and control cir- cuit according to the four temperature ; Max 15 , Max , Max 70 , Max 85 PASR A2 A1 A0 Size of Refreshed Array 0 0 0 Four Banks (default) 0 0 1 Two Banks (Bank 0,1) 0 1 0 One Bank (Bank 0) 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved

9 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Internal Temperature Compensated Self Refresh (TCSR) Note : 1. In order to save power consumption, Low Power DDR SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the four temperature range ; Max. 15 , Max. 45 , Max. 70 , Max. 85 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. Partial Array Self Refresh (PASR) Note : 1. In order to save power consumption, Mobile DDR SDRAM includes PASR option. 2. Low Power DDR SDRAM supports three kinds of PASR in self refresh mode; Four banks, Two banks, One bank. Temperature Range Self Refresh Current (Icc6) Unit Full Array 1/2 Array 1/4 Array Max. 15 210 160 130 Max. 45 220 170 135 Max. 70 230 180 140 Max. 85 250 190 150 BA1=0 BA0=0 BA0=1 BA1=0BA1=0 BA1=0 BA0=0 BA1=1 BA1=1 BA0=0 BA0=1 - Four Bank - Two Bank (Bank0,1) - One Bank (Bank0) Partial Self Refresh Area BA1=1BA1=1 BA1=0 BA1=0 BA0=0 BA0=1 BA1=1 BA0=1BA0=0BA0=0 BA0=1 BA1=1 BA0=1 Figure.3 EMRS code and TCSR, PASR

10 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Precharge The precharge command is used to precharge or close a bank that has been activated. The precharge command is issued when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank respectively or all banks simultaneously. The bank select addresses(BA0, BA1) are used to define which bank is precharged when the command is initiated. For write cycle, tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the precharge, an active command to the same bank can be initiated. Bank selection for precharge by Bank Address bits No Operation(NOP) & Device Deselect The device should be deselected by deactivating the CS signal. In this mode DDR SDRAM should ignore all the control inputs. The DDR SDRAMs are put in NOP mode when CS is active and by deactivating RAS, CAS and WE. Both Device Deselect and NOP com- mand can not affect operation already in progress. So even if the device is deselected or NOP command is issued under operation, operation will be complete. A10/AP BA1 BA0 Precharge 0 0 0 Bank A Only 0 0 1 Bank B Only 0 1 0 Bank C Only 0 1 1 Bank D Only

1 X X All Banks

11 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Row Active The Bank Activation cimmand is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock(CK). The DDR SDRAM has four independent banks, so two Bank Select addresses(BA0, BA1) are required. The Bank Activation command must be applied before any Read or Write operation is executed. The delay from the Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time(tRCD min). Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank. The minimum time interval between inter- leaved Bank Activation comands(Bank A to Bank B and vice versa) is the Bank to Bank delay time(tRRD min). Read Bank This command is used after the row activate command to initiate the burst read of data. The read command is initiated by activating CS, CAS, and deassertig WE, RAS at the same clock sampling(rising) edge as described in the command truth table. The length of the burst and the CAS latency time will be determined by the values programmed during the MRS cycle. Write Bank This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating RAS, CS, WE, and deassertig RAS at the same clock sampling(rising) edge as described in the command truth table. The length of the burst will be determined by the values programmed during the MRS cycle. Bank Activation Command Cycle 0 1 2 3 4 5 Tn Tn+1 CK CK Address Command Bank A Row Addr. RAS-CAS delay(tRCD) Bank A Col. Addr. NOP NOP NOPWrite A Bank B Bank A Activate with Auto Bank B Activate Row Addr. Bank A Row Addr. Bank A ActivateNOP ROW Cycle Time(tRC) RAS-RAS delay time(tRRD) : Don’t Care Figure.4 Bank activation command cycle timing Precharge

12 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Essential Functionality for DDR SDRAM The essential functionality that is required for the DDR SDRAM device is described in this chapter Burst Read Operation Burst Read operation in DDR SDRAM is in the same manner as the SDRAM such that the burst read command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock(CK) after tRCD from the bank activation. The address inputs (A0~A9) determine the starting address for the Burst. The Mode Register sets type of burst(Sequential or interleave) and burst length(2, 4, 8, 16). The first output data is available after the CAS Latency from the READ command, and the consecutive data are presented on the falling and rising edge of Data Strobe(DQS) adopted by DDR SDRAM until the burst length is completed. 0 1 2 3 4 5 6 7 8 CK CK Command NOP NOP NOP NOP NOP NOP NOP NOPREAD A tAC tRPRE Preambel Postamble Dout 0 Dout 1 Dout 2 Dout 3 CAS Latency=3 DQS DQs Figure.5 Burst read operation timing < Burst Length=4, CAS Latency=3 > tRPST

13 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Burst Write Operation The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock(CK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst write cycle. The first data of a burst write cycle must be applied on the DQ pins tDS(Data-in setup time) prior to data strobe edge enabled after tDQSS from the rising edge of the clock(CK) that the write command is issued. The remaining data inputs must be supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been finished, any additional data supplied to the DQ pins will be ignored. 1. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 0 1 2 3 4 5 6 7 8 CK CK Command NOP NOP NOP NOP NOP NOP NOP tWPRES*1 tDQSSmax DQS DQs Figure.6 Burst write operation timing < Burst Length=4 > WRITEA WRITEB Din 0 Din 1 Din 2 Din 3 Din 0 Din 2Din 1 Din 3

14 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Read Interrupted by a Read A Burst Read can be interrupted before completion of the burst by new Read command of any bank. When the previous burst is inter- rupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied. At this point the data from the interrupting Read command appears. Read to Read interval is minimum 1 Clock. Read Interrupted by a Write & Burst Stop To interrupt a burst read with a write command, Burst Stop command must be asserted to avoid data contention on the I/O bus by placing the DQs(Output drivers) in a high impedance state. To insure the DQs are tri-stated one cycle before the beginning of the write operation, Burst stop command must be applied at least 2 clock cycles for CL=2 and at least 3 clock cycles for CL=3 before the Write command. The following functionality establishes how a Write command may interrupt a Read burst. 1. For Write commands interrupting a Read burst, a Burst Terminate command is required to stop the read burst and tristate the DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command =RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer]. 2. It is illegal for a Write command to interrupt a Read with autoprecharge command. 0 1 2 3 4 5 6 7 8 CK CK Command NOPNOP NOP NOP NOP NOP NOP DQS DQs Figure.7 Read interrupted by a read timing < Burst Length=4, CAS Latency=3 > READ A tAC READ B Dout A0 Dout A1 Dout B0 Dout B1 Dout B2 Dout B3 tRPRE Preamble CAS Latency=3 0 1 2 3 4 5 6 7 8 CK CK Command NOPNOP NOPBurst Stop NOP NOP tDQSS DQS DQs Figure.8 Read interrupted by a Write and burst stop timing < Burst Length=4, CAS Latency=3 > READ tAC WRITE Dout 0 Dout 1 tRPRE Preamble CAS Latency=3 tWPRES tWPREH Din 0 Din 1 Din 2 Din 3

15 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Read Interrupted by a Precharge A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency. when a burst Read command is issued to a DDR SDRAM, a precharge command may be issued to the same bank before the Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and when a new Bank Activate command may be issued to the same bank. 1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank Activate command may be issued to the same bank after tRP (RAS Precharge time). 2. when a Precharge command interrupts a Read burst operation, the precharge command may be given on the rising clock edge which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last data word has been output, the output buffers are tristated, A new Bank Activate command may be issued to the same bank after tRP. 3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after tRP where tRP begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above. 4. For all cases above, tRP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a Precharge command and a new Bank Activate command to the same bank equals tRP/tCK(where tCK is the clock cycle time) with the result rounded up to the nearest integer number of clock cycles. (Note that rounding to x .5 is not possible since the Precharge and Bank Activate commands can only be given on a rising clock edge). In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Read with autoprecharge commands where tRAS(min) must still be satisfied such that a Read with autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst. 0 1 2 3 4 5 6 7 8 CK CK Command NOPNOP NOPPrecharge NOP NOP DQS DQs Figure.9 Read interrupted by a precharge timing < Burst Length=8, CAS Latency=3 > READ tAC Dout 0 Dout 1 tRPRE CAS Latency=3 NOP Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7 Interrupted by precharge 1tCK NOP

16 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Write Interrupted by a Write A Burst Write can be interrupted before completion of the burst by a new Write command, with the only restriction that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are over- ridden by the new address and data will be written into the device until the programmed burst length is satisfied. 0 1 2 3 4 5 6 7 8 CK CK Command NOPNOP NOP NOP NOP DQS DQs Figure.10 Write interrupted by a write timing < Burst Length=4 > WRITE A Din A0 NOPWRITE B Din A1 Din B0 Din B1 Din B2 Din B3 1tCK NOP

17 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Write Interrupted by a Precharge & DM A burst write operation can be interrupted before completion of the burst by a precharge of the same bank. Random column access is allowed. A write recovery time(tWR) is required from the last data to precharge command. When precharge command is asserted, any residual data from the burst write cycle must be masked by DM. Precharge timing for Write operations in DRAMs requries enough time to allow “write recovery “ which is the time required by a DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR SDRAM, a timing parameter, tWR, is used to indicate the required amount of time between the last valid write operation and a Precharge command to the same bank. The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and the address is sampled by the input clock. Inside the SDRAM, the data path is eventually synchronized with the address path by swithing clock domains from the data strobe clock domain to the input clock domain. This makes the definition of when a precharge operation can be initiated after a write very complex since the write recovery parameter must reference only the clock domain that is used to time the internal write operation, i.e., the input clock domain. tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and ends on the rising clok edge that strobes in the prechrge command. 1. For the earilest possible Precharge command following a Write burst without interrupting the burst , the minimum time for write recovery is defined by tWR. 2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask input data during the time between the last valid write data and the rising clock edge on which the Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM. The minimum time for write recovery is defined by tWR. 3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same bank after tWR+tRP where tWR+tRP starts on the falling DQS edge that strobed in the last valid data and ends on the rising clock edge that strobes in the Bank Activate command. During write with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible external Precharge command without interrupting the Write burst as described in 1 above. 4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min) must still be satisfied such that a Write with autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst. 5. Refer to “3.3.2 Burst write operation” 0 1 2 3 4 5 6 7 8 CK CK Command NOPNOP NOP Precharge DQS DQs Figure.11 Write interrupted by a precharge and DM timing < Burst Length=8 > WRITE A Din a0 NOP WRITE B Din a1 Din a2 Din a3 Din a4 Din a5 NOPNOP Din a0 Din a1 Din a2 Din a3 Din a4 Din a5 Din a6 Din a7 Din b0 Din b1 Din b0 Din b1 Din b2Din a6 Din a7 DM Min tDQSS DQS DQs DM Max tDQSS tDQSSmax tWPRES tWPREH tDQSSmin tWPRES tWPREH tWPRES tWPREH tDQSSmax tDQSSmin tWPRES tWPREH tWR tWR

18 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Burst Stop The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock(CK). The burst stop command has the fewest restrictions making it the easiest method to use when terminating a burst read operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and DQS(Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported during a write burst operation. The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required: 1. The BST command may only be issued on the rising edge of the onput clock, CK. 2. BST is only a valid command during Read bursts. 3. BST during a Write burst is undefined and shall not be used. 4. BST applies to all burst lengths. 5. BST is an undefined command during Read with autoprecharge and shall not be used. 6. When terminating a burst Read command, the BST command must be issued LBST(“BST Latency”) clock cycles before the clock edge at which the output buffers are tristated, where LBST equals the CAS latency for read operations. 7. When the burst terminates, the DQ and DQS pins are tristated. The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s). 0 1 2 3 4 5 6 7 8 CK CK Command NOP NOP NOP NOP DQS DQs Figure.12 Burst stop timing < Burst Length=4, CAS Latency=3 > Burst Stop Dout 0 NOPREAD A NOP Dout 1 NOP The burst read ends after a delay equal to the CAS latency. CAS Latency=3

19 Rev 0.7 64Mb Low Power DDR SDRAM Advanced DM masking The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data.(DM to data-mask latency is zero). DM must be issued at the rising or falling edge of data strobe. 0 1 2 3 4 5 6 7 8 CK CK Command NOP NOP NOP NOP DQS DQs Figure.13 DM masking timing < Burst Length=8 > NOPWRITE NOP NOPNOP Din 0 Din 1 Din 3Din 2 Din 5Din 4 Din 6 Din 7 tDQSSmax tWPRES tWPREH masked by DM=H DM

20 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Read with Auto Precharge If a read with auto-precharge command is issued, the DDR SDRAM automatically enters the precharge operation BL/2 clock later from a read with auto-precharge command when tRAS(min) is satisfied. If not, the start point of precharge operation will be delayed until tRAS(min) is satisfied. Once the precharge operation has started, the bank cannot be reactivated and the new command can not be asserted until the precharge time(tRP) has been satisfied. *NOTE : 1. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal. 0 1 2 3 4 5 6 7 8 9 10 11 CK CK NOP READ A NOP NOP DQS DQs Figure.14 Read with auto precharge timing NOPBANK A NOP NOPNOP NOP NOP NOPACTIVE Auto Precharge Dout 0 Dout 1 Dout 2 Dout 3 tRP *Bank can be reactivated at completion of tRP Auto-Precharge starts*1 tRAS(min)CAS Latency=3 < Burst Length=4, CAS Latency=3 > Command

21 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Write with Auto Precharge If A10 is high when write command is issued , the write with auto-precharge function is performed. Any new command to the same bank should not be issued until the internal precharge is completed. The internal precharge begins after keeping tWP(min). *NOTE : 1. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal. 0 1 2 3 4 5 6 7 8 9 10 11 CK CK NOP WRITE A NOP NOP DQS DQs Figure.15 Write with auto precharge timing NOPBANK A NOP NOPNOP NOP NOP NOPACTIVE Auto Precharge Din 0 Din 1 Din 2 Din 3 tRP *Bank can be reactivated at completion of tRP Internal precharge starts*1 tWR < Burst Length=4 > Command

22 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Auto Refresh & Self Refresh Auto Refresh An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the rising edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh command is applied. No control of the external address pins is required once this cycle has started because of the internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay between the auto refresh command and the next activate command or subsequent auto refresh com- mand must be greater than or equal to the tARFC(min). Self Refresh A Self Refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. Once the self Refresh command is initiated, CKE must be held low to keep the device in Self Refresh mode. After 1 clock cycle from the self refresh command, all of the external control signals including sysem clock(CK, CK) can be disabled except CKE. The clock is inter- nally disabled during Self Refresh operation to reduce power. To exit the Self Refresh mode, supply stable clock input before return- ing CKE high, assert deselect or NOP command and then assert CKE high. In case that the system uses burst auto refresh during normal operation, it is recommended to use burst 8192 auto refresh cycle immediately before entering self refresh mode and after exiting in self refresh mode. On the other hand, if the system uses the distributed auto refresh, the system only has to keep the refresh duty cycle. CK CK CK CK NOP CKE Active PRE Auto Refresh CMD CKE = High tRP tARFC(min) Figure.16 Auto refresh timing Self Refresh tIS Stable Clock tSRFX(min) tIS Figure.17 Self refresh timing Command Command

23 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Power down The device enters power down mode when CKE Low, and it exits when CKE High. Once the power down mode is initiated, all of the receiver circuits except CK and CKE are gated off to reduce power consumption. The both bank should be in idle state prior to enter- ing the precharge power down mode and CKE should be set high at least 1 tCK+tIS prior to Row active command. During power down mode, refresh operations cannot be performed, therefore the device cannot remain in power down mode longer than the refresh period(tREF) of the device. CK CK (NOP) CKE Active tIS tIS Figure.18 Power down entry and exit timing 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Precharge Precharge power down Entry Precharge power down Exit Active power down Entry Active power down Exit READ tIS tPDEX tIS Command

24 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Command Truth Tabe (V=Valid, X=Don,t Care, H=Logic High, L=Logic Low) 1. OP Code : Operation Code. A0 ~ A10 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by “Auto”. Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. 5. If A10/AP is “High” at row precharge, BA0 and BA1are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means “No Operation(NOP)” in DDR SDRAM. COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A9 ~ A0 Note Register Mode Register Set H X L L L L OP CODE 1,2 Refresh Auto Refresh H H L L L H X Self Refresh Entry L 3 Exit L H L H H H X H X X X 3 Bank Active & Row Addr. H X L L H H V Row Address Read & Column Address Auto Precharge Disable H X L H L H V L Column Address (A0 ~ A7) Auto Precharge Enable H 4 Wrie & Column Address Auto Precharge Disable H X L H L L V L Column Address (A0 ~ A7) Auto Precharge Enable H 4, 6 Deep Power Down Entry H L L H H L X Exit L H H X X X Burst Stop H X L H H L X 7 Precharge Bank Selection H X L L H L V L X All Banks X H 5 Active Power Down Entry H L H X X X XL V V V Exit L H X X X X Precharge Power Down Mode Entry H L H X X X X L H H H Exit L H H X X X L V V V DM H X X 8 No operation (NOP) : Not defined H X H X X X X L H H H 9

25 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Functional Truth Table Current State CS RAS CAS WE Address Command Action PRECHARGE STANDBY L H H L X Burst Stop ILLEGAL*2 L H L X BA, CA, A10 READ/WRITE ILLEGAL*2 L L H H BA, RA Active Bank Active, Latch RA L L H L BA, A10 PRE/PREA ILLEGAL*4 L L L H X Refresh AUTO-Refresh*5 L L L L Op-Code, Mode-Add MRS Mode Register Set*5 ACTIVE STANDBY L H H L X Burst Stop NOP L H L H BA, CA, A10 READ/READA Begin Read, Latch CA, Determine Auto-Precharge L H L L BA, CA, A10 WRITE/WRITEA Begin Write, Latch CA, Determine Auto-Precharge L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A10 PRE/PREA Precharge/Precharge All L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ L H H L X Burst Stop Terminate Burst L H L H BA, CA, A10 READ/READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 L H L L BA, CA, A10 WRITE/WRITEA ILLEGAL L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A10 PRE/PREA Terminate Burst, Precharge L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL

26 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Functional Truth Table Current State CS RAS CAS WE Address Command Action WRITE L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA Terminate Burst with DM=High, Latch CA, Begin Read, Determine Auto-Precharge*3 L H L L BA, CA, A10 WRITE/WRITEA Terminate Burst, Latch CA, Begin new Write, Determine Auto- Precharge*3 L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A10 PRE/PREA Terminate Burst with DM=High, Precharge L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL READ with AUTO PRECHARGE*6 (READA) L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL, Different Bank is LEGAL L H L L BA, CA, A10 WRITE/WRITEA ILLEGAL, Different Bank is LEGAL L L H H BA, RA Active ILLEGAL, Different Bank is LEGAL L L H L BA, A10 PRE/PREA ILLEGAL, Different Bank is LEGAL L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE with AUTO PRECHARGE*7 (WRITEA) L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL, Different Bank is LEGAL L H L L BA, CA, A10 WRITE/WRITEA ILLEGAL, Different Bank is LEGAL L L H H BA, RA Active ILLEGAL, Different Bank is LEGAL L L H L BA, A10 PRE/PREA ILLEGAL, Different Bank is LEGAL L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL

27 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Functional Truth Table Current State CS RAS CAS WE Address Command Active PRECHARGING (DURING tRP) L H H L X Burst Stop ILLEGAL*2 L H L X BA, CA, A10 READ/WRITE ILLEGAL*2 L L H H BA, RA Active ILLEGAL*2 L L H L BA, A10 PRE/PREA NOP*4(Idle after tRP) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW ACTIVATING (FROM ROW ACTIVE TO tRCD) L H H L X Burst Stop ILLEGAL*2 L H L X BA, CA, A10 READ/WRITE ILLEGAL*2 L L H H BA, RA Active ILLEGAL*2 L L H L BA, A10 PRE/PREA ILLEGAL*2 L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE RECOVERING (DURING tWR OR tCDLR) L H H L X Burst Stop ILLEGAL*2 L H L H BA, CA, A10 READ ILLEGAL*2 L H L L BA, CA, A10 WRITE WRITE L L H H BA, RA Active ILLEGAL*2 L L H L BA, A10 PRE/PREA ILLEGAL*2 L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL

28 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Functional Truth Table Current State CS RAS CAS WE Address Command Action REFRESHING L H H L X Burst Stop ILLEGAL L H L X BA, CA, A10 READ/WRITE ILLEGAL L L H H BA, RA Active ILLEGAL L L H L BA, A10 PRE/PREA ILLEGAL L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MODE REGISTER SETTING L H H L X Burst Stop ILLEGAL L H L X BA, CA, A10 READ/WRITE ILLEGAL L L H H BA, RA Active ILLEGAL L L H L BA, A10 PRE/PREA ILLEGAL L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL

29 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Functional Truth Table ABBREVIATIONS : H=High Level, L=Low level, X=Don’t Care NOTE : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around and write recovery requirements. 4. NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Refer to “Read with Auto Precharge Timing Diagram” for detailed information. 7. Refer to “Write with Auto Precharge Timing Diagram” for detailed infotmation. 8. CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 9. Power-Down and Self-Refresh and Deep Power Down Mode can be entered only from All Bank Idle state. 10. The Deep Power Down Mode is exited by asserting CKE high and full initialization is required after exting Deep Power Down Mode. ILLEGAL = Device operation and/or data integrity are not guaranteed. Current State CKEn-1 CKEn CS RAS CAS WE Add Action SELF- REFRESHING*8 L H H X X X X Exit Self-Refresh L H L H H H X Exit Self-Refresh L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP(Maintain Self-Refresh) POWER DOWN L H X X X X X Exit Power Down(Idle after tPDEX) L L X X X X X NOP(Maintain Power Down) DEEP POWER DOWN L H H X X X X Exit Deep Power Down *10 L L X X X X X NOP(Maintain Deep Power Down) ALL BANKS IDLE*9 H H X X X X X Refer to Function Truth Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State=Power Down ANY STATE other than listed above H H X X X X X Refer to Function Truth Table

30 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Absolute maximum ratings NOTE : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommand operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Conditions & Specifications DC Operating Conditions Recommended operating conditions (Voltage referenced to VSS=0V, TA=-25 to 85 ) NOTE : 1. Under all conditions, VDDQ must be less than or equal to VDD 2. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. Parameter Symbol Value Uint Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 2.7 V Voltage on VDD supply realtive to VSS VDD -0.5 ~ 2.7 V Voltage on VDD supply realtive to VSS VDDQ -0.5 ~ 2.7 V Storage temperature TSTG -55 ~ +150 Operatiing temperature TA -25 ~ +85 Power dissipation PD 1.0 W Short circuit current IOS 50 Parameter Symbol Min Max Unit Note Supply voltage(for device with a nominal VDD of 1.8V) VDD 1.7 1.95 V 1 I/O supply voltage VDDQ 1.7 1.95 V 1 Input logic high voltage VIH(DC) 0.7 x VDDQ VDDQ + 0.3 V 2 Input logic low voltage VIL(DC) -0.3 0.3 x VDDQ V 2 Output logic high voltage VOH(DC) 0.9 x VDDQ - V IOH = -0.1 Output logic low voltage VOL(DC) - 0.1 x VDDQ V IOL = 0.1 Input leakage current II -2 2 Output leakage current IOZ -5 5

31 Rev 0.7 64Mb Low Power DDR SDRAM Advanced DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, Temp = -25 to 85 ) NOTE : 1. DPD (Deep Power Down) function is an optional feature, and it will be enabled upon request. Please contact Ramsway for more information. 2. IDD specifications are tested after the device is properly intialized. 3. Input slew rate is 1V/ . 4. Definitions for IDD: LOW is defined as VIN 0.1*VDDQ; HIGH is defined as VIN 0.9*VDDQ; Parameter Symbol Test Condition DDR 266 DDR

222 Unit

(One Bank Active/Precharge current) IDD0 tRC=tRCmin; tCK=tCKmin ; CKE is HIGH; CS is HIGH between valid commands; address inputs are switching every two clock cycles; Data bus inputs are stable 80 75 Operating Current (One Bank Active-Read-Pre- charge current; Burst=4) IDD1 tRC=tRCmin; tCK=tCKmin ; CKE is HIGH; IOUT = 0 Address and control inputs changing once per clock cycle 100 95 Precharge Standby Current in power-down mode IDD2P All banks idle, CKE is LOW; CS is HIGH, tCK=tCKmin; Address and control inputs are switching every two clock cycles; Data bus inputs are stable 0.5 IDD2PS All banks idle, CKE is LOW; CS is HIGH, CK=LOW, CK=HIGH; address and control inputs are switching every two clock cycles; Data bus inputs are stable 0.5 Precharge Standby Current in non power-down mode IDD2N All banks idle, CKE is HIGH; CS is HIGH, tCK=tCKmin; Address and control inputs are switching every two clock cycles; Data bus inputs are stable 20 15 IDD2NS All banks idle, CKE is HIGH; CS is HIGH, CK=LOW, CK=HIGH; Address and control inputs are switching every two clock cycles; Data bus inputs are stable 10 10 Active Standby Current in power-down mode IDD3P One bank active, CKE is LOW; CS is HIGH, tCK=tCKmin; Address and control inputs switching every two clock cycles; Data bus inputs are stable IDD3PS One bank active, CKE is LOW; CS is HIGH, CK=LOW, CK=HIGH; Address and control inputs are switching every two clock cycles; Data bus inputs are stable Active Standby Current in non power-down mode (One Bank Active) IDD3N One bank active, CKE is HIGH; CS is HIGH, tCK=tCKmin; Address and control inputs switching every two clock cycles; Data bus inputs are stable 25 20 IDD3NS One bank active, CKE is HiGH; CS is HIGH, CK=LOW, CK=HIGH; Address and control inputs are switching every two clock cycles; Data bus inputs are stable 20 15 Operating Current (Burst Mode) IDD4R One bank active; BL=4; CL=3; tCK=tCKmin; Continuous read bursts; IOUT = 0 ; Address inputs are switching; 50% data change each burst tranfer 120 115 IDD4W One bank active; BL=4; tCK=tCKmin; Continuous write bursts; Address inputs are switching; 50% Data change each burst transfer 100 95 Refresh Current IDD5 tRC=tRFCmin; tCK=tCKmin; burst refresh; CKE is HIGH; Address and control inputs are switching; Data businputs are stable 100 95 Self Refresh Current IDD6 CKE is LOW; tCK= tCKmin ; Extended Mode Register set to all 0’s; address and control inputs are stable; Data bus inputs are stable TCSR Range Max Max

4 Banks 220 250

2 Banks 170 190

1 Bank 135 150

Deep Power Down Current IDD8 *1 Address and control inputs are stable; Data bus inputs are stable 10

32 Rev 0.7 64Mb Low Power DDR SDRAM Advanced STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: -address and command: inputs changing between HIGH and LOW once per two clock cycles -data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE. AC operating Conditions & Timing Specification NOTE : 1. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Parameter/Condition Symbol Min Max Unit Note Input High (Logic 1) Voltage, all inputs VIH(AC) 0.8 x VDDQ VDDQ + 0.3 V 1 Input Low (Logic 0) Voltage, all inputs VIL(AC) -0.3 0.2 x VDDQ V 1 Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.4 x VDDQ 0.6 x VDDQ V 2

33 Rev 0.7 64Mb Low Power DDR SDRAM Advanced AC Timing Parameters & Specification Parameter Symbol DDR266 DDR222 Unit Note Min Max Min Max Clock cycle time CL=2 tCK 12.0 15.0 CL=3 7.5 9 Row cycle time tRC 67.5 81 Row active time tRAS 45 70,000 54 70,000 RAS to CAS delay tRCD 22.5 27 Row precharge time tRP 22.5 27 Row active to Row active delay tRRD 15 15 Write recovery time tWR 15 15 Last data in to Active delay tDAL 2*tCK+tRP 2*tCK+tRP - 2 Last data in to Read command tCDLR 1 1 tCK Col. address to Col. address dealy tCCD 1 1 tCK Clock high level width tCH 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 tCK Output data access time from CK/CK CL=2 tAC 2.0 8.0 2.5 8.0 CL=3 2.0 6.0 2.5 6.0 DQS output data access time from CK/CK CL=2 tDQSCK 2.0 8.0 2.5 8.0 CL=3 2.0 6.0 2.5 6.0 Data storbe edge to output data edge tDQSQ 0.6 0.7 DQS Read Preamble CL=2 tRPRE 0.5 1.1 0.5 1.1 tCK CL=3 0.9 1.1 0.9 1.1 DQS Read Postamble tRPST 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 tCK DQS-in write preamble setup time tWPRES 0 0 DQS-in write preamble hold time tWPREH 0.25 0.25 tCK DQS-in write postamble time tWPST 0.4 0.6 0.4 0.6 tCK DQS-in write preamble time tWPRE 0.25 0.25 tCK DQS-in high level width tDQSH 0.4 0.6 0.4 0.6 tCK DQS-in low level width tDQSL 0.4 0.6 0.4 0.6 tCK DQS falling edge to CK set-up time tDSS 0.2 0.2 tCK DQS falling edge hold time from CK tDSH 0.2 0.2 tCK DQS-in cycle time tDSC 0.9 1.1 0.9 1.1 tCK Address and Control Input setup time tIS 1.3 1.5 Address and Control Input hold time tIH 1.3 1.5 Address and Control input pulse width tIPW 2.6 3.0 DQ & DM setup time to DQS tDS 0.8 1.1 5,6 DQ & DM hold time to DQS tDH 0.8 1.1 5,6 DQ & DM input pulse width tDIPW 1.8 2.4 DQ and DQS low-impedence time from CK/CK tLZ 1.0 1.0

34 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Parameter Symbol DDR266 DDR222 Unit Note Min Max Min Max DQ and DQS high-impedence time from CK/CK tHZ 6.0 7.0 Refresh inteval time 64Mb tREF 64 64 ms Mode register set cycle time tMRD 2 2 tCK Power down exit time tPDEX 1*tCK+tIS 1*tCK+tIS CKE min. pulse width (high and low pulse width) tCKE 2 2 tCK Auto refresh cycle time tARFC 80 80 Exit self refresh to active command tXSR 120 120 Data hold skew tQHS 0.75 1.0 Data hold from DQS to earliest DQ edge tQH tHPmin- tQHS tHPmin- tQHS Clock half period tHP tCLmin or tCHmin tCLmin or tCHmin

35 Rev 0.7 64Mb Low Power DDR SDRAM Advanced NOTES: 1.Input Setup/Hold Slew Rate Derating This derating table is used to increase tIS/tIH in the case where the input slew rate is below 1.0V/ . 2. Minimum 5CLK of tDAL(=tWP +tRP) is required because it need minimum 2 CLKs for tWP and minimum 3 CLKs for tRP. 3. tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25 ). tAC(max) value is measured at the low Vdd(1.7V) and cold temperature(-25 ). tAC is measured in the device with half driver strength(CL=10pF) and under the AC output load condition(fig.2 in next Page). 4. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High-Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 5. I/O Setup/Hold Slew Rate Derating This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 1.0V/ . 6. I/O Delta Rise/Fall Rate(1/slew-rate) Derating This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1=1.0V/ and slew rate 2=0.8V/ , then the Delta Rise/Fall Rate=-0.25 /V. 7. Maximum burst refresh cycle : 8 Input Setup/Hold Slew Rate tIS tIH (V/ ) ( ) ( ) 1.0 0 0 0.8 +50 +50 0.6 +100 +100 I/O Setup/Hold Slew Rate tDS tDH (V/ ) ( ) ( ) 1.0 0 0 0.8 +75 +75 0.6 +150 +150 Delta Rise/Fall Rate tDS tDH ( /V) ( ) ( ) 0 0 0 0.25 +50 +50 0.5 +100 +100

Figure 1. DC Output Load Circuit Figure 2. AC Output Load Circuit

38 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Basic timing (Setup, Hold and Access Time @ BL=4, CL=3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tIH tRPRE tRPST Hi-Z tDQSS tDSC tDQSL tWPREH tWPST tWPREStDQSQ tAC Hi-Z tHZ Db0Db1Db2Db3 tDHtDS BAa BAb Ra Ca Cb Active READ WRITE BAa Ra CS RAS CAS BA0, BA1 A10/AP ADDR (A0~An) WE DQS DQ DM COMMAND tCH tCL tCK tCH tCL tCK : Don’t Care Qa0 Qa1 Qa2 Qa3 CK CK CKE HIGH tIS tDQSH

39 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Multi Bank Interleaving READ (@BL=4, CL=3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Active CS RAS CAS BA0, BA1 A10/AP ADDR (A0~An) WE DQS DQ DM COMMAND : Don’t Care Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Active READ READ tRCD tRRD tCCD BAa BAb BAa BAb Ra Ra Rb Rb Ca Cb CK CK CKE HIGH

40 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Multi Bank Interleaving WRITE (@BL=4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Active CS RAS CAS BA0, BA1 A10/AP ADDR (A0~An) WE DQS DQ DM COMMAND : Don’t Care Da0 Da1Da2Da3Db0Db1Db2Db3 Active WRITE tRCD tRRD tCCD BAa BAb BAa BAb Ra Ra Ra Rb Ca Cb WRITE CK CK HIGHCKE

41 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Read with Auto Precharge (@BL=8) NOTE : The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal. 0 1 2 3 4 5 6 7 8 9 10 HIGH READ ACTIVE Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa7Qa6 : Don’t Care tRP Auto Precharge start Note 1 BAa BAb Ra Ca Cb COMMAND DM DQ (CL=3) DQS (CL=3) WE ADDR (A0~An) A10/AP BA0,BA1 CAS RAS CS CKE CK CK

42 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Write with Auto Precharge (@BL=8) NOTE : 1. The row active command of the precharge bank can be issued after tRP from this point The new read/write command of another activated bank can be issued from this point At burst read/write with auto precharge, CAS interrupt of the same bank is illegal. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CK CK CKE HIGH Active CS RAS CAS BA0, BA1 A10/AP ADDR (A0~An) WE DQS DQ DM COMMAND : Don’t Care Da0 Da1Da2Da3Da4Da5Da6Da7 WRITE BAa tRPtWR Auto Precharge start Note 1 BAa Ra Ca Cb

43 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Write followed by Precharge (BL=4) 0 1 2 3 4 5 6 7 8 9 10 HIGH WRITE Da0 Da1 Da3Da2 : Don’t Care tWR BAa Ca COMMAND DM DQ DQS WE ADDR (A0~An) A10/AP BA0,BA1 CAS RAS CS CKE CK CK BAa PRE CHARGE

44 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Write Interrupted by Precharge & DM (@BL=8) 0 1 2 3 4 5 6 7 8 9 10 HIGH WRITE Da0 Da1 Da3Da2 : Don’t Care BAa COMMAND DM DQ DQS WE ADDR (A0~An) A10/AP BA0,BA1 CAS RAS CS CKE CK CK BAa PRE CHARGE BAcBAb Da4 Da5 Da7Da6 Dc0 Dc1 Dc3Dc2Db1Db0 tWR tCCD WRITE WRITE Ca CcCb

45 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Write interrupted by a Read (@BL=8, CL=3) 0 1 2 3 4 5 6 7 8 9 10 HIGH WRITE Da0 Da1 Da3Da2 : Don’t Care COMMAND DM DQ DQS WE ADDR (A0~An) A10/AP BA0,BA1 CAS RAS CS CKE CK CK READ Da4 Da5 Qb0 Qb1 Qb3Qb2 tWTR BAa BAb Ca Cb Masked by DM Da6 Da7

46 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Read interrupted by Precharge (@BL=8) 0 1 2 3 4 5 6 7 8 9 10 HIGH Qa0 Qa1 Qa3Qa2 : Don’t Care COMMAND DM DQ(CL=3) DQS(CL=3) WE ADDR (A0~An) A10/AP BA0,BA1 CAS RAS CS CKE CK CK READ Qa4 Qa5 BAa Ca BAa PRE CHARGE 2 tCK Valid 4

47 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Read Interrupte by a Write & Burst Stop (@BL=8, CL=3) 0 1 2 3 4 5 6 7 8 9 10 HIGH Qb2 Qb3 Qb5Qb4 COMMAND DM DQ DQS WE ADDR (A0~An) A10/AP BA0,BA1 CAS RAS CS CKE CK CK READ Qb6 Qb7 BAa BAb WRITE Ca Cb Qb0 Qb1Qa0 Qa1 Burst Stop : Don’t Care

48 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Read Interrupted by a Read (@BL=8, CL=3) 0 1 2 3 4 5 6 7 8 9 10 HIGH READ : Don’t Care BAa COMMAND DM DQ DQS WE ADDR (A0~An) A10/AP BA0,BA1 CAS RAS CS CKE CK CK BAb Qb4 Qb5 Qb7Qb6Qb3Qb2 tCCD Ca Cb Qb1Qb0Qa1Qa0 READ

49 Rev 0.7 64Mb Low Power DDR SDRAM Advanced DM Function (@BL=8) only for write 0 1 2 3 4 5 6 7 8 9 10 HIGH WRITE : Don’t Care BAa COMMAND DM DQ DQS WE ADDR (A0~An) A10/AP BA0,BA1 CAS RAS CS CKE CK CK Qa6 Qa7Qa5Qa4Qa3Qa2Da1Da0 Ca

50 Rev 0.7 64Mb Low Power DDR SDRAM Advanced Mode Register Set NOTE : Power & Clock must be stable for 200 before precharge all banks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 5 16 17 18 19 DM DQ DQS WE ADDR (A0~An) A10/AP BA0,BA1 CAS RAS CS CKE CK CK tCK tRP ADDRESS KEY High-Z High-Z Precharge Command All Bank Mode Resister Set Command Any Command : Don’t Care