RF112L0H NXP | Alldatasheet
Document overview
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Technical content
Features
- Flexible low power tranceiver RFIC – ual-band 2x2 5GNR transceiver which is designed to mate with a baseband chip with integrated data converters and software defined modem functionality. – Tri-band sub-6GHz 2x2 TDD RF transceiver. – 2nd independent LO for use in I/Q calibration. – LO band selection is configured by software
- Receiver features – Direct conversion, low noise and high dynamic range receive chain – High speed AGC interface (RSSI detector and RX gain control) to baseband – Analog baseband filters (20, 40,80, and 100 MHz modulation bandwidth) with on-chip calibration – Analog differential I/Q interface to baseband
- Transmitter features – Direct conversion with adjustable gain transmit chain – Analog baseband filter (20, 40,80 and 100 MHz modulation bandwidth) with on-chip calibration – Analog differential I/Q interface to baseband
- Flexible frequency generation system – 122.88Mhz external oscillator for frequency reference
- Two interfaces for configuration and bi-directional data exchanges with the baseband – A low complexity high-speed custom LVDS bus (LLCP) – A traditional low-speed SPI bus
- Programmable digital core for transceiver control and calibration
- Auxiliary ADC support for calibration and external functions (voltage and temperature measurements)
- 64 pin QFN package NXP Semiconductors Document Number RF112L0H Data Sheet: Technical Data Rev. A, 12/2020 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Preliminary Confidential Proprietary
RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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1 Introduction
Table 1. Abbreviations and Definitions RF112L0H 1x2 Wi-Fi transceiver. analog baseband interfaces the bands cannot be used concurrently.
Figure 1. RF112L0H Transceiver Simplified model The RF112L0H Transceiver uses a direct conversion architecture for both RX and TX. pair for use as a low jitter 160 MHz frequency reference by other devices in the system.
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observe the wideband signal level and optimize the receiver gain for best performance. The interface allows quick updates of the transmitter and receiver gains. This figure shows top level block diagram of the RF112L0H Transceiver. Figure 2. RF112L0H Transceiver block diagram the time, to keep the LO-phase relations fixed after chip power-on.
observation receiver synthesizers are kept running all the time. and transmitters and of the other observation receiver. Figure 3. RF112L0H Digital Block Diagram
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2 Pin assignments
2.1 RF226R Transceiver QFN layout diagrams
This figure shows the complete view of the RF226R QFN diagram.
65 GND
Figure 4. RF226R Transceiver QFN layout
2.2 Pinout list
This table provides the pinout listing for the RF226R Transceiver by bus. Table 2. Pinout list by bus
5 I VDD_TRX1
3 I VDD_TRX1
1 I VDD_TRX1
8 O VDD_TRX1
7 O VDD_TRX1
Table continues on the next page...
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Table 2. Pinout list by bus (continued)
9 O VDD_TRX1
10 O VDD_TRX1
44 I VDD_TRX2
46 I VDD_TRX2
48 I VDD_TRX2
41 O VDD_TRX2
42 O VDD_TRX2
40 O VDD_TRX2
39 O VDD_TRX2
20 I VDD_TRX1
17 I VDD_TRX1
18 I VDD_TRX1
19 I VDD_TRX1
29 I VDD_TRX2
Table continues on the next page...
32 I VDD_TRX2
31 I VDD_TRX2
30 I VDD_TRX2
- The 65th pin serves as a ground and thermal pad
- Application requires pull-down 10+/-1% KOhm resistor.
- This pin can be left unconnected since they are configured as inputs with internal pull-down at reset.
- In normal mode should be pulled to ground.
- A 100 Ohms resistor should be placed between this pad and the other polarity pad.
3 Electrical characteristics
3.1 Overall DC electrical characteristics
This section describes the ratings, conditions, and other characteristics.
Electrical characteristics
RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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3.1.1 Absolute maximum ratings
This table provides the absolute maximum ratings. Table 3. Absolute maximum ratings 1,2
- Functional operating conditions are given in this table are stress ratings only, and functional operation at the maximums is
not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
- Exposing device to Absolute Maximum Ratings conditions for long periods of time may affect reliability or cause permanent
RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 11 Confidential Proprietary
3.1.2 Recommended operating conditions
This table provides the recommended operating conditions for this chip. NOTE The values shown are the recommended operating conditions and proper device operation outside these conditions is not guaranteed. Table 4. Recommended operating conditions
122.88 MHz
Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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Table 4. Recommended operating conditions (continued)
3.1.3 Power Sequencing
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1.8 V VDD_DIG_IO VDD_DIG_CORE Analog Supply Seconds Volts 0-5 ms 1.67 V 0.9 V Figure 5. RF226R Transceiver power sequencing
3.2 General specification
3.2.1 Operating Power Specification
core for the main modes of operation. Table 5. Power estimates for continuous RX mode
1.67 V analog VDD_TRX1
1.8 V digital VDD_DIG_IO,
- Continuous RX Mode includes RX1 HB, RX2 HB, RX1 MB, RX2 MB, RX1 LB, RX2 LB , AGC active.
- Maximum power scales digital dynamic power from thermal power mode by 1.2x.
Table 6. Power estimates for continuous TX mode Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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Table 6. Power estimates for continuous TX mode (continued)
- Continuous TX Mode includes TX1 HB,TX2 HB, TX1 MB,TX2 MB,TX1 LB,TX2 LB.
- Maximum power scales digital dynamic power from thermal power mode by 1.2x.
Table 7. Max current consumption
- Maximum current is provided for power supply design sizing.
3.3 Receiver specification
at RF before baseband filtering. RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 15 Confidential Proprietary
5 th order, Butterworth Gain control fc = 10 to 40 MHz dcccxt dcccxt RXBB_OUT_I_P RXBB_OUT_Q_P RXBB_OUT_Q_N RXBB_OUT_I_N V2I RSSI RX_HB_IN HB LO I HB LO Q RX mixer HB LNA V2I RSSI RX_LB_IN LB LO I LB LO Q RX mixer LB LNA Figure 6. Detailed block diagram of one receive chain. The second receive chain and the observation chains are identical, except for the RO2 chain which has no LB input. DC offset compensation algorithm has to be run in the baseband. observation receiver has no LB chain.
3.3.1 RxRF RSSI
20 MSps using sample clocks derived from the 160 MHz synthesizer, synchronized for
of 500-1000 ns in a periodic pattern. synthesizer, down-sampling and filtering is performed in the digital core. RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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3.3.2 Rx BB interface
The Rx BB output shall be connected to the ADC input in the baseband chip as shown in below: aaa-037106 BUF PCB TRX BB ADC agnd vlnp vcmout vinnR 1 R 1 R ESD R FSD R on R on R on R on R in_on R in_on R cm2 R cm2 R cm3 R cm3 R ESD C 1 C 1 C INFIX C INSW C INSWC INFIX RXBB_OUT_I_P avdd Sampling Capacitor Sampling Capacitor Sampling Switch Sampling Switch agnd agnd agnd RXBB_OUT_I_N Figure 7. Connection of Rx BB output of transceiver chip (TRX) to ADC input of mode voltage of the ADC is set by the Rx BB output buffer. ideal matching network with no losses. Table 8. Receiver specification correction and demodulation (data-aided equalization enabled). Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 17 Confidential Proprietary
Table 8. Receiver specification (continued)
4900 MHz, ChBW:
80 MHz, PVT
5300 MHz, ChBW:
6000 MHz, ChBW:
80 MHz, PV
RX total gain Gain into 100 Ω load. Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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given values are the products of Δ gd and the nominal channel BW, fchBW . Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 19 Confidential Proprietary
40 MHz channel
3.4 Transmitter specification
reconstruction filter, see figure below. the LO leakage remains low for all output power levels. RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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Reconstr, filter 5 th order, Butterworth Ic = 10 to 40 MHz Mixer load Driver PA HB LO I HB LO Q HB TXBB_IN_I_P TX_HB_OUT TXBB_IN_Q_P TXBB_IN_Q_N TXBB_IN_I_N Mixer load TX mixer TX mixer Driver PA LB LO I LB LO Q LB TX_LB_OUT Figure 8. Detailed block diagram of the transmit chains
3.4.1 Tx BB interface
Figure 9. Tx BB interface BB input common mode and input signal level requirements. RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 21 Confidential Proprietary
This table shows the transmitter specification. Unless otherwise specified, all values assume that the receivers are disabled. All RF signal levels are referred to the output of an ideal matching network with no losses. Table 9. Transmitter specification TX EVM RMS value over all subcarriers. All values are applicable at both -6 dBm and -26 dBm. Ideal IQ correction and demodulation (data-aided equalization enabled). Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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Table 9. Transmitter specification (continued) Figure 11 to Figure 15, also see spectrum maskFigure 10. Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 23 Confidential Proprietary
i.e. the given values are the products of Δ gd and the nominal channel BW, fchBW .
40 MHz channel BW
1.000 GHz ≤ f <
3.000 GHz
3.000 GHz ≤ f <
4.200 GHz
4.200 GHz ≤ f <
4.500 GHz
4.500 GHz ≤ f ≤
5.150 GHz
5.150 GHz < f <
6.500 GHz
6.500 GHz ≤ f <
7.500 GHz
Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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7.500 GHz ≤ f <
12.75 GHz
TX noise floor Spurs excluded.
100 MHz from the
Figure 10. Spectrum Mask RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 25 Confidential Proprietary
aaa-037576frequency (MHz) -43 dBr 20 30 10.25 9.75 -31 dBr -23 dBr 0 dBr Figure 11. Transmit spectrum mask, high band, 20MHz band width Figure 12. Transmit spectrum mask, low band, 20 MHz band width – at low output power limited by TX noise floor see examples in dashed blue. RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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frequency (MHz) -43 dBr -41.2 dBr Pout = -24 dBm -39.2 dBrPout = -26 dBm P out = -24 dBm P out = -26 dBm 80 120 40.5 39.5 -31 dBr -23 dBr 0 dBr Figure 15. Transmit spectrum mask, high band, 80MHz band width – at low output power limited by TX noise floor see examples in dashed blue.
3.5 Isolation
This table shows the minimum isolation between RF pins. Table 10. isolation between RF pins Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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Table 10. isolation between RF pins (continued)
3.6 Frequency generation specification
phases will be the same when returning to the same frequency after a frequency change. architecture is shown in the figure below. RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 29 Confidential Proprietary
LVDS_160M_IO_P LVDS_160M_IO_N XI XO fref_trx fref_obs1 fref_obs2 dig_clk_40M dig_clk_40M PFD Integer part Fractional part dig_clk_160Mdig_clk_160M ext_clk_160M VCO TRX Synthesizer TX2 HB path TX2_HB_LO_I TX2_HB_LO_Q D riv er Charge pump Mod. Loop filter 19.2 - 24.0 GHz PFD Integer part Fractional part VCO RO2 Synthesizer D rive r Charge pump Mod. Loop filter 19.2 - 24.0 GHz PFD Integer part Integer part Fractional part M U X VCO RO1 Synthesizer D riv er Charge pump Mod. Loop filter 19.2 - 24.0 GHz LO REF RX2 HB path RX2_HB_LO_I RX2_HB_LO_Q TX2 LB path TX2_LB_LO_I TX2_LB_LO_Q /4 RX2 LB path RX2_LB_LO_I RX2_LB_LO_Q RX1 HB path RX1_HB_LO_I RX1_HB_LO_Q RX1 LB path RX1_LB_LO_I RX1_LB_LO_Q RO2 HB path RO2_HB_LO_I RO2_HB_LO_Q RO2 WPLL RO1 WPLL WBPLL WBPLL RO1 HB path RO1_HB_LO_I RO1_HB_LO_Q RO1 HB path RO1_LB_LO_I RO1_LB_LO_Q Figure 16. LO and clock generation block diagram generated from a high frequency VCO running at four or eight times the LO frequency. coherence for the observation receivers. RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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TRX: fVCO = 19200.0 - 24000.0 MHz RO1 HB RO1 HB RO2 LB RO1 fVCO /2 1 6 3 3 .3 M H z 8 0 0 .0 M H z 8 3 3 .3 M H z9 8 0 .0 M H z 12 0 0 .0 M H z 19 6 0 .0 M H z 2 4 0 0 .0 M H z 2 9 4 0 .0 M H z 3 6 0 0 .0 M H z 3 9 2 0 .0 M H z 4 8 0 0 .0 M H z 4 9 0 0 .0 M H z 5 8 8 0 .0 M H z 7 2 0 0 .0 M H z 7 8 4 0 .0 M H z 9 6 0 0 .0 M H z 9 8 0 0 .0 M H z 6 0 0 0 .0 M H z 6 8 6 0 .0 M H z 8 4 0 0 .0 M H z 8 8 2 0 .0 M H z 1 0 8 0 0 .0 M H z 1 6 0 0 .0 M H z 1 6 6 6 .7 M H z 2 0 0 0 .0 M H z 2 0 8 3 .3 M H z 2 4 0 0 .0 M H z 2 5 0 0 .0 M H z 3 2 0 0 .0 M H z 3 3 3 3 .3 M H z 4 0 0 0 .0 M H z 416 6 .7 M H z 4 8 0 0 .0 M H z 5 0 0 0 .0 M H z 5 6 0 0 .0 M H z 5 8 3 3 .3 M H z 6 4 0 0 .0 M H z 6 6 6 6 .7 M H z 7 2 0 0 .0 M H z 7 5 0 0 .0 M H z 8 0 0 0 .0 M H z 8 3 3 3 .3 M H z 8 8 0 0 .0 M H z 9 16 6 .7 M H z 1 0 4 0 0 .0 M H z 1 0 8 3 3 .3 M H z 2 4 0 0 .0 M H z 3 0 0 0 .0 M H z 4 8 0 0 .0 M H z 6 0 0 0 .0 M H z 7 2 0 0 .0 M H z 9 0 0 0 .0 M H z 9 6 0 0 .0 M H z 2 0 0 0 .0 M H z 3 2 6 6 .7 M H z 4 0 0 0 .0 M H z 8 0 0 0 .0 M H z 8 16 6 .7 M H z 9 8 0 0 .0 M H z 1 0 0 0 0 .0 M H z 6 5 3 3 .3 M H z fVCO /4 fVCO /2 3 VCO /2 5f VCO /2 7f VCO /2 9f VCO /22f VCO 3f VCO 4f VCO 5f VCOfVCO 5f VCO /8 5f VCO /4 3f VCO /2 7f VCO /4 9f VCO /4 5f VCO /2 11f VCO /4 13f VCO /4f VCO /2 2f VCOfVCO 3f VCO /2 fVCO /4 3f VCO /8 f VCO /2fVCO /8 LB HB 2f VCO 3f VCO 5f VCO /2fVCO fVCO = 3200.0 - 4000.0 MHz RO2 fVCO = 1960.0 - 2400.0 MHz 0 1000 3000 4000 5000 6000 Frequency (MHz) 7000 8000 9000 10000 110002000 aaa-037093 3f VCO /4 Figure 17. Graphical illustration of the frequency planning. Y-axis has no relevance. RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 31 Confidential Proprietary
40 MHz 0.9 V CMOS input clock LLCP XO XO Xl LVDS_160M_IO_P LVDS_160M_IO_N Clk IO RESTN Mode DILL x440 MHz 160 MHz Figure 18. Generation of synthesizer references and digital clocks This table shows the frequency generation specification. Table 11. Frequency generation specification
24.0 GHz
2400 MHz
4000 MHz
Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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Table 11. Frequency generation specification (continued)
50 MHz)
160 MHz
Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 33 Confidential Proprietary
0.467 V1,2
RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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Figure 19. LVDS Load Termination
- Please see the figure below that defines the Vcm and the VPP_SE versus VPP_DIFF
Figure 20. LVDS Signal Swing
3.7 Digital Interface
3.7.1 LLCP Interface Characteristics
decoding across both data and strobe pair. RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 35 Confidential Proprietary
gain_data APB SLAVE MUX BASEBAND SoC LLCP INTERFACE RF112L0H LLCP INTERFACE READ RESP OR READ RSSI STREAM 8b10b DECODER DATA STROBE DECODER 8b10b ENCODER DATA STROBE ENCODER DOUT
640 Msps
320 Msps
Figure 21. LLCP communication interface
3.7.1.1 LLCP DC electrical characteristics
This table provides the DC electrical characteristics for the LLCP interface. Table 12. LLCP DC electrical characteristics (VDD_DIG_IO = 1.8V) 1
- For recommended operating conditions, seeTable 4 .
- Test condition: Rload=100Ohm between padp and padn
- Test condition: Vin = ovdd or 0.
- See figure "LLCP Input Waveform" .
3.7.1.2 LLCP AC Timing Specifications
This table provides the LLCP AC electrical characteristics for LLCP interface. Table 13. LLCP AC Electrical Characteristics Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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- Test condition: Rload=100Ohm between padp and padn.
- Measurement levels are 20-80% from output voltage
- See figure "LLCP LVDS Output Waveform" below.
equivalent propagation time for each differential signal. Figure 22. LLCP LVDS Output Waveform RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 37 Confidential Proprietary
-Vid +Vid Vicm (0.05 V to 1.57 V) Vid (100 V to 600 V) -Vid (-100 mV to -600 V) 0 mV differentialVid = padp-padn padn padp Figure 23. LLCP Input Waveform Figure 24. Output Offset Voltage Imbalance Waveform
3.8 Device start-up
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Table 14. Start-up specification LLCP (running at 100 Mbps) interfaces. calibration is reported in a register that can be polled over the LLCP or I2C interfaces. the LLCP or I2C interfaces subsequent to DLL calibration.
3.9 Specification of auxiliary functions
3.9.1 Auxiliary ADC
The auxiliary ADC will be used for internal calibration and during test. Internal signals are routed to the AUX ADC via the analog test bus. This table shows an auxiliary ADC specification. Table 15. Auxiliary ADC specification Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 39 Confidential Proprietary
Table 15. Auxiliary ADC specification (continued)
2 LSB
0.7 MHz
3.9.2 Temperature sensor
value can be processed by calibration unit to provide values in Celsius. This table shows the temperature sensor specification. Table 16. Temperature sensor specification LSB is referred to register content which is a 14-bit averaged ADC value. Output value LSB is referred to register content which is a 14-bit averaged ADC value. Table continues on the next page... RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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Table 16. Temperature sensor specification (continued)
4 Package information
4.1 Mechanical dimensions
table shows the package specification of the chip. Table 17. Package specification
25 K/W
Package information
RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 41 Confidential Proprietary
sot804-4_po 10-05-26 10-05-27 Unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 9.1 9.0 8.9 5.25 5.10 4.95 0.19 0.14 0.09 9.1 9.0 8.9 5.25 5.10 4.95 0.50 0.45 0.40 0.5 0.4 0.3 0.25 A Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm SOT804-4 A 1 b 0.30 0.21 0.18 c D (1) D h D s 0.1 0.05 0.05 v w y 0.1 y1D t 0.50 0.45 0.40 E (1) E h E s 0.19 0.14 0.09 E t e 0.5 e 1 7.5 7.5 L L 1 0.25 0 2.5 5 mm scale terminal 1 index area B AD E C yCy1 X detail X A c A 1 D h D s D t E h E s E t L L 1 b e 1 e e 1/2 e 1/2 e A C Bv Cw terminal 1 index area 17 32 64 49 Figure 25. Mechanical dimensions of the RF112L0H RF112L0H Transceiver Data Sheet, Rev. A, 12/2020
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5 Orderable part information
Table 18. Part encoding
6 Application
design for some specific pins.
6.1 External components
6.1.1 Crystal
the crystal, see the section Recommended operating conditions.
6.1.2 De-coupling
6.2 PCB design
Table 19. PCB trace requirements VDD_TRX2 Maximum trace length until all three traces are joined < 1mm. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. XO Place crystal close to XI and XO ports. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor. capacitor, <5mm for the large decoupling capacitor.
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7 Revision history
This table summarizes revisions to this document. Table 20. Revision history Rev A 12/2020 Initial NDA release.
Revision history
RF112L0H Transceiver Data Sheet, Rev. A, 12/2020 NXP Semiconductors Preliminary 45 Confidential Proprietary
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