RDA5807M RDA | Alldatasheet
Document overview
- Manufacturer or author: Anson
- PDF pages: 23
Technical content
Copyright © RDA Microelectronics Inc. 2006. All rights are reserved. The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. RDA5807M SINGLE-CHIP BROADCAST FM RADIO TUNER Rev.1.8–Aug.2014
1 General Description
The RDA5807M series is the newest generation single-chip broadcast FM stereo radio tuner with fully integrated synthesizer, IF selectivit y, RDS/RBDS and MPX decoder. The tuner uses the CMOS process, support multi-interface and require the least external component. All these make it very suitable for portable devices. The RDA5807M series has a powerful low-IF digital audio processor, this make it have optimum sound quality with varying reception conditions. The RDA5807M series support frequency range is from 50MHz to 115MHz.
1.1 Features
CMOS single-chip fully-integrated FM tuner Low power consumption Total current consumption lower than 20mA at 3.0V power supply when under normal situation Support worldwide frequency band 50 -115 MHz Support flexible channel spacing mode 100KHz, 200KHz, 50KHz and 25KHz Support RDS/RBDS Digital low-IF tuner Image-reject down-converter High performance A/D converter IF selectivity performed internally Fully integrated digital frequency synthesizer Fully integrated on-chip RF and IF VCO Fully integrated on-chip loop filter Autonomous search tuning Support 32.768KHz crystal oscillator Digital auto gain control (AGC) Digital adaptive noise cancellation Mono/stereo switch Soft mute High cut Programmable de-emphasis (50/75 s) Receive signal strength indicator (RSSI) and SNR Bass boost Volume control and mute Line-level analog output voltage 32.768 KHz 12M,24M,13M,26M,19.2M,38.4MHz Reference clock Only support 2-wire bus interface Directly support 32Ω resistance loading Integrated LDO regulator 2.7 to 3.3 V operation voltage MSOP －10pins
1.2 Applications
Cellular handsets MP3, MP4 players Portable radios PDAs, Notebook Figure1-1. RDA5807M Top View 101 RDA5807M LOUT ROUT GND VDD RCLK GND FMIN GND SCLK SDIO
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 2 of 23 Table of Contents
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 3 of 23
2 Functional Description
I ADC L DAC R DAC Q ADC Audio DSP Core digital filter MPX decoder stereo/mono audio VCO Synthesizer Interface Bus RSSI SDIO SCLK MCU LOUT ROUT FMIN RCLK 2.7-3.3 V
32.768 KHz
I PGA Q PGA RDS /RBDS Figure 2-1. RDA5807M FM Tuner Block Diagram
2.1 FM Receiver
The receiver uses a digital low-IF architecture that avoids the difficulties associated with direct conversion while delivering lower solution cost and reduces complexity, and integrates a low noise amplifier (LNA) supporting the FM broadcast band (50 to 115MHz), a multi-phase image-reject mixer array, a programmable gain control (PGA), a high resolution analog-to-digital converters (ADCs), an audio DSP and a high- fidelity digital-to-analog converters (DACs). The limiter prevents overloading and limits the amount of intermodulation products created by strong adjacent channels. The multi-phase mixer array down converts the LNA output differential RF signal to low-IF, it also has image-reject function and harmonic tones rejection. The PGA amplifies the mixer output IF signal and then digitized with ADCs. The DSP core finishes the channel selection, FM demodulation, stereo MPX decoder and output audio signal. The MPX decoder can autonomous switch from stereo to mono to limit the output noise. The DACs convert digital audio signal to analog and change the volume at same time. The DACs has low-pass feature and -3dB frequency is about 30 KHz.
2.2 Synthesizer
The frequency synthesizer generates the local oscillator signal which divi de to multi-phase, then be used to downconvert the RF input to a constant low intermediate frequency (IF). The synthesizer reference clock is 32.768 KHz. The synthesizer frequency is defined by bits CHAN[9:0] with the range from 50MHz to 115MHz.
2.3 Power Supply
The RDA5807M integrated one LDO which supplies power to the chip. The external supply voltage range is 2.7-3.3 V.
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 4 of 23
2.4 RESET and Control Interface select
The RDA5807M is RESET itself When VDD is Power up. And also support soft reset by trigger 02H BIT1 from 0 to 1. T he RDA5807M only support I 2C control interface bus mode.
2.5 Control Interface
The RDA5807M only supports I 2C control interface. The I 2C interface is compliant to I 2C Bus Specification 2.1. It includes two pins: SCLK and SDIO. A I 2C interface transfer begins with START condition, a command byte and data bytes, each byte has a followed ACK (or NACK) bit, and ends with STOP condition. The command byte includes a 7-bit chip address (0010000b) and a R/W bit. The ACK (or NACK) is always sent out by receiver. When in write transfer, data bytes is written out from MCU, and when in read transfer, data bytes is read out from RDA5807M. There is no visible register address in I 2C interface transfers. The I2C interface has a fixed start register address (0x02h for write transfer and 0x0Ah for read transfer), and an internal incremental address counter. If register address meets the end of r egister file, 0x3Ah, register address will wrap back to 0x00h. For write transfer, MCU programs registers from register 0x02h high byte, then register 0x02h low byte, then register 0x03h high byte, till the last register. RDA5807M always gives out ACK after every byte, and MCU gives out STOP condition when register programming is finished. For read transfer, after command byte from MCU, RDA5807M sends out register 0x0Ah high byte, then register 0x0Ah low byte, then register 0x0Bh high byte, till receives NACK from MCU. MCU gives out ACK for data bytes besides last data byte. MCU gives out NACK for last data byte, and then RDA5807M will return the bus to MCU, and MCU will give out STOP condition.
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 5 of 23
3 Electrical Characteristics
Table 3-1 DC Electrical Specificati on (Recommended Operation Conditions): SYMBOL DESCRIPTION MIN TYP MAX UNIT VDD Supply Voltage 2.7 3.0 3.3 V Tamb Ambient Temperature -20 27 +75 ℃ VIL CMOS Low Level Input Voltage 0 0.3*VDD V VIH CMOS High Level Input Voltage 0.7*VDD VDD V VTH CMOS Threshold Voltage 0.5*VDD V Table 3-2 DC Electrical Specificati on (Absolute Maximum Ratings): SYMBOL DESCRIPTION MIN TYP MAX UNIT Tamb Ambient Temperature -40 +90 °C IIN Input Current (1) -10 +10 mA VIN Input Voltage(1) -0.3 VDD+0.3 V Vlna FM Input Level +10 dBm Notes: 1. For Pin: SCLK, SDIO Table 3-3 Power Consumption Specification (VDD = 3 V, TA = 25℃, unless otherwise specified) SYMBOL DESCRIPTION CONDITION TYP UNIT IVDD Supply Current(1) ENABLE=1 20 mA IVDD Supply Current(2) ENABLE=1 21 mA IPD Powerdown Current ENABLE=0 15 A Notes: 1. For strong input signal condition 2. For weak input signal condition
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 6 of 23
4 Receiver Characteristics
Table 4-1 Receiver Characteristics (VDD = 3 V, TA = 25 °C, unless otherwise specified) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT General specifications Fin FM Input Frequency Range Adjust BAND Register 50 115 MHz Vrf Sensitivity1,2,3 S/N=26dB 50MHz - 1.4 1.8 V EMF 65MHz - 1.2 1.5 88MHz - 1.2 1.5 98MHz - 1.3 1.5 108MHz - 1.3 1.5 115MHz - 1.3 1.8 IP3in Input IP34 80 - - dBV αam AM Suppression1,2 m=0.3 60 - - dB S200 Adjacent Channel Selectivity ±200KHz 50 70 - dB S400 400KHz Selectivity ±400KHz 60 85 - dB VAFL; VAFR Audio L/R Output Voltage1,2 (Pins LOUT and ROUT) Volume [3:0] =1111 - 360 - mV S/N Maximum Signal to Noise Ratio1,2,3,5 Mono2 55 57 - dB Stereo6 53 55 - αSCS Stereo Channel Separation 35 - - dB RL Audio Output Loading Resistance Single-ended 32 - - Ω THD Audio Total Harmonic Distortion1,3,6 Volume[3:0] =1111 Rload=1KΩ - 0.15 0.2 Rload=32Ω - 0.2 - αAOI Audio Output L/R Imbalance1,6 - - 0.05 dB Rmute Mute Attenuation Ratio1 Volume[3:0]=0000 60 - - dB BWaudio Audio Response1 1KHz=0dB ±3dB point Low Freq9 - 100 - Hz High Freq - 14 - Pins FMIN, LOUT, ROUT Vcom_rfin Pins FMIN Input Common Mode Voltage 0 V Vcom Audio Output Common Mode Voltage8 1.0 1.05 1.1 V Notes:1. Fin=65 to 115MHz; Fmod=1KHz; de-emphasis=75s; MONO=1; L=R unless noted otherwise; 2. f = 2 2 . 5 K H z ; 3 . BAF = 300Hz to 15KHz, RBW <=10Hz; 4. |f 2-f1|>1MHz, f0=2xf1-f2, AGC disable, Fin=76 to 108MHz; 5. PRF=60dBUV ; 6 . f=75KHz,fpilot=10% 7. Measured at V EMF = 1 m V, f RF = 65 to 108MHz 8. At LOUT and ROUT pins 9. Adjustable
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 7 of 23
5 Serial Interface
5.1 I 2C Interface Timing
Table 5-1 I 2C Interface Timing Characteristics (VDD = 3 V, TA = 25 °C, unless otherwise specified) PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT SCLK Frequency fscl 0 - 400 KHz SCLK High Time thigh 0.6 - - s SCLK Low Time tlow 1.3 - - s Setup Time for START Condition tsu:sta 0.6 - - s Hold Time for START Condition thd:sta 0.6 - - s Setup Time for STOP Condition tsu:sto 0.6 - - s SDIO Input to SCLK↑ Setup tsu:dat 100 - - ns SDIO Input to SCLK↓ Hold thd:dat 0 - 900 ns STOP to START Time tbuf 1.3 - - s SDIO Output Fall Time tf:out 20+0.1C b - 250 ns SDIO Input, SCLK Rise/Fall Time tr:in / tf:in 20+0.1C b - 300 ns Input Spike Suppression tsp - - 50 ns SCLK, SDIO Capacitive Loading Cb - - 50 pF Digital Input Pin Capacitance 5 pF SCLK SDIO 1-7 8 9 1-7 8 9 1-7 8 9 START ACKdata high byteACKr/waddress data low byte ACK STOP tsu:sta thd:sta tsp START tsu:sto tbuftsu:dat thd:dat Figure 5-1. I2C Interface Write Timing Diagram SCLK SDIO 1-7 8 9 1-7 8 9 1-7 8 9 START ACKdata high byteACKr/waddress data low byte NACK STOP tsp START tbuftsu:sta thd:sta tsu:dat thd:dat tsu:sto Figure 5-2. I2C Interface Read Timing Diagram
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 8 of 23
6 Register Definition
REG BITS NAME FUNCTION DEFAULT 00H 15:0 CHIPID[7:0] Chip ID. 0x5804 02H 15 DHIZ Audio Output High-Z Disable. 0 = High impedance; 1 = Normal operation 14 DMUTE Mute Disable. 0 = Mute; 1 = Normal operation 13 MONO Mono Select. 0 = Stereo; 1 = Force mono 12 BASS Bass Boost. 0 = Disabled; 1 = Bass boost enabled
11 RCLK NON-CALIBRATE
0=RCLK clock is always supply 1=RCLK clock is not always supply when FM work ( when 1, RDA5807M can’t directly support -20 ℃ ~70 ℃ temperature. Only suppory ±20 temperature swing℃ from tune point)
10 RCLK DIRECT INPUT MODE 1=RCLK clock use the directly input mode 0
9 SEEKUP Seek Up. 0 = Seek down; 1 = Seek up 8 SEEK Seek. 0 = Disable stop seek; 1 = Enable Seek begins in the direction specified by SEEKUP and ends when a channel is found, or the entire band has been searched. The SEEK bit is set low and the STC bit is set high when the seek operation completes.
7 SKMODE Seek Mode
0 = wrap at the upper or lower band limit and continue seeking 1 = stop seeking at the upper or lower band limit 6:4 CLK_MODE[2:0] 000=32.768kHz 001=12Mhz 101=24Mhz 010=13Mhz 110=26Mhz 011=19.2Mhz 111=38.4Mhz 000
3 RDS_EN RDS/RBDS enable
If 1, rds/rbds enable
2 NEW_METHOD New Demodulate Method Enable, can improve
the receive sensitivity about 1dB. 1 SOFT_RESET Soft reset. If 0, not reset;
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 9 of 23 REG BITS NAME FUNCTION DEFAULT If 1, reset. 0 ENABLE Power Up Enable. 0 = Disabled; 1 = Enabled 03H 15:6 CHAN[9:0] Channel Select. BAND = 0 Frequency = Channel Spacing (kHz) x CHAN+ 87.0 MHz BAND = 1or 2 Frequency = Channel Spacing (kHz) x CHAN + 76.0 MHz BAND = 3 Frequency = Channel Spacing (kHz) x CHAN + 65.0 MHz CHAN is updated after a seek operation. 0x13f 5 DIRECT MODE Directly Control Mode, Only used when test. 0
4 TUNE Tune
0 = Disable 1 = Enable The tune operation begins when the TUNE bit is set high. The STC bit is set high when the tune operation completes. The tune bit is reset to low automatically when the tune operation completes.. 3:2 BAND[1:0] Band Select. 00 = 87–108 MHz (US/Europe) 01 = 76–91 MHz (Japan) 10 = 76–108 MHz (world wide) = 65 –76 MHz （East Europe） or 50-65MHz 1:0 SPACE[1:0] Channel Spacing. 00 = 100 kHz 01 = 200 kHz 10 = 50kHz 11 = 25KHz 04H 15 RSVD Reserved 0 14 STCIEN Seek/Tune Complete Interrupt Enable. 0 = Disable Interrupt 1 = Enable Interrupt Setting STCIEN = 1 will generate a low pulse on GPIO2 when the interrupt occurs.
13 RBDS 1 = RBDS mode enable
0 = RDS mode only 12 RDS_FIFO_EN 1 = RDS fifo mode enable. 0 11 DE De-emphasis. 0 = 75 µs; 1 = 50 µs
1 If 0x07h_bit<9> ( band )=1, 65-76MHz; =0, 50-76MHz
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 10 of 23 REG BITS NAME FUNCTION DEFAULT
10 RDS_FIFO_CLR 1 = clear RDS fifo 1
9 SOFTMUTE_EN If 1, softmute enable 0
8 AFCD AFC disable. If 0, afc work; If 1, afc disabled. 7 rsvd Read as 0. 0 6 I2S_ENABLE I2S enable. 0 = disabled; 1 = enabled. 5:4 GPIO3[1:0] General Purpose I/O 3.when gpio_sel=00or11 00 = High impedance 01 = Mono/Stereo indicator (ST) 10 = Low 11 = High 3:2 GPIO2[1:0] General Purpose I/O 2. when gpio_sel=10 00 = High impedance 01 = Interrupt (INT) 10 = Low 11 = High 1:0 GPIO1[1:0] General Purpose I/O 1. when gpio_sel=01 00 = High impedance 01 = Reserved 10 = Low 11 = High 05H 15 INT _MODE If 0, generate 5ms interrupt; If 1, interrupt last until read reg0CH action occurs. 14:13 Seek_mode Default value is 00; When = 10, will add the RSSI seek mode.
12 RSVD
11:8 SEEKTH[3:0] Seek SNR threshold value 1000 7:6 LNA_PORT_SEL[1:0] LNA input port selection bit: 00: no input 01: LNAN 10: LNAP 11: dual port input 5:4 LNA_ICSEL_BIT[1:0] Lna working current bit: 00=1.8mA 01=2.1mA 10=2.5mA 11=3.0mA 3:0 VOLUME[3:0] DAC Gain Control Bits (Volume). 0000=min; 1111=max 1011
2 The default noise threshold is 71dB
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 11 of 23 REG BITS NAME FUNCTION DEFAULT Volume scale is logarithmic When 0000, output mute and output impedance is very large 06H 15 RSVD reserved 0 14:13 OPEN_MODE[1:0] Open reserved register mode. 11=open behind registers writing function others: only open behind registers reading function 12 slave_master I2S slave or master. 1 = slave; 0 = master. 11 ws_lr Ws relation to l/r channel. If 0, ws=0 ->r, ws=1 ->l; If 1, ws=0 ->l, ws=1 ->r. 10 sclk_i_edge If 0, use normal sclk internally; If 1, inverte sclk internally. 9 data_signed If 0, I2S output unsigned 16-bit audio data. If 1, I2S output signed 16-bit audio data.
8 WS_I_EDGE If 0, use normal ws internally;
If 1, inverte ws internally. 7:4 I2S_SW_CNT[4:0] Only valid in master mode 4'b1000: WS_STEP_48; 4'b0111: WS_STEP=44.1kbps; 4'b0110: WS_STEP=32kbps; 4'b0101: WS_STEP=24kbps; 4'b0100: WS_STEP=22.05kbps; 4'b0011: WS_STEP=16kbps; 4'b0010: WS_STEP=12kbps; 4'b0001: WS_STEP=11.025kbps; 4'b0000: WS_STEP=8kbps;
3 SW_O_EDGE
If 1, invert ws output when as master. 0
2 SCLK_O_EDGE
If 1, invert sclk output when as master. 0
1 L_DELY
If 1, L channel data delay 1T. 0
0 R_DELY
If 1, R channel data delay 1T. 0 07H 15 RSVD Reserved 0 14:10 TH_SOFRBLEND[5:0] Threshold for noise soft blend setting, unit 2dB 10000 9 65M_50M MODE Valid when band[1:0] = 2’b11 (0x03H_bit<3:2>) 1 = 65~76 MHz; 0 = 50~76 MHz.
8 RSVD Reserved 0
7:2 SEEK_TH_OLD Seek threshold for old seek mode, Valid when Seek_Mode=10 000000
1 SOFTBLEND_EN If 1, Softblend enable 1
0 FREQ_MODE If 1, then freq setting changed. Freq = 76000(or 87000) kHz + freq_direct (08H) kHz.
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 12 of 23 REG BITS NAME FUNCTION DEFAULT 08H 15:0 freq_direct[15:0] Valid when freq_mode = 1. 0x0 0AH 15 RDSR RDS ready 0 = No RDS/RBDS group ready(default) 1 = New RDS/RBDS group ready 14 STC Seek/Tune Complete. 0 = Not complete 1 = Complete The seek/tune complete flag is set when the seek or tune operation completes. 13 SF Seek Fail. 0 = Seek successful; 1 = Seek failure The seek fail flag is set when the seek operation fails to find a channel with an RSSI level greater than SEEKTH[3:0].
12 RDSS RDS Synchronization
0 = RDS decoder not synchronized(default) 1 = RDS decoder synchronized Available only in RDS Verbose mode
11 BLK_E When RDS enable:
1 = Block E has been found 0 = no Block E has been found 10 ST Stereo Indicator. 0 = Mono; 1 = Stereo 9:0 READCHAN[9:0] Read Channel. BAND = 0 Frequency = Channel Spacing (kHz) x READCHAN[9:0]+ 87.0 MHz BAND = 1 or 2 Frequency = Channel Spacing (kHz) x READCHAN[9:0]+ 76.0 MHz BAND = 3 Frequency = Channel Spacing (kHz) x READCHAN[9:0]+ 65.0 MHz READCHAN[9:0] is updated after a tune or seek operation. 8’h00 0BH 15:9 RSSI[6:0] RSSI. 0000000 = min 1111111 = max RSSI scale is logarithmic.
8 FM TRUE 1 = the current channel is a station
0 = the current channel is not a station
7 FM_READY 1=ready
0=not ready <6:5> reserved 0 <4> ABCD_E 1= the block id of register 0cH,0dH,0eH,0fH is E 0= the block id of register 0cH, 0dH, 0eH,0fH is A, B, C, D
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 13 of 23 REG BITS NAME FUNCTION DEFAULT <3:2> BLERA[1:0] Block Errors Level of RDS_DATA_0, and is always read as Errors Level of RDS BLOCK A (in RDS mode) or BLOCK E (in RBDS mode when ABCD_E flag is 1) 00= 0 errors requiring correction 01= 1~2 errors requiring correction 10= 3~5 errors requiring correction 11= 6+ errors or error in checkword, correction not possible. Available only in RDS Verbose mode <1:0> BLERB[1:0] Block Errors Level of RDS_DATA_1, and is always read as Errors Level of RDS BLOCK B (in RDS mode ) or E (in RBDS mode when ABCD_E flag is 1). 00= 0 errors requiring correction 01= 1~2 errors requiring correction 10= 3~5 errors requiring correction 11= 6+ errors or error in checkword, correction not possible. Available only in RDS Verbose mode 0CH <15:0> RDSA[15:0] BLOCK A ( in RDS mode) or BLOCK E (in RBDS mode when ABCD_E flag is 1) 16’h5803 0DH <15:0> RDSB[15:0] BLOCK B ( in RDS mode) or BLOCK E (in RBDS mode when ABCD_E flag is 1) 16’h5804 0EH <15:0> RDSC[15:0] BLOCK C ( in RDS mode) or BLOCK E (in RBDS mode when ABCD_E flag is 1) 16’h5808 0FH <15:0> RDSD[15:0] BLOCK D ( in RDS mode) or BLOCK E (in RBDS mode when ABCD_E flag is 1) 16’h5804
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 14 of 23
7 Pins Description
Figure 7-1. RDA5807M Top View Table 7-1 RDA5807M Pins Description SYMBOL PIN DESCRIPTION GND 1,3,8 Ground. Connect to ground plane on PCB FMIN 2 FM single input RCLK 6 32.768KHz crystal oscillator and reference clock input SDIO 5 Data input/output for serial control bus SCLK 4 Clock input for serial control bus VDD 7 Power supply ROUT,LOUT 9,10 Right/Left audio output
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 15 of 23 Table 7-2 Internal Pin Configuration SYMBOL PIN DESCRIPTION FMIN 2 FMIN FMs MN1 50pF RCLK 6 SDIO /SCLK 5/4 47K Sin Sout MN1 SDIO\\SCLK
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 16 of 23
8 Application Diagram
8.1 Audio Loading Resistance Larger than 32 Ω & Reference Clock Application:
Figure 8-1. RDA5807M FM Tuner Application Diagram (Reference Clock Application)
8.1.1 Bill of Materials:
COMPONENT VALUE DESCRIPTION SUPPLIER U1 RDA5807M Broadcast FM Radio Tuner RDA J1 Common 32 Ω Resistance Headphone L1,L2,L3 100nH LC Chock for FMIN Input Murata C1,C3,C4 24pF Capacitor Murata C6,C7 4.7µF Audio AC Couple Capacitors Murata C5 22nF Power Supply Bypass Capacitor Murata C2 100pF AC Couple Capacitors Murata F1/F2 1.8K@100MHz FM Band Ferrite Murata R1,R2 10K Ω I 2C Bus Pull-up Resister Murata Notes: 1. J1: Common 32Ω Resistance Headphone; 2. U1: RDA5807M Chip; 3. V1: Power Supply (2.7~3.3V); 4. FM Choke (L1 and C1) for Audio Common and LNA Input Common; 5. Place C2 Close to 5807M pin7.
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 17 of 23
8.2 Audio Loading Resistance Larger than 32 Ω & DCXO Application:
Figure 8-2. RDA5807M FM Tuner Application Diagram (32.768K crystal)
8.2.1 Bill of Materials:
COMPONENT VALUE DESCRIPTION SUPPLIER U1 RDA5807M Broadcast FM Radio Tuner RDA J1 Common 32 Ω Resistance Headphone L1,L2,L3 100nH LC Chock for FMIN Input Murata C1,C3,C4 24pF Capacitor Murata C6,C7 4.7µF Audio AC Couple Capacitors Murata C5 22nF Power Supply Bypass Capacitor Murata C2 100pF AC Couple Capacitors Murata F1/F2 1.8K@100MHz FM Band Ferrite Murata R1,R2 10K Ω I 2C Bus Pull-up Resister Murata Notes: 1. J1: Common 32Ω Resistance Headphone; 2. U1: RDA5807M Chip; 3. V1: Power Supply (2.7~3.3V); 4. FM Choke (L1 and C1) for Audio Common and LNA Input Common; 5. Place C2 Close to 5807M pin7.
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 18 of 23
9 Physical Dimension
Figure 9-1 illustrates the package details for the RDA5807M. The package is lead-free and RoHS-compliant. Figure 9-1. 10-Pin MSOP
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 19 of 23
10 PCB Land Pattern
Figure 10-1.Classification Reflow Profile Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average Ramp-Up Rate (TSmax to Tp) 3 oC/second max. 3 oC/second max. Preheat -Temperature Min (Tsmin) -Temperature Max (Tsmax) -Time (tsmin to tsmax) 100 oC 100 oC 60-120 seconds 150 oC 200 oC 60-180 seconds Time maintained above: -Temperature (TL) -Time (tL) 183 oC 60-150seconds 217oC 60-150 seconds Peak /Classification Temperature(Tp) See Table-II See Table-III Time within 5 oC of actual Peak Temperature (t p) 10-30 seconds 20-40 seconds Ramp-Down Rate 6 oC/second max. 6 oC/seconds max. Time 25 oC to Peak Temperature 6 minutes max. 8 minutes max. Table-I Classification Reflow Profiles
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 20 of 23 Package Thickness Volume mm 3 <350 Volume mm3 ≥350 ＜2.5mm 240 + 0/-5 o C 225 + 0/-5 o C ≥2.5mm 225 + 0/-5 o C 225 + 0/-5 o C Table – II SnPb Eutectic Process – Package Peak Reflow Temperatures Package Thickness Volume mm3 ＜350 Volume mm3 350-2000 Volume mm3 ＞2000 ＜1.6mm 260 + 0 o C * 260 + 0 o C * 260 + 0 o C * 1.6mm – 2.5mm 260 + 0 o C * 250 + 0 o C * 245 + 0 o C * ≥2.5mm 250 + 0 o C * 245 + 0 o C * 245 + 0 o C * *Tolerance : The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature(this mean Peak reflow temperature + 0 o C. For example 260+ 0 o C ) at the rated MSL Level. Table – III Pb-free Process – Package Classification Reflow Temperatures Note 1: All temperature refer topside of the package. Measured on the package body surface. Note 2: The profiling tolerance is + 0 o C, - X o C (based on machine variation capability)whatever is required to control the profile process but at no time will it exceed - 5 o C. The producer assures process compatibility at the peak reflow profile temperatures defined in Table –III. Note 3: Package volume excludes external term inals(balls, bumps, lands, leads) and/or non integral heat sinks. Note 4: The maximum component temperature reached during reflow depends on package the thickness and volume. The use of convection reflow processes reduces the thermal gradients between packages. However, thermal gradients due to differences in thermal mass of SMD package may sill exist. Note 5: Components intended for use in a “lead-free” assembly process shall be evaluated using the “lead free” classification temperat ures and profiles defined in Table-I II III whether or not lead free.
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 21 of 23 RoHS Compliant The product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB) or polybrominated diphenyl ethers (PBDE), and are therefore considered RoHS compliant. ESD Sensitivity Integrated circuits are ESD sensitive and can be dam aged by static electricity. Proper ESD techniques should be used when handling these devices.
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 22 of 23 Change List REV DATE AUTHER CHANGE DESCRIPTION V1.0 2011-05-23 Chun Zhao Original Draft.
11 Notes ：
RDA Microelectronics, Inc. RDA FM PCB LAYOUT GUIDE The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of RDA. Page 23 of 23
12 Contact Information
RDA Microelectronics (Shanghai), Inc. Suite 1108 Block A, e-Wing Center, 113 Zhichun Road Haidian District, Beijing Tel: 86-10-62635360 Fax: 86-10-82612663 Postal Code: 100086 Suite 302 Building 2, 690 Bibo Road Pudong District, Shanghai Tel: 86-21-50271108 Fax: 86-21-50271099 Postal Code: 201203 Copyright © RDA Microelectronics Inc. 2006. All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.