R8CL35A

R8CL35A RENESAS | Alldatasheet

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www.renesas.com All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). REJ09B0441-0010 Rev.0.10 Revision Date: Jul 30, 2008 Preliminary R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Hardware Manual RENESAS MCU R8C FAMILY / R8C/Lx SERIES

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Notes regarding these materials

General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardwa re functions and electrical characteristics of the MCU. It is intended for users de signing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautio nary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section. The revision history summarizes the loca tions of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the R8C/L35A Group, R8C/L35B Group, R8C/L36A Group, R8C/L36B Group, R8C/L38A Group, R8C/L38B Group, R8C/L3AA Group, R8C/L3AB Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Document Type Description Document Title Document No. Shortsheet Hardware overview R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Shortsheet REJ03B0243 Hardware manual Hardware specifications (pin assignments, memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description Note: Refer to the application notes for details on using peripheral functions. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Hardware Manual This hardware manual Software manual Description of CPU instruction set R8C/Tiny Series Software Manual REJ09B0001 Application note Information on using peripheral functions and application examples Sample programs Information on writing programs in assembly language and C Available from the Renesas Technology Corp. website. Renesas technical update Product specifications, updates on documents, etc.

1. Notation of Numbers and Symbols The notation conventions for register na mes, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,” or “pin” to distinguish the three categories. Examples the PM03 bit in the PM0 register P3_5 pin, VCC pin (2) Notation of Numbers The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: 11b Hexadecimal: EFA0h Decimal: 1234

1. Register Notation The symbols and terms used in register diagrams are described below. x.x.x XXX Register (Symbol) R/W: Read and write. R: Read only. W: Write only. −: Nothing is assigned.

• Reserved bit Reserved bit. Set to specified value.
• Nothing is assigned. Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value. Operation is not guaranteed when a value is set.
• Function varies according to the operating mode. The function of the bit varies with the peripheral functi on mode. Refer to the regist er diagram for information on the individual modes. Address XXXXh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol XXX7 XXX6 XXX5 XXX4 — — XXX1 XXX0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 XXX0 XXX bit b1 b0 0 0: XXX 0 1: XXX 1 0: Do not set. 1 1: XXX R/W b1 XXX1 R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b3 — Reserved bit Set to 0. R/W b4 XXX4 XXX bit Function varies acco rding to the operating mode. R/W b5 XXX5 W b6 XXX6 R/W b7 XXX7 XXX bit 0: XXX 1: XXX R *2 *3

1. List of Abbrevia tions and Acronyms All trademarks and registered trademarks are the property of their respective owners. Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bps bits per second CRC Cyclic Redundancy Check DMA Direct Memory Access DMAC Direct Memory Access Controller GSM Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus I/O Input/Output IrDA Infrared Data Association LSB Least Significant Bit MSB Most Significant Bit NC Non-Connection PLL Phase Locked Loop PWM Pulse Width Modulation SFR Special Function Register SIM Subscriber Identity Module UART Universal Asynchrono us Receiver/Transmitter VCO Voltage Controlled Oscillator

12.2.1 Interrupt Control Register

(TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, S1TIC, S1RIC, TRAIC, TRBIC, U2BCNIC,

12.2.2 Interrupt Control Register

12.7 Interrupts of Timer RC, Timer RD, Timer RG, Synchronous Serial Communication Unit, I 2C bus

21.3.7 Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1) for Input Capture Function

21.3.14 Timer RD General Registers Ai, Bi, Ci , and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi)

21.4.17 Timer RD General Registers Ai, Bi, Ci , and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi)

21.5.14 Timer RD PWM Mode Output Level Control Register i (TRDPOCRi) (i = 0 or 1) in PWM Mode

21.5.16 Timer RD General Registers Ai, Bi, Ci , and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi)

21.6.11 Timer RD Interrupt Enable Re gister i (TRDIERi) (i = 0 or 1) in Reset Synchronous PWM Mode 396

21.6.13 Timer RD General Registers Ai, Bi, Ci , and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi)

21.7.14 Timer RD General Registers Ai, Bi, C1 , and Di (TRDGRAi, TRDGRBi, TRDGRC1, TRDGRDi)

21.8.14 Timer RD General Registers Ai, Bi, Ci , and Di (TRDGRAi, TRDGRBi, TRDGRCi, TRDGRDi)

37.21.1 Inserting Bypass Capacitor between Pins V CC and VSS as Countermeasure against Noise and

Note: 1. Blank spaces are reserved. No access is allowed. Address Register Symbol Page 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 PM0 51 0005h Processor Mode Register 1 PM1 212 0006h System Clock Control Register 0 CM0 129, 146 0007h System Clock Control Register 1 CM1 130, 147 0008h Module Standby Control Register MSTCR 280, 335, 351, 372, 389, 404, 421, 565, 597 0009h System Clock Control Register 3 CM3 131, 148 000Ah Protect Register PRCR 168 000Bh Reset Source Determination Register RSTFR 51 000Ch Oscillation Stop Detection Register OCD 132, 149 000Dh Watchdog Timer Reset Register WDTR 212 000Eh Watchdog Timer Start Register WDTS 212 000Fh Watchdog Timer Control Register WDTC 213 0010h 0011h 0012h 0013h 0014h 0015h High-Speed On-Chip Oscillator Control Register 7 FRA7 132 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch Count Source Protection Mode Register CSPR 213 001Dh 001Eh 001Fh 0020h Power-Off Mode Control Register 0 POMCR0 152 0021h 0022h 0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 133, 150 0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 133 0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 134 0026h On-Chip Reference Voltage Control Register OCVREFCR 644 0027h 0028h 0029h High-Speed On-Chip Oscillator Control Register 4 FRA4 135 002Ah High-Speed On-Chip Oscillator Control Register 5 FRA5 135 002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 135 002Ch 002Dh 002Eh 002Fh High-Speed On-Chip Oscillator Control Register 3 FRA3 135 0030h Voltage Monitor Circuit/Comparator A Control Register CMPA 64, 671 0031h Voltage Monitor Circuit Edge Select Register VCAC 65, 672 0032h 0033h Voltage Detect Register 1 VCA1 65, 672 0034h Voltage Detect Register 2 VCA2 66, 151, 673 0035h 0036h Voltage Detection 1 Level Select Register VD1LS 67 0037h 0038h Voltage Monitor 0 Circuit Control Register VW0C 68 0039h Voltage Monitor 1 Circuit Control Register VW1C 69, 674 003Ah Voltage Monitor 2 Circuit Control Register VW2C 70, 675 003Bh 003Ch 003Dh 003Eh 003Fh Address Register Symbol Page 0040h 0041h Flash Memory Ready Interrupt Control Register FMRDYIC 175 0042h 0043h INT7 Interrupt Control Register INT7IC 176 0044h INT6 Interrupt Control Register INT6IC 176 0045h INT5 Interrupt Control Register INT5IC 176 0046h INT4 Interrupt Control Register INT4IC 176 0047h Timer RC Interrupt Control Register TRCIC 175 0048h Timer RD0 Interrupt Control Register TRD0IC 175 0049h Timer RD1 Interrupt Control Register TRD1IC 175 004Ah Timer RE Interrupt Control Register TREIC 174 004Bh UART2 Transmit Interrupt Control Register S2TIC 174 004Ch UART2 Receive Interrupt Control Register S2RIC 174 004Dh Key Input Interrupt Control Register KUPIC 174 004Eh A/D Conversion Interrupt Control Register ADIC 174 004Fh SSU Interrupt Control Register / IIC bus Interrupt Control Register SSUIC/IICIC 175 0050h 0051h UART0 Transmit Interrupt Control Register S0TIC 174 0052h UART0 Receive Interrupt Control Register S0RIC 174 0053h UART1 Transmit Interrupt Control Register S1TIC 174 0054h UART1 Receive Interrupt Control Register S1RIC 174 0055h INT2 Interrupt Control Register INT2IC 176 0056h Timer RA Interrupt Control Register TRAIC 174 0057h 0058h Timer RB Interrupt Control Register TRBIC 174 0059h INT1 Interrupt Control Register INT1IC 176 005Ah INT3 Interrupt Control Register INT3IC 176 005Bh 005Ch 005Dh INT0 Interrupt Control Register INT0IC 176 005Eh UART2 Bus Collision Detection Interrupt Control Register U2BCNIC 174 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh Timer RG Interrupt Control Register TRGIC 175 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h Voltage Monitor 1 / Comparator A1 Interrupt Control Register VCMP1IC 174 0073h Voltage Monitor 2 / Comparator A2 Interrupt Control Register VCMP2IC 174 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh SFR Page Reference

Note: 1. Blank spaces are reserved. No access is allowed. Address Register Symbol Page 0080h DTC Activation Control Register DTCTL 224 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 DTCEN0 223 0089h DTC Activation Enable Register 1 DTCEN1 223 008Ah DTC Activation Enable Register 2 DTCEN2 223 008Bh DTC Activation Enable Register 3 DTCEN3 223 008Ch DTC Activation Enable Register 4 DTCEN4 223 008Dh DTC Activation Enable Register 5 DTCEN5 223 008Eh DTC Activation Enable Register 6 DTCEN6 223 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register U0MR 496 00A1h UART0 Bit Rate Register U0BRG 496 00A2h UART0 Transmit Buffer Register U0TB 497 00A3h 00A4h UART0 Transmit/Receive Control Register 0 U0C0 498 00A5h UART0 Transmit/Receive Control Register 1 U0C1 498 00A6h UART0 Receive Buffer Register U0RB 499 00A7h 00A8h UART2 Transmit/Receive Mode Register U2MR 517 00A9h UART2 Bit Rate Register U2BRG 517 00AAh UART2 Transmit Buffer Register U2TB 518 00ABh 00ACh UART2 Transmit/Receive Control Register 0 U2C0 519 00ADh UART2 Transmit/Receive Control Register 1 U2C1 520 00AEh UART2 Receive Buffer Register U2RB 521 00AFh 00B0h UART2 Digital Filter Function Select Register URXDF 522 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh UART2 Special Mode Register 5 U2SMR5 522 00BCh UART2 Special Mode Register 4 U2SMR4 523 00BDh UART2 Special Mode Register 3 U2SMR3 523 00BEh UART2 Special Mode Register 2 U2SMR2 524 00BFh UART2 Special Mode Register U2SMR 524 Address Register Symbol Page 00C0h A/D Register 0 AD0 645 00C1h 00C2h A/D Register 1 AD1 645 00C3h 00C4h A/D Register 2 AD2 645 00C5h 00C6h A/D Register 3 AD3 645 00C7h 00C8h A/D Register 4 AD4 645 00C9h 00CAh A/D Register 5 AD5 645 00CBh 00CCh A/D Register 6 AD6 645 00CDh 00CEh A/D Register 7 AD7 645 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Mode Register ADMOD 646 00D5h A/D Input Select Register ADINSEL 647 00D6h A/D Control Register 0 ADCON0 648 00D7h A/D Control Register 1 ADCON1 648 00D8h D/A0 Register DA0 668 00D9h D/A1 Register DA1 668 00DAh 00DBh 00DCh D/A Control Register DACON 668 00DDh 00DEh 00DFh 00E0h Port P0 Register P0 86 00E1h Port P1 Register P1 86 00E2h Port P0 Direction Register PD0 85 00E3h Port P1 Direction Register PD1 85 00E4h Port P2 Register P2 86 00E5h Port P3 Register P3 86 00E6h Port P2 Direction Register PD2 85 00E7h Port P3 Direction Register PD3 85 00E8h Port P4 Register P4 86 00E9h Port P5 Register P5 86 00EAh Port P4 Direction Register PD4 85 00EBh Port P5 Direction Register PD5 85 00ECh Port P6 Register P6 86 00EDh Port P7 Register P7 86 00EEh Port P6 Direction Register PD6 85 00EFh Port P7 Direction Register PD7 85 00F0h 00F1h 00F2h 00F3h 00F4h Port P10 Register P10 86 00F5h Port P11 Register P11 86 00F6h Port P10 Direction Register PD10 85 00F7h Port P11 Direction Register PD11 85 00F8h Port P12 Register P12 86 00F9h Port P13 Register P13 86 00FAh Port P12 Direction Register PD12 85 00FBh Port P13 Direction Register PD13 85 00FCh 00FDh 00FEh 00FFh

Note: 1. Blank spaces are reserved. No access is allowed. Address Register Symbol Page 0100h Timer RA Control Register TRACR 241 0101h Timer RA I/O Control Register TRAIOC 241, 244, 247, 249, 251, 254 0102h Timer RA Mode Register TRAMR 242 0103h Timer RA Prescaler Register TRAPRE 242 0104h Timer RA Register TRA 243 0105h LIN Control Register 2 LINCR2 629 0106h LIN Control Register LINCR 630 0107h LIN Status Register LINST 630 0108h Timer RB Control Register TRBCR 258 0109h Timer RB One-Shot Control Register TRBOCR 258 010Ah Timer RB I/O Control Register TRBIOC 259, 262, 266, 269, 273 010Bh Timer RB Mode Register TRBMR 259 010Ch Timer RB Prescaler Register TRBPRE 260 010Dh Timer RB Secondary Register TRBSC 260 010Eh Timer RB Primary Register TRBPR 261 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h Timer RE Second Data Register / Timer RE Counter Data Register TRESEC 447, 454 0119h Timer RE Minute Data Register / Timer RE Compare Data Register TREMIN 447, 454 011Ah Timer RE Hour Data Register TREHR 448 011Bh Timer RE Day of Week Data Register TREWK 448 011Ch Timer RE Control Register 1 TRECR1 449, 455 011Dh Timer RE Control Register 2 TRECR2 450, 455 011Eh Timer RE Count Source Select Register TRECSR 451, 456 011Fh 0120h Timer RC Mode Register TRCMR 281 0121h Timer RC Control Register 1 TRCCR1 282, 304, 312, 318 0122h Timer RC Interrupt Enable Register TRCIER 282 0123h Timer RC Status Register TRCSR 283 0124h Timer RC I/O Control Register 0 TRCIOR0 284, 299, 305 0125h Timer RC I/O Control Register 1 TRCIOR1 284, 300, 306 0126h Timer RC Counter TRC 285 0127h 0128h Timer RC General Register A TRCGRA 285 0129h 012Ah Timer RC General Register B TRCGRB 285 012Bh 012Ch Timer RC General Register C TRCGRC 285 012Dh 012Eh Timer RC General Register D TRCGRD 285 012Fh Address Register Symbol Page 0130h Timer RC Control Register 2 TRCCR2 286, 313, 319 0131h Timer RC Digital Filter Function Select Register TRCDF 286, 319 0132h Timer RC Output Master Enable Register TRCOER 287 0133h Timer RC Trigger Control Register TRCADCR 287 0134h 0135h Timer RD Control Expansion Register TRDECR 335, 352, 373, 390, 404, 421 0136h Timer RD Trigger Control Register TRDADCR 352, 373, 390, 422 0137h Timer RD Start Register TRDSTR 336, 353, 374, 391, 406, 423 0138h Timer RD Mode Register TRDMR 336, 354, 374, 391, 406, 423 0139h Timer RD PWM Mode Register TRDPMR 337, 354, 375 013Ah Timer RD Function Control Register TRDFCR 337, 355, 375, 392, 407, 424 013Bh Timer RD Output Master Enable Register 1 TRDOER1 356, 376, 393, 408, 425 013Ch Timer RD Output Master Enable Register 2 TRDOER2 356, 376, 393, 408, 425 013Dh Timer RD Output Control Register TRDOCR 357, 377, 426 013Eh Timer RD Digital Filter Function Select Register 0 TRDDF0 338 013Fh Timer RD Digital Filter Function Select Register 1 TRDDF1 338 0140h Timer RD Control Register 0 TRDCR0 339, 358, 377, 394, 409, 427 0141h Timer RD I/O Control Register A0 TRDIORA0 340, 359 0142h Timer RD I/O Control Register C0 TRDIORC0 341, 360 0143h Timer RD Status Register 0 TRDSR0 342, 361, 378, 395, 410, 428 0144h Timer RD Interrupt Enable Register 0 TRDIER0 343, 362, 379, 396, 411, 429 0145h Timer RD PWM Mode Output Level Control Register 0 TRDPOCR0 379 0146h Timer RD Counter 0 TRD0 343, 362, 380, 396, 411, 4290147h 0148h Timer RD General Register A0 TRDGRA0 344, 363, 381, 397, 412, 4300149h 014Ah Timer RD General Register B0 TRDGRB0 344, 363, 381, 397, 412, 430014Bh 014Ch Timer RD General Register C0 TRDGRC0 344, 363, 381, 397, 430014Dh 014Eh Timer RD General Register D0 TRDGRD0 344, 363, 381, 397, 412, 430014Fh 0150h Timer RD Control Register 1 TRDCR1 339, 358, 377, 409 0151h Timer RD I/O Control Register A1 TRDIORA1 340, 359 0152h Timer RD I/O Control Register C1 TRDIORC1 341, 360 0153h Timer RD Status Register 1 TRDSR1 342, 361, 378, 395, 410, 428 0154h Timer RD Interrupt Enable Register 1 TRDIER1 343, 362, 379, 396, 411, 429 0155h Timer RD PWM Mode Output Level Control Register 1 TRDPOCR1 379 0156h Timer RD Counter 1 TRD1 343, 362, 380, 4120157h 0158h Timer RD General Register A1 TRDGRA1 344, 363, 381, 397, 412, 4300159h 015Ah Timer RD General Register B1 TRDGRB1 344, 363, 381, 397, 412, 430015Bh 015Ch Timer RD General Register C1 TRDGRC1 344, 363, 381, 397, 412, 430015Dh 015Eh Timer RD General Register D1 TRDGRD1 344, 363, 381, 397, 412, 430015Fh

Note: 1. Blank spaces are reserved. No access is allowed. Address Register Symbol Page 0160h UART1 Transmit/Receive Mode Register U1MR 496 0161h UART1 Bit Rate Register U1BRG 496 0162h UART1 Transmit Buffer Register U1TB 497 0163h 0164h UART1 Transmit/Receive Control Register 0 U1C0 498 0165h UART1 Transmit/Receive Control Register 1 U1C1 498 0166h UART1 Receive Buffer Register U1RB 499 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h Timer RG Mode Register TRGMR 463 0171h Timer RG Count Control Register TRGCNTC 464 0172h Timer RG Control Register TRGCR 465, 489 0173h Timer RG Interrupt Enable Register TRGIER 466 0174h Timer RG Status Register TRGSR 467 0175h Timer RG I/O Control Register TRGIOR 468, 477, 481 0176h Timer RG Counter TRG 469 0177h 0178h Timer RG General Register A TRGGRA 470 0179h 017Ah Timer RG General Register B TRGGRB 470 017Bh 017Ch Timer RG General Register C TRGGRC 470 017Dh 017Eh Timer RG General Register D TRGGRD 470 017Fh 0180h Timer RA Pin Select Register TRASR 87, 243 0181h Timer RB/RC Pin Select Register TRBRCSR 88, 261, 288 0182h Timer RC Pin Select Register 0 TRCPSR0 89, 289 0183h Timer RC Pin Select Register 1 TRCPSR1 90, 290 0184h Timer RD Pin Select Register 0 TRDPSR0 91, 345, 364, 382, 398, 414, 432 0185h Timer RD Pin Select Register 1 TRDPSR1 92, 346, 365, 383, 399, 415, 433 0186h 0187h Timer RG Pin Select Register TRGPSR 93 0188h UART0 Pin Select Register U0SR 93, 500 0189h UART1 Pin Select Register U1SR 94, 501 018Ah UART2 Pin Select Register 0 U2SR0 95, 525 018Bh UART2 Pin Select Register 1 U2SR1 96, 526 018Ch SSU/IIC Pin Select Register SSUIICSR 97, 566, 597 018Dh Key Input Pin Select Register KISR 98, 192 018Eh INT Interrupt Input Pin Select Register INTSR 99, 185 018Fh Address Register Symbol Page 0190h 0191h 0192h 0193h SS Bit Counter Register SSBR 567 0194h SS Transmit Data Register L / IIC bus Transmit Data Register SSTDR/ ICDRT 567, 598 0195h SS Transmit Data Register H SSTDRH 567 0196h SS Receive Data Register L / IIC bus Receive Data Register SSRDR/ ICDRR 568, 598 0197h SS Receive Data Register H SSRDRH 568 0198h SS Control Register H / IIC bus Control Register 1 SSCRH / ICCR1 568, 599 0199h SS Control Register L / IIC bus Control Register SSCRL / ICCR2 569, 600 019Ah SS Mode Register / IIC bus Mode Register SSMR / ICMR 570, 601 019Bh SS Enable Register / IIC bus Interrupt Enable Register SSER / ICIER 571, 602 019Ch SS Status Register / IIC bus Status Register SSSR / ICSR 572, 603 019Dh SS Mode Register 2 / Slave Address Register SSMR2 / SAR 573, 604 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h Flash Memory Status Register FST 726 01B3h 01B4h Flash Memory Control Register 0 FMR0 728 01B5h Flash Memory Control Register 1 FMR1 730 01B6h Flash Memory Control Register 2 FMR2 732 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh 01C0h Address Match Interrupt Register 0 RMAD0 196 01C1h 01C2h 01C3h Address Match Interrupt Enable Register 0 AIER0 196 01C4h Address Match Interrupt Register 1 RMAD1 196 01C5h 01C6h 01C7h Address Match Interrupt Enable Register 1 AIER1 196 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh

Note: 1. Blank spaces are reserved. No access is allowed. Address Register Symbol Page 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h Port P0 Pull-Up Control Register P0PUR 99 01E1h Port P1 Pull-Up Control Register P1PUR 99 01E2h Port P2 Pull-Up Control Register P2PUR 99 01E3h Port P3 Pull-Up Control Register P3PUR 99 01E4h Port P4 Pull-Up Control Register P4PUR 99 01E5h Port P5 Pull-Up Control Register P5PUR 99 01E6h Port P6 Pull-Up Control Register P6PUR 99 01E7h Port P7 Pull-Up Control Register P7PUR 99 01E8h 01E9h 01EAh Port P10 Pull-Up Control Register P10PUR 100 01EBh Port P11 Pull-Up Control Register P11PUR 100 01ECh Port P12 Pull-Up Control Register P12PUR 100 01EDh Port P13 Pull-Up Control Register P13PUR 100 01EEh 01EFh 01F0h Port P10 Drive Capacity Control Register P10DRR 100 01F1h Port P11 Drive Capacity Control Register P11DRR 101 01F2h 01F3h 01F4h 01F5h Input Threshold Control Register 0 VLT0 101 01F6h Input Threshold Control Register 1 VLT1 102 01F7h Input Threshold Control Register 2 VLT2 103 01F8h Comparator B Control Register 0 INTCMP 686 01F9h 01FAh External Input Enable Register 0 INTEN 186, 686 01FBh External Input Enable Register 1 INTEN1 187 01FCh INT Input Filter Select Register 0 INTF 188, 687 01FDh INT Input Filter Select Register 1 INTF1 188 01FEh Key Input Enable Register 0 KIEN 193 01FFh Key Input Enable Register 1 KIEN1 194 Address Register Symbol Page 0200h LCD Control Register LCR0 694 0201h LCD Bias Control Register LCR1 695 0202h LCD Display Control Register LCR2 696 0203h LCD Clock Control Register LCR3 696 0204h 0205h 0206h LCD Port Select Register 0 LSE0 697 0207h LCD Port Select Register 1 LSE1 697 0208h LCD Port Select Register 2 LSE2 698 0209h LCD Port Select Register 3 LSE3 698 020Ah LCD Port Select Register 4 LSE4 699 020Bh LCD Port Select Register 5 LSE5 699 020Ch LCD Port Select Register 6 LSE6 700 020Dh LCD Port Select Register 7 LSE7 700 020Eh 020Fh 0210h LCD Display Data Register LRA0L 701 0211h LRA1L 701 0212h LRA2L 701 0213h LRA3L 701 0214h LRA4L 701 0215h LRA5L 701 0216h LRA6L 701 0217h LRA7L 701 0218h LRA8L 701 0219h LRA9L 701 021Ah LRA10L 701 021Bh LRA11L 701 021Ch LRA12L 701 021Dh LRA13L 701 021Eh LRA14L 701 021Fh LRA15L 701 0220h LRA16L 701 0221h LRA17L 701 0222h LRA18L 701 0223h LRA19L 701 0224h LRA20L 701 0225h LRA21L 701 0226h LRA22L 701 0227h LRA23L 701 0228h LRA24L 701 0229h LRA25L 701 022Ah LRA26L 701 022Bh LRA27L 701 022Ch LRA28L 701 022Dh LRA29L 701 022Eh LRA30L 701 022Fh LRA31L 701 0230h LRA32L 701 0231h LRA33L 701 0232h LRA34L 701 0233h LRA35L 701 0234h LRA36L 701 0235h LRA37L 701 0236h LRA38L 701 0237h LRA39L 701 0238h LRA40L 701 0239h LRA41L 701 023Ah LRA42L 701 023Bh LRA43L 701 023Ch LRA44L 701 023Dh LRA45L 701 023Eh LRA46L 701 023Fh LRA47L 701

Note: 1. Blank spaces are reserved. No access is allowed. Address Register Symbol Page 0240h LCD Display Data Register LRA48L 701 0241h LRA49L 701 0242h LRA50L 701 0243h LRA51L 701 0244h LRA52L 701 0245h LRA53L 701 0246h LRA54L 701 0247h LRA55L 701 0248h LRA56L 701 0249h LRA57L 701 024Ah LRA58L 701 024Bh LRA59L 701 024Ch LRA60L 701 024Dh LRA61L 701 024Eh LRA62L 701 024Fh LRA63L 701 0250h LRA64L 701 0251h LRA65L 701 0252h LRA66L 701 0253h LRA67L 701 0254h LRA68L 701 0255h LRA69L 701 0256h LRA70L 701 0257h LRA71L 701 0258h LRA72L 701 0259h LRA73L 701 025Ah LRA74L 701 025Bh LRA75L 701 025Ch LRA76L 701 025Dh LRA77L 701 025Eh LRA78L 701 025Fh LRA79L 701 0260h LRA80L 701 0261h LRA81L 701 0262h LRA82L 701 0263h LRA83L 701 0264h LRA84L 701 0265h LRA85L 701 0266h LRA86L 701 0267h LRA87L 701 0268h LRA88L 701 0269h LRA89L 701 026Ah LRA90L 701 026Bh LRA91L 701 026Ch LRA92L 701 026Dh LRA93L 701 026Eh LRA94L 701 026Fh LRA95L 701 0270h LCD Display Control Data Register LRA0H 702 0271h LRA1H 702 0272h LRA2H 702 0273h LRA3H 702 0274h LRA4H 702 0275h LRA5H 702 0276h LRA6H 702 0277h LRA7H 702 0278h LRA8H 702 0279h LRA9H 702 027Ah LRA10H 702 027Bh LRA11H 702 027Ch LRA12H 702 027Dh LRA13H 702 027Eh LRA14H 702 027Fh LRA15H 702 Address Register Symbol Page 0280h LCD Display Control Data Register LRA16H 702 0281h LRA17H 702 0282h LRA18H 702 0283h LRA19H 702 0284h LRA20H 702 0285h LRA21H 702 0286h LRA22H 702 0287h LRA23H 702 0288h LRA24H 702 0289h LRA25H 702 028Ah LRA26H 702 028Bh LRA27H 702 028Ch LRA28H 702 028Dh LRA29H 702 028Eh LRA30H 702 028Fh LRA31H 702 0290h LRA32H 702 0291h LRA33H 702 0292h LRA34H 702 0293h LRA35H 702 0294h LRA36H 702 0295h LRA37H 702 0296h LRA38H 702 0297h LRA39H 702 0298h LRA40H 702 0299h LRA41H 702 029Ah LRA42H 702 029Bh LRA43H 702 029Ch LRA44H 702 029Dh LRA45H 702 029Eh LRA46H 702 029Fh LRA47H 702 02A0h LRA48H 702 02A1h LRA49H 702 02A2h LRA50H 702 02A3h LRA51H 702 02A4h LRA52H 702 02A5h LRA53H 702 02A6h LRA54H 702 02A7h LRA55H 702 02A8h LRA56H 702 02A9h LRA57H 702 02AAh LRA58H 702 02ABh LRA59H 702 02ACh LRA60H 702 02ADh LRA61H 702 02AEh LRA62H 702 02AFh LRA63H 702 02B0h LRA64H 702 02B1h LRA65H 702 02B2h LRA66H 702 02B3h LRA67H 702 02B4h LRA68H 702 02B5h LRA69H 702 02B6h LRA70H 702 02B7h LRA71H 702 02B8h LRA72H 702 02B9h LRA73H 702 02BAh LRA74H 702 02BBh LRA75H 702 02BCh LRA76H 702 02BDh LRA77H 702 02BEh LRA78H 702 02BFh LRA79H 702

Note: 1. Blank spaces are reserved. No access is allowed. Address Register Symbol Page 02C0h LCD Display Control Data Register LRA80H 702 02C1h LRA81H 702 02C2h LRA82H 702 02C3h LRA83H 702 02C4h LRA84H 702 02C5h LRA85H 702 02C6h LRA86H 702 02C7h LRA87H 702 02C8h LRA88H 702 02C9h LRA89H 702 02CAh LRA90H 702 02CBh LRA91H 702 02CCh LRA92H 702 02CDh LRA93H 702 02CEh LRA94H 702 02CFh LRA95H 702 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh Address Register Symbol Page 2C00h DTC Transfer Vector Area 2C01h DTC Transfer Vector Area 2C02h DTC Transfer Vector Area 2C03h DTC Transfer Vector Area 2C04h DTC Transfer Vector Area 2C05h DTC Transfer Vector Area 2C06h DTC Transfer Vector Area 2C07h DTC Transfer Vector Area 2C08h DTC Transfer Vector Area 2C09h DTC Transfer Vector Area 2C0Ah DTC Transfer Vector Area : DTC Transfer Vector Area : DTC Transfer Vector Area 2C3Ah DTC Transfer Vector Area 2C3Bh DTC Transfer Vector Area 2C3Ch DTC Transfer Vector Area 2C3Dh DTC Transfer Vector Area 2C3Eh DTC Transfer Vector Area 2C3Fh DTC Transfer Vector Area 2C40h DTC Control Data 0 DTCD0 2C41h 2C42h 2C43h 2C44h 2C45h 2C46h 2C47h 2C48h DTC Control Data 1 DTCD1 2C49h 2C4Ah 2C4Bh 2C4Ch 2C4Dh 2C4Eh 2C4Fh 2C50h DTC Control Data 2 DTCD2 2C51h 2C52h 2C53h 2C54h 2C55h 2C56h 2C57h 2C58h DTC Control Data 3 DTCD3 2C59h 2C5Ah 2C5Bh 2C5Ch 2C5Dh 2C5Eh 2C5Fh 2C60h DTC Control Data 4 DTCD4 2C61h 2C62h 2C63h 2C64h 2C65h 2C66h 2C67h 2C68h DTC Control Data 5 DTCD5 2C69h 2C6Ah 2C6Bh 2C6Ch 2C6Dh 2C6Eh 2C6Fh

Note: 1. Blank spaces are reserved. No access is allowed. Address Register Symbol Page 2C70h DTC Control Data 6 DTCD6 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h 2C78h DTC Control Data 7 DTCD7 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh 2C80h DTC Control Data 8 DTCD8 2C81h 2C82h 2C83h 2C84h 2C85h 2C86h 2C87h 2C88h DTC Control Data 9 DTCD9 2C89h 2C8Ah 2C8Bh 2C8Ch 2C8Dh 2C8Eh 2C8Fh 2C90h DTC Control Data 10 DTCD10 2C91h 2C92h 2C93h 2C94h 2C95h 2C96h 2C97h 2C98h DTC Control Data 11 DTCD11 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh 2CA0h DTC Control Data 12 DTCD12 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h 2CA8h DTC Control Data 13 DTCD13 2CA9h 2CAAh 2CABh 2CACh 2CADh 2CAEh 2CAFh Address Register Symbol Page 2CB0h DTC Control Data 14 DTCD14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h DTC Control Data 15 DTCD15 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h DTC Control Data 16 DTCD16 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h 2CC8h DTC Control Data 17 DTCD17 2CC9h 2CCAh 2CCBh 2CCCh 2CCDh 2CCEh 2CCFh 2CD0h DTC Control Data 18 DTCD18 2CD1h 2CD2h 2CD3h 2CD4h 2CD5h 2CD6h 2CD7h 2CD8h DTC Control Data 19 DTCD19 2CD9h 2CDAh 2CDBh 2CDCh 2CDDh 2CDEh 2CDFh 2CE0h DTC Control Data 20 DTCD20 2CE1h 2CE2h 2CE3h 2CE4h 2CE5h 2CE6h 2CE7h 2CE8h DTC Control Data 21 DTCD21 2CE9h 2CEAh 2CEBh 2CECh 2CEDh 2CEEh 2CEFh

Note: 1. Blank spaces are reserved. No access is allowed. Address Register Symbol Page 2CF0h DTC Control Data 22 DTCD22 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h 2CF8h DTC Control Data 23 DTCD23 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh 2D00h 2D01h 0FFDBh Option Function Select Register 2 OFS2 53, 208, 215 0FFFFh Option Function Select Register OFS 52, 71, 207, 214, 724

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 1 of 809 R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group RENESAS MCU 1. Overview

1.1 Features

The R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, and R8C/L3AB Group of single- chip MCUs incorporate the R8C CPU core, which implements a powerful instruction set for a high level of efficiency and supports a 1 Mbyte address space, allowing execution of instructions at high speed. In addition, th e CPU core integrates a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow for additional power control. These MCUs use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI. Integration of many peripheral functions, including mult ifunction timer and serial interface, helps reduce the number of system components.

1.1.1 Applications

Household appliances, office equipment, audio equipment, consumer products, etc. PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 2 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

1.1.2 Differences between Groups

Tables 1.1 and 1.2 list the differences between the groups, and Table 1.3 lists the I/O ports provided for each information. The explanations in the chapters which follow apply to the R8C/L3AA Group only. Note the differences shown below. Note: 1. I/O ports are shared with I/O functi ons, such as interrupts or timers. Refer to Tables 1.15 to 1.17, Pin Name Information by Pin Number, for details. Note: 1. The symbol “ √” indicates a programmable I/O port. Table 1.1 Differences between Groups (1) Item Function R8C/L35A Group, R8C/L36A Group R8C/L38A Group, R8C/L3AA Group R8C/L35B Group, R8C/L36B Group R8C/L38B Group, R8C/L3AB Group Data flash

1 KB × 4 blocks with BGO

(background operation) function Provided Not provided Table 1.2 Differences between Groups (2) Item Function R8C/L35A Group R8C/L35B Group R8C/L36A Group R8C/L36B Group R8C/L38A Group R8C/L38B Group R8C/L3AA Group R8C/L3AB Group I/O Ports Programmable I/O ports 41 pins 52 pins 68 pins 88 pins High current drive ports 5 pi ns 8 pins 8 pins 16 pins Interrupts INT interrupt pins 5 pins 8 pins 8 pins 8 pins Key input interrupt pins 4 pins 4 pins 8 pins 8 pins Timers Timer RA pins (I/O: 1, output: 1) 1 pin (I/O pin only) 2 pins 2 pins 2 pins Timer RB pin (output: 1) None 1 pin 1 pin 1 pin Timer RD pin (I/O: 8) None None 8 pins 8 pins Timer RE pin (output: 1) None 1 pin 1 pin 1 pin Timer RG pin (I/O: 2, output: 2) None None None 4 pins A/D Converter Analog input pin 12 pins 12 pins 16 pins 20 pins LCD Drive Control Circuit LCD power supply 3 pins (VL1, VL2, VL4) 4 pins (VL1 to VL4) 4 pins (VL1 to VL4) 4 pins (VL1 to VL4) Common output pins Max. 4 pins Max. 8 pins Max. 8 pins Max. 8 pins Segment output pins Max. 24 pins Max. 32 pins Max. 48 pins Max. 56 pins Other Pin Function WKUP1 Not supported Supported Supported Supported Packages 52-pin LQFP 64-pin LQFP 80-pin LQFP 100-pin LQFP/ 100-pin QFP Table 1.3 Programmable I/O Ports Provided for Each Group Programmable I/O Port R8C/L35A Group R8C/L35B Group Total: 41 I/O pins R8C/L36A Group R8C/L36B Group Total: 52 I/O pins R8C/L38A Group R8C/L38B Group Total: 68 I/O pins R8C/L3AA Group R8C/L3AB Group Total: 88 I/O pins bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 3 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

1.1.3 Specifications

Tables 1.4 to 1.6 list the specifications. Table 1.4 Specifications (1) Item Function Specification CPU Central processing unit R8C CPU core

• Number of fundamental instructions: 89
• Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte) Memory ROM/RAM Data flash Refer to Tables 1.7 to 1.14 Product Lists. Power Supply Voltage Detection Voltage detection circuit • Power-on reset
• Voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) I/O Ports Programmable I/O ports R8C/L35A Group R8C/L35B Group
• CMOS I/O ports: 41, selectable pull-up resistor
• High current drive ports: 5 R8C/L36A Group R8C/L36B Group
• CMOS I/O ports: 52, selectable pull-up resistor
• High current drive ports: 8 R8C/L38A Group R8C/L38B Group
• CMOS I/O ports: 68, selectable pull-up resistor
• High current drive ports: 8 R8C/L3AA Group R8C/L3AB Group
• CMOS I/O ports: 88, selectable pull-up resistor
• High current drive ports: 16 Clock Clock generation circuits 4 circuits: XIN clock oscillation circuit XCIN clock oscillation circuit (32 kHz) High-speed on-chip oscillator (with frequency adjustment function) Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Division ratio selectable from 1, 2, 4, 8, and 16
• Low-power-consumption modes: Standard operating mode (high-speed clock, low-speed clock, high- speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode, power-off mode Real-time clock (timer RE) Interrupts R8C/L35A Group R8C/L35B Group
• Number of interrupt vectors: 69
• External Interrupt: 9 (INT × 5, key input × 4)
• Priority levels: 7 levels R8C/L36A Group R8C/L36B Group
• Number of interrupt vectors: 69
• External Interrupt: 12 (INT × 8, key input × 4)
• Priority levels: 7 levels R8C/L38A Group R8C/L38B Group
• Number of interrupt vectors: 69
• External Interrupt: 16 (INT × 8, key input × 8)
• Priority levels: 7 levels R8C/L3AA Group R8C/L3AB Group
• Number of interrupt vectors: 69
• External Interrupt: 16 (INT × 8, key input × 8)
• Priority levels: 7 levels Watchdog Timer • 14 bits × 1 (with prescaler)
• Selectable reset start function
• Selectable low-speed on-chip oscillator for watchdog timer DTC (Data Transfer Controller) • 1 channel
• Activation sources: 38
• Transfer modes: 2 (normal mode, repeat mode)

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 4 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Notes: 1. This applies when four pins are selected for common output. Table 1.5 Specifications (2) Item Function Specification Timer Timer RA 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode Timer RB 8 bits × 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait one- shot generation mode Timer RC 16 bits × 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output: 3 pins), PWM2 mode (PWM output: 1 pin) Timer RD 16 bits × 2 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output: 6 pins), reset synchronous PWM mode (three-phase waveform output: 6 pins, sawtooth wave modulation), complementary PWM mode (three-phase waveform output: 6 pins, triangular wave modulation), PWM3 mode (PWM output with fixed period: 2 pins) Timer RE 8 bits × 1 Real-time clock mode (counting of seconds, minutes, hours, days of week), output compare mode Timer RG 16 bits × 1 Phase-counting mode, timer mode (output compare function, input capture function), PWM mode (output: 1 pin) Serial Interface UART0, UART1 Clock synchronous serial I/O/UART × 2 channels UART2 Clock synchronous serial I/O/UART, I 2C mode (I2C-bus), multiprocessor communication function Synchronous Serial Communication Unit (SSU) 1 (shared with I2C-bus) I2C bus 1 (shared with SSU) LIN Module Hardware LIN: 1 ch annel (timer RA, UART0 used) A/D Converter R8C/L35A Group R8C/L35B Group 10-bit resolution × 12 channels, including sample and hold function, with sweep mode R8C/L36A Group R8C/L36B Group 10-bit resolution × 12 channels, including sample and hold function, with sweep mode R8C/L38A Group R8C/L38B Group 10-bit resolution × 16 channels, including sample and hold function, with sweep mode R8C/L3AA Group R8C/L3AB Group 10-bit resolution × 20 channels, including sample and hold function, with sweep mode D/A Converter 8-bit resolution × 2 circuits Comparator A • 2 circuits (shared with voltage monitor 1 and voltage monitor 2)

• External reference voltage input available Comparator B 2 circuits LCD Drive Control Circuit R8C/L35A Group R8C/L35B Group Common output: Max. 4 pins Segment output: Max. 24 pins Bias: 1/2, 1/3 Duty: static, 1/2, 1/3, 1/4 R8C/L36A Group R8C/L36B Group Common output: Max. 8 pins Segment output: Max. 32 pins (1) Duty: static, 1/2, 1/3, 1/4, 1/8 R8C/L38A Group R8C/L38B Group Common output: Max. 8 pins Segment output: Max. 48 pins (1) R8C/L3AA Group R8C/L3AB Group Common output: Max. 8 pins Segment output: Max. 56 pins (1) Voltage multiplier and dedicated regulator integrated

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 5 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 1.6 Specifications (2) Note: 1. Specify the D version if D ve rsion functions are to be used. Item Function Specification Flash Memory R8C/L35A Group R8C/L36A Group R8C/L38A Group R8C/L3AA Group

• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash) 1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function R8C/L35B Group R8C/L36B Group R8C/L38B Group R8C/L3AB Group
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 1,000 times
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function Operating Frequency/ Supply Voltage f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V) f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V) Current Consumption TBD (VCC = 5.0 V, f(XIN) = 20 MHz) TBD (VCC = 3.0 V, f(XIN) = 10 MHz) TBD (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)) TBD (VCC = 3.0 V, stop mode) TBD (VCC = 3.0 V, power-off mode, timer RE enabled) TBD (VCC = 3.0 V, power-off mode, timer RE disabled) Operating Ambient Temperature -20 to 85 °C (N version) -40 to 85°C (D version) (1)

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 6 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

1.2 Product Lists

with Memory Size and Package of R8C/Lx Group. Table 1.7 Product List for R8C/L35A Group (D): Under development Figure 1.1 Correspondence of Part No., with Memory Size and Package of R8C/L35A Group Part No. Internal ROM Capacity Internal RAM Capacity Package Type RemarksProgram ROM Data Flash R5F2L357ANFP (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0052JA-A N Version R5F2L358ANFP (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0052JA-A R5F2L35AANFP (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0052JA-A R5F2L35CANFP (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0052JA-A R5F2L357ADFP (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0052JA-A D Version R5F2L358ADFP (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0052JA-A R5F2L35AADFP (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0052JA-A R5F2L35CADFP (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0052JA-A Current of Jul 2008 Part No. R 5 F 2L 35 C A N FP Package type: FP, FA: LQFP Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L35A Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 7 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 1.8 Product List for R8C/L35B Group (D): Under development Figure 1.2 Correspondence of Part No., with Memory Size and Package of R8C/L35B Group Part No. Internal ROM Capacity Internal RAM Capacity Package Type Remarks R5F2L357BNFP (D) 48 Kbytes 6 Kbytes PLQP0052JA-A N Version R5F2L358BNFP (D) 64 Kbytes 8 Kbytes PLQP0052JA-A R5F2L35ABNFP (D) 96 Kbytes 10 Kbytes PLQP0052JA-A R5F2L35CBNFP (D) 128 Kbytes 10 Kbytes PLQP0052JA-A R5F2L357BDFP (D) 48 Kbytes 6 Kbytes PLQP0052JA-A D Version R5F2L358BDFP (D) 64 Kbytes 8 Kbytes PLQP0052JA-A R5F2L35ABDFP (D) 96 Kbytes 10 Kbytes PLQP0052JA-A R5F2L35CBDFP (D) 128 Kbytes 10 Kbytes PLQP0052JA-A Current of Jul 2008 Part No. R 5 F 2L 35 C B N FP Package type: FP, FA: LQFP Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L35B Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 8 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 1.9 Product List for R8C/L36A Group (D): Under development Figure 1.3 Correspondence of Part No., with Memory Size and Package of R8C/L36A Group Part No. Internal ROM Capacity Internal RAM Capacity Package Type RemarksProgram ROM Data Flash R5F2L367ANFP (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0064KB-A N Version R5F2L367ANFA (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0064GA-A R5F2L368ANFP (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0064KB-A R5F2L368ANFA (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0064GA-A R5F2L36AANFP (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064KB-A R5F2L36AANFA (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064GA-A R5F2L36CANFP (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064KB-A R5F2L36CANFA (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064GA-A R5F2L367ADFP (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0064KB-A D Version R5F2L367ADFA (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0064GA-A R5F2L368ADFP (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0064KB-A R5F2L368ADFA (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0064GA-A R5F2L36AADFP (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064KB-A R5F2L36AADFA (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064GA-A R5F2L36CADFP (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064KB-A R5F2L36CADFA (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0064GA-A Current of Jul 2008 Part No. R 5 F 2L 36 C A N FP Package type: FP, FA: LQFP Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L36A Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 9 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 1.10 Product List for R8C/L36B Group (D): Under development Figure 1.4 Correspondence of Part No., with Memory Size and Package of R8C/L36B Group Part No. Internal ROM Capacity Internal RAM Capacity Package Type Remarks R5F2L367BNFP (D) 48 Kbytes 6 Kbytes PLQP0064KB-A N Version R5F2L367BNFA (D) 48 Kbytes 6 Kbytes PLQP0064GA-A R5F2L368BNFP (D) 64 Kbytes 8 Kbytes PLQP0064KB-A R5F2L368BNFA (D) 64 Kbytes 8 Kbytes PLQP0064GA-A R5F2L36ABNFP (D) 96 Kbytes 10 Kbytes PLQP0064KB-A R5F2L36ABNFA (D) 96 Kbytes 10 Kbytes PLQP0064GA-A R5F2L36CBNFP (D) 128 Kbytes 10 Kbytes PLQP0064KB-A R5F2L36CBNFA (D) 128 Kbytes 10 Kbytes PLQP0064GA-A R5F2L367BDFP (D) 48 Kbytes 6 Kbytes PLQP0064KB-A D Version R5F2L367BDFA (D) 48 Kbytes 6 Kbytes PLQP0064GA-A R5F2L368BDFP (D) 64 Kbytes 8 Kbytes PLQP0064KB-A R5F2L368BDFA (D) 64 Kbytes 8 Kbytes PLQP0064GA-A R5F2L36ABDFP (D) 96 Kbytes 10 Kbytes PLQP0064KB-A R5F2L36ABDFA (D) 96 Kbytes 10 Kbytes PLQP0064GA-A R5F2L36CBDFP (D) 128 Kbytes 10 Kbytes PLQP0064KB-A R5F2L36CBDFA (D) 128 Kbytes 10 Kbytes PLQP0064GA-A Current of Jul 2008 Part No. R 5 F 2L 36 C B N FP Package type: FP, FA: LQFP Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L36B Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 10 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 1.11 Product List for R8C/L38A Group (D): Under development Figure 1.5 Correspondence of Part No., with Memory Size and Package of R8C/L38A Group Part No. Internal ROM Capacity Internal RAM Capacity Package Type RemarksProgram ROM Data Flash R5F2L387ANFP (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0080KB-A N Version R5F2L387ANFA (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0080JA-A R5F2L388ANFP (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0080KB-A R5F2L388ANFA (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0080JA-A R5F2L38AANFP (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0080KB-A R5F2L38AANFA (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0080JA-A R5F2L38CANFP (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0080KB-A R5F2L38CANFA (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0080JA-A R5F2L387ADFP (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0080KB-A D Version R5F2L387ADFA (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0080JA-A R5F2L388ADFP (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0080KB-A R5F2L388ADFA (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0080JA-A R5F2L38AADFP (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0080KB-A R5F2L38AADFA (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0080JA-A R5F2L38CADFP (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0080KB-A R5F2L38CADFA (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0080JA-A Current of Jul 2008 Part No. R 5 F 2L 38 C A N FP Package type: FP, FA: LQFP Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L38A Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 11 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 1.12 Product List for R8C/L38B Group (D): Under development Figure 1.6 Correspondence of Part No., with Memory Size and Package of R8C/L38B Group Part No. Internal ROM Capacity Internal RAM Capacity Package Type Remarks R5F2L387BNFP (D) 48 Kbytes 6 Kbytes PLQP0080KB-A N Version R5F2L387BNFA (D) 48 Kbytes 6 Kbytes PLQP0080JA-A R5F2L388BNFP (D) 64 Kbytes 8 Kbytes PLQP0080KB-A R5F2L388BNFA (D) 64 Kbytes 8 Kbytes PLQP0080JA-A R5F2L38ABNFP (D) 96 Kbytes 10 Kbytes PLQP0080KB-A R5F2L38ABNFA (D) 96 Kbytes 10 Kbytes PLQP0080JA-A R5F2L38CBNFP (D) 128 Kbytes 10 Kbytes PLQP0080KB-A R5F2L38CBNFA (D) 128 Kbytes 10 Kbytes PLQP0080JA-A R5F2L387BDFP (D) 48 Kbytes 6 Kbytes PLQP0080KB-A D Version R5F2L387BDFA (D) 48 Kbytes 6 Kbytes PLQP0080JA-A R5F2L388BDFP (D) 64 Kbytes 8 Kbytes PLQP0080KB-A R5F2L388BDFA (D) 64 Kbytes 8 Kbytes PLQP0080JA-A R5F2L38ABDFP (D) 96 Kbytes 10 Kbytes PLQP0080KB-A R5F2L38ABDFA (D) 96 Kbytes 10 Kbytes PLQP0080JA-A R5F2L38CBDFP (D) 128 Kbytes 10 Kbytes PLQP0080KB-A R5F2L38CBDFA (D) 128 Kbytes 10 Kbytes PLQP0080JA-A Current of Jul 2008 Part No. R 5 F 2L 38 C B N FP Package type: FP, FA: LQFP Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L38B Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 12 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 1.13 Product List for R8C/L3AA Group (D): Under development Figure 1.7 Correspondence of Part No., with Memory Size and Package of R8C/L3AA Group Part No. Internal ROM Capacity Internal RAM Capacity Package Type RemarksProgram ROM Data Flash R5F2L3A7ANFP (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0100KB-A N Version R5F2L3A7ANFA (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PRQP0100JD-B R5F2L3A8ANFP (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0100KB-A R5F2L3A8ANFA (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PRQP0100JD-B R5F2L3AAANFP (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0100KB-A R5F2L3AAANFA (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PRQP0100JD-B R5F2L3ACANFP (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0100KB-A R5F2L3ACANFA (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PRQP0100JD-B R5F2L3A7ADFP (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PLQP0100KB-A D Version R5F2L3A7ADFA (D) 48 Kbytes 1 Kbyte × 4 6 Kbytes PRQP0100JD-B R5F2L3A8ADFP (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PLQP0100KB-A R5F2L3A8ADFA (D) 64 Kbytes 1 Kbyte × 4 8 Kbytes PRQP0100JD-B R5F2L3AAADFP (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0100KB-A R5F2L3AAADFA (D) 96 Kbytes 1 Kbyte × 4 10 Kbytes PRQP0100JD-B R5F2L3ACADFP (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PLQP0100KB-A R5F2L3ACADFA (D) 128 Kbytes 1 Kbyte × 4 10 Kbytes PRQP0100JD-B Current of Jul 2008 Part No. R 5 F 2L 3A C A N FP Package type: FP: LQFP (0.50 mm pin pitch) FA: LQFP (0.65 mm pin pitch) Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L3AA Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 13 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 1.14 Product List for R8C/L3AB Group (D): Under development Figure 1.8 Correspondence of Part No., with Memory Size and Package of R8C/L3AB Group Part No. Internal ROM Capacity Internal RAM Capacity Package Type Remarks R5F2L3A7BNFP (D) 48 Kbytes 6 Kbytes PLQP0100KB-A N Version R5F2L3A7BNFA (D) 48 Kbytes 6 Kbytes PRQP0100JD-B R5F2L3A8BNFP (D) 64 Kbytes 8 Kbytes PLQP0100KB-A R5F2L3A8BNFA (D) 64 Kbytes 8 Kbytes PRQP0100JD-B R5F2L3AABNFP (D) 96 Kbytes 10 Kbytes PLQP0100KB-A R5F2L3AABNFA (D) 96 Kbytes 10 Kbytes PRQP0100JD-B R5F2L3ACBNFP (D) 128 Kbytes 10 Kbytes PLQP0100KB-A R5F2L3ACBNFA (D) 128 Kbytes 10 Kbytes PRQP0100JD-B R5F2L3A7BDFP (D) 48 Kbytes 6 Kbytes PLQP0100KB-A D Version R5F2L3A7BDFA (D) 48 Kbytes 6 Kbytes PRQP0100JD-B R5F2L3A8BDFP (D) 64 Kbytes 8 Kbytes PLQP0100KB-A R5F2L3A8BDFA (D) 64 Kbytes 8 Kbytes PRQP0100JD-B R5F2L3AABDFP (D) 96 Kbytes 10 Kbytes PLQP0100KB-A R5F2L3AABDFA (D) 96 Kbytes 10 Kbytes PRQP0100JD-B R5F2L3ACBDFP (D) 128 Kbytes 10 Kbytes PLQP0100KB-A R5F2L3ACBDFA (D) 128 Kbytes 10 Kbytes PRQP0100JD-B Current of Jul 2008 Part No. R 5 F 2L 3A C B N FP Package type: FP: LQFP (0.50 mm pin pitch) FA: LQFP (0.65 mm pin pitch) Classification N: Operating ambient temperature -20°C to 85°C D: Operating ambient temperature -40°C to 85°C ROM capacity 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/L3AB Group R8C/Lx Series Memory type F: Flash memory Renesas MCU Renesas semiconductor

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 14 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

1.3 Block Diagrams

Figure 1.9 shows a Block Diagram of R8C/L35A and R8C/L35B Groups. Figure 1.10 shows a Block Diagram of R8C/L36A and R8C/L36B Groups. Figure 1.11 shows a Block Diagram of R8C/L38A and R8C/L38B Groups. Figure 1.12 shows a Block Diagram of R8C/L3AA and R8C/L3AB Groups. Figure 1.9 Block Diagram of R8C/L35A and R8C/L35B Groups Watchdog timer (14 bits) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT RAM (2) Multiplier Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 bits × 2) Timer RE (8 bits × 1) Timer RG (16 bits × 1) R8C CPU core Memory R0H R0L R1H R1L FB SB USP ISP INTB PC FLG I/O ports Notes: 1. ROM capacity varies with MCU type. 2. RAM capacity varies with MCU type. A/D converter (10 bits × 12 channels) UART or clock synchronous serial I/O (8 bits × 3) I2C bus or SSU (8 bits × 1) LIN module Port P0 Port P3 Port P4 Port P2 ROM (1) Peripheral functions LCD drive control circuit Common output: Max. 4 pins Segment output: Max. 24 pins D/A converter (8 bits × 2 channels) Port P11 Port P12 Port P13 Port P7 Comparator A Comparator B DTC

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 15 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 1.10 Block Diagram of R8C/L36A and R8C/L36B Groups Watchdog timer (14 bits) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT RAM (2) Multiplier Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 bits × 2) Timer RE (8 bits × 1) Timer RG (16 bits × 1) R8C CPU core Memory R0H R0L R1H R1L FB SB USP ISP INTB PC FLG I/O ports Notes: 1. ROM capacity varies with MCU type. 2. RAM capacity varies with MCU type. A/D converter (10 bits × 12 channels) UART or clock synchronous serial I/O (8 bits × 3) I2C bus or SSU (8 bits × 1) LIN module Port P0 Port P3 Port P4 Port P2 ROM (1) Peripheral functions LCD drive control circuit Common output: Max. 8 pins Segment output: Max. 32 pins D/A converter (8 bits × 2 channels) Port P11 Port P12 Port P13 Port P7 Comparator A Comparator B DTC

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 16 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 1.11 Block Diagram of R8C/L38A and R8C/L38B Groups Watchdog timer (14 bits) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT RAM (2) Multiplier Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 bits × 2) Timer RE (8 bits × 1) Timer RG (16 bits × 1) R8C CPU core Memory R0H R0L R1H R1L FB SB USP ISP INTB PC FLG I/O ports Notes: 1. ROM capacity varies with MCU type. 2. RAM capacity varies with MCU type. A/D converter (10 bits × 16 channels) UART or clock synchronous serial I/O (8 bits × 3) I2C bus or SSU (8 bits × 1) LIN module Port P0 Port P3 Port P4 Port P2 ROM (1) Peripheral functions LCD drive control circuit Common output: Max. 8 pins Segment output: Max. 48 pins D/A converter (8 bits × 2 channels) Port P11 Port P12 Port P13 Port P7 Comparator A Comparator B DTC Port P1 Port P6

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 17 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 1.12 Block Diagram of R8C/L3AA and R8C/L3AB Groups Watchdog timer (14 bits) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT RAM (2) Multiplier Timers Timer RA (8 bits × 1) Timer RB (8 bits × 1) Timer RC (16 bits × 1) Timer RD (16 bits × 2) Timer RE (8 bits × 1) Timer RG (16 bits × 1) R8C CPU core Memory R0H R0L R1H R1L FB SB USP ISP INTB PC FLG I/O ports Notes: 1. ROM capacity varies with MCU type. 2. RAM capacity varies with MCU type. A/D converter (10 bits × 20 channels) UART or clock synchronous serial I/O (8 bits × 3) I2C bus or SSU (8 bits × 1) LIN module Port P0 Port P1 Port P3 Port P5Port P4 Port P2 ROM (1) Peripheral functions LCD drive control circuit Common output: Max. 8 pins Segment output: Max. 56 pins D/A converter (8 bits × 2 channels) Port P6 Port P10 Port P11 Port P12 Port P13 Port P7 Comparator A Comparator B DTC

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 18 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

1.4 Pin Assignments

number. Figure 1.13 Pin Assignment (Top View) of PLQP0052JA-A Package 27282930313233343536373839 13121110987654321 P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3 P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3 P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2 P11_0/SCL/SSCK/(CLK2/INT0)/IVREF1/LVCOUT1 P7_7/COM0 P7_6/COM1 P7_5/COM2 P7_4/COM3 P4_7/SEG39/TRCIOD/TRCIOB P4_6/SEG38/TRCIOC/TRCIOB P4_5/SEG37/TRCIOB P4_4/SEG36/TRCIOA/TRCTRG P4_3/SEG35/TRCCLK/TRCTRG P13_2/AN2/RXD0/LVCMP1 P13_3/AN3/CLK0/LVCMP2 VL4 CL1/P12_2 CL2/P12_3 VL2 VL1 P0_0/SEG0/AN4 P0_1/SEG1/AN5 P0_2/SEG2/AN6 P0_3/SEG3/AN7 P0_4/SEG4/AN8 P0_5/SEG5/AN9 R8C/L35A Group R8C/L35B Group P11_4/TRAIO/(INT4/RXD0) P12_0/XIN VCC/AVCC XCOUT RESET P12_1/XOUT XCIN P13_0/AN0/DA0 P13_1/AN1/DA1/TXD0/LVREF VREF WKUP0 MODE VSS/AVSS P2_7/SEG23/KI7 P3_0/SEG24/INT0 P4_0/SEG32/TXD1 P4_1/SEG33/RXD1 P4_2/SEG34/CLK1 P3_1/SEG25/INT1 P3_2/SEG26/INT2 P3_3/SEG27/INT3 P0_6/SEG6/AN10 P0_7/SEG7/AN11 P2_4/SEG20/KI4 P2_5/SEG21/KI5 P2_6/SEG22/KI6 Notes: 1. The pin in parentheses can be assigned by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions. PLQP0052JA-A (52P6A-A) (top view)

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 19 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 1.14 Pin Assignment (Top View) of PLQP0064KB-A and PLQP0064GA-A Packages P7_6/COM1 P7_5/COM2 P7_4/COM3 P7_3/SEG55/COM4 P7_2/SEG54/COM5 P7_1/SEG53/COM6 P7_0/SEG52/COM7 P4_7/SEG39/TRCIOD/TRCIOB P4_6/SEG38/TRCIOC/TRCIOB P4_5/SEG37/TRCIOB P4_4/SEG36/TRCIOA/TRCTRG P4_3/SEG35/TRCCLK/TRCTRG P4_2/SEG34/CLK1 P7_7/COM0 P11_0/SCL/SSCK/(CLK2/INT0)/IVREF1/LVCOUT1 P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2 P13_3/AN3/CLK0/LVCMP2 VL4 CL1/P12_2 CL2/P12_3 VL3 VL2 VL1 P0_0/SEG0/AN4 P0_1/SEG1/AN5 P0_2/SEG2/AN6 P0_3/SEG3/AN7 P0_4/SEG4/AN8 P0_5/SEG5/AN9 P13_2/AN2/RXD0/LVCMP1 P13_1/AN1/DA1/TXD0/LVREF P13_0/AN0/DA0/WKUP1 36373839404142434445464748 33 3435 131211109876543211 6 1514 P2_7/SEG23/KI7 P3_0/SEG24/INT0 P3_4/SEG28/INT4 P3_5/SEG29/INT5 P3_6/SEG30/INT6 P3_1/SEG25/INT1 P3_2/SEG26/INT2 P3_3/SEG27/INT3 P0_6/SEG6/AN10 P2_5/SEG21/KI5 P2_6/SEG22/KI6 P3_7/SEG31/INT7/ADTRG/TRCTRG P4_0/SEG32/TXD1 P4_1/SEG33/RXD1 P0_7/SEG7/AN11 P2_4/SEG20/KI4 RESET P12_1/XOUT P11_7/TREO/(INT7/ADTRG) P11_6/TRBO/(INT6) P11_5/TRAO/(INT5) VSS/AVSS P12_0/XIN VCC/AVCC WKUP0 XCIN XCOUT P11_4/TRAIO/(INT4/RXD0) P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3 P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3 VREF MODE PLQP0064KB-A (64P6Q-A) PLQP0064GA-A (64P6U-A) (top view) R8C/L36A Group R8C/L36B Group Notes: 1. The pin in parentheses can be assigned by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions.

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 20 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 1.15 Pin Assignment (Top View) of PLQP0080KB-A and PLQP0080JA-A Packages 131211109876543211 6 1514 MODE XCIN VSS/AVSS P12_0/XIN VCC/AVCC XCOUT RESET P12_1/XOUT P13_2/AN2/RXD0/LVCMP1 WKUP0 VREF P11_7/TREO/(INT7/ADTRG) P11_6/TRBO/(INT6) P11_5/TRAO/(INT5) P13_1/AN1/DA1/TXD0/LVREF P13_0/AN0/DA0/WKUP1 17 20 1918P11_4/TRAIO/(INT4/RXD0) P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3 P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3 P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2 P7_1/SEG53/COM6 P7_0/SEG52/COM7 P6_6/SEG50/TRDIOC1 P6_5/SEG49/TRDIOB1 P6_4/SEG48/TRDIOA1 P6_3/SEG47/TRDIOD0 P6_2/SEG46/TRDIOC0 P6_1/SEG45/TRDIOB0 P6_0/SEG44/TRDIOA0/TRDCLK P4_7/SEG39/TRCIOD/TRCIOB P4_6/SEG38/TRCIOC/TRCIOB P4_5/SEG37/TRCIOB P7_2/SEG54/COM5 P7_3/SEG55/COM4 P7_4/COM3 P7_5/COM2 P7_6/COM1 P7_7/COM0 P11_0/SCL/SSCK/(CLK2/INT0)/IVREF1/LVCOUT1 P2_6/SEG22/KI6 P2_7/SEG23/KI7 P3_3/SEG27/INT3 P3_4/SEG28/INT4 P3_5/SEG29/INT5 P3_0/SEG24/INT0 P3_1/SEG25/INT1 P3_2/SEG26/INT2 P2_1/SEG17/KI1 P2_4/SEG20/KI4 P2_5/SEG21/KI5 P3_6/SEG30/INT6 P3_7/SEG31/INT7/ADTRG/TRCTRG P4_0/SEG32/TXD1 P2_2/SEG18/KI2 P2_3/SEG19/KI3 48495051525354555657585960 45 4647 44 41 4243 P4_1/SEG33/RXD1 P4_2/SEG34/CLK1 P4_3/SEG35/TRCCLK/TRCTRG P4_4/SEG36/TRCIOA/TRCTRG P0_0/SEG0/AN4 P0_1/SEG1/AN5 P0_2/SEG2/AN6 P0_3/SEG3/AN7 P0_4/SEG4/AN8 P0_5/SEG5/AN9 P0_6/SEG6/AN10 P0_7/SEG7/AN11 P1_0/SEG8/AN12 P1_1/SEG9/AN13 P1_2/SEG10/AN14 P1_3/SEG11/AN15 P2_0/SEG16/KI0 VL1 VL2 VL3 77CL2/P12_3 78CL1/P12_2 79VL4 80P13_3/AN3/CLK0/LVCMP2 R8C/L38A Group R8C/L38B Group PLQP0080KB-A (80P6Q-A) PLQP0080JA-A (FP-80W/FP-80WV) (top view) P6_7/SEG51/TRDIOD1 Notes: 1. The pin in parentheses can be assigned by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions.

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 21 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 1.16 Pin Assignment (Top View) of PLQP0100KB-A Package 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 42 5 51525354555657585960616263646566676869707172737475 100 P0_4/SEG4/AN8 P0_5/SEG5/AN9 P0_6/SEG6/AN10 P0_7/SEG7/AN11 P1_0/SEG8/AN12 P1_1/SEG9/AN13 P1_2/SEG10/AN14 P1_3/SEG11/AN15 P1_4/SEG12 P1_5/SEG13 P1_6/SEG14 P1_7/SEG15 P2_0/SEG16/KI0 VL4 CL2/P12_3 P2_4/SEG20/KI4 P2_5/SEG21/KI5 P2_6/SEG22/KI6 P2_7/SEG23/KI7 P3_0/SEG24/INT0 P3_1/SEG25/INT1 P3_2/SEG26/INT2 P3_3/SEG27/INT3 P3_5/SEG29/INT5 P3_7/SEG31/INT7/ADTRG/TRCTRG P4_0/SEG32/TXD1 P4_1/SEG33/RXD1 P4_2/SEG34/CLK1 P4_3/SEG35/TRCCLK/TRCTRG P4_4/SEG36/TRCIOA/TRCTRG P4_5/SEG37/TRCIOB P4_6/SEG38/TRCIOC/TRCIOB P4_7/SEG39/TRCIOD/TRCIOB P3_6/SEG30/INT6 P3_4/SEG28/INT4 P13_7/AN19/TRGCLKB CL1/P12_2 VL3 VL2 VL1 P13_4/AN16/TRGIOA P13_5/AN17/TRGCLKA P13_6/AN18/TRGIOB P10_4/(TRDIOA1/KI4) P10_3/(TRDIOD0/KI3) P10_2/(TRDIOC0/KI2) P2_1/SEG17/KI1 P2_2/SEG18/KI2 P2_3/SEG19/KI3 P0_3/SEG3/AN7 P0_2/SEG2/AN6 P0_1/SEG1/AN5 P0_0/SEG0/AN4 VCC/AVCC P12_0/XIN P12_1/XOUT VSS/AVSS MODE XCIN XCOUT VREF P10_6/(TRDIOC1/KI6) P11_0/SCL/SSCK/(CLK2/INT0) /IVREF1/LVCOUT1 P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2 P13_2/AN2/RXD0/LVCMP1 P13_3/AN3/CLK0/LVCMP2 P13_0/AN0/DA0/WKUP1 P13_1/AN1/DA1/TXD0/LVREF P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3 P11_4/TRAIO/(INT4/RXD0) P11_5/TRAO/(INT5) WKUP0 P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3 P10_5/(TRDIOB1/KI5) P10_7/(TRDIOD1/KI7) P10_0/(TRDIOA0/TRDCLK/KI0) P10_1/(TRDIOB0/KI1) R8C/L3AA Group R8C/L3AB Group RESET P11_7/TREO/(INT7/ADTRG) P11_6/TRBO/(INT6) P5_0/SEG40 P5_1/SEG41 P7_0/SEG52/COM7 P6_7/SEG51/TRDIOD1 P6_6/SEG50/TRDIOC1 P6_5/SEG49/TRDIOB1 P6_4/SEG48/TRDIOA1 P7_1/SEG53/COM6 P5_3/SEG43 P6_0/SEG44/TRDIOA0/TRDCLK P6_1/SEG45/TRDIOB0 P7_5/COM2 P7_7/COM0 P7_3/SEG55/COM4 P7_4/COM3 P7_2/SEG54/COM5 P7_6/COM1 P5_2/SEG42 P6_2/SEG46/TRDIOC0 P6_3/SEG47/TRDIOD0 PLQP0100KB-A (100P6Q-A) (top view) Notes: 1. The pin in parentheses can be assigned by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions.

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 22 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 1.17 Pin Assignment (Top View) of PRQP0100JD-B Package 1 3456789 1 0 1 1 1 2 1 32 100 6880 79 78 77 76 75 74 73 72 71 70 69 5667 66 65 64 63 62 61 60 59 58 57 55 54 53 52 51 15 16 17 18 19 20 21 22 23 24 2514 26 27 28 29 30 R8C/L3AA Group R8C/L3AB Group PRQP0100JD-B (100P6F-A) (top view) VCC/AVCC P12_0/XIN P12_1/XOUT VSS/AVSS MODE XCIN XCOUT VREF P10_6/(TRDIOC1/KI6) P11_0/SCL/SSCK/(CLK2/INT0) /IVREF1/LVCOUT1 P13_2/AN2/RXD0/LVCMP1 P13_3/AN3/CLK0/LVCMP2 P13_0/AN0/DA0/WKUP1 P13_1/AN1/DA1/TXD0/LVREF P11_2/SDA/SSO/(RXD2/SCL2/TXD2/SDA2/INT2)/IVREF3 P11_4/TRAIO/(INT4/RXD0) P11_5/TRAO/(INT5) WKUP0 P11_3/SCS/(CTS2/RTS2/INT3)/IVCMP3 P10_5/(TRDIOB1/KI5) P10_7/(TRDIOD1/KI7) RESET P11_7/TREO/(INT7/ADTRG) P11_6/TRBO/(INT6) P10_4/(TRDIOA1/KI4) P10_3/(TRDIOD0/KI3) P10_2/(TRDIOC0/KI2) P1_7/SEG15 P2_0/SEG16/KI0 P2_4/SEG20/KI4 P2_5/SEG21/KI5 P2_6/SEG22/KI6 P2_7/SEG23/KI7 P3_0/SEG24/INT0 P3_1/SEG25/INT1 P3_2/SEG26/INT2 P3_3/SEG27/INT3 P3_5/SEG29/INT5 P3_7/SEG31/INT7/ADTRG/TRCTRG P4_0/SEG32/TXD1 P4_1/SEG33/RXD1 P4_2/SEG34/CLK1 P4_3/SEG35/TRCCLK/TRCTRG P4_4/SEG36/TRCIOA/TRCTRG P4_5/SEG37/TRCIOB P4_6/SEG38/TRCIOC/TRCIOB P4_7/SEG39/TRCIOD/TRCIOB P3_6/SEG30/INT6 P3_4/SEG28/INT4 P2_1/SEG17/KI1 P2_2/SEG18/KI2 P2_3/SEG19/KI3 P1_4/SEG12 P1_5/SEG13 P1_6/SEG14 P0_4/SEG4/AN8 P0_5/SEG5/AN9 P0_6/SEG6/AN10 P0_7/SEG7/AN11 P1_0/SEG8/AN12 P1_1/SEG9/AN13 VL4 CL2/P12_3 P13_7/AN19/TRGCLKB CL1/P12_2 VL3 VL2 VL1 P13_6/AN18/TRGIOB P0_3/SEG3/AN7 P0_2/SEG2/AN6 P0_1/SEG1/AN5 P0_0/SEG0/AN4 P7_0/SEG52/COM7 P6_7/SEG51/TRDIOD1 P6_6/SEG50/TRDIOC1 P6_5/SEG49/TRDIOB1 P6_4/SEG48/TRDIOA1 P7_1/SEG53/COM6 P5_3/SEG43 P6_0/SEG44/TRDIOA0/TRDCLK P6_1/SEG45/TRDIOB0 P7_5/COM2 P7_7/COM0 P7_3/SEG55/COM4 P7_4/COM3 P7_2/SEG54/COM5 P7_6/COM1 P5_2/SEG42 P6_2/SEG46/TRDIOC0 P6_3/SEG47/TRDIOD0 Notes: 1. The pin in parentheses can be assigned by a program. 2. Confirm the pin 1 position on the package by referring to the package dimensions. P10_1/(TRDIOB0/KI1) P10_0/(TRDIOA0/TRDCLK/KI0) P5_0/SEG40 P5_1/SEG41 P1_2/SEG10/AN14 P1_3/SEG11/AN15 P13_4/AN16/TRGIOA P13_5/AN17/TRGCLKA P11_1/SSI/(RXD2/SCL2/TXD2/SDA2/INT1)/IVCMP1/LVCOUT2

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 23 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Notes: 1. The pin in parentheses can be assigned by a program. 2. The number in brackets indicates the pin number for the 100P6F package. 3. 0000The WKUP1 pin is not available in the R8C/L35A and R8C/L35B Groups. Table 1.15 Pin Name Information by Pin Number (1) Pin Number Control Pin Port I/O Pin Functions for Peripheral Modules L3AA L3AB (Note 2) L38A L38B L36A L36B L35A L35B Interrupt Timer Serial Interface SSU I2C bus A/D Converter, D/A Converter, Comparators A, B, Voltage Detection Circuit LCD drive control circuit 1 [3] 80 61 51 P13_3 CLK0 AN3/LVCMP2 2 [4] 1 62 52 P13_2 RXD0 AN2/LVCMP1 3 [5] 2 63 1 P13_1 TXD0 AN1/DA1/LVREF 4 [6] 3 64 2 WKUP1(3) P13_0 AN0/DA0 5 [ 7 ] 413 WKUP0 6 [ 8 ] 524 V R E F 7 [ 9 ] 635 M O D E 8 [ 1 0 ]746 XCIN 9 [ 1 1 ]857X C O U T 10 [12] 9 6 8 RESET 11 [13] 10 7 9 XOUT P12_1 12 [14] 11 8 10 VSS/ AVSS 13 [15] 12 9 11 XIN P12_0 14 [16] 13 10 12 VCC/ AVCC 15 [17] 14 11 P11_7 (INT7) TREO (ADTRG) 16 [18] 15 12 P11_6 (INT6) TRBO 17 [19] 16 13 P11_5 (INT5) TRAO 18 [20] 17 14 13 P11_4 (INT4) TRAIO (RXD0) 19 [21] 18 15 14 P11_3 (INT3)( C T S 2 /RTS2)S C S IVCMP3 20 [22] 19 16 15 P11_2 (INT2) (RXD2/SCL2/ TXD2/SDA2) SSO SDA IVREF3 21 [23] 20 17 16 P11_1 (INT1) (RXD2/SCL2/ TXD2/SDA2) SSI IVCMP1/LVCOUT2 22 [24] 21 18 17 P11_0 (INT0) (CLK2) SSCK SCL IVREF1/LVCOUT1 23 [25] P10_7 (KI7) (TRDIOD1) 24 [26] P10_6 (KI6) (TRDIOC1) 25 [27] P10_5 (KI5) (TRDIOB1) 26 [28] P10_4 (KI4) (TRDIOA1) 27 [29] P10_3 (KI3) (TRDIOD0) 28 [30] P10_2 (KI2) (TRDIOC0) 29 [31] P10_1 (KI1) (TRDIOB0) (TRDIOA0/ TRDCLK) 31 [33] 22 19 18 P7_7 COM0 32 [34] 23 20 19 P7_6 COM1 33 [35] 24 21 20 P7_5 COM2 34 [36] 25 22 21 P7_4 COM3 35 [37] 26 23 P7_3 SEG55/ COM4 36 [38] 27 24 P7_2 SEG54/ COM5 37 [39] 28 25 P7_1 SEG53/ COM6 38 [40] 29 26 P7_0 SEG52/ COM7 39 [41] 30 P6_7 TRDIOD1 SEG51

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 24 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Notes: 1. The pin in parentheses can be assigned by a program. 2. The number in brackets indicates the pin number for the 100P6F package. Table 1.16 Pin Name Information by Pin Number (2) Pin Number Control Pin Port I/O Pin Functions for Peripheral Modules L3AA L3AB (Note 2) L38A L38B L36A L36B L35A L35B Interrupt Timer Serial Interface SSU I2C bus A/D Converter, D/A Converter, Comparators A, B, Voltage Detection Circuit LCD drive control circuit 40 [42] 31 P6_6 TRDIOC1 SEG50 41 [43] 32 P6_5 TRDIOB1 SEG49 42 [44] 33 P6_4 TRDIOA1 SEG48 43 [45] 34 P6_3 TRDIOD0 SEG47 44 [46] 35 P6_2 TRDIOC0 SEG46 45 [47] 36 P6_1 TRDIOB0 SEG45 46 [48] 37 P6_0 TRDIOA0/ TRDCLK SEG44 47 [49] P5_3 SEG43 48 [50] P5_2 SEG42 49 [51] P5_1 SEG41 50 [52] P5_0 SEG40 51 [53] 38 27 22 P4_7 TRCIOD/ TRCIOB SEG39 52 [54] 39 28 23 P4_6 TRCIOC/ TRCIOB SEG38 53 [55] 40 29 24 P4_5 TRCIOB SEG37 54 [56] 41 30 25 P4_4 TRCIOA/ TRCTRG SEG36 55 [57] 42 31 26 P4_3 TRCCLK/ TRCTRG SEG35 56 [58] 43 32 27 P4_2 CLK1 SEG34 57 [59] 44 33 28 P4_1 RXD1 SEG33 58 [60] 45 34 29 P4_0 TXD1 SEG32 59 [61] 46 35 P3_7 INT7 TRCTRG ADTRG SEG31 60 [62] 47 36 P3_6 INT6 SEG30 61 [63] 48 37 P3_5 INT5 SEG29 62 [64] 49 38 P3_4 INT4 SEG28 63 [65] 50 39 30 P3_3 INT3 SEG27 64 [66] 51 40 31 P3_2 INT2 SEG26 65 [67] 52 41 32 P3_1 INT1 SEG25 66 [68] 53 42 33 P3_0 INT0 SEG24 67 [69] 54 43 34 P2_7 KI7 SEG23 68 [70] 55 44 35 P2_6 KI6 SEG22 69 [71] 56 45 36 P2_5 KI5 SEG21 70 [72] 57 46 37 P2_4 KI4 SEG20 71 [73] 58 P2_3 KI3 SEG19 72 [74] 59 P2_2 KI2 SEG18 73 [75] 60 P2_1 KI1 SEG17 74 [76] 61 P2_0 KI0 SEG16 75 [77] P1_7 SEG15 76 [78] P1_6 SEG14 77 [79] P1_5 SEG13 78 [80] P1_4 SEG12 79 [81] 62 P1_3 AN15 SEG11 80 [82] 63 P1_2 AN14 SEG10 81 [83] 64 P1_1 AN13 SEG9 82 [84] 65 P1_0 AN12 SEG8 83 [85] 66 47 38 P0_7 AN11 SEG7 84 [86] 67 48 39 P0_6 AN10 SEG6 85 [87] 68 49 40 P0_5 AN9 SEG5

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 25 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Notes: 1. The pin in parentheses can be assigned by a program. 2. The number in brackets indicates the pin number for the 100P6F package. Table 1.17 Pin Name Information by Pin Number (3) Pin Number Control Pin Port I/O Pin Functions for Peripheral Modules L3AA L3AB (Note 2) L38A L38B L36A L36B L35A L35B Interrupt Timer Serial Interface SSU I2C bus A/D Converter, D/A Converter, Comparators A, B, Voltage Detection Circuit LCD drive control circuit 86 [88] 69 50 41 P0_4 AN8 SEG4 87 [89] 70 51 42 P0_3 AN7 SEG3 88 [90] 71 52 43 P0_2 AN6 SEG2 89 [91] 72 53 44 P0_1 AN5 SEG1 90 [92] 73 54 45 P0_0 AN4 SEG0 91 [93] 74 55 46 VL1 92 [94] 75 56 47 VL2 93 [95] 76 57 VL3 94 [96] 77 58 48 P12_3 CL2 95 [97] 78 59 49 P12_2 CL1 96 [98] 79 60 50 VL4 97 [99] P13_7 TRGCLKB AN19 98 [100] P13_6 TRGIOB AN18 99 [1] P13_5 TRGCLKA AN17 100 [2] P13_4 TRGIOA AN16

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 26 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

1.5 Pin Functions

Tables 1.18 and 1.19 list pin functions. I: Input O: Output I/O: Input and output Note: 1. Contact the oscillator manufacturer for oscillation characteristics. Table 1.18 Pin Functions (1) Item Pin Name I/O Type Description Power supply input VCC, VSS − Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Analog power supply input AVCC, AVSS − Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Reset input RESET I Driving this pin low resets the MCU. MODE MODE I Connect this pin to VCC via a resistor. Power-off mode exit input WKUP0 I This pin is provided for input to exit the mode used in power-off mode. Connect to VSS when not using power-off mode. WKUP1 I This pin is provided for input to exit the mode used in power-off mode. XIN clock input XIN I These pins are provid ed for XIN clock generation circuit I/O. Connect a ceramic oscillator or a crystal oscillator between pins XIN and XOUT. (1) To use an external clock, input it to the XIN pin and leave the XOUT pin open. XIN clock output XOUT O XCIN clock input XCIN I These pins are pr ovided for XCIN clock generation circuit I/O. Connect a crystal oscillator between pins XCIN and XCOUT. (1) To use an external clock, input it to the XCIN pin and leave the XCOUT pin open. XCIN clock output XCOUT O INT interrupt input INT0 to INT7 II N T interrupt input pins. Key input interrupt KI0 to KI7 I Key input interrupt input pins Timer RA TRAIO I/O Timer RA I/O pin TRAO O Timer RA output pin Timer RB TRBO O Timer RB output pin Timer RC TRCCLK I External clock input pin TRCTRG I External trigger input pin TRCIOA, TRCIOB, TRCIOC, TRCIOD I/O Timer RC I/O pins Timer RD TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 I/O Timer RD I/O pins TRDCLK I External clock input pin Timer RE TREO O Divided clock output pin Timer RG TRGCLKA, TRGCLKB I Timer RG input pins TRGIOA, TRGIOB I/O Timer RG I/O pins Serial interface CLK0, CLK1, CLK2 I/O Transfer clock I/O pins RXD0, RXD1, RXD2 I Serial data input pins TXD0, TXD1, TXD2 O Serial data output pins CTS2 I Transmission control input pin RTS2 O Reception control output pin SCL2 I/O I2C mode clock I/O pin SDA2 I/O I2C mode data I/O pin

1. Overview REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 27 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group I: Input O: Output I/O: Input and output Note: 1. Contact the oscillator manufacturer for oscillation characteristics. Table 1.19 Pin Functions (2) Item Pin Name I/O Type Description I2C bus SCL I/O Clock I/O pin SDA I/O Data I/O pin SSU SSI I/O Data I/O pin SCS I/O Chip-select signal I/O pin SSCK I/O Clock I/O pin SSO I/O Data I/O pin Reference voltage input VREF I Reference voltage input pin for the A/D converter and the D/A converter A/D converter AN0 to AN11 I A/D converter analog input pins ADTRG I AD external trigger input pin D/A converter DA0, DA1 O D/A converter output pins Comparator A LVCMP1, LVCMP2 I Comparator A analog voltage input pins LVREF I Comparator A reference voltage input pin LVCOUT1, LVCOUT2 O Comparator A output pins Comparator B IVCMP1, IVCMP3 I Comparator B analog voltage input pins IVREF1, IVREF3 I Comparator B reference voltage input pins Voltage detection circuit LVCMP2 I Detection target voltage in put pin for voltage detection 2 I/O ports P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0, P5_3, P6_0 to P6_7 P7_0 to P7_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_3, P13_0 to P13_7 I/O CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. Ports P10_0 to P10_7 and P11_0 to P11_7 can be used as LED drive ports. Segment output SEG0 to SEG55 O LCD segment output pins Common output COM0 to COM7 O LCD common output pins Voltage multiplier capacity connect pins CL1, CL2 O Connect pins for the LCD control voltage multiplier LCD power supply VL1 I/O Apply the voltage: 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VL4. VL1 can be used as the reference potential input or output pin when setting the voltage multiplier. VL2 to VL4 I

1. Central Processing Unit (CPU) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 29 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

2.1 Data Registers (R 0, R1, R2, and R3)

R0 is a 16-bit register for transfer, ar ithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0.

2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addr essing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32- bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the starting address of an interrupt vector table.

2.5 Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.

2.6 User Stack Pointer (USP) a nd Interrupt Stack Pointer (ISP)

The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP.

2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8 Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.

2.8.1 Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.

2.8.2 Debug Flag (D)

The D flag is for debugging only. Set it to 0.

2.8.3 Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.

2.8.4 Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.

2.8.5 Register Bank Select Flag (B)

Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.

2.8.6 Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.

1. Central Processing Unit (CPU) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 30 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

2.8.7 Interrupt Enable Flag (I)

The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt requ est is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

1. Memory REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 31 of 809 R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Under development Preliminary specification Specifications in this manual are tentative and subject to change. 3. Memory Figure 3.1 is a Memory Map of each group. Each gr oup has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program RO M) is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is al located addresses 0FFDCh to 0FFFFh. The starting ad dress of each interrupt routine is stored here. The internal ROM (data flash) is allocated addresses 03000h to 03FFFh. The internal RAM is allocated higher addresses, beginn ing with address 00400h. For example, a 6-Kbyte internal RAM area is allocated addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) ar e allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral function control registers are allocated here. All unalloca ted spaces within the SFRs are reserved and cannot be accessed by users. Figure 3.1 Memory Map 0FFFFh 0FFDCh Notes: 1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte). 2. Blank spaces are reserved. No access is allowed.FFFFFh 0FFFFh 0YYYYh 0XXXXh 00400h 002FFh 00000h Internal ROM (program ROM) Internal RAM SFR (Refer to 4. Special Function Registers (SFRs)) 02FFFh 02C00h SFR (Refer to 4. Special Function Registers (SFRs)) ZZZZZh Internal ROM (program ROM) 03FFFh 03000h Internal ROM (data flash) (1) 0FFD8h Reserved area Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer, oscillation stop detection, voltage monitor Address break (Reserved) Reset Part Number Internal ROM Internal RAM Capacity Address 0YYYYh Capacity Address 0XXXXh Address ZZZZZh

48 Kbytes 04000h − 6 Kbytes 01BFFh

64 Kbytes 04000h 13FFFh 8 Kbytes 023FFh

96 Kbytes 04000h 1BFFFh 10 Kbytes 02BFFh

128 Kbytes 04000h 23FFFh 10 Kbytes 02BFFh

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 32 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 4. Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.16 list SFR information. Table 4.1 SFR Information (1) (1) X: Undefined Notes: 1. Blank spaces are reserved . No access is allowed. 2. The CWR bit in the RSTFR register is set to 0 after power-on, voltage monitor 0 reset, or exit from power-off mode. Software reset, watchdog timer reset, or oscillation stop detection reset does not affect this bit. 3. The CSPROINI bit in the OFS register is set to 0. 4. The LVDAS bit in the OFS register is set to 1. 5. The LVDAS bit in the OFS register is set to 0. Address Register Symbol After Reset 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 PM0 00h 0005h Processor Mode Register 1 PM1 00h 0006h System Clock Control Register 0 CM0 00100000b 0007h System Clock Control Register 1 CM1 00100000b 0008h Module Standby Control Register MSTCR 00h 0009h System Clock Control Register 3 CM3 00h 000Ah Protect Register PRCR 00h 000Bh Reset Source Determination Register RSTFR XXXX00XXb (2) 000Ch Oscillation Stop Detection Register OCD 00000100b 000Dh Watchdog Timer Reset Register WDTR XXh 000Eh Watchdog Timer Start Register WDTS XXh 000Fh Watchdog Timer Control Register WDTC 00111111b 0010h 0011h 0012h 0013h 0014h 0015h High-Speed On-Chip Oscillator Control Register 7 FRA7 When shipping 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch Count Source Protection Mode Register CSPR 00h 10000000b (3) 001Dh 001Eh 001Fh 0020h Power-Off Mode Control Register 0 POMCR0 X0000000b 0021h 0022h 0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h 0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping 0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h 0026h On-Chip Reference Voltage Control Register OCVREFCR 00h 0027h 0028h 0029h High-Speed On-Chip Oscillator Control Register 4 FRA4 When Shipping 002Ah High-Speed On-Chip Oscillator Control Register 5 FRA5 When Shipping 002Bh High-Speed On-Chip Oscillator Control Register 6 FRA6 When Shipping 002Ch 002Dh 002Eh 002Fh High-Speed On-Chip Oscillator Control Register 3 FRA3 When shipping 0030h Voltage Monitor Circuit/Comparator A Control Register CMPA 00h 0031h Voltage Monitor Circuit Edge Select Register VCAC 00h 0032h 0033h Voltage Detect Register 1 VCA1 00001000b 0034h Voltage Detect Register 2 VCA2 00h (4) 00100000b (5) 0035h 0036h Voltage Detection 1 Level Select Register VD1LS 00000111b 0037h 0038h Voltage Monitor 0 Circuit Control Register VW0C 1100X010b (4) 1100X011b (5) 0039h Voltage Monitor 1 Circuit Control Register VW1C 10001010b

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 33 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.2 SFR Information (2) (1) X: Undefined Notes: 1. Blank spaces are reserved . No access is allowed. 2. Selectable by the IICSEL bit in the SSUIICSR register. Address Register Symbol After Reset 003Ah Voltage Monitor 2 Circuit Control Register VW2C 10000010b 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h Flash Memory Ready Interrupt Control Register FMRDYIC XXXXX000b 0042h 0043h INT7 Interrupt Control Register INT7IC XX00X000b 0044h INT6 Interrupt Control Register INT6IC XX00X000b 0045h INT5 Interrupt Control Register INT5IC XX00X000b 0046h INT4 Interrupt Control Register INT4IC XX00X000b 0047h Timer RC Interrupt Control Register TRCIC XXXXX000b 0048h Timer RD0 Interrupt Control Register TRD0IC XXXXX000b 0049h Timer RD1 Interrupt Control Register TRD1IC XXXXX000b 004Ah Timer RE Interrupt Control Register TREIC XXXXX000b 004Bh UART2 Transmit Interrupt Control Register S2TIC XXXXX000b 004Ch UART2 Receive Interrupt Control Register S2RIC XXXXX000b 004Dh Key Input Interrupt Control Register KUPIC XXXXX000b 004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b 004Fh SSU Interrupt Control Register / IIC bus Interrupt Control Register (2) SSUIC/IICIC XXXXX000b 0050h 0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b 0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b 0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b 0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b 0055h INT2 Interrupt Control Register INT2IC XX00X000b 0056h Timer RA Interrupt Control Register TRAIC XXXXX000b 0057h 0058h Timer RB Interrupt Control Register TRBIC XXXXX000b 0059h INT1 Interrupt Control Register INT1IC XX00X000b 005Ah INT3 Interrupt Control Register INT3IC XX00X000b 005Bh 005Ch 005Dh INT0 Interrupt Control Register INT0IC XX00X000b 005Eh UART2 Bus Collision Detection Interrupt Control Register U2BCNIC XXXXX000b 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh Timer RG Interrupt Control Register TRGIC XXXXX000b 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h Voltage monitor 1 / Comparator A1 Interrupt Control Register VCMP1IC XXXXX000b 0073h Voltage monitor 2 / Comparator A2 Interrupt Control Register VCMP2IC XXXXX000b 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 34 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.3 SFR Information (3) (1) X: Undefined Note: 1. Blank spaces are reserved . No access is allowed. Address Register Symbol After Reset 0080h DTC Activation Control Register DTCTL 00h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 DTCEN0 00h 0089h DTC Activation Enable Register 1 DTCEN1 00h 008Ah DTC Activation Enable Register 2 DTCEN2 00h 008Bh DTC Activation Enable Register 3 DTCEN3 00h 008Ch DTC Activation Enable Register 4 DTCEN4 00h 008Dh DTC Activation Enable Register 5 DTCEN5 00h 008Eh DTC Activation Enable Register 6 DTCEN6 00h 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register U0MR 00h 00A1h UART0 Bit Rate Register U0BRG XXh 00A2h UART0 Transmit Buffer Register U0TB XXh 00A3h XXh 00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b 00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b 00A6h UART0 Receive Buffer Register U0RB XXh 00A7h XXh 00A8h UART2 Transmit/Receive Mode Register U2MR 00h 00A9h UART2 Bit Rate Register U2BRG XXh 00AAh UART2 Transmit Buffer Register U2TB XXh 00ABh XXh 00ACh UART2 Transmit/Receive Control Register 0 U2C0 00001000b 00ADh UART2 Transmit/Receive Control Register 1 U2C1 00000010b 00AEh UART2 Receive Buffer Register U2RB XXh 00AFh XXh 00B0h UART2 Digital Filter Function Select Register URXDF 00h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh UART2 Special Mode Register 5 U2SMR5 00h 00BCh UART2 Special Mode Register 4 U2SMR4 00h 00BDh UART2 Special Mode Register 3 U2SMR3 000X0X0Xb 00BEh UART2 Special Mode Register 2 U2SMR2 X0000000b 00BFh UART2 Special Mode Register U2SMR X0000000b

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 35 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.4 SFR Information (4) (1) X: Undefined Note: 1. Blank spaces are reserved . No access is allowed. Address Register Symbol After Reset 00C0h A/D Register 0 AD0 XXh 000000XXb00C1h 00C2h A/D Register 1 AD1 XXh 00C3h 000000XXb 00C4h A/D Register 2 AD2 XXh 00C5h 000000XXb 00C6h A/D Register 3 AD3 XXh 00C7h 000000XXb 00C8h A/D Register 4 AD4 XXh 00C9h 000000XXb 00CAh A/D Register 5 AD5 XXh 00CBh 000000XXb 00CCh A/D Register 6 AD6 XXh 00CDh 000000XXb 00CEh A/D Register 7 AD7 XXh 00CFh 000000XXb 00D0h 00D1h 00D2h 00D3h 00D4h A/D Mode Register ADMOD 00h 00D5h A/D Input Select Register ADINSEL 11000000b 00D6h A/D Control Register 0 ADCON0 00h 00D7h A/D Control Register 1 ADCON1 00h 00D8h D/A 0 Register DA0 00h 00D9h D/A 1 Register DA1 00h 00DAh 00DBh 00DCh D/A Control Register DACON 00h 00DDh 00DEh 00DFh 00E0h Port P0 Register P0 XXh 00E1h Port P1 Register P1 XXh 00E2h Port P0 Direction Register PD0 00h 00E3h Port P1 Direction Register PD1 00h 00E4h Port P2 Register P2 XXh 00E5h Port P3 Register P3 XXh 00E6h Port P2 Direction Register PD2 00h 00E7h Port P3 Direction Register PD3 00h 00E8h Port P4 Register P4 XXh 00E9h Port P5 Register P5 XXh 00EAh Port P4 Direction Register PD4 00h 00EBh Port P5 Direction Register PD5 00h 00ECh Port P6 Register P6 XXh 00EDh Port P7 Register P7 XXh 00EEh Port P6 Direction Register PD6 00h 00EFh Port P7 Direction Register PD7 00h 00F0h 00F1h 00F2h 00F3h 00F4h Port P10 Register P10 XXh 00F5h Port P11 Register P11 XXh 00F6h Port P10 Direction Register PD10 00h 00F7h Port P11 Direction Register PD11 00h 00F8h Port P12 Register P12 XXh 00F9h Port P13 Register P13 XXh 00FAh Port P12 Direction Register PD12 00h 00FBh Port P13 Direction Register PD13 00h 00FCh 00FDh 00FEh 00FFh

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 36 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.5 SFR Information (5) (1) X: Undefined Note: 1. Blank spaces are reserved . No access is allowed. Address Register Symbol After Reset 0100h Timer RA Control Register TRACR 00h 0101h Timer RA I/O Control Register TRAIOC 00h 0102h Timer RA Mode Register TRAMR 00h 0103h Timer RA Prescaler Register TRAPRE FFh 0104h Timer RA Register TRA FFh 0105h LIN Control Register 2 LINCR2 00h 0106h LIN Control Register LINCR 00h 0107h LIN Status Register LINST 00h 0108h Timer RB Control Register TRBCR 00h 0109h Timer RB One-Shot Control Register TRBOCR 00h 010Ah Timer RB I/O Control Register TRBIOC 00h 010Bh Timer RB Mode Register TRBMR 00h 010Ch Timer RB Prescaler Register TRBPRE FFh 010Dh Timer RB Secondary Register TRBSC FFh 010Eh Timer RB Primary Register TRBPR FFh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h Timer RE Second Data Register / Timer RE Counter Data Register TRESEC XXh 0119h Timer RE Minute Data Register / Timer RE Compare Data Register TREMIN XXh 011Ah Timer RE Hour Data Register TREHR XXh 011Bh Timer RE Day of Week Data Register TREWK XXh 011Ch Timer RE Control Register 1 TRECR1 XXXXX0XXb 011Dh Timer RE Control Register 2 TRECR2 XXh 011Eh Timer RE Count Source Select Register TRECSR 00001000b 011Fh 0120h Timer RC Mode Register TRCMR 01001000b 0121h Timer RC Control Register 1 TRCCR1 00h 0122h Timer RC Interrupt Enable Register TRCIER 01110000b 0123h Timer RC Status Register TRCSR 01110000b 0124h Timer RC I/O Control Register 0 TRCIOR0 10001000b 0125h Timer RC I/O Control Register 1 TRCIOR1 10001000b 0126h Timer RC Counter TRC 00h 0127h 00h 0128h Timer RC General Register A TRCGRA FFh 0129h FFh 012Ah Timer RC General Register B TRCGRB FFh 012Bh FFh 012Ch Timer RC General Register C TRCGRC FFh 012Dh FFh 012Eh Timer RC General Register D TRCGRD FFh 012Fh FFh 0130h Timer RC Control Register 2 TRCCR2 00011000b 0131h Timer RC Digital Filter Function Select Register TRCDF 00h 0132h Timer RC Output Master Enable Register TRCOER 0 1111111b 0133h Timer RC Trigger Control Register TRCADCR 00h 0134h 0135h Timer RD Control Expansion Register TRDECR 00h 0136h Timer RD Trigger Control Register TRDADCR 00h 0137h Timer RD Start Register TRDSTR 11111100b 0138h Timer RD Mode Register TRDMR 00001110b 0139h Timer RD PWM Mode Register TRDPMR 10001000b 013Ah Timer RD Function Control Register TRDFCR 10000000b 013Bh Timer RD Output Master Enable Register 1 TRDOER1 FFh 013Ch Timer RD Output Master Enable Register 2 TRDOER2 0 1111111b 013Dh Timer RD Output Control Register TRDOCR 00h 013Eh Timer RD Digital Filter Function Select Register 0 TRDDF0 00h 013Fh Timer RD Digital Filter Function Select Register 1 TRDDF1 00h

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 37 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.6 SFR Information (6) (1) X: Undefined Note: 1. Blank spaces are reserved . No access is allowed. Address Register Symbol After Reset 0140h Timer RD Control Register 0 TRDCR0 00h 0141h Timer RD I/O Control Register A0 TRDIORA0 10001000b 0142h Timer RD I/O Control Register C0 TRDIORC0 10001000b 0143h Timer RD Status Register 0 TRDSR0 11100000b 0144h Timer RD Interrupt Enable Register 0 TRDIER0 11100000b 0145h Timer RD PWM Mode Output Level Control Register 0 TRDPOCR0 11111000b 0146h Timer RD Counter 0 TRD0 00h 0147h 00h 0148h Timer RD General Register A0 TRDGRA0 FFh 0149h FFh 014Ah Timer RD General Register B0 TRDGRB0 FFh 014Bh FFh 014Ch Timer RD General Register C0 TRDGRC0 FFh 014Dh FFh 014Eh Timer RD General Register D0 TRDGRD0 FFh 014Fh FFh 0150h Timer RD Control Register 1 TRDCR1 00h 0151h Timer RD I/O Control Register A1 TRDIORA1 10001000b 0152h Timer RD I/O Control Register C1 TRDIORC1 10001000b 0153h Timer RD Status Register 1 TRDSR1 11000000b 0154h Timer RD Interrupt Enable Register 1 TRDIER1 11100000b 0155h Timer RD PWM Mode Output Level Control Register 1 TRDPOCR1 11111000b 0156h Timer RD Counter 1 TRD1 00h 0157h 00h 0158h Timer RD General Register A1 TRDGRA1 FFh 0159h FFh 015Ah Timer RD General Register B1 TRDGRB1 FFh 015Bh FFh 015Ch Timer RD General Register C1 TRDGRC1 FFh 015Dh FFh 015Eh Timer RD General Register D1 TRDGRD1 FFh 015Fh FFh 0160h UART1 Transmit/Receive Mode Register U1MR 00h 0161h UART1 Bit Rate Register U1BRG XXh 0162h UART1 Transmit Buffer Register U1TB XXh 0163h XXh 0164h UART1 Transmit/Receive Control Register 0 U1C0 00001000b 0165h UART1 Transmit/Receive Control Register 1 U1C1 00000010b 0166h UART1 Receive Buffer Register U1RB XXh 0167h XXh 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h Timer RG Mode Register TRGMR 01000000b 0171h Timer RG Count Control Register TRGCNTC 00h 0172h Timer RG Control Register TRGCR 10000000b 0173h Timer RG Interrupt Enable Register TRGIER 11110000b 0174h Timer RG Status Register TRGSR 11100000b 0175h Timer RG I/O Control Register TRGIOR 00h 0176h Timer RG Counter TRG 00h 0177h 00h 0178h Timer RG General Register A TRGGRA FFh 0179h FFh 017Ah Timer RG General Register B TRGGRB FFh 017Bh FFh 017Ch Timer RG General Register C TRGGRC FFh 017Dh FFh 017Eh Timer RG General Register D TRGGRD FFh 017Fh FFh

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 38 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.7 SFR Information (7) (1) X: Undefined Notes: 1. Blank spaces are reserved . No access is allowed. 2. Selectable by the IICSEL bit in the SSUIICSR register. Address Register Symbol After Reset 0180h Timer RA Pin Select Register TRASR 00h 0181h Timer RB/RC Pin Select Register TRBRCSR 00h 0182h Timer RC Pin Select Register 0 TRCPSR0 00h 0183h Timer RC Pin Select Register 1 TRCPSR1 00h 0184h Timer RD Pin Select Register 0 TRDPSR0 00h 0185h Timer RD Pin Select Register 1 TRDPSR1 00h 0186h 0187h Timer RG Pin Select Register TRGPSR 00h 0188h UART0 Pin Select Register U0SR 00h 0189h UART1 Pin Select Register U1SR 00h 018Ah UART2 Pin Select Register 0 U2SR0 00h 018Bh UART2 Pin Select Register 1 U2SR1 00h 018Ch SSU/IIC Pin Select Register SSUIICSR 00h 018Dh Key Input Pin Select Register KISR 00h 018Eh INT Interrupt Input Pin Select Register INTSR 00h 018Fh 0190h 0191h 0192h 0193h SS Bit Counter Register SSBR 1111 1000b 0194h SS Transmit Data Register L / IIC bus Transmit Data Register (2) SSTDR/ICDRT FFh 0195h SS Transmit Data Register H SSTDRH FFh 0196h SS Receive Data Register L / IIC bus Receive Data Register (2) SSRDR/ICDRR FFh 0197h SS Receive Data Register H (2) SSRDRH FFh 0198h SS Control Register H / IIC bus Control Register 1 (2) SSCRH/ICCR1 00h 0199h SS Control Register L / IIC bus Control Register 2 (2) SSCRL/ICCR2 0 1111101b 019Ah SS Mode Register / IIC bus Mode Register (2) SSMR/ICMR 00010000b/00011000b 019Bh SS Enable Register / IIC bus Interrupt Enable Register (2) SSER/ICIER 00h 019Ch SS Status Register / IIC bus Status Register (2) SSSR/ICSR 00h/0000X000b 019Dh SS Mode Register 2 / Slave Address Register (2) SSMR2/SAR 00h 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h Flash Memory Status Register FST 10000X00b 01B3h 01B4h Flash Memory Control Register 0 FMR0 00h 01B5h Flash Memory Control Register 1 FMR1 00h 01B6h Flash Memory Control Register 2 FMR2 00h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 39 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.8 SFR Information (8) (1) X: Undefined Note: 1. Blank spaces are reserved . No access is allowed. Address Register Symbol After Reset 01C0h Address Match Interrupt Register 0 RMAD0 XXh 01C1h XXh 01C2h 0000XXXXb 01C3h Address Match Interrupt Enable Register 0 AIER0 00h 01C4h Address Match Interrupt Register 1 RMAD1 XXh 01C5h XXh 01C6h 0000XXXXb 01C7h Address Match Interrupt Enable Register 1 AIER1 00h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h Port P0 Pull-Up Control Register P0PUR 00h 01E1h Port P1 Pull-Up Control Register P1PUR 00h 01E2h Port P2 Pull-Up Control Register P2PUR 00h 01E3h Port P3 Pull-Up Control Register P3PUR 00h 01E4h Port P4 Pull-Up Control Register P4PUR 00h 01E5h Port P5 Pull-Up Control Register P5PUR 00h 01E6h Port P6 Pull-Up Control Register P6PUR 00h 01E7h Port P7 Pull-Up Control Register P7PUR 00h 01E8h 01E9h 01EAh Port 10 Pull-Up Control Register P10PUR 00h 01EBh Port 11 Pull-Up Control Register P11PUR 00h 01ECh Port 12 Pull-Up Control Register P12PUR 00h 01EDh Port 13 Pull-Up Control Register P13PUR 00h 01EEh 01EFh 01F0h Port P10 Drive Capacity Control Register P10DRR 00h 01F1h Port P11 Drive Capacity Control Register P11DRR 00h 01F2h 01F3h 01F4h 01F5h Input Threshold Control Register 0 VLT0 00h 01F6h Input Threshold Control Register 1 VLT1 00h 01F7h Input Threshold Control Register 2 VLT2 00h 01F8h Comparator B Control Register 0 INTCMP 00h 01F9h 01FAh External Input Enable Register 0 INTEN 00h 01FBh External Input Enable Register 1 INTEN1 00h 01FCh INT Input Filter Select Register 0 INTF 00h 01FDh INT Input Filter Select Register 1 INTF1 00h 01FEh Key Input Enable Register 0 KIEN 00h 01FFh Key Input Enable Register 1 KIEN1 00h

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 40 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.9 SFR Information (9) (1) X: Undefined Note: 1. Blank spaces are reserved . No access is allowed. Address Register Symbol After Reset 0200h LCD Control Register LCR0 00h 0201h LCD Bias Control Register LCR1 00h 0202h LCD Display Control Register LCR2 00h 0203h LCD Clock Control Register LCR3 00h 0204h 0205h 0206h LCD Port Select Register 0 LSE0 00h 0207h LCD Port Select Register 1 LSE1 00h 0208h LCD Port Select Register 2 LSE2 00h 0209h LCD Port Select Register 3 LSE3 00h 020Ah LCD Port Select Register 4 LSE4 00h 020Bh LCD Port Select Register 5 LSE5 00h 020Ch LCD Port Select Register 6 LSE6 00h 020Dh LCD Port Select Register 7 LSE7 00h 020Eh 020Fh 0210h LCD Display Data Register LRA0L XXh 0211h LRA1L XXh 0212h LRA2L XXh 0213h LRA3L XXh 0214h LRA4L XXh 0215h LRA5L XXh 0216h LRA6L XXh 0217h LRA7L XXh 0218h LRA8L XXh 0219h LRA9L XXh 021Ah LRA10L XXh 021Bh LRA11L XXh 021Ch LRA12L XXh 021Dh LRA13L XXh 021Eh LRA14L XXh 021Fh LRA15L XXh 0220h LRA16L XXh 0221h LRA17L XXh 0222h LRA18L XXh 0223h LRA19L XXh 0224h LRA20L XXh 0225h LRA21L XXh 0226h LRA22L XXh 0227h LRA23L XXh 0228h LRA24L XXh 0229h LRA25L XXh 022Ah LRA26L XXh 022Bh LRA27L XXh 022Ch LRA28L XXh 022Dh LRA29L XXh 022Eh LRA30L XXh 022Fh LRA31L XXh 0230h LRA32L XXh 0231h LRA33L XXh 0232h LRA34L XXh 0233h LRA35L XXh 0234h LRA36L XXh 0235h LRA37L XXh 0236h LRA38L XXh 0237h LRA39L XXh 0238h LRA40L XXh 0239h LRA41L XXh 023Ah LRA42L XXh 023Bh LRA43L XXh 023Ch LRA44L XXh 023Dh LRA45L XXh 023Eh LRA46L XXh 023Fh LRA47L XXh

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 41 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.10 SFR Information (10) (1) X: Undefined Note: 1. Blank spaces are reserved . No access is allowed. Address Register Symbol After Reset 0240h LCD Display Data Register LRA48L XXh 0241h LRA49L XXh 0242h LRA50L XXh 0243h LRA51L XXh 0244h LRA52L XXh 0245h LRA53L XXh 0246h LRA54L XXh 0247h LRA55L XXh 0248h LRA56L XXh 0249h LRA57L XXh 024Ah LRA58L XXh 024Bh LRA59L XXh 024Ch LRA60L XXh 024Dh LRA61L XXh 024Eh LRA62L XXh 024Fh LRA63L XXh 0250h LRA64L XXh 0251h LRA65L XXh 0252h LRA66L XXh 0253h LRA67L XXh 0254h LRA68L XXh 0255h LRA69L XXh 0256h LRA70L XXh 0257h LRA71L XXh 0258h LRA72L XXh 0259h LRA73L XXh 025Ah LRA74L XXh 025Bh LRA75L XXh 025Ch LRA76L XXh 025Dh LRA77L XXh 025Eh LRA78L XXh 025Fh LRA79L XXh 0260h LRA80L XXh 0261h LRA81L XXh 0262h LRA82L XXh 0263h LRA83L XXh 0264h LRA84L XXh 0265h LRA85L XXh 0266h LRA86L XXh 0267h LRA87L XXh 0268h LRA88L XXh 0269h LRA89L XXh 026Ah LRA90L XXh 026Bh LRA91L XXh 026Ch LRA92L XXh 026Dh LRA93L XXh 026Eh LRA94L XXh 026Fh LRA95L XXh 0270h LCD Display Control Data Register LRA0H XXh 0271h LRA1H XXh 0272h LRA2H XXh 0273h LRA3H XXh 0274h LRA4H XXh 0275h LRA5H XXh 0276h LRA6H XXh 0277h LRA7H XXh 0278h LRA8H XXh 0279h LRA9H XXh 027Ah LRA10H XXh 027Bh LRA11H XXh 027Ch LRA12H XXh 027Dh LRA13H XXh 027Eh LRA14H XXh 027Fh LRA15H XXh

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 42 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.11 SFR Information (11) (1) X: Undefined Note: 1. Blank spaces are reserved . No access is allowed. Address Register Symbol After Reset 0280h LCD Display Control Data Register LRA16H XXh 0281h LRA17H XXh 0282h LRA18H XXh 0283h LRA19H XXh 0284h LRA20H XXh 0285h LRA21H XXh 0286h LRA22H XXh 0287h LRA23H XXh 0288h LRA24H XXh 0289h LRA25H XXh 028Ah LRA26H XXh 028Bh LRA27H XXh 028Ch LRA28H XXh 028Dh LRA29H XXh 028Eh LRA30H XXh 028Fh LRA31H XXh 0290h LRA32H XXh 0291h LRA33H XXh 0292h LRA34H XXh 0293h LRA35H XXh 0294h LRA36H XXh 0295h LRA37H XXh 0296h LRA38H XXh 0297h LRA39H XXh 0298h LRA40H XXh 0299h LRA41H XXh 029Ah LRA42H XXh 029Bh LRA43H XXh 029Ch LRA44H XXh 029Dh LRA45H XXh 029Eh LRA46H XXh 029Fh LRA47H XXh 02A0h LRA48H XXh 02A1h LRA49H XXh 02A2h LRA50H XXh 02A3h LRA51H XXh 02A4h LRA52H XXh 02A5h LRA53H XXh 02A6h LRA54H XXh 02A7h LRA55H XXh 02A8h LRA56H XXh 02A9h LRA57H XXh 02AAh LRA58H XXh 02ABh LRA59H XXh 02ACh LRA60H XXh 02ADh LRA61H XXh 02AEh LRA62H XXh 02AFh LRA63H XXh 02B0h LRA64H XXh 02B1h LRA65H XXh 02B2h LRA66H XXh 02B3h LRA67H XXh 02B4h LRA68H XXh 02B5h LRA69H XXh 02B6h LRA70H XXh 02B7h LRA71H XXh 02B8h LRA72H XXh 02B9h LRA73H XXh 02BAh LRA74H XXh 02BBh LRA75H XXh 02BCh LRA76H XXh 02BDh LRA77H XXh 02BEh LRA78H XXh 02BFh LRA79H XXh

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 43 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.12 SFR Information (12) (1) X: Undefined Note: 1. Blank spaces are reserved . No access is allowed. Address Register Symbol After Reset 02C0h LCD Display Control Data Register LRA80H XXh 02C1h LRA81H XXh 02C2h LRA82H XXh 02C3h LRA83H XXh 02C4h LRA84H XXh 02C5h LRA85H XXh 02C6h LRA86H XXh 02C7h LRA87H XXh 02C8h LRA88H XXh 02C9h LRA89H XXh 02CAh LRA90H XXh 02CBh LRA91H XXh 02CCh LRA92H XXh 02CDh LRA93H XXh 02CEh LRA94H XXh 02CFh LRA95H XXh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 44 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.13 SFR Information (13) (1) X: Undefined Note: 1. Blank spaces are reserved . No access is allowed. Address Register Symbol After Reset 2C00h DTC Transfer Vector Area XXh 2C01h DTC Transfer Vector Area XXh 2C02h DTC Transfer Vector Area XXh 2C03h DTC Transfer Vector Area XXh 2C04h DTC Transfer Vector Area XXh 2C05h DTC Transfer Vector Area XXh 2C06h DTC Transfer Vector Area XXh 2C07h DTC Transfer Vector Area XXh 2C08h DTC Transfer Vector Area XXh 2C09h DTC Transfer Vector Area XXh 2C0Ah DTC Transfer Vector Area XXh : DTC Transfer Vector Area XXh : DTC Transfer Vector Area XXh 2C3Ah DTC Transfer Vector Area XXh 2C3Bh DTC Transfer Vector Area XXh 2C3Ch DTC Transfer Vector Area XXh 2C3Dh DTC Transfer Vector Area XXh 2C3Eh DTC Transfer Vector Area XXh 2C3Fh DTC Transfer Vector Area XXh 2C40h DTC Control Data 0 DTCD0 XXh 2C41h XXh 2C42h XXh 2C43h XXh 2C44h XXh 2C45h XXh 2C46h XXh 2C47h XXh 2C48h DTC Control Data 1 DTCD1 XXh 2C49h XXh 2C4Ah XXh 2C4Bh XXh 2C4Ch XXh 2C4Dh XXh 2C4Eh XXh 2C4Fh XXh 2C50h DTC Control Data 2 DTCD2 XXh 2C51h XXh 2C52h XXh 2C53h XXh 2C54h XXh 2C55h XXh 2C56h XXh 2C57h XXh 2C58h DTC Control Data 3 DTCD3 XXh 2C59h XXh 2C5Ah XXh 2C5Bh XXh 2C5Ch XXh 2C5Dh XXh 2C5Eh XXh 2C5Fh XXh 2C60h DTC Control Data 4 DTCD4 XXh 2C61h XXh 2C62h XXh 2C63h XXh 2C64h XXh 2C65h XXh 2C66h XXh 2C67h XXh 2C68h DTC Control Data 5 DTCD5 XXh 2C69h XXh 2C6Ah XXh 2C6Bh XXh 2C6Ch XXh 2C6Dh XXh 2C6Eh XXh 2C6Fh XXh

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 45 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.14 SFR Information (14) (1) X: Undefined Note: 1. Blank spaces are reserved . No access is allowed. Address Register Symbol After Reset 2C70h DTC Control Data 6 DTCD6 XXh 2C71h XXh 2C72h XXh 2C73h XXh 2C74h XXh 2C75h XXh 2C76h XXh 2C77h XXh 2C78h DTC Control Data 7 DTCD7 XXh 2C79h XXh 2C7Ah XXh 2C7Bh XXh 2C7Ch XXh 2C7Dh XXh 2C7Eh XXh 2C7Fh XXh 2C80h DTC Control Data 8 DTCD8 XXh 2C81h XXh 2C82h XXh 2C83h XXh 2C84h XXh 2C85h XXh 2C86h XXh 2C87h XXh 2C88h DTC Control Data 9 DTCD9 XXh 2C89h XXh 2C8Ah XXh 2C8Bh XXh 2C8Ch XXh 2C8Dh XXh 2C8Eh XXh 2C8Fh XXh 2C90h DTC Control Data 10 DTCD10 XXh 2C91h XXh 2C92h XXh 2C93h XXh 2C94h XXh 2C95h XXh 2C96h XXh 2C97h XXh 2C98h DTC Control Data 11 DTCD11 XXh 2C99h XXh 2C9Ah XXh 2C9Bh XXh 2C9Ch XXh 2C9Dh XXh 2C9Eh XXh 2C9Fh XXh 2CA0h DTC Control Data 12 DTCD12 XXh 2CA1h XXh 2CA2h XXh 2CA3h XXh 2CA4h XXh 2CA5h XXh 2CA6h XXh 2CA7h XXh 2CA8h DTC Control Data 13 DTCD13 XXh 2CA9h XXh 2CAAh XXh 2CABh XXh 2CACh XXh 2CADh XXh 2CAEh XXh 2CAFh XXh

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 46 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.15 SFR Information (15) (1) X: Undefined Note: 1. Blank spaces are reserved . No access is allowed. Address Register Symbol After Reset 2CB0h DTC Control Data 14 DTCD14 XXh 2CB1h XXh 2CB2h XXh 2CB3h XXh 2CB4h XXh 2CB5h XXh 2CB6h XXh 2CB7h XXh 2CB8h DTC Control Data 15 DTCD15 XXh 2CB9h XXh 2CBAh XXh 2CBBh XXh 2CBCh XXh 2CBDh XXh 2CBEh XXh 2CBFh XXh 2CC0h DTC Control Data 16 DTCD16 XXh 2CC1h XXh 2CC2h XXh 2CC3h XXh 2CC4h XXh 2CC5h XXh 2CC6h XXh 2CC7h XXh 2CC8h DTC Control Data 17 DTCD17 XXh 2CC9h XXh 2CCAh XXh 2CCBh XXh 2CCCh XXh 2CCDh XXh 2CCEh XXh 2CCFh XXh 2CD0h DTC Control Data 18 DTCD18 XXh 2CD1h XXh 2CD2h XXh 2CD3h XXh 2CD4h XXh 2CD5h XXh 2CD6h XXh 2CD7h XXh 2CD8h DTC Control Data 19 DTCD19 XXh 2CD9h XXh 2CDAh XXh 2CDBh XXh 2CDCh XXh 2CDDh XXh 2CDEh XXh 2CDFh XXh 2CE0h DTC Control Data 20 DTCD20 XXh 2CE1h XXh 2CE2h XXh 2CE3h XXh 2CE4h XXh 2CE5h XXh 2CE6h XXh 2CE7h XXh 2CE8h DTC Control Data 21 DTCD21 XXh 2CE9h XXh 2CEAh XXh 2CEBh XXh 2CECh XXh 2CEDh XXh 2CEEh XXh 2CEFh XXh

1. Special Function Registers (SFRs) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 47 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 4.16 SFR Information (16) (1) X: Undefined Notes: 1. Blank spaces are reserved . No access is allowed. 2. This register cannot be changed by a program . Use a flash programmer to write to it. Address Register Symbol After Reset 2CF0h DTC Control Data 22 DTCD22 XXh 2CF1h XXh 2CF2h XXh 2CF3h XXh 2CF4h XXh 2CF5h XXh 2CF6h XXh 2CF7h XXh 2CF8h DTC Control Data 23 DTCD23 XXh 2CF9h XXh 2CFAh XXh 2CFBh XXh 2CFCh XXh 2CFDh XXh 2CFEh XXh 2CFFh XXh 2D00h 2D01h 0FFDBh Option Function Select Register 2 OFS2 (Note 2) 0FFFFh Option Function Select Register OFS (Note 2)

1. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 48 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5. Resets The following resets are available: hardware reset, power-on reset, voltage monitor 0 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources and Figure 5.1 shows the Reset Circuit Block Diagram. Figure 5.1 Reset Circuit Block Diagram Table 5.1 Reset Names and Sources Reset Name Source Hardware reset T he input voltage to the RESET pin is held low. Power-on reset VCC rises. Voltage monitor 0 reset VCC falls. (Monitor voltage: Vdet0) Watchdog timer reset Underflow of the watchdog timer Software reset Write 1 to the PM03 bit in the PM0 register. RESET Power-on reset circuit Voltage detection circuit Watchdog timer CPU Pins, CPU, and SFRs (1) VCC Hardware reset Power-on reset Voltage monitor 0 reset Watchdog timer reset Software reset Note: 1. The CWR bit in the RSTFR register is set to 0 (cold start-up) after power-on, voltage monitor 0 reset, or exit from power-off mode. This bit remains unchanged at a software reset, watchdog timer reset, or oscillation detection reset.

1. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 49 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 5.2 shows the Pin Status while RESET Pin Level is Lo w. Figure 5.2 shows the CPU Register Status after Reset and Figure 5.3 shows the Reset Sequence. Figure 5.2 CPU Register Status after Reset Table 5.2 Pin Status while RESET Pin Level is Low Pin Name Pin Status P0 to P13 High impedance WKUP0 High impedance XCIN, XCOUT Undefined VL1 to LVL4 High impedance b19 b0 Interrupt table register (INTB) Program counter (PC) User stack pointer (USP) Interrupt stack pointer (ISP) Static base register (SB) Content of addresses 0FFFEh to 0FFFCh Flag register (FLG) CIPL DZSBOIU b15 b0 b15 b0 b15 b0b8 b7 b15 b0 0000h 0000h 0000h 0000h 0000h 0000h 0000h Data register (R0) Data register (R1) Data register (R2) Data register (R3) Address register (A0) Address register (A1) Frame base register (FB) 00000h 0000h 0000h 0000h 0000h

1. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 50 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 5.3 Reset Sequence Activation time of flash memory (CPU clock × 148 cycles) 0FFFCh 0FFFEh 0FFFDh Content of reset vector CPU clock Address (internal address signal) Notes: 1. Hardware reset. 2. When the low-level input width of the RESET pin is set to fOCO-S clock × 8 cycles or more, the RESET pin is driven high at the same time as the internal reset signal is held high. CPU clock × 28 cycles fOCO-S clock × 32 cycles (2) fOCO-S Internal reset signal RESET pin 10 µs or more required (1)

1. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 51 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

5.1 Registers

5.1.1 Processor Mode Register 0 (PM0)

Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM0 register.

5.1.2 Reset Source Determina tion Register (RSTFR)

Notes: 1. The CWR bit is set to 0 (cold start-up) after power-on, vo ltage monitor 0 reset, or exit from power-off mode. This bit remains unchanged at a hardware reset, software reset, or watchdog timer reset. 2. When 1 is written to the CWR bit by a program, it is set to 1. (Writing 0 does not affect this bit.) 3. When the VW0C0 bit in the VW0C register is set to 0 (voltage monitor 0 reset disabled), the CWR bit value is undefined. 4. A hardware reset or an exit from power-off mode is detected. Address 0004h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 — b3 PM03 Software reset bit Setting this bit to 1 resets the MCU. When read, the content is 0. R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 — Address 000Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — WDR SWR HWR CWR After Reset X X X X 0 0 X X (Note 1) Bit Symbol Bit Name Function R/W b0 CWR Cold start-up/warm start-up determine flag (2, 3) 0: Cold start-up 1: Warm start-up R/W b1 HWR Hardware reset detect flag (4) 0: Not detected 1: Detected R b2 SWR Software reset detect flag 0: Not detected 1: Detected R b3 WDR Watchdog timer reset detect flag 0: Not detected 1: Detected R b4 — Reserved bits When read, the content is undefined. R b5 — b6 — b7 —

1. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 52 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

5.1.3 Option Function Se lect Register (OFS)

Notes: 1. If the block including the OFS register is er ased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. Address 0FFFFh B i t b 7 b 6b 5b 4b 3b 2b 1b 0 Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON W h e n s h i p p i n g 1 1111111 ( N o t e 1 ) Bit Symbol Bit Name Function R/W b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset 1: Watchdog timer is stopped after reset R/W b1 — Reserved bit Set to 1. R/W b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled 1: ROMCP1 bit enabled R/W b3 ROMCP1 ROM code protect bi t 0: ROM code protect enabled 1: ROM code protect disabled R/W b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4 0 0: 3.80 V selected (Vdet0_3) 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) R/W b5 VDSEL1 R/W b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset 1: Voltage monitor 0 reset disabled after reset R/W b7 CSPROINI Count source protection mode after reset select bit 0: Count source protection mode enabled after reset 1: Count source protection mode disabled after reset R/W

1. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 53 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

5.1.4 Option Function Sel ect Register 2 (OFS2)

Note: 1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh. The OFS2 register is located on the flash memory. Write to this register with a program. After writing, do not write additions to this register. Bits WDTRCS0 and WDTRCS1 (Watchdog Timer Refresh Acknowledgement Period Set Bit) Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh acknowledgement period for the watchdog timer can be selected. For details, refer to 15.3.1.1 Refresh Acknowledgment Period. Address 0FFDBh B i t b 7 b 6 b 5 b 4 b 3b 2b 1b 0 Symbol — — — — WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0 When shipping 1 1 1 1 1 1 1 1 (Note 1) Bit Symbol Bit Name Function R/W b0 WDTUFS0 Watchdog timer underflow period set bit b1 b0 0 0: 03FFh 0 1: 0FFFh 1 0: 1FFFh 1 1: 3FFFh R/W b1 WDTUFS1 R/W b2 WDTRCS0 Watchdog timer refresh acknowledgement period set bit b3 b2 0 0: 25% 0 1: 50% 1 0: 75% 1 1: 100% R/W b3 WDTRCS1 R/W b4 — Reserved bits Set to 1. R/W b5 — b6 — b7 —

1. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 54 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

5.2 Hardware Reset

A reset is applied using the RESET pin. When a low-level signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, the pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Status while RESET Pin Level is Low). When the input level applied to the RESET pin changes from low to high, a program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock with no division is automatically selected as the CPU clock. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after reset. The internal RAM is not reset. If the RESET pin is pulled low while writing to the internal RAM is in progress, the contents of internal RAM will be undefined. Figure 5.4 shows an Example of Hardware Reset Circuit and Operation and Figure 5.5 shows an Example of Hardware Reset Circuit (Usage Example of External Supply V oltage Detection Circuit) and Operation.

5.2.1 When Power Supply is Stable

(1) Apply a low-level signal to the RESET pin. (2) Wait for 10 µs. (3) Apply a high-level signal to the RESET pin.

5.2.2 Power On

(1) Apply a low-level signal to the RESET pin. (2) Let the supply voltage increase until it meets the recommended operating conditions. (3) Wait for td(P-R) or more to allow the inte rnal power supply to stabilize (refer to 36. Electrical Characteristics). (4) Wait for 10 µs. (5) Apply a high-level signal to the RESET pin.

1. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 55 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 5.4 Example of Hardware Reset Circuit and Operation Figure 5.5 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation RESET VCC VCC RESET 1.8 V 0 V

0.2 VCC or below

td(P-R) + 10 µs or more 0 V Note: 1. Refer to 36. Electrical Characteristics. RESET VCC VCC RESET 1.8 V 0 V 0 V 5 V 5 V Example when VCC = 5 V Supply voltage detection circuit Note: 1. Refer to 36. Electrical Characteristics. td(P-R) + 10 µs or more

1. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 56 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

5.3 Power-On Reset Function

When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while the rise gradient is trth or more, the power-on reset function is enabled and the pins, CPU, and SFRs are reset. When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8 VCC or above. When the input voltage to the VCC pin reaches the Vdet0 level or above, th e low-speed on-chip oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held high and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no division is automatically selected as the CPU clock after reset. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after power-on reset. After power-on reset, voltage monitor 0 reset is enabled when the LVDAS bit in the OFS register is set to 0 (voltage monitor 0 reset enabled after reset). Figure 5.6 shows an Example of Power-On Reset Circuit and Operation. Figure 5.6 Example of Power-On Reset Circuit and Operation RESET VCC 4.7 kΩ (reference) Notes: 1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. 2. Refer to 36. Electrical Characteristics. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0, bits VW0C0 and VW0C6 in the VW0C register to 1 individually, and the VCA25 bit in the VCA2 register to 1. Vdet0 Vpor1 Internal reset signal (low valid) tw(por1) Vccmin External Power VCC trthtrth fOCO-S × 32 1 fOCO-S × 32

1. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 57 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

5.4 Voltage Monitor 0 Reset

A reset is applied using the on-chip voltage detection 0 ci rcuit. The voltage detection 0 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet0. The Vdet0 voltage detection level can be changed by the settings of bits VDSEL0 and VDSEL1 in the OFS register. When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFRs are reset. When the input voltage to the VCC pin reaches the Vdet0 level or above, th e low-speed on-chip oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held high and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no division is automatically selected as the CPU clock after a reset. The LVDAS bit in the OFS register can be used to select whether voltage monitor 0 re set is enabled or disabled after a reset. The setting of the LVDAS bit is enabled at all resets. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0, bits VW0C0 and VW0C6 bits in the VW0C register to 1 individually, and the VCA25 bit in the VCA2 register to Bits VDSEL0 to VDSEL1 and LVDAS cannot be changed by a program. To set these bits, write values to b4 to b6 of address 0FFFFh using a flash programmer. Refer to 5.1.3 Option Function Select Register (OFS) for details of the OFS register. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after voltage monitor 0 reset. The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while writing to the internal RAM is in progress, the contents of internal RAM are undefined. Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset. Figure 5.7 shows an Example of V oltage Monitor 0 Reset Circuit and Operation. Figure 5.7 Example of Voltage Monitor 0 Reset Circuit and Operation RESET VCC 4.7 kΩ (reference) VCC Vccmin Internal reset signal (low valid) Sampling time (1, 2) tw(Vdet0) fOCO-S × 32 Vdet0 Vpor1 Notes: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (1.8 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. 4. Refer to 36. Electrical Characteristics. 5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0, bits VW0C0 and VW0C6 in the VW0C register to 1 individually, and the VCA25 bit in the VCA2 register to 1.

1. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 58 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

5.5 Watchdog Timer Reset

When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins, CPU, and SFRs when the watchdog timer underflows. Then the program beginning with the address indicated by the reset vector is executed. The low-speed on-chip oscillator clock with no division is automatically selected as the CPU clock after reset. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after watchdog timer reset. The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined. The underflow period and refresh acknowledge period for the watchdog timer can be set by bits WDTUFS0 and WDTUFS1 and bits WDTRCS0 and WDTRCS1 in the OFS2 register, respectively. Refer to 15. Watchdog Timer for details of the watchdog timer.

5.6 Software Reset

When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFRs. The program beginning with the address indicated by the reset vector is executed. The low-speed on-chip oscillator clock with no division is automatically selected for the CPU clock after reset. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after software reset. The internal RAM is not reset.

1. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 59 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

5.7 Cold Start-Up/Warm Start- Up Determination Function

The cold start-up/warm start-up determination function uses the CWR bit in the RSTFR register to determine cold start-up (reset process) at power-on and warm start-up (reset process) when a reset occurred during operation. The CWR bit is set to 0 (cold start-up) at power-on and al so set to 0 at a voltage moni tor 0 reset or an exit from power-off mode. When 1 is written to the CWR bit by a prog ram, it is set to 1. This bit remains unchanged at a hardware reset, software reset, or watchdog timer reset. The cold start-up/warm stat-up determination function uses voltage monitor 0 reset. To set the bits associated with voltage monitor 0 reset, follow Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset. Figure 5.8 shows an Operating Example of Cold Start-Up/Warm Start-Up Function Figure 5.8 Operating Example of Cold Start-Up/Warm Start-Up Function

5.8 Reset Source Determination Function

The RSTFR register can be used to de tect whether a hardware reset, softwa re reset, or watchdog timer reset has occurred. If a hardware reset or an exit from power-off mode occurs, the HWR bit is set to 1 (detected). If a software reset occurs, the SWR bit is set to 1 (detected). If a watchdog timer reset occurs, the WDR bit is set to 1 (detected). Set to 1 by a program. Vdet0 CWR bit in RSTFR register Voltage monitor 0 reset VCC Set to 1 by a program. The above applies when the digital filter is not used.

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 60 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 6. Voltage Detection Circuit The voltage detection circuit monitors th e voltage input to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program.

6.1 Introduction

The detection voltage of voltage detection 0 can be selected among four levels using the OFS register. The detection voltage of voltage detection 1 can be selected among 16 levels using the VD1LS register. As a detection target, the voltage input to VCC and the LVCMP2 pin can be switched for voltage detection 2 only. The voltage monitor 0 reset, and voltage monitor 1 interrupt and voltage monitor 2 interrupt can also be used. Note that voltage monitor 1 and voltage monitor 2 share the voltage detection circuit with comparator A1 and comparator A2. Either voltage monito r 1 and voltage monitor 2 or compar ator A1 and comp arator A2 can be selected. Table 6.1 Voltage Detectio n Circuit Specifications Item Voltage Monitor 0 Voltage Monitor 1 Voltage Monitor 2 VCC monitor Voltage to monitor Vdet0 Vdet1 Vdet2 Detection target Whether passing through Vdet0 by falling Whether passing through Vdet1 by rising or falling Whether passing through Vdet2 by rising or falling The input voltage to VCC and the LVCMP2 pin can be switched by the VCA24 bit in the VCA2 register. Detection voltage Selectable among 4 levels using the OFS register. Selectable among 16 levels using the VD1LS register. The detection voltage level varies depending on when VCC is selected or when LVCMP2 is selected. Each value is set as the fixed level. Monitor None The VW1C3 bit in the VW1C register The VCA13 bit in the VCA1 register Whether VCC is higher or lower than Vdet1 Whether VCC or LVCMP2 input voltage is higher or lower than Vdet2 Process at voltage detection Reset Voltage monitor 0 reset None None Reset at Vdet0 > VCC; CPU operation restarts at VCC > Vdet0 Interrupts None Voltage monitor 1 interrupt Voltage monitor 2 interrupt Non-maskable or maskable selectable Non-maskable or maskable selectable Interrupt request at: Vdet1 > VCC and/or VCC > Vdet1 Interrupt request at: Vdet2 > VCC (LVCMP2) and/or VCC (LVCMP2) > Vdet2 Digital filter Switching enable/disable Supported Supported Supported Sampling time (fOCO-S divided by n) × 4 n: 1, 2, 4, and 8 (fOCO-S divided by n) × 2 n: 1, 2, 4, and 8 (fOCO-S divided by n) × 2 n: 1, 2, 4, and 8

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 61 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 6.1 Block Diagram of Voltage Detection Circuit Table 6.2 Pin Configuration of Voltage Detection Circuit Pin Name I/O Function LVCMP2 Input Detection target voltage pin for voltage detection 2 VCA25 ≥ Vdet2 Internal reference voltage VCA27 VCA26 VCC Voltage detection 1 signal VCA13 bit Voltage detection 2 signal Voltage detection 0 signal ≥ Vdet1 ≥ Vdet0 VCA1 register VW1C3 bit VW1C register Level selection circuit (16 levels) LVCMP2 VCA24 = 1 VCA24 = 0 VCA13: Bit in VCA1 register VCA24, VCA25, VCA26, VCA27: Bits in VCA2 register VW1C3: Bit in VW1C register VD1S0 to VD1S3: Bits in VD1LS register VDSEL0, VDSEL1: Bits in OFS register Shared with comparator A VD1S3 to VD1S0 Level selection circuit (4 levels) VDSEL1 to VDSEL0

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 63 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 6.4 Block Diagram of Voltage Monitor 2 Interrupt Generation Circuit 1/2 1/2 1/2 Voltage detection 2 circuit VCA27 VCA13 When VCA27 bit is set to 0 (disabled), voltage detection 2 signal is driven high. Voltage detection 2 signal fOCO-S VW2F1 to VW2F0 = 00b = 01b = 10b = 11b VW2C2 bit is set to 0 (not detected) by writing 0 by a program. When VCA27 bit is set to 0 (voltage detection 2 circuit disabled), VW2C2 bit is set to 0. VW2C2 VW2C3 Watchdog timer block Watchdog timer underflow signal VW2C3 bit is set to 0 (not detected) by writing 0 by a program. COMPSEL IRQ2SEL Maskable interrupt signal Non-maskable interrupt signal Voltage monitor 2 interrupt signal Watchdog timer interrupt signal Comparator A2 interrupt signal Voltage monitor 2 interrupt generation circuit VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C VCA13: Bit in VCA1 register VCA23, VCA24, VCA27: Bits in VCA2 register COMPSEL, IRQ2SEL: Bits in CMPA register VCAC2: Bit in VCAC register LVCMP2 VCA24 = 1 VCA24 = 0 VCC VW2C1 = 0 VW2C1 = 1 Digital filter Edge selection circuit VW2C0 Internal reference voltage VCA23 = 0 VCAC2 VW2C6

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 64 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.2 Registers

6.2.1 Voltage Monitor Ci rcuit/Comparator A Control Register (CMPA)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol COMPSEL — IRQ2SEL IRQ1SEL CM2OE CM1OE CM2POR CM1POR A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 CM1POR LVCOUT1 output polarity select bit 0: Non-inverted comparator A1 comparison result is output to LVCOUT1. 1: Inverted comparator A1 comparison result is output to LVCOUT1. R/W b1 CM2POR LVCOUT2 output polarity select bit 0: Non-inverted Comparator A2 comparison result is output to LVCOUT2. 1: Inverted comparator A2 comparison result is output to LVCOUT2. R/W b2 CM1OE LVCOUT1 output enable bit 0: Output disabled 1: Output enabled R/W b3 CM2OE LVCOUT2 output enable bit 0: Output disabled 1: Output enabled R/W b4 IRQ1SEL Voltage monitor 1/comparator A1 interrupt type select bit 0: Non-maskable interrupt 1: Maskable interrupt R/W b5 IRQ2SEL Voltage monitor 2/comparator A2 interrupt type select bit 0: Non-maskable interrupt 1: Maskable interrupt R/W b6 — Reserved bit Set to 0. R/W b7 COMPSEL Voltage monitor/comparator A interrupt type selection enable bit 0: Bits IRQ1SEL and IRQ2SEL disabled 1: Bits IRQ1SEL and IRQ2SEL enabled R/W

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 65 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.2.2 Voltage Monito r Circuit Edge Select Register (VCAC)

Notes: 1. When the VCA1 bit is set to 0 (one edge), the VW1C7 bit in the VW1C register is enabled. Set the VW1C7 bit after setting the VCAC1 bit to 0. 2. When the VCA2 bit is set to 0 (one edge), the VW2C7 bit in the VW2C register is enabled. Set the VW2C7 bit after setting the VCAC2 bit to 0.

6.2.3 Voltage Detect Register (VCA1)

Note: 1. When the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled), the VCA13 bit is enabled. When the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2 circuit disabled), the VCA13 bit is set to 1 (VCC ≥ Vdet2). Address 0031h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — — VCAC2 VCAC1 — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 VCAC1 Voltage monitor 1 circuit edge select bit (1) 0: One edge 1: Both edges R/W b2 VCAC2 Voltage monitor 2 circuit edge select bit (2) 0: One edge 1: Both edges R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 — b6 — b7 — Address 0033h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00001000 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 — b3 VCA13 Voltage detection 2 signal monitor flag (1) 0: VCC < Vdet2 1: VCC ≥ Vdet2 or voltage detection 2 circuit disabled R b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 —

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 66 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.2.4 Voltage Detect Register 2 (VCA2)

Notes: 1. Use the VCA20 bit only when the MCU enters wait mode. To set the VCA20 bit, follow the procedure shown in Figure 10.7 Handling Procedure for Reducing Internal Power Consumption Using VCA20 Bit. 2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop mode). 3. To use voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection circuit starts operation. 4. To use the voltage detection 1/comparator A1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1/comparator A1 circuit starts operation. 5. To use the voltage detection 2/compar ator A2 interrupt or the VCAC13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2/comparator A2 circuit starts operation. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register. Address 0034h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VCA27 VCA26 VCA25 VCA24 VCA23 VCA22 VCA21 VCA20 After Reset The LVDAS bit in the OFS register is set to 1. 00000000 After Reset The LVDAS bit in the OFS register is set to 0. 00100000 Bit Symbol Bit Name Function R/W b0 VCA20 Internal power low consumption enable bit (1) 0: Low consumption disabled 1: Low consumption enabled (2) R/W b1 VCA21 Comparator A1 reference voltage input select bit 0: Internal reference voltage 1: LVREF pin input voltage R/W b2 VCA22 LVCMP1 comparison voltage external input select bit 0: Supply voltage (VCC) 1: LVCMP1 pin input voltage R/W b3 VCA23 Comparator A2 reference voltage input select bit 0: Internal reference voltage 1: LVREF pin input voltage R/W b4 VCA24 LVCMP2 comparison voltage external input select bit 0: Supply voltage (VCC) (Vdet2_0) 1: LVCMP2 pin input voltage (Vdet2_EXT) R/W b5 VCA25 Voltage detection 0 enable bit (3) 0: Voltage detection 0 circuit disabled 1: Voltage detection 0 circuit enabled R/W b6 VCA26 Voltage detection 1/comparator A1 enable bit (4) 0: Voltage detection 1/comparator A1 circuit disabled 1: Voltage detection 1/comparator A1 circuit enabled R/W b7 VCA27 Voltage detection 2/comparator A2 enable bit (5) 0: Voltage detection 2/comparator A2 circuit disabled 1: Voltage detection 2/comparator A2 circuit enabled R/W

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 67 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.2.5 Voltage Detection 1 Leve l Select Register (VD1LS)

Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VD1LS register. Address 0036h B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l ———— V D 1 S 3 V D 1 S 2 V D 1 S 1 V D 1 S 0 A f t e r R e s e t 00000111 Bit Symbol Bit Name Function R/W b0 VD1S0 Voltage detection 1 level select bit (Reference voltage when the voltage falls) b3 b2 b1 b0 0 0 0 0: 2.20 V (Vdet1_0) 0 0 0 1: 2.35 V (Vdet1_1) 0 0 1 0: 2.50 V (Vdet1_2) 0 0 1 1: 2.65 V (Vdet1_3) 0 1 0 0: 2.80 V (Vdet1_4) 0 1 0 1: 2.95 V (Vdet1_5) 0 1 1 0: 3.10 V (Vdet1_6) 0 1 1 1: 3.25 V (Vdet1_7) 1 0 0 0: 3.40 V (Vdet1_8) 1 0 0 1: 3.55 V (Vdet1_9) 1 0 1 0: 3.70 V (Vdet1_A) 1 0 1 1: 3.85 V (Vdet1_B) 1 1 0 0: 4.00 V (Vdet1_C) 1 1 0 1: 4.15 V (Vdet1_D) 1 1 1 0: 4.30 V (Vdet1_E) 1 1 1 1: 4.45 V (Vdet1_F) R/W b1 VD1S1 R/W b2 VD1S2 R/W b3 VD1S3 R/W b4 — Reserved bits Set to 0. R/W b5 — R/W b6 — R/W b7 — R/W

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 68 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.2.6 Voltage Monitor 0 Circ uit Control Register (VW0C)

Note: 1. The VW0C0 bit is enabled when the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit enabled). Set the VW0C0 bit to 0 (disabled) when the VCA25 bit in the VCA2 register is set to 0 (voltage detection 0 circuit disabled). To set the VW0C0 bit to 1 (enabled), follow the procedure in Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset. Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing to the VW0C register. Address 0038h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — VW0F1 VW0F0 — — VW0C1 VW0C0 After Reset The LVDAS bit in the OFS register is set to 1. 1100X010 After Reset The LVDAS bit in the OFS register is set to 0. 1100X011 Bit Symbol Bit Name Function R/W b0 VW0C0 Voltage monitor 0 reset enable bit (1) 0: Disabled 1: Enabled R/W b1 VW0C1 Voltage monitor 0 digital filter disabled mode select bit 0: Digital filter enabled mode (digital filter circuit enabled) 1: Digital filter disabled mode (digital filter circuit disabled) R/W b2 — Reserved bit Set to 0. R/W b3 — Reserved bit When read, the content is undefined. R b4 VW0F0 Sampling clock select bit b5 b4 0 0: fOCO-S divided by 1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 R/W b5 VW0F1 R/W b6 — Reserved bits Set to 1. R/W b7 — R/W

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 69 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.2.7 Voltage Monitor 1 Circ uit Control Register (VW1C)

Notes: 1. The VW1C0 is enabled when the VCA26 bit in the VCA2 r egister is set to 1 (voltage detection 1 circuit enabled). Set the VW1C0 bit to 0 (disabled) when the VCA26 bit is set to 0 (voltage detection 1 circuit disabled). To set the VW0C0 bit to 1 (enabled), follow the procedure shown in Table 6.4 Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt. 2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW1C1 bit. 3. Bits VW1C2 and VW1C3 are enabled when the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled). 4. Set the VW1C2 bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged even if 1 is written to it). 5. The VW1C7 bit is enabled when the VCAC1 bit in the VC AC register is set to 0 (one edge). After setting the VCAC1 bit to 0, set the VW1C7 bit. Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing the VW1C register. Rewriting the VW1C register may set the VW1C2 bit to 1. Set the VW1C2 bit to 0 after rewriting the VW1C register. Address 0039h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VW1C7 — VW1F1 VW1F0 VW1C3 VW1C2 VW1C1 VW1C0 A f t e r R e s e t 10001010 Bit Symbol Bit Name Function R/W b0 VW1C0 Voltage monitor 1 reset enable bit (1) 0: Disabled 1: Enabled R/W b1 VW1C1 Voltage monitor 0 digital filter disable mode select bit (2) 0: Digital filter enabled mode (digital filter circuit enabled) 1: Digital filter disable mode (digital filter circuit disabled) R/W b2 VW1C2 Voltage change detection flag (3, 4) 0: Not detected 1: Vdet1 passing detected R/W b3 VW1C3 Voltage detection 1 signal monitor flag (3) 0: VCC < Vdet1 1: VCC ≥ Vdet1 or voltage detection 1 circuit disabled R b4 VW1F0 Sampling clock select bit b5 b4 0 0: fOCO-S divided by 1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 R/W b5 VW1F1 R/W b6 — Reserved bit Set to 0. R/W b7 VW1C7 Voltage monitor 1 reset generation condition select bit (5) 0: When VCC reaches Vdet1 or above. 1: When VCC reaches Vdet1 or below. R/W

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 70 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.2.8 Voltage Monitor 2 Circ uit Control Register (VW2C)

Notes: 1. The VW2C0 is enabled when the VCA27 bit in the VCA2 r egister is set to 1 (voltage detection 2 circuit enabled). Set the VW2C0 bit to 0 (disabled) when the VCA27 bit is set to 0 (voltage detection 2 circuit disabled). To set the VW2C0 bit to 1 (enabled), follow the procedure shown in Table 6.5 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt. 2. To use the voltage monitor 2 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW2C1 bit. 3. The VW2C2 bit is enabled when the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). 4. Set this bit to 0 by a program. When 0 is written by a pr ogram, this bit is set to 0 (and remains unchanged even if 1 is written to it). 5. The VW2C7 bit is enabled when the VCAC2 bit in the VC AC register is set to 0 (one edge). After setting the VCAC2 bit to 0, set the VW2C7 bit. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW2C register. Rewriting the VW2C register may set the VW2C2 bit to 1. After rewriting this register, set the VW2C2 bit to 0. Address 003Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VW2C7 — VW2F1 VW2F0 VW2C3 VW2C2 VW2C1 VW2C0 A f t e r R e s e t 10000010 Bit Symbol Bit Name Function R/W b0 VW2C0 Voltage monitor 2 interrupt enable bit (1) 0: Disabled 1: Enabled R/W b1 VW2C1 Voltage monitor 2 digital filter disable mode select bit (2) 0: Digital filter enable mode (digital filter circuit enabled) 1: Digital filter disable mode (digital filter circuit disabled) R/W b2 VW2C2 Voltage change detection flag (3, 4) 0: Not detected 1: Vdet2 passing detected R/W b3 VW2C3 WDT detection monitor flag (4) 0: Not detected 1: Detected R/W b4 VW2F0 Sampling clock select bit b5 b4 0 0: fOCO-S divided by 1 0 1: fOCO-S divided by 2 1 0: fOCO-S divided by 4 1 1: fOCO-S divided by 8 R/W b5 VW2F1 R/W b6 — Reserved bit Set to 0. R/W b7 VW2C7 Voltage monitor 2 interrupt generation condition select bit (5) 0: When VCC or LVCMP2 reaches Vdet2 or above. 1: When VCC or LVCMP2 reaches Vdet2 or below. R/W

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 71 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.2.9 Option Function Se lect Register (OFS)

Notes: 1. If the block including the OFS register is er ased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. Address 0FFFFh B i t b 7 b 6b 5b 4b 3b 2b 1b 0 Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON W h e n s h i p p i n g 1 1111111 ( N o t e 1 ) Bit Symbol Bit Name Function R/W b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset 1: Watchdog timer is stopped after reset R/W b1 — Reserved bit Set to 1. R/W b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled 1: ROMCP1 bit enabled R/W b3 ROMCP1 ROM code protect bi t 0: ROM code protect enabled 1: ROM code protect disabled R/W b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4 0 0: 3.80 V selected (Vdet0_3) 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) R/W b5 VDSEL1 R/W b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset 1: Voltage monitor 0 reset disabled after reset R/W b7 CSPROINI Count source protection mode after reset select bit 0: Count source protection mode enabled after reset 1: Count source protection mode disabled after reset R/W

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 72 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.3 VCC Input Voltage

6.3.1 Monitoring Vdet0

Vdet0 cannot be monitored.

6.3.2 Monitoring Vdet1

Once the following settings are made, the comparison re sult of voltage monitor 1 can be monitored by the VW1C3 bit in the VW1C register after td(E-A) has elapsed (refer to 36. Electrical Characteristics). (1) Set bits VD1S3 to VD1S0 in the VD1LS register (voltage detection 1 detection voltage). (2) Set the VCA21 bit in the VCA2 register to 0 (internal reference voltage). (3) Set the VCA22 bit in the VCA2 register to 0 (VCC voltage). (4) Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled).

6.3.3 Monitoring Vdet2

Once the following settings are made, the comparison re sult of voltage monitor 2 can be monitored by the VCA13 bit in the VCA1 register after td(E-A) has elapsed (refer to 36. Electrical Characteristics). (1) Set the VCA23 bit in the VCA2 register to 0 (internal reference voltage). (2) Set the VCA24 bit in the VCA2 register to 0 (VCC voltage), or 1 (LVCMP2 pin input voltage). (3) Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled).

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 73 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.4 Voltage Monitor 0 Reset

Table 6.3 lists the Procedure for Setting Bits Associated with V oltage Monitor 0 Reset and Figure 6.5 shows an Operating Example of V oltage Monitor 0 Reset. To use the voltage monitor 0 reset to exit stop mode, set the VW0C1 bit in the VW0C register to 1 (digital filter disabled). Note: 1. When the VW0C0 bit is set to 0, steps 3 and 4 can be executed simultaneously (with one instruction). Figure 6.5 Operating Example of Voltage Monitor 0 Reset Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 0 Reset Step When Using Digital Filter When Using No Digital Filter 1 Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled). 2 Wait for td(E-A).

3 Select the sampling clock of the digital filter by

bits VW0F1 to VW0F0 in the VW0C register. Set the VW0C7 bit in the VW0C register to 1. (1) Set the VW0C1 bit in the VW0C register to 0 (digital filter enabled). Set the VW0C1 bit in the VW0C register to 1 (digital filter disabled). 5 Set the VW0C2 bit in the VW0C register to 0.

6 Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on).

7 Wait for 4 cycles of the sampling clock of

the digital filter. − (No wait time required) 8 Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled). Vdet0 Internal reset signal VCC The above applies under the following conditions:

• VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled)
• VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled) When the internal reset signal is driven low, the pins, CPU, and SFRs are initialized. When the internal reset signal level changes from low to high, a program is executed beginning with the address indicated by the reset vector. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after reset. fOCO-S × 32Sampling clock of digital filter × 4 cycles VW0C1 bit is set to 0 (digital filter enabled) Internal reset signalVW0C1 bit is set to 1 (digital filter disabled) fOCO-S × 32 VW0C1 and VW0C7: Bits in VW0C register

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 74 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.5 Voltage Monitor 1 Interrupt

Table 6.4 lists the Procedure for Setting Bits Associated with V oltage Monitor 1 Interrupt. Figure 6.6 shows an Operating Example of V oltage Monitor 1 Interrupt. To use the voltage monitor 1 interrupt to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter disabled). Notes: When the VW1C0 bit is set to 0, steps 2, 3, and 4 can be executed simultaneously (with one instruction). 2. When the VW1C0 bit is set to 0, steps 6 and 7 can be executed simultaneously (with one instruction). 3. When the VW1C0 bit is set to 0, steps 8 and 9 can be executed simultaneously (with one instruction). Table 6.4 Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt Step When Using Digital Filter When Using No Digital Filter 1 Select the voltage detection 1 detection voltage by bits VD1S3 to VD1S0 in the VD1LS register. 2 Set the VCA21 bit in the VCA2 register to 0 (internal reference voltage). 3 (1) Set the VCA22 bit in the VCA2 register to 0 (VCC voltage). 4 (1) Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). 5 Wait for td(E-A). 6 Set the COMPSEL bit in th e CMPA register to 1. 7 (2) Select the interrupt type by the IRQ1SEL in the CMPA register.

8 Select the sampling clock of the digital filter by

bits VW1F1 to VW1F0 in the VW1C register. Set the VW1C1 bit in the VW1C register to 1 (digital filter disabled). 9 (3) Set the VW1C1 bit in the VW1C register to 0 (digital filter enabled).

10 Select the interrupt request timing by the VCAC1 bit in the VCAC register and

the VW1C7 bit in the VW1C register. 11 Set the VW1C2 bit in the VW1C register to 0.

12 Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on)

13 Wait for 2 cycles of the sampling clock of

− (No wait time required)

14 Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt enabled)

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 75 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 6.6 Operating Example of Voltage Monitor 1 Interrupt Vdet1 VW1C3 bit VCC The above applies under the following conditions:

• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt enabled) Note: 1. When voltage monitor 0 reset is not used, set the power supply to VCC ≥ 1.8 V.

1.8 V (1)

digital filter × 2 cycles VW1C2 bit VW1C2 bit 1VW1C1 bit is set to 1 (digital filter disabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 0 (when VCC reaches Vdet1 or above) VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register VCAC1: Bit in VCAC register Sampling clock of digital filter × 2 cycles Set to 0 by a program. Voltage monitor 1 interrupt request Voltage monitor 1 interrupt request Set to 0 when an interrupt request is acknowledged. VW1C2 bit Voltage monitor 1 interrupt request VW1C1 bit is set to 0 (digital filter enabled) and VCAC1 bit is set to 1 (both edges) VW1C2 bit Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. Voltage monitor 1 interrupt request VW1C1 bit is set to 0 (digital filter enabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 0 (when VCC reaches Vdet1 or above) VW1C2 bit Voltage monitor 1 interrupt request VW1C1 bit is set to 0 (digital filter enabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 1 (when VCC reaches Vdet1 or below) Set to 0 by a program. VW1C2 bit Voltage monitor 1 interrupt request VW1C1 bit is set to 1 (digital filter disabled) and VCAC1 bit is set to 1 (both edges) Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. VW1C1 bit is set to 1 (digital filter disabled), VCAC1 bit is set to 0 (one edge), and VW1C7 bit is set to 1 (when VCC reaches Vdet1 or below) Set to 0 when an interrupt request is acknowledged. Set to 0 when an interrupt request is acknowledged.

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 76 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.6 Voltage Monitor 2 Interrupt

Table 6.5 lists the Procedure for Setting Bits Associated with V oltage Monitor 2 Interrupt. Figure 6.7 shows an Operating Example of V oltage Monitor 2 Interrupt. To use the voltage monitor 2 interrupt to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter disabled). Notes: When the VW2C0 bit is set to 0, steps 1, 2, and 3 can be executed simultaneously (with one instruction). 2. When the VW2C0 bit is set to 0, steps 5 and 6 can be executed simultaneously (with one instruction). 3. When the VW2C0 bit is set to 0, steps 7 and 8 can be executed simultaneously (with one instruction). Table 6.5 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt Step When Using Digital Filter When Using No Digital Filter 1 Set the VCA23 bit in the VCA2 register to 0 (internal reference voltage). 2 (1) Set the VCA24 bit in the VCA2 register to 0 (VCC voltage) or 1 (LCVCMP2 pin input voltage). 3 (1) Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). 4 Wait for td(E-A). 5 Set the COMPSEL bit in th e CMPA register to 1. 6 (2) Select the interrupt type by the IRQ2SEL in the CMPA register.

7 Select the sampling clock of the digital filter by

bits VW2F1 to VW2F0 in the VW2C register. Set the VW2C1 bit in the VW2C register to 1 (digital filter disabled). 8 (3) Set the VW2C1 bit in the VW2C register to 0 (digital filter enabled).

9 Select the interrupt request timing by the VCAC2 bit in the VCAC register and

the VW2C7 bit in the VW2C register. 10 Set the VW2C2 bit in the VW2C register to 0.

11 Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on).

12 Wait for 2 cycles of the sampling clock of

the digital filter. − (No wait time required) 13 Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt enabled).

1. Voltage Detection Circuit REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 77 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 6.7 Operating Example of Voltage Monitor 2 Interrupt Vdet2 VW1C3 bit VCC or LVCMP2 The above applies under the following conditions:

• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt enabled) Note: 1. When voltage monitor 0 reset is not used, set the power supply to VCC ≥ 1.8 V.

digital filter × 2 cycles VW2C2 bit VW2C2 bit 1VW2C1 bit is set to 1 (digital filter disabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 0 (when VCC or LVCMP2 reaches Vdet2 or above) VCA13: Bit in VCA1 register VW2C1, VW2C2, VW2C3, VW2C7: Bits in VW2C register VCAC2: Bit in VCAC register Sampling clock of digital filter × 2 cycles Set to 0 by a program. Voltage monitor 2 interrupt request Voltage monitor 2 interrupt request Set to 0 when an interrupt request is acknowledged. VW2C2 bit Voltage monitor 2 interrupt request VW2C1 bit is set to 0 (digital filter enabled) and VCAC2 bit is set to 1 (both edges) VW2C2 bit Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. Voltage monitor 2 interrupt request VW2C1 bit is set to 0 (digital filter enabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 0 (when VCC or LVCMP2 reaches Vdet2 or above) VW2C2 bit Voltage monitor 2 interrupt request VW2C1 bit is set to 0 (digital filter enabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 1 (when VCC or LVCMP2 reaches Vdet2 or below) Set to 0 by a program. VW2C2 bit Voltage monitor 2 interrupt request VW2C1 bit is set to 1 (digital filter disabled) and VCAC2 bit is set to 1 (both edges) Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. Set to 0 by a program. Set to 0 when an interrupt request is acknowledged. Set to 0 by a program.VW2C1 bit is set to 1 (digital filter disabled), VCAC2 bit is set to 0 (one edge), and VW2C7 bit is set to 1 (when VCC or LVCMP2 reaches Vdet2 or below) Set to 0 when an interrupt request is acknowledged. Set to 0 when an interrupt request is acknowledged.

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 78 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 7. I/O Ports I/O ports are shared with the LCD po rts for the LCD dive control waveform output and the I/O functions for the oscillation circuits, timers, and A/D converter. When these functions are not used, pins can be used as I/O ports. Table 7.1 lists the Overview of I/O Ports. The following explanation applies to the R8C/L33A Group and R8C/L3AB Group, which have the maximum number of I/O ports. For other groups, note that only the pins listed in Table 7.2 are provided. Notes: 1. In input mode, whether an internal pull-up resistor is connected or not can be sele cted by registers P0PUR to and P13PUR. 2. Whether the drive capacity of the output transistor is set to low or high can be selected by registers P10DRR and P11DRR. 3. The input threshold value can be selected among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC) using registers VLT0 and VLT1. Note: 1. The symbol “ √” indicates a programmable I/O port. Table 7.1 Overview of I/O Ports Port I/O Format I/O Setting Internal Pull-Up Resister (1) Drive Capacity Switch (2) Input Level Switch (3) P0 to P4 I/O CMOS3 state Set in 1-bit units. Set in 1-bit units. None Set in 8-bit units. P5_0 to P5_3 I/O CMOS3 state Set in 1-bit units. Set in 1-bit units. None Set in 4-bit units. P6, P7 I/O CMOS3 state Set in 1-bit units. Set in 1-bit units. None Set in 8-bit units. P10, P11 I/O CMOS3 state Set in 1-bit units. Set in 1-bit units. Set in 1-bit units. Set in 8-bit units. P12_0 to P12_3 I/O CMOS3 state Set in 1-bit units. Set in 1-bit units. None Set in 4-bit units. P13 I/O CMOS3 state Set in 1-bit units. Set in 1-bit units. None Set in 8-bit units. Table 7.2 Programmable I/O Ports Provided for Each Group Programmable I/O Port R8C/L35A Group R8C/L35B Group Total: 41 I/O pins R8C/L36A Group R8C/L36B Group Total: 52 I/O pins R8C/L38A Group R8C/L38B Group Total: 68 I/O pins R8C/L3AA Group R8C/L3AB Group Total: 88 I/O pins bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 79 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.1 I/O Port Functions

The PDi_j (j = 0 to 7) bit in the PDi (i = 0 to 7, 10 to 13) register controls the input/output of ports P0 to P7 and P10 to P13. The Pi register consists of a port latch to retain output data and a circuit to read the pin status. Figures 7.1 to 7.4 show the I/O Port Configurations, and Table 7.3 lists the I/O Port Functions. Note: 1. i = 0 to 7, 10 to 13; j = 0 to 7

7.2 Effect on Peripheral Functions

I/O ports function as I/O ports for peripheral functions (refer to Tables 1.15 to 1.17 Pin Name Information by Pin Number). Table 7.4 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 7, 10 to 13; j = 0 to 7). Refer to the description of each function for information on how to set peripheral functions.

7.3 Pins Other than I/O Ports

Figure 7.5 shows the Pin Configuration. Table 7.3 I/O Port Functions Operation When Accessing Pi Register Value of PDi_j Bit in PDi Register (1) When PDi_j Bit is Set to 0 (Input Mode) W hen PDi_j Bit is Set to 1 (Output Mode) Read Read the pin input level. Read the port latch. Write Write to the port latch. Write to the port latch. The value written to the port latch is output from the pin. Table 7.4 Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 7, 10 to 13; j = 0 to 7) I/O of Peripheral Function PDi_j Bit Settings for Shared Pin Function Input Set this bit to 0 (input mode). Output This bit can be set to either 0 or 1 (output regardless of the port setting).

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 80 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 7.1 I/O Port Configuration (1) VL4 Data bus Direction register VL3 VL2 VL1 VSS P0 to P3, P5, and P7 Port latch Input level switch function P0, P1_0 to P1_3 only VL4 Data bus Pin select register Input to individual peripheral function Direction register VL3 VL2 VL1 VSS P4 and P6 Port latch Input level switch function (Note 1) (Note 1) Analog input of A/D converter Note: 1. symbolizes a parasitic diode. Pull-up selection LCD port select Input to individual peripheral function Pin select register Input to individual peripheral function Pin select register Pull-up selection LCD port select

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 81 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 7.2 I/O Port Configuration (2) Input to individual peripheral function Analog input of comparators A and B Data bus Pin select register Input to individual peripheral function Direction register (Note 2) Pin select register P10 and P11 Port latch Input level switch function P11_0 to P11_3 only (Note 1) VL4 Data bus Direction register (Note 1) LCD port select VL3 VL2 VL1 VSS P12_2 and P12_3 Port latch Input level switch function Notes: 1. symbolizes a parasitic diode. 2. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. Pull-up selection Drive capacity selection Pull-up selection

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 82 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 7.3 I/O Port Configuration (3) Input to XIN clock Data bus Pull-up selection Direction register (Note 1) (Note 2) P12_0/XIN Port latch Input level switch function Data bus Pull-up selection Direction register (Note 1) (Note 2) Port latch Input level switch function CM13 RfXIN P12_1/XOUT CM05, CM07: Bits in CM0 register CM11, CM13: Bits in CM1 register CM07 CM05 CM13 = 0 CM13 = 1 CM05 Stop mode CM11 Stop mode Notes: 1. symbolizes a parasitic diode. 2. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC.

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 83 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 7.4 I/O Port Configuration (4) Input to individual peripheral function Analog input of A/D converter Data bus Pull-up selection Pin select register Input to individual peripheral function Direction register (Note 1) (Note 2) Pin select register P13_0 to P13_7 Port latch Input level switch function P13_0 and P13_1 only Analog input of comparator A P13_2 to P13_4 only Analog input of D/A converter Notes: 1. symbolizes a parasitic diode. 2. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC.

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 84 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 7.5 Pin Configuration A/D converter VREF (Note 1) VREF (Note 2) MODE input signal (Note 1) MODE (Note 1) RESET RESET input signal (Note 1) XCIN/XCOUT (Note 2) XCIN (Note 1) (Note 2) XCOUT CM12 RfXCIN Power-off mode input signal (Note 1) CM03 Stop mode Input to XIN clock Stop mode WKUP0 Notes: 1. symbolizes a parasitic diode. 2. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC.

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 85 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4 Registers

7.4.1 Port Pi Directi on Register (PDi) (i = 0 to 7, 10 to 13)

Notes: 1. Bits PD5_4 to PD5_7 in the PD5 register are unavailable on this MCU. If it is necessary to set bits PD5_4 to PD5_7, set to 0. When read, the content is 0. 2. Bits PD12_4 to PD12_7 in the PD12 register are unavailable on this MCU. If it is necessary to set bits PD12_4 to PD12_7, set to 0. When read, the content is 0. The PDi register selects whether I/O ports are used for input or output. Each bit in the PDi register corresponds to one port. Address 00E2h (PD0), 00E3h (PD1), 00E6h (PD2), 00E7h (PD3), 00EAh (PD4 (1)), 00EBh (PD5 (2)), 00EEh (PD6), 00EFh (PD7), 00F6h (PD10), 00F7h (PD11), 00FAh (PD12), 00FBh (PD13), B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PDi_7 PDi_6 PDi_5 PDi_4 PDi_3 PDi_2 PDi_1 PDi_0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 PDi_0 Port Pi_0 direction bit 0: Input mode (function as an input port) 1: Output mode (function as an output port) R/W b1 PDi_1 Port Pi_1 direction bit R/W b2 PDi_2 Port Pi_2 direction bit R/W b3 PDi_3 Port Pi_3 direction bit R/W b4 PDi_4 Port Pi_4 direction bit R/W b5 PDi_5 Port Pi_5 direction bit R/W b6 PDi_6 Port Pi_6 direction bit R/W b7 PDi_7 Port Pi_7 direction bit R/W

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 86 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.2 Port Pi Register (Pi) (i = 0 to 7, 10 to 13)

Notes: 1. Bits PD5_4 to PD5_7 in the PD5 register are unavailable on this MCU. If it is necessary to set bits PD5_4 to PD5_7, set to 0. When read, the content is 0. 2. Bits PD12_4 to PD12_7 in the PD12 register are unavailable on this MCU. If it is necessary to set bits PD12_4 to PD12_7, set to 0. When read, the content is 0. Data input and output to and from exte rnal devices are accomplished by read ing and writing to the Pi register. The Pi register consists of a port latch to retain output data and a circuit to read the pin status. The value written in the port latch is output from the pin. Each bit in the Pi register corresponds to one port. Pi_j Bit (i = 0 to 7, 10 to 13, j = 0 to 7) (Port Pi_0 Bit) The pin level of any I/O port which is set to input mode can be read by reading the corresponding bit in this register. The pin level of any I/O port which is set to output mode can be controlled by writing to the corresponding bit in this register. Address 00E0h (P0), 00E1h (P1), 00E4h (P2), 00E5h (P3), 00E8h (P4 (1)), 00E9h (P5 (2)), 00ECh(P6), 00EDh (P7), 00F4h (P10), 00F5h (P11), 00F8h (P12), 00F9h (P13), B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol Pi_7 Pi_6 Pi_5 Pi_4 Pi_3 Pi_2 Pi_1 Pi_0 A f t e r R e s e t XXXXXXXX Bit Symbol Bit Name Function R/W b0 Pi_0 Port Pi_0 bit 0: Low level 1: High level R/W b1 Pi_1 Port Pi_1 bit R/W b2 Pi_2 Port Pi_2 bit R/W b3 Pi_3 Port Pi_3 bit R/W b4 Pi_4 Port Pi_4 bit R/W b5 Pi_5 Port Pi_5 bit R/W b6 Pi_6 Port Pi_6 bit R/W b7 Pi_7 Port Pi_7 bit R/W

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 87 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.3 Timer RA Pin Se lect Register (TRASR)

Note: 1. To use hardware LIN, set 01b to bits TRAIOSEL1 to TRAIOSEL0. To use the I/O pin for timer RA, set the TRASR register. Set this register before setting the timer RA associated registers. Also, do not change the setting value of this register during timer RA operation. Address 0180h B i t b 7b 6b 5 b 4 b 3 b 2 b 1 b 0 Symbol — — — — — — TRAIOSEL1 TRAIOSEL0 A f t e r R e s e t 000 0 0 0 0 0 Bit Symbol Bit Name Function R/W b0 TRAIOSEL0 TRAIO pin select bit b1 b0 0 0: TRAIO pin not used 0 1: P11_4 assigned 1 0: INT4 assigned 1 1: Do not set. R/W b1 TRAIOSEL1 R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b3 — b4 — b5 — b6 — b7 —

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 88 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.4 Timer RB/RC Pin Se lect Register (TRBRCSR)

The register function for timer RB is not implemented. To use the I/O pins for timer RC, set the TRBRCSR register. Set this register before setting the timer RC associated registers. Also, do not change the setting value of the TRCCLKSEL0 bit during timer RC operation. Address 0181h B i t b 7 b 6b 5b 4b 3 b 2 b 1 b 0 Symbol TRCTRGSEL1 TRCTRGSEL0 — TRCCLKSEL0 — — — — A f t e r R e s e t 0 0 0 0 0000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 — b4 TRCCLKSEL0 TRCCLK pin select bit 0: TRCCLK pin not used 1: TRCCLK pin used R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 TRCTRGSEL0 TRCTRG pin select bit b7 b6 0 0: TRCTRG pin not used 0 1: P3_7 assigned 1 0: P4_3 assigned 1 1: P4_4 assigned R/W b7 TRCTRGSEL1 R/W

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 89 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.5 Timer RC Pin Select Register 0 (TRCPSR0)

The TRCPSR0 register selects whether to use the timer RC input. To use the I/O pins for timer RC, set this register. Set the TRCPSR0 register before setting the timer RC associated registers. Also, do not change the setting value of this register during timer RC operation. Address 0182h B i t b 7 b 6b 5 b 4b 3 b 2 b 1b 0 Symbol — — TRCIOBSEL1 TRCIOBSEL0 — —— TRCIOASEL0 A f t e r R e s e t 0 00 00 0 00 Bit Symbol Bit Name Function R/W b0 TRCIOASEL0 TRCIOA pin select bit 0: TRCIOA pin not used 1: TRCIOA pin used R/W b1 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b2 — b3 — b4 TRCIOBSEL0 TRCIOB pin select bit b5 b4 0 0: TRCIOB pin not used 0 1: P4_5 assigned 1 0: P4_6 assigned 1 1: P4_7 assigned R/W b5 TRCIOBSEL1 R/W b6 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b7 —

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 90 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.6 Timer RC Pin Select Register 1 (TRCPSR1)

Notes: 1. When bits TRCIOBSEL1 to TRCIOBSEL 0 in the TRCPSR0 register are se t to 10b (P4_6 a ssigned as TRCIOB pin), P4_6 functions as the TRCIOB pin regardless of the content of the TRCIOCSEL0 bit. 2. When bits TRCIOBSEL1 to TRCIO BSEL0 in the TRCPSR0 register are set to 11b (P4_7 assigned as TRCIOB pin), P4_7 functions as the TRCIOB pin regardless of the content of the TRCIODSEL0 bit. The TRCPSR1 register selects whether to use the timer RC input. To use the I/O pins for timer RC, set this register. Set the TRCPSR1 register before setting the timer RC associated registers. Also, do not change the setting value of this register during timer RC operation. Address 0183h B i t b 7b 6 b 5 b 4b 3b 2 b 1 b 0 Symbol — — — TRCIODSEL0 — —— TRCIOCSEL0 A f t e r R e s e t 0 000 0 000 Bit Symbol Bit Name Function R/W b0 TRCIOCSEL0 TRCIOC pin select bit (1) 0: TRCIOC pin not used 1: P4_6 assigned R/W b1 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b2 — b3 — b4 TRCIODSEL0 TRCIOD pin select bit (2) 0: TRCIOD pin not used 1: P4_7 assigned R/W b5 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b6 — b7 —

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 91 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.7 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0184h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 T RDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit b1 b0 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. R/W b1 TRDIOA0SEL1 R/W b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. R/W b3 TRDIOB0SEL1 R/W b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. R/W b5 TRDIOC0SEL1 R/W b6 TRDIOD0SEL0 TRDIOD0 pin select bit b7 b6 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W b7 TRDIOD0SEL1 R/W

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 92 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.8 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0185h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 T RDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA1SEL0 TRDIOA1 pin select bit b1 b0 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. R/W b1 TRDIOA1SEL1 R/W b2 TRDIOB1SEL0 TRDIOB1 pin select bit b3 b2 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. R/W b3 TRDIOB1SEL1 R/W b4 TRDIOC1SEL0 TRDIOC1 pin select bit b5 b4 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. R/W b5 TRDIOC1SEL1 R/W b6 TRDIOD1SEL0 TRDIOD1 pin select bit b7 b6 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W b7 TRDIOD1SEL1 R/W

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 93 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.9 Timer RG Pin Sel ect Register (TRGPSR)

The TRGPSR register selects which pin is assigned as th e timer RG input/output. To use the I/O pins for timer RG , set this register. Set the TRGPSR register before setting the timer RG associated registers. Also, do not change the setting value of this register during timer RG operation.

7.4.10 UART0 Pin Select Register (U0SR)

The U0SR register selects which pin is assigned as the UART0 input/output. To use the I/O pins for UART0, set this register. Set the U0SR register before setting the UART0 associat ed registers. Also, do not change the setting value of this register during UART0 operation. Address 0187h B i t b 7b 6b 5b 4 b 3 b 2 b 1 b 0 Symbol TRGCLKBSEL0 TRGCLKASEL0 TRGIOBSEL0 TRGIOASEL0 — — — — After Reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 — b4 TRGIOASEL0 TRGIOA pi n select bit 0: TRGIOA pin not used 1: TRGIOA pin used R/W b5 TRGIOBSEL0 TRGIOB pi n select bit 0: TRGIOB pin not used 1: TRGIOB pin used R/W b6 TRGCLKASEL0 TRGCLKA pin select bit 0: TRGCLKA pin not used 1: TRGCLKA pin used R/W b7 TRGCLKBSEL0 TRGCLKB pin select bit 0: TRGCLKB pin not used 1: TRGCLKB pin used R/W Address 0188h B i t b 7 b 6 b 5b 4b 3b 2 b 1 b 0 Symbol — — — CLK0SEL0 — RXD0SEL0 RXD0SEL1 TXD0SEL0 A f t e r R e s e t 000 0 0 0 0 0 Bit Symbol Bit Name Function R/W b0 TXD0SEL0 TXD0 pin select bit 0: TXD0 pin not used 1: TXD0 pin used R/W b1 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b2 RXD0SEL0 RXD0 pin select bit b3 b2 0 0: RXD0 pin not used 0 1: P13_2 assigned 1 0: P11_4 assigned 1 1: Do not set. R/W b3 RXD0SEL1 R/W b4 CLK0SEL0 CLK0 pin select bit 0: CLK0 pin not used 1: CLK0 pin used R/W b5 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b6 — b7 —

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 94 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.11 UART1 Pin Sele ct Register (U1SR)

The U1SR register selects which pin is assigned as the UART1 input/output. To use the I/O pins for UART1, set this register. Set the U1SR register before setting the UART1 associat ed registers. Also, do not change the setting value of this register during UART1 operation. Address 0189h B i t b 7 b 6 b 5b 4b 3b 2b 1b 0 Symbol — — — CLK1SEL0 — RXD1SEL0 — TXD1SEL0 A f t e r R e s e t 0 0 000000 Bit Symbol Bit Name Function R/W b0 TXD1SEL0 TXD1 pin select bit 0: TXD1 pin not used 1: TXD1 pin used R/W b1 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b2 RXD1SEL0 RXD1 pin select bit 0: RXD1 pin not used 1: RXD1 pin used R/W b3 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b4 CLK1SEL0 CLK1 pin select bit 0: CLK1 pin not used 1: CLK1 pin used R/W b5 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b6 — b7 —

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 95 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.12 UART2 Pin Select Register 0 (U2SR0)

The U2SR0 register selects which pin is assigned as the UART2 input/outp ut. To use the I/O pins for UART2, set this register. Set the U2SR0 register before setting the UART2 associated registers. Also, do not change the setting value of this register during UART2 operation. Address 018Ah B i t b 7 b 6b 5 b 4b 3b 2 b 1 b 0 Symbol — — RXD2SEL1 RXD2SEL0 — — TXD2SEL1 TXD2SEL0 A f t e r R e s e t 0 00 000 0 0 Bit Symbol Bit Name Function R/W b0 TXD2SEL0 TXD2/SDA2 pin select bit b1 b0 0 0: TXD2/SDA2 pin not used 0 1: P11_2 assigned 1 0: P11_1 assigned 1 1: Do not set. R/W b1 TXD2SEL1 R/W b2 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b3 — b4 RXD2SEL0 RXD2/SCL2 pin select bit b5 b4 0 0: RXD2/SCL2 pin not used 0 1: P11_1 assigned 1 0: P11_2 assigned 1 1: Do not set. R/W b5 RXD2SEL1 R/W b6 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b7 —

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 96 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.13 UART2 Pin Select Register 1 (U2SR1)

The U2SR1 register selects which pin is assigned as the UART2 input/outp ut. To use the I/O pins for UART2, set this register. Set the U2SR1 register before setting the UART2 associated registers. Also, do not change the setting value of this register during UART2 operation. Address 018Bh B i t b 7b 6b 5 b 4 b 3b 2 b 1 b 0 Symbol — — — CTS2SEL0 — — — CLK2SEL0 A f t e r R e s e t 000 0 00 0 0 Bit Symbol Bit Name Function R/W b0 CLK2SEL0 CLK2 pin select bit 0: CLK2 pin not used 1: CLK2 pin used R/W b1 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b2 — b3 — b4 CTS2SEL0 CTS2 /RTS2 pin select bit 0: CTS2 /RTS2 pin not used 0: CTS2/RTS2 pin used R/W b5 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b6 — b7 —

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 97 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.14 SSU/IIC Pin Select Register (SSUIICSR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 IICSEL SSU/I2C bus switch bit 0: SSU function selected 1: I2C bus function selected R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 — b3 — b4 — b5 — b6 — b7 —

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 98 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.15 Key Input Pin Se lect Register (KISR)

The KISR register selects which pin is assigned as the KIi (i = 1 to 7) input. To use the KIi, set this register. Set the KISR register before setting the KIi associated registers. Also, do not change the setting values in this register during KIi operation. Address 018Dh B i t b 7b 6 b 5 b 4b 3b 2b 1 b 0 Symbol KI7SEL0 KI6SEL0 KISEL0 KI4SEL 0 KI3SEL0 KI2SEL0 KI1SEL0 KI0SEL0 A f t e r R e s e t 00 0 0000 0 Bit Symbol Bit Name Function R/W b0 KI0SEL0 KI0 pin select bit 0: P2_0 assigned 1: P10_0 assigned R/W b1 KI1SEL0 KI1 pin select bit 0: P2_1 assigned 1: P10_1 assigned R/W b2 KI2SEL0 KI2 pin select bit 0: P2_2 assigned 1: P10_2 assigned R/W b3 KI3SEL0 KI3 pin select bit 0: P2_3 assigned 1: P10_3 assigned R/W b4 KI4SEL0 KI4 pin select bit 0: P2_4 assigned 1: P10_4 assigned R/W b5 KI5SEL0 KI5 pin select bit 0: P2_5 assigned 1: P10_5 assigned R/W b6 KI6SEL0 KI6 pin select bit 0: P2_6 assigned 1: P10_6 assigned R/W b7 KI7SEL0 KI7 pin select bit 0: P2_7 assigned 1: P10_7 assigned R/W

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 99 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.16 INT Interrupt Input Pi n Select Register (INTSR)

The INTSR register selects which pin is assigned as the INTi (i = 1 to 7) input. To use the INTi, set this register. Set the INTSR register before setting the INTi associated registers. Also, do not change the setting values in this register during INTi operation.

7.4.17 Port Pi Pull-Up Control Re gister (PiPUR) (i = 0 to 7)

Note: 1. When this bit is set to 1 (pulled up), the pin whose port direction bit is set to 0 (input mode) is pulled up. For ports set to output as I/O pins fo r peripheral functions, the setting valu es of the PiPUR register are invalid and no pull-up resistor is connected. Address 018Eh B i t b 7b 6 b 5 b 4b 3b 2b 1 b 0 Symbol INT7SEL0 INT6SEL0 INT5SEL0 INT4SEL 0 INT3SEL0 INT2SEL0 INT1SEL0 INT0SEL0 A f t e r R e s e t 00 0 0000 0 Bit Symbol Bit Name Function R/W b0 INT0SEL0 INT0 pin select bit 0: P3_0 assigned 1: P11_0 assigned R/W b1 INT1SEL0 INT1 pin select bit 0: P3_1 assigned 1: P11_1 assigned R/W b2 INT2SEL0 INT2 pin select bit 0: P3_2 assigned 1: P11_2 assigned R/W b3 INT3SEL0 INT3 pin select bit 0: P3_3 assigned 1: P11_3 assigned R/W b4 INT4SEL0 INT4 pin select bit 0: P3_4 assigned 1: P11_4 assigned R/W b5 INT5SEL0 INT5 pin select bit 0: P3_5 assigned 1: P11_5 assigned R/W b6 INT6SEL0 INT6 pin select bit 0: P3_6 assigned 1: P11_6 assigned R/W b7 INT7SEL0 INT7 pin select bit 0: P3_7 assigned 1: P11_7 assigned R/W Address 01E0h (P0PUR), 01E1h (P1PUR), 01E2h (P2PUR), 01E3h (P3PUR), 01E4h (P4PUR), 01E5h (P5PUR), 01E6h (P6PUR), 01E7h (P7PUR) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PUi7 PUi6 PUi5 PUi4 PUi3 PUi2 PUi1 PUi0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 PUi0 Port Pi_0 pull-up 0: Not pulled up 1: Pulled up (1) R/W b1 PUi1 Port Pi_1 pull-up R/W b2 PUi2 Port Pi_2 pull-up R/W b3 PUi3 Port Pi_3 pull-up R/W b4 PUi4 Port Pi_4 pull-up R/W b5 PUi5 Port Pi_5 pull-up R/W b6 PUi6 Port Pi_6 pull-up R/W b7 PUi7 Port Pi_7 pull-up R/W

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 100 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.18 Port Pj Pull-Up Control Re gister (PjPUR) (j = 10 to 13)

Note: 1. When this bit is set to 1 (pulled up), the pin whose port direction bit is set to 0 (input mode) is pulled up. For ports set to output as I/O pins fo r peripheral functions, the setting valu es of the PjPUR register are invalid and no pull-up resistor is connected.

7.4.19 Port P10 Drive Capacity Control Register (P10DRR)

Note: 1. Both high-level output and low-level output are set to high drive capacity. The P10DRR register selects whether the drive capacity of the P10 output transistor is set to low or high. The P10DRRi bit (i = 0 to 7) is used to select whether the drive capacity of the output transistor is set to low or high for each pin. Address 01EAh (P10PUR), 01EBh (P11PUR), 01ECh (P12PUR), 01EDh (P13PUR) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PUj7 PUj6 PUj5 PUj4 PUj3 PUi2 PUj1 PUj0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 PUj0 Port Pj_0 pull-up 0: Not pulled up 1: Pulled up (1) R/W b1 PUj1 Port Pj_1 pull-up R/W b2 PUj2 Port Pj_2 pull-up R/W b3 PUj3 Port Pj_3 pull-up R/W b4 PUj4 Port Pj_4 pull-up R/W b5 PUj5 Port Pj_5 pull-up R/W b6 PUj6 Port Pj_6 pull-up R/W b7 PUj7 Port Pj_7 pull-up R/W Address 01F0h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol P10DRR7 P10DRR6 P10DRR5 P10DRR4 P10DRR3 P10DRR2 P10DRR1 P10DRR0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 P10DRR0 P10_0 drive capacity 0: Low 1: High (1) R/W b1 P10DRR1 P10_1 drive capacity R/W b2 P10DRR2 P10_2 drive capacity R/W b3 P10DRR3 P10_3 drive capacity R/W b4 P10DRR4 P10_4 drive capacity R/W b5 P10DRR5 P10_5 drive capacity R/W b6 P10DRR6 P10_6 drive capacity R/W b7 P10DRR7 P10_7 drive capacity R/W

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 101 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.20 Port P11 Drive Capacity Control Register (P11DRR)

Note: 1. Both high-level output and low-level output are set to high drive capacity. The P11DRR register selects whether the drive capacity of the P11 output transistor is set to low or high. The P11DRRi bit (i = 0 to 7) is used to select whether the drive capacity of the output transistor is set to low or high for each pin.

7.4.21 Input Threshold Cont rol Register 0 (VLT0)

The VLT0 register selects the voltage level of the inpu t threshold values for ports P0 to P3. Bits VLT00 to VLT07 are used to select the input threshold values among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC). Address 01F1h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol P11DRR7 P11DRR6 P11DRR5 P11DRR4 P11DRR3 P11DRR2 P11DRR1 P11DRR0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 P11DRR0 P11_0 drive capacity 0: Low 1: High (1) R/W b1 P11DRR1 P11_1 drive capacity R/W b2 P11DRR2 P11_2 drive capacity R/W b3 P11DRR3 P11_3 drive capacity R/W b4 P11DRR4 P11_4 drive capacity R/W b5 P11DRR5 P11_5 drive capacity R/W b6 P11DRR6 P11_6 drive capacity R/W b7 P11DRR7 P11_7 drive capacity R/W Address 01F5h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VLT07 VLT06 VLT05 VLT04 VLT03 VLT02 VLT01 VLT00 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 VLT00 P0 input level select bit b1 b0 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b1 VLT01 R/W b2 VLT02 P1 input level select bit b3 b2 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b3 VLT03 R/W b4 VLT04 P2 input level select bit b5 b4 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b5 VLT05 R/W b6 VLT06 P3 input level select bit b7 b6 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b7 VLT07 R/W

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 102 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.22 Input Threshold Cont rol Register 1 (VLT1)

The VLT1 register selects the voltage level of the inpu t threshold values for ports P4 to P7. Bits VLT10 to VLT17 are used to select the input threshold values among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC). Address 01F6h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VLT17 VLT16 VLT15 VLT14 VLT13 VLT12 VLT11 VLT10 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 VLT10 P4 input level select bit b1 b0 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b1 VLT11 R/W b2 VLT12 P5_0 and P5_3 input level select bit b3 b2 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b3 VLT13 R/W b4 VLT14 P6 input level select bit b5 b4 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b5 VLT15 R/W b6 VLT16 P7 input level select bit b7 b6 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b7 VLT17 R/W

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 103 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.4.23 Input Threshold Cont rol Register 2 (VLT2)

The VLT2 register selects th e voltage level of the input threshold values for ports P10 to P13. Bits VLT20 to VLT27 are used to select the input threshold values among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC). Address 01F7h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VLT17 VLT16 VLT15 VLT14 VLT13 VLT12 VLT11 VLT10 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 VLT20 P10 input level select bit b1 b0 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b1 VLT21 R/W b2 VLT22 P11 input level select bit b3 b2 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b3 VLT23 R/W b4 VLT24 P12_0 to P12_3 input level select bit b5 b4 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b5 VLT25 R/W b6 VLT26 P13 input level select bit b7 b6 0 0: 0.50 × VCC 0 1: 0.35 × VCC 1 0: 0.70 × VCC 1 1: Do not set. R/W b7 VLT27 R/W

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 104 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.5 Port Settings

Tables 7.5 to 7.23 list the port settings. X: 0 or 1 Note: 1. Pulled up by setting the corresponding bit in the P0PUR register to 1. Table 7.5 Port P0 Pin Register PD0 LSE0 ADINSEL — FunctionBit PD0_i LSEi CH ADGSEL 21010 Port P0_0 SEG0 AN4 i = 0 0 0 XXXXX Input port (1) 1 0 X X X X X Output port X 1 XXXXX LCD drive control output (SEG0) 0 0 10000 A/D converter input (AN4) (1) Port P0_1 SEG1 AN5 i = 1 0 0 XXXXX Input port (1) 1 0 X X X X X Output port X 1 XXXXX LCD drive control output (SEG1) 0 0 10100 A/D converter input (AN5) (1) Port P0_2 SEG2 AN6 i = 2 0 0 XXXXX Input port (1) 1 0 X X X X X Output port X 1 XXXXX LCD drive control output (SEG2) 0 0 11000 A/D converter input (AN6) (1) Port P0_3 SEG3 AN7 i = 3 0 0 XXXXX Input port (1) 1 0 X X X X X Output port X 1 XXXXX LCD drive control output (SEG3) 0 0 11100 A/D converter input (AN7) (1) Port P0_4 SEG4 AN8 i = 4 0 0 XXXXX Input port (1) 1 0 X X X X X Output port X 1 XXXXX LCD drive control output (SEG4) 0 0 00001 A/D converter input (AN8) (1) Port P0_5 SEG5 AN9 i = 5 0 0 XXXXX Input port (1) 1 0 X X X X X Output port X 1 XXXXX LCD drive control output (SEG5) 0 0 00101 A/D converter input (AN9) (1) Port P0_6 SEG6 AN10 i = 6 0 0 XXXXX Input port (1) 1 0 X X X X X Output port X 1 XXXXX LCD drive control output (SEG6) 0 0 01001 A/D converter input (AN10) (1) Port P0_7 SEG7 AN11 i = 7 0 0 XXXXX Input port (1) 1 0 X X X X X Output port X 1 XXXXX LCD drive control output (SEG7) 0 0 01101 A/D converter input (AN11) (1)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 105 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1 Note: 1. Pulled up by setting the corresponding bit in the P1PUR register to 1. Table 7.6 Port P1 Pin Register PD1 LSE1 ADINSEL — FunctionBit PD1_i LSEi+8 CH ADGSEL 21010 Port P1_0 SEG8 AN12 i = 0 0 0 XXXXX Input port (1) 1 0 X X X X X Output port X 1 XXXXX LCD drive control output (SEG8) 0 0 10001 A/D converter input (AN12) (1) Port P1_1 SEG9 AN13 i = 1 0 0 XXXXX Input port (1) 1 0 X X X X X Output port X 1 XXXXX LCD drive control output (SEG9) 0 0 10101 A/D converter input (AN13) (1) Port P1_2 SEG10 AN14 i = 2 0 0 XXXXX Input port (1) 1 0 X X X X X Output port X 1 XXXXX LCD drive control output (SEG10) 0 0 11001 A/D converter input (AN14) (1) Port P1_3 SEG11 AN15 i = 3 0 0 XXXXX Input port (1) 1 0 X X X X X Output port X 1 XXXXX LCD drive control output (SEG11) 0 0 11101 A/D converter input (AN15) (1) Port P1_4 SEG12 i = 4

00 Input port (1)

X1 LCD drive control output (SEG12) Port P1_5 SEG13 i = 5 X1 LCD drive control output (SEG13) Port P1_6 SEG14 i = 6 X1 LCD drive control output (SEG14) Port P1_7 SEG15 i = 7 X1 LCD drive control output (SEG15)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 106 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P2PUR register to 1. Table 7.7 Port P2 Pin Register PD2 LSE2 KISR KIEN KIEN1 — FunctionBit PD2_i LSEi+16 KIiSEL0 KIiEN KIiEN Port P2_0 SEG16 KI0 i = 0 00XX — Input port (1) 1 0 X X — Output port X1 XX — LCD drive control output (SEG16) 00 01 — KI0 input (1) Port P2_1 SEG17 KI1 i = 1 00XX — Input port (1) 1 0 X X — Output port X1 XX — LCD drive control output (SEG17) 00 01 — KI1 input (1) Port P2_2 SEG18 KI2 i = 2 00XX — Input port (1) 1 0 X X — Output port X1 XX — LCD drive control output (SEG18) 00 01 — KI2 input (1) Port P2_3 SEG19 KI3 i = 3 00XX — Input port (1) 1 0 X X — Output port X1 XX — LCD drive control output (SEG19) 00 01 — KI3 input (1) Port P2_4 SEG20 KI4 i = 4 00X — X Input port (1) 1 0 X — X Output port X1 X — X LCD drive control output (SEG20) 00 0 — 1 KI4 input (1) Port P2_5 SEG21 KI5 i = 5 00X — X Input port (1) 1 0 X — X Output port X1 X — X LCD drive control output (SEG21) 00 0 — 1 KI5 input (1) Port P2_6 SEG22 KI6 i = 6 00X — X Input port (1) 1 0 X — X Output port X1 X — X LCD drive control output (SEG22) 00 0 — 1 KI6 input (1) Port P2_7 SEG23 KI7 i = 7 00X — X Input port (1) 1 0 X — X Output port X1 X — X LCD drive control output (SEG23) 00 0 — 1 KI7 input (1)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 107 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P3PUR register to 1. Table 7.8 Port P3 Pin Register PD3 LSE3 INTSR INTEN INTEN1 ADMOD TRBRCSR TRCMR TRCCR2 FunctionBit PD3_i LSEi+24 INTiSEL0 INTiEN INTiEN ADCAP1 ADCAP TRCTRG SEL1 TRCTRG SEL0 PWM2 TCEG1 TCEG0 Port P3_0 SEG24 INT0 i = 0 X 1 X X ——— —— LCD drive control output (SEG24) Port P3_1 SEG25 INT1 i = 1 X 1 X X ———————— LCD drive control output (SEG25) Port P3_2 SEG26 INT2 i = 2 X 1 X X ——— —— LCD drive control output (SEG26) Port P3_3 SEG27 INT3 i = 3 X 1 X X ———————— LCD drive control output (SEG27) Port P3_4 SEG28 INT4 i = 4 X1X — X — — — — LCD drive control output (SEG28) Port P3_5 SEG29 INT5 i = 5 X 1 X — X ——————— LCD drive control output (SEG29) Port P3_6 SEG30 INT6 i = 6 X1X — X — — — — LCD drive control output (SEG30) Port P3_7 SEG31 INT7 ADTRG TRCTRG i = 7 00X — XXXXXXXX Input port (1) 1 0 X — X X X X X X X X Output port X1X —1XXXXXXX LCD drive control output (SEG31) 000—1XXXXXXX INT7 input (1) 000—111XXXXX ADTRG input (1) 00X — XXX010 0 1 PWM2 mode TRCTRG input (1)—1 X

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 108 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Notes: 1. Pulled up by setting the corresponding bit in the P4PUR register to 1. 2. N-channel open-drain output by setting the MCH bit in the U1C0 register to 1. Table 7.9 Ports P4_0 to 4_2 Pin Register PD4 LSE4 U1SR U1MR — FunctionBit PD4_i LSEi+32 CLK1SEL0 RXD1SEL0 TXD1SEL0 SMD2 SMD1 SMD0 CKDIR Port P4_0 SEG32 TXD1 i = 0 00 — — 0XXXX Input port (1) 0 0 — — 0 X X X X Output port X1 — — 0XXXX LCD drive control output (SEG32) 00 — — 1 001 X TXD1 output (2) 10X 110 Port P4_1 SEG33 RXD1 i = 1 0 0—X—X X X X Input port (1) 0 0 — X — X X X X Output port X 1—X—X X X X LCD drive control output (SEG33) 00 — 1 — XXXX RXD1 input (1) Port P4_2 SEG34 CLK1 i = 2 000 — — XXXX Input port (1) 0 0 0 — — X X X X Output port X10 — — XXXX LCD drive control output (SEG34) 001 — — XXX1 CLK1 (external clock) input (1) X01 — — 0010 CLK1 (internal clock) output (2)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 109 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P4PUR register to 1. Table 7.10 Ports P4_3 and 4_4 Pin Register PD4 LSE4 TRBRCSR TRCCR1 TRCMR TRCCR2 — FunctionBit PD4_i LSE35 TRCTRG SEL1 TRCTRG SEL0 TRCCLK SEL0 TCK2 TCK1 TCK0 PWM2 TCEG1 TCEG0 Port P4_3 SEG35 TRCCLK TRCTRG i = 3 0 0 XXX X X X X X X Input port (1) 1 0 XXX X X X X X X Output port X 1 XXX X X X X X X LCD drive control output (SEG35) 0X X X 1 10 1 XXX TRCCLK input (1) 00 1 0 XX XX0 01 PWM2 mode TRCTRG input (1) Pin Register PD4 LSE4 TRBRCSR TRCPSR0 TRCOER TRCMR TRCIOR0 TRCCR2 Function Bit PD4_i LSE36 TRCTRG SEL1 TRCTRG SEL0 TRCIOA SEL0 EA PWM2 IOA2 IOA1 IOA0 TCEG1 TCEG Port P4_4 SEG36 TRCIOA TRCTRG i = 4

00 X X 0 XXX XXXX Input port (1)

10 X X 0 XXX XXXX Output port

X1 X X 0 XXX XXXX LCD drive control output (SEG36) X0 X X 1 01 00 1 X X Timer waveform (output compare function)01 X X X

00 X X 1 X1 1 XXXX Timer mode (input capture

function) (1) 00 1 1 XX0XXX 01 PWM2 mode TRCTRG input (1)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 110 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P4PUR register to 1. Table 7.11 Ports P4_5 to 4_7 Pin Register PD4 LSE4 TRCPSR0 TRCOER TRCMR TRCIOR0 —F u n c t i o nBit PD4_i LSE37 TRCIOBSEL EB PWM2 PWMB IOB 10 210 Port P4_5 SEG37 TRCIOB i = 5

00 Other than 01b X X X XXX Input port (1)

10 Other than 01b X X X XXX O u t p u t p o r t

X1 Other than 01b X X X XXX LCD drive control output (SEG37) X001 0 0 X XXX PWM2 mode waveform output X001 0 1 1 XXX PWM mode waveform output X001 0 1 0 001 Timer waveform output (output compare function)01X

0001 X 1 0 1XX Timer mode (input

capture function) (1) Pin Register PD4 LSE4 TRCPSR0 TRCPSR1 TRCOER TRCMR TRCIOR0 TRCIOR1 FunctionBit PD4_i LSE38 TRCIOBSEL TRCIOC SEL0 EB EC PWM2 PWMB PWMC IOB IOC 10 210210 Port P4_6 SEG38 TRCIOB TRCIOC i = 6

00 Other than 10b 0XXXXXXXXXXX Input port (1)

10 Other than 10b 0XXXXXXXXXXX O u t p u t p o r t

X1 Other than 10b 0XXXXXXXXXXX LCD drive control output (SEG38) X010X0X0XXXXXXXX PWM2 mode waveform output X010X0X11XXXXXXX PWM mode waveform output X010X0X10X 001XXX Timer waveform output (output compare function)01XXXX 00100XX10X1XXXXX Timer mode (input capture function) (1) X0 Other than 10b 1X01X1XXXXXX PWM mode waveform output X0 Other than 10b 1X01X0 XXX001 Timer waveform (output compare function)XXX01X

00 Other than 10b 1XX1X0XXX1XX Timer mode (input

capture function) (1) Pin Register PD4 LSE4 TRCPSR0 TRCPSR1 TRCOER TRCMR TRCIOR0 TRCIOR1 FunctionBit PD4_i LSE39 TRCIOBSEL TRCIOD SEL0 EB ED PWM2 PWMB PWMD IOB IOD 10 210210 Port P4_7 SEG39 TRCIOB TRCIOD i = 7

00 Other than 11b 0XXXXXXXXXXX Input port (1)

10 Other than 11b 0XXXXXXXXXXX O u t p u t p o r t

X1 Other than 11b 0XXXXXXXXXXX LCD drive control output (SEG39) X011X0X0XXXXXXXX PWM2 mode waveform output X011X0X11XXXXXXX PWM mode waveform output X011X0X10X 001XXX Timer waveform output (output compare function)01XXXX 00110XX10X1XXXXX Timer mode (input capture function) (1) X0 Other than 11b 1X01X1XXXXXX PWM mode waveform output X0 Other than 11b 1X01X0 XXX001 Timer waveform output (output compare function)XXX01X

00 Other than 11b 1XX1X0XXX1XX Timer mode (input

capture function) (1)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 111 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P5PUR register to 1. Table 7.12 Port P5 Pin Register PD5 LSE5 — FunctionBit PD5_i LSEi+40 Port P5_0 SEG40 i = 0

X1 LCD drive control output (SEG40) Port P5_1 SEG41 i = 1 X1 LCD drive control output (SEG41) Port P5_2 SEG42 i = 2 X1 LCD drive control output (SEG42) Port P5_3 SEG43 i = 3 X1 LCD drive control output (SEG43)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 112 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P6PUR register to 1. Table 7.13 Ports P6_0 to P6_3 Pin Register PD6 LSE5 TRDPSR0 TRDOER1 TRDFCR TRDIORA0 FunctionBit PD6_i LSE44 TRDIOA0SEL EA0 CMD1 CMD0 STCLK PWM3 IOA2 IOA1 IOA010 Port P6_0 SEG44 TRDIOA0 TRDCLK i = 0

00 Other than

X XXXXX X X Input port (1)

10 X XXXXX X X O u t p u t p o r t

01b X XXXXX X X LCD drive control output (SEG44) 00 0 1 X 00011 X X Timer mode (input capture function) (1) 0 0 0 1 X XX 1 1000 External clock input (TRDCLK) (1) X0 0 1 0 0000 X X X PWM3 mode waveform output X0 0 1 0 0001 001 Timer mode waveform output (output compare function)01X Pin Register PD6 LSE5 TRDPSR0 TRDOER1 TRDFCR TRDPMR TRDIORB0 FunctionBit PD6_i LSE45 TRDIOB0SEL EB0 CMD1 CMD0 PWM3 PWMB0 IOB2 IOB1 IOB010 Port P6_1 SEG45 TRDIOB0 i = 1 X XXXXX X X Input port (1) 01b X XXXXX X X LCD drive control output (SEG45) 00 0 1 X 00101 X X Timer mode (input capture function) (1) X0 0 1 0 1XXXX X X Complementary PWM mode waveform output X0 0 1 0 01XX X X X Reset synchronous PWM mode waveform output X 0 0 1 0 0 0 0 X X X X PWM3 mode waveform output X0 0 1 0 0011 X X X P W M m ode waveform output X0 0 1 0 0010 001 Timer mode waveform output (output compare function)01X Pin Register PD6 LSE5 TRDPSR0 TRDOER1 TRDFCR TRDPMR TRDIORC0 FunctionBit PD6_i LSE46 TRDIOC0SEL EC0 CMD1 CMD0 PWM3 PWMC0 IOC2 IOC1 IOC010 Port P6_2 SEG46 TRDIOC0 i = 2 X XXXXX X X Input port (1) 01b X XXXXX X X LCD drive control output (SEG46) 00 0 1 X 00101 X X Timer mode (input capture function) (1) X0 0 1 0 1XXXX X X Complementary PWM mode waveform output X0 0 1 0 01XX X X X Reset synchronous PWM mode waveform output X0 0 1 0 0011 X X X P W M m ode waveform output X0 0 1 0 0010 001 Timer mode waveform output (output compare function)01X Pin Register PD6 LSE5 TRDPSR0 TRDOER1 TRDFCR TRDPMR TRDIORC0 FunctionBit PD6_i LSE47 TRDIOD0SEL ED0 CMD1 CMD0 PWM3 PWMD0 IOD2 IOD1 IOD010 Port P6_3 SEG47 TRDIOD0 i = 3 X XXXXX X X Input port (1) 01b X XXXXX X X LCD drive control output (SEG47) 00 0 1 X 00101 X X Timer mode (input capture function) (1) X0 0 1 0 1XXXX X X Complementary PWM mode waveform output X0 0 1 0 01XX X X X Reset synchronous PWM mode waveform output X0 0 1 0 0011 X X X P W M m ode waveform output X0 0 1 0 0010 001 Timer mode waveform output (output compare function)01X

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 113 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P6PUR register to 1. Table 7.14 Ports P6_4 to P6_7 Pin Register PD6 LSE6 TRDPSR1 TRDOER1 TRDFCR TRDIORA1 FunctionBit PD6_i LSE48 TRDIOA1SEL EA1 CMD1 CMD0 PWM3 — IOA2 IOA1 IOA010 Port P6_4 SEG48 TRDIOA1 i = 4

X XXX X X X Input port (1) 1 0 X X X X X X X Output port X1 Other than 01b X XXX X X X LCD drive control output (SEG48) 00 0 1 X 001 1 X X Timer mode (input capture function) (1) X0 0 1 0 1XX X X X Complementary PWM mode waveform output X0 0 1 0 01X X X X Reset synchronous PWM mode waveform output X0 0 1 0 001 001 Timer mode waveform output (output compare function)01X Pin Register PD6 LSE6 TRDPSR1 TRDOER1 TRDFCR TRDPMR TRDIORB1 FunctionBit PD6_i LSE49 TRDIOB1SEL EB1 CMD1 CMD0 PWM3 PWMB1 IOB2 IOB1 IOB010 Port P6_5 SEG49 TRDIOB1 i = 5 X XXXXX X X Input port (1) 01b X XXXXX X X LCD drive control output (SEG49) 00 0 1 X 00101 X X Timer mode (input capture function) (1) X0 0 1 0 1XXXX X X Complementary PWM mode waveform output X0 0 1 0 01XX X X X Reset synchronous PWM mode waveform output X0 0 1 0 0011 X X X P W M m ode waveform output X0 0 1 0 0010 001 Timer mode waveform output (output compare function)01X Pin Register PD6 LSE6 TRDPSR1 TRDOER1 TRDFCR TRDPMR TRDIORC1 FunctionBit PD6_i LSE50 TRDIOC1SEL EC1 CMD1 CMD0 PWM3 PWMC1 IOC2 IOC1 IOC010 Port P6_6 SEG50 TRDIOC1 i = 6 X XXXXX X X Input port (1)

00 X XXXXX X X O u t p u t p o r t

01b X XXXXX X X LCD drive control output (SEG50) 00 0 1 X 00101 X X Timer mode (input capture function) (1) X0 0 1 0 1XXXX X X Complementary PWM mode waveform output X0 0 1 0 01XX X X X Reset synchronous PWM mode waveform output X0 0 1 0 0011 X X X P W M m ode waveform output X0 0 1 0 0010 001 Timer mode waveform output (output compare function)01X Pin Register PD6 LSE6 TRDPSR1 TRDOER1 TRDFCR TRDPMR TRDIORD1 FunctionBit PD6_i LSE51 TRDIOC1SEL ED1 CMD1 CMD0 PWM3 PWMD1 IOD2 IOD1 IOD010 Port P6_7 SEG51 TRDIOD1 i = 7 X XXXXX X X Input port (1) 01b X XXXXX X X LCD drive control output (SEG51) 00 0 1 X 00101 X X Timer mode (input capture function) (1) X0 0 1 0 1XXXX X X Complementary PWM mode waveform output X0 0 1 0 01XX X X X Reset synchronous PWM mode waveform output X0 0 1 0 0011 X X X P W M m ode waveform output X0 0 1 0 0010 001 Timer mode waveform output (output compare function)01X

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 114 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P6PUR or P7PUR register to 1. Table 7.15 Port P7 Pin Register PD7 LSE6/ LSE7 LCR0 — Function Bit PD7_i LSEi+52 LDTY 210 Port P7_0 SEG52 COM7 i = 0 0 0 XXX Input port (1) 1 0 X X X Output port X 1 0 X X LCD drive control output (SEG52) 1 0 0 LCD drive control output (COM7) Port P7_1 SEG53 COM6 i = 1 0 0 XXX Input port (1) 1 0 X X X Output port X 1 0 X X LCD drive control output (SEG53) 1 0 0 LCD drive control output (COM6) Port P7_2 SEG54 COM5 i = 2 0 0 XXX Input port (1) 1 0 X X X Output port X 1 0 X X LCD drive control output (SEG54) 1 0 0 LCD drive control output (COM5) Port P7_3 SEG55 COM4 i = 3 0 0 XXX Input port (1) 1 0 X X X Output port X 1 0 X X LCD drive control output (SEG55) 1 0 0 LCD drive control output (COM4) Port P7_4 COM3 i = 4

X 1 LCD drive control output (COM3) Port P7_5 COM2 i = 5 X 1 LCD drive control output (COM2) Port P7_6 COM1 i = 6 X 1 LCD drive control output (COM1) Port P7_7 COM0 i = 7 X 1 LCD drive control output (COM0)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 115 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P10PUR register to 1. Table 7.16 Ports P10_0 to P10_3 Pin Register PD10 KISR KIEN TRDPSR0 TRDOER1 TRDFCR TRDIORA0 FunctionBit PD10_i KIiSEL0 KIiEN TRDIOA0SEL EA0 CMD1 CMD0 STCLK PWM3 IOA2 IOA1 IOA010 Port P10_0 (TRDIOA0 TRDCLK KI0) i = 0 0X X Other than 10b X XXXX X X X Input port (1) 1X X X XXXX X X X O u t p u t p o r t 01 1 Other than 10b X XXXX X X X KI0 input (1) 0X X 1 0 X 0001 1 X X Timer mode (input capture function) (1) 0X X 1 0 X XX11 0 0 0 External clock input (TRDCLK) (1) XX X 1 0 0 0000 X X X P W M 3 m o d e w a v e f o r m o u t p u t XX X 1 0 0 0001 001 Timer mode waveform output (output compare function)01X Pin Register PD10 KISR KIEN TRDPSR0 TRDOER1 TRDFCR TRDPMR TRDIORB0 FunctionBit PD10_i KIiSEL0 KIiEN TRDIOB0SEL EB0 CMD1 CMD0 PWM3 PWMB0 IOB2 IOB1 IOB010 Port P10_1 (TRDIOB0 KI1) i = 1 0X X Other than 10b X XXXX X X X Input port (1) 1X X X XXXX X X X O u t p u t p o r t 01 1 Other than 10b X XXXX X X X KI1 input (1) 0X X 1 0 X 0010 1 X X Timer mode (input capture function) (1) XX X 1 0 0 1XXX X X X Complementary PWM mode waveform output XX X 1 0 0 01XX X X X Reset synchronous PWM mode waveform output X X X 1 0 0 0 0 0 X X X X PWM3 mode waveform output XX X 1 0 0 0011 X X X P W M m ode waveform output XX X 1 0 0 0010 001 Timer mode waveform output (output compare function)01X Pin Register PD10 KISR KIEN TRDPSR0 TRDOER1 TRDFCR TRDPMR TRDIORC0 FunctionBit PD10_i KIiSEL0 KIiEN TRDIOC0SEL EB0 CMD1 CMD0 PWM3 PWMC0 IOC2 IOC1 IOC010 Port P10_2 (TRDIOC0 KI2) i = 2 0X X Other than 10b X XXXX X X X Input port (1) 1X X X XXXX X X X O u t p u t p o r t 01 1 Other than 10b X XXXX X X X KI2 input (1) 0X X 1 0 X 0010 1 X X Timer mode (input capture function) (1) XX X 1 0 0 1XXX X X X Complementary PWM mode waveform output XX X 1 0 0 01XX X X X Reset synchronous PWM mode waveform output XX X 1 0 0 0011 X X X P W M m ode waveform output XX X 1 0 0 0010 001 Timer mode waveform output (output compare function)01X Pin Register PD10 KISR KIEN TRDPSR0 TRDOER1 TRDFCR TRDPMR TRDIORD0 FunctionBit PD10_i KIiSEL0 KIiEN TRDIOD0SEL ED0 CMD1 CMD0 PWM3 PWMD0 IOD2 IOD1 IOD010 Port P10_3 (TRDIOD0 KI3) i = 3 0X X Other than 10b X XXXX X X X Input port (1) 1X X X XXXX X X X O u t p u t p o r t 01 1 Other than 10b X XXXX X X X KI3 input (1) 0X X 1 0 X 0010 1 X X Timer mode (input capture function) (1) XX X 1 0 0 1XXX X X X Complementary PWM mode waveform output XX X 1 0 0 01XX X X X Reset synchronous PWM mode waveform output XX X 1 0 0 0011 X X X P W M m ode waveform output XX X 1 0 0 0010 001 Timer mode waveform output (output compare function)01X

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 116 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P10PUR register to 1. Table 7.17 Ports P10_4 to P10_7 Pin Register PD10 KISR KIEN1 TRDPSR1 TRDOER1 TRDFCR TRDIORA1 FunctionBit PD10_i KIiSEL0 KIiEN TRDIOA1SEL EA1 CMD1 CMD0 PWM3 — IOA2 IOA1 IOA010 Port P10_4 (TRDIOA1 KI4) i = 4 0X X Other than 10b X XXX X X X Input port (1) 1X X X XXX X X X O u t p u t p o r t 01 1 Other than 10b X XXX X X X KI4 input (1) 0X X 1 0 X 001 1 X X Timer mode (input capture function) (1) X X X10 0 1 X X XXX Complementary PWM mode waveform output X X X10 0 0 1 X XXX Reset synchronous PWM mode waveform output XX X 1 0 0 001 001 Timer mode waveform output (output compare function)01X Pin Register PD10 KISR KIEN TRDPSR1 TRDOER1 TRDFCR TRDPMR TRDIORA1 FunctionBit PD10_i KIiSEL0 KIiEN TRDIOB1SEL EB1 CMD1 CMD0 PWM3 PWMB1 IOB2 IOB1 IOB010 Port P10_5 (TRDIOB1 KI5) i = 5 0X X Other than 10b X XXXX X X X Input port (1) 1X X X XXXX X X X O u t p u t p o r t 01 1 Other than 10b X XXXX X X X KI5 input (1) 0X X 1 0 X 0010 1 X X Timer mode (input capture function) (1) XX X 1 0 0 1XXX X X X Complementary PWM mode waveform output XX X 1 0 0 01XX X X X Reset synchronous PWM mode waveform output XX X 1 0 0 0011 X X X P W M m ode waveform output XX X 1 0 0 0010 001 Timer mode waveform output (output compare function)01X Pin Register PD10 KISR KIEN TRDPSR1 TRDOER1 TRDFCR TRDPMR TRDIORC1 FunctionBit PD10_i KIiSEL0 KIiEN TRDIOC1SEL EC1 CMD1 CMD0 PWM3 PWMC1 IOC2 IOC1 IOC010 Port P10_6 (TRDIOC1 KI6) i = 6 0X X Other than 10b X XXXX X X X Input port (1) 1X X X XXXX X X X O u t p u t p o r t 01 1 Other than 10b X XXXX X X X KI6 input (1) 0X X 1 0 X 0010 1 X X Timer mode (input capture function) (1) XX X 1 0 0 1XXX X X X Complementary PWM mode waveform output XX X 1 0 0 01XX X X X Reset synchronous PWM mode waveform output XX X 1 0 0 0011 X X X P W M m ode waveform output XX X 1 0 0 0010 001 Timer mode waveform output (output compare function)01X Pin Register PD10 KISR KIEN TRDPSR1 TRDOER1 TRDFCR TRDPMR TRDIORC1 FunctionBit PD10_i KIiSEL0 KIiEN TRDIOD1SEL ED1 CMD1 CMD0 PWM3 PWMD1 IOD2 IOD1 IOD010 Port P10_7 (TRDIOD1 KI7) i = 7 0X X Other than 10b X XXXX X X X Input port (1) 1X X X XXXX X X X O u t p u t p o r t 01 1 Other than 10b X XXXX X X X KI7 input (1) 0X X 1 0 X 0010 1 X X Timer mode (input capture function) (1) XX X 1 0 0 1XXX X X X Complementary PWM mode waveform output XX X 1 0 0 01XX X X X Reset synchronous PWM mode waveform output XX X 1 0 0 0011 X X X P W M m ode waveform output XX X 1 0 0 0010 001 Timer mode waveform output (output compare function)01X

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 117 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Notes: 1. Pulled up by setting the corresponding bit in the P11PUR register to 1. 2. Output drive capacity high by setting the corresponding bit in the P10DRR register to 1. 3. N-channel open-drain output by setting the SCKOS bit in the SSMR2 register to 1. 4. N-channel open-drain output by setting the NODC bit in the U2SMR3 register to 1. 5. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output) and setting the BIDE bit to 0 (standard mode). 6. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1. 7. Synchronous serial comm unication unit (refer to Table 27.4 Association between Communication Modes and I/O Pins). Table 7.18 Ports P11_0 and P11_1 Pin Register PD11 INTSR INTEN INTCMP ACMR SSUIICSR ICCR1 SSU Associated Register (7) U2SR1 U2MR Function Bit PD11_i INTi SEL0 INTiEN INT1 CP0 CM10E IICSEL ICE SSCK output control SSCK input control CLK2SEL0 SMD CKDIR210 Port P11_0 SCL SSCK (CLK2 INT0) IVREF1 LVCOUT1 i = 0 0XXX 0 0X 0 0 0X X X X Input port (1)

10 X X

1XXX 0 0X 0 0 0X X X X Output port (2) 0XXX 0 1 1 X X 0 X X X X SCL input/output (2) 0XXX 0 0 X 0 1 0 X X X X SSCK input (1) 0XXX 0 0 X 1 0 0 X X X X SSCK output (2, 5) 0XXX 0 0X 0 0 1X X X 1 CLK2 input (1) 0XXX 0 0X 0 0 1 001 0 CLK2 output (2, 6) 011X0 0X 0 0 0X X X X INT0 input (1) input (IVREF1)10 X X XXX X 1 0X 0 0 0X X X X Comparator A1 output (LVCOUT1) (2)10 X X Pin Register PD11 INTSR INTEN INTCMP ACMR SSUIICSR SSU Associated Register (7) U2SR0 U2MR U2SMR Function Bit PD11_i INTi SEL0 INTiEN INT1 CP0 CM20E IICSEL SSI output control SSI input control RXD2 SEL TXD2 SEL SMD IICM 1010 2 1 0 Port P11_1 SSI (RXD2 SCL2 TXD2 SDA2 INT1) IVCMP1 LVCOUT2 i = 1 0XXX 0 X 0 0 X X Other than 10b XXX X Input port (1) 1XXX 0 X 0 0 X X X X X X Output port (2) 0XXX 0 0 0 1 X X X X X X SSI input (1) XXX X 0 0 1 0 X X X X X X SSI output (2, 5) 0XXX 0 X 0 0 0 1 X X X 0 RXD2 input (1)

0 X X X 0 X 0 0 0 1 010 1 SCL2

input/output (2, 6) XXX X 0 X 0 0 X X 1 0 001 0 TXD2 output (2, 6) 10X 0 110 0

0 X X X 0 X 0 0 X X 1 0 010 1 SDA2

input/output (2, 6) 0 1100 X 0 0 X X Other than 10b XXX X INT1 input (1) 0 0110 X 0 0 X X X X X X Comparator B1 input (IVCMP1) 0XXX 1 X 0 0 X X X X X X Comparator A2 output (LVCOUT2) (2)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 118 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Notes: 1. Pulled up by setting the corresponding bit in the P11PUR register to 1. 2. Output drive capacity high by setting the corresponding bit in the P11DRR register to 1. 3. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output). 4. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1. 5. N-channel open-drain output by setting the CSOS bit in the SSMR2 register to 1. 6. Synchronous serial communication unit (refer to Table 27.4 Association between Communication Modes and I/O Pins). Table 7.19 Ports P11_2 and P11_3 Pin Register PD11 INTSR INTEN INTCMP — SSUIICSR ICCR1 SSU Associated Register (6) U2SR0 U2MR U2SMR Function Bit PD11_i INTi SEL0 INTiEN INT3 CP0 —I I C S E L I C E SSI output control SSI input control RXD2 SEL TXD2 SEL SMD IICM 1010 2 1 0 Port P11_2 SDA SSO (RXD2 SCL2 TXD2 SDA2 INT2 IVREF3 i = 2 0XX X— 1 0 X X X X Other than 01b XXX 0 Input port (1)

0 X X X — 0 X 0 0 X X XXX 0

1XX X— 1 0 X X X X Other than 01b XXX 0 Output port (2)

1 X X X — 0 X 0 0 X X XXX 0

0XX X— 1 1 X X X X Other than 01b XXX 0 SDA input/output (2)

0 X X X — 0 X 0 1 X X XXX 0 SSO input (1)

0 X X X — 0 X 1 0 X X XXX 0 SSO output (2, 3)

0XX X— RXD2 input (1) 0X 0 0 0XX X— input/output (2, 4) 0X 0 0 XXX— 1 0 X X XX01 001 TXD2 output (2, 4) XXX— 0 X 0 0 10X 110 0XX X— input/outpu (2, 4)0X 0 0

011 X— X X 0 0 X X 0 1 XXX X INT2 input (1)

0XX 1— X X 0 0 X X Other than 01b XXX X Comparator B3 reference voltage input (IVREF3) Pin Register PD11 INTSR INTEN INTCMP —— SSMR2 U2CO U2SR1 U2MR — FunctionBit PD11_i INTi SEL0 INTiEN INT3 CP0 —— CSS CRS CRD CTSSEL0 SMD 10 2 1 0 Port P11_3 SCS (CTS2 RTS2 INT3) IVCMP3 i = 3

0 X X X — — 0 0 X X 0 XXX Input port (1)

1 X X X — — 0 0 X X 0 XXX Output port (2)

X X X X — — 0 1 X X X XXX SCS input (1) X X X X — — 1 X X X X XXX SCS output (2, 5) 0XX X— — 0 0 0 0 1 Other than 000b CTS2 input (1) 0XX X— — 0 0 1 0 1 RTS2 output (2) 0 1 1 0 — — 0 0 X X 0 XXX INT3 input (1) 0 0 1 1 — — 0 0 X X 0 XXX Comparator B3 input (IVCMP3)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 119 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Notes: 1. Pulled up by setting the corresponding bit in the P11PUR register to 1. 2. Output drive capacity high by setting the corresponding bit in the P11DRR register to 1. Table 7.20 Ports P11_4 to P11_7 Pin Register PD11 INTSR INTEN1 TRASR TRAIOC TRAMR U0SR FunctionBit PD11_i INTi SEL0 INTiEN TRAIOSEL TOPCR TMOD0 RXD0SEL 1 0 21010 Port P11_4 TRAIO (INT4 RXD0) i = 4

0 X X 0 0 X XXXXX Input port (1)

1 X X 0 0 X XXXXX Output port (2)

000b, 001b XX TRAIO input (1) 0 1 1 0 0 X XXXXX INT4 input (1) 01 1 1 0 0 Other than 000b, 001b XX TRAIO/INT4 input (1) XX X 1 1 0 0 0 1 X X TRAIO pulse output (2)

0 X X 0 0 X XXX10 RXD0 input (1)

Register PD11 INTSR INTEN1 — TRAIOC ——— FunctionBit PD11_i INTi SEL0 INTiEN — TOENA ——— Port P11_5 TRAO (INT5) i = 5 0X X — 0 Input port (1) 1X X — 0 Output port (2) XX X — 1 TRAO input (1) 01 1 — 0 INT5 input (1) Pin Register PD11 INTSR INTEN1 — TRBIOC TRBMR FunctionBit PD11_i INTi SEL0 INTiEN — TOCNT TMOD Port P11_6 TRBO (INT6) i = 6 0X X — X 0 0 Input port (1) 1X X — X 0 0 Output port (2) XX X — 1 X X XX X — 0 0 1 Programmable waveform generation mode (2) XX X — 0 1 0 Programmable one-shot generation mode (2) XX X — 0 1 1 Programmable wait one- shot generation mode (2) 01 1 —X0 0 INT6 input (1) Pin Register PD11 INTSR INTEN1 — TRECR1 ADMOD FunctionBit PD11_i INTi SEL0 INTiEN TOENA ADCAP — 1 0 Port P11_7 TREO (INT7 ADTRG) i = 7 0X X — 0 X X Input port (1) 1X X — 0 X X Output port (2) XX X — 1 X X TREO output (2) 01 1 — 0X X INT7 input (1) 01 1 — 0 1 1 ADTRG input (1)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 120 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P12PUR register to 1. Table 7.21 Ports P12_0 to P12_3 Pin Register PD12 CM0 CM1 Circuit Specifications Function Bit PD12_i CM05 CM07 CM10 CM11 CM13 Oscillation buffer Feedback resistor Port P12_0 XIN i = 4 0 11010 O F F O F F Input port (1) 1 11010 O F F O F F O u t p u t p o r t 0 10010 O N O N XIN clock input (1) 0 10110 O N O N XIN clock input stop (STOP mode) (1) 0 00001 O N O N XIN-XOUT oscillation (on-chip feedback resistor enabled) 0 00011 O N O F F XIN-XOUT oscillation (on-chip feedback resistor disabled ) 0 10001 O F F O N XIN-XOUT oscillation stop (on-chip feedback resistor enabled) 0 10011 O F F O F F XIN-XOUT oscillation stop (on-chip feedback resistor disabled ) 00 0 1 X 1 O F FO F F oscillation stop (STOP mode) Pin Register PD12 CM0 CM1 Circuit Specifications Function Bit PD12_i CM05 CM07 CM10 CM11 CM13 Oscillation buffer Feedback resistor Port P12_1 XOUT i = 1 0 1X010 O F F O F F Input port (1) 1 1 X 0 1 0 OFF OFF Output port 0 00001 O N O N XIN-XOUT oscillation (on-chip feedback resistor enabled) 0 00011 O N O F F XIN-XOUT oscillation (on-chip feedback resistor disabled ) 0 10001 O F F O N XIN-XOUT oscillation stop (on-chip feedback resistor enabled) 0 10011 O F F O F F XIN-XOUT oscillation stop (on-chip feedback resistor disabled ) 00 0 1 X 1 O F FO F F oscillation stop (STOP mode) Pin Register PD12 LSE7 —F u n c t i o nBit PD12_i LSE60 Port P12_2 CL1 i = 2

Port P12_3 CL2 i = 3

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 121 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Notes: 1. Pulled up by setting the corresponding bit in the P13PUR register to 1. 2. N-channel open-drain output by setting the NCH bit in the U0C0 register to 1. Table 7.22 Ports P13_0 to P13_3 Pin Register PD13 ADINSEL DACON — FunctionBit PD13_i CH ADGSEL DA0E210 1 0 Port P13_0 AN0 DA0 WKUP1 i = 0 0X X X X X 0 Input port (1)

1 X X X X X 0 Output port

0X X X X X 0 WKUP1 input (1) 00 0 0 0 0 0 A/D converter input (AN0) (1) 0X X X X X 1 D/A converter output (DA0) Pin Register PD13 ADINSEL DACON VCA2 U0SR U0MR — FunctionBit PD13_i CH ADGSEL DA1E VCA21 VCA23 TXD0 SEL0 SMD 210 1 0 21 0 Port P13_1 AN1 DA1 TXD0 LVREF i = 1 0X X X X X 0 XX 0X X X Input port (1)

1 X X X X X 0 X X 0 X X X Output port

00 0 1 0 0 0 XX 0X X X A/D converter input (AN1) (1) 0X X X X X 1 XX 0X X X D/A converter output (DA1) 0X X X X X 0 XX 1 00 1 TXD0 output (2)10 X 11 0 0X X X X X 0 1 X 0X X X Comparator A1 reference input (LVREF) 0X X X X X 0 X 1 0X X X Comparator A2 reference input (LVREF) Pin Register PD13 ADINSEL — VCA2 U0SR — FunctionBit PD13_i CH ADGSEL —V C A 2 2 RXD0 SEL 210 1 0 10 Port P13_2 AN2 RXD0 LVCMP1 i = 2 0X X X X X— X X X Input port (1)

1 X X X X X — X X X Output port

00 1 0 0 0— X X X A/D converter input (AN2) (1) 0X X X X X— X 0 1 RXD0 input (1) 0X X X X X— 1 X X Comparator A1 input (LVCMP1) Pin Register PD13 ADINSEL — VCA2 U0SR U0MR — FunctionBit PD13_i CH ADGSEL — VCA24 CLK0 SEL0 SMD CKDIR210 1 0 210 Port P13_3 AN3 CLK0 LVCMP2 i = 3 0X X X X X— X 0X X XX Input port (1)

1 X X X X X — X 0 X X X X Output port

0 011 0 0 — X 0 XXX X A/D converter input (AN3) (1) 0X X X X X— X 1X X X 1 CLK0 (external clock input) (1) X XXXX X — X 1 001 0 CLK0 (internal clock) output 0X X X X X— 1 0X X XX Comparator A2 input (LVCMP2)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 122 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group X: 0 or 1; —: No change in outcome Note: 1. Pulled up by setting the corresponding bit in the P13PUR register to 1. Table 7.23 Ports P13_4 to P13_7 Pin Register PD13 ADINSEL TRGPSR TRGIOR TRGMR FunctionCH ADGSEL TRG IOASEL IOA PWMBit PD13_i 210 1 0 2 1 0 Port P13_4 AN16 TRGIOA i = 4 0X X X X X 0 X X X X Input port (1)

1 X X X X X 0 X X X X Output port

00 0 0 1 0 0 X X X X A/D converter input (AN16) (1) 0X X X X X 1 1 X X 0 Timer mode (input capture function) (1) XX X X X X 1 X X X 1 PWM mode waveform output XX X X X X 1 0 Timer mode waveform output (output compare function)1X Pin Register PD13 ADINSEL TRGPSR TRGCR TRGMR FunctionCH ADGSEL TRG CLKA SEL TCK MDFBit PD13_i 210 1 0 2 1 0 Port P13_5 AN17 TRGCLKA i = 5 0X X X X X 0 X X X X Input port (1) 00 0 1 1 0 0 X X X X A/D converter input (AN17) (1) XX X X X X 1 1 0 1 0 TRGCLKA input (other than phase- counting mode) (1) XX X X X X 1 X X X 1 TRGCLKA input (phase-counting mode) (1) Pin Register PD13 ADINSEL TRGPSR TRGIOR FunctionCH ADGSEL TRG IOBSEL IOB Bit PD13_i 210 1 0 2 1 0 Port P13_6 AN18 TRGIOB i = 6 0X X X X X 0 X X X Input port (1)

1 X X X X X 0 X X X Output port

00 1 0 1 0 0 X X X A/D converter input (AN18) (1) 0X X X X X 1 1 X X Timer mode (input capture function) (1) XX X X X X 1 0

01 Timer mode waveform

output (output compare function)1X Pin Register PD13 ADINSEL TRGPSR TRGCR TRGMR FunctionCH ADGSEL TRG CLKB SEL TCK MDFBit PD13_i 210 1 0 2 1 0 Port P13_7 AN19 TRGCLKB i = 7 0X X X X X 0 X X X X Input port (1) 00 1 1 1 0 0 X X X X A/D converter input (AN19) (1) 0X X X X X 1 1 1 1 0 TRGCLKB input (other than phase- counting mode) (1) 0X X X X X 1 X X X 1 TRGCLKB input (phase-counting mode) (1)

1. I/O Ports REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 123 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

7.6 Unassigned Pin Handling

Table 7.24 lists Unassigned Pin Handling. Notes: 1. If these ports are set to output mode and left open, they remain in input mode until they are switched to output mode by a program. The voltage level of these pins may be undefined and the power current may increase while the ports remain in input mode. The content of the direction registers may chang e due to noise or program runaway caused by noise. In order to enhance program reliability, t he program should periodically repeat the setting of the direction registers. 2. Connect these unassigned pins to the MCU using th e shortest wire length (2 cm or less) possible. 3. When power-off mode is not used. 4. When the power-on reset function is used. Figure 7.6 Unassigned Pin Handling Table 7.24 Unassigned Pin Handling Pin Name Connection Ports P0 to P7, Ports P10, P11, 12_2, P12_3

• After setting to input mode, connect each pin to VSS via a resistor (pull-down) or connect each pin to VCC via a resistor (pull-up). (2)
• After setting to output mode, leave these pins open. (1, 2) Ports P12_0, P12_1 Connect to VCC via a pull-up resistor. (2) VREF Connect to VCC. WKUP0 (3) Connect to VSS. (3) RESET (4) Connect to VCC via a pull-up resistor. (4) Notes: 1. When the power-on reset function is used. 2. When power-off mode is not used. MCU Ports P0 to P7, Ports P10, P11 Ports P12_2, P12_3 (Input mode ) (Input mode) (Output mode) Open RESET (1) VREF WKUP0 (2) Ports P12_0, P12_1

1. Bus REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 124 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 8. Bus The bus cycles differ when accessing ROM/RAM and when accessing SFR. Table 8.1 lists the Bus Cycles by Access Area. ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are accessed twice in 8-bit units. Table 8.2 shows Access Units and Bus Operations. Note: 1. Data flash is provided only in the following four: the R8C/L35A Group, L36A Group, L38A Group, and L3AA Group. Table 8.2 Access Units and Bus Operations Table 8.1 Bus Cycles by Access Area Access Area Bus Cycle SFR/Data flash 2 cycles of CPU clock Program ROM/RAM 1 cycle of CPU clock Area SFR, Data flash Even address Byte access ROM (program ROM), RAM Odd address Byte access Even address Word access Odd address Word access CPU clock Data Data Data Even EvenAddress CPU clock Data Address CPU clock Data Address CPU clock Data Address CPU clock Data Address CPU clock Data Address CPU clock Data Address CPU clock Data Address Data Data Odd Odd Data Even Even + 1 Data Data Odd Odd + 1 Data Data Even Even + 1 Data Data Odd Odd + 1 Data

1. Bus REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 125 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group However, only the following SFRs are connected with the 16-bit bus: Interrupts: Each interrupt control register Timer RC: Registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD Timer RD: Registers TRDi (i = 0 or 1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi Timer RG: Registers TRG , TRGGRA, and TRGGRB SSU: Registers SSTDR, SSTDRH, SSRDR, and SSRDRH UART2: Registers U2MR, U2BRG, U2TB, U2C0, U2C1, U2RB, U2SMR5, U2SMR4, U2SMR3, U2SMR2, and U2SMR A/D converter: Registers AD0, AD1, AD2, AD3, AD4, AD5, AD6, AD7, ADMOD, ADINSEL, ADCON0, and ADCON1 D/A converter: Registers DA0 and DA1 Address match interrupt: Registers RMAD0, AIER0, RMAD1, and AIER1 Therefore, they are accessed on ce in 16-bit units. The bus operation is th e same as “Area: SFR, Data flash, Even address Byte Access” in Table 8.2 Access Units and Bus Operations, and 16-bit data is accessed at a time.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 126 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9. Clock Generation Circuit The following five circuits are incorporated in the clock generation circuit:

• XIN clock oscillation circuit
• XCIN clock oscillation circuit
• Low-speed on-chip oscillator
• High-speed on-chip oscillator
• Low-speed on-chip oscillator for the watchdog timer

9.1 Introduction

Table 9.1 lists the Specification Overview of Clock Ge neration Circuit. Figure 9.1 shows the Clock Generation Circuit and Figure 9.2 shows the Peripheral Function Clock. Notes: 1. These pins can be used as P12_0 and P12_1 when usin g the on-chip oscillator clock as the CPU clock while the XIN clock oscillation circuit and the XCIN clock oscillation circuit are not used. 2. To input an external clock, set the CM05 bit in the CM0 register to 1 (XIN clock stops), the CM11 bit in the CM1 register to 1 (on-chip feedback resistor enabled), and the CM13 bit to 1 (XIN-XOUT pin). 3. The clock frequency is set to up to 20 MHz by a divi der when using the high-speed on-chip oscillator as the CPU clock source. 4. This applies when the CSPROINI bit in the OFS register is set to 1 (count source protection mode disabled after reset). 5. This applies when the CSPROINI bit in the OFS register is set to 0 (count source protection mode enabled after reset). Table 9.1 Specification Overview of Clock Generation Circuit Item XIN Clock Oscillation Circuit XCIN Clock Oscillation Circuit On-Chip Oscillator Low-Speed On-Chip Oscillator for Watchdog Timer High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator Applications • CPU clock source

• Peripheral function clock source
• CPU clock source
• Peripheral function clock source
• CPU clock source
• Peripheral function clock source
• CPU and peripheral function clock source when XIN clock stops oscillating
• CPU clock source
• Peripheral function clock source
• CPU and peripheral function clock source when XIN clock stops oscillating
• Watchdog timer clock source Clock frequency 0 to 20 MHz 32.768 kHz Approx. 40 MHz (3) Approx. 125 kHz Approx. 125 kHz Connectable oscillator
• C e r a m i c resonator
• Crystal oscillator
• Crystal oscillator −−− Oscillator connect pins XIN, XOUT (1) XCIN, XCOUT − (1) − (1) − Oscillation stop, restart function Usable Usable Usable Usable Usable Oscillator status after reset Stop Oscillate Stop Oscillate Stop (4) Oscillate (5) Others Externally generated clock can be input (2)
• Externally generated clock can be input
• On-chip feedback resistor Rf (connected/ not connected selectable) −−−

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 127 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 9.1 Clock Generation Circuit S Q R Charge/ discharge circuit S Q R FRA00 High-speed on-chip oscillator FRA01 = 1 FRA01 = 0 CM14 a b c d e Divider Oscillation stop detection XIN clock XOUT CM02 WAIT instruction RESET CM10 = 1 (stop mode) a dc h b CM06 = 0 CM17 to CM16 = 11b CM06 = 1 CM06 = 0 CM17 to CM16 = 10b CM06 = 0 CM17 to CM16 = 01b CM06 = 0 CM17 to CM16 = 00b Detail of divider Oscillation Stop Detection Circuit Pulse generation circuit for clock edge detection and charge/ discharge control XIN clock Forcible discharge when OCD0 = 0 Watchdog timer interruptOCD1 OCD2 bit switch signal CM14 bit switch signal Oscillation stop detection, watchdog timer, voltage monitor 1 interrupt, voltage monitor 2 interrupt eg FRA2 register fOCO-S g h Voltage monitor 2 interrupt System clock Low-speed on-chip oscillator FRA1 register, FRA3 register Frequency adjustable On-chip oscillator clock fC Power-on reset circuit Voltage detection circuit Voltage monitor 1 interrupt Divider (1/128) Power-on reset Software reset Interrupt request 1/81/2 CPU clock f32 fOCO40M fC4 fC32 fOCO128 fOCO fOCO-F fOCO-S Peripheral function clock fC2 fC fOCO-WDTLow-speed on-chip oscillator for watchdog timerCSPRO CM30 CM13 CM05 XIN CM03 fC CM01, CM02, CM03, CM04, CM05, CM06, CM07: Bits in CM0 register CM10, CM11, CM12, CM13, CM14, CM16, CM17: Bits in CM1 register CM30: Bit in CM3 register OCD0, OCD1, OCD2: Bits in OCD register FRA00, FRA01, FRA03: Bits in FRA0 register CSPRO: Bit in CSPR register Oscillation stop detection Interrupt generation circuit FRA03 = 1 FRA03 = 0 CM07 CM07 = 0 CM07 = 1 CM05 XCOUTXCIN CM12 CM13 = 0 CM13 = 1 CM11 CM02 OCD2 = 1 OCD2 = 0 Divider fC-LCD CM02 CM01 CM01 CM04 = 1 CM04 = 0 (Receiver) (Oscillator)

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 128 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 9.2 Peripheral Function Clock A/D converterTimer RDTimer RBTimer RAINTi SSU/ I2C bus Watchdog timer UART2 UART1 UART0 Timer RE CPU clock f32 fOCO40M fOCO-F fC4 fC32 fOCO128 Timer RC LCD fOCO-WDT fOCO CPU fC fC2 Timer RG fC-LCD i = 0 to 7

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 129 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.2 Registers

9.2.1 System Clock Cont rol Register 0 (CM0)

Notes: 1. The CM05 bit stops the XIN clock when high-speed on-c hip oscillator mode or low-speed on-chip oscillator mode is selected. This bit cannot be used to detect whether the XIN clock has stopped. To stop the XIN clock, set the bits in the following order: (a) Set bits OCD1 to OCD0 in the OCD register to 00b. (b) Set the OCD2 bit to 1 (on-chip oscillator clock selected). 2. During external clock input, only the clock oscillation buffer stops and clock input is acknowledged. 3. Only when the CM05 bit to 1 (XIN clock stops) and the CM07 bit is set to 1 (XCIN clock), P12_0 and P12_1 can be used as I/O ports. 4. When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode). 5. Change the CM07 bit from 0 to 1 (XCIN clock) after the XCIN clock oscillation has become stable. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM0 register. Address 0006h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CM07 CM06 CM05 CM04 CM03 CM02 CM01 — A f t e r R e s e t 00100000 Bit Symbol Bit Name Function R/W b0 — Reserved bit Set to 0. R/W b1 CM01 Peripheral function clock stop bit in wait mode b1 b0 0 0: Peripheral function clock does not stop in wait mode 0 1: Clocks f1 to f32 stop in wait mode 1 0: Clocks f1 to f32 and fC stop in wait mode 1 1: Clocks f1 to f32, fC, and fC-LCD stop in wait mode R/W b2 CM02 R/W b3 CM03 XCIN clock stop bit 0: XCIN clock oscillates 1: XCIN clock stops R/W b4 CM04 XCIN external clock input enable bit 0: External clock input disabled 1: External clock input enabled R/W b5 CM05 XIN clock (XIN-XOUT) stop bit (1, 3) 0: XIN clock oscillates 1: XIN clock stops (2) R/W b6 CM06 System clock division select bit 0 (4) 0: Bits CM16 and CM17 in CM1 register enabled 1: Divide-by-8 mode R/W b7 CM07 XIN and XCIN clock select bit (5) 0: XIN clock 1: XCIN clock R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 130 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.2.2 System Clock Cont rol Register 1 (CM1)

Notes: 1. When the CM06 bit is set to 0, bits CM16 and CM17 are enabled. 2. When the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled. 3. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit can be set to 1 (low-speed on-chip oscillator off). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator on). It remains unchanged even if 1 is written to it. 4. To use the voltage monitor 1 interrupt or voltage monitor 2 interrupt (when the digital filter is used), set the CM14 bit to 0 (low-speed on-chip oscillator on). 5. To use P12_0 and P12_1 as input ports, set the CM13 bit to 0 (I/O ports), the CM05 bit in the CM0 register to 1 (XIN clock stops), and the CM07 bit to 1 (XCIN clock). To use as external clock input, set the CM13 bit to 0 (I/O ports), the CM05 bit to 1 (XIN clock oscillates), the CM07 bit to 0 (XIN clock). When the PD12_0 bit in the PD12 register is further set to 0 (input mode), an external clock can be input. XOUT can be used as the input port P12_1 at this time. 6. When the CM10 bit is set to 1 (stop mode), the XOUT pin is held high while the CM13 bit is set to 1 (XIN-XOUT pin). 7. Once the CM13 bit is set to 1 by a program, it cannot be set to 0. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM1 register. Address 0007h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CM17 CM16 — CM14 CM13 CM12 CM11 CM10 A f t e r R e s e t 00100000 Bit Symbol Bit Name Function R/W b0 CM10 All clock stop control bit (2, 5) 0: Clock oscillates 1: All clocks stop (stop mode) R/W b1 CM11 XIN-XOUT on-chip feedback resistor select bit 0: On-chip feedback resistor enabled 1: On-chip feedback resistor disabled R/W b2 CM12 XCIN-XCOUT on-chip feedback resistor select bit 0: On-chip feedback resistor enabled 1: On-chip feedback resistor disabled R/W b3 CM13 Port/XIN-XOUT switch bit (5, 6, 7) 0: I/O ports P12_0 and P12_1 1: XIN-XOUT pin R/W b4 CM14 Low-speed on-chip oscillator oscillation stop bit (3, 4) 0: Low-speed on-chip oscillator on 1: Low-speed on-chip oscillator off R/W b5 — Reserved bit Set to 1. R/W b6 CM16 System clock division select bit 1 (1) b7 b6 0 0: No division mode 0 1: Divide-by-2 mode 1 0: Divide-by-4 mode 1 1: Divide-by-16 mode R/W b7 CM17 R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 131 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.2.3 System Clock Cont rol Register 3 (CM3)

Notes: 1. When the MCU exits wait mode by a peripheral function inte rrupt, the CM30 bit is set to 0 (other than wait mode). 2. Set the CM35 bit to 0 in stop mode. When the MCU enters wait mode, if the CM35 bit is set to 1 (no division), the CM06 bit in the CM0 register is set to 0 (bits CM16 and CM17 enabled) and bits CM17 and CM16 in the CM1 register is set to 00b (no division mode). 3. When bits CM37 to CM36 are set to 10b (high-speed on-chip oscillator clock selected), the following will be set when the MCU exits wait mode or stop mode:

• OCD2 bit in OCD register = 1 (on-chip oscillator selected)
• FRA00 bit in FRA0 register = 1 (high-speed on-chip oscillator on)
• FRA01 bit in FRA0 register = 1 (high-speed on-chip oscillator selected) 4. When bits CM37 to CM36 are set to 11b (XIN clock selected), the following will be set when the MCU exits wait mode or stop mode.
• OM05 bit in OM0 register = 1 (XIN clock oscillates)
• OM13 bit in OM1 register = 1 (XIN-XOUT pin)
• OCD2 bit in OCD register = 0 (XIN clock selected) Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM3 register. CM30 bit (Wait Control Bit) When the CM30 bit is set to 1 (MCU enters wait mode), the CPU clock stops (wait mode). However, the XIN clock, XCIN clock, and on-chip oscillator clock do not stop, so peripheral functions using these clocks continue operating. The MCU exits wait mode by a reset or peripheral function interrupt. If the MCU enters wait mode while the I flag is set to 0 (maskable interrupt disabled), it resumes executing the instruction immediately after the instruction to set the CM30 bit to 1 when exiting wait mode. If the MCU enters wait mode with the WAIT instruction, interrupt handling is performed by the CPU when exiting wait mode. Address 0009h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CM37 CM36 CM35 — — — — CM30 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 CM30 Wait control bit (1) 0: Other than wait mode 1: MCU enters wait mode R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 — b3 — b4 — b5 CM35 CPU clock divisi on ratio select bit when exiting wait mode 0: Following settings are enabled: CM06 bit in CM0 register Bits CM16 and CM17 in CM1 register 1: No division (2) R/W b6 CM36 CPU clock select bit when exiting wait or stop mode b7 b6 0 0: MCU exits with the CPU clock used immediately before entering wait or stop mode 0 1: Do not set. 1 0: High-speed on-chip oscillator clock selected (3) 1 1: XIN clock selected (4) R/W b7 CM37 R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 132 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.2.4 Oscillation Stop De tection Register (OCD)

Notes: 1. Set bits OCD1 to OCD0 to 00b before the MCU enters stop mode, high-speed on-chip oscillator mode, or low- speed on-chip oscillator mode (XIN clock stops). 2. When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator on). 3. The OCD2 bit is automatically set to 1 (on-chip oscilla tor clock selected) when the XIN clock oscillation stop is detected while bits OCD1 to OCD0 are set to 11b. When the OCD3 bit is set to 1 (XIN clock stops), the OCD2 bit remains unchanged even if 0 (XIN clock selected) is written to it. 4. The OCD3 bit is enabled when the OCD0 bit is set to 1 (oscillation stop detection function enabled). 5. The OCD3 bit remains 0 (XIN clock oscillates) when bits OCD1 to OCD0 are set to 00b. 6. Refer to 9.7.1 How to Use Oscillation Stop Detection Function for the switching pr ocedure when the XIN clock re-oscillates after detecting an oscillation stop. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the OCD register.

9.2.5 High-Speed On-Chip Oscillat or Control Register 7 (FRA7)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — OCD3 OCD2 OCD1 OCD0 A f t e r R e s e t 00000100 Bit Symbol Bit Name Function R/W b0 OCD0 Oscillation stop detection enable bit (6) 0: Oscillation stop detection function disabled (1) 1: Oscillation stop detection function enabled R/W b1 OCD1 Oscillation stop detection interrupt enable bit 0: Disabled (1) 1: Enabled R/W b2 OCD2 System clock select bit (3) 0: XIN clock selected (6) 1: On-chip oscillator clock selected (2) R/W b3 OCD3 Clock monitor bit (4, 5) 0: XIN clock oscillates 1: XIN clock stops R b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 — Address 0015h B i t b 7b 6b 5b 4b 3b 2b 1b 0 After Reset When shipping Bit Function R/W b7-b0 32 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the FRA3 register and by transferring the correction value of the FRA6 register to the FRA1 register. R

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 133 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.2.6 High-Speed On-Chip Oscillat or Control Register 0 (FRA0)

Notes: 1. Change the FRA01 bit under the following conditions.

• FRA00 = 1 (high-speed on-chip oscillator on)
• CM14 bit in CM1 register = 0 (low-speed on-chip oscillator on)
• Bits FRA22 to FRA20 in the FRA2 register: All division mode can be set when VCC = 3.0 V to 5.5 V 000b to 111b Division ratio of 4 or more when VCC = 2.7 V to 5.5 V 010b to 111b (divide-by-4 or more) Division ratio of 8 or more when VCC = 2.2 V to 5.5 V 110b to 111b (divide-by-8 or more) 2. When setting the FRA01 bit to 0 (low-speed on-chip oscillator selected), do not set the FRA00 bit to 0 (high- speed on-chip oscillator off) at the same time. Set the FRA01 bit to 0 before setting the FRA00 bit to 0. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA0 register.

9.2.7 High-Speed On-Chip Oscillat or Control Register 1 (FRA1)

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA1 register. Address 0023h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — FRA03 — FRA01 FRA00 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 FRA00 High-speed on-chip oscillator enable bit 0: High-speed on-chip oscillator off 1: High-speed on-chip oscillator on R/W b1 FRA01 High-speed on-chip oscillator select bit (1) 0: Low-speed on-chip oscillator selected (2) 1: High-speed on-chip oscillator selected R/W b2 — Reserved bit Set to 0. R/W b3 FRA03 fOCO128 clock select bit 0: fOCO-S divided by 128 selected 1: fOCO-F divided by 128 selected R/W b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 — Address 0024h B i t b 7b 6b 5b 4b 3b 2b 1b 0 After Reset When shipping Bit Function R/W b7-b0 The frequency of the high-speed on-chi p oscillator can be changed by the following settings.

40 MHz: FRA1=FRA3=Value after a reset

36.864 MHz: Transfer the data of the FRA4 regi ster to the FRA1 register, and transfer the

data of the FRA5 register to the FRA3 register.

32 MHz: Transfer the data of the FRA6 regist er to the FRA1 register, and transfer the

data of the FRA7 register to the FRA3 register. R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 134 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.2.8 High-Speed On-Chip Oscillat or Control Register 2 (FRA2)

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA2 register. Address 0025h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — — FRA22 FRA21 FRA20 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 FRA20 High-speed on-chip oscillator frequency switch bit Division ratio selection These bits select the division ratio for the high- speed on-chip oscillator clock. b2 b1 b0 0 0 0: Divide-by-2 mode 0 0 1: Divide-by-3 mode 0 1 0: Divide-by-4 mode 0 1 1: Divide-by-5 mode 1 0 0: Divide-by-6 mode 1 0 1: Divide-by-7 mode 1 1 0: Divide-by-8 mode 1 1 1: Divide-by-9 mode R/W b1 FRA21 R/W b2 FRA22 R/W b3 — Reserved bits Set to 0. R/W b4 — b5 — b6 — b7 —

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 135 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.2.9 High-Speed On-Chip Oscillat or Control Register 4 (FRA4)

9.2.10 High-Speed On-Chip Oscillat or Control Register 5 (FRA5)

9.2.11 High-Speed On-Chip Oscillat or Control Register 6 (FRA6)

9.2.12 High-Speed On-Chip Oscillat or Control Register 3 (FRA3)

Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA3 register. Address 0029h B i t b 7b 6b 5b 4b 3b 2b 1b 0 After Reset When shipping Bit Function R/W b7-b0 36.864 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the FRA1 register and by transferring the correction value of the FRA5 register to the FRA3 register. R Address 002Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 After Reset When shipping Bit Function R/W b7-b0 36.864 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the FRA3 register and by transferring the correction value of the FRA4 register to the FRA1 register. R Address 002Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 After Reset When shipping Bit Function R/W b7-b0 32 MHz frequency correction data is stored. The frequency can be adjusted by transferring this value to the FRA1 register and by transferring the correction value of the FRA7 register to the FRA3 register. R Address 002Fh B i t b 7b 6b 5b 4b 3b 2b 1b 0 After Reset When shipping Bit Function R/W b7-b0 The frequency of the high-speed on-chi p oscillator can be changed by the following settings. data of the FRA5 register to the FRA3 register. data of the FRA7 register to the FRA3 register. R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 136 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group The clocks generated by the clock generation circuits are described below.

9.3 XIN Clock

The XIN clock is supplied by the XIN clock oscillation circui t. This clock is used as the clock source for the CPU and peripheral function clocks. The XIN clock oscillatio n circuit is configured by connecting a resonator between pins XIN and XOUT. The XIN clock oscillation circuit includes an on-ch ip feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the chip. The XIN clock oscillation circuit may also be config ured by feeding an externally generated clock to the XOUT pin. Figure 9.3 shows Examples of XIN Clock Connection Circuit. During and after reset, the XIN clock stops. After setting the CM13 bit in the CM1 register to 1 (X IN-XOUT pin), the XIN clock starts oscillating when the CM05 bit in the CM0 register is set to 0 (XIN clock oscillates). After the XIN clock oscillation stabilizes, the XIN clock is used as the CPU clock source by setting the OCD2 bit in the OCD register to 0 (XIN clock selected). The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 (XIN clock stops) by setting the OCD2 bit is to 1 (on-chip oscillator clock selected). In stop mode, all clocks including the XIN clock stop. Refer to 10. Power Control for details. Figure 9.3 Examples of XIN Clock Connection Circuit XIN XOUT MCU (on-chip feedback resistor) Rd (1) COUTCIN Ceramic resonator external circuit XIN XOUT MCU (on-chip feedback resistor) External clock input circuit Externally generated clock VCC VSS Note: 1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity settings. Use the values recommended by the oscillator manufacturer. If the oscillator manufacturer's datasheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between XIN and XOUT following the instructions. Open Rf (1)

• When CM05 bit in CM0 register is 0 (XIN clock oscillates) and CM13 bit in CM1 register is 1 (XIN-XOUT pin)
• When CM05 bit in CM0 register is 1 (XIN clock stops), CM07 bit is 0 (XIN clock), CM11 bit in CM1 register is 1 (on-chip feedback resistor disabled), and CM13 bit is 0 (input ports P12_0 and P12_1)

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 137 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.4 On-Chip Oscillator Clock

The on-chip oscillator clock is supplied by the on-chip os cillator (high-speed on-chip oscillator or low-speed on- chip oscillator). This clock is selected by the FRA01 bit in the FRA0 register.

9.4.1 Low-Speed On-Chi p Oscillator Clock

The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock, and peripheral function clock (fOCO, fOCO-S, and fOCO128). After a reset, the on-chip oscillator clock generate d by the low-speed on-chip oscillator divided by 1 (no division) is selected as the CPU clock. If the XIN clock stops oscillating when bits OCD1 to OCD0 in the OCD register ar e set to 11b, the low-speed on-chip oscillator automatically starts operating and supplies the necessary clock for the MCU. The frequency of the low-speed on-chip oscillator vari es depending on the supply voltage and the operating ambient temperature. Application products must be de signed with sufficient margin to allow for frequency changes.

9.4.2 High-Speed On-Chip Oscillator Clock

The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock, and peripheral function clock (fOCO, fOCO-F, fOCO40M, and fOCO128). To use the high-speed on-chip oscillator clock as the cl ock source for the CPU clock, peripheral clock, fOCO, and fOCO-F, set bits FRA20 to FRA22 in the FRA2 register as follows:

• All division mode can be set when VCC = 3.0 V to 5.5 V 000b to 111b
• Division ratio of 4 or more when VCC = 2.7 V to 5.5 V 010b to 111b (divide-by-4 or more)
• Division ratio of 8 or more when VCC = 2.2 V to 5.5 V 110b to 111b (divide-by-8 or more) After a reset, the on-chip oscillator cl ock generated by the high-speed on-c hip oscillator stops. Oscillation is started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). Frequency correction data is stored in registers FRA4 to FRA7. To adjust the frequency of the high-speed on-chip oscillat or clock to 36.864 MHz, first transfer the correction value of the FRA4 register to the FRA1 register and the co rrection value of the FRA5 register to the FRA3 register before using the values. This enables the settin g errors of bit rates such as 9,600 bps and 38,400 bps to be 0% when the serial interface is used in UART mode (refer to Table 24.8 and Table 25.8 Bit Rate Setting Example in UART Mode (Internal Clock Selected)). To adjust the frequency of the high-speed on-chip oscillator clock to 32 MHz, first transfer the correction value of the FRA6 register to the FRA1 register and the corr ection value of the FRA7 register to the FRA3 register before using the values.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 138 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.5 XCIN Clock

The XCIN clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The XCIN clock osci llation circuit is configured by connecting a resonator between pins XCIN and XCOUT. The XCIN clock oscillation circuit includes an on-chip a feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the chip. The XCIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure 9.4 shows Examples of XCIN Clock Connection Circuits. Bits CM04 to CM03 in the CM0 register are set to 00b (e xternal clock input disabled, XCIN clock oscillates) by reset and the XCIN clock starts oscillating (with the on- chip feedback resistor enab led). After the XCIN clock oscillation stabilizes following reset, the XCIN clock is used as the CPU clock sour ce by setting the CM07 bit in the CM07 register to 1 (XCIN clock). When the CM03 bit is set to 1 (XCIN clock stops), the XCIN clock stops. When bits CM04 to CM03 are set to 10b (external cloc k input enabled, XCIN cloc k oscillates), an externally generated clock can also be input to the XCIN pin. Leave the XCOUT pin open at this time. This MCU has an on-chip feedback resistor, which can be disabled/enabled by the CM12 bit in the CM1 register. When the XCIN clock is not used, set bits CM04 to CM03 to 01b (external clock input disabled, XCIN clock stops) and the CM12 bit to 1 (on-chip feedback resistor disabled). In stop mode, all clocks including the XCIN clock stop. Refer to 10. Power Control for details. Figure 9.4 Examples of XCIN Clock Connection Circuits XCIN XCOUT MCU (on-chip feedback resistor) Rd (1) COUTCIN XCIN XCOUT MCU (on-chip feedback resistor) Externally generated clock VCC VSS Note: 1. Insert a damping resistor and a feedback resistor if required. The resistance w ill vary depending on the oscillator and the osc illation drive c apacity settings. Use the value recommended by the osc illator manufacturer. If the oscillator m anufacturer's datasheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between XCIN and XCOUT following the instructions. Open External crystal oscillator circuit External clock input circuit Rf (1)

• When CM03 bit in CM0 register is 0 (XCIN clock osc illates) and CM04 bit is 0 (external clock input disabled)
• When CM03 bit in CM0 register is 1 (XCIN clock stops) and CM04 bit is 1 (external clock input enabled)

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 139 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.6 CPU Clock and Peri pheral Function Clock

There are a CPU clock to operate the CPU and a peripher al function clock to operate the peripheral functions. (Refer to Figure 9.1 Clock Generation Circuit.)

9.6.1 System Clock

The system clock is the clock source for the CPU and peripheral function clocks. The XIN clock, XCIN clock, or on-chip oscillator clock can be selected.

9.6.2 CPU Clock

The CPU clock is an operating clock for the CPU and the watchdog timer. The system clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. The division ratio can be selected by the CM06 bit in the CM0 register and bits CM16 and CM17 in the CM1 register. Use the XCIN clock while the XCIN clock oscillation stabilizes. After a reset, the low-speed on-chip oscillator clock divided by 1 (no division) is used as the CPU clock. When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode). To enter stop mode, set the CM35 bit in the CM3 register to 0 (settings of CM 06 in CM0 register and bits CM16 and CM17 in CM1 register enabled).

9.6.3 Peripheral Function Clo ck (f1, f2, f4, f8, and f32)

The peripheral function clock is an operating clock for the peripheral functions. The fi (i = 1, 2, 4, 8, and 32) clock is generated by the system clock divided by i. It is used for timers RA, RB, RC, RD, RE, RG , the serial interface, the A/D converter, and the LCD waveform control circuit. When the MCU enters wait mode after bits CM02 to CM01 in the CM0 register are set to 01, 10, or 11, the fi clock stops. 9.6.4 fOCO fOCO is an operating clock for the peripheral functions. This clock runs at the same frequency as the on-chip os cillator clock and can be used as the source for timer RA. In wait mode, the fOCO clock does not stop. 9.6.5 fOCO40M fOCO40M is used as the count source for timers RC, RD, and RG . This clock is generated by the high-speed on-chip oscillator and supplied by setting the FRA00 bit to 1. In wait mode, the fOCO40M clock does not stop. This clock can be used with supply voltage VCC = 3.0 to 5.5 V . 9.6.6 fOCO-F fOCO-F is used as the count source for timers RC and RD, and the A/D converter. This clock is generated by the high-speed on-chip oscillator, divided by i (i = 2, 3, 4, 5, 6, 7, 8, or 9; division ratio selected by the FRA2 register). It is supplied by setting the FRA00 bit to 1. In wait mode, the fOCO-F clock does not stop.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 140 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 9.6.7 fOCO-S fOCO-S is an operating clock for the voltage detection circuit. This clock is generated by the low-speed on-chip oscillator and supplied by setting the CM14 bit to 0 (low- speed on-chip oscillator on). In wait mode, the fOCO-S clock does not stop. 9.6.8 fOCO128 fOCO128 clock is generated by fOCO-S or fOCO-E divided by 128. fOCO-S divided by 128 is selected by setting the FRA03 bit to 0 and fOCO-F divided by 128 is selected by setting the FRA03 bit to 1. fOCO128 is configured as the capture signal used in the TRCGRA register for timer RC and timer RD0 for timer RD. 9.6.9 fC-LCD fC-LCD is used in the LCD waveform control circuit. Use this clock only while the XCIN clock oscillation stabilizes. 9.6.10 fC, fC2, fC4, and fC32 fC, fC2, fC4, and fC32 are used for timers RA, RD, RE and the serial interface. Use theses clocks while the XCIN clock oscillation stabilizes. 9.6.11 fOCO-WDT fOCO-WDT is an operating clock for the watchdog timer. This clock is generated by the low-speed on-chip oscillator for the watchdog timer and supplied by setting the CSPRO bit in the CSPR register to 1 (count source protection mode enabled). In count source protection mode for the watchdog timer, the fOCO-WDT clock does not stop.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 141 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.7 Oscillation Stop Detection Function

The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register. Table 9.2 lists the Specifications of Oscillation Stop Detection Function. When the XIN clock is the CPU clock so urce and bits OCD1 to OCD0 are set to 11b, the MCU is placed in the following states if the XIN clock stops.

• OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)
• OCD3 bit in OCD register = 1 (XIN clock stops)
• CM14 bit in CM1 register = 0 (low-speed on-chip oscillator on)
• Oscillation stop detection interrupt request is generated

9.7.1 How to Use Oscillat ion Stop Detection Function

• The oscillation stop detection interr upt shares a vector with the voltage monitor 1 interrupt, the voltage monitor 2 interrupt, and the watchdog timer interrupt. To use the oscillation stop detection interrupt and watchdog timer interrupt, the interrupt source needs to be determined. Table 9.3 lists the Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, V oltage Monitor 1, or V oltage Monitor 2 Interrupt. Figure 9.6 shows an Example of Determining Interrupt Sources for Oscillation Stop Detection, Watchdog Timer, V oltage Monitor 1, or V oltage Monitor 2 Interrupt.
• When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source for the CPU clock and the peripheral functions by a program. Figure 9.5 shows the Procedure for Switching Low-Speed On-Chip Oscillator to XIN Clock.
• To enter wait mode while the oscillation stop detection function is used, set bits CM02 to CM1 to 00 (peripheral function clock does not stop in wait mode).
• Since the oscillation stop detection function is a fu nction for cases where the XIN clock is stopped by an external cause, set bits OCD1 to OCD0 to 00b to stop or start the XIN clock by a program (select stop mode or change the CM05 bit).
• This function cannot be used when the XIN clock freque ncy is below 2 MHz. In this case, set bits OCD1 to OCD0 to 00b.
• To use the low-speed on-chip oscillator clock as th e clock source for the CPU clock and the peripheral functions after detecting the oscillat ion stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-chip oscillator selected) and then bits OCD1 to OCD0 to 11b. To use the high-speed on-chip oscillator clock as the clock source for the CP U clock and the peripheral functions after detecting the oscillation stop, first set the FRA00 bit to 1 (high-speed on-chip oscillator on) and the FRA01 bit to 1 (high-speed on-chip oscillator selected). Then set bits OCD1 to OCD0 to 11b. Table 9.2 Specifications of Oscillation Stop Detection Function Item Specification Oscillation stop detection clock and frequency bandwidth f(XIN) ≥ 2 MHz Condition for enabling the oscillation stop detection function Bits OCD1 to OCD0 are set to 11b. Operation at oscillation stop detection Osc illation stop detection interrupt generation Table 9.3 Determination of Interrupt Sources fo r Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Generated Interrupt Source Bit Indicati ng Interrupt Source Oscillation stop detection (when (a) or (b)) (a) OCD3 bit in OCD register = 1 (b) Bits OCD1 to OCD0 in OCD register = 11b and OCD2 bit = 1 Watchdog timer VW2C3 bit in VW2C register = 1 Voltage monitor 1 VW1C2 bit in VW1C register = 1 Voltage monitor 2 VW2C2 bit in VW2C register = 1

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 143 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 9. Clock Generation CircuitR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

9.8 Notes on Clock Generation Circuit

9.8.1 Oscillation Stop Detection Function

Since the oscillation stop detection function cannot be used when the XIN clock frequency is below 2 MHz, set bits OCD1 to OCD0 to 00b.

9.8.2 Oscillation Circuit Constants

Consult the oscillator manufacturer to determine the optimal oscillation circuit constants for the user system. To use the MCU with supply voltage below VCC = 2.7 V , it is recommended to set the CM11 bit in the CM1 register to 1 (on-chip feedback resistor disabled) and connect the feedback resistor to the chip externally.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 144 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 10. Power ControlR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 10. Power Control There are four power control modes. Al l modes other than wait mode, stop mode, and power-off mode are referred to as standard operating mode.

10.1 Introduction

Table 10.1 lists each mode. Figure 10.1 shows the State Transitions in Power Control Mode. Table 10.1 Power Control Mode Operation Standard operating mode High-speed clock The CPU and peripheral functions operate.High-speed on-chip oscillator Low-speed clock The CPU and peripheral functions operate.Low-speed on-chip oscillator Wait mode The CPU stops and peripheral functions operate. Stop mode The CPU and peripheral functions stop (oscillation stops). Power-off mode Functions other than the low-speed clock and timer RE stop or all functions stop.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 145 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 10. Power ControlR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 10.1 State Transitions in Power Control Mode CM10 = 1 All oscillators stop Stop mode State Transitions in Power Control Mode Wait mode Low-speed on-chip oscillator mode CM07 = 0 CM14 = 0 OCD2 = 1 FRA01 = 0 High-speed on-chip oscillator mode CM07 = 0 OCD2 = 1 FRA00 = 1 FRA01 = 1 High-speed clock mode CM05 = 0 CM07 = 0 CM13 = 1 OCD2 = 0 Standard operating mode CM14 = 0 OCD2 = 1 FRA01 = 0 CM05 = 0 CM13 = 1 OCD2 = 0 CM05 = 0 CM13 = 1 OCD2 = 0 OCD2 = 1 FRA00 = 1 FRA01 = 1 FRA00 = 1 FRA01 = 1 CM14 = 0 FRA01 = 0 CPU operation stops Interrupt WAIT instruction CM30 = 1Interrupt CM04, CM05, CM07: Bits in CM0 register CM13, CM14: Bits in CM1 register CM30: Bit in CM3 register OCD2: Bit in OCD register FRA00, FRA01: Bits in FRA0 register Low-speed clock mode CM04 = 1 CM07 = 1 CM07 = 0 CM14 = 0 OCD2 = 1 FRA01 = 0 CM07 = 1 CM07 = 0 OCD2 = 1 FRA00 = 1 FRA01 = 1 CM07 = 1 CM07 = 1 CM05 = 0 CM07 = 0 CM13 = 1 OCD2 = 0 Interrupt (timer RE) WKUP0, WKUP1 input Successive write to POMCR0 register Power-off mode Reset

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 146 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 10. Power ControlR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

10.2 Registers

10.2.1 System Clock Cont rol Register 0 (CM0)

Notes: 1. The CM05 bit stops the XIN clock when high-speed on-chip oscillator mode or low-speed on-chip oscillator mode is selected. This bit cannot be used to detect whether th e XIN clock has stopped. To stop the XIN clock, set the bits in the following order: (a) Set bits OCD1 to OCD0 in the OCD register to 00b. (b) Set the OCD2 bit to 1 (on-chip oscillator clock selected). 2. During external clock input, only the clock oscillation buffer stops and clock input is acknowledged. 3. Only when the CM05 bit to 1 (XIN clock stops) and the CM07 bit is set to 1 (XCIN clock), P12_0 and P12_1 can be used as I/O ports. 4. When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode). 5. Change the CM07 bit from 0 to 1 (XCIN clock) after the XCIN clock oscillation has become stable. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM0 register. Address 0006h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CM07 CM06 CM05 CM04 CM03 CM02 CM01 — A f t e r R e s e t 00100000 Bit Symbol Bit Name Function R/W b0 — Reserved bit Set to 0. R/W b1 CM01 Peripheral function clock stop bit in wait mode b1 b0 0 0: Peripheral function clock does not stop in wait mode 0 1: Clocks f1 to f32 stop in wait mode 1 0: Clocks f1 to f32 and fC stop in wait mode 1 1: Clocks f1 to f32, fC, and fC-LCD stop in wait mode R/W b2 CM02 R/W b3 CM03 XCIN clock stop bit 0: XCIN clock oscillates 1: XCIN clock stops R/W b4 CM04 XCIN external clock input enable bit 0: External clock input disabled 1: External clock input enabled R/W b5 CM05 XIN clock (XIN-XOUT) stop bit (1, 3) 0: XIN clock oscillates 1: XIN clock stops (2) R/W b6 CM06 System clock division select bit 0 (4) 0: Bits CM16 and CM17 in CM1 register enabled 1: Divide-by-8 mode R/W b7 CM07 XIN and XCIN clock select bit (5) 0: XIN clock 1: XCIN clock R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 147 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 10. Power ControlR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

10.2.2 System Clock Cont rol Register 1 (CM1)

Notes: 1. When the CM06 bit is set to 0, bits CM16 and CM17 are enabled. 2. When the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled. 3. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit can be set to 1 (low-speed on-chip oscillator off). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator on). It remains unchanged even if 1 is written to it. 4. To use the voltage monitor 1 interrupt or voltage monitor 2 interrupt (when the digital filter is used), set the CM14 bit to 0 (low-speed on-chip oscillator on). 5. To use P12_0 and P12_1 as input ports, set the CM13 bit to 0 (I/O ports), the CM05 bit in the CM0 register to 1 (XIN clock stops), and the CM07 bit to 1 (XCIN clock). To use as external clock input, set the CM13 bit to 0 (I/O ports), the CM05 bit to 1 (XIN clock oscillates), the CM07 bit to 0 (XIN clock). When the PD12_0 bit in the PD12 register is further set to 0 (input mode), an external clock can be input. XOUT can be used as the input port P12_1 at this time. 6. When the CM10 bit is set to 1 (stop mode), the XOUT pin is held high while the CM13 bit is set to 1 (XIN-XOUT pin). 7. Once the CM13 bit is set to 1 by a program, it cannot be set to 0. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM1 register. Address 0007h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CM17 CM16 — CM14 CM13 CM12 CM11 CM10 A f t e r R e s e t 00100000 Bit Symbol Bit Name Function R/W b0 CM10 All clock stop control bit (2, 5) 0: Clock oscillates 1: All clocks stop (stop mode) R/W b1 CM11 XIN-XOUT on-chip feedback resistor select bit 0: On-chip feedback resistor enabled 1: On-chip feedback resistor disabled R/W b2 CM12 XCIN-XCOUT on-chip feedback resistor select bit 0: On-chip feedback resistor enabled 1: On-chip feedback resistor disabled R/W b3 CM13 Port/XIN-XOUT switch bit (5, 6, 7) 0: I/O ports P12_0 and P12_1 1: XIN-XOUT pin R/W b4 CM14 Low-speed on-chip oscillator oscillation stop bit (3, 4) 0: Low-speed on-chip oscillator on 1: Low-speed on-chip oscillator off R/W b5 — Reserved bit Set to 1. R/W b6 CM16 System clock division select bit 1 (1) b7 b6 0 0: No division mode 0 1: Divide-by-2 mode 1 0: Divide-by-4 mode 1 1: Divide-by-16 mode R/W b7 CM17 R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 148 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 10. Power ControlR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

10.2.3 System Clock Cont rol Register 3 (CM3)

Notes: 1. When the MCU exits wait mode by a peripheral function interrupt, the CM30 bit is set to 0 (other than wait mode). 2. Set the CM35 bit to 0 in stop mode. When the MCU enters wait mode, if the CM35 bit is set to 1 (no division), the CM06 bit in the CM0 register is set to 0 (bits CM16 and CM17 enabled) and bits CM17 and CM16 in the CM1 register is set to 00b (no division mode). 3. When bits CM37 to CM36 are set to 10b (high-speed on-chip oscillator clock selected), the following will be set when the MCU exits wait mode or stop mode:

• OCD2 bit in OCD register = 1 (on-chip oscillator selected)
• FRA00 bit in FRA0 register = 1 (high-speed on-chip oscillator on)
• FRA01 bit in FRA0 register = 1 (high-speed on-chip oscillator selected) 4. When bits CM37 to CM36 are set to 11b (XIN clock se lected), the following will be set when the MCU exits wait mode or stop mode.
• OM05 bit in OM0 register = 1 (XIN clock oscillates)
• OM13 bit in OM1 register = 1 (XIN-XOUT pin)
• OCD2 bit in OCD register = 0 (XIN clock selected) Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM3 register. CM30 bit (Wait Control Bit) When the CM30 bit is set to 1 (MCU enters wait mode), the CPU clock stops (wait mode). However, the XIN clock, XCIN clock, and on-chip oscillator clock do not stop, so peripheral functions using these clocks continue operating. The MCU exits wait mode by a reset or peripheral function interrupt. If the MCU enters wait mode while the I flag is set to 0 (maskable interrupt disabled), it resumes executing the instruction immediately after the instruction to set the CM30 bit to 1 when exiting wait mode. If the MCU enters wait mode with the WAIT instruction, interrupt handling is performed by the CPU when exiting wait mode. Address 0009h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CM37 CM36 CM35 — — — — CM30 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 CM30 Wait control bit (1) 0: Other than wait mode 1: MCU enters wait mode R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 — b3 — b4 — b5 CM35 CPU clock division ratio select bit when exiting wait mode 0: Following settings are enabled: CM06 bit in CM0 register Bits CM16 and CM17 in CM1 register 1: No division (2) R/W b6 CM36 CPU clock select bit when exiting wait or stop mode b7 b6 0 0: MCU exits with the CPU clock used immediately before entering wait or stop mode 0 1: Do not set. 1 0: High-speed on-chip oscillator clock selected (3) 1 1: XIN clock selected (4) R/W b7 CM37 R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 149 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 10. Power ControlR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

10.2.4 Oscillation Stop De tection Register (OCD)

Notes: 1. Set bits OCD1 to OCD0 to 00b bef ore the MCU enters stop mode, high-speed on-chip oscillator mode, or low- speed on-chip oscillator mode (XIN clock stops). 2. When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator on). 3. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) when the XIN clock oscillation stop is detected while bits OCD1 to OCD0 are set to 11b. When the OCD3 bit is set to 1 (XIN clock stops), the OCD2 bit remains unchanged even if 0 (XIN clock selected) is written to it. 4. The OCD3 bit is enabled when the OCD0 bit is set to 1 (oscillation stop detection function enabled). 5. The OCD3 bit remains 0 (XIN clock oscillates) when bits OCD1 to OCD0 are set to 00b. 6. Refer to 9.7.1 How to Use Oscillation Stop Detection Function for the switching procedure when the XIN clock re-oscillates after detecting an oscillation stop. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the OCD register. Address 000Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — OCD3 OCD2 OCD1 OCD0 A f t e r R e s e t 00000100 Bit Symbol Bit Name Function R/W b0 OCD0 Oscillation stop detection enable bit (6) 0: Oscillation stop detection function disabled (1) 1: Oscillation stop detection function enabled R/W b1 OCD1 Oscillation stop detection interrupt enable bit 0: Disabled (1) 1: Enabled R/W b2 OCD2 System clock select bit (3) 0: XIN clock selected (6) 1: On-chip oscillator clock selected (2) R/W b3 OCD3 Clock monitor bit (4, 5) 0: XIN clock oscillates 1: XIN clock stops R b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 —

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10.2.5 High-Speed On-Chip Oscillat or Control Register 0 (FRA0)

Notes: 1. Change the FRA01 bit under the following conditions.

• FRA00 = 1 (high-speed on-chip oscillator on)
• CM14 bit in CM1 register = 0 (low-speed on-chip oscillator on)
• Bits FRA22 to FRA20 in the FRA2 register: All division mode can be set when VCC = 3.0 V to 5.5 V 000b to 111b Division ratio of 4 or more when VCC = 2.7 V to 5.5 V 010b to 111b (divide-by-4 or more) Division ratio of 8 or more when VCC = 2.2 V to 5.5 V 110b to 111b (divide-by-8 or more) 2. When setting the FRA01 bit to 0 (low-speed on-chip oscillator selected), do not set the FRA00 bit to 0 (high- speed on-chip oscillator off) at the same time. Set the FRA01 bit to 0 before setting the FRA00 bit to 0. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA0 register. Address 0023h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — FRA03 — FRA01 FRA00 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 FRA00 High-speed on-chip oscillator enable bit 0: High-speed on-chip oscillator off 1: High-speed on-chip oscillator on R/W b1 FRA01 High-speed on-chip oscillator select bit (1) 0: Low-speed on-chip oscillator selected (2) 1: High-speed on-chip oscillator selected R/W b2 — Reserved bit Set to 0. R/W b3 FRA03 fOCO128 clock select bit 0: fOCO-S divided by 128 selected 1: fOCO-F divided by 128 selected R/W b4 — Reserved bits Set to 0. R/W b5 — b6 — b7 —

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 151 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 10. Power ControlR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

10.2.6 Voltage Detect Register 2 (VCA2)

Notes: 1. Use the VCA20 bit only when the MCU enters wait mode. To set the VCA20 bit, follow the procedure shown in Figure 10.7 Handling Procedure for Reducing Internal Power Consumption Using VCA20 Bit. 2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop mode). 3. To use voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection circuit starts operation. 4. To use the voltage detection 1/comparator A1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1/comparator A1 circuit starts operation. 5. To use the voltage detection 2/comparator A2 interrupt or the VCAC13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2/comparator A2 circuit starts operation. Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register. Address 0034h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol VCA27 VCA26 VCA25 VCA24 VCA23 VCA22 VCA21 VCA20 After Reset The LVDAS bit in the OFS register is set to 1. 00000000 After Reset The LVDAS bit in the OFS register is set to 0. 00100000 Bit Symbol Bit Name Function R/W b0 VCA20 Internal power low consumption enable bit (1) 0: Low consumption disabled 1: Low consumption enabled (2) R/W b1 VCA21 Comparator A1 reference voltage input select bit 0: Internal reference voltage 1: LVREF pin input voltage R/W b2 VCA22 LVCMP1 comparison voltage external input select bit 0: Supply voltage (VCC) 1: LVCMP1 pin input voltage R/W b3 VCA23 Comparator A2 reference voltage input select bit 0: Internal reference voltage 1: LVREF pin input voltage R/W b4 VCA24 LVCMP2 comparison voltage external input select bit 0: Supply voltage (VCC) (Vdet2_0) 1: LVCMP2 pin input voltage (Vdet2_EXT) R/W b5 VCA25 Voltage detection 0 enable bit (3) 0: Voltage detection 0 circuit disabled 1: Voltage detection 0 circuit enabled R/W b6 VCA26 Voltage detection 1/comparator A1 enable bit (4) 0: Voltage detection 1/comparator A1 circuit disabled 1: Voltage detection 1/comparator A1 circuit enabled R/W b7 VCA27 Voltage detection 2/comparator A2 enable bit (5) 0: Voltage detection 2/comparator A2 circuit disabled 1: Voltage detection 2/comparator A2 circuit enabled R/W

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10.2.7 Power-Off Mode Cont rol Register 0 (POMCR0)

Note: 1. Write to the POMCR0 register five times successively to enter power-off mode. Address 0020h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol POM07 POM06 POM05 POM04 POM03 POM02 POM01 POM00 A f t e r R e s e t X0000000 Initial write: Selection of the pin status in power-off mode and the exit methods Bit Symbol Bit Name Function R/W b0 POM00 Power-off mode select bit 0: Power-off 0 (all functions stop) 1: Power-off 1 (timer RE enabled) W b1 POM01 Reserved bits Set to 0. W b2 POM02 W b3 POM03 WKUP1 input enable bit 0: Input disabled 1: Input enabled W b4 POM04 Reserved bits Set to 0. W b5 POM05 W b6 POM06 W b7 POM07 W Second to fifth write: Entering power-off mode Bit Function R/W b7 to b0 Write 88h, 15h, 92h, and 25h successively. W Read Bit Symbol Bit Name Function R/W b0 POM00 WKUP0 source power-off exit flag 0: Undetected 1: Detected R b1 POM01 WKUP1 source power-off exit flag 0: Undetected 1: Detected R b2 — Nothing is assigned. When read, the content is undefined. R b3 — b4 — b5 — b6 POM06 Timer RE source power-off exit flag 0: Undetected 1: Detected R b7 — Nothing is assigned. When read, the content is undefined. R

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10.3 Standard Operating Mode

Table 10.2 lists the Clock Selection in Standard Operating Mode. In standard operating mode, the CPU and peripheral function clocks are supplied to operate the CPU and the peripheral functions. Power control is enabled by contro lling the CPU clock frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the more power consumption decreases. If unnecessary oscillator circuits stop, power consumption is further reduced. Before the clock sources for the CPU clock can be switch ed over, the new clock source needs to be oscillating and stable. If the new clock source is the XIN clock or XCIN clock, allow sufficient wait time in a program until oscillation stabilizes before the MCU exits. −: Indicates that either 0 or 1 can be set. Table 10.2 Clock Selection in Standard Operating Mode Modes OCD Register CM1 Register CM0 Register FRA0 Register OCD2 CM17 CM16 CM14 CM13 CM07 CM06 CM05 CM04 CM03 FRA01 FRA00 High-speed clock mode No division 0 0 0 − 1 000 −− − − Divide-by-2 0 0 1 − 1 000 −− − − Divide-by-4 0 1 0 − 1 000 −− − − Divide-by-16 0 1 1 − 1 000 −− − − Low-speed clock mode No division − 00 −− 10 − 00 −− Divide-by-2 − 01 −− 10 − 00 −− Divide-by-4 − 10 −− 10 − 00 −− Divide-by-16 − 11 −− 10 − 00 −− High-speed on-chip oscillator mode No division 1 0 0 Divide-by-2 1 0 1 −− 00 −−− 11 Divide-by-4 1 1 0 −− 00 −−− 11 Divide-by-16 1 1 1 −− 00 −−− 11 Low-speed on-chip oscillator mode No division 1 0 0 0 Divide-by-2 1 0 1 0 − 00 −−− 0 − Divide-by-4 1 1 0 0 − 00 −−− 0 − Divide-by-16 − 110 − 00 −−− 0 −

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10.3.1 High-Speed Clock Mode

The XIN clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. When the CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on), fOCO can be used for timer RA. Also, when the FRA00 bit is set to 1, fOCO40M can be used for timers RC, RD, and RG . When the CM14 bit is set to 0 (low-s peed on-chip oscillator on), fOCO-S can be used for the voltage detection circuit.

10.3.2 Low-Speed Clock Mode

The XCIN clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. In this mode, low consumption operation is enabled by stopping the XIN clock and the high-speed on-chip oscillator, and by setting the FMR27 bit in the FMR2 register to 1 (flash memory low-consumption-current read mode enabled). Also, when the FRA00 bit is set to 1, fOCO40M can be used for timers RC, RD, and RG . When the CM14 bit is set to 0 (low-s peed on-chip oscillator on), fOCO-S can be used for the voltage detection circuit. To enter wait mode from low-speed clock mode, lower consumption current in wait mode is enabled by setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled). To reduce the power consumption, refer to 10.7 Reducing Power Consumption.

10.3.3 High-Speed On-Chip Oscillator Mode

The high-speed on-chip oscillator is used as the on-chip oscillator clock when the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The on- chip oscillator divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. When the FRA00 bit is set to 1, fOCO40M can be used for timers RC, RD, and RG . Also, when the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection circuit.

10.3.4 Low-Speed On-C hip Oscillator Mode

When the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 0, the low-speed on-chip oscillator is used as the on-chip oscillator clock. At this time, the on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 is used as the CPU clock. The on-chip oscillator clock is also the clock source for the peri pheral function clocks. When the FRA00 bit is set to 1, fOCO40M can be used for timers RC, RD, and RG. Also, When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection circuit. In this mode, low consumption operation is enabled by stopping the XIN clock and the high-speed on-chip oscillator, and by setting the FMR27 bit in the FMR2 register to 1 (flash memory low-consumption-current read mode enabled). To enter wait mode from low-speed clock mode, current consumption in wait mode can be further reduced by setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled). To reduce the power consumption, refer to 10.7 Reducing Power Consumption.

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10.4 Wait Mode

Since the CPU clock stops in wait mode, CPU operation using the CPU clock and watchdog timer operation with count source protection mode disabled are halted. Howeve r, the XIN clock, XCIN clock, and on-chip oscillator clock do not stop, so peripheral functions using these clocks continue operating.

10.4.1 Peripheral Funct ion Clock Stop Function

The peripheral function clock to stop in wait mode can be selected by setting bits CM01 and CM02 in the CM0 register (peripheral functi on clock stop bits in wait mode). Th is controls power consumption according to applications.

10.4.2 Entering Wait Mode

The MCU enters wait mode by executing the WAIT instruction or setting the CM30 bit in the CM3 register to 1 (MCU enters wait mode). When the OCD2 bit in the OCD register is set to 1 (on- chip oscillator selected as system clock), set the OCD1 bit in the OCD register to 0 (oscillation stop det ection interrupt disabled) before executing the WAIT instruction or setting the CM30 bit in the CM3 register to 1 (MCU enters wait mode). If the MCU enters wait mode while the OCD1 bit is set to 1 (oscillation stop detection interrupt enabled), current consumption is not reduced because the CPU clock does not stop.

10.4.3 Pin Status in Wait Mode

Each I/O port retains its states immediately before the MCU enters wait mode.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 156 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 10. Power ControlR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

10.4.4 Exiting Wait Mode

The MCU exits wait mode by a reset or peripheral function interrupt. The peripheral function interrupts are affected by bits CM01 and CM02. The following interrupts can be used to exit wait mode:

• When bits CM02 to CM01 are set to 00b (peripheral fu nction clock does not stop in wait mode), peripheral function interrupts other than A/D conversion interrupts.
• When bits CM02 to CM01 are set to 01b (clocks f1 to f32 stop in wait mode), the interrupts of the peripheral functions operating with external signals, the on-chip oscillator clock, or clocks fC1 to f32.
• When bits CM02 to CM01 are set to 10b (clocks f1 to f32 and fC stop in wait mode), the interrupts of the peripheral functions operating with external signals or the on-chip oscillator clock.
• When bits CM02 to CM01 are set to 11b (clocks f1 to f32, fC, and fC-LCD stop in wait mode), the same applies when bits CM02 to CM01 are set to 10b. Table 10.3 lists Interrupts to Exit Wait Mode and Usage Conditions. Table 10.3 Interrupts to Exit Wait Mode and Usage Conditions Interrupt CM02 to CM01 = 00b CM02 to CM01 = 01b CM02 to CM01 = 10b CM02 to CM01 = 11b Serial interface interrupt Usable when operating with an internal or external clock. Usable when operating with fC or an external clock. Usable when operating with an external clock. Usable when operating with an external clock. Clock synchronous serial I/O with chip select interrupt / I2C bus interface interrupt Usable in all modes. (Do not use.) (Do not use.) (Do not use.) Key input interrupt Usab le Usable Usable Usable A/D conversion interrupt (Do not use.) (Do not use.) (Do not use.) (Do not use.) Timer RA interrupt Usable in all modes. Usable if there is no filter in event counter mode. Usable by selecting fOCO, fC, or fC32 as the count source. Usable if there is no filter in event counter mode. Usable by selecting fOCO as the count source. Usable if there is no filter in event counter mode. Usable by selecting fOCO as the count source. Timer RB interrupt Usable in all modes. (Do not use.) (Do not use.) (Do not use.) Timer RC interrupt Usable in all modes. (Do not use.) (Do not use.) (Do not use.) Timer RD interrupt Usable in all modes. Usable by selecting fOCO40M as the count source. Usable by selecting fOCO40M as the count source. Usable by selecting fOCO40M as the count source. Timer RE interrupt Usable in all modes. Usable when operating in real time clock mode. Usable when operating in real time clock mode. Usable when operating in real time clock mode. Timer RG interrupt Usable in all modes. (Do not use.) (Do not use.) (Do not use.) INT interrupt Usable Usable if there is no filter. Usable if there is no filter. Usable if there is no filter. Voltage monitor 1 interrupt Usable Usable Usable Usable Voltage monitor 2 interrupt Usable Usable Usable Usable Oscillation stop detection interrupt Usable (Do not use.) (Do not use.) (Do not use.) Watchdog timer interrupt Usable in count source protection mode. Usable in count source protection mode. Usable in count source protection mode. Usable in count source protection mode. Comparator A1 interrupt Usable Usable Usable Usable Comparator A2 interrupt Usable Usable Usable Usable LCD counter interrupt Usable Usable by selecting fC- LCD as the count source. Usable by selecting fC- LCD as the count source. (Do not use.)

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10.5 Stop Mode

All oscillator circuits except fOCO-WDT stop in stop mode. Since the CPU clock and the peripheral function clock stop, CPU operation and peripheral functi on operation using these clocks are halted. If the voltage applied to the VCC pin is VRAM or more, the content of internal RAM is retained. The peripheral functions clocked by external signals continue operating. Table 10.4 lists Interrupts to Exit Stop Mode and Usage Conditions.

10.5.1 Entering Stop Mode

The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode). To use stop mode, set the following before the MCU enters stop mode:

• Bits OCD1 to OCD0 in the OCD register = 00b
• CM35 bit in CM3 register = 0 (settings of CM06 bi t in CM0 register and bits CM16 and CM17 in CM1 register enabled)

10.5.2 Pin Status in Stop Mode

Each I/O port retains its state before the MCU enters stop mode. However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pin), the XOUT (P12_0) pin is held high. Table 10.4 Interrupts to Exit Stop Mode and Usage Conditions Interrupt Usage Conditions Key input interrupt − INT interrupt Usable if there is no filter. Timer RA interrupt Usable if there is no filter when an external pulse is counted in event counter mode. Serial interface interrupt When an external clock is selected. Voltage monitor 1 interrupt Usable in digital filter disabled mode (the VW1C1 bit in the VW1C register is set to 1). Voltage monitor 2 interrupt Usable in digital filter disabled mode (the VW2C1 bit in the VW2C register is set to 1). Comparator A1 interrupt Usable in digital filter disabled mode (the VW1C1 bit in the VW1C register is set to 1). Comparator A2 interrupt Usable in digital filter disabled mode (the VW2C1 bit in the VW2C register is set to 1).

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10.5.3 Exiting Stop Mode

The MCU exits stop mode by a reset or peripheral function interrupt. Figure 10.4 shows the Time from Stop Mode to Interrupt Routine Execution. To use a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to 1. (1) Set the interrupt priority level in bits ILVL2 to IL VL0 of the peripheral function interrupts to be used for exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for exiting stop mode to 000b (interrupt disabled). (2) Set the I flag to 1. (3) Operate the peripheral function to be used for exiting stop mode. When the MCU exits stop mode by a peripheral function interrupt, the interrupt sequence is executed when an interrupt request is generated and the CPU clock supply starts. The clock used immediately before stop mode divided by 8 is used as the CPU clock when the MCU exits stop mode by a peripheral function interrupt. To enter stop mode, set the CM35 bit in the CM3 register to 0 (settings of CM06 bit in CM0 register and bits CM16 and CM17 in CM1 register enabled). Figure 10.4 Time from Stop Mode to Interrupt Routine Execution Interrupt request generation 100 µs (max.) Stop mode Internal power stabilization time Oscillation time of CPU clock source used immediately before stop mode T4T2 Interrupt sequenceFlash memory activation sequence CPU clock restart sequence 100 µs (max.) Internal Power Stabilization Time (T0) 100 µs (max.) Period of system clock × 1 cycle + 60 µs (max.) Period of system clock × 1 cycle Period of CPU clock × 2 cycles Same as above Time until CPU Clock Supply (T3) Time until Flash Memory Activation (T2) Time for Interrupt Sequence (T4) Period of CPU clock × 20 cycles Same as above FMSTP Bit (flash memory operates) (flash memory stops) FMR0 Register The total of T0 to T4 is the time from wait mode until an interrupt routine is executed. Remarks

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10.6 Power-Off Mode

All functions stop in power-off mode. However, the low-speed clock and timer RE functions can be set to operate or stop by means of register settings. The least power is consumed in this mode.

10.6.1 Pin Handling in Power-Off Mode

Figure 10.5 shows Pin Handling in Power-Off Mode. To use this mode, hardware reset input is required. For details of hardware resets, refer to 5.2 Hardware Reset.

10.6.2 Entering Power-Off Mode

Table 10.5 lists the register settings in power-off mode. The pin status in power-off mode and the method of exiting are selected by the initial write to the POMCR0 register. When 88h, 15h, 92h, and 25h are then written successively, the MCU enters power-off mode.

• Power-off 0 When the POM00 bit is set to 0 (power-off 0) by the initial write, all functions stop once the MCU enters power-off mode.
• Power-off 1 When the POM00 bit is set to 1 (power-off 1) by the initial write, all functions except the low-speed clock and timer RE stop once the MCU enters power-off mode. Th e timer RE interrupt can be used to exit the mode when power-off 1 is selected. An access to another register during the write to the POMCR0 register does not affect entering the mode.

10.6.3 Pin Status in Power-Off Mode

Table 10.6 lists the Pin Status in Power-Off Mode. Wh en the MCU enters power-off mode, the contents of RAM and registers are not retained. Save the data needs to be retained to the data flash before entering power- off mode. Figure 10.5 Pin Handling in Power-Off Mode (1) When power-off mode is used Always pull up WKUP0. Pull up WKUP1 when selected as the exit source. Input a low-level signal to exit the mode. MCU VCC WKUP0 WKUP1 RESET Input a hardware reset as reset input. For details of resets, refer to 5.2 Hardware Reset. RESET WKUP0 VCC MCU (2) When power-off mode is not used Connect WKUP0 to VSS. A hardware reset or the power-on reset function can be used as reset input.

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10.6.4 Exiting Power-Off Mode

To exit power-off mode, input a low signal pulse to the RESET , WKUP0, or WKUP1 pin or use the timer RE interrupt (power-off 1 is selected). The timer RE interrupt enabled in the TREC2 register can be used to exit the mode. After exiting power-off mode, the operation is the same as a normal reset sequence. When power-off mode is exit ed, the exit source can be id entified by reading the fl ags in the SDCR0 register. The values of these flags are undefined after power-on and set to 0 by writing to the SDCR0 register. If multiple exit sources coincide, multiple flags are set. Figure 10.6 show the Time from Power-Off Mode to Reset Vector Address Read Execution. Notes: 1. To use WKUP1 to exit power-off mode, set the POM03 bit to 1 (input enabled) by the initial write to the POMCR0 register. 2. To use timer RE to exit power-off mode, enable the timer RE interrupt in registers TREIC and TRECR2, then set the POM00 bit in the POMCR0 register to 1 (timer RE enabled). When all interrupts are disabled by the TRECR2 register, the low-speed clock and timer RE functions operate, but timer RE cannot be used to exit power-off mode. Figure 10.6 Time from Power-Off Mode to Reset Vector Address Read Execution Table 10.5 Entering Power-Off Mode and Exit Methods Entering Power-Off Mode Status Exit Method Write the pin state and the exit method to the POMCR0 register (1, 2) in power-off mode. Then, write 88h,15h, 92h, and 25h successively. All functions stop when the SDC00 bit is set to 0 (power-off 0) by the initial write. RESET input, WKUP0 input, or WKUP1 input Functions other the low-speed clock and timer RE stop when the SDC00 bit is set to 1 (power-off 1) by the initial write. RESET input, timer RE interrupt, WKUP0 input, or WKUP1 input Table 10.6 Pin Status in Power-Off Mode Pin Name Status Ports P0 to P7 The states of registers LSE0 to LSE7 before entering power-off mode are retained. When LCD ports are selected by these registers, low-level output. When ports are selected, the pins are placed in the high-impedance state. Ports 10 to P13 High impedance WKUP0 WKUP0 input XCIN, XCOUT Oscillation is off (high impedance) at power-off 0, and oscillation is on at power-off 1. VL1 to VL4 High impedance Power-off mode Power-off exit source generation Internal reset time Internal power stabilization time Flash memory activation sequence Idling time Note: 1. If the with of low-level input to the RESET or WKUP0 pin exceeds the internal power stabilization time and internal reset time (T0 +T1), the excess is added to the time until a reset vector address is read. 64 µs (fOCO-S clock × 8 cycles) Idling Time (T3) 224 µs CPU clock × 28 cycles Remarks The total of T0 to T3 is the time from power-off mode until a reset vector address is read. Max. 1,424 µs CPU clock × 108 to 178 cycles Time until Flash Memory Activation (T2)Internal Reset Time (T1)Internal Power Stabilization Time (T0) Max. 2 ms

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10.7 Reducing Power Consumption

This section describes key points and processing methods for reducing power consumption. They should be referred to when designing a system or creating a program.

10.7.1 Voltage Detection Circuit

When voltage monitor 1 and comparator A1 are not used, set the VCA26 bit in the VCA2 register to 0 (voltage detection 1 circuit disabled). When voltage monitor 2 and comparator A2 are not used, set the VCA27 bit in the VCA2 register to 0 (voltage detection 2 circuit disabled). When power-on reset and voltage monitor 0 reset are not used, set the VCA25 bit in the VCA2 register to 0 (voltage detection 0 circuit disabled).

10.7.2 Ports

Even after the MCU enters wait mode or stop mode, the states of the I/O ports are retained. Current flows into the output ports in the active state, and shoot-through current flows into the input ports in the high-impedance state. Unnecessary ports should be set to input and fixe d to a stable electric potential before the MCU enters wait mode or stop mode.

10.7.3 Clocks

Power consumption generally depends on the number of the operating clocks and th eir frequencies. The fewer the number of operating clocks or the lower their frequencies, the more power consumption decreases. Unnecessary clocks should be stopped accordingly. Stopping the low-speed on-chip oscillator oscillation: CM14 bit in CM1 register Stopping the high-speed on-chip oscillator oscillation: FRA00 bit in FRA0 register

10.7.4 Wait Mode, Stop M ode, and Power-Off Mode

Power consumption can be reduced in wait mode, stop mode, and power-off mode.

10.7.5 Stopping Peripheral Function Clocks

When peripheral function clocks are not necessary in wait mode, set bi ts CM01 and CM02 bit in the CM0 register to stop the clock.

10.7.6 Timers

When timer RA is not used, set the TCKCUT bit in the TRAMR register to 1 (count source cutoff). When timer RB is not used, set the TCKCUT bit in the TRBMR register to 1 (count source cutoff). When timer RC is not used, set the MSTTRC bit in the MSTCR register to 1 (standby). When timer RD is not used, set the MSTTRD bit in the MSTCR register to 1 (standby). When timer RG is not used, set the MSTTRG bit in the MSTCR register to 1 (standby).

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10.7.7 A/D Converter

When the A/D converter is not used , power consumption can be reduced by setting the ADSTBY bit in the ADCON1 register to 0 (A/D operation stops (standby)) to shut off any analog circuit current flow.

10.7.8 Clock Synchronous Serial Interface

When the SSU or I2C bus is not used, set the MSTIIC bit in the MSTCR register to 1 (standby).

10.7.9 Reducing Internal Power Consumption

When the MCU enters wait mode using low-speed clock mode or low-speed on-chip oscillator mode, internal power consumption can be reduced by using the VCA 20 bit in the VCA2 register. Figure 10.7 shows the Handling Procedure for Reducing Internal Power Consum ption Using VCA20 Bit. To enable reduced internal power consumption by the VCA20 bit, follow this procedure. Figure 10.7 Handling Procedure for Reducing In ternal Power Consumption Using VCA20 Bit Notes: 1. Execute this routine to handle all interrupts generated in wait mode. However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine. 2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite. 3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode). 4. When the MCU enters wait mode, follow 10.4 Wait Mode. Procedure for enabling reduced internal power consumption using the VCA20 bit Enter low-speed clock mode or low-speed on-chip oscillator mode Stop the XIN clock and the high-speed on-chip oscillator clock VCA20 ← 1 (internal power low consumption enabled) (2, 3) Enter wait mode (4) VCA20 ← 0 (internal power low consumption disabled) (2) Start the XIN clock or the high-speed on-chip oscillator clock (Wait until the XIN clock or the high-speed on-chip oscillator clock oscillation stabilizes) Enter high-speed clock mode or high-speed on-chip oscillator mode In the interrupt routine VCA20 ← 0 (internal power low consumption disabled) (2) (This is automatically set when exiting wait mode) Start the XIN clock or the high-speed on-chip oscillator clock Enter high-speed clock mode or high-speed on-chip oscillator mode Enter low-speed clock mode or low-speed on-chip oscillator mode Exit wait mode by interrupt Stop the XIN clock and the high-speed on-chip oscillator clock VCA20 ← 1 (internal power low consumption enabled) (2, 3) Interrupt handling completed Step (1) Step (2) Step (3) Step (4) Step (5) Step (6) Step (7) Step (8) Step (5) Step (6) Step (7) Step (8) (Wait until the XIN clock or the high-speed on-chip oscillator clock oscillation stabilizes) Step (1) Step (2) Step (3) If it is necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine, execute steps (6) and (7) in the routine. If the high-speed clock or high-speed on-chip oscillator starts during the interrupt routine, execute steps (1) to (3) at the end of the routine. (Note 1) Interrupt handling VCA20: Bit in VCA2 register

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10.7.10 Stopping Flash Memory

In low-speed on-chip oscillator mode and low-speed clock mode, power consumption can be further reduced by stopping the flash memory using the FMSTP bit in the FMR0 register. Access to the flash memory is disabled by setting the FMSTP bit to 1 (flash memo ry stops). The FMSTP bit must be written to by a program transferred to RAM. When the MUC enters stop mode or wait mode while CPU rewrite mode is disabl ed, the power for the flash memory is automatically turned off. It is turned back on again after the MCU exit stop mode or wait mode. This eliminates the need to set the FMR0 register. Figure 10.8 shows the Handling Procedure Example for Reducing Power Consumption Using FMSTP Bit. Figure 10.8 Handling Procedure Example for Re ducing Power Consumption Using FMSTP Bit FMSTP bit setting program Transfer the FMSTP bit setting program to RAM Jump to the FMSTP bit setting program (The subsequent processing is executed by the program in the RAM) After writing 0 to the FMR01 bit, write 1 (CPU rewrite mode enabled) Enter low-speed clock mode or low-speed on-chip oscillator mode Process in low-speed clock mode or low-speed on-chip oscillator mode Write 0 to the FMR01 bit (CPU rewrite mode disabled) Jump to the specified address in the flash memory Notes: 1. After setting the FMR01 bit to 1 (CPU rewrite mode enabled), set the FMSTP bit to 1 (flash memory stops). 2. Before switching the CPU clock source, make sure the designated clock is stable. 3. Insert a wait time of 60 µs by a program. Do not access the flash memory during this wait time. Write 1 to the FMSTP bit (flash memory stops. low power consumption state) (1) Wait until the flash memory circuit stabilizes (60 µs) (3) Write 0 to the FMSTP bit (flash memory operates) Switch the clock source for the CPU clock (2) FMR01, FMSTP: Bits in FMR0 register Stop the high-speed on-chip oscillator

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10.7.11 Low-Current-Cons umption Read Mode

In low-speed clock mode and low-speed on-chip oscill ator mode, the current consumption when reading the flash memory can be reduced by setting the FMR27 bit in the FMR2 register to 1 (enabled). Figure 10.9 shows the Handling Procedure Example of Low-Current-Consumption Read Mode. Figure 10.9 Handling Procedure Example of Low-Current-Consumption Read Mode Notes: 1. To set the FMR27 bit to 1, first write 0 and then write 1 immediately. After writing 0, do not generate an interrupt before writing 1. 2. In low-current-consumption read mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled). Handling procedure for enabling low-current-consumption read mode by the FMR27 bit Step (1) Step (2) Step (3) Step (4) Step (5) Step (6) Step (7) Step (8) FMR27: Bit in FMR2 register Enter low-speed clock mode or low-speed on-chip oscillator mode Stop the high-speed on-chip oscillator clock FMR27 ← 1 (low-current-consumption read mode enabled) (1) Enter low-current-consumption read mode (2) FMR27 ← 0 (low-current-consumption read mode disabled) Start the high-speed on-chip oscillator clock (Wait until the high-speed on-chip oscillator clock oscillation stabilizes) Enter high-speed on-chip oscillator mode

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10.8 Notes on Power Control

10.8.1 Stop Mode

To enter stop mode, set the FMR01 bit in the FMR0 regi ster to 0 (CPU rewrite mode disabled) and then the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops. Insert at least four NOP instructions following the JM P.B instruction after the instruction which sets the CM10 bit to 1.

• Program example to enter stop mode BCLR 1, FMR0; CPU rewrite mode disabled BSET 0, PRCR; Protect disabled FSET I; Enable interrupt BSET 0, CM1; Stop mode JMP.B LABEL_001 LABEL_001: NOP NOP NOP NOP

10.8.2 Wait Mode

To enter wait mode with the WAIT instruction, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then execute the WAIT instruction. An instruction queu e pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least four NOP instructions after the WAIT instruction.

• Program example to execute the WAIT instruction BCLR 1, FMR0; CPU rewrite mode disabled FSET I; Enable interrupt WAIT; Wait mode NOP NOP NOP NOP

10.8.3 Power-Off Mode

To enter power-off mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then access the POMCR0 register. A period of a few micro seconds is required between accessing the POMCR0 register and entering power-off mode. As the CPU continues to operate during this period, insert the NOP and the WAIT instructions to stop the program.

• Program example to enter power-off mode (when timer RE and the low-speed clock is enabled) BCLR 1, FMR0; CPU rewrite mode disabled MOV . B #08H, POMCR0; Select power-off 0 and WKUP1 input enabled MOV . B #88H, POMCR0; Fixed value MOV . B #15H, POMCR0; Fixed value MOV . B #92H, POMCR0; Fixed value MOV . B #25H, POMCR0; Fixed value NOP; NOP; NOP; NOP; Enter power-off mode WAIT; Wait mode

1. Protection REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 168 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 11. Protection The protection function protects important registers from being easily overwritten if a program runs out of control. The registers protected by the PRCR register are as follows:

• Registers protected by PRC0 bit: Registers CM0, CM1, CM3, OCD, FRA0, FRA1, FRA2, and FRA3
• Registers protected by PRC1 bit: Registers PM0 and PM1
• Registers protected by PRC2 bit: PD0 register
• Registers protected by PRC3 bit: Registers OCVREFCR, VCA2, VD1LS, VW0C, VW1C, and VW2C

11.1 Register

11.1.1 Protect Register (PRCR)

Note: 1. The PRC2 bit is set to 0 after writing 1 to it and execut ing a write to any address. Since the other bits are not set to 0, set them to 0 by a program. Address 000Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — PRC3 PRC2 PRC1 PRC0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 PRC0 Protect bit 0 Enables writing to registers CM0, CM1, CM3, OCD, FRA0, FRA1, FRA2, and FRA3. 0: Write disabled 1: Write enabled R/W b1 PRC1 Protect bit 1 Enables writing to registers PM0 and PM1. 0: Write disabled 1: Write enabled R/W b2 PRC2 Protect bit 2 Enables writing to the PD0 register. 0: Write disabled 1: Write enabled (1) R/W b3 PRC3 Protect bit 3 Enables writing to registers OCVREFCR, VCA2, VD1LS, VW0C, VW1C, and VW2C. 0: Write disabled 1: Write enabled R/W b4 — Reserved bits Set to 0. R/W b5 — b6 — Reserved bits When read, the content is 0. R b7 —

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12.1 Introduction

12.1.1 Types of Interrupts

Figure 12.1 shows the Types of Interrupts. Figure 12.1 Types of Interrupts

• Maskable interrupts: These interrupts are enabled or disabled by the interrupt enable flag (I flag). The interrupt priority can be changed based on the interrupt priority level.
• Non-maskable interrupts: These interrup ts are not enabled or disabled by the interrupt enable flag (I flag). The interrupt priority cannot be changed based on the interrupt priority level. Interrupts (non-maskable interrupts) Hardware Software (non-maskable interrupts) (maskable interrupts) Special Peripheral function (1) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Watchdog timer Oscillation stop detection Voltage monitor 1 / compatator A1 (3) Voltage monitor 2 / compatator A2 (3) Single step (2) Address break (2) Address match Notes: 1. A peripheral function interrupt is generated by a peripheral function in the MCU. 2. Do not use these interrupts. These are provided exclusively for use by development tools. 3. A non-maskable or maskable interrupt can be selected by bits IREQ1SEL and IREQ2SEL in the CMPA register.

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12.1.2 Software Interrupts

A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.

12.1.2.1 Undefined Instruction Interrupt

An undefined instruction interrupt is generated when the UND instruction is executed.

12.1.2.2 Overflow Interrupt

An overflow interrupt is generated wh en the O flag is set to 1 (arithmetic operation overflow) and the INTO instruction is executed. Instructions that set the O flag are as follows: ABS, ADC, ADCF, ADD, CMP, DIV , DIVU, DIVX, NEG , RMPA, SBB, SHA, and SUB.

12.1.2.3 BRK Interrupt

A BRK interrupt is generated when the BRK instruction is executed.

12.1.2.4 INT Instruction Interrupt

An INT instruction interrupt is generated when the INT instruction is executed. Software interrupt numbers 0 to 63 can be specified with the INT instruction. Because software interrupt numbers are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction. For software interrupt numbers 0 to 31, the U flag is saved on the stack during in struction execution and the U flag is set to 0 (ISP selected) before the interrupt sequ ence is executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.

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12.1.3 Special Interrupts

Special interrupts are non-maskable.

12.1.3.1 Watchdog Timer Interrupt

A watchdog timer interrupt is generated by the watchdog timer. For details, refer to 15. Watchdog Timer.

12.1.3.2 Oscillation Stop Detection Interrupt

An oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the oscillation stop detection function, refer to 9. Clock Generation Circuit.

12.1.3.3 Voltage Monitor 1/Comparator A1 Interrupt

A voltage monitor 1/Comparator A1 interrupt is generated by the voltage detection circuit or the comparator A. A non-maskable or maskable interrupt can be selected by IRQ1SEL bit in the CMPA register. For details of the voltage detection circuit, refer to 6. Voltage Detection Circuit and for details of the comparator A, refer to 32. Comparator A.

12.1.3.4 Voltage Monitor 2/Comparator A2 Interrupt

A voltage monitor 2/Comparator A2 interrupt is generated by the voltage detection circuit or the comparator A. A non-maskable or maskable interrupt can be selected by IRQ2SEL bit in the CMPA register. For details of the voltage detection circuit, refer to 6. Voltage Detection Circuit and for details of the comparator A, refer to 32. Comparator A.

12.1.3.5 Single-Step Interrupt , Address Break Interrupt

Do not use these interrupts. They are provided exclusively for use by development tools.

12.1.3.6 Address Match Interrupt

An address match interrupt is generated immediately before executing an instruction that is stored at an address indicated by registers RMAD0 to RMAD1 if the AIER0 b it in the AIER0 register or AIER1 bit in the AIER1 register is set to 1 (address match interrupt enabled). For details of the address match interrupt, refer to 12.6 Address Match Interrupt.

12.1.4 Peripheral Function Interrupts

A peripheral function interrupt is generated by a peripheral function in the MCU. Peripheral function interrupts are maskable. Refer to Table 12.2 Relocatable Vector Tables for sources of the corresponding peripheral function interrupt. For details of peripheral functions , refer to the descriptions of individual peripheral functions.

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12.1.5 Interrupts and Interrupt Vectors

There are 4 bytes in each vector. Set the starting addre ss of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector. Figure 12.2 shows an Interrupt Vector. Figure 12.2 Interrupt Vector

12.1.5.1 Fixed Vector Tables

The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh. Table 12.1 lists the Fixed Vector Ta bles. The vector addresses (H) of fi xed vectors are used by the ID code check function. For details, refer to 35.3 Functions to Prevent Flash Memory from being Rewritten. Note: 1. Do not use these interrupts. They are provid ed exclusively for use by development tools. Table 12.1 Fixed Vector Tables Interrupt Source Vector Addresses Address (L) to (H) Remarks Reference Undefined instruction 0FFDC h to 0FFDFh Interrupt with UND instruction R8C/Tiny Series Software Manual Overflow 0FFE0h to 0FFE3h Interrupt with INTO instruction BRK instruction 0FFE4h to 0FFE7h If the content of address 0FFE7h is FFh, program execution starts from the address shown by the vector in the relocatable vector table. Address match 0FFE8h to 0FFEBh 12.6 Address Match Interrupt Single step (1) 0FFECh to 0FFEFh Watchdog timer, Oscillation stop detection, Voltage monitor 1/ comparator A1, Voltage monitor 2/ comparator A2 0FFF0h to 0FFF3h 15. Watchdog Timer, 9. Clock Generation Circuit, 6. Voltage Detection Circuit, 32. Comparator A Address break (1) 0FFF4h to 0FFF7h (Reserved) 0FFF8h to 0FFFBh Reset 0FFFCh to 0FFFFh 5. Resets Vector address (L) Vector address (H) MSB LSB Low-order address Middle-order address High-order address0 0 0 0 0 0 0 0 0 0 0 0

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12.1.5.2 Relocatable Vector Tables

The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 12.2 lists the Relocatable Vector Tables. Notes: 1. These addresses are relative to those in the INTB register. 2. Selectable by the IICSEL bit in the SSUIICSR register. 3. These interrupts are not disabled by the I flag. Table 12.2 Relocatable Vector Tables Interrupt Source Vector Addresses (1) Address (L) to Address (H) Software Interrupt Number Interrupt Control Register Reference BRK instruction (3) +0 to +3 (0000h to 0003h) 0 − R8C/Tiny Series Software Manual Flash memory ready +4 to +7 (0004h to 0007h) 1 FMRDYIC 35. Flash Memory (Reserved) 2 −− INT7 +12 to +15 (000Ch to 000Fh) 3 INT7IC 12.4 INT Interrupt INT6 +16 to +19 (0010h to 0013h) 4 INT6IC 12.4 INT Interrupt INT5 +20 to +23 (0014h to 0017h) 5 INT5IC 12.4 INT Interrupt INT4 +24 to +27 (0018h to 001Bh) 6 INT4IC 12.4 INT Interrupt Timer RC +28 to +31 (001Ch to 001Fh) 7 TRCIC 20. Timer RC Timer RD0 +32 to +35 (0020h to 0023h) 8 TRD0IC 21. Timer RD Timer RD1 +36 to +39 (0024h to 0027h) 9 TRD1IC Timer RE +40 to +43 (0028h to 002Bh) 10 TREIC 22. Timer RE UART2 transmission/NACK2 +44 to +47 (002Ch to 002Fh) 11 S2TIC 25. Serial Interface (UART2) UART2 reception/ACK2 +48 to +51 (0030h to 0033h) 12 S2RIC Key input +52 to +55 (0034h to 0037h) 13 KUPIC 12.5 Key Input Interrupt A/D conversion +56 to +59 (0038h to 003Bh) 14 ADIC 30. A/D Converter Synchronous serial communication unit/ I 2C bus interface (2) +60 to +63 (003Ch to 003Fh) 15 SSUIC/IIC IC 27. Synchronous Serial Communication Unit (SSU), 28. I2C bus Interface (Reserved) 16 −− UART0 transmission +68 to +71 (0044h to 0047h) 17 S0TIC 24. Serial Interface (UARTi (i = 0 or 1))UART0 reception +72 to +75 (0048h to 004Bh) 18 S0RIC UART1 transmission +76 to +79 (004Ch to 004Fh) 19 S1TIC UART1 reception +80 to +83 (0050h to 0053h) 20 S1RIC INT2 +84 to +87 (0054h to 0057h) 21 INT2IC 12.4 INT Interrupt Timer RA +88 to +91 (0058h to 005Bh) 22 TRAIC 18. Timer RA (Reserved) 23 −− Timer RB +96 to +99 (0060h to 0063h) 24 TRBIC 19. Timer RB INT1 +100 to +103 (0064h to 0067h) 25 INT1IC 12.4 INT Interrupt INT3 +104 to +107 (0068h to 006Bh) 26 INT3IC (Reserved) 27 −− (Reserved) 28 −− INT0 +116 to +119 (0074h to 0077h) 29 INT0IC 12.4 INT Interrupt UART2 bus collision detection +120 to +123 (0078h to 007Bh) 30 U2BCNIC 25. Serial Interface (UART2) (Reserved) 31 −− Software (3) +128 to +131 (0080h to 0083h) to +164 to +167 (00A4h to 00A7h) 32 to 41 − R8C/Tiny Series Software Manual (Reserved) 42 −− Timer RG +172 to +175 (00ACh to 00AFh) 43 TRGIC 23. Timer RG (Reserved) 44 to 49 −− Voltage monitor 1/comparator A1 +200 to +203 (00C8h to 00CBh) 50 VCMP1IC 6. Voltage Detection Circuit 32. Comparator AVoltage monitor 2/comparator A2 +204 to +207 (00CCh to 00CFh) 51 VCMP2IC (Reserved) 52 to 55 −− Software (3) +224 to +227 (00E0h to 00E3h) to +252 to +255 (00FCh to 00FFh) 56 to 63 − R8C/Tiny Series Software Manual

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12.2 Registers

(TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0 TIC, S0RIC, S1TIC, S1RIC, TRAIC, TRBIC, U2BCNIC, VCMP1IC, VCMP2IC) Note: 1. Only 0 can be written to the IR bit. Do not write 1 to this bit. Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated. Refer to 12.8.5 Rewriting Interrupt Control Register. Address 004Ah (TREIC), 004Bh (S2TIC), 004Ch (S2RIC), 004Dh (KUPIC), 004Eh (ADIC), 0051h (S0TIC), 0052h (S0RIC), 0053h (S1TIC), 0054h (S1RIC), 0056h (TRAIC), 0058h (TRBIC), 005Eh (U2BCNIC), 0072h (VCMP1IC), 0073h (VCMP2IC), B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l — — — — I R I L V L 2 I L V L 1 I L V L 0 A f t e r R e s e t XXXXX000 Bit Symbol Bit Name Function R/W b0 ILVL0 Interrupt priority level select bit b2 b1 b0 0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 R/W b1 ILVL1 R/W b2 ILVL2 R/W b3 IR Interrupt request bit 0: No interrupt requested 1: Interrupt requested R/W (1) b4 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b5 — b6 — b7 —

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 175 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group (FMRDYIC, TRCIC, TRD0IC, TRD1IC, SSUIC/IICIC, TRGIC) Note: 1. Selectable by the IICSEL bit in the SSUIICSR register. Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated. Refer to 12.8.5 Rewriting Interrupt Control Register. Address 0041h (FMRDYIC), 0047h (TRCIC), 0048h (TRD0IC), 0049h (TRD1IC), 004Fh (SSUIC/IICIC (Note 1)), 006Bh (TRGIC) B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l ————I R I L V L 2 I L V L 1 I L V L 0 A f t e r R e s e t XXXXX000 Bit Symbol Bit Name Function R/W b0 ILVL0 Interrupt priority level select bit b2 b1 b0 0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 R/W b1 ILVL1 R/W b2 ILVL2 R/W b3 IR Interrupt request bit 0: No interrupt requested 1: Interrupt requested R/W (1) b4 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b5 — b6 — b7 —

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 176 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.2.3 INTi Interrupt Control Regi ster (INTiIC) (i = 0 to 7)

Notes: 1. Only 0 can be written to the IR bit. Do not write 1 to this bit. 2. When the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (falling edge selected). 3. The IR bit may be set to 1 (interrupt requested) when the POL bit is rewritten. Refer to

12.8.4 Changing

Interrupt Sources. Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated. Refer to 12.8.5 Rewriting Interrupt Control Register. Address 0043h (INT7IC), 0044h (INT6IC), 0045h (INT5IC), 0046h (INT4IC), 0055h (INT2IC), 0059h (INT1IC), 005Ah (INT3IC), 005Dh (INT0IC) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — POL IR ILVL2 ILVL1 ILVL0 After Reset X X 0 0 X 0 0 0 Bit Symbol Bit Name Function R/W b0 ILVL0 Interrupt priority level select bit b2 b1 b0 0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 R/W b1 ILVL1 R/W b2 ILVL2 R/W b3 IR Interrupt request bit 0: No interrupt requested 1: Interrupt requested R/W (1) b4 POL Polarity switch bit (3) 0: Falling edge selected 1: Rising edge selected (2) R/W b5 — Reserved bit Set to 0. R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b7 —

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 177 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.3 Interrupt Control

The following describes enabling and disabling maskable interrupts and setting the acknowledgement priority. This description does not apply to non-maskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interrupt control register to enable or disable a maskab le interrupt. Whether an inte rrupt is requested or not is indicated by the IR bit in the corresponding interrupt control register.

12.3.1 I Flag

The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts.

12.3.2 IR Bit

The IR bit is set to 1 (interrupt requ ested) when an interrupt request is ge nerated. After the interrupt request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (no interrupt requested). The IR bit can be set to 0 by a program. Do not write 1 to this bit. However, the IR bit operations of the timer RC in terrupt, the timer RD interrupt, the synchronous serial communication unit interrupt the I 2C bus interface interrupt, and the flash memory interrupt are different. Refer to 12.7 Interrupts of Timer RC, Timer RD, Timer RG , Synchronous Serial Communication Unit, I2C bus Interface, and Flash Memory (Interrupts with Multiple Interrupt Request Sources).

12.3.3 Bits ILVL2 to ILVL0, IPL

Interrupt priority levels can be set using bits ILVL2 to ILVL0. Table 12.3 lists the Settings of Interrupt Priority Le vels and Table 12.4 lists th e Interrupt Priority Levels Enabled by IPL. The following are the conditions when an interrupt is acknowledged:

• I flag = 1
• IR bit = 1
• Interrupt priority level > IPL The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another. Table 12.3 Settings of Interrupt Priority Levels Bits ILVL2 to ILVL0 Interrupt Priority Level Priority 000b Level 0 (interrupt disabled) − 001b Level 1 Low 010b Level 2 011b Level 3 100b Level 4 101b Level 5 110b Level 6 111b Level 7 High Table 12.4 Interrupt Priority Levels Enabled by IPL IPL Enabled Interrupt Priority Level 000b Interrupt level 1 and above 001b Interrupt level 2 and above 010b Interrupt level 3 and above 011b Interrupt level 4 and above 100b Interrupt level 5 and above 101b Interrupt level 6 and above 110b Interrupt level 7 and above 111b All maskable interrupts disabled

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 178 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.3.4 Interrupt Sequence

The following describes an interrupt sequence which is performed from when an interrupt request is acknowledged until the interrupt routine is executed. When an interrupt request is generated while an instruct ion is being executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle. However, for the SMOVB, SMOVF, SSTR, or RMPA instruction, if an interrupt request is generated while the instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt sequence is performed as indicated below. Figure 12.3 shows the Time Required for Executing Interrupt Sequence. (1) The CPU obtains interrupt information (interrupt nu mber and interrupt request level) by reading address 00000h. The IR bit for the corresponding interrupt is set to 0 (no interrupt requested). (2) (2) The FLG register is saved to a temporary register (1) in the CPU immediately before entering the interrupt sequence. (3) The I, D and U flags in the FLG register are set as follows: The I flag is set to 0 (interrupts disabled). The D flag is set to 0 (single-step interrupt disabled). The U flag is set to 0 (ISP selected). However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63 is executed. (4) The CPU internal temporary register (1) is saved on the stack. (5) The PC is saved on the stack. (6) The interrupt priority level of the acknowledged interrupt is set in the IPL. (7) The starting address of the interrupt routine se t in the interrupt vector is stored in the PC. After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt routine. Figure 12.3 Time Required for Executing Interrupt Sequence Notes: 1. These registers cannot be accessed by the user. 2. Refer to 12.7 Interrupts of Timer RC, Timer RD, Timer RG , Synchronous Serial Communication Unit, I 2C bus Interface, and Flash Memory (Interrupts with Multiple Interrupt Request Sources) for the IR bit operations of the above interrupts. 123456789 1 0 11 12 13 14 15 16 17 18 19 20 CPU Clock Address Bus Data Bus RD WR Address 0000h Undefined Undefined Undefined Interrupt information SP-2 SP-1 SP-4 SP-3 VEC VEC+1 VEC+2 PC SP-2 content SP-1 content SP-4 content SP-3 content VEC content VEC+1 content VEC+2 content Note: 1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to accept instructions.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 179 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.3.5 Interrupt Response Time

Figure 12.4 shows the Interrupt Response Time. The interrupt response time is the period from when an interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt response time includes the period from when an interru pt request is generated until the currently executing instruction is completed (refer to (a) in Figure 12.4) and the period required for executing the interrupt sequence (20 cycles, refer to (b) in Figure 12.4). Figure 12.4 Interrupt Response Time

12.3.6 IPL Change when Interrupt Request is Acknowledged

When a maskable interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is set in the IPL. When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5 is set in the IPL. Table 12.5 lists the IPL Value When Software or Special Interrupt is Acknowledged. Table 12.5 IPL Value When Software or Special Interrupt is Acknowledged Interrupt Source without Interrupt Priority Level Value Set in IPL Watchdog timer, oscillation stop detection, voltage monitor 1/comparator A1, voltage monitor 2/comparator A2, address break Software, address match, single-step No change Interrupt request generation Interrupt request acknowledgement Instruction Interrupt sequence Instruction in interrupt routine Time (a) 20 cycles (b) Interrupt response time (a) The period from when an interrupt request is generated until the currently executing instruction is completed. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (no wait states if the divisor is a register). (b) 21 cycles for address match and single-step interrupts.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 180 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.3.7 Saving Registers

In the interrupt sequence, the FLG register and PC are saved on the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register, are saved on the stack, the 16 low-order bits in the PC are saved. Figure 12.5 shows the Stack State Before and After Acknowledgement of Interrupt Request. The other necessary registers should be saved by a progr am at the beginning of the interrupt routine. The PUSHM instruction can save several registers in the register bank being currently used (1) with a single instruction. Note: 1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB. Figure 12.5 Stack State Before and After Acknowledgement of Interrupt Request Stack [SP] SP value before interrupt request acknowledgement (1) Previous stack contents LSBMSB Address Previous stack contents m−4 m−3 m−2 m−1 m m+1 Stack state before interrupt request acknowledgement [SP] New SP value (1) Previous stack contents LSBMSB Previous stack contents m m+1 Stack state after interrupt request acknowledgement PCL PCM FLGL FLGH PCH m−4 m−3 m−2 m−1 StackAddress PCL : 8 low-order bits of PC PCM : 8 middle-order bits of PC PCH : 4 high-order bits of PC FLGL : 8 low-order bits of FLG FLGH : 4 high-order bits of FLG Note: 1. When an INT instruction for software numbers 32 to 63 has been executed, this SP is indicated by the U flag. Otherwise it is ISP.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 182 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.3.8 Returning from Interrupt Routine

When the REIT instruction is executed at the end of an interrupt rout ine, the FLG register and PC, which have been saved on the stack, are automatical ly restored. The program, that was running before the interrupt request was acknowledged, starts running again. Registers saved by a program in an interrupt routine s hould be saved using the POPM instruction or a similar instruction before executing the REIT instruction.

12.3.9 Interrupt Priority

If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with the higher priority is acknowledged. Set bits ILVL2 to ILVL0 to select any priority level fo r maskable interrupt s (peripheral function). However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the higher priority interrupts acknowledged. The priority of the watchdog timer and other special interrupts is set by hardware. Figure 12.7 shows the Hardware Interrupt Priority. Software interrupts are not affected by the interrupt priority. When an instruction is executed, the MCU executes the interrupt routine. Figure 12.7 Hardware Interrupt Priority Address break Watchdog timer Oscillation stop detection Voltage monitor 1/comparator A1 Voltage monitor 2/comparator A2 Peripheral function Single step Address match High Low Reset

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 183 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.3.10 Interrupt Priority Level Selection Circuit

The interrupt priority level selection circuit is used to select the highest priority interrupt. Figure 12.8 shows the Interrupt Priority Level Selection Circuit. Figure 12.8 Interrupt Priority Level Selection Circuit UART0 reception UART2 reception/ACK2 UART0 transmission Key input IPL Lowest Highest Peripheral function interrupt priority (if priority levels are same) Interrupt request level select output signal Interrupt request acknowledgementI flag Address match Watchdog timer Oscillation stop detection Voltage monitor 1 / comparator A1 Note: 1. Selectable by the IICSEL bit in the SSUIICSR register. Flash memory ready UART1 transmission Timer RE Timer RD0 Timer RD1 Voltage monitor 2 / comparator A2 INT5 A/D conversion UART2 transmission/ NACK2 SSU / I2C bus (1) Voltage monitor 2 / comparator A2 INT2 INT3 Timer RA Priority level of interrupts Level 0 (initial value) UART1 reception UART2 bus collision detection Timer RB Priority level of interrupts INT1 INT4 INT7 INT6 INT0 Timer RG Voltage monitor 1 / comparator A1 Timer RC

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 184 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.4 INT Interrupt

12.4.1 INTi Interrupt (i = 0 to 7)

The INTi interrupt is generated by an INTi input. To use the INTi interrupt, set the INTiEN bit in the INTEN register is to 1 (enabled). The edge polarity is selected using the INTiPL bit in the INTEN register and the POL bit in the INTiIC register. The input pin used as the INTi input can be selected. Also, inputs can be passed through a digital filter with three different sampling clocks. The INT0 pin is shared with the pulse output forced cutoff input of timer RC and timer RD, and the external trigger input of timer RB. Table 12.6 lists the Pin Configuration of INT Interrupt. Table 12.6 Pin Configuration of INT Interrupt Pin Name Assigned Pin I/O Function INT0 P3_0 or P11_0 Input INT0 interrupt input, timer RB external trigger input, timer RC and timer RD pulse output forced cutoff input INT1 P3_1 or P11_1 Input INT1 interrupt input INT2 P3_2 or P11_2 Input INT2 interrupt input INT3 P3_3 or P11_3 Input INT3 interrupt input INT4 P3_4 or P11_4 Input INT4 interrupt input INT5 P3_5 or P11_5 Input INT5 interrupt input INT6 P3_6 or P11_6 Input INT6 interrupt input INT7 P3_7 or P11_7 Input INT7 interrupt input

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 185 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.4.2 INT Interrupt Input Pi n Select Register (INTSR)

The INTSR register selects which pin is assigned as the INTi (i = 1 to 7) input. To use the INTi, set this register. Set the INTSR register before setting the INTi associated registers. Also, do not change the setting values in this register during INTi operation. Address 018Eh B i t b 7b 6 b 5 b 4b 3b 2b 1 b 0 Symbol INT7SEL0 INT6SEL0 INT5SEL0 INT4SEL 0 INT3SEL0 INT2SEL0 INT1SEL0 INT0SEL0 A f t e r R e s e t 00 0 0000 0 Bit Symbol Bit Name Function R/W b0 INT0SEL0 INT0 pin select bit 0: P3_0 assigned 1: P11_0 assigned R/W b1 INT1SEL0 INT1 pin select bit 0: P3_1 assigned 1: P11_1 assigned R/W b2 INT2SEL0 INT2 pin select bit 0: P3_2 assigned 1: P11_2 assigned R/W b3 INT3SEL0 INT3 pin select bit 0: P3_3 assigned 1: P11_3 assigned R/W b4 INT4SEL0 INT4 pin select bit 0: P3_4 assigned 1: P11_4 assigned R/W b5 INT5SEL0 INT5 pin select bit 0: P3_5 assigned 1: P11_5 assigned R/W b6 INT6SEL0 INT6 pin select bit 0: P3_6 assigned 1: P11_6 assigned R/W b7 INT7SEL0 INT7 pin select bit 0: P3_7 assigned 1: P11_7 assigned R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 186 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.4.3 External Input Enab le Register 0 (INTEN)

Notes: 1. To set the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (falling edge selected). 2. The IR bit in the INTiIC register may be set to 1 (interrupt requested) if the INTiPL bit is rewritten. Refer to 12.8.4 Changing Interrupt Sources. Address 01FAh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol INT3PL INT3EN INT2PL INT2 EN INT1PL INT1EN INT0PL INT0EN A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 INT0EN INT0 input enable bit 0: Disabled 1: Enabled R/W b1 INT0PL INT0 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W b2 INT1EN INT1 input enable bit 0: Disabled 1: Enabled R/W b3 INT1PL INT1 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W b4 INT2EN INT2 input enable bit 0: Disabled 1: Enabled R/W b5 INT2PL INT2 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W b6 INT3EN INT3 input enable bit 0: Disabled 1: Enabled R/W b7 INT3PL INT3 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 187 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.4.4 External Input Enab le Register 1 (INTEN1)

Notes: 1. To set the INTiPL bit (i = 4 to 7) to 1 (both edges), set the POL bit in the INTiIC register to 0 (falling edge selected). 2. The IR bit in the INTiIC register may be set to 1 (interrupt requested) if the INTiPL bit is rewritten. Refer to 12.8.4 Changing Interrupt Sources. Address 01FBh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol INT7PL IN7EN INT6PL INT6EN INT5PL INT5EN INT4PL INT4EN A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 INT4EN INT4 input enable bit 0: Disabled 1: Enabled R/W b1 INT4PL INT4 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W b2 INT5EN INT5 input enable bit 0: Disabled 1: Enabled R/W b3 INT5PL INT5 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W b4 INT6EN INT6 input enable bit 0: Disabled 1: Enabled R/W b5 INT6PL INT6 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W b6 IN7EN INT7 input enable bit 0: Disabled 1: Enabled R/W b7 INT7PL INT7 input polarity select bit (1, 2) 0: One edge 1: Both edges R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 188 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.4.5 INT Input Filter Se lect Register 0 (INTF)

12.4.6 INT Input Filter Se lect Register 1 (INTF1)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol INT3F1 INT3F0 INT2F1 INT2F0 INT1F1 INT1F0 INT0F1 INT0F0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 INT0F0 INT0 input filter select bit b1 b0 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b1 INT0F1 R/W b2 INT1F0 INT1 input filter select bit b3 b2 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b3 INT1F1 R/W b4 INT2F0 INT2 input filter select bit b5 b4 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b5 INT2F1 R/W b6 INT3F0 INT3 input filter select bit b7 b6 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b7 INT3F1 R/W Address 01FDh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol INT7F1 INT7F0 INT6F1 INT6F0 INT5F1 INT5F0 INT4F1 INT4F0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 INT4F0 INT4 input filter select bit b1 b0 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b1 INT4F1 R/W b2 INT5F0 INT5 input filter select bit b3 b2 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b3 INT5F1 R/W b4 INT6F0 INT6 input filter select bit b5 b4 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b5 INT6F1 R/W b6 INT7F0 INT7 input filter select bit b7 b6 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b7 INT7F1 R/W

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12.4.7 INTi Input Filter (i = 0 to 7)

The INTi input contains a digital filter. The sampling clock is selected using bits INTiF0 and INTiF1 in the INTF register. The INTi level is sampled every sampling clock cycl e and if the sampled input level matches three times, the IR bit in the INTiIC register is set to 1 (interrupt requested). Figure 12.9 shows the INTi Input Filter Configuration. Figure 12.10 shows an Operating Example of INTi Input Filter. Figure 12.9 INTi Input Filter Configuration Figure 12.10 Operating Example of INTi Input Filter i = 0 to 7 INTiF0, INTiF1: Bits in INTF register INTiEN, INTiPL: Bits in INTEN register = 01b INTi Sampling clock Digital filter (matches 3 times) INTi interrupt = 10b = 11bf32 INTiF1 to INTiF0 INTiEN INTiF1 to INTiF0 = other than 00b = 00b INTiPL = 0 INTiPL = 1 Both-edge detection circuit INTi input Sampling timing IR bit in INTiIC register Set to 0 by a program. Note: 1. This is an operating example when bits INTiF1 to INTiF0 in the INTiF register are set to 01b, 10b, or 11b (digital filte r enabled). i = 0 to 7

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 190 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.5 Key Input Interrupt

A key input interrupt request is generated by one of the input edges of pins K10 to K17. The key input interrupt can be used as a key-on wake-up function to exit wait or stop mode. The KIiEN bit (i = 0 to 7) in the KIEN register is be used to select whether or not the pins are used as the KIi input. The KIiPL bit in the KIEN register is also be used to select the input polarity. When inputting a low signal to the KIi pin, which sets the KIiPL bit to 0 (f alling edge), the input to the other pins K10 to K17 is not detected as interrupts. When inputting a high signal to the KIi pin, which sets the KIiPL bit to 1 (rising edge), the input to the other pins K10 to K17 is also not detected as interrupts. Figure 12.11 shows a Block Diagram of Key Input Inte rrupt. Table 12.7 lists the Key Input Interrupt Pin Configuration. Figure 12.11 Block Diagram of Key Input Interrupt KI7 KI6 KI7PL = 0 KI7PL = 1 KI7EN bit Pull-up control register value for the corresponding port Direction register value for the corresponding port KUPIC register Interrupt control circuit Key input interrupt request KI6PL = 0 KI6PL = 1 KI6EN bit KI5 KI5PL = 0 KI5PL = 1 KI5EN bit KI4 KI4PL = 0 KI4PL = 1 KI4EN bit KI3 KI2 KI3PL = 0 KI3PL = 1 KI3EN bit KI2PL = 0 KI2PL = 1 KI2EN bit KI1 KI1PL = 0 KI1PL = 1 KI1EN bit KI0 KI0PL = 0 KI0PL = 1 KI0EN bit i = 0 to 7 KIiEN, KIiPL: Bits in KIEN or KIEN1 register Pull-up transistor Pull-up transistor Pull-up transistorPull-up transistor Pull-up transistor Pull-up transistorPull-up transistorPull-up transistor

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 191 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 12.7 Key Input Interrupt Pin Configuration Pin Name I/O Function KI0 Input KI0 interrupt input KI1 Input KI1 interrupt input KI2 Input KI2 interrupt input KI3 Input KI3 interrupt input KI4 Input KI4 interrupt input KI5 Input KI5 interrupt input KI6 Input KI6 interrupt input KI7 Input KI7 interrupt input

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 192 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.5.1 Key Input Pin Sel ect Register (KISR)

The KISR register selects which pin is assigned as the KIi (i = 1 to 7) input. To use the KIi, set this register. Set the KISR register before setting the KIi associated registers. Also, do not change the setting values in this register during KIi operation. Address 018Dh B i t b 7b 6 b 5 b 4b 3b 2b 1 b 0 Symbol KI7SEL0 KI6SEL0 KISEL0 KI4SEL 0 KI3SEL0 KI2SEL0 KI1SEL0 KI0SEL0 A f t e r R e s e t 00 0 0000 0 Bit Symbol Bit Name Function R/W b0 KI0SEL0 KI0 pin select bit 0: P2_0 assigned 1: P10_0 assigned R/W b1 KI1SEL0 KI1 pin select bit 0: P2_1 assigned 1: P10_1 assigned R/W b2 KI2SEL0 KI2 pin select bit 0: P2_2 assigned 1: P10_2 assigned R/W b3 KI3SEL0 KI3 pin select bit 0: P2_3 assigned 1: P10_3 assigned R/W b4 KI4SEL0 KI4 pin select bit 0: P2_4 assigned 1: P10_4 assigned R/W b5 KI5SEL0 KI5 pin select bit 0: P2_5 assigned 1: P10_5 assigned R/W b6 KI6SEL0 KI6 pin select bit 0: P2_6 assigned 1: P10_6 assigned R/W b7 KI7SEL0 KI7 pin select bit 0: P2_7 assigned 1: P10_7 assigned R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 193 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.5.2 Key Input Enable Register 0 (KIEN)

The IR bit in the KUPIC register may be set to 1 (interrupt requested) when the KIEN register is rewritten. Refer to 12.8.4 Changing Interrupt Sources. Address 01FEh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol KI3PL KI3EN KI2PL KI2EN KI1PL KI1EN KI0PL KI0EN A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 KI0EN KI0 input enable bit 0: Disabled 1: Enabled R/W b1 KI0PL KI0 input polarity select bit 0: Falling edge 1: Rising edge R/W b2 KI1EN KI1 input enable bit 0: Disabled 1: Enabled R/W b3 KI1PL KI1 input polarity select bit 0: Falling edge 1: Rising edge R/W b4 KI2EN KI2 input enable bit 0: Disabled 1: Enabled R/W b5 KI2PL KI2 input polarity select bit 0: Falling edge 1: Rising edge R/W b6 KI3EN KI3 input enable bit 0: Disabled 1: Enabled R/W b7 KI3PL KI3 input polarity select bit 0: Falling edge 1: Rising edge R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 194 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.5.3 Key Input Enable Register 1 (KIEN1)

The IR bit in the KUPIC register may be set to 1 (interrupt requested) when the KIEN1 register is rewritten. Refer to 12.8.4 Changing Interrupt Sources. Address 01FFh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol KI7PL KI7EN KI6PL KI6EN KI5PL KI5EN KI4PL KI4EN A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 KI4EN KI4 input enable bit 0: Disabled 1: Enabled R/W b1 KI4PL KI4 input polarity select bit 0: Falling edge 1: Rising edge R/W b2 KI5EN KI5 input enable bit 0: Disabled 1: Enabled R/W b3 KI5PL KI5 input polarity select bit 0: Falling edge 1: Rising edge R/W b4 KI6EN KI6 input enable bit 0: Disabled 1: Enabled R/W b5 KI6PL KI6 input polarity select bit 0: Falling edge 1: Rising edge R/W b6 KI7EN KI7 input enable bit 0: Disabled 1: Enabled R/W b7 KI7PL KI7 input polarity select bit 0: Falling edge 1: Rising edge R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 195 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.6 Address Match Interrupt

An address match interrupt request is generated immediat ely before execution of the instruction at the address indicated by the RMADi (i = 0 or 1) register. This interr upt is used as a break function by the debugger. When the on-chip debugger is used, do not set an address match interrupt (registers AIER0, AIER1, RMAD0, and RMAD1, and fixed vector tables) in the user system. Set the starting address of any instruct ion in the RMADi (i = 0 or 1) register. The AIERi bit in the AIERi register can be used to select the interrupt enabled or disabled. The address match interrupt is not affected by the I flag and IPL. The PC value (refer to 12.3.7 Saving Registers ) which is saved on the stack wh en an address match interrupt request is acknowledged varies depending on the instruc tion at the address indicated by the RMADi register. (The appropriate return address is not save d on the stack.) When returning from the address match interrupt, follow one of the following means:

• Rewrite the contents of the stack and use the REIT instruction to return.
• Use an instruction such as POP to restore the stack to its previous st ate before the interrupt request was acknowledged. Then use a jump instruction to return. Table 12.8 lists the PC Value Saved on Stack When Address Match Interrupt Request is Acknowledged. Notes: 1. Refer to the 12.3.7 Saving Registers. 2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001). Chapter 4. Instruction Code/Number of Cycles contains diagrams showing operation code below each syntax. Operation code is shown in the bold frame in the diagrams. Table 12.8 PC Value Saved on Stack When Address Match Interrupt Request is Acknowledged Address Indicated by RMADi Register (i = 0 or 1) PC Value Saved (1)
• Instruction with 2-byte operation code (2)
• Instruction with 1-byte operation code (2) ADD.B:S #IMM8,dest SUB.B:S #I MM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B: S #IMM8,dest STZ #IMM8,dest STNZ #IMM8,dest STZX #IMM81,#IMM82,dest CMP .B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (however, dest = A0 or A1) Address indicated by RMADi register + 2
• Instructions other than listed above Address indicated by RMADi register + 1 Table 12.9 Correspondence Between Address Match Interrupt Sources and Associated Registers Address Match Interrupt Source Address Match In terrupt Enable Bit Address Match Interrupt Register Address match interrupt 0 AIER0 RMAD0 Address match interrupt 1 AIER1 RMAD1

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 196 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.6.1 Address Match Interrupt Enable Register i (AIERi) (i = 0 or 1)

12.6.2 Address Match Interrupt Regi ster i (RMADi) (i = 0 or 1)

Address 01C3h (AIER0), 01C7h (AIER1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l ——————— A I E R 0 A I E R 0 r e g i s t e r A f t e r R e s e t 00000000 S y m b o l ——————— A I E R 1 A I E R 1 r e g i s t e r A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 AIERi Address match interrupt i enable bit 0: Disabled 1: Enabled R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 — b3 — b4 — b5 — b6 — b7 — Address 01C2h to 01C0h (RMAD0), 01C6h to 01C4h (RMAD1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t XXXXXXXX Bit b23 b22 b21 b20 b19 b18 b17 b16 A f t e r R e s e t 0000XXXX Bit Symbol Function Setting Range R/W b19 to b0 — Address setting register for address match interrupt 00000h to FFFFFh R/W b20 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b21 — b22 — b23 —

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 197 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.7 Interrupts of Timer RC, Timer RD, Timer RG, Synchronous Serial Communication

Unit, I 2C bus Interface, and Flash Memory (Interrupts with Multiple Interrupt Request Sources) The interrupts of timer RC, timer RD (timer RD0) interrupt, timer RD (timer RD1), timer RG , the synchronous serial communication unit, the I 2C bus interface, and the flash memory each have multiple interrupt request sources. An interrupt request is generated by the logical OR of several interrupt request sources and is reflected in the IR bit in the corresponding interrup t control register. Therefore, each of these peripheral functions has its own interrupt request source status register (status register) and interrupt request source enable register (enable register) to control the generation of interrupt requests (change of the IR bit in the interrupt control register). Table 12.10 lists the Registers Associated with Interrupts of Timer RC, Timer RD, Timer RG , Synchronous Serial Communication Unit, I 2C bus Interface, and Flash Memory and Figure 12.12 shows a Block Diagram of Timer RD Interrupt. Figure 12.12 Block Diagram of Timer RD Interrupt Table 12.10 Registers Associated with Interrupts of Timer RC, Timer RD, Timer RG, Synchronous Serial Communication Unit, I2C bus Interface, and Flash Memory Peripheral Function Name Status Register of Interrupt Request Source Enable Register of Interrupt Request Source Interrupt Control Register Timer RC TRCSR TRCIER TRCIC Timer RD Timer RD0 TRDSR0 TRDIER0 TRD0IC Timer RD1 TRDSR1 TRDIER1 TRD1IC Timer RG TRGSR TRGIER TRGIC Synchronous serial communication unit SSSR SSER SSUIC I2C bus interface ICSR ICIER IICIC Flash memory RDYSTI RDYSTIE FMRDYIC BSYAEI BSYAEIE CMDERIE Timer RD i interrupt request (IR bit in TRDiIC register) IMFA bit IMIEA bit IMFB bit IMIEB bit IMFC bit IMIEC bit IMFD bit IMIED bit UDF bit OVF bit OVIE bit i = 0 or 1 IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register Timer RD i

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 198 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group As with other maskable interrupts, the interrupts of ti mer RC, timer RD (timer RD0), timer RD (timer RD1), timer RG , the synchronous serial communication unit, the I 2C bus interface, and the flash memory are controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since each interrupt source is generated by a combination of multiple interrupt request sources, the following differences from other maskable interrupts apply:

• When bits in the enable register are set to 1 and the corresponding bits in the status register are set to 1 (interrupt enabled), the IR bit in the interrupt control register is set to 1 (interrupt requested).
• When either bits in the status register or the corresponding bits in the enable register, or both are set to 0, the IR bit is set to 0 (no interrupt requested). That is, even if the interrupt is not acknowledged after th e IR bit is set to 1, the interrupt request will not be retained. Also, the IR bit is not set to 0 even if 0 is written to this bit.
• Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged. The IR bit is also not automatically set to 0 when the interrupt is acknowledged. Set individual bits in the status register to 0 in the interrupt routine. Refer to the status register figure for how to set individual bits in the status register to 0.
• When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is set to 1, the IR bit remains 1.
• When multiple bits in the enable regi ster are set to 1, use the status regi ster to determine which request source causes an interrupt. Refer to chapters of the individual peripheral functions ( 20. Timer RC , 21. Timer RD , 23. Timer RG , 27. Synchronous Serial Communication Unit (SSU), 28. I2C bus Interface, and 35. Flash Memory) for the status register and enable register. For the interrupt control register, refer to 12.3 Interrupt Control.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 199 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.8 Notes on Interrupts

12.8.1 Reading Address 00000h

Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the IR bit for the acknowledged interrupt is set to 0. If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause the interrupt to be cancel ed, or an unexpected interrupt to be generated.

12.8.2 SP Setting

Set a value in the SP before an interrupt is acknowledged. The SP is set to 0000h after a reset. If an interrupt is acknowledged before setting a value in the SP, the program may run out of control.

12.8.3 External Interrupt, Key Input Interrupt

Either the low-level width or high-level width shown in the Electrical Characteristics is required for the signal input to pins INT0 to INT7 and pins KI0 to KI7, regardless of the CPU clock. For details, refer to Table 36.XX (VCC = 5 V), Table 36.XX (VCC = 3 V), Table 36.XX (VCC = 1.8 V) External Interrupt INTi (i = 0 to 7) Input, Key Input Interrupt KIi (i = 0 to 7).

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 200 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.8.4 Changing Interrupt Sources

The IR bit in the interrupt control register may be se t to 1 (interrupt requested) when the interrupt source changes. To use an interrupt, set the IR bit to 0 (no interrupt requested) after changing interrupt sources. Changing interrupt sources as referred to here includes all factors that change the source, polarity, or timing of the interrupt assigned to a software interrupt number. Therefore, if a m ode change of a peripheral function involves the source, polarity, or timing of an interrupt, set the IR bit to 0 (no interrupt requested) after making these changes. Refer to the descriptions of the individual peripheral functions for related interrupts. Figure 12.13 shows a Procedure Example for Changing Interrupt Sources. Figure 12.13 Procedure Example for Changing Interrupt Sources Notes: 1. The above settings must be executed individually. Do not execute two or more settings simultaneously (using one instruction). 2. To prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 for the interrupt whose source is to be changed. 3. Refer to 12.8.5 Rewriting Interrupt Control Register for the instructions to use and related notes. Interrupt source change Disable interrupts (2, 3) Set the IR bit to 0 (no interrupt request) using the MOV instruction (3) Change interrupt sources (including the mode of peripheral functions) Enable interrupts (2, 3) Change completed IR bit: Bit in the interrupt control register bit for the interrupt whose source is to be changed

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 201 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 12. InterruptsR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.8.5 Rewriting Interr upt Control Register

(a) The contents of the interrupt control register can be rewritten only while no interrupt requests corresponding to that regist er are generated. If an interrupt reques t may be generated, disable the interrupt before rewriting the contents of the interrupt control register. (b) When rewriting the contents of the interrupt control register after disabling th e interrupt, be careful to choose appropriate instructions. Changing any bit other than the IR bit If an interrupt request corresponding to the register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and the interrupt may be ignored. If this causes a problem, use one of the following instructions to rewrite the contents of the register: AND, OR, BCLR, and BSET. Changing the IR bit Depending on the instruction used, the IR bit may not be set to 0 (no interrupt requested). Use the MOV instruction to set the IR bit to 0. (c) When using the I flag to disable an interrupt, set the I flag as shown in the sample programs below. Refer to (b) regarding rewriting the contents of interrupt control registers using the sample programs. Examples 1 to 3 shows how to prevent the I flag from being set to 1 (interrupts enabled) before the contents of the interrupt control register are rewritten for the effects of the internal bus and the instruction queue buffer. Example 1: Use the NOP instructions to pause program until the interrupt control register is rewritten INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts Example 2: Use a dummy read to delay the FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h MOV .W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use the POPC inst ruction to change the I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set the TRAIC register to 00h POPC FLG ; Enable interrupts

1. ID Code Areas REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 202 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 13. ID Code Areas The ID code areas are used to implement a function that prevents the flash memory from being rewritten in standard serial I/O mode. This function prevents the flash memory from being read, rewritten, or erased.

13.1 Introduction

The ID code areas are assigned to 0FFDFh, 0FFE3h, 0FFEBh, 0FFEFh, 0FFF3h, 0FFF7h, and 0FFFBh of the respective vector highest-order addresses of the fixed vector table. Figure 13.1 shows the ID Code Areas. Figure 13.1 ID Code Areas 4 bytes Address Watchdog timer, oscillation stop detection, voltage monitor 1, voltage monitor 2 (Reserved) Undefined instruction vector Overflow vector BRK instruction vector Address match vector Single step vector Address break vector Reset vector ID code areas ID1 ID2 ID3 ID4 ID5 ID6 ID7 OFS 0FFDFh to 0FFDCh 0FFE3h to 0FFE0h 0FFE7h to 0FFE4h 0FFEBh to 0FFE8h 0FFEFh to 0FFECh 0FFF3h to 0FFF0h 0FFF7h to 0FFF4h 0FFFBh to 0FFF8h 0FFFFh to 0FFFCh

1. ID Code Areas REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 203 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

13.2 Functions

The ID code areas are used in standard serial I/O mode. Unless 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes stored in the ID code areas and the ID codes sent from the serial programmer or the on-chip debugging emulator are checked to see if they match. If the ID codes match, the commands sent from the seri al programmer or the on-chip debugging emulator are ackno wledged. If the ID codes do not match, the commands are not acknowledged. To use the serial programmer or the on-chip debugging emulator, first write predetermined ID codes to the ID code areas. If 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes are not checked and all commands are accepted. As the ID code areas are allocated in the flash memory ( not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The character sequence of the ASCII codes “ALeRASE” is the reserved word used for the forced erase function. The character sequence of the ASCII codes “Protect” is th e reserved word used for th e standard serial I/O mode disabled function. Table 13.1 shows the ID Code Reserved Word. The reserved word is a set of reserved characters when all the addresses and data in the ID code storage addresses sequentially match Table 13.1. When the forced erase function or standard serial I/O mode disabled fu nction is not used, use anot her character sequence of the ASCII codes. Table 13.1 ID Code Reserved Word Note: 1. Reserve word: A set of characters when all the addresses and data in the ID code storage addresses sequentially match Table 13.1. ID Code Storage Address lD Code Reserved Word (ASCII) (1) ALeRASE Protect 0FFDFh ID1 41h (upper-case “A”) 50h (upper-case “P”) 0FFE3h ID2 4Ch (upper-case “L”) 72h (lower-case “r”) 0FFEBh ID3 65h (lower-case “e”) 6Fh (lower-case “o”) 0FFEFh ID4 52h (upper-case “R”) 74h (lower-case “t”) 0FFF3h ID5 41h (upper-case “A”) 65h (lower-case “e”) 0FFF7h ID6 53h (upper-case “S”) 63h (lower-case “c”) 0FFFBh ID7 45h (upper-case “E”) 74h (lower-case “t”)

1. ID Code Areas REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 204 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

13.3 Forced Erase Function

This function is used in standard serial I/O mode. When the ID codes sent from the serial programmer or the on- chip debugging emulator are “ALeRASE” in ASCII code, the content of the user ROM area will be erased at once. However, if the contents of the ID code addre sses are set to other than “ALeRASE” (other than Table 13.1 ID Code Reserved Word) when the ROMCR bit in the OFS register is set to 1 and the ROMCP1 bit is set to 0 (ROM code protect enabled), forced erasure is not executed and the ID codes are checked with the ID code check function. Table 13.2 lists the Conditions and Operations of Forced Erase Function. When the contents of the ID code addresses are set to “ALeRASE” in ASCII code, if the ID codes sent from the serial programmer or the on-chip debugging emulator ar e “ALeRASE”, the content of the user ROM area will be erased. If the ID codes sent from the serial programmer are other than “ALeRASE”, the ID codes do not match and no command is acknowledged, thus the user ROM area remains protected. Note: 1. For “Protect”, refer to 13.4 Standard Serial I/O Mode Disabled Function.

13.4 Standard Serial I/O Mode Disabled Function

This function is used in standard serial I/O mode. When the I/D codes in the ID code storage addresses are set to the reserved character sequence of the ASCII codes “Protect” (refer to Table 13.1 ID Code Reserved Word ), communication with the serial programmer or the on-chip debugging emulator is not performed. This does not allow the flash memory to be read, rewritten, or eras ed using the serial programmer or the on-chip debugging emulator. Also, if the ID codes are also set to the reserved ch aracter sequence of the ASCI I codes “Protect” when the ROMCR bit in the OFS register is set to 1 and the ROMCP1 bit is set to 0 (ROM code protect enabled), ROM code protection cannot be disabled using the serial programmer or the on-chip debugging emulator. This prevents the flash memory from being read, rewritten, or erased using the serial programmer, the on-chip debugging emulator, or the parallel programmer. Table 13.2 Conditions and Operations of Forced Erase Function Condition Operation ID code from serial programmer or on-chip debugging emulator ID code in ID code storage address Bits ROMCP1 and ROMCR in OFS register ALeRASE ALeRASE – All erasure of user ROM area (forced erase function)Other than ALeRASE (1) Other than 01b (ROM code protect disabled) 01b (ROM code protect enabled) ID code check (ID code check function) Other than ALeRASE ALeRASE – ID code check (ID code check function. No ID code match) Other than ALeRASE (1) – ID code check (ID code check function)

1. ID Code Areas REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 205 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

13.5 Notes on ID Code Areas

13.5.1 Setting Example of ID Code Areas

As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example.

• To set 55h in all of the ID code areas .org 00FFDCH .lword dummy | (55000000h) ; UND .lword dummy | (55000000h) ; INTO .lword dummy ; BREAK .lword dummy | (55000000h) ; ADDRESS MATCH .lword dummy | (55000000h) ; SET SINGLE STEP .lword dummy | (55000000h) ; WDT .lword dummy | (55000000h) ; ADDRESS BREAK .lword dummy | (55000000h) ; RESERVE (Programming formats vary depending on the compiler. Check the compiler manual.)

1. Option Function Select Area REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 206 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 14. Option Function Select Area

14.1 Introduction

The option function select area is used to select the MCU state after a reset, the function to prevent rewriting in parallel I/O mode, or the watchdog timer operation. Th e reset vector highest-order-addresses, 0FFFFh and 0FFDBh, are assigned as the option function select area. Figure 14.1 shows the Option Function Select Area. Figure 14.1 Option Function Select Area Address 0FFDBh to 0FFD8h OFS2 Option function select area 4 bytes 0FFFFh to 0FFFCh OFS Reset vector Reserved area

1. Option Function Select Area REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 207 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

14.2 Registers

Registers OFS and OFS2 are used to select the MCU state after a reset, the function to prevent rewriting in parallel I/O mode, or the watchdog timer operation.

14.2.1 Option Function Se lect Register (OFS)

Notes: 1. If the block including the OFS register is erased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. Address 0FFFFh B i t b 7 b 6b 5b 4b 3b 2b 1b 0 Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON W h e n s h i p p i n g 1 1111111 ( N o t e 1 ) Bit Symbol Bit Name Function R/W b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset 1: Watchdog timer is stopped after reset R/W b1 — Reserved bit Set to 1. R/W b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled 1: ROMCP1 bit enabled R/W b3 ROMCP1 ROM code protect bit 0: ROM code protect enabled 1: ROM code protect disabled R/W b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4 0 0: 3.80 V selected (Vdet0_3) 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) R/W b5 VDSEL1 R/W b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset 1: Voltage monitor 0 reset disabled after reset R/W b7 CSPROINI Count source protection mode after reset select bit 0: Count source protection mode enabled after reset 1: Count source protection mode disabled after reset R/W

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14.2.2 Option Function Sel ect Register 2 (OFS2)

Note: 1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh. The OFS2 register is located on the flash memory. Write to this register with a program. After writing, do not write additions to this register. Bits WDTRCS0 and WDTRCS1 (Watchdog Timer Refresh Acknowledgement Period Set Bit) Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh acknowledgement period for the watchdog timer can be selected. For details, refer to 15.3.1.1 Refresh Acknowledgment Period. Address 0FFDBh B i t b 7b 6b 5b 4 b 3 b 2 b 1 b 0 Symbol — — — — WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0 When shipping 1 1 1 1 1 1 1 1 (Note 1) Bit Symbol Bit Name Function R/W b0 WDTUFS0 Watchdog timer underflow period set bit b1 b0 0 0: 03FFh 0 1: 0FFFh 1 0: 1FFFh 1 1: 3FFFh R/W b1 WDTUFS1 R/W b2 WDTRCS0 Watchdog timer refresh acknowledgement period set bit b3 b2 0 0: 25% 0 1: 50% 1 0: 75% 1 1: 100% R/W b3 WDTRCS1 R/W b4 — Reserved bits Set to 1. R/W b5 — b6 — b7 —

1. Option Function Select Area REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 209 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

14.3 Notes on Option Function Select Area

14.3.1 Setting Example of Op tion Function Select Area

As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an instruction. Write appropriate values when creating a program. The following shows a setting example.

• To set FFh in the OFS register .org 00FFFCH .lword reset | (0FF000000h) ; RESET (Programming formats vary depending on the compiler. Check the compiler manual.)

1. Watchdog Timer REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 210 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 15. Watchdog Timer The watchdog timer is a function that detects when a pr ogram is out of control. Use of the watchdog timer is recommended to improve the reliability of the system.

15.1 Introduction

The watchdog timer contains a 14-bit counter and allows selection of count source protection mode enable or disable. Table 15.1 lists the Watchdog Timer Specifications. Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset. Figure 15.1 shows the Watchdog Timer Block Diagram. Table 15.1 Watchdog Timer Specifications Item Count Source Protection Mode Disabled Count Source Protection Mode Enabled Count source CPU clock Low-sp eed on-chip oscillator clock for the watchdog timer Count operation Decrement Count start condition Either of the following can be selected:

• After a reset, count starts automatically.
• Count starts by writing to the WDTS register. Count stop condition Stop mode, wait mode None Watchdog timer initialization conditions
• Reset
• Write 00h and then FFh to the WDTR register (with acknowledgement period setting).
• Underflow Operations at underflow Watchdog timer interrupt or watchdog timer reset Watchdog timer reset Selectable functions • Division ratio of the prescaler Selectable by the WDTC7 bit in the WDTC register or the CM07 bit in the CM0 register.
• Count source protection mode Whether count source protection mode is enabled or disabled after a reset can be selected by the CSPROINI bit in the OFS register (flash memory). If count source protection mode is disabled after a reset, it can be enabled or disabled by the CSPRO bit in the CSPR register (program).
• Start or stop of the watchdog timer after a reset Selectable by the WDTON bit in the OFS register (flash memory).
• Initial value of the watchdog timer Selectable by bits WDTUFS0 and WDTUFS1 in the OFS2 register.
• Refresh acknowledgement period for the watchdog timer Selectable by bits WDTRCS0 and WDTRCS1 in the OFS2 register.

1. Watchdog Timer REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 211 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 15.1 Watchdog Timer Block Diagram 1/2 Watchdog timer CPU clock Bits WDTRCS0 and WDTRCS1 CM07 = 1 (Note 1) PM12 = 1 Watchdog timer reset PM12 = 0 Watchdog timer interrupt request Prescaler CSPRO = 0 CSPRO = 1 CSPRO: Bit in CSPR register WDTC7: Bit in WDTC register PM12: Bit in PM1 register CM07: Bit in CM0 register WDTUFS0, WDTUFS1, WDTRCS0, WDTRCS1: Bits in OFS2 register Note: 1. A value set by bits WDTUFS0 and WDTUFS1 is set in the watchdog timer (value when shipping: 3FFFh). Internal reset signal (Low active) CM07 = 0, WDC7 = 0 CM07 = 0, WDC7 = 1 Low-speed on-chip oscillator for watchdog timer Oscillation starts when CSPRO = 1 Refresh period control circuitWrite to WDTR register

1. Watchdog Timer REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 212 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

15.2 Registers

15.2.1 Processor Mode Register 1 (PM1)

Note: 1. The PM12 bit is set to 1 when 1 is written by a pr ogram (and remains unchanged even if 0 is written to it). This bit is automatically set to 1 when the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled). Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM1 register.

15.2.2 Watchdog Timer Reset Register (WDTR)

Note: 1. Write the WDTR register during the count operation of the watchdog timer.

15.2.3 Watchdog Timer Start Register (WDTS)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 PM12 WDT interrupt/reset switch bit 0: Watchdog timer interrupt 1: Watchdog timer reset (1) R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 — b6 — b7 — Reserved bit Set to 0. R/W Address 000Dh B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit Function R/W b7 to b0 Writing 00h and then FFh into this register initializes the watchdog timer. The initial value of the watchdog timer is specified by bits WDTUFS0 and WDTUF1 in the OFS2 register. (1) W Address 000Eh B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit Function R/W b7 to b0 A write instruction to this register starts the watchdog timer. W

1. Watchdog Timer REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 213 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

15.2.4 Watchdog Timer C ontrol Register (WDTC)

15.2.5 Count Source Protecti on Mode Register (CSPR)

Notes: 1. When 0 is written to the CSPROINI bit in the OFS register, the value after reset is 10000000b. 2. To set the CSPRO bit to 1, write 0 and then 1 to it. This bit cannot be set to 0 by a program. Address 000Fh B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00111111 Bit Symbol Bit Name Function R/W b0 — The following bits of the watchdog timer can be read. When bits WDTUFS1 to WDTUFS0 in the OFS2 register are 00b (03FFh): b5 to b0 01b (0FFFh): b8 to b3 10b (1FFFh): b9 to b4 11b (3FFFh): b10 to b5 R b1 — R b2 — R b3 — R b4 — R b5 — R b6 — Reserved bit When read, the content is 0. R b7 WDTC7 Prescaler select bit 0: Divide-by-16 1: Divide-by-128 R/W Address 001Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 ( N o t e 1 ) Bit Symbol Bit Name Function R/W b0 — Reserved bits Set to 0. R/W b1 — b2 — b3 — b4 — b5 — b6 — b7 CSPRO Count source protection mode select bit (2) 0: Count source protection mode disabled 1: Count source protection mode enabled R/W

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15.2.6 Option Function Se lect Register (OFS)

Notes: 1. If the block including the OFS register is erased, the OFS register value is set to FFh. 2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of voltage monitor 0 reset and power-on reset. 3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset). The OFS register is allocated in the flash memory. Write to this register with a program. After writing, do not write additions to this register. LVDAS Bit (Voltage Detection 0 Circuit Start Bit) The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1. Address 0FFFFh B i t b 7 b 6b 5b 4b 3b 2b 1b 0 Symbol CSPROINI LVDAS VDSEL1 VDSEL0 ROMCP1 ROMCR — WDTON W h e n s h i p p i n g 1 1111111 ( N o t e 1 ) Bit Symbol Bit Name Function R/W b0 WDTON Watchdog timer start select bit 0: Watchdog timer automatically starts after reset 1: Watchdog timer is stopped after reset R/W b1 — Reserved bit Set to 1. R/W b2 ROMCR ROM code protect disable bit 0: ROM code protect disabled 1: ROMCP1 bit enabled R/W b3 ROMCP1 ROM code protect bit 0: ROM code protect enabled 1: ROM code protect disabled R/W b4 VDSEL0 Voltage detection 0 level select bit (2) b5 b4 0 0: 3.80 V selected (Vdet0_3) 0 1: 2.85 V selected (Vdet0_2) 1 0: 2.35 V selected (Vdet0_1) 1 1: 1.90 V selected (Vdet0_0) R/W b5 VDSEL1 R/W b6 LVDAS Voltage detection 0 circuit start bit (3) 0: Voltage monitor 0 reset enabled after reset 1: Voltage monitor 0 reset disabled after reset R/W b7 CSPROINI Count source protection mode after reset select bit 0: Count source protection mode enabled after reset 1: Count source protection mode disabled after reset R/W

1. Watchdog Timer REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 215 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

15.2.7 Option Function Sel ect Register 2 (OFS2)

Note: 1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh. The OFS2 register is located on the flash memory. Write to this register with a program. After writing, do not write additions to this register. Bits WDTRCS0 and WDTRCS1 (Watchdog Timer Refresh Acknowledgement Period Set Bit) Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh acknowledgement period for the watchdog timer can be selected. For details, refer to 15.3.1.1 Refresh Acknowledgment Period. Address 0FFDBh B i t b 7b 6b 5b 4 b 3 b 2 b 1 b 0 Symbol — — — — WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0 When shipping 1 1 1 1 1 1 1 1 (Note 1) Bit Symbol Bit Name Function R/W b0 WDTUFS0 Watchdog timer underflow period set bit b1 b0 0 0: 03FFh 0 1: 0FFFh 1 0: 1FFFh 1 1: 3FFFh R/W b1 WDTUFS1 R/W b2 WDTRCS0 Watchdog timer refresh acknowledgement period set bit b3 b2 0 0: 25% 0 1: 50% 1 0: 75% 1 1: 100% R/W b3 WDTRCS1 R/W b4 — Reserved bits Set to 1. R/W b5 — b6 — b7 —

1. Watchdog Timer REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 216 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

15.3 Functional Description

15.3.1 Common Items for Multiple Modes

15.3.1.1 Refresh Acknowledgment Period

The period for acknowledging refreshment operation to the watchdog timer (write to the WDTR register) can be selected by bits WDTRCS0 and WDTRCS1 in th e OFS2 register. Figure 15.2 shows the Refresh Acknowledgement Period for Watchdog Timer. Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, a refresh operation executed during the refresh acknowledgement period is acknowledged. Any refresh operation executed during the period other than the above is processed as an incorrect write, and a watchdog timer interrupt or watchdog timer reset (selectable by the PM12 bit in the PM1 register) is generated. Do not execute any refresh operation while the count operation of the watchdog timer is stopped. Figure 15.2 Refresh Acknowledgement Period for Watchdog Timer Count starts Note: 1. A watchdog timer interrupt or watchdog timer reset is generated. Watchdog timer period Underflow Refresh can be acknowledged Refresh can be acknowledged Refresh can be acknowledged Processed as incorrect write (1) Refresh can be acknowledged Processed as incorrect write (1) Processed as incorrect write (1) 25% 50% 75% 100% Refresh acknowledge period 100% (WDTRCS1 to WDTRCS0 = 11b) 75% (WDTRCS1 to WDTRCS0 = 10b) 50% (WDTRCS1 to WDTRCS0 = 01b) 25% (WDTRCS1 to WDTRCS0 = 00b) WDTRCS0, WDTRCS1: Bits in OFS2 register

1. Watchdog Timer REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 217 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

15.3.2 Count Source Protection Mode Disabled

The count source for the watchdog timer is the CPU clock when count source protection mode is disabled. Table 15.2 lists the Watchdog Timer Specifications (Count Source Protection Mode Disabled). Notes: 1. The watchdog timer is initialized when 00h and th en FFh is written to the WDTR register. The prescaler is initialized after a reset. This may cause some errors due to the prescaler during the watchdog timer period. 2. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 of address 0FFFFh with a flash programmer. 3. Write the WDTR register during the count operation of the watchdog timer. Table 15.2 Watchdog Timer Specifications (Count Source Protection Mode Disabled) Item Specification Count source CPU clock Count operation Decrement Period Division ratio of prescaler (n) × count value of watchdog timer (m) (1) CPU clock n: 16 or 128 (selected by the WDTC7 bit in the WDTC register), or 2 when the low-speed clock is selected (CM07 bit in CM0 register = 1) m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register Example: The period is approximately 13.1 ms when: - The CPU clock frequency is set to 20 MHz. - The prescaler is divided by 16. - Bits WDTUFS1 to WDTUFS0 are set to 11b (3FFFh). Watchdog timer initialization conditions

• Reset
• Write 00h and then FFh to the WDTR register. (3)
• Underflow Count start conditions The operation of the wa tchdog timer after a reset is selected by the WDTON bit (2) in the OFS register (address 0FFFFh).
• When the WDTON bit is set to 1 (watchdog timer is stopped after reset). The watchdog timer and prescaler are stopped after a reset and start counting when the WDTS register is written to.
• When the WDTON bit is set to 0 (watchdog timer starts automatically after reset). The watchdog timer and prescaler start counting automatically after a reset. Count stop condition Stop mode, wait mode (Count resumes from the retained value after exiting.) Operations at underflow • When the PM12 bit in the PM1 register is set to 0. Watchdog timer interrupt
• When the PM12 bit in the PM1 register is set to 1. Watchdog timer reset (refer to

5.5 Watchdog Timer Reset)

1. Watchdog Timer REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 218 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

15.3.3 Count Source Protection Mode Enabled

The count source for the watchdog timer is the low-spee d on-chip oscillator clock for the watchdog timer when count source protection mode is enabled. If the CPU cloc k stops when a program is out of control, the clock can still be supplied to the watchdog timer. Table 15.3 lists the Watchdog Timer Specifications (Count Source Protection Mode Enabled). Notes: 1. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 of address 0FFFFh with a flash programmer. 2. Even if 0 is written to the CS PROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI bit cannot be changed by a program. To set this bit, write 0 to bit 7 of address 0FFFFh with a flash programmer. 3. Write the WDTR register during the count operation of the watchdog timer. Table 15.3 Watchdog Timer Specifications (Count Source Protection Mode Enabled) Item Specification Count source Low- speed on-chip oscillator clock Count operation Decrement Period Count value of watchdog timer (m) Low-speed on-chip oscillator clock for the watchdog timer m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register Example: The period is approximately 8.2 ms when: - The on-chip oscillator clock for the watchdog timer is set to 125 kHz. - Bits WDTUFS1 to WDTUFS0 are set to 00b (03FFh). Watchdog timer initialization conditions

• R e s e t
• Write 00h and then FFh to the WDTR register. (3)
• Underflow Count start conditions The operation of the watchdog timer after a reset is selected by the WDTON bit (1) in the OFS register (address 0FFFFh).
• When the WDTON bit is set to 1 (watchdog timer is stopped after reset). The watchdog timer and prescaler are stopped after a reset and start counting when the WDTS register is written to.
• When the WDTON bit is set to 0 (watchdog timer starts automatically after reset). The watchdog timer and prescaler start counting automatically after a reset. Count stop condition None (Count does not stop ev en in wait mode once it starts. The MCU does not enter stop mode.) Operation at underflow Watchdog timer reset (Refer to 5.5 Watchdog Timer Reset.) Registers, bits • When the CSPPRO bit in the CSPR register is set to 1 (count source protection mode enabled) (2), the following are set automatically: - The low-speed on-chip oscillator for the watchdog timer is on. - The PM12 bit in the PM1 register is set to 1 (watchdog timer reset when the watchdog timer underflows).

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 219 of 809 16. DTC Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 16. DTC The DTC (data transfer controller) is a function that transfers data between the SFR and on-chip memory without using the CPU. This chip incorporates one DTC channel. The DTC is activated by a peripheral function interrupt to perform data transfers. The DTC and CPU use the same bus, and the DTC takes priority over the CPU in using the bus. To control DTC data transfers, control da ta comprised of a transfer source address, a transfer destination address, and operating modes are allocated in the DTC control data area. Each time the DTC is activated, the DTC reads control data to perform data transfers.

16.1 Overview

Table 16.1 lists the DTC Specifications and Figure 16.1 shows DTC Block Diagram. i = 0 to 6, j = 0 to 23 Table 16.1 DTC Specifications Item Specification Activation sources 38 sources Allocatable control data 24 sets Address space which can be transferred 64 Kbytes (00000h to 0FFFFh) Maximum number of transfer times Normal mode 256 times Repeat mode 255 times Maximum size of block to be transferred Normal mode 256 bytes Repeat mode 255 bytes Unit of transfers Byte Transfer mode Normal mode Transfers end on completion of the transfer causing the DTCCTj register value to change from 1 to 0. Repeat mode On completion of the transfer causing the DTCCTj register value to change from 1 to 0, the repeat area address is initialized and the DTRLDj register value is reloaded to the DTCCTj register to continue transfers. Address control Normal mode Fixed or incremented Repeat mode Addresses of the area not selected as the repeat area are fixed or incremented. Priority of activation sources See Table 16.5 DTC Activation Sources and DTC Vector Addresses. Interrupt request Normal mode When the data transfe r causing the DTCCTj register value to change from 1 to 0 is performed, the activation source interrupt request is generated for the CPU, and interrupt handling is performed on completion of the data transfer. Repeat mode When the data transfer causing the DTCCTj register value to change from 1 to 0 is performed while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled), the activation source interrupt request is generated for the CPU, and interrupt handling is performed on completion of the transfer. Transfer start When bits DTCENi0 to DTCENi7 in the DTCENi registers are 1 (activation enabled), data transfer is started each time the corresponding DTC activation sources are generated. Transfer stop Normal mode • When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled).

• When the data transfer causing the DTCCTj register value to change from 1 to 0 is completed. Repeat mode • When bits DTCENi0 to DTCENi7 are set to 0 (activation disabled).
• When the data transfer causing the DTCCTj register value to change from 1 to 0 is completed while the RPTINT bit is 1 (interrupt generation enabled).

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 220 of 809 16. DTC Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 16.1 DTC Block Diagram

16.2 Registers

When the DTC is activated, control data (DTCCRj, DT BLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj, j = 0 to 23) allocated in the control data area is read, and th en transferred to the control registers (DTCCR, DTBLS, DTCCT, DTRLD, DTSAR, and DTDAR) in the DTC. On completion of the DTC data transfer, the contents of the DTC control registers are written back to the control data area. Each DTCCR, DTBLS, DTCCT, DTRLD, DTSAR, and DTDAR register cannot be directly read or written to. DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj are allocated as control data at addresses from 2C40h to 2CFFh in the DTC control data area, and can be directly accessed. Also, registers DTCTL and DTCENi (i = 0 to 6) can be directly accessed. DTCEN0 to DTCEN6 Interrupt controller Peripheral interrupt request Control circuit DTCCR DTBLS DTCCT DTRLD DTSAR DTDAR DTC activation request Peripheral interrupt request Internal bus CPU Bus interface ROM RAM Peripheral functions DTCCR: DTC control register DTBLS: DTC block size register DTCCT: DTC transfer count register DTRLD: DTC transfer count reload register DTSAR: DTC source address register DTDAR: DTC destination address register DTCTL: DTC activation control register DTCEN0 to DTCEN6: DTC activation enable registers 0 to 6Peripheral bus DTCTL

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16.2.1 DTC Control Register j (DTCCRj) (j = 0 to 23)

Notes: 1. This bit is valid when the MODE bit is 1 (repeat mode). 2. Settings of bits SAMOD and DAMOD are invalid for the repeat area. 3. Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).

16.2.2 DTC Block Size Register j (DTBLSj) (j = 0 to 23)

Note: 1. When the DTBLS register is set to 00h, the block size is 256 bytes. Address See Table 16.4 Control Data Allocation Addresses. B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — RPTINT CHNE DAMOD SAMOD RPTSEL MODE A f t e r R e s e t XXXXXXXX Bit Symbol Bit Name Function R/W b0 MODE Transfer mode select bit 0: Normal mode 1: Repeat mode R/W b1 RPTSEL Repeat area select bit (1) 0: Transfer destination is the repeat area. 1: Transfer source is the repeat area. R/W b2 SAMOD Source address control bit (2) 0: Fixed 1: Incremented R/W b3 DAMOD Destination address control bit (2) 0: Fixed 1: Incremented R/W b4 CHNE Chain transfer enable bit (3) 0: Chain transfers disabled 1: Chain transfers enabled R/W b5 RPTINT Repeat mode interrupt enable bit (1) 0: Interrupt generation disabled 1: Interrupt generation enabled R/W b6 — Reserved bits Set to 0. R/W b7 — Address See Table 16.4 Control Data Allocation Addresses. B i t b 7b 6b 5b 4b 3b 2b 1 b 0 A f t e r R e s e t XXXXXXX X Bit Function Setting Range R/W b7 to b0 These bits specify the size of the data block to be transferred by one activation. 00h to FFh (1) R/W

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16.2.3 DTC Transfer Count Regist er j (DTCCTj) (j = 0 to 23)

Note: 1. When the DTCCT register is set to 00h, the number of transfer times is 256. Each time the DTC is activated, the DTCCT register is decremented by 1.

16.2.4 DTC Transfer Count Reload Re gister j (DTRLDj) (j = 0 to 23)

Note: 1. Set the initial value for the DTCCT register.

16.2.5 DTC Source Addr ess Register j (DTSARj) (j = 0 to 23)

16.2.6 DTC Destination Register j (DTDARj) (j = 0 to 23)

Address See Table 16.4 Control Data Allocation Addresses. B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit Function Setting Range R/W b7 to b0 These bits specify the number of times of DTC data transfers. 00h to FFh (1) R/W Address See Table 16.4 Control Data Allocation Addresses. B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit Function Setting Range R/W b7 to b0 This register value is reloaded to the DTCCT register in repeat mode. 00h to FFh (1) R/W Address See Table 16.4 Control Data Allocation Addresses. B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t XXXXXXXX Bit Function Setting Range R/W b15 to b0 These bits specify a transfer source address for data transfer. 0000h to FFFFh R/W Address See Table 16.4 Control Data Allocation Addresses. B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t XXXXXXXX Bit Function Setting Range R/W b15 to b0 These bits specify a transfer destination address for data transfer. 0000h to FFFFh R/W

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16.2.7 DTC Activation Enable Regi sters i (DTCENi) (i = 0 to 6)

i = 0 to 6 The DTCENi registers enable/disable DTC activation by interrupt sources. Table 16.2 shows Correspondences between Bits DTCENi0 to DTCENi7 (i = 0 to 6) and Interrupt Sources. Address 0088h (DTCEN0), 0089h (DTCEN1), 008Ah (DTCEN2), 008Bh (DTCEN3), 008Ch (DTCEN4), 008Dh (DTCEN5), 008Eh (DTCEN6) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol DTCENi7 DTCENi6 DTCENi5 DTCENi4 DTCENi3 DTCENi2 DTCENi1 DTCENi0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 DTCENi0 DTC activation enable bit 0: Activation disabled 1: Activation enabled R/W b1 DTCENi1 R/W b2 DTCENi2 R/W b3 DTCENi3 R/W b4 DTCENi4 R/W b5 DTCENi5 R/W b6 DTCENi6 R/W b7 DTCENi7 R/W Table 16.2 Correspondences between Bits DTCENi 0 to DTCENi7 (i = 0 to 6) and Interrupt Sources Register DTCENi7 Bit DTCENi6 Bit DTCENi5 Bit DTCENi4 Bit DTCENi3 Bit DTCENi2 Bit DTCENi1 Bit DTCENi0 Bit DTCEN0 INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 DTCEN1 Key input A/D conversion UART0 reception UART0 transmission UART1 reception UART1 transmission UART2 reception UART2 transmission DTCEN2 SSU/I2C bus receive data full SSU/I2C bus transmit data empty Comparator Comparator A1 —— Timer RC input- capture/ compare- match A Timer RC input- capture/ compare- match B DTCEN3 Timer RC input- capture/ compare- match C Timer RC input- capture/ compare- match D Timer RD0 input- capture/ compare- match A Timer RD0 input- capture/ compare- match B Timer RD0 input- capture/ compare- match C Timer RD0 input- capture/ compare- match D Timer RD1 input- capture/ compare- match A Timer RD1 input- capture/ compare- match B DTCEN4 Timer RD1 input- capture/ compare- match C Timer RD1 input- capture/ compare- match D Timer RG input- capture/ compare- match A DTCEN6 Timer RG input- capture/ compare- match B Timer RA — Timer RB Flash memory ready status ———

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16.2.8 DTC Activation Co ntrol Register (DTCTL)

Note: 1. The results of writing to these bits are as follows:

• The bit is set to 0 when it is first read as 1 and then 0 is written to it.
• The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.)
• The bit’s value remains unchanged if 1 is written to it. The DTCTL register controls DTC act ivation when a non-maskable interrupt (an interrupt by the watchdog timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2) is generated. NMIF Bit (Non-Maskable Interrupt Generation Bit) The NMIF bit is set to 1 when a watchdog timer inte rrupt, an oscillation stop detection interrupt, a voltage monitor 1 interrupt, or a voltage monitor 2 interrupt is generated. When the NMIF bit is 1, the DTC is not activated even if the interrupt which enables DTC activation is generated. If the NMIF bit is changed to 1 during DTC transfer, the transfer is continued until it is completed. Address 0080h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Reserved bit Set to 0. R/W b1 NMIF Non-maskable interrupt generation bit (1) 0: Non-maskable interrupts not generated 1: Non-maskable interrupts generated R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b3 — b4 — b5 — b6 — b7 —

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16.3 Function Description

16.3.1 Overview

When the DTC is activated, control data is read from th e DTC control data area to perform data transfers and control data after data transfer is written back to the DTC control data area. 24 sets of control data can be stored in the DTC control data area, which allows 24 types of data transfers to be performed. There are two transfer modes: normal mode and repeat mode. When the CHNE bit in the DTCCRj (j = 0 to 23) register is set to 1 (chain transfers enabled), multiple control data is read and da ta transfers are continuously performed by one activation source (chain transfers). A transfer source address is specifie d by the 16-bit register DTSARj, an d a transfer destination address is specified by the 16-bit register DTDARj. The values in the registers DTSARj and DTDARj are separately fixed or incremented according to the control data on completion of the data transfer.

16.3.2 Activation Sources

The DTC is activated by an interrupt source. Figure 16.2 is a Block Diagram Showing Control of DTC Activation Sources. The interrupt sources to activate the DTC are selected with the DTCENi (i = 0 to 6) register. The DTC sets 0 (activation disabled) to the corre sponding bit among bits DTCENi0 to DTCENi7 in the DTCENi register during operation when the setting of data transfer (the first transfer in chain transfers) is either of the following:

• Transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 in normal mode
• Transfer causing the DTCCTj register value to change to 0 while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled) in repeat mode If the data transfer setting is not either of the above and the activation source is an interrupt source for timer RC, timer RD, or the flash memory, the DTC sets 0 to the interrupt source flag corresponding to the activation source during operation. Table 16.3 shows the DTC Activation Sources and Interrupt Source Flags for Setting to 0 during DTC Operation. If multiple activation sources are simultaneously generate d, DTC activation will be performed according to the DTC activation source priority. If multiple activation sources are simultaneously genera ted on completion of DTC operation, the next transfer will be performed according to the priority. DTC activation is not affected by the I flag or interrupt control register, unlike with interrupt request operation. Therefore, even if interrupt requests cannot be ackno wledged because interrupts ar e disabled, DTC activation requests can be acknowledged. The IR bit in the interrupt control register does not change even when an interrupt source to enable DTC activation is generated. Figure 16.2 Block Diagram Showing Co ntrol of DTC Activation Sources Interrupt controller Select interrupt source or DTC activation source DTCENi Clear control Peripheral function 1 Peripheral function 2 (timer RC, timer RD, flash memory) DTC Interrupt request Peripheral interrupt request Peripheral interrupt request DTC activation request Select DTC activation or interrupt generation. Set the bit among bits DTCENi0 to DTCENi7 (i = 0 to 6) to 0.Set the interrupt source flag in the status register to 0.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 226 of 809 16. DTC Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 16.3 DTC Activation Sources and Interrupt Source Flags for Setting to 0 during DTC Operation DTC activation source generation Interrupt Source Flag for Setting to 0 Timer RC input-capture/compare-match A IMFA bit in TRCSR register Timer RC input-capture/compare-match B IMFB bit in TRCSR register Timer RC input-capture/compare-match C IMFC bit in TRCSR register Timer RC input-capture/compare-match D IMFD bit in TRCSR register Timer RD0 input-capture/compare-match A IMFA bit in TRDSR0 register Timer RD0 input-capture/compare-match B IMFB bit in TRDSR0 register Timer RD0 input-capture/compare-match C IMFC bit in TRDSR0 register Timer RD0 input-capture/compare-match D IMFD bit in TRDSR0 register Timer RD1 input-capture/compare-match A IMFA bit in TRDSR1 register Timer RD1 input-capture/compare-match B IMFB bit in TRDSR1 register Timer RD1 input-capture/compare-match C IMFC bit in TRDSR1 register Timer RD1 input-capture/compare-match D IMFD bit in TRDSR1 register Flash memory ready status RDYSTI bit in FST register

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16.3.3 Control Data Allocatio n and DTC Vector Table

Control data is allocated in the following order: registers DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, and DTDARj (j = 0 to 23). Table 16.4 shows the Control Data Allocation Addresses. j = 0 to 23 Table 16.4 Control Data Allocation Addresses Register Symbol Control Data No. Address DTCCRj Register DTBLSj Register DTCCTj Register DTRLDj Register DTSARj Register (Lower

8 Bits)

(Higher (Lower (Higher 2C47h 2C40h 2C41h 2C42h 2C43h 2C 44h 2C45h 2C46h 2C47h DTCD1 Control Data 1 2C48h to 2C4Fh 2C48h 2C49h 2C4Ah 2C4Bh 2C4Ch 2C4Dh 2C4Eh 2C4Fh DTCD2 Control Data 2 2C50h to 2C57h 2C50h 2C51h 2C52h 2C53h 2C 54h 2C55h 2C56h 2C57h DTCD3 Control Data 3 2C58h to 2C5Fh 2C58h 2C59h 2C5Ah 2C5Bh 2C5Ch 2C5Dh 2C5Eh 2C5Fh DTCD4 Control Data 4 2C60h to 2C67h 2C60h 2C61h 2C62h 2C63h 2C 64h 2C65h 2C66h 2C67h DTCD5 Control Data 5 2C68h to 2C6Fh 2C68h 2C69h 2C6Ah 2C6Bh 2C6Ch 2C6Dh 2C6Eh 2C6Fh DTCD6 Control Data 6 2C70h to 2C77h 2C70h 2C71h 2C72h 2C73h 2C 74h 2C75h 2C76h 2C77h DTCD7 Control Data 7 2C78h to 2C7Fh 2C78h 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh DTCD8 Control Data 8 2C80h to 2C87h 2C80h 2C81h 2C82h 2C83h 2C 84h 2C85h 2C86h 2C87h DTCD9 Control Data 9 2C88h to 2C8Fh 2C88h 2C89h 2C8Ah 2C8Bh 2C8Ch 2C8Dh 2C8Eh 2C8Fh DTCD10 Control Data 10 2C90h to 2C97h 2C90h 2C91h 2C92h 2C93h 2C 94h 2C95h 2C96h 2C97h DTCD11 Control Data 11 2C98h to 2C9Fh 2C98h 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh DTCD12 Control Data 12 2CA0h to 2CA7h 2CA0h 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h DTCD13 Control Data 13 2CA8h to 2CAFh 2CA8h 2CA9h 2CAAh 2CABh 2CACh 2CADh 2CAEh 2CAFh DTCD14 Control Data 14 2CB0h to 2CB7h 2CB0h 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h DTCD15 Control Data 15 2CB8h to 2CBFh 2CB8h 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh DTCD16 Control Data 16 2CC0h to 2CC7h 2CC0h 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h DTCD17 Control Data 17 2CC8h to 2CCFh 2CC8h 2CC9h 2CCAh 2CCBh 2CCCh 2CCDh 2CCEh 2CCFh DTCD18 Control Data 18 2CD0h to 2CD7h 2CD0h 2CD1h 2CD2h 2CD3h 2CD4h 2CD5h 2CD6h 2CD7h DTCD19 Control Data 19 2CD8h to 2CDFh 2CD8h 2CD9h 2CDAh 2CDBh 2CDCh 2CDDh 2CDEh 2CDFh DTCD20 Control Data 20 2CE0h to 2CE7h 2CE0h 2CE1h 2CE2h 2CE3h 2CE4h 2CE5h 2CE6h 2CE7h DTCD21 Control Data 21 2CE8h to 2CEFh 2CE8h 2CE9h 2CEAh 2CEBh 2CECh 2CEDh 2CEEh 2CEFh DTCD22 Control Data 22 2CF0h to 2CF7h 2CF0h 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h DTCD23 Control Data 23 2CF8h to 2CFFh 2CF8h 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 228 of 809 16. DTC Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group When the DTC is activated, one control data is selected according to the data read from the vector table which has been assigned to each activation s ource, and the selected control data is read from the DTC control data area. Table 16.5 shows the DTC Activation Sources and DTC Ve ctor Addresses. A one-byte vector table area is assigned to each activation source and one value from 00000000b to 00010111b (control data numbers in Table 16.4) is stored in each area to select one of the 24 control data sets. Figures 16.3 to 16.6 show the DTC Internal Operation Flowchart. Table 16.5 DTC Activation Sources and DTC Vector Addresses Interrupt Request Source Interrupt Name So urce No. DTC Vector Address Priority External input INT0 0 2C00h High INT1 1 2C01h INT2 2 2C02h INT3 3 2C03h INT4 4 2C04h INT5 5 2C05h INT6 6 2C06h INT7 7 2C07h Key input Key input 8 2C08h A/D A/D conversion 9 2C09h UART0 UART0 reception 10 2C0Ah UART0 transmission 11 2C0Bh UART1 UART1 reception 12 2C0Ch UART1 transmission 13 2C0Dh UART2 UART2 reception 14 2C0Eh UART2 transmission 15 2C0Fh SSU/I2C bus Receive data full 16 2C10h Transmit data empty 17 2C11h Voltage detection circuit Comparator A2 18 2C12h Comparator A1 19 2C13h Timer RC Input-capture/compare-match A 22 2C16h Input-capture/compare-match B 23 2C17h Input-capture/compare-match C 24 2C18h Input-capture/compare-match D 25 2C19h Timer RD0 Input-capture/c ompare-match A 26 2C1Ah Input-capture/compare-match B 27 2C1Bh Input-capture/compare-match C 28 2C1Ch Input-capture/compare-match D 29 2C1Dh Timer RD1 Input-capture/c ompare-match A 30 2C1Eh Input-capture/compare-match B 31 2C1Fh Input-capture/compare-match C 32 2C20h Input-capture/compare-match D 33 2C21h Timer RE Timer RE 42 2C2Ah Timer RG Input-capture/compare-match A 47 2C2Fh Input-capture/compare-match B 48 2C30h Timer RA Timer RA 49 2C31h Timer RB Timer RB 51 2C33h Flash memory Flash memory ready status 52 2C34h Low

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16.3.4 Normal Mode

One to 256 bytes of data are transferred by one activatio n. The number of transfer times can be 1 to 256. When the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 is performed, an interrupt request for the CPU is generated during DTC operation. Table 16.6 shows Register Functions in Normal Mode. Figure 16.7 shows Data Transfers in Normal Mode. j =0 to 23 Figure 16.7 Data Transfers in Normal Mode Table 16.6 Register Functions in Normal Mode Register Symbol Function DTC block size register j DTBLSj Size of the data block to be transferred by one activation DTC transfer count register j DTCCTj Number of times of data transfers DTC transfer count reload register j DTRLDj Not used DTC source address register j DT SARj Data transfer source address DTC destination address register j DTDARj Data transfer destination address SRC Transfer DST Transfer source Transfer destination Size of the data block to be transferred by one activation (N bytes) DTBLSj = N DTSARj = SRC DTDARj = DST j = 0 to 23 Bits b3 to b0 in DTCCR register 00X0b 01X0b 10X0b 11X0b Source address control Fixed Incremented Fixed Incremented Destination address control Fixed Fixed Incremented Incremented Source address after transfer SRC SRC+N SRC SRC+N Destination address after transfer DST DST DST+N DST+N X: 0 or 1

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16.3.5 Repeat Mode

One to 255 bytes of data are transferred by one activation. Either of the transfer source or destination should be specified as the repeat area. The nu mber of transfer times can be 1 to 255. On completion of the specified number of transfer times, the DTCCTj (i =0 to 23) register and the addre ss specified for the repeat area are initialized to continue transfers. When the data transfer causing the DTCCTj register value to change to 0 is performed while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled), an interrupt request for the CPU is generated during DTC operation. The lower 8 bits of the initial value for the repeat area a ddress must be 00h. The size of data to be transferred must be set to 255 bytes or less before the specified number of transfer times is completed. Table 16.7 shows Register Functions in Repeat Mode. Figure 16.8 shows Data Transfers in Repeat Mode. j =0 to 23 Figure 16.8 Data Transfers in Repeat Mode Table 16.7 Register Functions in Repeat Mode Register Symbol Function DTC block size register j DTBLSj Size of the data block to be transferred by one activation DTC transfer count register j DTCCTj Number of times of data transfers DTC transfer count reload register j DTRLDj This register value is reloaded to the DTCCT register. (Data transfer count is initialized.) DTC source address register j DT SARj Data transfer source address DTC destination address register j DTD ARj Data transfer destination address SRC Transfer DST Transfer source Transfer destination Size of the data block to be transferred by one activation (N bytes) DTBLSj = N DTCCTj ≠ 1 DTSARj = SRC DTDARj = DST j = 0 to 23 Bits b3 to b0 in DTCCR register 0X11b 1X11b X001b X101b Source address control Repeat area Repeat area Fixed Incremented Destination address control Fixed Incremented Repeat area Repeat area Source address after transfer SRC+N SRC+N SRC SRC+N Destination address after transfer DST DST+N DST+N DST+N DTCCTj register = 1 SRC0/DST0 Repeat area Bits b3 to b0 in DTCCR register 0X11b 1X11b X001b X101b Source address control Repeat area Repeat area Fixed Incremented Destination address control Fixed Incremented Repeat area Repeat area Source address after transfer SRC0 SRC0 SRC SRC+N Destination address after transfer DST DST+N DST0 DST0 SRC/DST Address of the repeat area is initialized after a transfer. DTBLSj = N DTCCTj = 1 DTSARj = SRC DTDARj = DST j = 0 to 23 SRC0: Initial source address value DST0: Initial destination address value X: 0 or 1 X: 0 or 1 DTCCTj register ≠ 1

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16.3.6 Chain Transfers

When the CHNE bit in the DTCCRj (j = 0 to 22) register is 1 (chain transfers enabled), multiple data transfers can be continuously performed by one activation source. Figure 16.9 shows a Flow of Chain Transfers. When the DTC is activated, one control data is selected according to the data read from the DTC vector address corresponding to the activation source, and the selected control data is read from the DTC control data area. When the CHNE bit for the control data is 1 (chain transfers enabled), the next control data immediately following the current control data is read and transferred after the current transfer is completed. This operation is repeated until the data transfer with the control data for which the CHNE bit is 0 (chain transfers disabled) is completed. Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled). Figure 16.9 Flow of Chain Transfers

16.3.7 Interrupt Sources

When the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 is performed in normal mode, and when the data transfer causing the DTCCTj register valu e to change to 0 is performed while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled) in repeat mode, the interrupt request corresponding to the activation sour ce is generated for the CPU during DTC operation. However, no interrupt request is generated for the CPU when the activation source is SSU/I2C bus transmit data empty. Interrupt requests for the CPU are affected by the I flag or interrupt control register. In chain transfers, whether the interrupt request is generated or not is determined either by the number of transfer times specified for the first type of the transfer or the RPTI NT bit. When an interrup t request is generated for the CPU, the bit among bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 6) registers corresponding to the activation source are set to 0 (activation disabled). DTC activation source generation Read DTC vector Read control data 1 Transfer data Write back control data 1 Read control data 2 Data transfer Write back control data 2 End of DTC transfers Control data 1 CHNE = 1 Control data 2 CHNE = 0 DTC control data area CHNE: Bit in DTCCRj register

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 234 of 809 16. DTC Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

16.3.8 Operation Timings

The DTC requires four clock cycles to read control data allocated in the DTC control data area. The number of clock cycles required to write back control data differs depending on the control data settings. Figure 16.10 shows an Example of DTC Operation Timings and Figure 16.11 shows an Example of DTC Operation Timings in Chain Transfers. Table 16.8 shows the Specifications of Control Data Write-Back Operation. Figure 16.10 Example of DTC Operation Timings Figure 16.11 Example of DTC Operation Timings in Chain Transfers j = 0 to 23 X: 0 or 1 Table 16.8 Specifications of Control Data Write-Back Operation Bits b3 to b0 in DTCCR Register Operating Mode Address Control Control Data to be Written Back Number of Clock CyclesSource Destination DTCCTj Register DTRLDj Register DTSARj Register DTDARj Register 00X0b Normal mode Fixed Fixed Written back Written back Not written back Not written back 1 01X0b Incremented Fixed Written back Written back Written back Not written back 2 10X0b Fixed Incremented Written back Written back Not written back Written back 2 11X0b Incremented Incremented Written bac k Written back Written back Written back 3 0X11b Repeat mode Repeat area Fixed Written back Wri tten back Written back Not written back 2 1X11b Incremented Written back Wri tten back Written back Written back 3 X001b Fixed Repeat area Written back Written back Not written back Written back 2 X101b Incremented Written back Writt en back Written back Written back 3 Used by CPU Read Write Used by CPU Read control data Transfer data Write back control data Read vector CPU clock Address Used by CPU Read Write Used by CPU Read vector Read control data Transfer data Write back control data Read control data Transfer data Write back control data CPU clock Address Read Write

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 235 of 809 16. DTC Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

16.3.9 Number of DTC Execution Cycles

Table 16.9 shows the Operations Following DTC Activ ation and Required Number of Cycles for each operation. Table 16.10 shows the Number of Clock Cycles Required for Data Transfers. Note: 1. For the number of clock cycles required for data read/write, see Table 16.10 Number of Clock Cycles Required for Data Transfers. Data is transferred as described below, when the DTBLSj (j = 0 to 23) register = N, (1) When N = 2n (even), two-byte transfers are performed n times. (2) When N = 2n + 1 (odd), 2-byte transfers are perf ormed n times followed by one 1-byte transfer. From Tables 16.9 and 16.10, the total number of required execution cycles can be obtained by the following formula: Number of required execution cycles = 1 + Σ[formula A] + 2 Σ: Sum of the cycles for th e number of transfer times performed by one activation sour ce ([the number of transfer times for which CHNE is set to 1] + 1) (1) For N = 2n (even) Formula A = J + n • SK2 + n • SL2 (2) For N = 2n+1 (odd) Formula A = J + n • SK2 + 1 • SK1 + n • SL2 + 1 • SL1 J: Number of cycles required to read or write back control data Table 16.9 Operations Following DTC Activation and Required Number of Cycles Vector Read Control Data Read/Write (J) Data Read Data Write Internal Operation 1 5 to 7 (Note 1) (Note 1) 2 1 5 to 7 (Note 1) (Note 1) 2 Table 16.10 Number of Clock Cycles Required for Data Transfers Operation Unit of Transfers On-Chip RAM (During DTC Transfers) On-Chip ROM (User Area) On-Chip ROM (Data Area) SFR (Word Access) SFR (Byte Access)Even Address Odd Address Even Address Odd Address Data read 1-byte SK1 1 1 2 2 2 2 - b y t e S K 2 1224244 Data write 1-byte SL1 1 —— 22 2-byte SL2 12 —— 244

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 236 of 809 16. DTC Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

16.3.10 DTC Activation Source Acknowle dgement and Interrupt Source Flags

16.3.10.1 Interrupt Sources Except for Flash Memory, Timer RC, Timer RD, and

Synchronous Serial Communication Unit (SSU)/I2C bus When the DTC activation source is an interrupt source except for the flash memory, timer RC, timer RD, or the synchronous serial communication unit/I2C bus, the same DTC activation source cannot be acknowledged for 8 to 12 cycles of the CPU clock after the interrupt source is generated. If a DTC activation source is generated during DTC operation and acknowledged, the same DTC activation source cannot be acknowledged for 8 to 12 cycles of the CPU clock on completion of the DTC tran sfer immediately before the DTC is activated by the source.

16.3.10.2 Flash Memory

When the DTC activation source is flash memory ready status, even if a flash memory ready status interrupt request is generated, it is not ac knowledged as the DTC activation source after the RDYSTI bit in the FST register is set to 1 (flash memory ready status interrupt request) and before the DTC sets the RDYSTI bit to 0 (no flash memory ready status interrupt request). If a flash memory ready st atus interrupt request is generated after the DTC sets the RDYSTI bit to 0, the DTC acknowledges it as the activation source. 8 to 12 cycles of the CPU clock are required after the RDYSTI bit is set to 1 and before the DTC sets the interrupt request flag to 0. If a flash memory ready st atus interrupt request is generated during DTC operation and acknowledged as the DTC activation source, the RD YSTI bit is set to 0 after 8 to 12 cycl es of the CPU clock on completion of the DTC transfer immediately before the DTC is activated by the source.

16.3.10.3 Timer RC, Timer RD

When the DTC activation source is an interrupt source for timer RC or timer RD, even if an input capture/compare match in individual timers occurs, it is not acknowledged as the DT C activation source after the interrupt source flag is set to 1 and before the DT C sets the flag to 0. If an input capture/compare match occurs after the DTC sets the interr upt source flag to 0, the DTC acknowl edges it as the activation source. 8 to 12 cycles of the CPU clock plus 0.5 to 1.5 cycles of the timer operating clock are required after the interrupt source flag is set to 1 and before the DTC sets the flag to 0. If individual DTC activation sources are generated for timer C and timer D during DTC operation and acknowledged, the interrupt source flag is set to 0 after 8 to 12 cycles of the CPU clock plus 0.5 to 1.5 cycles of the timer operating clock on completion of the DTC transfer immediately before the DTC is activated by the source.

16.3.10.4 SSU/I 2C bus Receive Data Full

When the DTC activation source is SSU/I2C bus receive data full, read the SSRDR register/the ICDRR register using a data transfer. The RDRF bit in the SSSR re gister/the ICSR register is set to 0 (no data in SSRDR/ICDRR register) by reading the SSRDR register/ the ICDRR register. If an interrupt source for receive data full is subsequently generated, the DTC acknowledges it as the activation source.

16.3.10.5 SSU/I 2C bus Transmit Data Empty

When the DTC activation source is SSU/I 2C bus transmit data empty, write to the SSTDR register/the ICDRT register using a data transfer. The TDRE bit in the SSSR register/the ICSR register is set to 0 (data is not transferred from registers SSTDR/ICDRT to SSTRSR/IC DRS) by writing to the SSTDR register/the ICDRT register. If an interrupt source for transmit data empty is subsequently generated, the DTC acknowledges it as the activation source.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 237 of 809 16. DTC Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

16.4 Notes on DTC

16.4.1 DTC activation source

• Do not generate any DTC activation sources before entering wait mode or during wait mode.
• Do not generate any DTC activation sources before entering stop mode or during stop mode.

16.4.2 DTCENi (i = 0 to 6) Registers

• Modify bits DTCENi0 to DTCENi7 only while an interrupt request corresponding to the bit is not generated.
• When the interrupt source flag in the status register for the peripheral function is 1, do not modify the corresponding activation source bit among bits DTCENi0 to DTCENi7.
• Do not access the DTCENi register using a DTC transfer.

16.4.3 Peripheral Modules

• Do not set the status register bit for the peripheral function to 0 using a DTC transfer.
• When the DTC activation source is SSU/I 2C bus receive data full, read the SSRDR register/the ICDRR register using a DTC transfer. The RDRF bit in the SSSR register/the ICSR register is set to 0 (no data in SSRDR/ICDRR register) by reading the SSRDR register/the ICDRR register. However, the RDRF bit is not set to 0 by reading the SSRDR register/the ICDRR register when the DTC data transfer setting is either of the following: - Transfer causing the DTCCTj (j = 0 to 23) register value to change from 1 to 0 in normal mode - Transfer causing the DTCCRj regist er value to change from 1 to 0 while the RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled) in repeat mode.
• When the DTC activation source is SSU/I 2C bus transmit data empty, write to the SSTDR register/the ICDRT register using a DTC transfer. The TDRE bit in the SSSR register/the ICSR register is set to 0 (data is not transferred from registers SSTDR/ICDRT to SSTRSR/ICDRS) by writing to the SSTDR register/the ICDRT register.

1. Timers REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 238 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 17. Timers The following six types of timers are available:

• Timer RA: 8-bit timer with an 8-bit prescaler
• Timer RB: 8-bit timer with an 8-bit prescaler
• Timer RC: 16-bit timer
• Timer RD: Two 16-bit timers
• Timer RE: 4-bit counter and 8-bit counter
• Timer RG: 16-bit timer All these timers operate independently.

1. Timers REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 239 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Notes: 1. Rectangular waves are output in these modes. Since the waves are inverted at each overflow, the “H” and “L” level widths of the pulses are the same. 2. The underflow interrupt can be set to timer RD1 and timer RG. Table 17.1 Functional Comparison of Timers Item Timer RA0 Timer RB Timer RC Timer RD Timer RE Timer RG Configuration 8-bit timer with 8-bit prescaler (with reload register) 8-bit timer with 8-bit prescaler (with reload register) 16-bit timer (with input capture and output compare) 16-bit timer × 2 (with input capture and output compare) 4-bit counter 8-bit counter 16-bit timer (with input capture and output compare) Count Decrement Decrement Increment Increment/Decrement Increment Increment/ Decrement Count sources • f1

• f 2
• f 8
• f O C O
• f C 3 2
• f C
• f 1
• f 2
• f 8
• T i m e r R A underflow
• f 1
• f 2
• f 4
• f 8
• f 3 2
• fOCO40M
• fOCO-F
• TRCCLK
• f 1
• f 2
• f 4
• f 8
• f 3 2
• fOCO40M
• fOCO-F
• TRDCLK
• f 4
• f 8
• f 3 2
• f C 4
• f 1
• f 2
• f 4
• f 8
• f 3 2
• fOCO40M
• T R G C L K A
• T R G C L K B Function Count of the internal count source Timer mode Timer mode Timer mode (output compare function) Timer mode (output compare function) —T i m e r m o d e (output compare function) Count of the external count source Event counter mode — Timer mode (output compare function) Timer mode (output compare function) —T i m e r m o d e (output compare function), Please counting mode External pulse width/period measurement Pulse width measurement mode, pulse period measurement mode — Timer mode (input capture function; 4 pins) Timer mode (input compare function; 2 × 4 pins) —T i m e r m o d e (Input capture function; 2 pins) PWM output Pulse output mode (1), Event counter mode (1) Programmable waveform generation mode Timer mode (output compare function; 4 pins) (1), PWM mode (3 pins), PWM2 mode (1 pin) Timer mode (output compare function; 2 × 4 pins) (1), PWM mode (2 × 3 pins), PWM3 mode (2 × 2 pins) Output compare mode (1) Timer mode (output compare function; 2 pins), PWM mode (1 pin) One-shot waveform output — Programmable one-shot generation mode, Programmable wait one-shot generation mode PWM mode (3 pins) PWM mode (2 × 3 pins) Three-phase waveforms output — — — Reset synchronous PWM mode (2 × 3 pins, Sawtooth wave modulation), Complementary PWM mode (2 × 3 pins, triangular wave modulation, dead time) Timer Timer mode (only fC32 count) — — — Real-time clock mode Input pin TRAIO INT0 INT0, TRCCLK, TRCTRG, TRCIOA, TRCIOB, TRCIOC, TRCIOD INT0 , TRDCLK, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 — TRGCLKA, TRGCLKB, TRGIOA, TRGIOB Output pin TRAO TRAIO TRBO TRCIOA, TRCIOB, TRCIOC, TRCIOD TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 TREO TRGIOA, TRGIOB Related interrupt Timer RA interrupt Timer RB interrupt, INT0 interrupt Compare match/input capture A to D interrupt, Overflow interrupt, INT0 interrupt Compare match/input capture A0 to D0 interrupt, Compare match/input capture A1 to D1 interrupt, Overflow interrupt, Underflow interrupt (2), INT0 interrupt Timer RE interrupt Compare match/ input capture A to B interrupt, Underflow interrupt (2), Overflow interrupt Timer stop Provided Provided Provided Provided Provided Provided

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 240 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 18. Timer RA Timer RA is an 8-bit timer with an 8-bit prescaler.

18.1 Introduction

The prescaler and timer each consist of a reload register a nd counter. The reload register and counter are allocated at the same address, and can be accessed when accessing registers TRAP RE and TRA (refer to Tables 18.2 to 18.6 the Specifications of Each Mode). The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting and reloading. Figure 18.1 shows the Timer RA Block Diagram. Table 18.1 lists the Timer RA Pin Configuration. Timer RA supports the following five operating modes:

• Timer mode: The timer counts an internal count source.
• Pulse output mode: The timer counts an internal count source and outputs pulses which invert the polarity by underflow of the timer.
• Event counter mode: The timer counts external pulses.
• Pulse width measurement mode: T he timer measures the pulse width of an external pulse.
• Pulse period measurement mode: The timer measures the pulse period of an external pulse. Figure 18.1 Timer RA Block Diagram Table 18.1 Timer RA Pin Configuration Pin Name Assigned Pin I/O Function TRAIO P11_4 I/O Function differs according to the mode. Refer to descriptions of individual modes for details.TRAO P11_5 Output Bits TCK2 to TCK0 Bits TMOD2 to TMOD0 = other than 010b Counter Reload register TRAPRE register (prescaler) Data bus Timer RA interrupt Write to TRAMR register Write 1 to TSTOP bit TCSTF, TSTOP: Bits in TRACR register TEDGSEL, TOPCR, TOENA, TIPF1, TIPF0, TIOGT1, TIOGT0: Bits in TRAIOC register TMOD0 to TMOD2, TCK0 to TCK2, TCKCUT: Bits in TRAMR register Toggle flip-flop Q Q CLR CK TOENA bit TRAO pin TCSTF bit TCKCUT bit Bits TMOD2 to TMOD0 = 011b or 100b Bits TMOD2 to TMOD0 = 010b Polarity switching Digital filter Counter Reload register TRA register (timer) Bits TIPF1 to TIPF0 = 01b = 10bf8 = 11bf32 Count control circuit Bits TMOD2 to TMOD0 = 001b TOPCR bit Underflow signal Measurement end signal Bits TIPF1 to TIPF0 = other than 000b = 00b TEDGSEL = 1 TEDGSEL = 0 = 000b = 001b = 011bf2 = 010bfOCO = 100bfC32 Bits TIOGT1 to TIOGT0 = 01b = 10b Event input enabled for “H” period of INT2 Event input always enabled= 00b Event input enabled for “H” period of TRCIOD (timer RC compare match signal) = 110bfC TRAIO pin

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 241 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.2 Registers

18.2.1 Timer RA Cont rol Register (TRACR)

Notes: 1. Refer to 18.8 Notes on Timer RA for notes regarding bits TSTART and TCSTF. 2. When 1 is written to the TSTOP bit, bits TSTART and TCSTF and registers TPRAPRE and TRA are set to the values after a reset. 3. Bits TEDGF and TUNDF can be set to 0 by writing 0 to these bits by a program. However, their value remains unchanged when 1 is written. 4. Set to 0 in timer mode, pulse output mode, and event counter mode. In pulse width measurement mode and pulse period m easurement mode, use the MOV instruction to set the TRACR register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, write 1 to them.

18.2.2 Timer RA I/O Cont rol Register (TRAIOC)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — TUNDF TEDGF — TSTOP TCSTF TSTART A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TSTART Timer RA count start bit (1) 0: Count stops 1: Count starts R/W b1 TCSTF Timer RA count status flag (1) 0: Count stops 1: During count operation R b2 TSTOP Timer RA count forcible stop bit (2) When this bit is set to 1, the count is forcibly stopped. When read, the content is 0. R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 TEDGF Active edge judgment flag (3, 4) 0: Active edge not received 1: Active edge received (end of measurement period) R/W b5 TUNDF Timer RA underflow flag (3, 4) 0: No underflow 1: Underflow R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 — Address 0101h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TEDGSEL TRAIO polarity switch bit Function varies according to the operating mode. R/W b1 TOPCR TRAIO output control bit R/W b2 TOENA TRAO output enable bit R/W b3 TIOSEL Hardware LIN function select bit R/W b4 TIPF0 TRAIO input filter select bit R/W b5 TIPF1 R/W b6 TIOGT0 TRAIO event input control bit R/W b7 TIOGT1 R/W

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 242 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.2.3 Timer RA Mode Register (TRAMR)

When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rewrite the TRAMR register.

18.2.4 Timer RA Prescal er Register (TRAPRE)

Note: 1. When 1 is written to the TSTOP bit in the TRACR register, the TRAPRE register is set to FFh. Address 0102h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TCKCUT TCK2 TCK1 TCK0 — TMOD2 TMOD1 TMOD0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TMOD0 Timer RA operating mode select bit b2 b1 b0 0 0 0: Timer mode 0 0 1: Pulse output mode 0 1 0: Event counter mode 0 1 1: Pulse width measurement mode 1 0 0: Pulse period measurement mode 1 0 1: Do not set. 1 1 0: Do not set. 1 1 1: Do not set. R/W b1 TMOD1 R/W b2 TMOD2 R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 TCK0 Timer RA count source select bit b6 b5 b4 0 0 0: f1 0 0 1: f8 0 1 0: fOCO 0 1 1: f2 1 0 0: fC32 1 0 1: Do not set. 1 1 0: fC 1 1 1: Do not set. R/W b5 TCK1 R/W b6 TCK2 R/W b7 TCKCUT Timer RA count source cutoff bit 0: Count source provided 1: Count source cut off R/W Address 0103h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 ( N o t e 1 ) Bit Mode Function Setting Range R/W b7 to b0 Timer mode Counts an internal count source. 00h to FFh R/W Pulse output mode 00h to FFh R/W Event counter mode Counts an external count source. 00h to FFh R/W Pulse width measurement mode Measures the pulse width of input pulses from external (counts an internal count source). 00h to FFh R/W Pulse period measurement mode Measures the pulse period of input pulses from external (counts an internal count source). 00h to FFh R/W

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 243 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.2.5 Timer RA Register (TRA)

Note: 1. When 1 is written to the TSTOP bit in the TRACR register, the TRAPRE register is set to FFh.

18.2.6 Timer RA Pin Se lect Register (TRASR)

Note: 1. To use hardware LIN, set 01b to bits TRAIOSEL1 to TRAIOSEL0. To use the I/O pin for timer RA, set the TRASR register. Set this register before setting the timer RA associated registers. Also, do not change the setting value of this register during timer RA operation. Address 0104h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 ( N o t e 1 ) Bit Mode Function Setting Range R/W b7 to b0 All modes Counts the TRAPRE register underflows. 00h to FFh R/W Address 0180h B i t b 7b 6b 5 b 4 b 3 b 2 b 1 b 0 Symbol — — — — — — TRAIOSEL1 TRAIOSEL0 A f t e r R e s e t 000 0 0 0 0 0 Bit Symbol Bit Name Function R/W b0 TRAIOSEL0 TRAIO pin select bit b1 b0 0 0: TRAIO pin not used 0 1: P11_4 assigned 1 0: INT4 assigned 1 1: Do not set. R/W b1 TRAIOSEL1 R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b3 — b4 — b5 — b6 — b7 —

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 244 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.3 Timer Mode

In this mode, the timer counts an internally generated count source (refer to Table 18.2).

18.3.1 Timer RA I/O Control Regi ster (TRAIOC) in Timer Mode

Table 18.2 Timer M ode Specifications Item Specification Count sources f1, f2, f8, fOCO, fC32 Count operations • Decrement

• When the timer underflows, the contents of the reload register are reloaded and the count is continued. Division ratio 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register Count start condition 1 (count starts) is writ ten to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is writte n to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request generation timing When timer RA underflows [timer RA interrupt]. TRAIO pin function Programmable I/O port TRAO pin function Programmable I/O port Read from timer The count value can be read out by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during count operation, values are written to the reload register and counter (refer to

18.3.2 Timer Write

Control during Count Operation). Address 0101h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TEDGSEL TRAIO polarity switch bit Set to 0 in timer mode. R/W b1 TOPCR TRAIO output control bit R/W b2 TOENA TRAO output enable bit R/W b3 TIOSEL Hardware LIN function select bit Set to 0. However, set to 1 when the hardware LIN function is used. R/W b4 TIPF0 TRAIO input filter select bit Set to 0 in timer mode. R/W b5 TIPF1 R/W b6 TIOGT0 TRAIO event input control bit R/W b7 TIOGT1 R/W

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 245 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.3.2 Timer Write Contro l during Count Operation

Timer RA has a prescaler and a time r (which counts the prescaler unde rflows). The prescaler and timer each consist of a reload register and a coun ter. When writing to the prescaler or timer, values are written to both the reload register and counter. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed. Figure 18.2 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count Operation. Figure 18.2 Operating Example of Timer RA when Counter Value is Rewritten during Count Operation Count source Reload register of timer RA prescaler IR bit in TRAIC register 0 Counter of timer RA prescaler Reload register of timer RA Counter of timer RA Write 01h into the TRAPRE register and 25h into the TRA register by a program. After writing, the reload register is written with the first count source. Reload with the second count source Reload at underflow After writing, the reload register is written at the first underflow.Reload at the second underflow The IR bit remains unchanged until underflow is generated by a new value. 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h New value (01h)Previous value New value (25h)Previous value 03h 24h 02h 25h The above applies under the following condition: Both the TSTART and TCSTF bits in the TRACR register are set to 1 (during count operation).

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 246 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.4 Pulse Output Mode

In pulse output mode, an internally generated count so urce is counted, and a pulse with inverted polarity is output from the TRAIO pin each time the timer underflows (refer to Table 18.3). Note: 1. By writing to the TRAMR register, the output puls e is set to the level when the pulse output starts. Table 18.3 Pulse Output Mode Specifications Item Specification Count sources f1, f2, f8, fOCO, fC32, fC Count operations • Decrement

• When the timer underflows, the contents of the reload register are reloaded and the count is continued. Division ratio 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register Count start condition 1 (count starts) is writte n to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is writ ten to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request generation timing When timer RA underflows [timer RA interrupt]. TRAIO pin function Pulse output or programmable output port TRAO pin function Programmable I/O po rt or inverted output of TRAIO Read from timer The count value can be read out by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during count operation, values are written to the reload register and counter (refer to 18.3.2 Timer Write Control during Count Operation). Selectable functions • TRAIO signal polarity switch function The level when the pulse output starts is selected by the TEDGSEL bit in the TRAIOC register. (1)
• TRAO output function Pulses inverted from the TRAIO output polarity can be output from the TRAO pin (selectable by the TOENA bit in the TRAIOC register).
• Pulse output stop function Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC register.
• TRAIO pin select function Use of the TRAIO pin is selected by the TRAIOSEL0 bit in the TRASR register.

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 247 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.4.1 Timer RA I/O Cont rol Register (TRAIOC) in Pulse Output Mode

B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TEDGSEL TRAIO polarity switch bit 0: TRAIO output starts at high 1: TRAIO output starts at low R/W b1 TOPCR TRAIO output control bit 0: TRAIO output 1: Port P11_4 R/W b2 TOENA TRAO output enable bit 0: Port P11_5 1: TRAO output (inverted TRAIO output is output from P11_5) R/W b3 TIOSEL Hardware LIN function select bit Set to 0. R/W b4 TIPF0 TRAIO input filter select bit Set to 0 in pulse output mode. R/W b5 TIPF1 R/W b6 TIOGT0 TRAIO event input control bit R/W b7 TIOGT1 R/W

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 248 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.5 Event Counter Mode

In event counter mode, external signal inputs to the TRAIO pin are counted (refer to Table 18.4). Note: 1. By writing to the TRAMR register, the output puls e is set to the level when the pulse output starts. Table 18.4 Event Counter Mode Specifications Item Specification Count source External signal input to the TRAI O pin (active edge selectable by a program) Count operations • Decrement

• When the timer underflows, the contents of the reload register are reloaded and the count is continued. Division ratio 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register Count start condition 1 (count starts) is writte n to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request generation timing When timer RA underflows [timer RA interrupt]. TRAIO pin function Count source input TRAO pin function Programmable I/O port or pulse output (1) Read from timer The count value can be read out by reading registers TRA and TRAPRE. Write to timer • When register s TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during count operation, values are written to the reload register and counter (refer to 18.3.2 Timer Write Control during Count Operation). Selectable functions •I N T 2 input polarity switch function The active edge of the count source is selected by the TEDGSEL bit in the TRAIOC register.
• Count source input pin select function Use of the TRAIO pin is selected by the TRAIOSEL0 bit in the TRASR register.
• Pulse output function Pulses of inverted polarity can be output from the TRAO pin each time the timer underflows (selectable by the TOENA bit in the TRAIOC register). (1)
• Digital filter function Whether enabling or disabling the digital filter and the sampling frequency is selected by bits TIPF0 and TIPF1 in the TRAIOC register.
• Event input control function The enabled period for the event input to the TRAIO pin is selected by bits TIOGT0 and TIOGT1 in the TRAIOC register.

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 249 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.5.1 Timer RA I/O Cont rol Register (TRAIOC) in Event Counter Mode

Note: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. Address 0101h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TEDGSEL TRAIO polarity switch bit 0: Count at the rising edge of TRAIO input and TRAO output starts at low 1: Count at the falling edge of TRAIO input and TRAO output starts at high R/W b1 TOPCR TRAIO output control bit Set to 0 in event counter mode. R/W b2 TOENA TRAO output enable bit 0: Port P11_05 1: TRAO output R/W b3 TIOSEL Hardware LIN function select bit Set to 0. R/W b4 TIPF0 TRAIO input filter select bit (1) b5 b4 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b5 TIPF1 R/W b6 TIOGT0 TRAIO event input control bit b7 b6 0 0: Event input always enabled 0 1: Event input enabled for high-level period of INT2 1 0: Event input enabled for low-level period of timer RC compare match signal 1 1: Do not set. R/W b7 TIOGT1 R/W

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 250 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.6 Pulse Width Measurement Mode

In pulse width measurement mode, the pulse width of an external si gnal input to the TRAIO pin is measured (refer to Table 18.5). Figure 18.3 shows an Operating Example in Pulse Width Measurement Mode. Table 18.5 Pulse Width Measurement Mode Specifications Item Specification Count sources f1, f2 , f8, fOCO, fC32, fC Count operations • Decrement

• The count is continued only while the measured pulse is high or low level.
• When the timer underflows, the contents of the reload register are reloaded and the count is continued. Count start condition 1 (count starts) is writte n to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is writ ten to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request generation timing
• When timer RA underflows [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA interrupt] TRAIO pin function Measured pulse input TRAO pin function Programmable I/O port Read from timer The count value can be read out by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TR A are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during count operation, values are written to the reload register and counter (refer to

Control during Count Operation). Selectable functions • Measurement level setting A high-level or low-level period is selected by the TEDGSEL bit in the TRAIOC register.

• Measured pulse input pin select function Use of the TRAIO pin is selected by bits TRAIOSEL0 in the TRASR register.
• Digital filter function Whether enabling or disabling the digital filter and the sampling frequency is selected by bits TIPF0 and TIPF1 in the TRAIOC register.

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 251 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.6.1 Timer RA I/O Control Register (TRAIOC) in Pulse Width Measurement

Note: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. Address 0101h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TEDGSEL TRAIO polarity switch bit 0: Low-level width of TRAIO input is measured 1: High-level width of TRAIO input is measured R/W b1 TOPCR TRAIO output control bit Set to 0 in pulse width measurement mode. R/W b2 TOENA TRAO output enable bit R/W b3 TIOSEL Hardware LIN function select bit Set to 0. However, set to 1 when the hardware LIN function is used. R/W b4 TIPF0 TRAIO input filter select bit (1) b5 b4 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b5 TIPF1 R/W b6 TIOGT0 TRAIO event input control bit Set to 0 in pulse width measurement mode. R/W b7 TIOGT1 R/W

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 252 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.6.2 Operating Example

Figure 18.3 Operating Example in Pulse Width Measurement Mode FFFFh n 0000h Content of counter (hex) n = higher: content of TRA register; lower: content of TRAPRE register Measurement starts Measurement stops Underflow Period TSTART bit in TRACR register Measured pulse (TRAIO pin input) TEDGF bit in TRACR register TUNDF bit in TRACR register

• High-level width of measured pulse is measured. (TEDGSEL = 1)
• TRAPRE = FFh Set to 1 by a program. IR bit in TRAIC register Set to 0 by a program. Measurement stops Measurement starts Set to 0 when an interrupt request is acknowledged or by a program. Measurement starts Set to 0 by a program. The above applies under the following conditions:

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 253 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.7 Pulse Period Measurement Mode

In pulse period measur ement mode, the pulse period of an external signal input to the TRAIO pin is measured (refer to Table 18.6). Figure 18.4 shows an Operating Example in Pulse Period Measurement Mode. Note: 1. Input a pulse with a period longer than twice the timer RA prescaler period. Also, input a pulse with a longer high-/low-level width than the timer RA prescaler period. If a pulse with a shorter period is input to the TRAIO pin, the input may be ignored. Table 18.6 Pulse Period Measurement Mode Specifications Item Specification Count sources f1, f2, f8, fOCO, fC32, fC Count operations • Decrement

• After the active edge of the measured pulse is input, the contents of the read- out buffer are retained at the first underflow of timer RA prescaler. Then timer RA reloads the contents of the reload register at the second underflow of timer RA prescaler and continues counting. Count start condition 1 (count starts) is writte n to the TSTART bit in the TRACR register. Count stop conditions • 0 (count stops) is wr itten to TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request generation timing
• When timer RA underflows or reloads [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA interrupt] TRAIO pin function Measured pulse input (1) TRAO pin function Programmable I/O port Read from timer The count value can be re ad out by reading registers TRA and TRAPRE. Write to timer • When registers TRAPRE and TR A are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during count operation, values are written to the reload register and counter (refer to 18.3.2 Timer Write Control during Count Operation). Selectable functions • Measurement period selection The measurement period of the input pulse is selected by the TEDGSEL in the TRAIOC register.
• Measured pulse input pin select function Use of the TRAIO pin is selected by bits TRAIOSEL0 in the TRASR register.
• Digital filter function Whether enabling or disabling the digital filter and the sampling frequency is selected by bits TIPF0 and TIPF1 in the TRAIOC register.

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 254 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.7.1 Timer RA I/O Control Register (T RAIOC) in Pulse Period Measurement

Note: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. Address 0101h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol TIOGT1 TIOGT0 TIPF1 TIPF0 TIOSEL TOENA TOPCR TEDGSEL A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TEDGSEL TRAIO polarity switch bit 0: Period from one rising edge to next rising edge of measured pulse is measured 1: Period from one falling edge to next falling edge of measured pulse is measured R/W b1 TOPCR TRAIO output control bit Set to 0 in pulse period measurement mode. R/W b2 TOENA TRAO output enable bit R/W b3 TIOSEL Hardware LIN function select bit Set to 0. R/W b4 TIPF0 TRAIO input filter select bit (1) b5 b4 0 0: No filter 0 1: Filter with f1 sampling 1 0: Filter with f8 sampling 1 1: Filter with f32 sampling R/W b5 TIPF1 R/W b6 TIOGT0 TRAIO event input control bit Set to 0 in pulse period measurement mode. R/W b7 TIOGT1 R/W

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 255 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.7.2 Operating Example

Figure 18.4 Operating Example in Pulse Period Measurement Mode Underflow signal of timer RA prescaler Notes: 1. The content of the read-out buffer can be read by reading the TRA register in pulse period measurement mode. 2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge received) when the timer RA prescaler underflows for the second time. 3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge received). The contents of the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge is input, the measured result of the previous period is retained. 4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the TUNDF bit in the TRACR register. 5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit. 6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously. 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh 01h 00h 0Fh 0Eh0Fh 0Dh0Fh 0Bh 0Ah 0Dh 01h 00h 0Fh 0Eh09h TSTART bit in TRACR register TEDGF bit in TRACR register Measured pulse (TRAIO pin input) Contents of TRA Contents of read-out buffer (1) IR bit in TRAIC register TUNDF bit in TRACR register Set to 1 by a program. Count starts TRA reload TRA read (3) Retained Set to 0 by a program. The above applies when the period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with the initial value of the TRA register as 0Fh. 0Eh TRA reload Retained Set to 0 when an interrupt request is acknowledged or by a program. Set to 0 by a program. Underflow (Note 2) (Note 2) (Note 4) (Note 6) (Note 5)

1. Timer RA REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 256 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

18.8 Notes on Timer RA

• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these regist ers are read 1 byte at a time in the MCU. Consequently, the timer value may be updated during the period when these two registers are being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits re main unchanged if 1 is written. When using the READ- MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit remains 0 (count stops) for zero or one cycle of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access regi sters associated with timer RA (1) other than the TCSTF bit. Timer RA starts counting at the first active edge of the count source after The TCSTF bit is set to 1 (during count operation). The TCSTF bit remains 1 for zero or one cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA (1) other than the TCSTF bit. Note: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval.

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 257 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 19. Timer RB Timer RB is an 8-bit timer with an 8-bit prescaler.

19.1 Introduction

The prescaler and timer each consist of a reload register a nd counter (refer to Tables 19.2 to 19.5 for the Specifications of Each Mode) for accessing the reload regi ster and counter. Timer RB has timer RB primary and timer RB secondary as reload registers. The count source for timer RB is the opera ting clock that regulates the timing of timer operations such as counting and reloading. Figure 19.1 shows the Timer RB Block Diagram. Table 19.1 lists the Timer RB Pin Configuration. Timer RB supports the four operating modes:

• Timer mode: The timer counts an internal count source (peripheral function clock or timer RA underflows).
• Programmable waveform generation mode: The timer outputs pulses of a given width successively.
• Programmable one-shot generation mode: The timer outputs a one-shot pulse.
• Programmable wait one-shot generation mode: The timer outputs a delayed one-shot pulse. Figure 19.1 Timer RB Block Diagram Table 19.1 Timer RB Pin Configuration Pin Name Assigned Pin I/O Function TRBO P11_6 Output Pulse output (programmable waveform generation mode, programmable one-shot generation mode, programmable wait one-shot generation mode) INT0PL bit = 00b = 01b = 11b = 10bTimer RA underflow Bits TCK1 to TCK0 TSTART bit TRBPRE register (prescaler) Timer RB interrupt INT0 interrupt TCSTF bit Toggle flip-flop Q Q CLR CK TOPL = 1 TOPL = 0P11_6 bit in P11 register f2 Bits TMOD1 to TMOD0 = 10b or 11b TOSSTF bit Polarity selection INOSEG bit One edge/both edges input polarity switchingDigital filterINT0 pin INT0EN bit Bits TMOD1 to TMOD0 = 01b, 10b, 11b Counter Reload register Counter (timer RB) Reload register TRBPR register Data bus TRBSC register Reload register TCKCUT bit INOSTG bit TSTART, TCSTF: Bits in TRBCR register TOSSTF: Bit in TRBOCR register TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register TMOD0, TMOD1, TCK0, TCK1, TCKCUT: Bits in TRBMR register (timer) TOCNT = 0 TOCNT = 1 Bits TMOD1 to TMOD0 = 01b, 10b, 11b TRBO pin

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 258 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.2 Registers

19.2.1 Timer RB Cont rol Register (TRBCR)

Notes: 1. Refer to 19.7 Notes on Timer RB for precautions regarding bits TSTART, TCSTF and TSTOP. 2. When 1 is written to the TSTOP bit, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit in the TRBOCR register are set to values after a reset. 3. Indicates that count operation is in progress in timer mode or programmable waveform mode. In programmable one-shot generation mode or programmable wait one-shot generation mode, it indicates that a one-shot pulse trigger has been acknowledged.

19.2.2 Timer RB One-Shot Control Register (TRBOCR)

Note: 1. When 1 is written to the TSTOP bit in the TRBCR register, the TOSSTF bit is set to 0. The TRBOCR register is enabled when bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot generation mode) or 11b (programmable wait one-shot generation mode). Address 0108h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — — TSTOP TCSTF TSTART A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TSTART Timer RB count start bit (1) 0: Count stops 1: Count starts R/W b1 TCSTF Timer RB count status flag (1) 0: Count stops 1: During count operation (3) R b2 TSTOP Timer RB count forcible stop bit (1, 2) When this bit is set to 1, the count is forcibly stopped. When read, the content is 0. R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 — b6 — b7 — Address 0109h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — — TOSSTF TOSSP TOSST A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOSST Timer RB one-shot start bit When this bit is set to 1, one-shot trigger generated. When read, the content is 0. R/W b1 TOSSP Timer RB one-shot stop bit When this bit is set to 1, counting of one-shot pulses (including programmable wait one-shot pulses) stops. When read, the content is 0. R/W b2 TOSSTF Timer RB one-shot status flag (1) 0: One-shot stopped 1: One-shot operating (including wait period) R b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 — b6 — b7 —

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 259 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.2.3 Timer RB I/O Cont rol Register (TRBIOC)

19.2.4 Timer RB Mode Register (TRBMR)

Notes: 1. Change bits TMOD0 and TMOD1, TCK0 and TCK1, and TCKCUT when both the TSTART and TCSTF bits in the TRBCR register set to 0 (count stops). 2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable waveform generation mode, programmable one-shot generation mode, or programmable wait one-shot generation mode, the TWRC bit must be set to 1 (write to reload register only). Address 010Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l ———— I N O S E G I N O S T G T O C N T T O P L A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOPL Timer RB output level select bit Function varies according to the operating mode. R/W b1 TOCNT Timer RB output switch bit R/W b2 INOSTG One-shot trigger control bit R/W b3 INOSEG One-shot trigger polarity select bit R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 — Address 010Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TCKCUT — TCK1 TCK0 TWRC — TMOD1 TMOD0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TMOD0 Timer RB operating mode select bit (1) b1 b0 0 0: Timer mode 0 1: Programmable waveform generation mode 1 0: Programmable one-shot generation mode 1 1: Programmable wait one-shot generation mode R/W b1 TMOD1 R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b3 TWRC Timer RB write control bit (2) 0: Write to reload register and counter 1: Write to reload register only R/W b4 TCK0 Timer RB count source select bit (1) b5 b4 0 0: f1 0 1: f8 1 0: Timer RA underflow 1 1: f2 R/W b5 TCK1 R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 TCKCUT Timer RB count source cutoff bit (1) 0: Count source provided 1: Count source cut off R/W

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 260 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.2.5 Timer RB Prescal er Register (TRBPRE)

When 1 is written to the TSTOP bit in the TRBCR register, the TRBPRE register is set to FFh.

19.2.6 Timer RB Seconda ry Register (TRBSC)

Notes: 1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted. 2. The count value can be read by reading the TRBPR register even when the secondary period is being counted. When 1 is written to the TSTOP bit in the TRBCR register, the TRBSC register is set to FFh. To write to the TRBSC register, perform the following steps. (1) Write the value into the TRBSC register. (2) Write the value into the TRBPR register. (If the valu e does not change, write the same value second time.) Address 010Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit Mode Function Setting Range R/W b7 to b0 Timer mode Counts an internal count source or timer RA underflows. 00h to FFh R/W Programmable waveform generation mode 00h to FFh R/W Programmable one-shot generation mode 00h to FFh R/W Programmable wait one-shot generation mode 00h to FFh R/W Address 010Dh B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit Mode Function Setting Range R/W b7 to b0 Timer mode Disabled 00h to FFh — Programmable waveform generation mode Counts timer RB prescaler underflows (1) 00h to FFh W (2) Programmable one-shot generation mode Disabled 00h to FFh — Programmable wait one-shot generation mode Counts timer RB prescaler underflows (one-shot width is counted) 00h to FFh W (2)

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 261 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.2.7 Timer RB Primar y Register (TRBPR)

Note: 1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted. When 1 is written to the TSTOP bit in the TRBCR register, the TRBPR register is set to FFh.

19.2.8 Timer RB/RC Pin Se lect Register (TRBRCSR)

The register function for timer RB is not implemented. To use the I/O pins for timer RC, set the TRBRCSR register. Set this register before setting the timer RC associated registers. Also, do not change the setting value of the TRCCLKSEL0 bit during timer RC operation. Address 010Eh B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit Mode Function Setting Range R/W b7 to b0 Timer mode Counts timer RB prescaler underflows. 00h to FFh R/W Programmable waveform generation mode Counts timer RB prescaler underflows. (1) 00h to FFh R/W Programmable one-shot generation mode Counts timer RB prescaler underflows (one-shot width is counted) 00h to FFh R/W Programmable wait one-shot generation mode Counts timer RB prescaler underflows (wait period width is counted) 00h to FFh R/W Address 0181h B i t b 7 b 6b 5b 4b 3 b 2 b 1 b 0 Symbol TRCTRGSEL1 TRCTRGSEL0 — TRCCLKSEL0 — — — — A f t e r R e s e t 0 0 0 0 0000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 — b4 TRCCLKSEL0 TRCCLK pin select bit 0: TRCCLK pin not used 1: TRCCLK pin used R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 TRCTRGSEL0 TRCTRG pin select bit b7 b6 0 0: TRCTRG pin not used 0 1: P3_7 assigned 1 0: P4_3 assigned 1 1: P4_4 assigned R/W b7 TRCTRGSEL1 R/W

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 262 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.3 Timer Mode

In timer mode, a internally generated count sour ce or timer RA underflows are counted (refer to Table 19.2 ). Registers TRBOCR and TRBSC are not used in this mode.

19.3.1 Timer RB I/O Control Regi ster (TRBIOC) in Timer Mode

Table 19.2 Timer M ode Specifications Item Specification Count sources f1, f2, f8, timer RA underflow Count operations • Decrement

• When the timer underflows, it reloads the reload register content before the count continues (when timer RB underflows, the content of timer RB primary reload register is reloaded). Division ratio 1/(n+1)(m+1) n: Value set in TRBPRE register, m: Value set in TRBPR register Count start condition 1 (count starts) is written to the TSTART bit in the TRBCR register. Count stop conditions • 0 (count stops) is wri tten to the TSTART bit in the TRBCR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register. Interrupt request generation timing When timer RB underflows [timer RB interrupt]. TRBO pin function Programmable I/O port INT0 pin function Programmable I/O port or INT0 interrupt input Read from timer The count value can be read out by reading registers TRBPR and TRBPRE. Write to timer • When registers TRBPRE and TR BPR are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written during count operation: If the TWRC bit in the TRBMR register is set to 0, the value is written to both the reload register and the counter. If the TWRC bit is set to 1, the value is written to the reload register only. (Refer to 19.3.2 Timer Write Control during Count Operation.) Address 010Ah B i t b 7b 6b 5b 4b 3b 2b 1 b 0 S y m b o l ———— I N O S E G I N O S T G T O C N T T O P L A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TOPL Timer RB output level select bit Set to 0 in timer mode. R/W b1 TOCNT Timer RB output switch bit R/W b2 INOSTG One-shot trigger control bit R/W b3 INOSEG One-shot trigger polarity select bit R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 —

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 263 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.3.2 Timer Write Contro l during Count Operation

Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a co unter. In timer mode, the TWRC bit in the TRBMR register can be used to select whether writing to the prescaler or timer during count operation is performed to both the reload register and counter or only to the reload register. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload register and counter, the counter value is not updated immediately after the WRITE instruction is executed. If the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be shifted when the prescaler value changes. Figure 19.2 shows an Operating Example of Timer RB when Counter Value is Rewritten during Count Operation.

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 264 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 19.2 Operating Example of Timer RB when Counter Value is Rewritten during Count Operation Count source Reloads register of timer RB prescaler IR bit in TRBIC register 0 Counter of timer RB prescaler Reloads register of timer RB Counter of timer RB Write 01h into the TRBPRE register and 25h into the TRBPR register by a program. After writing, the reload register is written with the first count source. Reload with the second count source Reload at underflow After writing, the reload register is written at the first underflow. Reload at the second underflow The IR bit remains unchanged until underflow is generated by a new value. When the TWRC bit is set to 0 (write to reload register and counter) Count source Reloads register of timer RB prescaler IR bit in TRBIC register Counter of timer RB prescaler Reloads register of timer RB Counter of timer RB Write 01h into the TRBPRE register and 25h into the TRBPR register by a program. After writing, the reload register is written with the first count source. Reload at underflow After writing, the reload register is written at the first underflow. Reload at underflow Only the prescaler values are updated, extending the duration until timer RB underflows. When the TWRC bit is set to 1 (write to reload register only) 05h 04h 03h 02h 01h 00h 01h 00h 01h 00h06h 01h 00h 01h 03h 00h 02h 01h 25h New value (25h)Previous value New value (01h)Previous value New value (01h)Previous value 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h New value (25h)Previous value 03h 24h 02h 25h The above applies under the following condition: Both the TSTART and TCSTF bits in the TRBCR register are set to 1 (during count operation).

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 265 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.4 Programmable Waveform Generation Mode

In programmable waveform ge neration mode, the signal output from th e TRBO pin is inverted each time the counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table 19.3). Counting starts by counting the setting value of the TRBPR register. The TRBOCR register is unused in this mode. Figure 19.3 shows an Operating Example in Timer RB in Programmable Waveform Generation Mode. Notes: 1. Even when the secondary period is being counted, the TRBPR register may be read. 2. The set values are reflected in the waveform output beginning with the following primary period after writing to the TRBPR register. Table 19.3 Programmable Waveform Generation Mode Specifications Item Specification Count sources f1, f2, f8, timer RA underflow Count operations • Decrement

• When the timer underflows, it reloads the contents of the primary reload and secondary reload registers alternately before the count continues. Width and period of output waveform Primary period: (n+1)(m+1)/fi Secondary period: (n+1)(p+1)/fi Period: (n+1){(m+1)+(p+1)}/fi fi: Frequency of count source n: Value set in TRBPRE register m: Value set in TRBPR register p: Value set in TRBSC register Count start condition 1 (count starts) is written to the TSTART bit in the TRBCR register. Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register. Interrupt request generation timing In half a cycle of the count source, after timer RB underflows during the secondary period (at the same time as the TRBO output change) [timer RB interrupt] TRBO pin function Programmable output port or pulse output INT0 pin function Programmable I/O port or INT0 interrupt input Read from timer The count value can be read out by reading registers TRBPR and TRBPRE (1). Write to timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count operation, values are written to the reload registers only. (2) Selectable function • Output level select function The output level during primary and secondary periods is selected by the TOPL bit in the TRBIOC register.

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 266 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.4.1 Timer RB I/O Contro l Register (TRBIOC) in Programmable Waveform

B i t b 7b 6b 5b 4b 3b 2b 1 b 0 S y m b o l ———— I N O S E G I N O S T G T O C N T T O P L A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TOPL Timer RB output level select bit 0: High-level output for the primary period, low-level output for the secondary period Low-level output when the timer is stopped 1: Low-level output for the primary period, high-level output for the secondary period High-level output when the timer is stopped R/W b1 TOCNT Timer RB output switch bit 0: Timer RB waveform is output 1: P11_6 port latch value is output R/W b2 INOSTG One-shot trigger control bit Set to 0 in programmable waveform generation mode. R/W b3 INOSEG One-shot trigger polarity select bit R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 —

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 267 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.4.2 Operating Example

Figure 19.3 Operating Example in Timer RB in Programmable Waveform Generation Mode IR bit in TRBIC register Count source Underflow signal of Timer RB prescaler Counter of timer RB TRBO pin output TOPL bit in TRBIO register Set to 1 by a program. Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the following conditions: TSTART bit in TRBCR register 01h 00h 02h Timer RB secondary reload Timer RB primary reload Set to 0 by a program. TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h TOCNT in TRBIOC register = 0 (timer RB waveform output from the TRBO pin) 02h 01h 00h 01h 00h Primary period Primary period Secondary period Waveform output starts Waveform output inverted Waveform output starts The initial output is the same level as during the secondary period.

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 268 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.5 Programmable One-shot Generation Mode

In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 19.4). When a trigger is generated, the timer starts operating from the point only once for a given period eq ual to the set value in the TRBPR register. The TRBSC register is not used in this mode. Figure 19.4 shows an Operating Example in Programmable One-Shot Generation Mode. Note: 1. The set value is reflected at the following one- shot pulse after writing to the TRBPR register. Table 19.4 Programmable One-Shot Generation Mode Specifications Item Specification Count sources f1, f2, f8, timer RA underflow Count operations • The setting value of the TRBPR register is decremented.

• When the timer underflows, it reloads the contents of the reload register before the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the content of the reload register before it stops. One-shot pulse output time (n+1)(m+1)/fi fi: Frequency of count source n: Value set in TRBPRE register, m: Value set in TRBPR register Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated.
• 1 (one-shot starts) is written to the TOSST bit in the TRBOCR register.
• Trigger input to the INT0 pin Count stop conditions • When reloading completes after timer RB underflows during the primary period
• 1 (one-shot stops) is written to the TOSSP bit in the TRBOCR register.
• 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register. Interrupt request generation timing In half a cycle of the count source, after the timer underflows (at the same time as the waveform output from the TRBO pin ends) [timer RB interrupt] TRBP pin function Pulse output INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled): external trigger (INT0 interrupt input) Read from timer The count value can be re ad out by reading registers TRBPR and TRBPRE. Write to timer • When registers TRBPRE and TR BPR are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written during count operation, values are written to the reload register only (1). Selectable functions • Outp ut level select function The output level of the one-shot pulse waveform is selected by the TOPL bit in the TRBIOC register.
• One-shot trigger select function Refer to 19.5.3 One-Shot Trigger Selection.

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 269 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.5.1 Timer RB I/O Contro l Register (TRBIOC) in Programmable One-Shot

Note: 1. Refer to 19.5.3 One-Shot Trigger Selection. Address 010Ah B i t b 7b 6b 5b 4b 3b 2b 1 b 0 S y m b o l ———— I N O S E G I N O S T G T O C N T T O P L A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TOPL Timer RB output level select bit 0: High-level output of a one-shot pulse, low-level output when the timer is stopped 1: Low-level output of a one-shot pulse, high-level output when the timer is stopped R/W b1 TOCNT Timer RB output switch bit Set to 0 in programmable one-shot generation mode. R/W b2 INOSTG One-shot trigger control bit (1) 0: INT0 pin one-shot trigger disabled 1: INT0 pin one-shot trigger enabled R/W b3 INOSEG One-shot trigger polarity select bit (1) 0: Falling edge trigger 1: Rising edge trigger R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 —

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 270 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.5.2 Operating Example

Figure 19.4 Operating Example in Programmable One-Shot Generation Mode TOSSTF bit in TRBOCR register INT0 pin input IR bit in TRBIC register Count source Underflow signal of timer RB prescaler Counter of timer RB TRBIO pin output TOPL bit in TRBIOC register Set to 1 by a program. Set to 1 by a program. Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the following conditions: TSTART bit in TRBCR register 01h 00h 01h 00h 01h Count starts Timer RB primary reload Count starts Timer RB primary reload Set to 0 by a program. Waveform output starts Waveform output ends Waveform output starts Waveform output ends Set to 0 when count ends. Set to 1 by INT0 pin input trigger TRBPRE = 01h, TRBPR = 01h TOPL in TRBIOC register = 0, TOCNT = 0 INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at the rising edge)

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 271 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.5.3 One-Shot Trigger Selection

In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts). A one-shot trigger can be generated by either of the following causes:

• 1 is written to the TOSST bit in the TRBOCR register by a program.
• Trigger input from the INT0 pin. When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation mode, count operation starts for the wait period.) If a one- shot trigger occurs while the TOSSTF bit is set to 1, no retriggering occurs. To use trigger input from the INT0 pin, input the trigger after making the following settings:
• Set the PD4_5 bit in the PD4 register to 0 (input port).
• Select the INT0 digital filter with bits INT0F0 and INT0F1 in the INTF register.
• Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is select ed, further select falling or rising edge with the INOSEG bit in TRBIOC register.
• Set the INT0EN bit in the INTEN register to 0 (enabled).
• After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger enabled). Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.
• Processing to handle the interrupts is required. Refer to 12. Interrupts, for details.
• If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The INOSEG bit in the TRBIOC register does not affect INT0 interrupts).
• If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the value of the IR bit in the INT0IC register changes.

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 272 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.6 Programmable Wait One-Shot Generation Mode

In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 19.5). When a trigger is generated from that point, the timer outputs a pulse only once for a given length of time equal to the setting value of the TRBSC register after waiting for a given length of time equal to the setting value of the TRBPR register. Figure 19.5 shows an Operating Example in Programmable Wait One-Shot Generation Mode. Note: 1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR. Table 19.5 Programmable Wait One-Shot Generation Mode Specifications Item Specification Count sources f1, f2, f8, timer RA underflow Count operations • The setting value of the timer RB primary is decremented.

• When a count of the timer RB primary underflows, the timer reloads the contents of timer RB secondary before the count continues.
• When a count of the timer RB secondary underflows, the timer reloads the contents of timer RB primary before the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the content of the reload register before it stops. Wait time (n+1)(m+1)/fi fi: Frequency of count source n: Value set in TRBPRE register, m: Value set in TRBPR register One-shot pulse output time (n+1)(p+1)/fi fi: Frequency of count source n: Value set in TRBPRE register, p: Value set in TRBSC register Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated.
• 1 (one-shot starts) is written to the TOSST bit in the TRBOCR register.
• Trigger input to the INT0 pin Count stop conditions • When reloading completes after timer RB underflows during the secondary period.
• 1 (one-shot stops) is written to the TOSSP bit in the TRBOCR register.
• 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register. Interrupt request generation timing In half a cycle of the count source after timer RB underflows during secondary period (at the same time as the waveform output from the TRBO pin ends) [timer RB interrupt]. TRBO pin function Pulse output INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled): external trigger (INT0 interrupt input) Read from timer The count value can be read out by reading registers TRBPR and TRBPRE. Write to timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written during count operation, values are written to the reload registers only. (1) Selectable functions • Output level select function The output level of the one-shot pulse waveform is selected by the TOPL bit in the TRBIOC register.
• One-shot trigger select function Refer to 19.5.3 One-Shot Trigger Selection.

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 273 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.6.1 Timer RB I/O Control Register (T RBIOC) in Programmable Wait One-Shot

Note: 1. Refer to 19.5.3 One-Shot Trigger Selection. Address 010Ah B i t b 7b 6b 5b 4b 3b 2b 1 b 0 S y m b o l ———— I N O S E G I N O S T G T O C N T T O P L A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 TOPL Timer RB output level select bit 0: High-level output of a one-shot pulse, low-level output when the timer stops or during wait 1: Low-level output of a one-shot pulse, low-level output when the timer stops or during wait R/W b1 TOCNT Timer RB output switch bit Set to 0 in programmable wait one-shot generation mode. R/W b2 INOSTG One-shot trigger control bit (1) 0: INT0 pin one-shot trigger disabled 1: INT0 pin one-shot trigger enabled R/W b3 INOSEG One-shot trigger polarity select bit (1) 0: Falling edge trigger 1: Rising edge trigger R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 —

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 274 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.6.2 Operating Example

Figure 19.5 Operating Example in Programmable Wait One-Shot Generation Mode TOSSTF bit in TRBOCR register INT0 pin input IR bit in TRBIC register Count source Underflow signal of Timer RB prescaler Counter of timer RB TRBIO pin output TOPL bit in TRBIOC register Set to 1 by a program. Set to 1 by setting 1 to the TOSST bit in the TRBOCR register, or INT0 pin input trigger. Set to 0 when an interrupt request is acknowledged or by an program. The above applies under the following conditions: TSTART bit in TRBCR register 01h 00h 00h 01h Count starts Timer RB secondary reload Timer RB primary reload Set to 0 by a program. Wait starts Waveform output starts Waveform output ends Set to 0 when count ends. TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at the rising edge) 04h 03h 02h 01h Wait (primary period) One-shot pulse (secondary period)

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 275 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.7 Notes on Timer RB

• Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time in the MCU. Consequently, the timer value may be updated during the period when these two registers are being read.
• In programmable one-shot generation mode and programma ble wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0 (count stops) or setting the TOSSP bit in the TRBOCR register to 1 (one- shot stops), the timer reloads the value of reload re gister and stops. Therefore, in programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer count value before the timer stops.
• The TCSTF bit remains 0 (count stops) for one or two cy cles of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RB (1) other than the TCSTF bit. Timer RB starts counting at the first active edge of the count source after the TCSTF bit is set to 1 (during count operation). The TCSTF bit remains 1 for one or two cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB (1) other than the TCSTF bit. Note: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and TRBPR
• When the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• When 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes after one or two cycles of the count source have elapse d. When 1 is written to the TOSSP bit during the period between when 1 is written to the TOSST bit and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewi se, when 1 is written to the TOSST bit during the period between when 1 is written to the TOSSP bit and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1.

19.7.1 Timer Mode

To write to registers TRBPRE and TRBPR during count op eration (TCSTF bit in the TRBCR register is set to 1), note the following:

• When the TRBPRE register is writte n continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval.

19.7.2 Programmable Waveform Generation Mode

To write to registers TRBPRE and TRBPR during count op eration (TCSTF bit in the TRBCR register is set to 1), note the following:

• When the TRBPRE register is writte n continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval.

1. Timer RB REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 276 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

19.7.3 Programmable One-Shot Generation Mode

To write to registers TRBPRE and TRBPR during count op eration (TCSTF bit in the TRBCR register is set to 1), note the following:

• When the TRBPRE register is written continuously during count operation, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation, allow thr ee or more cycles of the prescaler underflow for each write interval.

19.7.4 Programmable Wait One-shot Generation Mode

To write to registers TRBPRE and TRBPR during count op eration (TCSTF bit in the TRBCR register is set to 1), note the following:

• When the TRBPRE register is writte n continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval.

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 277 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 20. Timer RC Timer RC is a 16-bit timer with four I/O pins.

20.1 Introduction

Timer RC uses either f1 or fOCO40M as its operating clock. Table 20.1 lists the Timer RC Operating Clocks. Table 20.2 lists the Timer RC Pin Configuration. Figure 20.1 shows the Timer RC Block Diagram. Timer RC supports the following three modes:

• Timer mode - Input capture function The counter value is captured to a register, using an external signal as the trigger. - Output compare function A match between the valu es of a counter and a register is detected. (Pin output can be changed at detection.) The following two modes use the output compare function:
• PWM mode Pulses of a given width are output continuously.
• PWM2 mode A one-shot waveform or PWM waveform is output following the trigger after the wait time has elapsed. For the input capture function, the output compare f unction, and in PWM mode, settings may be selected independently for each pin. In PWM2 mode, waveforms are output based on a combination of the counter or the register. Table 20.1 Timer RC Operating Clocks Condition Timer RC Operating Clock The count source is f1, f2, f4, f8, f32, or TRCCLK input. (Bits TCK2 to TCK0 in the TRCCR1 register are set to 000b to 101b.) The count source is fOCO40M. (Bits TCK2 to TCK0 in the TRCCR1 register are set to 110b.) fOCO40M

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 278 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 20.1 Timer RC Block Diagram Table 20.2 Timer RC Pin Configuration Pin Name Assigned Pin I/O Function TRCIOA P4_4 I/O Function differs according to the mode. Refer to descriptions of individual modes for details. TRCIOB P4_5, P4_6, or P4_7 TRCIOC P4_6 TRCIOD P4_7 TRCCLK P4_3 Input External clock input TRCTRG P3_7, P4_3, or P4_4 Input PWM2 mode external trigger input TRCMR register Data bus TRCCR1 register TRCIER register TRCSR register TRCIOR0 register TRC register TRCGRA register TRCGRB register TRCGRC register TRCGRD register TRCCR2 register TRCDF register TRCOER register Timer RC control circuit INT0 TRCCLKCount source select circuit f1, f2, f4, f8, f32, fOCO40M Timer RC interrupt request TRCIOR1 register TRCIOB TRCIOC TRCIOD TRCIOA/TRCTRG TRCADCR register

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 279 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.2 Registers

Table 20.3 lists the Registers Associated with Timer RC. −: Invalid Table 20.3 Registers Associated with Timer RC Address Symbol Mode Related Information Timer PWM PWM2Input Capture Function Output Compare Function 0008h MSTCR Valid Valid Valid Valid 20.2.1 Module Standby Control Register (MSTCR) 0120h TRCMR Valid Valid Valid Valid 20.2.2 Timer RC Mode Register (TRCMR) 0121h TRCCR1 Valid Valid Valid Valid Timer RC control register 1

20.2.3 Timer RC Control Register 1 (TRCCR1)

20.5.1 Timer RC Control Register 1 (TRCCR1) in

Timer Mode (Output Compare Function)

20.6.1 Timer RC Control Register 1 (TRCCR1) in

20.7.1 Timer RC Control Register 1 (TRCCR1) in

0122h TRCIER Valid Valid Valid Valid 20.2.4 Timer RC Interrupt Enable Register (TRCIER) 0123h TRCSR Valid Valid Valid Valid 20.2.5 Timer RC Status Register (TRCSR) 0124h TRCIOR0 Valid Valid −− Timer RC I/O control register 0, timer RC I/O control register 1

20.2.6 Timer RC I/O Control Register 0 (TRCIOR0)

20.2.7 Timer RC I/O Control Register 1 (TRCIOR1)

20.4.1 Timer RC I/O Control Register 0 (TRCIOR0)

in Timer Mode (Input Capture Function)

20.4.2 Timer RC I/O Control Register 1 (TRCIOR1)

in Timer Mode (Input Capture Function)

20.5.2 Timer RC I/O Control Register 0 (TRCIOR0)

in Timer Mode (Output Compare Function)

20.5.3 Timer RC I/O Control Register 1 (TRCIOR1)

in Timer Mode (Output Compare Function) 0125h TRCIOR1 0126h 0127h TRC Valid Valid Valid Valid 20.2.8 Timer RC Counter (TRC) 0128h 0129h TRCGRA Valid Valid Valid Valid 20.2.9 Timer RC General Registers A, B, C, and D (TRCGRA, TRCGRB, TRCGRC, TRCGRD) 012Ah 012Bh TRCGRB 012Ch 012Dh TRCGRC 012Eh 012Fh TRCGRD 0130h TRCCR2 −− − Valid 20.2.10 Timer RC Control Register 2 (TRCCR2) 0131h TRCDF Valid −− Valid 20.2.11 Timer RC Digital Filter Function Select Register (TRCDF) 0132h TRCOER − Valid Valid Valid 20.2.12 Timer RC Output Master Enable Register (TRCOER) 0133h TRCADCR − Valid Valid Valid 20.2.13 Timer RC Trigger Control Register (TRCADCR) 0181h TRBRCSR Valid Valid Valid Valid 20.2.14 Timer RB/RC Pin Select Register (TRBRCSR) 0182h TRCPSR0 Valid Valid Valid Valid 20.2.15 Timer RC Pin Select Register 0 (TRCPSR0) 0183h TRCPSR1 Valid Valid Valid Valid 20.2.16 Timer RC Pin Select Register 1 (TRCPSR1)

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 280 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.2.1 Module Standby Control Register (MSTCR)

Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any acce ss to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. Address 0008h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — MSTTRG MSTTRC MSTTRD MSTIIC — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 MSTIIC SSU, I 2C bus standby bit 0: Active 1: Standby (1) R/W b4 MSTTRD Timer RD standby bit 0: Active 1: Standby (2) R/W b5 MSTTRC Timer RC standby bit 0: Active 1: Standby (3) R/W b6 MSTTRG Timer RG standby bit 0: Active 1: Standby (4) R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 281 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.2.2 Timer RC Mode Register (TRCMR)

Notes: 1. These bits are enabled when the PWM2 bit is set to 1 (timer mode or PWM mode). 2. Set the BFC bit to 0 (general register) in PWM2 mode. For notes on the TRCMR register in PWM2 mode, refer to 20.9.6 TRCMR Register in PWM2 Mode. Address 0120h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TSTART — BFD BFC PWM2 PWMD PWMC PWMB A f t e r R e s e t 01001000 Bit Symbol Bit Name Function R/W b0 PWMB PWM mode of TRCIOB select bit (1) 0: Timer mode 1: PWM mode R/W b1 PWMC PWM mode of TRCIOC select bit (1) 0: Timer mode 1: PWM mode R/W b2 PWMD PWM mode of TRCIOD select bit (1) 0: Timer mode 1: PWM mode R/W b3 PWM2 PWM2 mode select bit 0: PWM 2 mode 1: Timer mode or PWM mode R/W b4 BFC TRCGRC register function select bit (2) 0: General register 1: Buffer register of TRCGRA register R/W b5 BFD TRCGRD register function select bit 0: General register 1: Buffer register of TRCGRB register R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b7 TSTART TRC count start bit 0: Count stops 1: Count starts R/W

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 282 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.2.3 Timer RC Contro l Register 1 (TRCCR1)

Note: 1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops). 2. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.

20.2.4 Timer RC Interrupt Enable Register (TRCIER)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR TCK2 TCK1 TCK0 TOD TOC TOB TOA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOA TRCIOA output level select bit (1) Function varies according to the operating mode (function). R/W b1 TOB TRCIOB output level select bit (1) R/W b2 TOC TRCIOC output level select bit (1) R/W b3 TOD TRCIOD output level select bit (1) R/W b4 TCK0 Count source select bit (1) b6 b5 b4 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRCCLK input rising edge 1 1 0: fOCO40M 1 1 1: fOCO-F (2) R/W b5 TCK1 R/W b6 TCK2 R/W b7 CCLR TRC counter clear select bit 0: Clear disabled (free-running operation) 1: TRC counter cleared by input capture or by compare match with the TRCGRA register R/W Address 0122h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol OVIE — — — IMIED IMIEC IMIEB IMIEA A f t e r R e s e t 01110000 Bit Symbol Bit Name Function R/W b0 IMIEA Input-capture/compare-match interrupt enable bit A 0: Interrupt (IMIA) by IMFA bit disabled 1: Interrupt (IMIA) by IMFA bit enabled R/W b1 IMIEB Input-capture/compare-match interrupt enable bit B 0: Interrupt (IMIB) by IMFB bit disabled 1: Interrupt (IMIB) by IMFB bit enabled R/W b2 IMIEC Input-capture/compare-match interrupt enable bit C 0: Interrupt (IMIC) by IMFC bit disabled 1: Interrupt (IMIC) by IMFC bit enabled R/W b3 IMIED Input-capture/compare-match interrupt enable bit D 0: Interrupt (IMID) by IMFD bit disabled 1: Interrupt (IMID) by IMFD bit enabled R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — b6 — b7 OVIE Overflow interrupt enable bit 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled R/W

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 283 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.2.5 Timer RC Status Register (TRCSR)

Note: 1. The results of writing to these bits are as follows:

• The bit is set to 0 when it is first read as 1 and then 0 is written to it.
• The bit remains unchanged even if it is first read as 0 and then 0 is written to it. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it.)
• The bit’s value remains unchanged if 1 is written to it. Notes: 1. Edge selected by bits IOj0 and IOj1 (j = A, B, C, or D) in registers TRCIOR0 and TRCIOR1. 2. Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA and TRCGRB). Address 0123h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol OVF — — — IMFD IMFC IMFB IMFA A f t e r R e s e t 01110000 Bit Symbol Bit Name Function R/W b0 IMFA Input-capture/compare-match flag A [Condition for setting to 0] Write 0 after reading. (1) [Condition for setting to 1] Refer to Table 20.4 Conditions for Setting Bit of Each Flag to 1. R/W b1 IMFB Input-capture/compare-match flag B R/W b2 IMFC Input-capture/compare-match flag C R/W b3 IMFD Input-capture/compare-match flag D R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — b6 — b7 OVF Overflow flag [Condition for setting to 0] Write 0 after reading. (1) [Condition for setting to 1] Refer to Table 20.4 Conditions for Setting Bit of Each Flag to 1. R/W Table 20.4 Conditions for Setting Bit of Each Flag to 1 Bit Symbol Timer Mode PWM Mode PWM2 ModeInput capture Function Output Compare Function IMFA TRCIOA pin input edge (1) When the values of registers TRC and TRCGRA match. IMFB TRCIOB pin input edge (1) When the values of registers TRC and TRCGRB match. IMFC TRCIOC pin input edge (1) When the values of registers TRC and TRCGRC match. (2) IMFD TRCIOD pin input edge (1) When the values of registers TRC and TRCGRD match. (2) OVF When the TRC register overflows.

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 284 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.2.6 Timer RC I/O Cont rol Register 0 (TRCIOR0)

Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffe r register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffe r register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. The TRCIOR0 register is enabled in timer mode. It is disabled in PWM mode and PWM2 mode.

20.2.7 Timer RC I/O Cont rol Register 1 (TRCIOR1)

Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffe r register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffe r register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. The TRCIOR1 register is enabled in timer mode. It is disabled in PWM mode and PWM2 mode. Address 0124h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOA0 TRCGRA control bit Function varies according to the operating mode (function). R/W b1 IOA1 R/W b2 IOA2 TRCGRA mode select bit (1) 0: Output compare function 1: Input capture function R/W b3 — Reserved bit Set to 1. R/W b4 IOB0 TRCGRB control bit Function varies according to the operating mode (function). R/W b5 IOB1 R/W b6 IOB2 TRCGRB mode select bit (2) 0: Output compare function 1: Input capture function R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — Address 0125h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOC0 TRCGRC control bit Function varies according to the operating mode (function). R/W b1 IOC1 R/W b2 IOC2 TRCGRC mode select bit (1) 0: Output compare function 1: Input capture function R/W b3 IOC3 TRCGRC register function select bit 0: TRCIOA output register 1: General register or buffer register R/W b4 IOD0 TRCGRD control bit Function varies according to the operating mode (function). R/W b5 IOD1 R/W b6 IOD2 TRCGRD mode select bit (2) 0: Output compare function 1: Input capture function R/W b7 IOD3 TRCGRD register function select bit 0: TRCIOB output register 1: General register or buffer register R/W

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 285 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.2.8 Timer RC Counter (TRC)

Access the TRC register in 16-bit units. Do not access it in 8-bit units.

20.2.9 Timer RC General Registers A, B, C, and D (TRCGRA, TRCGRB, TRCGRC,

TRCGRD) Access registers TRCGRA to TRCGRD in 16-bit units. Do not access them in 8-bit units. Address 0127h to 0126h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b15 to b0 Counts a count source. Count operation is increment. When an overflow occurs, the OVF bit in the TRCSR register is set to 1. 0000h to FFFFh R/W Address 0129h to 0128h (TRCGRA), 012Bh to 012Ah (TRCGRB), 012Dh to 012Ch (TRCGRC), 012Fh to 012Eh (TRCGRD) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 11111111 Bit Function R/W b15 to b0 Function varies according to the operating mode. R/W

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 286 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.2.10 Timer RC Contro l Register 2 (TRCCR2)

Notes: 1. Enabled when in PWM mode. 2. For notes on PWM2 mode, refer to 20.9.6 TRCMR Register in PWM2 Mode. 3. In timer mode and PWM mode, these bits are disabled.

20.2.11 Timer RC Digital Filter Function Select Register (TRCDF)

Notes: 1. These bits are enabled for the input capture function. 2. These bits are enabled when in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG trigger input enabled). Address 0130h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TCEG1 TCEG0 CSEL — — POLD POLC POLB A f t e r R e s e t 00011000 Bit Symbol Bit Name Function R/W b0 POLB PWM mode output level control bit B (1) 0: TRCIOB output level selected as low active 1: TRCIOB output level selected as high active R/W b1 POLC PWM mode output level control bit C (1) 0: TRCIOC output level selected as low active 1: TRCIOC output level selected as high active R/W b2 POLD PWM mode output level control bit D (1) 0: TRCIOD output level selected as low active 1: TRCIOD output level selected as high active R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b4 — b5 CSEL TRC count operation select bit (2) 0: Count continues at compare match with the TRCGRA register 1: Count stops at compare match with the TRCGRA register R/W b6 TCEG0 TRCTRG input edge select bit (3) b7 b6 0 0: Trigger input from the TRCTRG pin disabled 0 1: Rising edge selected 1 0: Falling edge selected 1 1: Both edges selected R/W b7 TCEG1 R/W Address 0131h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol DFCK1 DFCK0 — DFTRG DFD DFC DFB DFA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 DFA TRCIOA pin digital filter function select bit (1) 0: Function is not used 1: Function is used R/W b1 DFB TRCIOB pin digital filter function select bit (1) 0: Function is not used 1: Function is used R/W b2 DFC TRCIOC pin digital filter function select bit (1) 0: Function is not used 1: Function is used R/W b3 DFD TRCIOD pin digital filter function select bit (1) 0: Function is not used 1: Function is used R/W b4 DFTRG TRCTRG pin digital filter function select bit (2) 0: Function is not used 1: Function is used R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 DFCK0 Digital filter function clock select bit (1, 2) b7 b6 0 0: f32 0 1: f8 1 0: f1 1 1: Count source (clock selected by bits TCK0 to TCK2 in the TRCCR1 register) R/W b7 DFCK1 R/W

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 287 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.2.12 Timer RC Output Master Enable Register (TRCOER)

Note: 1. These bits are disabled for pins set as input-capture input.

20.2.13 Timer RC Trigger C ontrol Register (TRCADCR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PTO — — — ED EC EB EA A f t e r R e s e t 01111111 Bit Symbol Bit Name Function R/W b0 EA TRCIOA output disable bit (1) 0: Output enabled 1: Output disabled (TRCIOA pin functions as a programmable I/O port) R/W b1 EB TRCIOB output disable bit (1) 0: Output enabled 1: Output disabled (TRCIOB pin functions as a programmable I/O port) R/W b2 EC TRCIOC output disable bit (1) 0: Output enabled 1: Output disabled (TRCIOC pin functions as a programmable I/O port) R/W b3 ED TRCIOD output disable bit (1) 0: Output enabled 1: Output disabled (TRCIOD pin functions as a programmable I/O port) R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — b6 — b7 PTO INT0 of pulse output forced cutoff signal input enabled bit 0: Pulse output forced cutoff input disabled 1: Pulse output forced cutoff input enabled (Bits EA, EB, EC, and ED are set to 1 (output disabled) when a low-level signal is applied to the INT0 pin) R/W Address 0133h B i t b 7 b 6 b 5 b 4 b 3b 2b 1b 0 Symbol — — — — ADTRGDE ADTRGCE ADTRGBE ADTRGAE A f t e r R e s e t 0000 0 0 0 0 Bit Symbol Bit Name Function R/W b0 ADTRGAE A/D trigger A enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match between registers TRC and TRCGRA R/W b1 ADTRGBE A/D trigger B enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match between registers TRC and TRCGRB R/W b2 ADTRGCE A/D trigger C enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match between registers TRC and TRCGRC R/W b3 ADTRGDE A/D trigger D enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match between registers TRC and TRCGRD R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 —

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 288 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.2.14 Timer RB/RC Pin Se lect Register (TRBRCSR)

The register function for timer RB is not implemented. To use the I/O pins for timer RC, set the TRBRCSR register. Set this register before setting the timer RC associated registers. Also, do not change the setting value of the TRCCLKSEL0 bit during timer RC operation. Address 0181h B i t b 7 b 6b 5b 4b 3 b 2 b 1 b 0 Symbol TRCTRGSEL1 TRCTRGSEL0 — TRCCLKSEL0 — — — — A f t e r R e s e t 0 0 0 0 0000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 — b4 TRCCLKSEL0 TRCCLK pin select bit 0: TRCCLK pin not used 1: TRCCLK pin used R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 TRCTRGSEL0 TRCTRG pin select bit b7 b6 0 0: TRCTRG pin not used 0 1: P3_7 assigned 1 0: P4_3 assigned 1 1: P4_4 assigned R/W b7 TRCTRGSEL1 R/W

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 289 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.2.15 Timer RC Pin Select Register 0 (TRCPSR0)

The TRCPSR0 register selects whether to use the timer RC input. To use the I/O pins for timer RC, set this register. Set the TRCPSR0 register before setting the timer RC associated registers. Also, do not change the setting value of this register during timer RC operation. Address 0182h B i t b 7 b 6b 5 b 4b 3 b 2 b 1b 0 Symbol — — TRCIOBSEL1 TRCIOBSEL0 — —— TRCIOASEL0 A f t e r R e s e t 0 00 00 0 00 Bit Symbol Bit Name Function R/W b0 TRCIOASEL0 TRCIOA pin select bit 0: TRCIOA pin not used 1: TRCIOA pin used R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 — b3 — b4 TRCIOBSEL0 TRCIOB pin select bit b5 b4 0 0: TRCIOB pin not used 0 1: P4_5 assigned 1 0: P4_6 assigned 1 1: P4_7 assigned R/W b5 TRCIOBSEL1 R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 —

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 290 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.2.16 Timer RC Pin Select Register 1 (TRCPSR1)

Notes: 1. When bits TRCIOBSEL1 to TRCIOBSEL 0 in the TRCPSR0 register are se t to 10b (P4_6 a ssigned as TRCIOB pin), P4_6 functions as the TRCIOB pin regardless of the content of the TRCIOCSEL0 bit. 2. When bits TRCIOBSEL1 to TRCIO BSEL0 in the TRCPSR0 register are set to 11b (P4_7 assigned as TRCIOB pin), P4_7 functions as the TRCIOB pin regardless of the content of the TRCIODSEL0 bit. The TRCPSR1 register selects whether to use the timer RC input. To use the I/O pins for timer RC, set this register. Set the TRCPSR1 register before setting the timer RC associated registers. Also, do not change the setting value of this register during timer RC operation. Address 0183h B i t b 7b 6 b 5 b 4b 3b 2 b 1 b 0 Symbol — — — TRCIODSEL0 — —— TRCIOCSEL0 A f t e r R e s e t 0 000 0 000 Bit Symbol Bit Name Function R/W b0 TRCIOCSEL0 TRCIOC pin select bit (1) 0: TRCIOC pin not used 1: P4_6 assigned R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 — b3 — b4 TRCIODSEL0 TRCIOD pin select bit (2) 0: TRCIOD pin not used 1: P4_7 assigned R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 — b7 —

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 291 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.3 Common Items for Multiple Modes

20.3.1 Count Source

The method of selecting the count source is common to all modes. Table 20.5 lists the Count Source Selection, and Figure 20.2 shows the Count Source Block Diagram. Figure 20.2 Count Source Block Diagram The pulse width of the external clock input to the TRCCLK pin should be set to three cycles or more of the timer RC operation clock. (See Table 20.1 Timer RC Operating Clocks.) To select fOCO40M as the count source, set the FRA00 bit in the FRA0 register set to 1 (high-speed on-chip oscillator on), and then set bits TCK2 to TCK0 in the TRCCR1 register to 110b (fOCO40M). Table 20.5 Count Source Selection Count Source Selection Method f1, f2, f4, f8, f32 The count source is selected by bits TCK0 to TCK2 in TRCCR1 register fOCO40M - The FRA00 bit in the FRA0 register set to 1 (high-speed on-chip oscillator on). - Bits TCK2 to TCK0 in the TRCCR1 register are set to 110b (fOCO40M). External signal input to TRCCLK pin - Bits TCK2 to TCK0 in TRCCR1 register are set to 101b (count source is rising edge of external clock) - The corresponding direction bit in the direction register is set is set to 0 (input mode) TCK2 to TCK0 TRC register TCK0 to TCK2: Bits in TRCCR1 register f32 = 001b = 010b = 011b = 000b = 110b = 100b Count source TRCCLK = 101b fOCO40M

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 292 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.3.2 Buffer Operation

Bits BFC and BFD in the TRCMR regist er are used to select the TRCGRC or TRCGRD register as the buffer register of the TRCGRA or TRCGRB register.

• Buffer register of TRCGRA register: TRCGRC register
• Buffer register of TRCGRB register: TRCGRD register Buffer operation differs depending on the mode. Table 20.6 lists the Buffer Operation in Each Mode, Figure 20.3 shows the Buffer Operation of Input Capture Function, and Figure 20.4 shows the Buffer Operation of Output Compare Function. Figure 20.3 Buffer Operation of Input Capture Function Table 20.6 Buffer Operation in Each Mode Function, Mode Transfer Timing Transfer Destination Register Input capture function Input capture si gnal input The content of the TRCGRA (TRCGRB) register is transferred to the buffer register. Output compare function Comp are match between the TRC register and the TRCGRA (TRCGRB) register The content of the buffer register is transferred to the TRCGRA (TRCGRB) register.PWM mode PWM2 mode • Compare match between the TRC register and the TRCGRA register
• TRCTRG pin trigger input The content of the buffer register (TRCGRD) is transferred to the TRCGRB register. m Transfer n n-1 n+1 TRCIOA input TRC register The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (TRCGRC register is used as the buffer register of the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 100b (input capture at the rising edge). m Transfer n TRCGRC register TRCGRA register TRC TRCIOA input (input capture signal) TRCGRA register TRCGRC register (buffer)

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 293 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 20.4 Buffer Operation of Output Compare Function Make the following settings in timer mode.

• To use the TRCGRC register as the buffer register of the TRCGRA register: Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
• To use the TRCGRD register as the buffer register of the TRCGRB register: Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. When the TRCGRC or TRCGRD register is also used as the buffer register for the output compare function, in PWM mode, or PWM2 mode, the IMFC or IMFD bit in the TRCSR register is set to 1 by a compare match with the TRC register. When the TRCGRC register or TRCGRD register is also used as the bu ffer register for the input capture function, the IMFC or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC or TRCIOD pin. mnTRCGRA register m-1 m+1TRC register The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (TRCGRC register is used as the buffer register of the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (low-level output at compare match). n Transfer TRCGRC register (buffer) m TRCIOA output TRCGRC register TRCGRA register Comparator TRC Compare match signal

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 294 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.3.3 Digital Filter

The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is determined when three matches occur. The digital filter function and sampling clock can be selected using the TRCDF register. Figure 20.5 shows a Block Diagram of Digital Filter. Figure 20.5 Block Diagram of Digital Filter C DQ Latch C DQ Latch C DQ Latch Match detect circuit Edge detect circuit DFj (or DFTRG) Sampling clock IOA2 to IOA0 IOB2 to IOB0 IOC2 to IOC0 IOD2 to IOD0 (or TCEG1 to TCEG0) DFCK1 to DFCK0 TRCIOj input signal (or TRCTRG input signal) Clock cycle selected by TCK2 to TCK0 (or DFCK1 to DFCK0) Sampling clock TRCIOj input signal (or TRCTRG input signal) Input signal after passing through digital filter If fewer than three matches occur, the matches are recognized as noise and no transmission is performed. Maximum signal transmission delay is five sampling clocks. Three matches occur and a signal change is confirmed. f32 j = A, B, C, or D TCK0 to TCK2: Bits in TRCCR1 register DFTRG, DFCK0, DFCK1, DFj: Bits in TRCDF register IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register TCEG0, TCEG1: Bits in TRCCR2 register C DQ Latch C DQ Latch Timer RC operating clock f1 or fOCO40M Count source = 00b = 01b = 10b = 11b TCK2 to TCK0 = 001b = 010b = 011b = 000b = 100b = 101b f32 TRCCLK fOCO40M = 110b fOCO-F = 111b

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 295 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.3.4 Forced Cutoff of Pulse Output

When using the timer mode’s output compare function, PWM mode, or PWM2 mode, pulse output from the TRCIOj (j = A, B, C, or D) output pin can be forcibly cut off and the TRCIOj pin set to function as a programmable I/O port by means of input to the INT0 pin. A pin used for output by the timer mode’s output compare function, PWM mode, or PWM2 mode can be set to function as the timer RC output pin by setting the Ej bit in the TRCOER register to 0 (timer RC output enabled). If a low-level signal is input to the INT0 pin while the PTO bit in the TRCOER register is set to 1 (pulse output forced cutoff signal input INT0 enabled), bits EA, EB, EC , and ED in the TRCOER re gister are all set to 1 (timer RC output disabled, TRCIOj output pin functions as a programmable I/O port). When one or two cycles of the timer RC operation clock after a low-level signal input to the INT0 pin (refer to Table 20.1 Timer RC Operating Clocks) has elapsed, the TRCIOj output pin functions as a programmable I/O port. Make the following settings to use this function.

• Set the pin state following forced cutoff of pulse output (high impedance (input), low-level output, or high- level output). (Refer to 7. I/O Ports.)
• Set the INT0EN bit to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge) in the INTEN register.
• Set the direction registers for the I/O ports selected as INT0 to input mode: When INT0 is assigned to P3_0 by the INT0SEL0 bit in the INTSR register, set the PD3_0 bit in the PD3 register to 0 (input mode). When INT0 is assigned to P11_0 by the INT0SEL0 bit in the INTSR register, set the PD11_0 bit in the PD11 register to 0 (input mode).
• Select the INT0 digital filter with bits INT0F0 and INT0F1 in the INTF register.
• Set the PTO bit in the TRCOER register to 1 (pulse output forced cutoff signal input INT0 enabled). The IR bit in the INT0IC register is set to 1 (interru pt requested) in accordance wi th the setting of the POL bit and a change in the INT0 pin input (refer to 12.8 Notes on Interrupts). For details on interrupts, refer to 12. Interrupts.

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 296 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 20.6 Forced Cutoff of Pulse Output INT0 input TRCIOA PTO bit D S Q EA bitEA bit write value TRCIOB D S Q EB bitEB bit write value TRCIOC D S Q EC bitEC bit write value TRCIOD D S Q ED bitED bit write value EA, EB, EC, ED, PTO: Bits in TRCOER register Timer RC output data Timer RC output data Timer RC output data Timer RC output data

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 297 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.4 Timer Mode (I nput Capture Function)

This function measures the width or period of an external si gnal. An external signal input to the TRCIOj (j = A, B, C, or D) pin acts as a trigger for transferring the cont ent of the TRC register (counter) to the TRCGRj register (input capture). The input capture function, or any other mode or function, can be selected for each individual pin. Table 20.7 lists the Input Capture Function Specifications , Figure 20.7 shows a Block Diagram of Input Capture Function, Table 20.8 lists the Functions of TRCGRj Register when Using Input Capture Function, and Figure 20.8 shows an Operating Example of Input Capture Function. j = A, B, C, or D Table 20.7 Input Capture Function Specifications Item Specification Count sources f1, f2, f4, f8, f32, fOCO40M External signal (rising edge) input to the TRCCLK pin Count operation Increment Count period 1/fk × 65,536 fk: Frequency of count source Count start condition 1 (count starts) is writt en to the TSTART bit in the TRCMR register. Count stop condition 0 (count stops) is written to the TSTART bit in the TRCMR register. The TRC register retains a value before the count stops. Interrupt request generation timing

• Input capture (active edge of the TRCIOj input)
• TRC register overflows TRCIOA, TRCIOB, TRCIOC, and TRCIOD pins function Programmable I/O port or input capture input (selectable for each individual pin) INT0 pin function Programmable I/O port or INT0 interrupt input Read from timer The count value can be read by reading TRC register. Write to timer The TRC register can be written to. Selectable functions • Input-c apture input pin selection One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Input-capture input active edge selection Rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 20.3.2 Buffer Operation.)
• Digital filter (Refer to 20.3.3 Digital Filter.)
• Timing for setting the TRC register to 0000h Overflow or input capture

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 298 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 20.7 Block Diagram of Input Capture Function Notes: 1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register is used as the buffer register for the TRCGRA register) 2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register is used as the buffer register for the TRCGRB register) 3. The trigger input of the TRCGRA register can select the TRCIOA pin input or fOCO128 signal. TRCGRA register TRC register Input capture signal TRCGRC register TRCGRB register Input capture signal TRCGRB register TRCIOB (Note 1) (Note 2) TRCIOC TRCIOD Input capture signal Input capture signal Polarity switching Polarity switching Polarity switching Polarity switching TRCIOA Divided by 128 IOA3 = 0 IOA3 = 1 fOCO fOCO128 Input capture signal (Note 3)

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 299 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.4.1 Timer RC I/O Control Register 0 (TRCIOR0) in Timer Mode (Input Capture

Function) Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffe r register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffe r register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. 3. The IOA3 bit is enabled when the IOA2 bit is set to 1 (input capture function). Address 0124h B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l — I O B 2I O B 1I O B 0I O A 3I O A 2I O A 1I O A 0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOA0 TRCGRA control bit b1 b0 0 0: Input capture to the TRCGRA register at the rising edge 0 1: Input capture to the TRCGRA register at the falling edge 1 0: Input capture to the TRCGRA register at both edges 1 1: Do not set. R/W b1 IOA1 R/W b2 IOA2 TRCGRA mode select bit (1) Set to 1 (input capture) for the input capture function. R/W b3 IOA3 TRCGRA input-capture input switch bit (3) 0: fOCO128 signal 1: TRCIOA pin input R/W b4 IOB0 TRCGRB control bit b5 b4 0 0: Input capture to the TRCGRB register at the rising edge 0 1: Input capture to the TRCGRB register at the falling edge 1 0: Input capture to the TRCGRB register at both edges 1 1: Do not set. R/W b5 IOB1 R/W b6 IOB2 TRCGRB mode select bit (2) Set to 1 (input capture) for the input capture function. R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 300 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.4.2 Timer RC I/O Control Register 1 (TRCIOR1) in Timer Mode (Input Capture

Function) Notes: 1. When the BFC bit in the TRCMR register is set to 1 (buffe r register of TRCGRA register), set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffe r register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. j = A, B, C, or D BFC, BFD: Bits in TRCMR register Address 0125h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOC0 TRCGRC control bit b1 b0 0 0: Input capture to the TRCGRC register at the rising edge 0 1: Input capture to the TRCGRC register at the falling edge 1 0: Input capture to the TRCGRC register at both edges 1 1: Do not set. R/W b1 IOC1 R/W b2 IOC2 TRCGRC mode select bit (1) Set to 1 (input capture) for the input capture function. R/W b3 IOC3 TRCGRC register function select bit Set to 1. R/W b4 IOD0 TRCGRD control bit b5 b4 0 0: Input capture to the TRCGRD register at the rising edge 0 1: Input capture to the TRCGRD register at the falling edge 1 0: Input capture to the TRCGRD register at both edges 1 1: Do not set. R/W b5 IOD1 R/W b6 IOD2 TRCGRD mode select bit (2) Set to 1 (input capture) for the input capture function. R/W b7 IOD3 TRCGRD register function select bit Set to 1. R/W Table 20.8 Functions of TRCGRj Register when Using Input Capture Function Register Setting Register Function Input Capture Input Pin TRCGRA − General register. Can be used to read the TRC register value at input capture. TRCIOA TRCGRB TRCIOB TRCGRC BFC = 0 General register. Can be us ed to read the TRC register value at input capture. TRCIOC TRCGRD BFD = 0 TRCIOD TRCGRC BFC = 1 Buffer regist ers. Can be used to retain the transferred value from the general register. (Refer to 20.3.2 Buffer Operation.) TRCIOA TRCGRD BFD = 1 TRCIOB

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 301 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.4.3 Operating Example

Figure 20.8 Operating Example of Input Capture Function TRC register count value TSTART bit in TRCMR register TRCGRA register TRCIOA input TRCGRC register IMFA bit in TRCSR register OVF bit in TRCSR register TRCCLK input count source The above applies under the following conditions:

• The CCLR bit in the TRCCR1 register is set to 1 (TRC counter cleared by input capture).
• Bits TCK2 to TCK0 in the TRCCR1 register are set to 101b (TRCCLK input selected as the count source).
• Bits IOA2 to IOA0 in the TRCIORA register are set to 101b (input capture at the falling edge of the TRCIOA input).
• The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register of the TRCGRA register). Transfer FFFFh 0009h 0006h 0000h 0009h0006h 0006h Transfer Set to 0 by a program. 65,536

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 302 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.5 Timer Mode (Out put Compare Function)

This function detects when the contents of the TRC register (counter) and the TRCGRj register (j = A, B, C, or D) match (compare match). When a match occurs, a signal is output from the TRCIOj pin at a given level. The output compare function, or other mode or function, can be selected for each individual pin. Table 20.9 lists the Output Compare Function Specific ations, Figure 20.9 shows a Block Diagram of Output Compare Function, Table 20.10 lists the Functions of TRCGRj Register when Using Output Compare Function, and Figure 20.10 shows an Operating Example of Output Compare Function. j = A, B, C, or D Table 20.9 Output Compare Function Specifications Item Specification Count sources f1, f2, f4, f8, f32, fOCO40M, fOCO-F External signal input to the TRCCLK pin (rising edge) Count operation Increment Count periods • The CCLR bit in the TRCCR1 regist er is set to 0 (free-running operation): 1/fk × 65,536 fk: Frequency of count source

• The CCLR bit in the TRCCR1 register is set to 1 (TRC register is set to 0000h by TRCGRA compare match): 1/fk × (n + 1) n: Value set in TRCGRA register Waveform output timing Compare match Count start condition 1 (count starts) is written to the TSTART bit in the TRCMR register. Count stop condition • When the CSEL bit in the TRCCR2 register is set to 0 (count continues after compare match with the TRCGRA register). 0 (count stops) is written to the TSTART bit in the TRCMR register. The output compare output pin retains the output level before the count stops, the TRC register retains a value before the count stops.
• When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA register). The count stops at a compare match with the TRCGRA register. The output- compare output pin retains the level after the output is changed by the compare match. Interrupt request generation timing
• Compare match (the contents of the TRC register and the TRCGRj register match.)
• TRC register overflow TRCIOA, TRCIOB, TRCIOC, and TRCIOD pins function Programmable I/O port or output compare output (selectable for each individual pin) INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input Read from timer The count value can be read by reading the TRC register. Write to timer The TRC register can be written to. Selectable functions • Output-compare output pin selection One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Output level selection at the compare match Low-level output, High-level output, or toggle output
• Initial output level selection Selectable output level for the period from the count start to the compare match
• Timing for setting the TRC register to 0000h Overflow or compare match with the TRCGRA register
• Buffer operation (Refer to 20.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 20.3.4 Forced Cutoff of Pulse Output.)
• Timer RC can be used as an internal timer by disabling the timer RC output
• Changing output pins for registers TRCGRC and TRCGRD TRCGRC can be used for output control of the TRCIOA pin and TRCGRD can be used for output control of the TRCIOB pin.
• A/D trigger generation

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 303 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 20.9 Block Diagram of Output Compare Function TRCIOA Output control Comparator TRCGRA TRC TRCIOC TRCGRC TRCIOB TRCGRB TRCIOD TRCGRD Output control Output control Output control Compare match signal Compare match signal Compare match signal Compare match signal Comparator Comparator Comparator

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 304 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.5.1 Timer RC Control Register 1 (T RCCR1) in Timer Mode (Output Compare

Function) Notes: 1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops). 2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRCCR1 register is set. j = A, B, C, or D BFC, BFD: Bits in TRCMR register Address 0121h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR TCK2 TCK1 TCK0 TOD TOC TOB TOA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOA TRCIOA output level select bit (1, 2) 0: Initial output at low 1: Initial output at high R/W b1 TOB TRCIOB output level select bit (1, 2) R/W b2 TOC TRCIOC output level select bit (1, 2) R/W b3 TOD TRCIOD output level select bit (1, 2) R/W b4 TCK0 Count source select bit (1) b6 b5 b4 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRCCLK input rising edge 1 1 0: fOCO40M 1 1 1: Do not set. R/W b5 TCK1 R/W b6 TCK2 R/W b7 CCLR TRC counter clear select bit 0: Clear disabled (free-running operation) 1: Clear by compare match with the TRCGRA register R/W Table 20.10 Functions of TRCGRj Register when Using Output Compare Function Register Setting Register Function Output Compare Output Pin TRCGRA − General register. Write a compare value to one of these registers. TRCIOA TRCGRB TRCIOB TRCGRC BFC = 0 General register. Writ e a compare value to one of these registers. TRCIOC TRCGRD BFD = 0 TRCIOD TRCGRC BFC = 1 Buffer register. Write the next compare value to one of these registers. (Refer to 20.3.2 Buffer Operation.) TRCIOA TRCGRD BFD = 1 TRCIOB

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 305 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.5.2 Timer RC I/O Contro l Register 0 (TRCIOR0) in Timer Mode (Output

Compare Function) Notes: 1. When the BFC bit in the TRCMR register is set to 1 ( buffer register of TRCGRA register), set the IOC2 bit in theTRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 (buffe r register of TRCGRB register), set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. Address 0124h B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l — I O B 2I O B 1I O B 0I O A 3I O A 2I O A 1I O A 0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOA0 TRCGRA control bit b1 b0 0 0: Pin output by compare match is disabled (TRCIOA pin functions as a programmable I/O port) 0 1: Low-level output at compare match with the TRCGRA register 1 0: High-level output at compare match with the TRCGRA register 1 1: Toggle output at compare match with the TRCGRA register R/W b1 IOA1 R/W b2 IOA2 TRCGRA mode select bit (1) Set to 0 (output compare) for the output compare function. R/W b3 IOA3 TRCGRA input capture input switch bit Set to 1. R/W b4 IOB0 TRCGRB control bit b5 b4 0 0: Pin output by compare match is disabled (TRCIOB pin functions as a programmable I/O port) 0 1: Low-level output at compare match with the TRCGRB register 1 0: High-level output at compare match with the TRCGRB register 1 1: Toggle output at compare match with the TRCGRB register R/W b5 IOB1 R/W b6 IOB2 TRCGRB mode select bit (2) Set to 0 (output compare) for the output compare function. R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 306 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.5.3 Timer RC I/O Contro l Register 1 (TRCIOR1) in Timer Mode (Output

Compare Function) Notes: 1. When the BFC bit in the TRCMR register is set to 1 ( buffer register of TRCGRA register), set the IOC2 bit in theTRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register. 2. When the BFD bit in the TRCMR register is set to 1 ( buffer register of TRCGRB register), set the IOD2 bit in theTRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register. Address 0125h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOC0 TRCGRC control bit b1 b0 0 0: Pin output by compare match is disabled 0 1: Low-level output at compare match with the TRCGRC register 1 0: High-level output at compare match with the TRCGRC register 1 1: Toggle output at compare match with the TRCGRC register R/W b1 IOC1 R/W b2 IOC2 TRCGRC mode select bit (1) Set to 0 (output compare) for the output compare function. R/W b3 IOC3 TRCGRC register function select bit 0: TRCIOA output register 1: General register or buffer register R/W b4 IOD0 TRCGRD control bit b5 b4 0 0: Pin output by compare match is disabled 0 1: Low-level output at compare match with the TRCGRD register 1 0: High-level output at compare match with the TRCGRD register 1 1: Toggle output at compare match with the TRCGRD register R/W b5 IOD1 R/W b6 IOD2 TRCGRD mode select bit (2) Set to 0 (output compare) for the output compare function. R/W b7 IOD3 TRCGRD register function select bit 0: TRCIOB output register 1: General register or buffer register R/W

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 307 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.5.4 Operating Example

Figure 20.10 Operating Example of Output Compare Function Output level held m n p TRC register value Count source m+1 m+1 TSTART bit in TRCMR register TRCIOA output IMFA bit in TRCSR register n+1 TRCIOB output “H” output at compare match Set to 0 by a program. IMFB bit in TRCSR register Initial output “L” Initial output “L” TRCIOC output Set to 0 by a program. IMFC bit in TRCSR register Initial output “H” “L” output at compare match P+1 m: Value set in TRCGRA register n: Value set in TRCGRB register p: Value set in TRCGRC register The above applies under the following conditions: Count restarts Count stops Output level held Set to 0 by a program.

• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD are not used as buffer registers).
• Bits EA, EB, and EC in the TRCOER register are set to 0 (TRCIOA, TRCIOB, and TRCIOC pin output enabled).
• The CCLR bit in the TRCCR1 register is set to 1 (TRC register is set to 0000h by compare match with TRCGRA register ).
• Bits TOA and TOB in the TRCCR1 register are are set to 0 (initial output at low until compare match) and the TOC bit is set to 1 (initial output at high until compare match).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted by TRCGRA compare match).
• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (TRCIOB high-level output at TRCGRB compare match).
• Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (TRCIOC low-level output at TRCGRC compare match).
• The CSEL bit in the TRCCR2 register is set to 0 (TRC count continues after TRCGRA compare match). Output level held Output inverted at compare match

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 308 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.5.5 Changing Output Pins in Registers TRCGRC and TRCGRD

The TRCGRC register can be used for output control of the TRCIOA pin, and the TRCGRD register can be used for output control of the TRCIOB pin. Each pin output can be controlled as follows:

• TRCIOA output is controlled by the values of registers TRCGRA and TRCGRC.
• TRCIOB output is controlled by the values of registers TRCGRB and TRCGRD. Figure 20.11 Changing Output Pins in Registers TRCGRC and TRCGRD Change output pins in registers TRCGRC and TRCGRD as follows:
• Set the IOC3 bit in the TRCIOR1 register to 0 (TRCIOA output register) and set the IOD3 bit to 0 (TRCIOB output register).
• Set bits BFC and BFD in the TRCMR register to 0 (general register).
• Set different values in register s TRCGRC and TRCGRA. Also, set diff erent values in registers TRCGRD and TRCGRB. TRCIOA Output control Comparator TRCGRA TRC TRCIOC TRCGRC TRCIOB TRCGRB TRCIOD TRCGRD Output control Output control Output control Compare match signal Compare match signal Compare match signal Compare match signal Comparator Comparator Comparator

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 310 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.6 PWM Mode

This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output. PWM mode or timer mode can be selected for each individual pin. (However, the TRCGRA register cannot be used for timer mode since the register is used when using any pin for PWM mode.) Table 20.11 lists the PWM Mode Specifications, Figure 20.13 shows a Block Diagram of PWM Mode, Table 20.12 lists the Functions of TRCGRh Register in PWM Mode, and Figures 20.14 and 20.15 show Operating Examples in PWM Mode. j = B, C, or D h = A, B, C, or D Table 20.11 PWM Mode Specifications Item Specification Count source f1, f2, f4, f8, f32, fOCO40M, fOCO-F External signal (rising edge) input to the TRCCLK pin Count operation Increment PWM waveform PWM period: 1/fk × (m + 1) Active level width: 1/fk × (m - n) Inactive width: 1/fk × (n + 1) fk: Frequency of count source m: Value set in TRCGRA register n: Value set in TRCGRj register Count start condition 1 (count starts) is writ ten to the TSTART bit in the TRCMR register. Count stop condition • When the CSEL bit in th e TRCCR2 register is set to 0 (count continues after compare match with the TRCGRA register). 0 (count stops) is written to the TSTART bit in the TRCMR register. The PWM output pin retains the output level before the count stops, The TRC register retains a value before the count stops.

• When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA register). The count stops at a compare match with the TRCGRA register. The PWM output pin retains the level after the output is changed by the compare match. Interrupt request generation timing
• Compare match (the contents of the TRC register and the TRCGRj register match)
• TRC register overflow TRCIOA pin function Programmable I/O port TRCIOB, TRCIOC, and TRCIOD pins function Programmable I/O port or PWM output (selectable for each individual pin) INT0 pin function Programmable I/O port, pulse out put forced cutoff signal input, or INT0 interrupt input Read from timer The count value can be read by reading the TRC register. Write to timer The TRC register can be written to. Selectable functions • One to three pins selectable as PWM pins One or more of pins TRCIOB, TRCIOC, and TRCIOD
• Active level selectable for each individual pin
• Initial level selectable for each individual pin
• Buffer operation (Refer to 20.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 20.3.4 Forced Cutoff of Pulse Output.)
• A/D trigger generation m+1 n+1 m-n (Active level is low)

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 311 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 20.13 Block Diagram of PWM Mode TRCIOB Output control Comparator TRCGRA TRC Compare match signal TRCGRBTRCIOC TRCGRC TRCGRD TRCIOD Notes: 1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register is used as the buffer register of the TRCGRA register). 2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register is used as the buffer register of the TRCGRB register). (Note 1) (Note 2) Compare match signal Compare match signal Compare match signal Comparator Comparator Comparator

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 312 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.6.1 Timer RC Control Regist er 1 (TRCCR1) in PWM Mode

Notes: 1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops). 2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRCCR1 register is set. Address 0121h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR TCK2 TCK1 TCK0 TOD TOC TOB TOA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOA TRCIOA output level select bit (1) Disabled in PWM mode. R/W b1 TOB TRCIOB output level select bit (1, 2) 0: Initial output selected as non-active level 1: Initial output selected as active level R/W b2 TOC TRCIOC output level select bit (1, 2) R/W b3 TOD TRCIOD output level select bit (1, 2) R/W b4 TCK0 Count source select bit (1) b6 b5 b4 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRCCLK input rising edge 1 1 0: fOCO40M 1 1 1: Do not set. R/W b5 TCK1 R/W b6 TCK2 R/W b7 CCLR TRC counter clear select bit 0: Clear disabled (free-running operation) 1: Clear by compare match with the TRCGRA register R/W

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 313 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.6.2 Timer RC Control Regist er 2 (TRCCR2) in PWM Mode

Notes: 1. Enabled when in PWM mode. 2. For notes on PWM2 mode, refer to 20.9.6 TRCMR Register in PWM2 Mode. 3. In timer mode and PWM mode these bits are disabled. j = A, B, C, or D BFC, BFD: Bits in TRCMR register Note: 1. The output level does not change even if a compare match occurs when the TRCGRA register value (PWM period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value. Address 0130h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TCEG1 TCEG0 CSEL — — POLD POLC POLB A f t e r R e s e t 00011000 Bit Symbol Bit Name Function R/W b0 POLB PWM mode output level control bit B (1) 0: TRCIOB output level selected as low active 1: TRCIOB output level selected as high active R/W b1 POLC PWM mode output level control bit C (1) 0: TRCIOC output level selected as low active 1: TRCIOC output level selected as high active R/W b2 POLD PWM mode output level control bit D (1) 0: TRCIOD output level selected as low active 1: TRCIOD output level selected as high active R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b4 — b5 CSEL TRC count operation select bit (2) 0: Count continues at compare match with the TRCGRA register 1: Count stops at compare match with the TRCGRA register R/W b6 TCEG0 TRCTRG input edge select bit (3) b7 b6 0 0: Trigger input from the TRCTRG pin disabled 0 1: Rising edge selected 1 0: Falling edge selected 1 1: Both edges selected R/W b7 TCEG1 R/W Table 20.12 Functions of TRCGRh Register in PWM Mode Register Setting Register Function PWM Output Pin TRCGRA − General register. Set the PWM period. − TRCGRB − General register. Set the PWM output change point. TRCIOB TRCGRC BFC = 0 General register. Set the PWM output change point. TRCIOC TRCGRD BFD = 0 TRCIOD TRCGRC BFC = 1 Buffer register. Set the next PWM period. (Refer to

20.3.2 Buffer

Operation.) TRCGRD BFD = 1 Buffer register. Set the next PWM output change point. (Refer to 20.3.2 Buffer Operation.) TRCIOB

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 314 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.6.3 Operating Example

Figure 20.14 Operating Example in PWM Mode TRCIOC output TRCIOD output m: Value set in TRCGRA register n: Value set in TRCGRB register p: Value set in TRCGRC register q: Value set in TRCGRD register TRCIOB output IMFA bit in TRCSR register IMFB bit in TRCSR register IMFC bit in TRCSR register IMFD bit in TRCSR register The above applies under the following conditions:

• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD are not used as buffer registers).
• Bits EB, EC, and ED in the TRCOER register are set to 0 (TRCIOB, TRCIOC, and TRCIOD pin output enabled).
• Bits TOB and TOC in the TRCCR1 register are set to 0 (inactive level) and the TOD bit is set to 1 (active level).
• The POLB bit in the TRCCR2 register is set to 1 (high active), bits POLC and POLD are set to 0 (low active). m n p TRC register value Count source m+1 n+1 q m-n p+1 m-p m-qq+1 Inactive level “L” Active level “H” Inactive level “H” Active level “L” Set to 0 by a program. Set to 0 by a program. Set to 0 by a program. Set to 0 by a program. Initial output “L” until compare match Initial output “H” until compare match Initial output “L” utnil compare match

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 315 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 20.15 Operating Example in PWM Mode (Duty 0% and Duty 100%) Rewrite by a program. m p q TRC register value n m: Value set in TRCGRA register Set to 0 by a program. Rewrite by a program. 0000h q Duty 0% TRCGRB register IMFA bit in TRCSR register IMFB bit in TRCSR register TSTART bit in TRCMR register TRCIOB output p (p>m)n m p TRC register value n 0000h TRCGRB register IMFA bit in TRCSR register IMFB bit in TRCSR register TSTART bit in TRCMR register TRCIOB output pn m The above applies under the following conditions:

• The EB bit in the TRCOER register is set to 0 (TRCIOB pin output enabled).
• The POLB bit in the TRCCR2 register is set to 0 (low active). TRCIOB output does not switch to “L” because no compare match with the TRCGRB register has occurred. If compare matches occur simultaneously with registers TRCGRA and TRCGRB, the compare match with the TRCGRB register has priority. TRCIOB output switches to “L” (i.e. no change). TRCIOB output switches to “L” at compare match with the TRCGRB register (i.e. no change). Set to 0 by a program.Set to 0 by a program. Duty 100% Set to 0 by a program.

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 316 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.7 PWM2 Mode

This mode outputs a single PWM waveform. After a give n wait time has elapsed following the trigger, the pin output switches to active level. Then, after a given duration, the output switches back to inactive level. Furthermore, the counter stops at the same time the output returns to inactive level, making it possible to use PWM2 mode to output a programmable wait one-shot waveform. Since timer RC uses multiple general registers in PWM2 mode, other modes cannot be used in conjunction with it. Figure 20.16 shows a Block Diagram of PWM2 Mode, Ta ble 20.13 lists the PWM2 Mode Specifications, Table 20.14 lists the Functions of TRCGRj Register in PWM2 Mode, and Figures 20.17 to 20.19 show Operating Examples in PWM2 Mode. Figure 20.16 Block Diagram of PWM2 Mode TRCTRG Input control TRCIOB Output control Comparator TRCGRATRC TRCGRD register Compare match signal Comparator TRCGRB Comparator TRCGRC Note: 1. The BFD bit in the TRCMR register is set to 1 (TRCGRD regi ster is used as the buffer register of the TRCGRB register). Count clear signal Trigger signal (Note 1)

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 317 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group j = A, B, or C Table 20.13 PWM2 Mode Specifications Item Specification Count source f1, f2, f4, f8, f32, fOCO40M, fOCO-F External signal input to TRCCLK pin (rising edge) Count operation TRC register increment PWM waveform PWM period: 1/fk × (m + 1) (no TRCTRG input) Active level width: 1/fk × (n - p) Wait time from count start or trigger: 1/fk × (p + 1) fk: Frequency of count source m: Value set in TRCGRA register n: Value set in TRCGRB register p: Value set in TRCGRC register Count start conditions • Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues). 1 (count starts) is written to the TSTART bit in the TRCMR register.

• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG trigger enabled) and the TSTART bit in the TRCMR register is set to 1 (count starts). A trigger is input to the TRCTRG pin. Count stop conditions • 0 (count stops) is written to the TS TART bit in the TRCMR register while the CSEL bit in the TRCCR2 register is set to 0 or 1. The TRCIOB pin outputs the initial level in accordance with the value of the TOB bit in the TRCCR1 register. The TRC register retains the value before the count stops.
• The count stops at a compare match with TRCGRA while the CSEL bit in the TRCCR2 register is set to 1 The TRCIOB pin outputs the initial level. The TRC register retains the value before the count stops when the CCLR bit in the TRCCR1 register is set to 0. The TRC register is set to 0000h when the CCLR bit in the TRCCR1 register is set to 1. Interrupt request generation timing
• Compare match (the contents of the TRC register and the TRCGRj register match.)
• TRC register overflow TRCIOA/TRCTRG pins function Programmable I/O port or TRCTRG input TRCIOB pin function PWM output TRCIOC/TRCIOD pins function Programmable I/O port INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input Read from timer The count value can be read by reading the TRC register. Write to timer The TRC register can be written to. Selectable functions • External trigger and active edge selection The edge or edges of the signal input to the TRCTRG pin can be used as the PWM output trigger: rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 20.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 20.3.4 Forced Cutoff of Pulse Output.)
• Digital filter (Refer to 20.3.3 Digital Filter.)
• A/D trigger generation m+1 TRCTRG input TRCIOB output (TRCTRG: Rising edge, active level is high) n-p n+1 p+1 p+1 n+1 n-p

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 318 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.7.1 Timer RC Control Regist er 1 (TRCCR1) in PWM2 Mode

Notes: 1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops). 2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRCCR1 register is set. j = A, B, C, or D BFC, BFD: Bits in TRCMR register Note: 1. Do not set registers TRCGRB and TRCGRC to the same value. Address 0121h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR TCK2 TCK1 TCK0 TOD TOC TOB TOA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOA TRCIOA output level select bit (1) Disabled in PWM2 mode. R/W b1 TOB TRCIOB output level select bit (1, 2) 0: Active level is high (Initial output at low High-level output at compare match with the TRCGRC register Low-level output at compare match with the TRCGRB register) 1: Active level is low (Initial output at high Low-level output at compare match with the TRCGRC register High-level output at compare match with the TRCGRB register) R/W b2 TOC TRCIOC output level select bit (1) Disabled in PWM2 mode. R/W b3 TOD TRCIOD output level select bit (1) R/W b4 TCK0 Count source select bit (1) b6 b5 b4 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRCCLK input rising edge 1 1 0: fOCO40M 1 1 1: Do not set. R/W b5 TCK1 R/W b6 TCK2 R/W b7 CCLR TRC counter clear select bit 0: Clear disabled (free-running operation) 1: Clear by compare match with the TRCGRA register R/W Table 20.14 Functions of TRCGRj Register in PWM2 Mode Register Setting Register Function PWM2 Output Pin TRCGRA − General register. Set the PWM period. TRCIOB pin TRCGRB − General register. Set the PWM output change point. TRCGRC BFC = 0 General register. Set the PWM output change point (wait time after trigger). TRCGRD BFD = 0 (Not used in PWM2 mode.) − TRCGRD BFD = 1 Buffer register. Set the next PWM output change point. (Refer to 20.3.2 Buffer Operation.) TRCIOB pin

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 319 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.7.2 Timer RC Control Regist er 2 (TRCCR2) in PWM2 Mode

Notes: 1. Enabled when in PWM mode. 2. For notes on PWM2 mode, refer to 20.9.6 TRCMR Register in PWM2 Mode. 3. In timer mode and PWM mode, these bits are disabled.

20.7.3 Timer RC Digital Filt er Function Select Register (TRCDF) in PWM2 Mode

Notes: 1. These bits are enabled for the input capture function. 2. These bits are enabled when in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG trigger input enabled). Address 0130h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TCEG1 TCEG0 CSEL — — POLD POLC POLB A f t e r R e s e t 00011000 Bit Symbol Bit Name Function R/W b0 POLB PWM mode output level control bit B (1) 0: TRCIOB output level selected as low active 1: TRCIOB output level selected as high active R/W b1 POLC PWM mode output level control bit C (1) 0: TRCIOC output level selected as low active 1: TRCIOC output level selected as high active R/W b2 POLD PWM mode output level control bit D (1) 0: TRCIOD output level selected as low active 1: TRCIOD output level selected as high active R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b4 — b5 CSEL TRC count operation select bit (2) 0: Count continues at compare match with the TRCGRA register 1: Count stops at compare match with the TRCGRA register R/W b6 TCEG0 TRCTRG input edge select bit (3) b7 b6 0 0: Trigger input from the TRCTRG pin disabled 0 1: Rising edge selected 1 0: Falling edge selected 1 1: Both edges selected R/W b7 TCEG1 R/W Address 0131h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol DFCK1 DFCK0 — DFTRG DFD DFC DFB DFA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 DFA TRCIOA pin digital filter function select bit (1) 0: Function is not used 1: Function is used R/W b1 DFB TRCIOB pin digital filter function select bit (1) 0: Function is not used 1: Function is used R/W b2 DFC TRCIOC pin digital filter function select bit (1) 0: Function is not used 1: Function is used R/W b3 DFD TRCIOD pin digital filter function select bit (1) 0: Function is not used 1: Function is used R/W b4 DFTRG TRCTRG pin digital filter function select bit (2) 0: Function is not used 1: Function is used R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 DFCK0 Digital filter function clock select bit (1, 2) b7 b6 0 0: f32 0 1: f8 1 0: f1 1 1: Count source (clock selected by bits TCK0 to TCK2 in the TRCCR1 register) R/W b7 DFCK1 R/W

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 320 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.7.4 Operating Example

Figure 20.17 Operating Example in PWM2 Mode (TRCTRG Trigger Input Disabled) Set to 0 by a program. Set to 0 by a program. TRC register value Count source m+1 n+1 0000h FFFFh p+1 TRCIOB output m: Value set in TRCGRA register n: Value set in TRCGRB register p: Value set in TRCGRC register m n p TSTART bit in TRCMR register Count stops because CSEL bit is set to 1. “L” initial output “H” output at TRCGRC register compare match “L” output at TRCGRB register compare match IMFA bit in TRCSR register Set to 0 by a program.IMFB bit in TRCSR register CSEL bit in TRCCR2 register Set to 1 by a program. IMFC bit in TRCSR register Transfer TRCGRB register TRCGRD register n Next data Transfer n Transfer from buffer register to general register The above applies under the following conditions:

• The TOB bit in the TRCCR1 register is set to 0 (initial level is low, high-level output at compare match with the TRCGRC regi ster, low-level output at compare match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled). Set to 0000h by a program. Previous value is retained whenTSTART bit is set to TSTART bit is set to 0. TRC register is cleared by TRCGRA register compare match p+1 “H” output at TRCGRC register compare match No changeNo change Return to initial output when TSTART bit is set to 0.

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 321 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 20.18 Operating Example in PWM2 Mode (TRCTRG Trigger Input Enabled) Set to 0 by a program. TRC register value Count source m+1 n+1 0000h FFFFh p+1 TRCIOB output m: Value set in TRCGRA register n: Value set in TRCGRB register p: Value set in TRCGRC register m n p TSTART bit in TRCMR register Count stops because CSEL bit is set to 1. “L” initial output “H” output at TRCGRC register compare match IMFA bit in TRCSR register Set to 0 by a program.IMFB bit in TRCSR register CSEL bit in TRCCR2 register IMFC bit in TRCSR register Transfer TRCGRB register TRCGRD register Next data Transfer n Transfer from buffer register to general register The above applies under the following conditions:

• The TOB bit in the TRCCR1 register is set to 0 (initial level is low, high-level output at compare match with the TRCGRC register, low-level output at compare match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input). Set to 0000h by a program. Previous value is retained when TSTART bit is set to 0. TSTART bit is set to 0. TRC register is cleared by TRCGRA register compare match. Return to initial value when TSTART bit is set to TRC register (counter) is cleared by TRCTRG pin trigger input. TRCTRG input Count starts when TSTART bit is set to 1. n+1 p+1 p+1 “L” output at TRCGRB register compare match Inactive level so TRCTRG input is enabled. Active level so TRCTRG input is disabled. Set to 0 by a program. Set to 0 by a program. n Transfer n n Transfer Transfer from buffer register to general register n Set to 1 by a program. Change by a program. Count starts at TRCTRG pin trigger input.

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 322 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 20.19 Operating Example in PWM2 Mode (Duty 0% and Duty 100%)

• TRCGRC register setting value greater than TRCGRA register setting value m n TRC register value p Set to 0 by a program. 0000h IMFB bit in TRCSR register IMFC bit in TRCSR register TSTART bit in TRCMR register TRCIOB output The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial leve l is low, high-level output at compare match with the TRCGRC regi ster, low-level output at compare match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register ar e set to 00b (TRCTRG trigger input disabled). p+1 IMFA bit in TRCSR register “L” initial output No compare match with TRCGRB register, so “H” output continues. “H” output at TRCGRC register compare match m+1
• TRCGRB register setting value greater than TRCGRA register setting value m p TRC register value n 0000h IMFB bit in TRCSR register IMFC bit in TRCSR register TSTART bit in TRCMR register TRCIOB output n+1 IMFA bit in TRCSR register “L” initial output “L” output at TRCGRB register compare match (i.e. no change) No compare match with TRCGRC register, so “L” output continues. m+1 m: Value set in TRCGRA register n: Value set in TRCGRB register p: Value set in TRCGRC register

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 323 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.8 Timer RC Interrupt

Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single TRCIC register (bits IR and ILVL0 to ILVL2) and a single vector. Table 20.15 lists the Registers Associ ated with Timer RC Interrupt and Fi gure 20.20 shows a Block Diagram of Timer RC Interrupt. Figure 20.20 Block Diagram of Timer RC Interrupt Like other maskable interrupts, the timer RC interrupt is controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because a single interrupt source (timer RC interrupt) is generated from multiple interrupt request sources.

• The IR bit in the TRCIC register is set to 1 (interrupt requested) when a bit in the TRCSR register is set to 1 and the corresponding bit in the TRCIER register is also set to 1 (interrupt enabled).
• The IR bit is set to 0 (no interrupt requested) when the bit in the TRCSR register or the corresponding bit in the TRCIER register is set to 0, or both are set to 0. In other words, the interrupt request is not maintained if the IR bit is once set to 1 but the interrupt is not acknowledged.
• If another interrupt source is triggered after the IR bit is set to 1, the IR bit remains set to 1 and does not change.
• If multiple bits in the TRCIER register are set to 1, use the TRCSR register to determine the source of the interrupt request.
• The bits in the TRCSR register are not automatically set to 0 when an interrupt is acknowledged. Set them to 0 within the interrupt routine. Refer to 20.2.5 Timer RC Status Register (TRCSR) , for the procedure for setting these bits to 0. Refer to 20.2.4 Timer RC Interrupt Enable Register (TRCIER), for details of the TRCIER register. Refer to 12.3 Interrupt Control , for details of the TRCIC register and 12.1.5.2 Relocatable Vector Tables , for information on interrupt vectors. Table 20.15 Registers Associat ed with Timer RC Interrupt Timer RC Status Register Timer RC Interrupt Enable Register Timer RC Interrupt Control Register TRCSR TRCIER TRCIC Timer RC interrupt request (IR bit in TRCIC register) IMFA bit IMIEA bit IMFB bit IMIEB bit IMFC bit IMIEC bit IMFD bit IMIED bit OVF bit OVIE bit IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register

1. Timer RC REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 324 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

20.9 Notes on Timer RC

20.9.1 TRC Register

• The following note applies wh en the CCLR bit in the TRCCR1 register is set to 1 (TRC register cleared by compare match with TRCGRA register). When using a program to write a valu e to the TRC register while the TSTART bit in the TRCMR register is set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is set to 0000h. If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the write value will not be written to the TRC register and the TRC register will be set to 0000h.
• Reading from the TRC register immedi ately after writing to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV .W #XXXXh, TRC ;Write JMP.B L1 ;JMP.B instruction L1: MOV .W TRC,DATA ;Read

20.9.2 TRCSR Register

Reading from the TRCSR register immediately after writin g to it can result in the value previous to the write being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions. Program Example MOV .B #XXh, TRCSR ;Write JMP.B L1 ;JMP.B instruction L1: MOV .B TRCSR,DATA ;Read

20.9.3 TRCCR1 Register

To set bits TCK2 to TCK0 in the TRCCR1 register to 111b (fOCO-F), set fOCO-F to the clock frequency higher than the CPU clock frequency.

20.9.4 Count Source Switching

• Stop the count before switching the count source. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
• After switching the count source from fOCO40M to anothe r clock, allow two or more cycles of f1 to elapse after changing the clock setting before stopping fOCO40M. Switching procedure (1) Set the TSTART bit in the TRCMR register to 0 (count stops). (2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register. (3) Wait for two or more cycles of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).

20.9.5 Input Capture Function

• The pulse width of the input capture signal should be set to three cycles or more of the timer RC operation clock (refer to Table 20.1 Timer RC Operating Clocks).
• The value of the TRC register is tr ansferred to the TRCGRj register one or two cycles of the timer RC operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the digital filter function is not used).

20.9.6 TRCMR Regist er in PWM2 Mode

When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 325 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 21. Timer RD Timer RD has two 16-bit timers (timer RD0 and timer RD1).

21.1 Introduction

Timer RDi (i = 0 or 1) has four I/O pins. Timer RD uses either f1 or fOCO40M as its operating clock. Table 21.1 lists the Timer RD Operating Clocks. Figure 21.1 shows the Timer RD Block Diagram, and Table 21.2 lists the Timer RD Pin Configuration. Timer RD supports the following five modes:

• Timer mode - Input capture function The counter value is transf erred to a register with an external signal as the trigger. - Output compare function A match between the valu es of a counter and a register is detected. (Pin output can be changed at detection.) The following four modes use the output compare function:
• PWM mode Pulse of any width are continuously.
• Reset synchronous PWM mode Three-phase waveforms (6) without sawtooth wave modulation and dead time are output.
• Complementary PWM mode Three-phase waveforms (6) with triangular wave modulation and dead time are output.
• PWM3 mode PWM waveforms (2) with a fixed period are output. For the input capture function, the output compare function, and in PWM mode, timer RD0 and timer RD1 have the equivalent functions, and functions or modes can be se lected individu ally for each pin. Al so, a combination of these functions and modes can be used in timer RDi. In reset synchronous PWM mode, complementary PWM mo de, and PWM3 mode, a waveform is output with a combination of counters and registers in timer RD0 and timer RD1. Table 21.1 Timer RD Operating Clocks Condition Timer RD Operating Clock The count source is f1, f2, f4, f8, f32, fC2, or TRDCLK input. (Bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to 000b to 101b.) The count source is fOCO40M. (Bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to 110b.) fOCO40M

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 326 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 21.1 Timer RD Block Diagram Table 21.2 Timer RD Pin Configuration Pin Name Assigned Pin I/O Function TRDIOA0/TRDCLK P6_0 or P10_0 I/O Function varies according to the mode. Refer to descriptions of individual modes for details. TRDIOB0 P6_1 or P10_1 I/O TRDIOC0 P6_2 or P10_2 I/O TRDIOD0 P6_3 or P10_3 I/O TRDIOA1 P6_4 or P10_4 I/O TRDIOB1 P6_5 or P10_5 I/O TRDIOC1 P6_6 or P10_6 I/O TRDIOD1 P6_7 or P10_7 I/O TRDi register Data bus TRDGRAi register TRDGRBi register TRDGRCi register TRDGRDi register TRDCRi register TRDIORAi register TRDIORCi register TRDSRi register TRDIERi register TRDPOCRi register TRDECR register TRDADCR register TRDSTR register TRDMR register TRDPMR register TRDFCR register TRDOER1 register Timer RD control circuit INT0 TRDIOA0/TRDCLK (1) TRDIOB0 (1) TRDIOC0 (1) TRDIOD0 (1) TRDIOB1 (2) TRDIOC1 (2) TRDIOD1 (2) TRDIOA1 (2) Count source select circuit f1, f2, f4, f8, f32, fC2 fOCO40M Timer RD0 interrupt request Timer RD1 interrupt request A/D trigger Timer RDi i = 0 or 1 TRDDFi register TRDOER2 register TRDOCR register Notes 1: The TRDPSR0 register is used to select which pin is assigned. 2: The TRDPSR1 register is used to select which pin is assigned.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 327 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.2 Common Items for Multiple Modes

21.2.1 Count Sources

The count source selection method is the same in all m odes. However, the external clock cannot be selected in PWM3 mode. i = 0 or 1 Note: 1. The count source fOCO40M can be used with VCC = 3.0 to 5.5 V. Figure 21.2 Count Source Block Diagram The pulse width of the external clock input to the TRDC LK pin should be set to three or more cycles of the timer RD operating clock. (See Table 21.1 Timer RD Operating Clocks.) To select fOCO40M or fOCO-F as the count source, se t the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on) before setting bits TCK2 to TCK0 in the TRDCRi register (i = 0 or 1) to 110b (fOCO40M). Table 21.3 Count Source Selection Count Source Selection f1, f2, f4, f8, f32 The count source is selected by bits TCK0 to TCK2 in the TRDCRi register. fOCO40M (1) The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on). Bits TCK2 to TCK0 in the TRDCRi register is set to 110b (fOCO40M). fC2 Bits TCK2 to TCK0 in the TRDCRi regist er is set to 101b (TRDCLKi input or fC2) The ITCLKi bit in the TRDECR register is set to 1 (fC2) External signal input to TRDCLK pin The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). Bits TCK2 to TCK0 in the TRDCRi register are set to 101b (count source: external clock). The active edge is selected by bits CKEG0 and CKEG1 in the TRDCRi register. The PD2_0 bit in the PD2 register is set to 0 (input mode). TRDCLK/ TRDIOA0 TCK2 to TCK0 TRDi register ITCLK0, ITCLK1: Bits in TRDECR register TCK0 to TCK2, CKEG0, CKEG1: Bits in TRDCRi register STCLK: Bit in TRDFCR register f32 = 001b = 010b = 011b = 000b = 101b = 100b Active edge selection CKEG1 to CKEG0 TRDIOA0 I/O or programmable I/O port Count source STCLK = 0 fOCO40M = 110b ITCLKi = 0 STCLK = 1 ITCLKi = 1 fC2

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 328 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.2.2 Buffer Operation

The TRDGRCi (i = 0 or 1) register can be used as the buffer register of the TRDGRAi register, and the TRDGRDi register can be used as the buffer register of the TRDGRBi register by means of bits BFCi and BFDi in the TRDMR register.

• Buffer register of TRDGRAi: TRDGRCi register
• Buffer register of TRDGRBi: TRDGRDi register Buffer operation depends on the mode. Table 21.4 lists the Buffer Operation in Each Mode. i = 0 or 1 Figure 21.3 Buffer Operation of Input Capture Function Table 21.4 Buffer Operation in Each Mode Function and Mode Transfer Timing Transfer Register Input capture function Input capture sign al input The content of the TRDGRAi (TRDGRBi) register is transferred to the buffer register. Output compare function Compare match between the TRDi register and the TRDGRAi (TRDGRBi) register The content of the buffer register is transferred to the TRDGRAi (TRDGRBi) register. PWM mode Reset synchronous PWM mode Compare match between the TRD0 register and the TRDGRA0 register The content of the buffer register is transferred to the TRDGRAi (TRDGRBi) register. Complementary PWM mode
• Compare match between the TRD0 register and the TRDGRA0 register
• TRD1 register underflow The content of the buffer register is transferred to registers TRDGRB0, TRDGRA1, and TRDGRB1. PWM3 mode Compare match between the TRD0 register and the TRDGRA0 register The content of the buffer register is transferred to registers TRDGRA0, TRDGRB0, TRDGRA1, and TRDGRB1. m Transfer nTRDGRAi register n-1 n+1 TRDIOAi input TRDi register i = 0 or 1 The above applies under the following conditions:
• The BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is used as the buffer register of the TRDGRAi register).
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 100b (input capture at the falling edge). m Transfer TRDGRCi register (buffer) n TRDGRCi register (buffer) TRDGRAi register TRDi TRDIOAi input (input capture signal)

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 329 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 21.4 Buffer Operation of Output Compare Function Perform the following in timer mode (input capture and output compare functions). To use the TRDGRCi (i = 0 or 1) register as the buffer register of the TRDGRAi register:

• Set the IOC3 bit in the TRDIORCi register to 1 (general register or buffer register).
• Set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. To use the TRDGRDi register as the buffer register of the TRDGRBi register:
• Set the IOD3 bit in the TRDIORDi register to 1 (general register or buffer register).
• Set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. For the input capture function, bits IMFC and IMFD in the TRDSRi register are set to 1 at the input edge of the TRDIOCi pin when registers TRDGRCi and TRDGRDi are also used as buffer registers. For the output compare function, in reset synchr onous PWM mode, complementary PWM mode, and PWM3 mode, bits IMFC and IMFD in the TRDSRi register ar e set to 1 by a compare match with the TRDi register when registers TRDGRCi and TRDGRDi are also as buffer registers. mnTRDGRAi register m-1 m+1TRDi register i = 0 or 1 The above applies under the following conditions:
• The BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is used as the buffer register of the TRDGRAi register).
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 001b (low-level output at compare match). n Transfer TRDGRCi register (buffer) m TRDIOAi output TRDGRCi register (buffer) TRDGRAi register Comparator TRDi Compare match signal

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 330 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.2.3 Synchronous Operation

The TRD1 register is synchronized with the TRD0 register.

• Synchronous preset When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both the TRD0 and TRD1 registers after writing to the TRDi register.
• Synchronous clear When the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register are set to 011b (synchronous clear), the TRD0 register is set to 0000h at the same time as the TRD1 register is set to 0000h. Also, when the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register are set to 011b (synchronous clear), the TRD1 register is set to 0000h at the same time as the TRD0 register is set to 0000h. Figure 21.5 Synchronous Operation TRD0 register value TRDIOA0 input n n is set. n writing TRD1 register value n 0000h is set synchronizing with the TRD0 register. 0000h is set by input capture. The above applies under the following conditions:
• The SYNC bit in the TRDMR register is set to 1 (synchronous operation).
• Bits CCLR2 to CCLR0 in the TRDCR0 register are set to 001b (TRD0 register is set to 0000h by input capture). Bits CCLR2 to CCLR0 in the TRDCR1 register are set to 011b (TRD1 register is set to 0000h synchronizing with the TRD0 register).
• Bits IOA2 to IOA0 in the TRDIORA0 register are set to 100b.
• Bits CMD1 to CMD0 in the TRDFCR register are set to 00b. (Input capture at the rising edge of the TRDIOA0 input) The PWM 3 bit in the TRDFCR register is set to 1. n is set.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 331 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.2.4 Pulse Output Forced Cutoff

In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, the TRDIOji (i = 0 or 1, j = either A, B, C, or D) output pin can be forcibly set to a programmable I/O port by the INT0 pin input, and pulse output can be cut off. The pins used for output in the above function or modes can function as the output pin of timer RD when the applicable bit in the TRDOER1 register is set to 0 (timer RD output enabled). When the PTO bit in the TRDOER2 register to 1 (pulse output forced cutoff signal input INT0 enabled), all bits in the TRDOER1 register are set to 1 (timer RD output disabled, TRDIOji output pin functions as a programmable I/O port) after a low-level signal is applied to the INT0 pin. The TRDIOji output pin is set to a programmable I/O port after a low-level signal is applied to the INT0 pin and waiting for one or two cycl es of the timer RD operating clock (refer to Table 21.1 Timer RD Operating Clocks). Set the following to use this function:

• Set the pin status (high impedance, low-level, or high-l evel output) to pulse output forced cutoff by registers P2 and PD2.
• Set the INT0EN bit in the INTEN register to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge).
• Set the PD4_5 bit in the PD4 register to 0 (input mode).
• Set the INT0 digital filter by bits INT0F0 and INT0F1 in the INTF register.
• Set the PTO bit in the TRDOER2 register to 1 (pulse output forced cutoff signal input INT0 enabled). According to the selection of the POL bit in the INT0IC register and change of the INT0 pin input, the IR bit in the INT0IC register is set to 1 (interrupt requested). Refer to 12. Interrupts for details of interrupts.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 332 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 21.6 Pulse Output Forced Cutoff INT0 input PTO bit D S Q EA0 bitEA0 bit write value D S Q EB0 bitEB0 bit write value D S Q EC0 bitEC0 bit write value D S Q ED0 bitED0 bit write value D S Q EA1 bitEA1 bit write value D S Q EB1 bitEB1 bit write value D S Q EC1 bitEC1 bit write value D S Q ED1 bitED1 bit write value PTO: Bit in TRDOER2 register EA0, EB0, EC0, ED0, EA1, EB1, EC1, ED1: Bits in TRDOER1 register TRDIOA0 TRDIOB0 TRDIOC0 TRDIOD0 TRDIOA1 TRDIOB1 TRDIOC1 TRDIOD1 Timer RD output data Port P6_0/P10_0 output data Port P6_0/P10_0 input data Timer RD output data Port P6_1/P10_1 output data Port P6_1/P10_1 input data Timer RD output data Port P6_2/P10_2 output data Port P6_2/P10_2 input data Timer RD output data Port P6_3/P10_3 output data Port P6_3/P10_3 input data Timer RD output data Port P6_4/P10_4 output data Port P6_4/P10_4 input data Timer RD output data Port P6_5/P10_5 output data Port P6_5/P10_5 input data Timer RD output data Port P6_6/P10_6 output data Port P6_6/P10_6 input data Timer RD output data Port P6_7/P10_7 output data Port P6_7/P10_7 input data Port P6_0/P10_0 direction bit Port P6_1/P10_1 direction bit Port P6_2/P10_2 direction bit Port P6_3/P10_3 direction bit Port P6_4/P10_4 direction bit Port P6_5/P10_5 direction bit Port P6_6/P10_6 direction bit Port P6_7/P10_7 direction bit

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 333 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3 Input Capture Function

The input capture function measures the external signal width and period . The content of the TRDi register (counter) is transferred to the TRDGRji register as a trigger of the TRDIOji (i = 0 or 1, j = either A, B, C, or D) pin external signal (input capture). Since this function is enabled with a combination of the TRDIOji pin and TRDGRji register, the input capture function, or any other mode or function, can be selected for each individual pin. The TRDGRA0 register can also select the fOCO128 signal as input-capture trigger input. Figure 21.7 shows a Block Diagram of Input Capture Function, Table 21.5 lists the Input Capture Function Specifications. Figure 21.8 shows an Operating Example of Input Capture Function. Figure 21.7 Block Diagram of Input Capture Function i = 0 or 1 Notes 1: When the BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is used as the buffer register of the TRDGRAi register). 2: When the BFDi bit in the TRDMR register is set to 1 (TRDGRDi register is used as the buffer register of the TRDGRBi register). TRDGRAi register TRDi register Input capture signal TRDGRCi register TRDGRBi register Input capture signal TRDGRDi register TRDIOBi (Note 1) (Note 2) TRDIOCi TRDIODi 3: The trigger input of the TRDGRA0 register can select the TRDIOA0 pin input or fOCO128 signal. TRDIOAi (Note 3) Divided by 128 IOA3 = 0 IOA3 = 1 fOCO fOCO128 Input capture signal Input capture signal Input capture signal Polarity switching Polarity switching Polarity switching Polarity switching

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 334 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group i = 0 or 1, j = either A, B, C, or D Table 21.5 Input Capture Function Specifications Item Specification Count sources f1, f2, f4, f8, f32, fC2, fOCO40M External signal input to the TRDCLK pin (active edge selectable by a program) Count operations Increment Count period When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (free-running operation). 1/fk × 65,536 fk: Frequency of count source Count start condition 1 (count starts) is writte n to the TSTARTi bit in the TRDSTR register. Count stop condition 0 (count stops) is writte n to the TSTARTi bit in the TRDSTR register when the CSELi bit in the TRDSTR register is set to 1. Interrupt request generation timing

• Input capture (active edge of the TRDIOji input or fOCO128 signal edge)
• TRDi register overflows TRDIOA0 pin function Programmable I/O port, inpu t-capture input, or TRDCLK (external clock) input TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 pins function Programmable I/O port, or input-capture input (selectable for each individual pin) INT0 pin function Programmable I/O port or INT0 interrupt input Read from timer The count value can be read by reading the TRDi register. Write to timer • When the SYNC bit in the T RDMR register is set to 0 (timer RD0 and timer RD1 operate independently). Data can be written to the TRDi register.
• When the SYNC bit in the TRDMR register is set to 1 (timer RD0 and timer RD1 operate synchronously). Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi register. Selectable functions • Input-capture input pin selection Either one pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi.
• Input-capture input active edge selection The rising edge, falling edge, or both the rising and falling edges
• Timing for setting the TRDi register to 0000h Overflow or input capture
• Buffer operation (Refer to 21.2.2 Buffer Operation.)
• Synchronous operation (Refer to 21.2.3 Synchronous Operation.)
• Digital filter The TRDIOji input is sampled and the level is determined when the sampled input level match as three times.
• Input-capture trigger selection fOCO128 can be selected for input-capture trigger input of the TRDGRA0 register.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 335 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.1 Module Standby Control Register (MSTCR)

Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any acce ss to the timer RC associated registers (addresses 0170h to 017Fh) is disabled.

21.3.2 Timer RD Control Ex pansion Register (TRDECR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — MSTTRG MSTTRC MSTTRD MSTIIC — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 MSTIIC SSU, I 2C bus standby bit 0: Active 1: Standby (1) R/W b4 MSTTRD Timer RD standby bit 0: Active 1: Standby (2) R/W b5 MSTTRC Timer RC standby bit 0: Active 1: Standby (3) R/W b6 MSTTRG Timer RG standby bit 0: Active 1: Standby (4) R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — Address 0135h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ITCLK1 — — — ITCLK0 — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 336 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.3 Timer RD Start Register (T RDSTR) for Input Capture Function

Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1 TRDSTR Register for Notes on Timer RD.

21.3.4 Timer RD Mode Register (TRDMR) for Input Capture Function

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — CSEL1 CSEL0 TSTART1 TSTART0 A f t e r R e s e t 11111100 Bit Symbol Bit Name Function R/W b0 TSTART0 TRD0 count start flag 0: Count stops 1: Count starts R/W b1 TSTART1 TRD1 count start flag R/W b2 CSEL0 TRD0 count operation select bit Set to 1 for the input capture function. R/W b3 CSEL1 TRD1 count operation select bit R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — b6 — b7 — Address 0138h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BFD1 BFC1 BFD0 BFC0 — — — SYNC A f t e r R e s e t 00001110 Bit Symbol Bit Name Function R/W b0 SYNC Timer RD synchronous bit 0: Registers TRD0 and TRD1 operate independently 1: Registers TRD0 and TRD1 operate synchronously R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b2 — b3 — b4 BFC0 TRDGRC0 register function select bit 0: General register 1: Buffer register of TRDGRA0 register R/W b5 BFD0 TRDGRD0 register function select bit 0: General register 1: Buffer register of TRDGRB0 register R/W b6 BFC1 TRDGRC1 register function select bit 0: General register 1: Buffer register of TRDGRA1 register R/W b7 BFD1 TRDGRD1 register function select bit 0: General register 1: Buffer register of TRDGRB1 register R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 337 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.5 Timer RD PWM Mode Register (TRDPMR) for Input Capture Function

21.3.6 Timer RD Function C ontrol Register (TRDFCR) for Input Capture Function

Notes: 1. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. Address 0139h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — PWMD1 PWMC1 PWMB1 — PWMD0 PWMC0 PWMB0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 PWMB0 PWM mode of TRDIOB0 select bit Set to 0 (timer mode) for the input capture function. R/W b1 PWMC0 PWM mode of TRDIOC0 select bit R/W b2 PWMD0 PWM mode of TRDIOD0 select bit R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b4 PWMB1 PWM mode of TRDIOB1 select bit Set to 0 (timer mode) for the input capture function. R/W b5 PWMC1 PWM mode of TRDIOC1 select bit R/W b6 PWMD1 PWM mode of TRDIOD1 select bit R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — Address 013Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0 A f t e r R e s e t 10000000 Bit Symbol Bit Name Function R/W b0 CMD0 Combination mode select bit (1) Set to 00b (timer mode, PWM mode, or PWM3 mode) for the input capture function. R/W b1 CMD1 R/W b2 OLS0 Normal-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) Disabled for the input capture function. R/W b3 OLS1 Counter-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) R/W b4 ADTRG A/D trigger enable bit (in complementary PWM mode) R/W b5 ADEG A/D trigger edge select bit (in complementary PWM mode) R/W b6 STCLK External clock input select bit 0: External clock input disabled 1: External clock input enabled R/W b7 PWM3 PWM3 mode select bit (2) Set to 1 (other than PWM3 mode) for the input capture function. R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 338 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.7 Timer RD Digital Filter Function Select Re gister i (TRDDFi) (i = 0 or 1) for

Address 013Eh (TRDDF0), 013Fh (TRDDF1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol DFCK1 DFCK0 — — DFD DFC DFB DFA A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 DFA TRDIOA pin digital filter function select bit 0: Function is not used 1: Function is used R/W b1 DFB TRDIOB pin digital filter function select bit R/W b2 DFC TRDIOC pin digital filter function select bit R/W b3 DFD TRDIOD pin digital filter function select bit R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 DFCK0 Clock select bits for digital filter function b7 b6 0 0: f32 0 1: f8 1 0: f1 1 1: Count source (clock selected by bits TCK0 to TCK2 in the TRCCRi register) R/W b7 DFCK1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 339 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.8 Timer RD Control Register i (TRDC Ri) (i = 0 or 1) for Input Capture

Notes: 1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the TRDFCR register is 1 (external clock input enabled). 2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2). 3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to 0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 4. Enabled when the SYNC bit in the TRDMR register is set to 1 (registers TRD0 and TRD1 operate synchronously). Address 0140h (TRDCR0), 0150h (TRDCR1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TCK0 Count source select bit b2 b1 b0 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRDCLK input (1) or fC2 (2) 1 1 0: fOCO40M 1 1 1: Do not set. R/W b1 TCK1 R/W b2 TCK2 R/W b3 CKEG0 External clock edge select bit (3) b4 b3 0 0: Count at the rising edge 0 1: Count at the falling edge 1 0: Count at both edges 1 1: Do not set. R/W b4 CKEG1 R/W b5 CCLR0 TRDi counter clear select bit b7 b6 b5 0 0 0: Clear disabled (free-running operation) 0 0 1: Clear by input capture to the TRDGRAi register 0 1 0: Clear by input capture to the TRDGRBi register 0 1 1: Synchronous clear (clear simultaneously with other timer RDi counter) (4) 1 0 0: Do not set. 1 0 1: Clear by input capture to the TRDGRCi register 1 1 0: Clear by input capture to the TRDGRDi register 1 1 1: Do not set. R/W b6 CCLR1 R/W b7 CCLR2 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 340 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.9 Timer RD I/O Control Re gister Ai (TRDIORAi) (i = 0 or 1) for Input Capture

Notes: 1. To select 1 (TRDGRCi register is used as the buffer regi ster of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. 2. To select 1 (TRDGRDi register is used as the buffer regi ster of the TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. 3. The IOA3 bit is enabled in the TRDIORA0 register only. Set to the IOA3 bit in TRDIORA1 to 1. 4. The IOA3 bit is enabled when the IOA2 bit is set to 1 (input capture function). Address 0141h (TRDIORA0), 0151h (TRDIORA1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l — I O B 2I O B 1I O B 0I O A 3I O A 2I O A 1I O A 0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOA0 TRDGRA control bit b1 b0 0 0: Input capture to the TRDGRAi register at the rising edge 0 1: Input capture to the TRDGRAi register at the falling edge 1 0: Input capture to the TRDGRAi register at both edges 1 1: Do not set. R/W b1 IOA1 R/W b2 IOA2 TRDGRA mode select bit (1) Set to 1 (input capture) for the input capture function. R/W b3 IOA3 Input capture input switch bit (3, 4) 0: fOCO128 signal 1: TRDIOA0 pin input R/W b4 IOB0 TRDGRB control bit b5 b4 0 0: Input capture to the TRDGRBi register at the rising edge 0 1: Input capture to the TRDGRBi register at the falling edge 1 0: Input capture to the TRDGRBi register at both edges 1 1: Do not set. R/W b5 IOB1 R/W b6 IOB2 TRDGRB mode select bit (2) Set to 1 (input capture) for the input capture function. R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 341 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.10 Timer RD I/O Control Re gister Ci (TRDIORCi) (i = 0 or 1) for Input Capture

Notes: 1. To select 1 (TRDGRCi register is used as the buffer regi ster of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. 2. To select 1 (TRDGRDi register is used as the buffer regi ster of the TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. Address 0142h (TRDIORC0), 0152h (TRDIORC1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOC0 TRDGRC control bit b1 b0 0 0: Input capture to the TRDGRCi register at the rising edge 0 1: Input capture to the TRDGRCi register at the falling edge 1 0: Input capture to the TRDGRCi register at both edges 1 1: Do not set. R/W b1 IOC1 R/W b2 IOC2 TRDGRC mode select bit (1) Set to 1 (input capture) for the input capture function. R/W b3 IOC3 TRDGRC register function select bit Set to 1 (general register or buffer register) for the input capture function. R/W b4 IOD0 TRDGRD control bit b5 b4 0 0: Input capture to the TRDGRDi register at the rising edge 0 1: Input capture to the TRDGRDi register at the falling edge 1 0: Input capture to the TRDGRDi register at both edges 1 1: Do not set. R/W b5 IOD1 R/W b6 IOD2 TRDGRD mode select bit (2) Set to 1 (input capture) for the input capture function. R/W b7 IOD3 TRDGRD register function select bit Set to 1 (general register or buffer register) for the input capture function. R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 342 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.11 Timer RD Status Register i (TRDSRi) (i = 0 or 1) for Input Capture Function

Notes: 1. Nothing is assigned to b5 in the TRDSR0 register. If necessary, write 0 to b5. When read, the content is 1. 2. The results of writing to these bits are as follows:

• The bit is set to 0 when it is first read as 1 and then 0 is written to it.
• The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.)
• The bit’s value remains unchanged if 1 is written to it. 3. Edge selected by bits IOj0 and IOj1 (j = A or B) in the TRDIORAi register. 4. Edge selected by bits IOk0 and IOk1 (k = C or D) in the TRDIORCi register. Including when the BFki bit in the TRDMR register is set to 1 (TRDGRki is used as a buffer register) Address 0143h (TRDSR0), 0153h (TRDSR1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — UDF OVF IMFD IMFC IMFB IMFA After Reset 1 1 1 0 0 0 0 0 TRDSR0 register After Reset 1 1 0 0 0 0 0 0 TRDSR1 register Bit Symbol Bit Name Function R/W b0 IMFA Input-capture/compare-match flag A [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1]. TRDSR0 register: fOCO128 signal edge when the IOA3 bit in the TRDIORA0 register is set to 0 (fOCO128 signal). Input edge of TRDIOA0 pin when the IOA3 bit in the TRDIORA0 register is set to 1 (TRDIOA0 input) (3). TRDSR1 register: Input edge of TRDIOA1 pin (3). R/W b1 IMFB Input-capture/compare-match flag B [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] Input edge of TRDIOBi pin (3). R/W b2 IMFC Input-capture/compare-match flag C [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] Input edge of TRDIOCi pin (4). R/W b3 IMFD Input-capture/compare-match flag D [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] Input edge of TRDIODi pin (4). R/W b4 OVF Overflow flag [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register overflows. R/W b5 UDF Underflow flag (1) Disabled for the input capture function. R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b7 —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 343 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.12 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) for Input

21.3.13 Timer RD Counter i (TRDi) (i = 0 or 1) for Input Capture Function

Access the TRDi register in 16-bit units. Do not access it in 8-bit units. Address 0144h (TRDIER0), 0154h (TRDIER1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — OVIE IMIED IMIEC IMIEB IMIEA A f t e r R e s e t 11100000 Bit Symbol Bit Name Function R/W b0 IMIEA Input-capture/compare-match interrupt enable bit A 0: Interrupt (IMIA) by IMFA bit disabled 1: Interrupt (IMIA) by IMFA bit enabled R/W b1 IMIEB Input-capture/compare-match interrupt enable bit B 0: Interrupt (IMIB) by IMFB bit disabled 1: Interrupt (IMIB) by IMFB bit enabled R/W b2 IMIEC Input-capture/compare-match interrupt enable bit C 0: Interrupt (IMIC) by IMFC bit disabled 1: Interrupt (IMIC) by IMFC bit enabled R/W b3 IMIED Input-capture/compare-match interrupt enable bit D 0: Interrupt (IMID) by IMFD bit disabled 1: Interrupt (IMID) by the IMFD bit enabled R/W b4 OVIE Overflow/underflow interrupt enable bit 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b6 — b7 — Address 0147h to 0146h (TRD0), 0157h to 0156h (TRD1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b15 to b0 Counts an count source. Count operation is increment. When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. 0000h to FFFFh R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 344 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.14 Timer RD General Registers Ai , Bi, Ci, and Di (TRDGRAi, TRDGRBi,

TRDGRCi, TRDGRDi) (i = 0 or 1) for Input Capture Function Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The following registers are disabled for the input capture function: TRDOER1, TRDOER2, TRDOCR, TRDPOCR0, and TRDPOCR1. i = 0 or 1, j = either A, B, C, or D BFCi, BFDi: Bits in TRDMR register The pulse width of the input capture signal input to the TRDIOji pin should be set to three or more cycles of the timer RD operating clock (refer to Table 21.1 Timer RD Operating Clocks) when the digital filter is not used (the DFj bit in the TRDDFi register is set to 0). Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0), 014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0), 0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1), 015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 11111111 Bit Function R/W b15 to b0 Refer to Table 21.6 TRDGRji Register Functions for Input Capture Function R/W Table 21.6 TRDGRji Register Functi ons for Input Capture Function Register Setting Register Func tion Input-Capture Input Pin TRDGRAi − General register The value of the TRDi register can be read at input capture. TRDIOAi TRDGRBi TRDIOBi TRDGRCi BFCi = 0 General register The value of the TRDi register can be read at input capture. TRDIOCi TRDGRDi BFDi = 0 TRDIODi TRDGRCi BFCi = 1 Buffer register The value of the TRDi register can be read at input capture. (Refer to

21.2.2 Buffer Operation)

TRDGRDi BFDi = 1 TRDIOBi

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 345 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.15 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0184h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 T RDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit b1 b0 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. R/W b1 TRDIOA0SEL1 R/W b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. R/W b3 TRDIOB0SEL1 R/W b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. R/W b5 TRDIOC0SEL1 R/W b6 TRDIOD0SEL0 TRDIOD0 pin select bit b7 b6 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W b7 TRDIOD0SEL1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 346 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.16 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0185h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA1SEL0 TRDIOA1 pin select bit b1 b0 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. R/W b1 TRDIOA1SEL1 R/W b2 TRDIOB1SEL0 TRDIOB1 pin select bit b3 b2 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. R/W b3 TRDIOB1SEL1 R/W b4 TRDIOC1SEL0 TRDIOC1 pin select bit b5 b4 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. R/W b5 TRDIOC1SEL1 R/W b6 TRDIOD1SEL0 TRDIOD1 pin select bit b7 b6 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W b7 TRDIOD1SEL1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 347 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.17 Operating Example

Figure 21.8 Operating Example of Input Capture Function Set to 0 by a program. Transfer i = 0 or 1 The above applies under the following conditions: Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b. (TRDi register set to 0000h by TRDGRAi register input capture). Bits TCK2 to TCK0 in the TRDCRi register are set to 101b (TRDCLK input selected as the count source). Bits CKEG1 to CKEG0 in the TRDCRi register are set to 01b (count at the falling edge selected as the count source). Bits IOA2 to IOA0 in the TRDIORAi register are set to 101b (input capture at the falling edge of the TRDIOAi input). The BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is used as the buffer register of the TRDGRAi register). TRDi register count value FFFFh 0009h 0006h TSTARTi bit in TRDSTR register 65,536 TRDGRAi register 0000h TRDIOAi input TRDGRCi register IMFA bit in TRDSRi register OVF bit in TRDSRi register 0009h0006h 0006h TRDCLK input count source Transfer

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 348 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.3.18 Digital Filter

The TRDIOji input is sampled and the level is deter mined when the sampled input level matches three times. The digital filter function and sampling clock can be selected using the TRDDFi register. Figure 21.9 shows a Block Diagram of Digital Filter. Figure 21.9 Block Diagram of Digital Filter Clock period selected by bits TCK0 to TCK2 or bits DFCK0 and DFCK1 Sampling clock TRDIOji input signal Input signal through digital filtering If fewer than three matches occur, the matches are recognized as noise and no transmission is performed. Maximum signal transmission delay is five sampling clocks. Three matches occur and a signal change is confirmed. i = 0 or 1, j = either A, B, C, or D ITCLK0, ITCLK1: Bits in TRDECR register TCK0 to TCK2: Bits in TRDCRi register DFCK0, DFCK1 and DFj: Bits in TRDDF register IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register C DQ Latch C DQ Latch C DQ Latch Match detection circuit Edge detection circuit DFj Sampling clock IOA0 to IOA2 IOB0 to IOB2 IOC0 to IOC3 IOD0 to IOD3 TRDIOji input signal C DQ Latch C DQ Latch Timer RD operating clock f1 or fOCO40M =101b =100b =011b =010b =001b f32 TRDCLK f1 =000b DFCK1 to DFCK0 f32 Count source =110bfOCO40M =00b =01b =10b =11b TCK2 to TCK0 ITCLKi=0 ITCLKi=1 fC2

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 349 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4 Output Compare Function

This function detects matches (compare match) between the content of the TRDGRji (j = either A, B, C, or D) register and the content of the TRDi (i = 0 or 1) register . When the content matches, a user-set level is output from the TRDIOji pin. Since this function is enabled with a combination of the TRDIOji pin and TRDGRji register, the output compare function, or any other mode or function, can be selected for each individual pin. Figure 21.10 shows a Block Diagram of Output Compare Function, Table 21.7 lists the Output Compare Function Specifications. Figure 21.11 shows an Operating Example of Output Compare Function. Figure 21.10 Block Diagram of Output Compare Function TRDIOA0 Output control Comparator TRDGRA0 TRD0 TRDIOC0 Output control Comparator TRDGRC0 Compare match signal TRDIOB0 Output control Comparator TRDGRB0 TRDIOD0 Output control Comparator TRDGRD0 Timer RD0 TRDIOA1 Output control Comparator TRDGRA1 TRD1 TRDIOC1 Output control Comparator TRDGRC1 TRDIOB1 Output control Comparator TRDGRB1 TRDIOD1 Output control Comparator TRDGRD1 Timer RD1 Compare match signal Compare match signal Compare match signal Compare match signal Compare match signal Compare match signal Compare match signal IOC3 = 0 in TRDIORC0 register IOC3 = 1 IOD3 = 0 in TRDIORD0 register IOD3 = 1 IOC3 = 0 in TRDIORC1 register IOC3 = 1 IOD3 = 0 in TRDIORD1 register IOD3 = 1

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 350 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group i = 0 or 1, j = either A, B, C, or D Table 21.7 Output Compare Function Specifications Item Specification Count sources f1, f2, f4, f8, f32, fC2, fOCO40M, External signal input to the TRDCLK pin (active edge selectable by a program) Count operations Increment Count period • When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (free-running operation) 1/fk × 65,536 fk: Frequency of count source

• Bits CCLR1 to CCLR0 in the TRDCRi register are set to 01b or 10b (TRDi register is set to 0000h at compare match with the TRDGRji register). Frequency of count source x (n+1) n: Value set in TRDGRji register Waveform output timing Compare match Count start condition 1 (count starts) is written to the TSTARTi bit in the TRDSTR register. Count stop conditions • 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the CSELi bit in the TRDSTR register is set to 1. The output compare output pin holds output level before the count stops.
• When the CSELi bit in the TRDSTR register is set to 0, the count stops at the compare match with the TRDGRAi register. The output compare output pin holds the level after the output changes by the compare match. Interrupt request generation timing
• Compare match (the contents of the TRDi register and the TRDGRji register match.)
• TRDi register overflow TRDIOA0 pin function Programmable I/O port, output-c ompare output, or TRDCLK (external clock) input TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 pins function Programmable I/O port or output-compare output (selectable for each individual pin) INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input Read from timer The count value can be read by reading the TRDi register. Write to timer • When the SYNC bit in the TRDMR r egister is set to 0 (timer RD0 and timer RD1 operate independently). Data can be written to the TRDi register.
• When the SYNC bit in the TRDMR register is set to 1 (timer RD0 and timer RD1 operate synchronously). Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi register. Selectable functions • Output-compare output pin selection Either one or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi.
• Output level selection at the compare match Low-level output, high-level output, or output level inversion
• Initial output level selected Selectable level for the period from the count start to the compare match
• Timing for setting the TRDi register to 0000h Overflow or compare match with the TRDGRAi register
• Buffer operation (Refer to 21.2.2 Buffer Operation.)
• Synchronous operation (Refer to 21.2.3 Synchronous Operation.)
• Changing output pins for registers TRDGRCi and TRDGRDi The TRDGRCi register can be used as output control of the TRDIOAi pin and the TRDGRDi register can be used as output control of the TRDIOBi pin.
• Pulse output forced cutoff signal input (Refer to 21.2.4 Pulse Output Forced Cutoff.)
• Timer RD can be used as the internal timer without output.
• A/D trigger generation

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 351 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.1 Module Standby Control Register (MSTCR)

Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any acce ss to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. Address 0008h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — MSTTRG MSTTRC MSTTRD MSTIIC — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 MSTIIC SSU, I 2C bus standby bit 0: Active 1: Standby (1) R/W b4 MSTTRD Timer RD standby bit 0: Active 1: Standby (2) R/W b5 MSTTRC Timer RC standby bit 0: Active 1: Standby (3) R/W b6 MSTTRG Timer RG standby bit 0: Active 1: Standby (4) R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 352 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.2 Timer RD Control Ex pansion Register (TRDECR)

21.4.3 Timer RD Trigger C ontrol Register (TRDADCR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ITCLK1 — — — ITCLK0 — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W Address 0136h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 ADTRGA0E A/D trigger A0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRA0 R/W b1 ADTRGB0E A/D trigger B0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRB0 R/W b2 ADTRGC0E A/D trigger C0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRC0 R/W b3 ADTRGD0E A/D trigger D0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRD0 R/W b4 ADTRGA1E A/D trigger A1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRA1 R/W b5 ADTRGB1E A/D trigger B1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRB1 R/W b6 ADTRGC1E A/D trigger C1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRC1 R/W b7 ADTRGD1E A/D trigger D1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRD1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 353 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.4 Timer RD Start Register (T RDSTR) for Output Compare Function

Notes: 1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit. 2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit. 3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count stops). 4. When the CSEL1 bit is set to 0 and the compare match si gnal (TRDIOA1) is generated, this bit is set to 0 (count stops). Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1 TRDSTR Register for Notes on Timer RD. Address 0137h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — CSEL1 CSEL0 TSTART1 TSTART0 A f t e r R e s e t 11111100 Bit Symbol Bit Name Function R/W b0 TSTART0 TRD0 count start flag (3) 0: Count stops (1) 1: Count starts R/W b1 TSTART1 TRD1 count start flag (4) 0: Count stops (2) 1: Count starts R/W b2 CSEL0 TRD0 count operation select bit 0: Count stops at compare match with the TRDGRA0 register 1: Count continues after compare match with the TRDGRA0 register R/W b3 CSEL1 TRD1 count operation select bit 0: Count stops at compare match with the TRDGRA1 register 1: Count continues after compare match with the TRDGRA1 register R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — b6 — b7 —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 354 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.5 Timer RD Mode Register (T RDMR) for Output Compare Function

Note: 1. When selecting 0 (change the TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi (i = 0 or 1) register, set the BFji bit in the TRDMR register to 0.

21.4.6 Timer RD PWM Mode Register (TRDPMR) for Output Compare Function

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BFD1 BFC1 BFD0 BFC0 — — — SYNC A f t e r R e s e t 00001110 Bit Symbol Bit Name Function R/W b0 SYNC Timer RD synchronous bit 0: Registers TRD0 and TRD1 operate independently 1: Registers TRD0 and TRD1 operate synchronously R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b2 — b3 — b4 BFC0 TRDGRC0 register function select bit (1) 0: General register 1: Buffer register of TRDGRA0 register R/W b5 BFD0 TRDGRD0 register function select bit (1) 0: General register 1: Buffer register of TRDGRB0 register R/W b6 BFC1 TRDGRC1 register function select bit (1) 0: General register 1: Buffer register of TRDGRA1 register R/W b7 BFD1 TRDGRD1 register function select bit (1) 0: General register 1: Buffer register of TRDGRB1 register R/W Address 0139h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — PWMD1 PWMC1 PWMB1 — PWMD0 PWMC0 PWMB0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 PWMB0 PWM mode of TRDIOB0 select bit Set to 0 (timer mode) for the output compare function. R/W b1 PWMC0 PWM mode of TRDIOC0 select bit R/W b2 PWMD0 PWM mode of TRDIOD0 select bit R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b4 PWMB1 PWM mode of TRDIOB1 select bit Set to 0 (timer mode) for the output compare function. R/W b5 PWMC1 PWM mode of TRDIOC1 select bit R/W b6 PWMD1 PWM mode of TRDIOD1 select bit R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 355 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.7 Timer RD Function Control Regist er (TRDFCR) for Output Compare

Notes: 1. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. Address 013Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0 A f t e r R e s e t 10000000 Bit Symbol Bit Name Function R/W b0 CMD0 Combination mode select bit (1) Set to 00b (timer mode, PWM mode, or PWM3 mode) for the output compare function. R/W b1 CMD1 R/W b2 OLS0 Normal-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) Disabled for the output compare function. R/W b3 OLS1 Counter-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) R/W b4 ADTRG A/D trigger enable bit (in complementary PWM mode) R/W b5 ADEG A/D trigger edge select bit (in complementary PWM mode) R/W b6 STCLK External clock input select bit 0: External clock input disabled 1: External clock input enabled R/W b7 PWM3 PWM3 mode select bit (2) Set to 1 (other than PWM3 mode) for the output compare function. R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 356 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.8 Timer RD Output Master Enable Register 1 (TRDOER1) for Output

21.4.9 Timer RD Output Master Enable Register 2 (TRDOER2) for Output

Note: 1. Refer to 21.2.4 Pulse Output Forced Cutoff. Address 013Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ED1 EC1 EB1 EA1 ED0 EC0 EB0 EA0 A f t e r R e s e t 11111111 Bit Symbol Bit Name Function R/W b0 EA0 TRDIOA0 output disable bit 0: Output enabled 1: Output disabled (TRDIOA0 pin is used as a programmable I/O port) R/W b1 EB0 TRDIOB0 output disable bit 0: Output enabled 1: Output disabled (TRDIOB0 pin is used as a programmable I/O port) R/W b2 EC0 TRDIOC0 output disable bit 0: Output enabled 1: Output disabled (TRDIOC0 pin is used as a programmable I/O port) R/W b3 ED0 TRDIOD0 output disable bit 0: Output enabled 1: Output disabled (TRDIOD0 pin is used as a programmable I/O port) R/W b4 EA1 TRDIOA1 output disable bit 0: Output enabled 1: Output disabled (TRDIOA1 pin is used as a programmable I/O port) R/W b5 EB1 TRDIOB1 output disable bit 0: Output enabled 1: Output disabled (TRDIOB1 pin is used as a programmable I/O port) R/W b6 EC1 TRDIOC1 output disable bit 0: Output enabled 1: Output disabled (TRDIOC1 pin is used as a programmable I/O port) R/W b7 ED1 TRDIOD1 output disable bit 0: Output enabled 1: Output disabled (TRDIOD1 pin is used as a programmable I/O port) R/W Address 013Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 01111111 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b1 — — b2 — — b3 — — b4 — — b5 — — b6 — — b7 PTO INT0 of pulse output forced cutoff signal input enabled bit (1) 0: Pulse output forced cutoff input disabled 1: Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (output disabled) when a low-level signal is applied to the INT0 pin.) R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 357 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.10 Timer RD Output Control Regi ster (TRDOCR) for Output Compare

Write to the TRDOCR register when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). If the pin function is set for waveform output (refer to

7.5 Port Settings), the initial output level is output when

the TRDOCR register is set. Address 013Dh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOA0 TRDIOA0 output level select bit 0: Initial output at low 1: Initial output at high R/W b1 TOB0 TRDIOB0 output level select bit R/W b2 TOC0 TRDIOC0 initial output level select bit 0: Low 1: High R/W b3 TOD0 TRDIOD0 initial output level select bit R/W b4 TOA1 TRDIOA1 initial output level select bit R/W b5 TOB1 TRDIOB1 initial output level select bit R/W b6 TOC1 TRDIOC1 initial output level select bit R/W b7 TOD1 TRDIOD1 initial output level select bit R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 358 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.11 Timer RD Control Register i (TRDCRi ) (i = 0 or 1) for Output Compare

Notes: 1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the TRDFCR register is 1 (external clock input enabled). 2. This setting is enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2). 3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to 0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 4. This setting is enabled when the SYNC bit in the TRDMR re gister is set to 1 (registers TRD0 and TRD1 operate synchronously). Address 0140h (TRDCR0), 0150h (TRDCR1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TCK0 Count source select bit b2 b1 b0 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRDCLK input (1) or fC2 (2) 1 1 0: fOCO40M 1 1 1: Do not set. R/W b1 TCK1 R/W b2 TCK2 R/W b3 CKEG0 External clock edge select bit (3) b4 b3 0 0: Count at the rising edge 0 1: Count at the falling edge 1 0: Count at both edges 1 1: Do not set. R/W b4 CKEG1 R/W b5 CCLR0 TRDi counter clear select bit b7 b6 b5 0 0 0: Clear disabled (free-running operation) 0 0 1: Clear by compare match with the TRDGRAi register 0 1 0: Clear by compare match with the TRDGRBi register 0 1 1: Synchronous clear (clear simultaneously with other timer RDi counter) (4) 1 0 0: Do not set. 1 0 1: Clear by compare match with the TRDGRCi register 1 1 0: Clear by compare match with the TRDGRDi register 1 1 1: Do not set. R/W b6 CCLR1 R/W b7 CCLR2 R/W

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21.4.12 Timer RD I/O Control Register Ai (TRDIORAi) (i = 0 or 1) for Output

Notes: 1. To select 1 (TRDGRCi register is used as the buffer regi ster of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. 2. To select 1 (TRDGRDi register is used as the buffer regi ster of the TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. Address 0141h (TRDIORA0), 0151h (TRDIORA1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l — I O B 2I O B 1I O B 0I O A 3I O A 2I O A 1I O A 0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOA0 TRDGRA control bit b1 b0 0 0: Pin output by compare match is disabled (TRDIOAi pin functions as a programmable I/O port) 0 1: Low-level output at compare match with the TRDGRAi register 1 0: High-level output at compare match with the TRDGRAi register 1 1: Toggle output at compare match with the TRDGRAi register R/W b1 IOA1 R/W b2 IOA2 TRDGRA mode select bit (1) Set to 0 (output compare) for the output compare function. R/W b3 IOA3 Input capture input switch bit Set to 1. R/W b4 IOB0 TRDGRB control bit b5 b4 0 0: Pin output by compare match is disabled (TRDIOBi pin functions as a programmable I/O port) 0 1: Low-level output at compare match with the TRDGRBi register 1 0: High-level output at compare match with the TRDGRBi register 1 1: Toggle output at compare match with the TRDGRBi register R/W b5 IOB1 R/W b6 IOB2 TRDGRB mode select bit (2) Set to 0 (output compare) for the output compare function. R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 360 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.13 Timer RD I/O Control Register Ci (TRDIORCi) (i = 0 or 1) for Output

Notes: 1. To select 1 (TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. 2. To select 1 (TRDGRDi register is used as a buffer register of the TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. Address 0142h (TRDIORC0), 0152h (TRDIORC1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 IOC0 TRDGRC control bit b1 b0 0 0: Pin output by compare match is disabled 0 1: Low-level output at compare match with the TRDGRCi register 1 0: High-level output at compare match with the TRDGRCi register 1 1: Toggle output at compare match with the TRDGRCi register R/W b1 IOC1 R/W b2 IOC2 TRDGRC mode select bit (1) Set to 0 (output compare) for the output compare function. R/W b3 IOC3 TRDGRC register function select bit 0: TRDIOA output register (Refer to 21.4.21 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi.) 1: General register or buffer register R/W b4 IOD0 TRDGRD control bit b5 b4 0 0: Pin output by compare match is disabled 0 1: Low-level output at compare match with the TRDGRDi register 1 0: High-level output at compare match with the TRDGRDi register 1 1: Toggle output at compare match with the TRDGRDi register R/W b5 IOD1 R/W b6 IOD2 TRDGRD mode select bit (2) Set to 0 (output compare) for the output compare function. R/W b7 IOD3 TRDGRD register function select bit 0: TRDIOB output register (Refer to 21.4.21 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi.) 1: General register or buffer register R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 361 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.14 Timer RD Status Register i (TRDSR i) (i = 0 or 1) for Output Compare

Notes: 1. Nothing is assigned to b5 in the TRDSR0 register. If necessary, write 0 to b5. When read, the content is 1. 2. The results of writing to these bits are as follows:

• The bit is set to 0 when it is first read as 1 and then 0 is written to it.
• The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.)
• The bit’s value remains unchanged if 1 is written to it. 3. Including when the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as a buffer register). Address 0143h (TRDSR0), 0153h (TRDSR1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — UDF OVF IMFD IMFC IMFB IMFA After Reset 1 1 1 0 0 0 0 0 TRDSR0 register After Reset 1 1 0 0 0 0 0 0 TRDSR1 register Bit Symbol Bit Name Function R/W b0 IMFA Input-capture/compare-match flag A [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRAi register value. R/W b1 IMFB Input-capture/compare-match flag B [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRBi register value. R/W b2 IMFC Input-capture/compare-match flag C [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRCi register value (3). R/W b3 IMFD Input-capture/compare-match flag D [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRDi register value (3). R/W b4 OVF Overflow flag [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register overflows. R/W b5 UDF Underflow flag (1) This bit is disabled for the output compare function. R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b7 —

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21.4.15 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) for Output

21.4.16 Timer RD Counter i (TRDi) (i = 0 or 1) for Output Compare Function

Access the TRDi register in 16-bit units. Do not access it in 8-bit units. Address 0144h (TRDIER0), 0154h (TRDIER1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — OVIE IMIED IMIEC IMIEB IMIEA A f t e r R e s e t 11100000 Bit Symbol Bit Name Function R/W b0 IMIEA Input-capture/compare-match interrupt enable bit A 0: Interrupt (IMIA) by IMFA bit disabled 1: Interrupt (IMIA) by IMFA bit enabled R/W b1 IMIEB Input-capture/compare-match interrupt enable bit B 0: Interrupt (IMIB) by IMFB bit disabled 1: Interrupt (IMIB) by IMFB bit enabled R/W b2 IMIEC Input-capture/compare-match interrupt enable bit C 0: Interrupt (IMIC) by IMFC bit disabled 1: Interrupt (IMIC) by IMFC bit enabled R/W b3 IMIED Input-capture/compare-match interrupt enable bit D 0: Interrupt (IMID) by IMFD bit disabled 1: Interrupt (IMID) by the IMFD bit enabled R/W b4 OVIE Overflow/underflow interrupt enable bi t 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b6 — b7 — Address 0147h to 0146h (TRD0), 0157h to 0156h (TRD1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b15 to b0 A count source is counted. Count operation is increment. When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. 0000h to FFFFh R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 363 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.17 Timer RD General Registers Ai , Bi, Ci, and Di (TRDGRAi, TRDGRBi,

TRDGRCi, TRDGRDi) (i = 0 or 1) for Output Compare Function Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The following registers are disabled for the output compare function: TRDDF0, TRDDF1, TRDPOCR0, and TRDPOCR1. i = 0 or 1, j = either A, B, C, or D BFji: Bit in TRDMR register IO j3: Bit in TRDIORCi register Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0), 014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0), 0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1), 015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 11111111 Bit Function R/W b15 to b0 Refer to Table 21.8 TRDGRji Register Function for Output Compare Function R/W Table 21.8 TRDGRji Register Function for Output Compare Function Register Setting Register Function Output-Compare Output PinBFji IOj3 TRDGRAi −− General register. Write the compare value. TRDIOAi TRDGRBi TRDIOBi TRDGRCi 0 1 General register. Wr ite the compare value. TRDIOCi TRDGRDi TRDIODi TRDGRCi 1 1 Buffer register. Wr ite the next compare value. (Refer to 21.2.2 Buffer Operation.) TRDIOAi TRDGRDi TRDIOBi TRDGRCi 0 0 TRDIOAi output control (Refer to 21.4.21 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi.) TRDIOAi TRDGRDi TRDIOBi

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 364 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.18 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0184h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 T RDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit b1 b0 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. R/W b1 TRDIOA0SEL1 R/W b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. R/W b3 TRDIOB0SEL1 R/W b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. R/W b5 TRDIOC0SEL1 R/W b6 TRDIOD0SEL0 TRDIOD0 pin select bit b7 b6 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W b7 TRDIOD0SEL1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 365 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.19 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0185h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA1SEL0 TRDIOA1 pin select bit b1 b0 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. R/W b1 TRDIOA1SEL1 R/W b2 TRDIOB1SEL0 TRDIOB1 pin select bit b3 b2 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. R/W b3 TRDIOB1SEL1 R/W b4 TRDIOC1SEL0 TRDIOC1 pin select bit b5 b4 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. R/W b5 TRDIOC1SEL1 R/W b6 TRDIOD1SEL0 TRDIOD1 pin select bit b7 b6 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W b7 TRDIOD1SEL1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 366 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.20 Operating Example

Figure 21.11 Operating Example of Output Compare Function m n p TRDi register value m+1 m+1 TSTARTi bit in TRDSTR register TRDIOAi output IMFA bit in TRDSRi register n+1 TRDIOBi output IMFB bit in TRDSRi register TRDIOCi output IMFC bit in TRDSRi register Initial output “H” “L” output at compare match Set to 0 by a program. Count source i = 0 or 1 M: Value set in TRDGRAi register n: Value set in TRDGRBi register p: Value set in TRDGRCi register The above applies under the following conditions: The CSELi bit in the TRDSTR register is set to 1 (TRDi register count continues after compare match). Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers). Bits EAi, EBi, and ECi in the TRDOER1 register are set to 0 (TRDIOAi, TRDIOBi and TRDIOCi pin output enabled). Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (TRDi register is set to 000h by compare match with the TRDGRAi register). The IOD3 bit in the TRDIORCi register is set to 1 (TRDGRDi register does not control TRDIOBi pin output). m n p m+1 m+1 n+1 P+1 Count stops Count restarts Output level held Output level held Output level held Set to 0 by a program. Set to 0 by a program. “H” output at compare match Output inverted by compare match Initial output “L” Initial output “L” Bits TOAi and TOBi in the TRDOCR register is set to 0 (initial output at low until compare match), the TOCi bit is set to 1 (initial output at high until compare match). Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted by TRDGRAi register compare match). Bits IOB2 to IOB0 in the TRDIORAi register are set to 010b (TRDIOBi high-level output at TRDGRBi register compare match). Bits IOC3 to IOC0 in the TRDIORCi register are set to 1001b (TRDIOCi low-level output at TRDGRCi register compare match).

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 367 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.21 Changing Output Pins in Regist ers TRDGRCi (i = 0 or 1) and TRDGRDi

The TRDGRCi register can be used fo r output control of the TRDIOAi pin, and the TRDGRDi register can be used for output control of the TRDIOBi pin. Therefore, each pin output can be controlled as follows:

• TRDIOAi output is controlled by the values of registers TRDGRAi and TRDGRCi.
• TRDIOBi output is controlled by the values of registers TRDGRBi and TRDGRDi. Figure 21.12 Changing Output Pins in Registers TRDGRCi and TRDGRDi Change output pins in registers TRDGRCi and TRDGRDi as follows:
• Select 0 (change TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi register.
• Set the BFji bit in the TRDMR register to 0 (general register).
• Set different values in registers TRDGRCi and TRDGRA i. Also, set different valu es in registers TRDGRDi and TRDGRBi. TRDIOA0 Output control Comparator TRDGRA0 TRD0 TRDIOC0 Output control Comparator TRDGRC0 Compare match signal TRDIOB0 Output control Comparator TRDGRB0 TRDIOD0 Output control Comparator TRDGRD0 Timer RD0 TRDIOA1 Output control Comparator TRDGRA1 TRD1 TRDIOC1 Output control Comparator TRDGRC1 TRDIOB1 Output control Comparator TRDGRB1 TRDIOD1 Output control Comparator TRDGRD1 Timer RD1 Compare match signal Compare match signal Compare match signal Compare match signal Compare match signal Compare match signal Compare match signal IOC3 = 0 in TRDIORC0 register IOC3 = 1 IOD3 = 0 in TRDIORD0 register IOD3 = 1 IOC3 = 0 in TRDIORC1 register IOC3 = 1 IOD3 = 0 in TRDIORD1 register IOD3 = 1

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 369 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.4.22 A/D Trigger Generation

A compare match signal with registers TRDi (i = 0 or 1) and TRDGRji (j = A, B, C, or D) can be used as the conversion start trigger of the A/D converter. The TRDADCR register is used to select which compare match is used.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 370 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5 PWM Mode

In PWM mode, a PWM waveform is output. Up to three PWM waveforms with the same period can be output by timer RDi (i = 0 or 1). Also, up to six PWM waveforms with the same period can be output by synchronizing timer RD0 and timer RD1. Since this mode functions by a combination of the TRDIOji (i = 0 or 1, j = B, C, or D) pin and TRDGRji register, PWM mode, or any other mode or functio n, can be selected for each individual pin. (However, since the TRDGRAi register is used when using any pin for PWM mode, the TRDGRAi register cannot be used for other modes.) Figure 21.14 shows a Block Diagram of PWM Mode, and Table 21.9 lists the PWM Mode Specifications. Figures 21.15 and 21.16 show Operation Examples in PWM Mode. Figure 21.14 Block Diagram of PWM Mode TRDIOBi Output control TRDGRAi TRDi Compare match signal TRDGRBiTRDIOCi TRDGRCi TRDGRDi TRDIODi (Note 1) (Note 2) i = 0 or 1 Notes: 1. When the BFCi bit in the TRDMR register is set to 1 (TRDGRCi register is used as the buffer register of the TRDGRAi registe r). 2. When the BFDi bit in the TRDMR register is set to 1 (TRDGRDi register is used as the buffer register of the TRDGRBi registe r). Compare match signal Compare match signal Compare match signal Comparator Comparator Comparator Comparator

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 371 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group i = 0 or 1 j = either B, C, or D h = either A, B, C, or D Table 21.9 PWM Mode Specifications Item Specification Count sources f1, f2, f4 , f8, f32, fC2, fOCO40M External signal input to the TRDCLK pin (active edge selectable by a program) Count operations Increment PWM waveform PWM period: 1/fk x (m+1) Active level width: 1/fk x (m-n) Inactive level width: 1/fk x (n+1) fk: Frequency of count source m: Value set in TRDGRAi register n: Value set in TRDGRji register Count start condition 1 (count starts) is writte n to the TSTARTi bit in the TRDSTR register. Count stop conditions • 0 (count stops) is writte n to the TSTARTi bit in the TRDSTR register when the CSELi bit in the TRDSTR register is set to 1. The PWM output pin holds output level before the count stops.

• When the CSELi bit in the TRDSTR register is set to 0, the count stops at the compare match with the TRDGRAi register. The PWM output pin holds the level after the output changes by the compare match. Interrupt request generation timing
• Compare match (the contents of the TRDi register and the TRDGRhi register match.)
• TRDi register overflow TRDIOA0 pin function Programmable I/O port or TRDCLK (external clock) input TRDIOA1 pin function Programmable I/O port TRDIOB0, TRDIOC0, TRDIOD0, TRDIOB1, TRDIOC1, TRDIOD1 pins function Programmable I/O port or pulse output (selectable for each individual pin) INT0 pin function Programmable I/O port, pulse outp ut forced cutoff signal input, or INT0 interrupt input Read from timer The coun t value can be read by reading the TRDi register. Write to timer The value can be written to the TRDi register. Selectable functions • One to three PWM output pins selectable per timer RDi Either one pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi pin.
• Active level selectable for each individual pin.
• Initial output level selectable for each individual pin.
• Synchronous operation (Refer to 21.2.3 Synchronous Operation.)
• Buffer operation (Refer to 21.2.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 21.2.4 Pulse Output Forced Cutoff.)
• A/D trigger generation m+1 n+1 m-n (Active level is low)

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 372 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.1 Module Standby Control Register (MSTCR)

Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any acce ss to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. Address 0008h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — MSTTRG MSTTRC MSTTRD MSTIIC — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 MSTIIC SSU, I 2C bus standby bit 0: Active 1: Standby (1) R/W b4 MSTTRD Timer RD standby bit 0: Active 1: Standby (2) R/W b5 MSTTRC Timer RC standby bit 0: Active 1: Standby (3) R/W b6 MSTTRG Timer RG standby bit 0: Active 1: Standby (4) R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 373 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.2 Timer RD Control Ex pansion Register (TRDECR)

21.5.3 Timer RD Trigger C ontrol Register (TRDADCR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ITCLK1 — — — ITCLK0 — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W Address 0136h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 ADTRGA0E A/D trigger A0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRA0 R/W b1 ADTRGB0E A/D trigger B0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRB0 R/W b2 ADTRGC0E A/D trigger C0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRC0 R/W b3 ADTRGD0E A/D trigger D0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRD0 R/W b4 ADTRGA1E A/D trigger A1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRA1 R/W b5 ADTRGB1E A/D trigger B1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRB1 R/W b6 ADTRGC1E A/D trigger C1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRC1 R/W b7 ADTRGD1E A/D trigger D1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRD1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 374 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.4 Timer RD Start Regist er (TRDSTR) in PWM Mode

Notes: 1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit. 2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit. 3. When the CSEL0 bit is set to 0 and the compare match si gnal (TRDIOA0) is generated, this bit is set to 0 (count stops). 4. When the CSEL1 bit is set to 0 and the compare match si gnal (TRDIOA1) is generated, this bit is set to 0 (count stops). Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1 TRDSTR Register for Notes on Timer RD.

21.5.5 Timer RD Mode Regi ster (TRDMR) in PWM Mode

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — CSEL1 CSEL0 TSTART1 TSTART0 A f t e r R e s e t 11111100 Bit Symbol Bit Name Function R/W b0 TSTART0 TRD0 count start flag (3) 0: Count stops (1) 1: Count starts R/W b1 TSTART1 TRD1 count start flag (4) 0: Count stops (2) 1: Count starts R/W b2 CSEL0 TRD0 count operation select bit 0: Count stops at compare match with the TRDGRA0 register 1: Count continues after compare match with the TRDGRA0 register R/W b3 CSEL1 TRD1 count operation select bit 0: Count stops at compare match with the TRDGRA1 register 1: Count continues after compare match with the TRDGRA1 register R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — b6 — b7 — Address 0138h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BFD1 BFC1 BFD0 BFC0 — — — SYNC A f t e r R e s e t 00001110 Bit Symbol Bit Name Function R/W b0 SYNC Timer RD synchronous bit 0: Registers TRD0 and TRD1 operate independently 1: Registers TRD0 and TRD1 operate synchronously R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b2 — b3 — b4 BFC0 TRDGRC0 register function select bit 0: General register 1: Buffer register of TRDGRA0 register R/W b5 BFD0 TRDGRD0 register function select bit 0: General register 1: Buffer register of TRDGRB0 register R/W b6 BFC1 TRDGRC1 register function select bit 0: General register 1: Buffer register of TRDGRA1 register R/W b7 BFD1 TRDGRD1 register function select bit 0: General register 1: Buffer register of TRDGRB1 register R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 375 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.6 Timer RD PWM Mode Regi ster (TRDPMR) in PWM Mode

21.5.7 Timer RD Function Control Register (TRDFCR) in PWM Mode

Notes: 1. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. Address 0139h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — PWMD1 PWMC1 PWMB1 — PWMD0 PWMC0 PWMB0 A f t e r R e s e t 10001000 Bit Symbol Bit Name Function R/W b0 PWMB0 PWM mode of TRDIOB0 select bit 0: Timer mode 1: PWM mode R/W b1 PWMC0 PWM mode of TRDIOC0 select bit R/W b2 PWMD0 PWM mode of TRDIOD0 select bit R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b4 PWMB1 PWM mode of TRDIOB1 select bit 0: Timer mode 1: PWM mode R/W b5 PWMC1 PWM mode of TRDIOC1 select bit R/W b6 PWMD1 PWM mode of TRDIOD1 select bit R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — Address 013Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0 A f t e r R e s e t 10000000 Bit Symbol Bit Name Function R/W b0 CMD0 Combination mode select bit (1) Set to 00b (timer mode, PWM mode, or PWM3 mode) in PWM mode. R/W b1 CMD1 R/W b2 OLS0 Normal-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) Disabled in PWM mode. R/W b3 OLS1 Counter-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) R/W b4 ADTRG A/D trigger enable bit (in complementary PWM mode) R/W b5 ADEG A/D trigger edge select bit (in complementary PWM mode) R/W b6 STCLK External clock input select bit 0: External clock input disabled 1: External clock input enabled R/W b7 PWM3 PWM3 mode select bit (2) Set to 1 (other than PWM3 mode) in PWM mode. R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 376 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.8 Timer RD Output Master Enable Register 1 (TRDOER1) in PWM Mode

21.5.9 Timer RD Output Master Enable Register 2 (TRDOER2) in PWM Mode

Note: 1. Refer to 21.2.4 Pulse Output Forced Cutoff. Address 013Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ED1 EC1 EB1 EA1 ED0 EC0 EB0 EA0 A f t e r R e s e t 11111111 Bit Symbol Bit Name Function R/W b0 EA0 TRDIOA0 output disable bit Set to 1 (TRDIOA0 pin is used as a programmable I/O port) in PWM mode. R/W b1 EB0 TRDIOB0 output disable bit 0: Output enabled 1: Output disabled (TRDIOB0 pin is used as a programmable I/O port) R/W b2 EC0 TRDIOC0 output disable bit 0: Output enabled 1: Output disabled (TRDIOC0 pin is used as a programmable I/O port) R/W b3 ED0 TRDIOD0 output disable bit 0: Output enabled 1: Output disabled (TRDIOD0 pin is used as a programmable I/O port) R/W b4 EA1 TRDIOA1 output disable bit Set to 1 (TRDIOA1 pin is used as a programmable I/O port) in PWM mode. R/W b5 EB1 TRDIOB1 output disable bit 0: Output enabled 1: Output disabled (TRDIOB1 pin is used as a programmable I/O port) R/W b6 EC1 TRDIOC1 output disable bit 0: Output enabled 1: Output disabled (TRDIOC1 pin is used as a programmable I/O port) R/W b7 ED1 TRDIOD1 output disable bit 0: Output enabled 1: Output disabled (TRDIOD1 pin is used as a programmable I/O port) R/W Address 013Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 01111111 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b1 — — b2 — — b3 — — b4 — — b5 — — b6 — — b7 PTO INT0 of pulse output forced cutoff signal input enabled bit (1) 0: Pulse output forced cutoff input disabled 1: Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (output disabled) when a low-level signal is applied to the INT0 pin.) R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 377 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.10 Timer RD Output Control Register (TRDOCR) in PWM Mode

Note: 1. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRDOCR register is set. Write to the TRDOCR register when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops).

21.5.11 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in PWM Mode

Notes: 1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the TRDFCR register is 1 (external clock input enabled). 2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2). 3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to 0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). Address 013Dh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOA0 TRDIOA0 output level select bit Set to 0 (output enabled) in PWM mode. R/W b1 TOB0 TRDIOB0 output level select bit (1) 0: Initial output is inactive level 1: Initial output is active level R/W b2 TOC0 TRDIOC0 initial output level select bit (1) R/W b3 TOD0 TRDIOD0 initial output level select bit (1) R/W b4 TOA1 TRDIOA1 initial output level select bit Set this bit to 0 (output enabled) in PWM mode. R/W b5 TOB1 TRDIOB1 initial output level select bit (1) 0: Inactive level 1: Active level R/W b6 TOC1 TRDIOC1 initial output level select bit (1) R/W b7 TOD1 TRDIOD1 initial output level select bit (1) R/W Address 0140h (TRDCR0), 0150h (TRDCR1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TCK0 Count source select bit b2 b1 b0 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRDCLK input (1) or fC2 (2) 1 1 0: fOCO40M 1 1 1: Do not set. R/W b1 TCK1 R/W b2 TCK2 R/W b3 CKEG0 External clock edge select bit (3) b4 b3 0 0: Count at the rising edge 0 1: Count at the falling edge 1 0: Count at both edges 1 1: Do not set. R/W b4 CKEG1 R/W b5 CCLR0 TRDi counter clear select bit Set to 001b (TRDi register cleared by compare match with TRDGRAi register) in PWM mode. R/W b6 CCLR1 R/W b7 CCLR2 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 378 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.12 Timer RD Status Register i (T RDSRi) (i = 0 or 1) in PWM Mode

Notes: 1. Nothing is assigned to b5 in the TRDSR0 register. If necessary, write 0 to b5. When read, the content is 1. 2. The results of writing to these bits are as follows:

• The bit is set to 0 when it is first read as 1 and then 0 is written to it.
• The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.)
• The bit’s value remains unchanged if 1 is written to it. 3. Including when the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as a buffer register). Address 0143h (TRDSR0), 0153h (TRDSR1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — UDF OVF IMFD IMFC IMFB IMFA After Reset 1 1 1 0 0 0 0 0 TRDSR0 register After Reset 1 1 0 0 0 0 0 0 TRDSR1 register Bit Symbol Bit Name Function R/W b0 IMFA Input-capture/compare-match flag A [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRAi register value. R/W b1 IMFB Input-capture/compare-match flag B [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRBi register value. R/W b2 IMFC Input-capture/compare-match flag C [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRCi register value. (3) R/W b3 IMFD Input-capture/compare-match flag D [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRDi register value. (3) R/W b4 OVF Overflow flag [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register overflows. R/W b5 UDF Underflow flag (1) This bit is disabled in PWM Mode. R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b7 —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 379 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.13 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in PWM Mode

21.5.14 Timer RD PWM Mode Output Level Control Register i (TRDPOCRi) (i = 0 or

1) in PWM Mode Address 0144h (TRDIER0), 0154h (TRDIER1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — OVIE IMIED IMIEC IMIEB IMIEA A f t e r R e s e t 11100000 Bit Symbol Bit Name Function R/W b0 IMIEA Input-capture/compare-match interrupt enable bit A 0: Interrupt (IMIA) by IMFA bit disabled 1: Interrupt (IMIA) by IMFA bit enabled R/W b1 IMIEB Input-capture/compare-match interrupt enable bit B 0: Interrupt (IMIB) by IMFB bit disabled 1: Interrupt (IMIB) by IMFB bit enabled R/W b2 IMIEC Input-capture/compare-match interrupt enable bit C 0: Interrupt (IMIC) by IMFC bit disabled 1: Interrupt (IMIC) by IMFC bit enabled R/W b3 IMIED Input-capture/compare-match interrupt enable bit D 0: Interrupt (IMID) by IMFD bit disabled 1: Interrupt (IMID) by IMFD bit enabled R/W b4 OVIE Overflow/underflow interrupt enable bi t 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b6 — b7 — Address 0145h (TRDPOCR0), 0155h (TRDPOCR1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — — POLD POLC POLB A f t e r R e s e t 11111000 Bit Symbol Bit Name Function R/W b0 POLB PWM mode output level control bit B 0: TRDIOBi output level is selected as low active 1: TRDIOBi output level is selected as high active R/W b1 POLC PWM mode output level control bit C 0: TRDIOCi output level is selected as low active 1: TRDIOCi output level is selected as high active R/W b2 POLD PWM mode output level control bit D 0: TRDIODi output level is selected as low active 1: TRDIODi output level is selected as high active R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b4 — b5 — b6 — b7 —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 380 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.15 Timer RD Counter i (TRDi) (i = 0 or 1) in PWM Mode

Access the TRDi register in 16-bit units. Do not access it in 8-bit units. Address 0147h to 0146h (TRD0), 0157h to 0156h (TRD1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b15 to b0 A count source is counted. Count operation is increment. When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. 0000h to FFFFh R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 381 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.16 Timer RD General Registers Ai , Bi, Ci, and Di (TRDGRAi, TRDGRBi,

TRDGRCi, TRDGRDi) (i = 0 or 1) in PWM Mode Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The following registers are disabled in PWM mode: TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDIORA1, and TRDIORC1. i = 0 or 1 BFCi, BFDi: Bits in TRDMR register Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0), 014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0), 0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1), 015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 11111111 Bit Function R/W b15 to b0 Refer to Table 21.10 TRDGRji Register Functions in PWM Mode R/W Table 21.10 TRDGRji Register Functions in PWM Mode Register Setting Register Function PWM Output Pin TRDGRAi − General register. Set the PWM period − TRDGRBi − General register. Set the changing point of PWM output TRDIOBi TRDGRCi BFCi = 0 General register. Set th e changing point of PWM output TRDIOCi TRDGRDi BFDi = 0 TRDIODi TRDGRCi BFCi = 1 Buffer register. Set the next PWM period (Refer to 21.2.2 Buffer Operation.) TRDGRDi BFDi = 1 Buffer register. Set the changing point of the next PWM output (Refer to 21.2.2 Buffer Operation.) TRDIOBi

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 382 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.17 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0184h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 T RDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit b1 b0 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. R/W b1 TRDIOA0SEL1 R/W b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. R/W b3 TRDIOB0SEL1 R/W b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. R/W b5 TRDIOC0SEL1 R/W b6 TRDIOD0SEL0 TRDIOD0 pin select bit b7 b6 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W b7 TRDIOD0SEL1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 383 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.18 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0185h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA1SEL0 TRDIOA1 pin select bit b1 b0 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. R/W b1 TRDIOA1SEL1 R/W b2 TRDIOB1SEL0 TRDIOB1 pin select bit b3 b2 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. R/W b3 TRDIOB1SEL1 R/W b4 TRDIOC1SEL0 TRDIOC1 pin select bit b5 b4 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. R/W b5 TRDIOC1SEL1 R/W b6 TRDIOD1SEL0 TRDIOD1 pin select bit b7 b6 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W b7 TRDIOD1SEL1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 384 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.19 Operating Example

Figure 21.15 Operating Example in PWM Mode m n p TRDi register value Count source m+1 n+1 TRDIOCi output q m-n p+1 m-p m-qq+1 TRDIODi output m: Value set in TRDGRAi register n: Value set in TRDGRBi register p: Value set in TRDGRCi register q: Value set in TRDGRDi register Inactive level “L” Active level “H” Inactive level “H” Active level “L” Set to 0 by a program. Set to 0 by a program. Set to 0 by a program. TRDIOBi output IMFA bit in TRDSRi register IMFB bit in TRDSRi register IMFC bit in TRDSRi register IMFD bit in TRDSRi register i = 0 or 1 Set to 0 by a program. The above applies under the following conditions: Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers). Bits EBi, ECi and EDi in the TRDOER1 register are set to 0 (TRDIOBi, TRDIOCi and TRDIODi pin output enabled). Bits TOBi and TOCi in the TRDOCR register are set to 0 (i nactive level), the TODi bit is set to 1 (active level). The POLB bit in the TRDPOCRi register is set to 1 (active level is high), bits POLC and POLD are set to 0 (active level is low ). Initial output “L” until compare match Initial output “H” utnil compare match Initial output “L” until compare match

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 385 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 21.16 Operating Example in PWM Mode (Duty 0%, Duty 100%) m p q TRDi register value n m: Value set in TRDGRAi register Set to 0 by a program. Rewrite by a program. 0000h q Duty 0% TRDGRBi register IMFA bit in TRDSRi register IMFB bit in TRDSRi register TSTARTi bit in TRDSTR register TRDIOBi output p (p>m)n Since no compare match with TRDGRBi register is generated, “L” is not applied to TRDIOBi output. m p TRDi register value n 0000h TRDGRBi register IMFA bit in TRDSRi register IMFB bit in TRDSRi register TSTARTi bit in TRDSTR register TRDIOBi output pn “L” is applied to TRDIOBi output at compare match with TRDGRBi register (no change). m i = 0 or 1 The above applies under the following conditions: The EBi bit in the TRDOER1 register is set to 0 (TRDIOBi pin output enabled). The POLB bit in the TRDPOCRi register is set to 0 (active level is low). Rewrite by a program. Set to 0 by a program. Set to 0 by a program. When compare matches with registers TRDGRAi and TRDGRBi are generated simultaneously, compare match with TRDGRBi register has priority. “L” is applied to TRDIOBi output (no change). Duty 100% Set to 0 by a program.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 386 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.5.20 A/D Trigger Generation

A compare match signal with registers TRDi (i = 0 or 1) and TRDGRji (j = A, B, C, or D) can be used as the conversion start trigger of the A/D converter. The TRDADCR register is used to select which compare match is used.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 387 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6 Reset Synchronous PWM Mode

In this mode, three normal-phases and three counter-phases of the PWM waveform are output with the same period (three-phase, sawtooth wave modulation, and no dead time). Figure 21.17 shows a Block Diagram of Reset Sync hronous PWM Mode, and Table 21.11 lists the Reset Synchronous PWM Mode Specifications. Figure 21.18 shows an Operating Example in Reset Synchronous PWM Mode. Refer to Figure 21.16 Operating Example in PWM Mode (Duty 0%, Duty 100%) for an operating example in PWM Mode with duty 0% and duty 100%. Figure 21.17 Block Diagram of Reset Synchronous PWM Mode Period TRDIOC0 TRDIOB0 TRDIOD0 TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1 PWM1 PWM2 PWM3 Waveform control TRDGRB0 register TRDGRA1 register TRDGRB1 register Normal-phase Counter-phase TRDGRA0 register TRDGRD0 register TRDGRC1 register TRDGRD1 register TRDGRC0 register Buffer (1) Normal-phase Counter-phase Normal-phase Counter-phase Note: 1.When bits BFC0, BFD0, BFC1, and BFD1 in the TRDMR register are set to 1 (buffer register).

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 388 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group j = either A, B, C, or D Table 21.11 Reset Synchronous PWM Mode Specifications Item Specification Count sources f1, f2, f4, f8, f32, fC2, fOCO40M External signal input to the TRDCLK pin (active edge selectable by a program) Count operations The TRD0 register is in cremented (TRD1 register is not used). PWM waveform PWM period : 1/fk × (m+1) Active level width of normal-phase : 1/fk × (m-n) Active level width of counter-phase: 1/fk × (n+1) fk: Frequency of count source m: Value set in TRDGRA0 register n: Value set in TRDGRB0 register (PWM1 output), Value set in TRDGRA1 register (PWM2 output), Value set in TRDGRB1 register (PWM3 output) Count start condition 1 (count st arts) is written to the TSTART0 bit in the TRDSTR register. Count stop conditions • 0 (count stops) is writt en to the TSTART0 bit in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1. The PWM output pin holds the output level before the count stops

• When the CSEL0 bit in the TRDSTR register is set to 0, the count stops at the compare match with the TRDGRA0 register. The PWM output pin holds the level after the output changes by the compare match. Interrupt request generation timing
• Compare match (the content of the TRD0 register matches the contents of registers TRDGRj0, TRDGRA1, and TRDGRB1).
• TRD0 register overflow TRDIOA0 pin function Programmable I/O po rt or TRDCLK (external clock) input TRDIOB0 pin function PWM1 output normal-phase output TRDIOD0 pin function PWM1 output counter-phase output TRDIOA1 pin function PWM2 output normal-phase output TRDIOC1 pin function PWM2 output counter-phase output TRDIOB1 pin function PWM3 output normal-phase output TRDIOD1 pin function PWM3 output counter-phase output TRDIOC0 pin function Output inverted every PWM period INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input Read from timer The count value can be read by reading the TRD0 register. Write to timer The value can be written to the TRD0 register. Selectable functions • The normal-phase and co unter-phase active level and initial output level can be selected individually.
• Buffer operation (Refer to 21.2.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 21.2.4 Pulse Output Forced Cutoff.)
• A/D trigger generation m+1 Normal-phase n+1 (Active level is low) Counter-phase m-n

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 389 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.1 Module Standby Control Register (MSTCR)

Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any acce ss to the timer RC associated registers (addresses 0170h to 017Fh) is disabled. Address 0008h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — MSTTRG MSTTRC MSTTRD MSTIIC — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 MSTIIC SSU, I 2C bus standby bit 0: Active 1: Standby (1) R/W b4 MSTTRD Timer RD standby bit 0: Active 1: Standby (2) R/W b5 MSTTRC Timer RC standby bit 0: Active 1: Standby (3) R/W b6 MSTTRG Timer RG standby bit 0: Active 1: Standby (4) R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 390 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.2 Timer RD Control Ex pansion Register (TRDECR)

21.6.3 Timer RD Trigger C ontrol Register (TRDADCR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ITCLK1 — — — ITCLK0 — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W Address 0136h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 ADTRGA0E A/D trigger A0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRA0 R/W b1 ADTRGB0E A/D trigger B0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRB0 R/W b2 ADTRGC0E A/D trigger C0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRC0 R/W b3 ADTRGD0E A/D trigger D0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRD0 R/W b4 ADTRGA1E A/D trigger A1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRA1 R/W b5 ADTRGB1E A/D trigger B1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRB1 R/W b6 ADTRGC1E A/D trigger C1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRC1 R/W b7 ADTRGD1E A/D trigger D1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRD1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 391 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.4 Timer RD Start Register (TRD STR) in Reset Synchronous PWM Mode

Notes: 1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit. 2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit. 3. When the CSEL0 bit is set to 0 and the compare match si gnal (TRDIOA0) is generated, this bit is set to 0 (count stops). 4. When the CSEL1 bit is set to 0 and the compare match si gnal (TRDIOA1) is generated, this bit is set to 0 (count stops). Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1 TRDSTR Register for Notes on Timer RD.

21.6.5 Timer RD Mode Re gister (TRDMR) in Reset Synchronous PWM Mode

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — CSEL1 CSEL0 TSTART1 TSTART0 A f t e r R e s e t 11111100 Bit Symbol Bit Name Function R/W b0 TSTART0 TRD0 count start flag (3) 0: Count stops (1) 1: Count starts R/W b1 TSTART1 TRD1 count start flag (4) 0: Count stops (2) 1: Count starts R/W b2 CSEL0 TRD0 count operation select bit 0: Count stops at compare match with the TRDGRA0 register 1: Count continues after compare match with the TRDGRA0 register R/W b3 CSEL1 TRD1 count operation select bit 0: Count stops at compare match with the TRDGRA1 register 1: Count continues after compare match with the TRDGRA1 register R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — b6 — b7 — Address 0138h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BFD1 BFC1 BFD0 BFC0 — — — SYNC A f t e r R e s e t 00001110 Bit Symbol Bit Name Function R/W b0 SYNC Timer RD synchronous bit Set to 0 (registers TRD and TRD1 operate independently) in reset synchronous PWM mode. R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b2 — b3 — b4 BFC0 TRDGRC0 register function select bit 0: General register 1: Buffer register of TRDGRA0 register R/W b5 BFD0 TRDGRD0 register function select bit 0: General register 1: Buffer register of TRDGRB0 register R/W b6 BFC1 TRDGRC1 register function select bit 0: General register 1: Buffer register of TRDGRA1 register R/W b7 BFD1 TRDGRD1 register function select bit 0: General register 1: Buffer register of TRDGRB1 register R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 392 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.6 Timer RD Function Control Regi ster (TRDFCR) in Reset Synchronous

Notes: 1. When bits CMD1 to CMD0 are set to 01b, 10b, or 11b, the MCU enters reset synchronous PWM mode or complementary PWM mode in spite of the setting of the TRDPMR register. 2. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits are set to 0 (count stops). 3. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. Address 013Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0 A f t e r R e s e t 10000000 Bit Symbol Bit Name Function R/W b0 CMD0 Combination mode select bit (1, 2) Set to 01b (reset synchronous PWM mode) in reset synchronous PWM mode. R/W b1 CMD1 R/W b2 OLS0 Normal-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) 0: Initial output at high, active level is low 1: Initial output at low, active level is high R/W b3 OLS1 Counter-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) R/W b4 ADTRG A/D trigger enable bit (in complementary PWM mode) Disabled in reset synchronous PWM mode. R/W b5 ADEG A/D trigger edge select bit (in complementary PWM mode) R/W b6 STCLK External clock input select bit 0: External clock input disabled 1: External clock input enabled R/W b7 PWM3 PWM3 mode select bit (3) Disabled in reset synchronous PWM mode. R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 393 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.7 Timer RD Output Master Enable Register 1 (TRDOER1) in Reset

21.6.8 Timer RD Output Master Enable Register 2 (TRDOER2) in Reset

Note: 1. Refer to 21.2.4 Pulse Output Forced Cutoff. Address 013Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ED1 EC1 EB1 EA1 ED0 EC0 EB0 EA0 A f t e r R e s e t 11111111 Bit Symbol Bit Name Function R/W b0 EA0 TRDIOA0 output disable bit Set to 1 (TRDIOA0 pin is used as a programmable I/O port) in reset synchronous PWM mode. R/W b1 EB0 TRDIOB0 output disable bit 0: Output enabled 1: Output disabled (TRDIOB0 pin is used as a programmable I/O port) R/W b2 EC0 TRDIOC0 output disable bit 0: Output enabled 1: Output disabled (TRDIOC0 pin is used as a programmable I/O port) R/W b3 ED0 TRDIOD0 output disable bit 0: Output enabled 1: Output disabled (TRDIOD0 pin is used as a programmable I/O port) R/W b4 EA1 TRDIOA1 output disable bit 0: Output enabled 1: Output disabled (TRDIOA1 pin is used as a programmable I/O port) R/W b5 EB1 TRDIOB1 output disable bit 0: Output enabled 1: Output disabled (TRDIOB1 pin is used as a programmable I/O port) R/W b6 EC1 TRDIOC1 output disable bit 0: Output enabled 1: Output disabled (TRDIOC1 pin is used as a programmable I/O port) R/W b7 ED1 TRDIOD1 output disable bit 0: Output enabled 1: Output disabled (TRDIOD1 pin is used as a programmable I/O port) R/W Address 013Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 01111111 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b1 — — b2 — — b3 — — b4 — — b5 — — b6 — — b7 PTO INT0 of pulse output forced cutoff signal input enabled bit (1) 0: Pulse output forced cutoff input disabled 1: Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (output disabled) when a low-level signal is applied to the INT0 pin.) R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 394 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.9 Timer RD Control Re gister 0 (TRDCR0) in Reset Synchronous PWM Mode

Notes: 1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the TRDFCR register is 1 (external clock input enabled). 2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2). 3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to 0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). The TRDCR1 register is not used in reset synchronous PWM mode. Address 0140h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TCK0 Count source select bit b2 b1 b0 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRDCLK input (1) or fC2 (2) 1 1 0: fOCO40M 1 1 1: Do not set. R/W b1 TCK1 R/W b2 TCK2 R/W b3 CKEG0 External clock edge select bit (3) b4 b3 0 0: Count at the rising edge 0 1: Count at the falling edge 1 0: Count at both edges 1 1: Do not set. R/W b4 CKEG1 R/W b5 CCLR0 TRD0 counter clear select bit Set to 001b (TRD0 register cleared at compare match with TRDGRA0 register) in reset synchronous PWM mode. R/W b6 CCLR1 R/W b7 CCLR2 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 395 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.10 Timer RD Status Register i (TRD SRi) (i = 0 or 1) in Reset Synchronous

Notes: 1. Nothing is assigned to b5 in the TRDSR0 register. If necessary, write 0 to b5. When read, the content is 1. 2. The results of writing to these bits are as follows:

• The bit is set to 0 when it is first read as 1 and then 0 is written to it.
• The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.)
• The bit’s value remains unchanged if 1 is written to it. 3. Including when the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as a buffer register). Address 0143h (TRDSR0), 0153h (TRDSR1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — UDF OVF IMFD IMFC IMFB IMFA After Reset 1 1 1 0 0 0 0 0 TRDSR0 register After Reset 1 1 0 0 0 0 0 0 TRDSR1 register Bit Symbol Bit Name Function R/W b0 IMFA Input-capture/compare-match flag A [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRAi register value. R/W b1 IMFB Input-capture/compare-match flag B [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRBi register value. R/W b2 IMFC Input-capture/compare-match flag C [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRCi register value (3). R/W b3 IMFD Input-capture/compare-match flag D [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRDi register value (3). R/W b4 OVF Overflow flag [Condition for setting this bit to 0] Write 0 after reading (2) [Condition for setting this bit to 1] When the TRDi register overflows. R/W b5 UDF Underflow flag (1) This bit is disabled in reset synchronous PWM mode. R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b7 —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 396 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.11 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in Reset

21.6.12 Timer RD Counter 0 (TRD0) in Reset Synchronous PWM Mode

Access the TRD0 register in 16-bit units. Do not access it in 8-bit units. The TRD1 register is not used in reset synchronous PWM mode. Address 0144h (TRDIER0), 0154h (TRDIER1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — OVIE IMIED IMIEC IMIEB IMIEA A f t e r R e s e t 11100000 Bit Symbol Bit Name Function R/W b0 IMIEA Input-capture/compare-match interrupt enable bit A 0: Interrupt (IMIA) by IMFA bit disabled 1: Interrupt (IMIA) by IMFA bit enabled R/W b1 IMIEB Input-capture/compare-match interrupt enable bit B 0: Interrupt (IMIB) by IMFB bit disabled 1: Interrupt (IMIB) by IMFB bit enabled R/W b2 IMIEC Input-capture/compare-match interrupt enable bit C 0: Interrupt (IMIC) by IMFC bit disabled 1: Interrupt (IMIC) by IMFC bit enabled R/W b3 IMIED Input-capture/compare-match interrupt enable bit D 0: Interrupt (IMID) by IMFD bit disabled 1: Interrupt (IMID) by the IMFD bit enabled R/W b4 OVIE Overflow/underflow interrupt enable bi t 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b6 — b7 — Address 0147h to 0146h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b15 to b0 A count source is counted. Count operation is increment. When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1. 0000h to FFFFh R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 397 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.13 Timer RD General Registers Ai , Bi, Ci, and Di (TRDGRAi, TRDGRBi,

TRDGRCi, TRDGRDi) (i = 0 or 1) in Reset Synchronous PWM Mode Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The following registers are disabled in reset synchronous PWM mode: TRDPMR, TRDOCR, TRDDF0, TRDDF1, TRDI ORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1. BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0), 014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0), 0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1), 015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 11111111 Bit Function R/W b15 to b0 Refer to Table 21.12 TRDGRji Register Functions in Reset Synchronous PWM Mode R/W Table 21.12 TRDGRji Register Functions in Reset Synchronous PWM Mode Register Setting Register Function PWM Output Pin TRDGRA0 − General register. Set the PWM period. (Output inverted every PWM period and TRDIOC0 pin) TRDGRB0 − General register. Set the changing point of PWM1 output. TRDIOB0 TRDIOD0 TRDGRC0 BFC0 = 0 (These regist ers are not used in reset synchronous PWM mode.) TRDGRD0 BFD0 = 0 TRDGRA1 − General register. Set the changing point of PWM2 output. TRDIOA1 TRDIOC1 TRDGRB1 − General register. Set the changing point of PWM3 output. TRDIOB1 TRDIOD1 TRDGRC1 BFC1 = 0 (These points are not used in reset synchronous PWM mode.) TRDGRD1 BFD1 = 0 TRDGRC0 BFC0 = 1 Buffer register. Set the next PWM period. (Refer to 21.2.2 Buffer Operation.) (Output inverted every PWM period and TRDIOC0 pin) TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of the next PWM1 output. (Refer to 21.2.2 Buffer Operation.) TRDIOB0 TRDIOD0 TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of the next PWM2 output. (Refer to 21.2.2 Buffer Operation.) TRDIOA1 TRDIOC1 TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of the next PWM3 output. (Refer to 21.2.2 Buffer Operation.) TRDIOB1 TRDIOD1

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 398 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.14 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0184h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 T RDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit b1 b0 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. R/W b1 TRDIOA0SEL1 R/W b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. R/W b3 TRDIOB0SEL1 R/W b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. R/W b5 TRDIOC0SEL1 R/W b6 TRDIOD0SEL0 TRDIOD0 pin select bit b7 b6 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W b7 TRDIOD0SEL1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 399 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.15 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0185h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA1SEL0 TRDIOA1 pin select bit b1 b0 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. R/W b1 TRDIOA1SEL1 R/W b2 TRDIOB1SEL0 TRDIOB1 pin select bit b3 b2 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. R/W b3 TRDIOB1SEL1 R/W b4 TRDIOC1SEL0 TRDIOC1 pin select bit b5 b4 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. R/W b5 TRDIOC1SEL1 R/W b6 TRDIOD1SEL0 TRDIOD1 pin select bit b7 b6 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W b7 TRDIOD1SEL1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 400 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.16 Operating Example

Figure 21.18 Operating Example in Reset Synchronous PWM Mode Initial output “H” Active level “L” m n p TRD0 register value Count source m+1 TRDIOD0 output q m-n TRDIOD1 output m: Value set in TRDGRA0 register n: Value set in TRDGRB0 register p: Value set in TRDGRA1 register q: Value set in TRDGRB1 register Active level “L” Set to 0 by a program. TRDIOB0 output IMFA bit in TRDSR0 register IMFB bit in TRDSR0 register IMFA bit in TRDSR1 register IMFB bit in TRDSR1 register TSTARTi bit in TRDSTR register n+1 TRDIOC1 output TRDIOA1 output m-q m-p TRDIOB1 output TRDIOC0 output p+1 Initial output “H” i = 0 or 1 The above applies under the following condition: Bits OLS1 and OLS0 in the TRDFCR register are set to 0 (initial output at high, active level is low). 0000h Set to 0 by a program. Set to 0 by a program. Set to 0 by a program. Transfer from the buffer register to the general register during buffer operation Transfer from the buffer register to the general register during buffer operation q+1

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 401 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.6.17 A/D Trigger Generation

A compare match signal with registers TRDi (i = 0 or 1) and TRDGRji (j = A, B, C, or D) can be used as the conversion start trigger of the A/D converter. The TRDADCR register is used to select which compare match is used.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 402 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7 Complementary PWM Mode

In this mode, three normal-phases and three counter-phases of the PWM waveform are output with the same period (three-phase, triangular wave modulation, and with dead time). Figure 21.19 shows a Block Diagram of Complementary PWM Mode, and Table 21.13 lists the Complementary PWM Mode Specifications. Figure 21.20 shows the Output Model in Complementary PWM Mode, and Figure 21.21 shows an Operating Example in Complementary PWM Mode. Figure 21.19 Block Diagram of Complementary PWM Mode Period TRDIOC0 TRDIOB0 TRDIOD0 TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1 PWM1 PWM2 PWM3 Waveform control TRDGRB0 register TRDGRA1 register TRDGRB1 register Normal-phase Counter-phase TRDGRA0 register TRDGRD0 register TRDGRC1 register TRDGRD1 register Buffer Normal-phase Counter-phase Normal-phase Counter-phase

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 403 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group i = 0 or 1, j = either A, B, C, or D Note: 1. After a count starts, the PWM period is fixed. Table 21.13 Complementary PWM Mode Specifications Item Specification Count sources f1, f2, f4, f8, f32, fC2, fOCO40M External signal input to the TRDCLK pin (active edge selectable by a program) Set bits TCK2 to TCK0 in the TRDCR1 register to the same value (same count source) as bits TCK2 to TCK0 in the TRDCR0 register. Count operations Increment or decrement Registers TRD0 and TRD1 are decremented by the compare match with registers TRD0 and TRDGRA0 during increment operation. The TRD1 register value is changed from 0000h to FFFFh during decrement operation, and registers TRD0 and TRD1 are incremented. PWM operations PWM period: 1/fk × (m+2-p) × 2 (1) Dead time: p Active level width of normal-phase: 1/fk × (m-n-p+1) × 2 Active level width of counter-phase: 1/fk × (n+1-p) × 2 fk: Frequency of count source m: Value set in TRDGRA0 register n: Value set in TRDGRB0 register (PWM1 output) Value set in TRDGRA1 register (PWM2 output) Value set in TRDGRB1 register (PWM3 output) p: Value set in TRD0 register Count start condition 1 (count starts) is written to bits TSTART0 and TSTART1 in the TRDSTR register. Count stop conditions 0 (count stops) is written to bits TSTART0 and TSTART1 in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1. (The PWM output pin holds the output level before the count stops.) Interrupt request generation timing

• Compare match (The contents of the TRDi register and the TRDGRji register match.)
• TRD1 register underflow TRDIOA0 pin function Programmable I/O port or TRDCLK (external clock) input TRDIOB0 pin function PWM1 output normal-phase output TRDIOD0 pin function PWM1 output counter-phase output TRDIOA1 pin function PWM2 output normal-phase output TRDIOC1 pin function PWM2 output counter-phase output TRDIOB1 pin function PWM3 output normal-phase output TRDIOD1 pin function PWM3 output counter-phase output TRDIOC0 pin function Output inverted every 1/2 period of PWM INT0 pin function Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input Read from timer The count value can be read by reading the TRDi register. Write to timer The value can be written to the TRDi register. Selectable functions • Pulse output forced cutoff signal input (Refer to

21.2.4 Pulse Output Forced

Cutoff.)

• The normal-phase and counter-phase active level and initial output level can selected individually.
• Selectable transfer timing from the buffer register
• A/D trigger generation n+1 Normal-phase (Active level is low) Counter-phase m+2-p n+1-p p m-p-n+1

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 404 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.1 Module Standby Control Register (MSTCR)

Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any acce ss to the timer RC associated registers (addresses 0170h to 017Fh) is disabled.

21.7.2 Timer RD Control Ex pansion Register (TRDECR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — MSTTRG MSTTRC MSTTRD MSTIIC — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 MSTIIC SSU, I 2C bus standby bit 0: Active 1: Standby (1) R/W b4 MSTTRD Timer RD standby bit 0: Active 1: Standby (2) R/W b5 MSTTRC Timer RC standby bit 0: Active 1: Standby (3) R/W b6 MSTTRG Timer RG standby bit 0: Active 1: Standby (4) R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — Address 0135h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ITCLK1 — — — ITCLK0 — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 405 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.3 Timer RD Trigger C ontrol Register (TRDADCR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 ADTRGA0E A/D trigger A0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRA0 R/W b1 ADTRGB0E A/D trigger B0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRB0 R/W b2 ADTRGC0E A/D trigger C0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRC0 R/W b3 ADTRGD0E A/D trigger D0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRD0 R/W b4 ADTRGA1E A/D trigger A1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRA1 R/W b5 ADTRGB1E A/D trigger B1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRB1 R/W b6 ADTRGC1E A/D trigger C1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRC1 R/W b7 ADTRGD1E A/D trigger D1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRD1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 406 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.4 Timer RD Start Register (T RDSTR) in Complementary PWM Mode

Notes: 1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit. 2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit. 3. When the CSEL0 bit is set to 0 and the compare match si gnal (TRDIOA0) is generated, this bit is set to 0 (count stops). 4. When the CSEL1 bit is set to 0 and the compare match si gnal (TRDIOA1) is generated, this bit is set to 0 (count stops). Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1 TRDSTR Register for Notes on Timer RD.

21.7.5 Timer RD Mode Register (T RDMR) in Complementary PWM Mode

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — CSEL1 CSEL0 TSTART1 TSTART0 A f t e r R e s e t 11111100 Bit Symbol Bit Name Function R/W b0 TSTART0 TRD0 count start flag (3) 0: Count stops (1) 1: Count starts R/W b1 TSTART1 TRD1 count start flag (4) 0: Count stops (2) 1: Count starts R/W b2 CSEL0 TRD0 count operation select bit 0: Count stops at compare match with the TRDGRA0 register 1: Count continues after compare match with the TRDGRA0 register R/W b3 CSEL1 TRD1 count operation select bit 0: Count stops at compare match with the TRDGRA1 register 1: Count continues after compare match with the TRDGRA1 register R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — b6 — b7 — Address 0138h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BFD1 BFC1 BFD0 BFC0 — — — SYNC A f t e r R e s e t 00001110 Bit Symbol Bit Name Function R/W b0 SYNC Timer RD synchronous bit Set to 0 (registers TRD0 and TRD1 operate independently) in complementary PWM mode. R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b2 — b3 — b4 BFC0 TRDGRC0 register function select bit Set to 0 (general register) in complementary PWM mode. R/W b5 BFD0 TRDGRD0 register function select bit 0: General register 1: Buffer register of TRDGRB0 register R/W b6 BFC1 TRDGRC1 register function select bit 0: General register 1: Buffer register of TRDGRA1 register R/W b7 BFD1 TRDGRD1 register function select bit 0: General register 1: Buffer register of TRDGRB1 register R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 407 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.6 Timer RD Function Control Regist er (TRDFCR) in Complementary PWM

Notes: 1. When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the setting of the TRDPMR register. 2. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). 3. Set the ADCAP bit in the ADCON0 register to 1 (start by timer RD). 4. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. Address 013Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0 A f t e r R e s e t 10000000 Bit Symbol Bit Name Function R/W b0 CMD0 Combination mode select bit (1, 2) b1 b0 1 0: Complementary PWM mode (transfer from the buffer register to the general register at TRD1 register underflow) 1 1: Complementary PWM mode (transfer from the buffer register to the general register at compare match with registers TRD0 and TRDGRA0.) Other than above: Do not set. R/W b1 CMD1 R/W b2 OLS0 Normal-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) 0: Initial output at high, active level is low 1: Initial output at low, active level is high R/W b3 OLS1 Counter-phase output level select bit (in reset synchronous PWM mode or complementary PWM mode) 0: Initial output at high, active level is low 1: Initial output at low, active level is high R/W b4 ADTRG A/D trigger enable bit (in complementary PWM mode) 0: A/D trigger disabled 1: A/D trigger enabled (3) R/W b5 ADEG A/D trigger edge select bit (in complementary PWM mode) 0: A/D trigger is generated at compare match between registers TRD0 and TRDGRA0 1: A/D trigger is generated at underflow in the TRD1 register R/W b6 STCLK External clock input select bit 0: External clock input disabled 1: External clock input enabled R/W b7 PWM3 PWM3 mode select bit (4) Disabled in complementary PWM mode. R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 408 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.7 Timer RD Output Master Enable Register 1 (TRDOER1) in Complementary

21.7.8 Timer RD Output Master Enable Register 2 (TRDOER2) in Complementary

Note: 1. Refer to 21.2.4 Pulse Output Forced Cutoff. Address 013Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ED1 EC1 EB1 EA1 ED0 EC0 EB0 EA0 A f t e r R e s e t 11111111 Bit Symbol Bit Name Function R/W b0 EA0 TRDIOA0 output disable bit Set to 1 (TRDIOA0 pin is used as a programmable I/O port) in complementary PWM mode. R/W b1 EB0 TRDIOB0 output disable bit 0: Output enabled 1: Output disabled (TRDIOB0 pin is used as a programmable I/O port) R/W b2 EC0 TRDIOC0 output disable bit 0: Output enabled 1: Output disabled (TRDIOC0 pin is used as a programmable I/O port) R/W b3 ED0 TRDIOD0 output disable bit 0: Output enabled 1: Output disabled (TRDIOD0 pin is used as a programmable I/O port) R/W b4 EA1 TRDIOA1 output disable bit 0: Output enabled 1: Output disabled (TRDIOA1 pin is used as a programmable I/O port) R/W b5 EB1 TRDIOB1 output disable bit 0: Output enabled 1: Output disabled (TRDIOB1 pin is used as a programmable I/O port) R/W b6 EC1 TRDIOC1 output disable bit 0: Output enabled 1: Output disabled (TRDIOC1 pin is used as a programmable I/O port) R/W b7 ED1 TRDIOD1 output disable bit 0: Output enabled 1: Output disabled (TRDIOD1 pin is used as a programmable I/O port) R/W Address 013Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 01111111 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b1 — — b2 — — b3 — — b4 — — b5 — — b6 — — b7 PTO INT0 of pulse output forced cutoff signal input enabled bit (1) 0: Pulse output forced cutoff input disabled 1: Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (output disabled) when a low-level signal is applied to the INT0 pin.) R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 409 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.9 Timer RD Control Regi ster i (TRDCRi) (i = 0 or 1) in Complementary PWM

Notes: 1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the TRDFCR register is 1 (external clock input enabled). 2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2). 3. Set bits TCK2 to TCK0 and bits CKEG1 to CKEG0 in registers TRDCR0 and TRDCR1 to the same values. 4. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to 0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). Address 0140h (TRDCR0), 0150h (TRDCR1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TCK0 Count source select bit (3) b2 b1 b0 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRDCLK input (1) or fC2 (2) 1 1 0: fOCO40M 1 1 1: Do not set. R/W b1 TCK1 R/W b2 TCK2 R/W b3 CKEG0 External clock edge select bit (3, 4) b4 b3 0 0: Count at the rising edge 0 1: Count at the falling edge 1 0: Count at both edges 1 1: Do not set. R/W b4 CKEG1 R/W b5 CCLR0 TRDi counter clear select bit Set to 000b (clear disabled (free-running operation)) in complementary PWM mode. R/W b6 CCLR1 R/W b7 CCLR2 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 410 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.10 Timer RD Status Regi ster i (TRDSRi) (i = 0 or 1) in Complementary PWM

Notes: 1. Nothing is assigned to b5 in the TRDSR0 register. If necessary, write 0 to b5. When read, the content is 1. 2. The results of writing to these bits are as follows:

• The bit is set to 0 when it is first read as 1 and then 0 is written to it.
• The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.)
• The bit’s value remains unchanged if 1 is written to it. 3. Including when the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as a buffer register). Address 0143h (TRDSR0), 0153h (TRDSR1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — UDF OVF IMFD IMFC IMFB IMFA After Reset 1 1 1 0 0 0 0 0 TRDSR0 register After Reset 1 1 0 0 0 0 0 0 TRDSR1 register Bit Symbol Bit Name Function R/W b0 IMFA Input-capture/compare-match flag A [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRAi register value. R/W b1 IMFB Input-capture/compare-match flag B [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRBi register value. R/W b2 IMFC Input-capture/compare-match flag C [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRCi register value (3). R/W b3 IMFD Input-capture/compare-match flag D [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRDi register value (3). R/W b4 OVF Overflow flag [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRDi register overflows. R/W b5 UDF Underflow flag (1) [Condition for setting this bit to 0] Write 0 after reading. (2) [Condition for setting this bit to 1] When the TRD1 register underflows. R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b7 —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 411 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.11 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in Complementary

21.7.12 Timer RD Count er 0 (TRD0) in Complementary PWM Mode

Access the TRD0 register in 16-bit units. Do not access it in 8-bit units. Address 0144h (TRDIER0), 0154h (TRDIER1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — OVIE IMIED IMIEC IMIEB IMIEA A f t e r R e s e t 11100000 Bit Symbol Bit Name Function R/W b0 IMIEA Input-capture/compare-match interrupt enable bit A 0: Interrupt (IMIA) by IMFA bit disabled 1: Interrupt (IMIA) by IMFA bit enabled R/W b1 IMIEB Input-capture/compare-match interrupt enable bit B 0: Interrupt (IMIB) by IMFB bit disabled 1: Interrupt (IMIB) by IMFB bit enabled R/W b2 IMIEC Input-capture/compare-match interrupt enable bit C 0: Interrupt (IMIC) by IMFC bit disabled 1: Interrupt (IMIC) by IMFC bit enabled R/W b3 IMIED Input-capture/compare-match interrupt enable bit D 0: Interrupt (IMID) by IMFD bit disabled 1: Interrupt (IMID) by the IMFD bit enabled R/W b4 OVIE Overflow/underflow interrupt enable bit 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b6 — b7 — Address 0147h to 0146h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b15 to b0 Set the dead time. A count source is counted. Count operation is increment or decrement. When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1. 0000h to FFFFh R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 412 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.13 Timer RD Count er 1 (TRD1) in Complementary PWM Mode

Access the TRD1 register in 16-bit units. Do not access it in 8-bit units.

21.7.14 Timer RD General Registers Ai, Bi, C1, and Di (TRDGRAi, TRDGRBi,

TRDGRC1, TRDGRDi) (i = 0 or 1) in Complementary PWM Mode Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The TRDGRC0 register is not used in complementary PWM mode. The following registers are disabled in complementary PWM mode: TRDPMR, TRDOCR, TRDDF0, TRDDF1, TRDI ORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1. Address 0157h to 0156h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b15 to b0 Set 0000h. A count source is counted. Count operation is increment or decrement. When an underflow occurs, the UDF bit in the TRDSR1 register is set to 1. 0000h to FFFFh R/W Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0), 014Fh to 014Eh (TRDGRD0), 0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1), 015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 11111111 Bit Function R/W b15 to b0 Refer to Table 21.14 TRDGRji Register Functions in Complementary PWM Mode R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 413 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register Since values cannot be written to the TRDGRB0, TRDGRA1, or TRDGRB1 register directly after count operation starts (prohibited item), use the TRDGRD0, TRDGRC1, or TRDGRD1 register as a buffer register. However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register). Table 21.14 TRDGRji Register Functions in Complementary PWM Mode Register Setting Register Function PWM Output Pin TRDGRA0 − General register. Set the PWM period at initialization. Setting range: TRD0 register setting value or above, FFFFh - TRD0 register setting value or below Do not write to this register when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). (Output inverted every half period of TRDIOC0 pin) TRDGRB0 − General register. Set the changing point of PWM1 output at initialization. Setting range: TRD0 register setting value or above, TRDGRA0 register - TRD0 register setting value or below Do not write to this register when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). TRDIOB0 TRDIOD0 TRDGRA1 − General register. Set the changing point of PWM2 output at initialization. Setting range: TRD0 register setting value or above, TRDGRA0 register - TRD0 register setting value or below Do not write to this register when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). TRDIOA1 TRDIOC1 TRDGRB1 − General register. Set the changing point of PWM3 output at initialization. Setting range: TRD0 register setting value or above, TRDGRA0 register - TRD0 register setting value or below Do not write to this register when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). TRDIOB1 TRDIOD1 TRDGRC0 − This register is not used in complementary PWM mode. − TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of next PWM1 output. (Refer to 21.2.2 Buffer Operation.) Setting range: TRD0 register setting value or above, TRDGRA0 register - TRD0 register setting value or below Set this register to the same value as the TRDGRB0 register for initialization. TRDIOB0 TRDIOD0 TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of next PWM2 output. (Refer to 21.2.2 Buffer Operation.) Setting range: TRD0 register setting value or above, TRDGRA0 register - TRD0 register setting value or below Set this register to the same value as the TRDGRA1 register for initialization. TRDIOA1 TRDIOC1 TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of next PWM3 output. (Refer to 21.2.2 Buffer Operation.) Setting range: TRD0 register setting value or above, TRDGRA0 register - TRD0 register setting value or below Set this register to the same value as the TRDGRB1 register for initialization. TRDIOB1 TRDIOD1

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 414 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.15 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0184h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 T RDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit b1 b0 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. R/W b1 TRDIOA0SEL1 R/W b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. R/W b3 TRDIOB0SEL1 R/W b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. R/W b5 TRDIOC0SEL1 R/W b6 TRDIOD0SEL0 TRDIOD0 pin select bit b7 b6 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W b7 TRDIOD0SEL1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 415 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.16 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0185h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA1SEL0 TRDIOA1 pin select bit b1 b0 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. R/W b1 TRDIOA1SEL1 R/W b2 TRDIOB1SEL0 TRDIOB1 pin select bit b3 b2 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. R/W b3 TRDIOB1SEL1 R/W b4 TRDIOC1SEL0 TRDIOC1 pin select bit b5 b4 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. R/W b5 TRDIOC1SEL1 R/W b6 TRDIOD1SEL0 TRDIOD1 pin select bit b7 b6 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W b7 TRDIOD1SEL1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 416 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.17 Operating Example

Figure 21.20 Output Model in Complementary PWM Mode TRDi register value TRDIOD0 output 0000h TRDGRA0 register value TRDGRB0 register value TRDGRA1 register value TRDGRB1 register value TRDIOB0 output TRDIOC1 output TRDIOA1 output TRDIOD1 output TRDIOB1 output TRDIOC0 output TRD0 register value TRD1 register value i = 0 or 1

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 417 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 21.21 Operating Example in Complementary PWM Mode m+2-p p n+1 n+1-p p n+1-p n n n m-p-n+1 m n TRDi register value Count source TRDIOD0 output p m: Value set in TRDGRA0 register n: Value set in TRDGRB0 register p: Value set in TRD0 register TRDIOB0 output IMFA bit in TRDSR0 register TRDGRB0 register Bits TSTART0 and TSTART1 in TRDSTR register TRDIOC0 output 0000h m+1 (m-p-n+1) × 2 Width of normal- phase active level Dead time (n+1-p) × 2 Width of counter-phase active level FFFFh is set. UDF bit in TRDSR1 register Next data Change by a program. TRDGRD0 register Transfer (when bits CMD1 to CMD0 are set to 11b) Transfer (when bits CMD1 to CMD0 are set to 10b) TRD1 register value TRD0 register value CMD0, CMD1: Bits in TRDFCR register i = 0 or 1 The above applies under the following condition: Bits OLS1 and OLS0 in TRDFCR are set to 0 (initial output level at high, active level is low for normal-phase and counter-phase ) Set to 0 by a program. Active level “L” Initial output “H” Initial output “H” Set to 0 by a program. Set to 0 by a program.IMFB bit in TRDSR0 register

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 418 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.7.18 Transfer Timing from Buffer Register

• Transfer from the TRDGRD0, TRDGRC1, or TR DGRD1 register to the TRDGRB0, TRDGRA1, or TRDGRB1 register. When bits CMD1 to CMD0 in the TRDFCR register are set to 10b, the content is transferred when the TRD1 register underflows. When bits CMD1 to CMD0 are set to 11b, the conten t is transferred at compar e match between registers TRD0 and TRDGRA0.

21.7.19 A/D Trigger Generation

A compare match between registers TRD0 and TRDGRA0 and TRD1 underflow can be used as the conversion start trigger of the A/D converter. The trigger is selected by bits ADEG and ADTRG in the TRDFCR register. In addition, set bits ADCAP1 to ADCAP0 in the ADMOD register to 01b (start by timer RD).

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 419 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8 PWM3 Mode

In this mode, 2 PWM waveforms are output with the same period. Figure 21.22 shows a Block Diagram of PWM3 Mode, a nd Table 21.15 lists the PWM3 Mode Specifications. Figure 21.23 shows an Operating Example in PWM3 Mode. Figure 21.22 Block Diagram of PWM3 Mode TRDIOA0 Output control TRDGRC0 Compare match signal TRDIOB0 Output control Comparator TRDGRA0TRD0 TRDGRC1 Compare match signal Comparator TRDGRA1 TRDGRD0Comparator TRDGRB0 TRDGRD1Comparator TRDGRB1 Compare match signal Compare match signal Buffer

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 420 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group i = 0 or 1, j = either A, B, C, or D Table 21.15 PWM3 Mode Specifications Item Specification Count sources f1, f2, f4, f8, f32, fC2, fOCO40M Count operations The TRD0 register is in cremented (TRD1 register is not used). PWM waveform PWM peri od: 1/fk × (m+1) Active level width of TRDIOA0 output: 1/fk × (m-n) Active level width of TRDIOB0 output: 1/fk × (p-q) fk: Frequency of count source m: Value set in TRDGRA0 register n: Value set in TRDGRA1 register p: Value set in TRDGRB0 register q: Value set in TRDGRB1 register Count start condition 1 (count starts) is written to the TSTART0 bit in the TRDSTR register. Count stop conditions • 0 (count stops) is writte n to the TSTART0 bit in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1. The PWM output pin holds output level before the count stops

• When the CSEL0 bit in the TRDSTR register is set to 0, the count stops at compare match with the TRDGRA0 register. The PWM output pin holds the level after the output changes by the compare match. Interrupt request generation timing
• Compare match (The contents of the TRDi register and the TRDGRji register match.)
• TRD0 register overflow TRDIOA0, TRDIOB0 pins function PWM output TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 pins function Programmable I/O port INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input Read from timer The count value can be read by reading the TRD0 register. Write to timer The value can be written to the TRD0 register. Selectable functions • Pulse output fo rced cutoff signal input (Refer to 21.2.4 Pulse Output Forced Cutoff.)
• Buffer operation (Refer to 21.2.2 Buffer Operation.)
• Active level selectable for each individual pin
• A/D trigger generation m+1 TRDIOA0 output TRDIOB0 output (Active level is high) p-q m-n n+1 p+1 q+1

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 421 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.1 Module Standby Control Register (MSTCR)

Notes: 1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses 0193h to 019Dh) is disabled. 2. When the MSTTRD bit is set to 1 (standby), any access to the timer RD associated registers (addresses 0135h to 015Fh) is disabled. 3. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h to 0133h) is disabled. 4. When the MSTTRG bit is set to 1 (standby), any acce ss to the timer RC associated registers (addresses 0170h to 017Fh) is disabled.

21.8.2 Timer RD Control Ex pansion Register (TRDECR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — MSTTRG MSTTRC MSTTRD MSTIIC — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 MSTIIC SSU, I 2C bus standby bit 0: Active 1: Standby (1) R/W b4 MSTTRD Timer RD standby bit 0: Active 1: Standby (2) R/W b5 MSTTRC Timer RC standby bit 0: Active 1: Standby (3) R/W b6 MSTTRG Timer RG standby bit 0: Active 1: Standby (4) R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — Address 0135h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ITCLK1 — — — ITCLK0 — — — A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 ITCLK0 Timer RD0 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 — b6 — b7 ITCLK1 Timer RD1 fC2 select bit 0: TRDCLK input selected 1: fC2 selected R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 422 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.3 Timer RD Trigger C ontrol Register (TRDADCR)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ADTRGD1E ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E ADTRGB0E ADTRGA0E A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 ADTRGA0E A/D trigger A0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRA0 R/W b1 ADTRGB0E A/D trigger B0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRB0 R/W b2 ADTRGC0E A/D trigger C0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRC0 R/W b3 ADTRGD0E A/D trigger D0 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD0 and TRDGRD0 R/W b4 ADTRGA1E A/D trigger A1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRA1 R/W b5 ADTRGB1E A/D trigger B1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRB1 R/W b6 ADTRGC1E A/D trigger C1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRC1 R/W b7 ADTRGD1E A/D trigger D1 enable bit 0: A/D trigger disabled 1: A/D trigger generated at compare match with registers TRD1 and TRDGRD1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 423 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.4 Timer RD Start Regist er (TRDSTR) in PWM3 Mode

Notes: 1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit. 2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit. 3. When the CSEL0 bit is set to 0 and the compare match si gnal (TRDIOA0) is generated, this bit is set to 0 (count stops). 4. When the CSEL1 bit is set to 0 and the compare match si gnal (TRDIOA1) is generated, this bit is set to 0 (count stops). Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 21.10.1 TRDSTR Register for Notes on Timer RD.

21.8.5 Timer RD Mode Regist er (TRDMR) in PWM3 Mode

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — — CSEL1 CSEL0 TSTART1 TSTART0 A f t e r R e s e t 11111100 Bit Symbol Bit Name Function R/W b0 TSTART0 TRD0 count start flag (3) 0: Count stops (1) 1: Count starts R/W b1 TSTART1 TRD1 count start flag (4) 0: Count stops (2) 1: Count starts R/W b2 CSEL0 TRD0 count operation select bit 0: Count stops at compare match with the TRDGRA0 register 1: Count continues after compare match with the TRDGRA0 register R/W b3 CSEL1 TRD1 count operation select bit [not used in PWM3 mode] 0: Count stops at compare match with the TRDGRA1 register 1: Count continues after compare match with the TRDGRA1 register R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — b6 — b7 — Address 0138h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BFD1 BFC1 BFD0 BFC0 — — — SYNC A f t e r R e s e t 00001110 Bit Symbol Bit Name Function R/W b0 SYNC Timer RD synchronous bit Set to 0 (TRD0 and TRD1 operate independently) in PWM3 mode. R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b2 — b3 — b4 BFC0 TRDGRC0 register function select bit 0: General register 1: Buffer register of TRDGRA0 register R/W b5 BFD0 TRDGRD0 register function select bit 0: General register 1: Buffer register of TRDGRB0 register R/W b6 BFC1 TRDGRC1 register function select bit 0: General register 1: Buffer register of TRDGRA1 register R/W b7 BFD1 TRDGRD1 register function select bit 0: General register 1: Buffer register of TRDGRB1 register R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 424 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.6 Timer RD Functi on Control Register (TRDFCR) in PWM3 Mode

Notes: 1. Set bits CMD1 to CMD0 when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. Address 013Ah B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol PWM3 STCLK ADEG ADTRG OLS1 OLS0 CMD1 CMD0 A f t e r R e s e t 10000000 Bit Symbol Bit Name Function R/W b0 CMD0 Combination mode select bit (1) Set to 00b (timer mode, PWM mode, or PWM3 mode) in PWM3 mode. R/W b1 CMD1 R/W b2 OLS0 Normal-phase output level select bit (enabled in reset synchronous PWM mode or complementary PWM mode) Disabled in PWM3 mode. R/W b3 OLS1 Counter-phase output level select bit (enabled in reset synchronous PWM mode or complementary PWM mode) R/W b4 ADTRG A/D trigger enable bit (enabled in complementary PWM mode) R/W b5 ADEG A/D trigger edge select bit (enabled in complementary PWM mode) R/W b6 STCLK External clock input select bit Set to 0 (external clock input disabled) in PWM3 mode. R/W b7 PWM3 PWM3 mode select bit (2) Set to 0 (PWM3 mode) in PWM3 mode. R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 425 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.7 Timer RD Output Master Enable Register 1 (TRDOER1) in PWM3 Mode

21.8.8 Timer RD Output Master Enable Register 2 (TRDOER2) in PWM3 Mode

Note: 1. Refer to 21.2.4 Pulse Output Forced Cutoff. Address 013Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol ED1 EC1 EB1 EA1 ED0 EC0 EB0 EA0 A f t e r R e s e t 11111111 Bit Symbol Bit Name Function R/W b0 EA0 TRDIOA0 output disable bit 0: Output enabled 1: Output disabled (TRDIOA0 pin is used as a programmable I/O port) R/W b1 EB0 TRDIOB0 output disable bit 0: Output enabled 1: Output disabled (TRDIOB0 pin is used as a programmable I/O port) R/W b2 EC0 TRDIOC0 output disable bit Set to 1 (programmable I/O port) in PWM3 mode. R/W b3 ED0 TRDIOD0 output disable bit R/W b4 EA1 TRDIOA1 output disable bit R/W b5 EB1 TRDIOB1 output disable bit R/W b6 EC1 TRDIOC1 output disable bit R/W b7 ED1 TRDIOD1 output disable bit R/W Address 013Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 01111111 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b1 — — b2 — — b3 — — b4 — — b5 — — b6 — — b7 PTO INT0 of pulse output forced cutoff signal input enabled bit (1) 0: Pulse output forced cutoff input disabled 1: Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (output disabled) when a low-level signal is applied to the INT0 pin.) R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 426 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.9 Timer RD Output Control Re gister (TRDOCR) in PWM3 Mode

Note: 1. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the TRDOCR register is set. Write to the TRDOCR register when both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). Address 013Dh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TOA0 TRDIOA0 output level select bit (1) 0: Active level is high, initial output at low, high-level output at compare match with the TRDGRA1 register, low-level output at compare match with the TRDGRA0 register 1: Active level is low, initial output at high, low-level output at compare match with the TRDGRA1 register, high-level output at compare match with the TRDGRA0 register R/W b1 TOB0 TRDIOB0 output level select bit (1) 0: Active level is high, initial output at low, high-level output at compare match with the TRDGRB1register, low-level output at compare match with the TRDGRB0 register 1: Active level is low, initial output at high, low-level output at compare match with the TRDGRB1 register, high-level output at compare match with the TRDGRB0 register R/W b2 TOC0 TRDIOC0 initial output level select bit Disabled in PWM3 mode. R/W b3 TOD0 TRDIOD0 initial output level select bit R/W b4 TOA1 TRDIOA1 initial output level select bit R/W b5 TOB1 TRDIOB1 initial output level select bit R/W b6 TOC1 TRDIOC1 initial output level select bit R/W b7 TOD1 TRDIOD1 initial output level select bit R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 427 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.10 Timer RD Control Regist er 0 (TRDCR0) in PWM3 Mode

The TRDCR1 register is not used in PWM3 mode for the TRDCR0 register. Address 0140h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TCK0 Count source select bit b2 b1 b0 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: Do not set. 1 1 0: fOCO40M 1 1 1: Do not set. R/W b1 TCK1 R/W b2 TCK2 R/W b3 CKEG0 External clock edge select bit Disabled in PWM3 mode. R/W b4 CKEG1 R/W b5 CCLR0 TRD0 counter clear select bit Set to 001b (TRD0 register cleared at compare match with TRDGRA0 register) in PWM3 mode. R/W b6 CCLR1 R/W b7 CCLR2 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 428 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.11 Timer RD Status Register i (T RDSRi) (i = 0 or 1) in PWM3 Mode

Notes: 1. The results of writing to these bits are as follows:

• The bit is set to 0 when it is first read as 1 and then 0 is written to it.
• The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.)
• The bit’s value remains unchanged if 1 is written to it. 2. Including w hen the BFji (j = C or D) bit in the TRDMR regist er is set to 1 (TRDGRji is used as a buffer register). Address 0143h (TRDSR0), 0153h (TRDSR1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — UDF OVF IMFD IMFC IMFB IMFA After Reset 1 1 1 0 0 0 0 0 TRDSR0 register After Reset 1 1 0 0 0 0 0 0 TRDSR1 register Bit Symbol Bit Name Function R/W b0 IMFA Input-capture/compare-match flag A [Condition for setting this bit to 0] Write 0 after reading. (1) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRAi register value. R/W b1 IMFB Input-capture/compare-match flag B [Condition for setting this bit to 0] Write 0 after reading. (1) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRBi register value. R/W b2 IMFC Input-capture/compare-match flag C [Condition for setting this bit to 0] Write 0 after reading. (1) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRCi register value (2). R/W b3 IMFD Input-capture/compare-match flag D [Condition for setting this bit to 0] Write 0 after reading. (1) [Condition for setting this bit to 1] When the TRDi register value matches the TRDGRDi register value (2). R/W b4 OVF Overflow flag [Condition for setting this bit to 0] Write 0 after reading. (1) [Condition for setting this bit to 1] When the TRDi register overflows. R/W b5 UDF Underflow flag (1) This bit is disabled in PWM3 Mode. R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b7 —

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 429 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.12 Timer RD Interrupt Enable Register i (TRDIERi) (i = 0 or 1) in PWM3 Mode

21.8.13 Timer RD Counter 0 (TRD0) in PWM3 Mode

Access the TRD0 register in 16-bit units. Do not access it in 8-bit units. The TRD1 register is not used in PWM3 mode. Address 0144h (TRDIER0), 0154h (TRDIER1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — — OVIE IMIED IMIEC IMIEB IMIEA A f t e r R e s e t 11100000 Bit Symbol Bit Name Function R/W b0 IMIEA Input-capture/compare-match interrupt enable bit A 0: Interrupt (IMIA) by IMFA bit disabled 1: Interrupt (IMIA) by IMFA bit enabled R/W b1 IMIEB Input-capture/compare-match interrupt enable bit B 0: Interrupt (IMIB) by IMFB bit disabled 1: Interrupt (IMIB) by IMFB bit enabled R/W b2 IMIEC Input-capture/compare-match interrupt enable bit C 0: Interrupt (IMIC) by IMFC bit disabled 1: Interrupt (IMIC) by IMFC bit enabled R/W b3 IMIED Input-capture/compare-match interrupt enable bit D 0: Interrupt (IMID) by IMFD bit disabled 1: Interrupt (IMID) by the IMFD bit enabled R/W b4 OVIE Overflow/underflow interrupt enable bi t 0: Interrupt (OVI) by OVF bit disabled 1: Interrupt (OVI) by OVF bit enabled R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b6 — b7 — Address 0147h to 0146h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b15 to b0 A count source is counted. Count operation is increment. When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1. 0000h to FFFFh R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 430 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.14 Timer RD General Registers Ai , Bi, Ci, and Di (TRDGRAi, TRDGRBi,

TRDGRCi, TRDGRDi) (i = 0 or 1) in PWM3 Mode Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. The following registers are disabled for the PWM3 mode function: TRDPMR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1. Address 0149h to 0148h (TRDGRA0), 014Bh to 014Ah (TRDGRB0), 014Dh to 014Ch (TRDGRC0), 014Fh to 014Eh (TRDGRD0), 0159h to 0158h (TRDGRA1), 015Bh to 015Ah (TRDGRB1), 015Dh to 015Ch (TRDGRC1), 015Fh to 015Eh (TRDGRD1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 11111111 Bit Function R/W b15 to b0 Refer to Table 21.16 TRDGRji Register Functions in PWM3 Mode R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 431 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register Registers TRDGRC0, TRDGRC1, TRDGRD0, and TRDGRD1 are not used in PWM3 mode. To use them as buffer registers, set bits BFC0, BFC1, BFD0, and BFD1 to 0 (general register) and write a value to the TRDGRC0, TRDGRC1, TRDGRD0, or TRDGRD1 register. After this, b its BFC0, BFC1, BFD0, and BFD1 may be set to 1 (buffer register). Table 21.16 TRDGRji Register Functions in PWM3 Mode Register Setting Register Function PWM Output Pin TRDGRA0 − General register. Set the PWM period. Setting range: TRDGRA1 register setting value or above TRDIOA0 TRDGRA1 General register. Set the ch anging point (the active level timing) of PWM output. Setting range: TRDGRA0 register setting value or below TRDGRB0 General register. Set the ch anging point (the timing that returns to initial output level) of PWM output. Setting range: TRDGRB1 register setting value or above, TRDGRA0 register setting value or below TRDIOB0 TRDGRB1 General register. Set the changing point (active level timing) of PWM output. Setting range: TRDGRB0 register setting value or below TRDGRC0 BFC0 = 0 (These registers are not used in PWM3 mode.) TRDGRC1 BFC1 = 0 TRDGRD0 BFD0 = 0 TRDGRD1 BFD1 = 0 TRDGRC0 BFC0 = 1 Buffer regist er. Set the next PWM period. (Refer to 21.2.2 Buffer Operation.) Setting range: TRDGRC1 register setting value or above TRDIOA0 TRDGRC1 BFC1 = 1 Buffer register. Set th e changing point of next PWM output. (Refer to 21.2.2 Buffer Operation.) Setting range: TRDGRC0 register setting value or below TRDGRD0 BFD0 = 1 Buffer register. Set th e changing point of next PWM output. (Refer to 21.2.2 Buffer Operation.) Setting range: TRDGRD1 register setting value or above, TRDGRC0 register setting value or below TRDIOB0 TRDGRD1 BFD1 = 1 Buffer register. Set th e changing point of next PWM output. (Refer to 21.2.2 Buffer Operation.) Setting range: TRDGRD0 register setting value or below

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 432 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.15 Timer RD Pin Select Register 0 (TRDPSR0)

The TRDPSR0 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR0 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0184h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD0SEL1 TRDIOD0SEL0 TRDIOC0SEL1 TRDIOC0SEL0 T RDIOB0SEL1 TRDIOB0SEL0 TRDIOA0SEL1 TRDIOA0SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA0SEL0 TRDIOA0/TRDCLK pin select bit b1 b0 0 0: TRDIOA0/TRDCLK pin not used 0 1: P6_0 assigned 1 0: P10_0 assigned 1 1: Do not set. R/W b1 TRDIOA0SEL1 R/W b2 TRDIOB0SEL0 TRDIOB0 pin select bit b3 b2 0 0: TRDIOB0 pin not used 0 1: P6_1 assigned 1 0: P10_1 assigned 1 1: Do not set. R/W b3 TRDIOB0SEL1 R/W b4 TRDIOC0SEL0 TRDIOC0 pin select bit b5 b4 0 0: TRDIOC0 pin not used 0 1: P6_2 assigned 1 0: P10_2 assigned 1 1: Do not set. R/W b5 TRDIOC0SEL1 R/W b6 TRDIOD0SEL0 TRDIOD0 pin select bit b7 b6 0 0: TRDIOC0 pin not used 0 1: P6_3 assigned 1 0: P10_3 assigned 1 1: Do not set. R/W b7 TRDIOD0SEL1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 433 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.16 Timer RD Pin Select Register 1 (TRDPSR1)

The TRDPSR1 register selects which pin is assigned as the timer RD input/output. To use the I/O pins for timer RD, set this register. Set the TRDPSR1 register before setting the timer RD associated registers. Also, do not change the setting value of this register during timer RD operation. Address 0185h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TRDIOD1SEL1 TRDIOD1SEL0 TRDIOC1SEL1 TRDIOC1SEL0 TRDIOB1SEL1 TRDIOB1SEL0 TRDIOA1SEL1 TRDIOA1SEL0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 TRDIOA1SEL0 TRDIOA1 pin select bit b1 b0 0 0: TRDIOA1 pin not used 0 1: P6_4 assigned 1 0: P10_4 assigned 1 1: Do not set. R/W b1 TRDIOA1SEL1 R/W b2 TRDIOB1SEL0 TRDIOB1 pin select bit b3 b2 0 0: TRDIOB1 pin not used 0 1: P6_5 assigned 1 0: P10_5 assigned 1 1: Do not set. R/W b3 TRDIOB1SEL1 R/W b4 TRDIOC1SEL0 TRDIOC1 pin select bit b5 b4 0 0: TRDIOC1 pin not used 0 1: P6_6 assigned 1 0: P10_6 assigned 1 1: Do not set. R/W b5 TRDIOC1SEL1 R/W b6 TRDIOD1SEL0 TRDIOD1 pin select bit b7 b6 0 0: TRDIOC1 pin not used 0 1: P6_7 assigned 1 0: P10_7 assigned 1 1: Do not set. R/W b7 TRDIOD1SEL1 R/W

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 434 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.17 Operating Example

Figure 21.23 Operating Example in PWM3 Mode TRD0 register value Count source TRDIOA0 output 0000h FFFFh TRDIOB0 output m: Value set in TRDGRA0 register n: Value set in TRDGRA1 register p: Value set in TRDGRB0 register q: Value set in TRDGRB1 register m n p q TSTART0 bit in TRDSTR register Set to 0 by a program. Set to 0 by a program. m+1 n+1 m-n p+1 q+1 p-q Count stops Output “H” at compare match with the TRDGRA1 register Set to 0 by a program.Set to 0 by a program. Set to 0 by a program. Transfer m m Next data Transfer m Output “L” at compare match with the TRDGRA0 register Transfer from the buffer register to the general register Transfer from the buffer register to the general register Initial output “L” j = either A or B The above applies under the following conditions:

• Both the TOA0 and TOB0 bits in the TRDOCR register are set to 0 (initial output at low, high-level at compare match with the TRDGRj1 register, low-level output at compare match with the TRDGRj0 register).
• The BFC0 bit in the TRDMR register is set to 1 (TRDGRC0 register is used as the buffer register of the TRDGRA0 register). CSEL0 bit in TRDSTR register IMFA bit in TRDSR0 register IMFB bit in TRDSR0 register TRDGRA0 register TRDGRC0 register

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 435 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.8.18 A/D Trigger Generation

A compare match signal with registers TRDi (i = 0 or 1) and TRDGRji (j = A, B, C, or D) can be used as the conversion start trigger of the A/D converter. The TRDADCR register is used to select which compare match is used.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 436 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.9 Timer RD Interrupt

Timer RD generates the timer RDi (i = 0 or 1) interr upt request based on six sources for each timer RD0 and timer RD1. The timer RD interrupt uses the single TRDiIC register (bits IR, and ILVL0 to ILVL2), and a single vector for each timer RD0 and timer RD1. Table 21.17 li sts the Registers Associated with Timer RD Interrupt, and Figure 21.24 shows a Block Diagram of Timer RD Interrupt. Figure 21.24 Block Diagram of Timer RD Interrupt As with other maskable interrupts, the timer RD interrupt is controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since the inte rrupt source (timer RD interrupt) is generated by a combination of multiple interrupt request sources, the following differences from other maskable interrupts apply:

• When bits in the TRDSRi register corresponding to bits set to 1 in the TRDIERi register are set to 1 (interrupt enabled), the IR bit in the TRDiIC register is set to 1 (interrupt requested).
• When either bits in the TRDSRi register or bits in the TRDIERi register corresponding to bits in the TRDSRi register, or both of them, are set to 0, the IR bit is set to 0 (no interrupt requested). Therefore, even though the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be maintained.
• When the conditions of other request sources are met, the IR bit remains 1.
• When multiple bits in the TRDIERi register are se t to 1, which request source causes an interrupt is determined by the TRDSRi register.
• Since each bit in the TRDSRi register is not automatically set to 0 even if the interrupt is acknowledged, set each bit to 0 in the interrupt routine. For information on how to set these bits to 0, refer to the descriptions of Table 21.17 Registers Associat ed with Timer RD Interrupt Timer RD Status Register Timer RD Interrupt Enable Register Timer RD Interrupt Control Register Timer RD0 TRDSR0 TRDIER0 TRD0IC Timer RD1 TRDSR1 TRDIER1 TRD1IC Timer RDi interrupt request (IR bit in TRDiIC register) IMFA bit IMIEA bit IMFB bit IMIEB bit IMFC bit IMIEC bit IMFD bit IMIED bit UDF bit OVF bit OVIE bit i = 0 or 1 IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register Timer RDi

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 437 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Refer to 12.3 Interrupt Control for information on the TRDiIC register and 12.1.5.2 Relocatable Vector Tables for the interrupt vectors.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 438 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.10 Notes on Timer RD

21.10.1 TRDSTR Register

• Set the TRDSTR register using the MOV instruction.
• When the CSELi (i = 0 or 1) is set to 0 (count stops at compare match be tween registers TRDi and TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is written to the TSTARTi bit. When the CSELi bit is set to 0, write 0 to the TSTA RTi bit to change other bits without changing the TSTARTi bit. To stop counting by a program, write 0 to the TSTARTi bit after setting the CSELi bit to 1. If 1 is written to the CSELi bit and 0 is written to the TSTARTi bit is set to 0 at the same time (with one instruction), the count cannot be stopped.
• Table 21.18 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops while the TRDIOji (j = A, B, C, or D) pin is used for the timer RD output.21.10.2 TRDi Register (i = 0 or 1)
• When writing the value to the TRDi register by a prog ram while the TSTARTi bit in the TRDSTR register is set to 1 (count starts), avoid overlapping with the timin g for setting the TRDi register to 0000h, and then write. If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to the TRDi register, the value is not written and the TRDi register is set to 0000h. These notes apply when selecting the following by bits CCLR2 to CCLR0 in the TRDCRi register. - 001b (Clear by the TRDi register at compare match with the TRDGRAi register.) - 010b (Clear by the TRDi register at compare match with the TRDGRBi register.) - 011b (Synchronous clear) - 101b (Clear by the TRDi register at compare match with the TRDGRCi register.) - 110b (Clear by the TRDi register at compare match with the TRDGRDi register.)
• When writing the value to the TRDi register and continuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program example MOV .W #XXXXh, TRD0 ;Write JMP.B L1 ;JMP.B L1: MOV .W TRD0,DATA ;Read Table 21.18 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops Stopping Count TRDIOji Pin Output when Count Stops When the CSELi bit is set to 1, write 0 to the TSTARTi bit and the count stops. Holds the output level immediately before the count stops. When the CSELi bit is set to 0, the count stops at compare match between registers TRDi and TRDGRAi. Holds the output level after the output changes by the compare match.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 439 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.10.3 TRDSRi Register (i = 0 or 1)

When writing the value to the TRDSRi register and con tinuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program example MOV .B #XXh, TRDSR0 ;Write JMP.B L1 ;JMP.B L1: MOV .B TRDSR0,DA TA ;Read

21.10.4 Count Source Switching

• Switch the count source after the count stops. Switching procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change bits TCK2 to TCK0 in the TRDCRi register.
• When changing the count source fr om fOCO40M to another source and stopping fOCO40M, wait two or more cycles of f1 after setting the clock switch, and then stop fOCO40M. Switching procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change bits TCK2 to TCK0 in the TRDCRi register. (3) Wait for two or more cycles of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).

21.10.5 Input Capture Function

• The pulse width of the input capture signal should be se t to three or more cycles of the timer RD operating clock (refer to Table 21.1 Timer RD Operating Clocks).
• The value of the TRDi register is transferred to the TRDGRji register two or three cycles of the timer RD operating clock after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C, or D) (when the digital filter is not used).

21.10.6 Reset Synchronous PWM Mode

• When reset synchronous PWM mode is used for motor control, make sure OLS0 = OLS1.
• Set to reset synchronous PWM mode by the following procedure: Switching procedure (1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode). (3) Set bits CMD1 to CMD0 to 01b (reset synchronous PWM mode). (4) Set the other registers asso ciated with timer RD again.

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 440 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

21.10.7 Complementary PWM Mode

• When complementary PWM mode is used for motor control, make sure OLS0 = OLS1.
• Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure. Switching procedure: When setting to complementary PW M mode (including re-set), or changing the transfer timing from the buffer register to the general register in complementary PWM mode. (1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode). (3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode). (4) Set the registers associated with other timer RD again. Switching procedure: When stopping complementary PWM mode (1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode).
• Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation. When changing the PWM wave form, transfer the valu es written to registers TRDGRD0, TRDGRC1, and TRDGRD1 to registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation. However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register). The PWM period cannot be changed.
• If the value set in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1, in that order, when changing from increment to decrement operation. When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR register are set to 11b (complementary PWM mode, buffer data transferred at compare match between registers TRD0 and TRDGRA0), the content of the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to registers such as the TRDGRA0 register. Figure 21.25 Operation at Compare Match between Registers TRD0 and TRDGRA0 in Complementary PWM Mode No change IMFA bit in TRDSR0 register Transfer from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register TRD0 register count value TRDGRA0 register setting value m m+1 Set to 0 by a program. No transfer from buffer register When bits CMD1 to CMD0 in the TRDFCR register are set to 11b (transfer from the buffer register to the general register at compare match between registers TRD0 and TRDGRA0).

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 441 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

• The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment operation. The UDF bit is set to 1 when changi ng between 1, 0, and FFFFh operation. Also, when bits CMD1 to CMD0 in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at underflow in the TRD1 register), the conten t of the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDG RA1, and TRDGRB1). During FFFFh, 0, 1 operation, data are not transferred to register s such as the TRDGRB0 register. Also, at this time, the OVF bit remains unchanged. Figure 21.26 Operation when TRD1 Register Underflows in Complementary PWM Mode No change UDF bit in TRDSR0 register Transfer from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register TRD0 register count value Set to 0 by a program. No transfer from buffer register When bits CMD1 to CMD0 in the TRDFCR register are set to 10b (transfer from the buffer register to the general register when the TRD1 register underflows). OVF bit in TRDSR0 register FFFFh

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 442 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

• Using bits CMD1 to CMD0, select the timing of data tran sfer from the buffer regist er to the general register. However, transfer takes place with the following timing in spit e of the values of bits CMD1 to CMD0 in the following cases: Buffer register value ≥ TRDGRA0 register value: Transfer takes place at underflow of the TRD1 register. After this, when the buffer register is set to 0001h or above and a value smaller than the value of the TRDGRA0 register, and the TRD1 regist er underflows for the first time afte r setting, the value is transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1 to CMD0. Figure 21.27 Operation when Buffer Register Value ≥ TRDGRA0 Register Value in Complementary PWM Mode 0000h TRDGRD0 register TRDIOB0 output n3n2 m+1 n2 n1 n3n2 n2 n1n1TRDGRB0 register Transfer at TRD1 register underflow because of n3 > m Transfer at TRD1 register underflow because of first setting to n2 < m TRDIOD0 output m: Value set in TRDGRA0 register The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match between registers TRD0 and TRDGRA0 in complementary PWM mode).
• Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active high for normal-phase and counter-phase). TRD0 register count value TRD1 register count value Transfer with timing set by bits CMD1 to CMD0 Transfer with timing set by bits CMD1 to CMD0 Transfer Transfer TransferTransfer

1. Timer RD REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 443 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group When the value of the buffer register is set to 0000h: Transfer takes place at compare match between registers TRD0 and TRDGRA0. After this, when the buffer register is set to 0001h or above and a value than smaller the value of the TRDGRA0 register, and a compare match occurs betw een registers TRD0 and TRDGRA0 for the first time after setting, the value is transferred to the general regi ster. After that, the value is transferred with the timing selected by bits CMD0 and CMD1. Figure 21.28 Operation when Buffer Register Value Is Set to 0000h in Complementary PWM Mode

21.10.8 Count Source fOCO40M

• The count source fOCO40M can be used with supply voltage VCC = 2.7 to 5.5 V . For supply voltage other than that, do not set bits TCK2 to TCK0 in regi sters TRDCR0 and TRDCR to 110b (fOCO40M selected as the count source). 0000h TRDGRD0 register TRDIOB0 output m+1 0000h n1 0000hn1 n1n2TRDGRB0 register Transfer Transfer at compare match between registers TRD0 and TRDGRA0 because content of TRDGRD0 register is set to 0000h. Transfer at compare match between registers TRD0 and TRDGRA0 because of first setting to 0001h ≤ n1 < m Transfer with timing set by bits CMD1 to CMD0 TRDIOD0 output m: Value set in TRDGRA0 register The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (dat a in the buffer register is transferred at TRD1 register underfl ow in PWM mode).
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active high for normal-phase and counter-phase). TRD0 register count value TRD1 register count value Transfer with timing set by bits CMD1 to CMD0 Transfer Transfer Transfer

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 444 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 22. Timer RE Timer RE has a 4-bit counter and 8-bit counter.

22.1 Introduction

Timer RE supports the following two modes:

• Real-time clock mode A 1-second signal from fC4 is generated and seconds, minutes, hours, and days of the week are counted.
• Output compare mode A count source is co unted and compare matches are detected. The count source for timer RE is the operating clock that regulates the timing of timer operations. Table 22.1 lists the Timer RE Pin Configuration. Table 22.1 Timer RE Pin Configuration Pin Name Assigned Pin I/O Function TREO P11_7 Output Function differs according to the mode. Refer to descriptions of individual modes for details.

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 445 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.2 Real-Time Clock Mode

In real-time clock mode, a 1-second si gnal is generated from fC4 using a divide-by-2 frequency divider, 4-bit counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 22.1 shows a Block Diagram of Real-Time Clock Mode, Table 22.2 lists the Real-Time Clock Mode Specifications, and Table 22.3 lists Interrupt Sources. Figure 22.2 shows th e Definition of Time Representation and Figure 22.3 shows an Operating Example in Real-Time Clock Mode. Figure 22.1 Block Diagram of Real-Time Clock Mode TREWK register TREHR register TREMIN register TRESEC register H12_H24 bit PM bit MNIE HRIE WKIE 000 DYIE SEIE Timer RE interrupt INT bit BSY bit Overflow Timing control Data bus Overflow Overflow TREO pin (1s) Overflow (1/256)(1/16) fC4 (8.192 kHz) RCS6 to RCS4 = 000b = 010b = 100b = 011b TOENA = 001bfC 8-bit counter4-bit counter1/2 TOENA, H12_H24, PM, INT: Bits in TRECR1 register SEIE, MNIE, HRIE, DYIE, WKIE: Bits in TRECR2 register BSY: Bit in registers TRESEC, TREMIN, TREHR and TREWK RCS4 to RCS6: Bits in TRECSR register

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 446 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 22.2 Real-Time Clock Mode Specifications Item Specification Count source fC4 Count operation Increment Count start condition 1 (count starts) is wr itten to TSTART bit in TRECR1 register. Count stop condition 0 (count stops) is wr itten to TSTART bit in TRECR1 register. Interrupt request generation timing Select either one of the following:

• Update of second data
• Update of minute data
• Update of hour data
• Update of day of week data
• When day of week data is set to 000b (Sunday). TREO pin function Programmable I/O port or output of f2, fC, f4, f8, or 1 Hz Read from timer When readin g TRESEC, TREMIN, TREHR, or TREWK register, the count value can be read. The values read from registers TRESEC, TREMIN, and TREHR are represented by the BCD code. Write to timer When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer stops), the value can be written to registers TRESEC, TREMIN, TREHR, and TREWK. The values written to registers TRESEC, TREMIN, and TREHR are represented by the BCD codes. Selectable function • 12-hour mo de/24-hour mode switch function

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 447 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.2.1 Timer RE Second Da ta Register (TRESEC) in Real-Time Clock Mode

22.2.2 Timer RE Minute Da ta Register (TREMIN) in Real-Time Clock Mode

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BSY SC12 SC11 SC10 SC03 SC02 SC01 SC00 A f t e r R e s e t XXXXXXXX Bit Symbol Bit Name Function Setting Range R/W b0 SC00 1st digit of second count bit Count 0 to 9 every second. When the digit moves up, 1 is added to the 2nd digit of second. 0 to 9 (BCD code) R/W b1 SC01 R/W b2 SC02 R/W b3 SC03 R/W b4 SC10 2nd digit of second count bit When counting 0 to 5, 60 seconds are counted. 0 to 5 (BCD code) R/W b5 SC11 R/W b6 SC12 R/W b7 BSY Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN, TREHR, and TREWK are being updated. R Address 0119h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BSY MN12 MN11 MN10 MN03 MN02 MN01 MN00 A f t e r R e s e t XXXXXXXX Bit Symbol Bit Name Function Setting Range R/W b0 MN00 1st digit of minute count bit Count 0 to 9 every minute. When the digit moves up, 1 is added to the 2nd digit of minute. 0 to 9 (BCD code) R/W b1 MN01 R/W b2 MN02 R/W b3 MN03 R/W b4 MN10 2nd digit of minute count bit When counting 0 to 5, 60 minutes are counted. 0 to 5 (BCD code) R/W b5 MN11 R/W b6 MN12 R/W b7 BSY Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN, TREHR, and TREWK are being updated. R

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 448 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.2.3 Timer RE Hour Data Register (TREHR) in Real-Time Clock Mode

22.2.4 Timer RE Day of W eek Data Register (TREWK) in Real-Time Clock Mode

B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BSY — HR11 HR10 HR03 HR02 HR01 HR00 A f t e r R e s e t XXXXXXXX Bit Symbol Bit Name Function Setting Range R/W b0 HR00 1st digit of hour count bit Count 0 to 9 every hour. When the digit moves up, 1 is added to the 2nd digit of hour. 0 to 9 (BCD code) R/W b1 HR01 R/W b2 HR02 R/W b3 HR03 R/W b4 HR10 2nd digit of hour count bit Count 0 to 1 when the H12_H24 bit is set to 0 (12-hour mode). Count 0 to 2 when the H12_H24 bit is set to 1 (24-hour mode). 0 to 2 (BCD code) R/W b5 HR11 R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 BSY Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN, TREHR, and TREWK are updated. R Address 011Bh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BSY — — — — WK2 WK1 WK0 A f t e r R e s e t XXXXXXXX Bit Symbol Bit Name Function R/W b0 WK0 Day of week count bit b2 b1 b0 0 0 0: Sunday 0 0 1: Monday 0 1 0: Tuesday 0 1 1: Wednesday 1 0 0: Thursday 1 0 1: Friday 1 1 0: Saturday 1 1 1: Do not set. R/W b1 WK1 R/W b2 WK2 R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 — b6 — b7 BSY Timer RE busy flag This bit is set to 1 while registers TRESEC, TREMIN, TREHR, and TREWK are updated. R

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 449 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.2.5 Timer RE Control Register 1 (TRECR1) in Real-Time Clock Mode

Note: 1. This bit is automatically modified while timer RE counts. Figure 22.2 Definition of Time Representation Address 011Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TSTART H12_H24 PM TRERST INT TOENA TCSTF — A f t e r R e s e t XXXXX0XX Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 TCSTF Timer RE count status flag 0: Count stopped 1: Counting R b2 TOENA TREO pin output enable bit 0: Clock output disabled 1: Clock output enabled R/W b3 INT Interrupt request timing bit Set to 1 in real-time clock mode. R/W b4 TRERST Timer RE reset bit When setting this bit to 0 after setting it to 1, the following will occur:

• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and TSTART in the TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and the 4-bit counter is set to 0h. R/W b5 PM A.m./p.m. bit When the H12_H24 bit is set to 0 (12-hour mode) (1) 0: a.m. 1: p.m. When the H12_H24 bit is set to 1 (24-hour mode), its value is undefined. R/W b6 H12_H24 Operating mode select bit 0: 12-hour mode 1: 24-hour mode R/W b7 TSTART Timer RE count start bit 0: Count stops 1: Count starts R/W Noon H12_H24 bit = 1 (24-hour mode) Content of PM bit 0 (a.m.) 1 (p.m.) Content of TREHR Register H12_H24 bit = 0 (12-hour mode) Content of TREWK register 000 (Sunday) 0 1 2 3 4 5 7 9 11 13 15 176 8 10 12 14 16 0 1 2 3 4 5 7 9 11 1 3 56 8 10 0 2 4 H12_H24 bit = 1 (24-hour mode) Content of PM bit 1 (p.m.) Content of TREHR Register H12_H24 bit = 0 (12-hour mode) Content of TREWK register 000 (Sunday) 18 19 20 21 22 23 1 30 2 ⋅⋅⋅ 6 7 8 9 10 11 1 30 2 Date changes ⋅⋅⋅ ⋅⋅⋅0 (a.m.) 001 (Monday) ⋅⋅⋅ PM, H12_H24: Bits in TRECR1 register The above applies when counting starts from a.m. 0 on Sunday.

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 450 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.2.6 Timer RE Control Register 2 (TRECR2) in Real-Time Clock Mode

Note: 1. Do not set multiple enable bits to 1 (interrupt enabled). Address 011Dh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol COMIE WKIE DYIE HRIE MNIE SEIE SEIE05 SEIE025 A f t e r R e s e t XXXXXXXX Bit Symbol Bit Name Function R/W b0 SEIE025 Periodic interrupt triggered every 0.25 seconds enable bit (1) 0: Periodic interrupt triggered every 0.25 seconds is disabled 1: Periodic interrupt triggered every 0.25 seconds is enabled R/W b1 SEIE05 Periodic interrupt triggered every 0.5 seconds enable bit (1) 0: Periodic interrupt triggered every 0.5 seconds is disabled 1: Periodic interrupt triggered every 0.5 seconds is enabled R/W b2 SEIE Periodic interrupt triggered every second enable bit (1) 0: Periodic interrupt triggered every second is disabled 1: Periodic interrupt triggered every second is enabled R/W b3 MNIE Periodic interrupt triggered every minute enable bit (1) 0: Periodic interrupt triggered every minute is disabled 1: Periodic interrupt triggered every minute is enabled R/W b4 HRIE Periodic interrupt triggered every hour enable bit (1) 0: Periodic interrupt triggered every hour is disabled 1: Periodic interrupt triggered every hour is enabled R/W b5 DYIE Periodic interrupt triggered every day enable bit (1) 0: Periodic interrupt triggered every day is disabled 1: Periodic interrupt triggered every day is enabled R/W b6 WKIE Periodic interrupt triggered every week enable bit (1) 0: Periodic interrupt triggered every week is disabled 1: Periodic interrupt triggered every week is enabled R/W b7 COMIE Compare match interrupt enable bit Set to 0 in real-time clock mode. R/W Table 22.3 Interrupt Sources Source Interrupt Source Interrupt Enable Bit Periodic interrupt triggered every week The value of the TREWK register is set to 000b (Sunday) (1-week period). WKIE Periodic interrupt triggered every day The TREWK register is updated (1-day period). DYIE Periodic interrupt triggered every hour The TREHR register is updated (1-hour period). HRIE Periodic interrupt triggered every minute The TREMIN register is updated (1-minute period). MNIE Periodic interrupt triggered every second The TRESEC register is updated (1-second period). SEIE Periodic interrupt triggered every 0.5 seconds The 8-bit counter is updated (0.5-second period). SEIE05 Periodic interrupt triggered every 0.25 seconds The 8-bit counter is updated (0.25-second period). SEIE025

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 451 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.2.7 Timer RE Count Sour ce Select Register (TRECSR) in Real-Time Clock

Note: 1. Write to bits RCS4 to RCS6 when the TOENA bit in the TRECR1 register is set to 0 (clock output disabled). Address 011Eh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — RCS6 RCS5 RCS4 RCS3 RCS2 RCS1 RCS0 A f t e r R e s e t 00001000 Bit Symbol Bit Name Function R/W b0 RCS0 Count source select bit Set to 00b in real-time clock mode. R/W b1 RCS1 R/W b2 RCS2 4-bit counter select bit Set to 0 in real-time clock mode. R/W b3 RCS3 Real-time clock mode select bit Set to 1 in real-time clock mode. R/W b4 RCS4 Clock output select bit (1) b6 b5 b4 0 0 0: f2 0 0 1: fC 0 1 0: f4 0 1 1: 1 Hz 1 0 0: f8 Other than above: Do not set. R/W b5 RCS5 R/W b6 RCS6 R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 452 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.2.8 Operating Example

Figure 22.3 Operating Example in Real-Time Clock Mode IR bit in TREIC register IR bit in TREIC register Bits WK2 to WK0 in TREWK register (when SEIE bit in TRECR2 register is set to 1 (periodic interrupt triggered every second is enabled)) (when MNIE bit in TRECR2 register is set to 1 (periodic interrupt triggered every minute is enabled)) PM bit in TRECR1 register Bits HR11 to HR00 in TREHR register (Not change) Set to 0 when an interrupt is acknowledged or by a program. Bits MN12 to MN00 in TREMIN register 58 59 00 BSY bit Approx. 62.5 ms Bits SC12 to SC00 in TRESEC register BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK Approx. 62.5 ms (No change) (No change)

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 453 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.3 Output Compare Mode

In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and a compare value match is detected with the 8-bit counter. Figure 22.4 shows a Block Diagram of Output Compare Mode, Table 22.4 lists the Output Compare Mode Specifications, and Figure 22.5 shows an Operating Example in Output Compare Mode. Figure 22.4 Block Diagram of Output Compare Mode Table 22.4 Output Compare Mode Specifications Item Specification Count sources f4, f8, f32, fC4 Count operations • Increment

• When the 8-bit counter value matches the TREMIN register content, the value is set back to 00h and the count continues. The count value is retained while the count stops. Count periods • When RCS2 = 0 (4-bit counter is not used) 1/fi x 2 x (n+1)
• When RCS2 = 1 (4-bit counter is used) 1/fi x 32 x (n+1) fi: Frequency of count source n: Value set in TREMIN register Count start condition 1 (count starts) is written to the TSTART bit in the TRECR1 register. Count stop condition 0 (count stops) is write to the TSTART bit in the TRECR1 register. Interrupt request generation timing When the contents of the 8-bit counter and the TREMIN register match. TREO pin function Select either one of the following:
• Programmable I/O port
• Output of f2, fC, f4, or f8
• Compare output Read from timer When reading the TRESEC register, the 8-bit counter value can be read. When reading the TREMIN register, the compare value can be read. Write to timer Writing to the TRESEC register is disabled. When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer stops), writing to the TREMIN register is enabled. Selectable functions • Selectable use of 4-bit counter
• Compare output function Every time the 8-bit counter value matches the TREMIN register content, the TREO output polarity is inverted. The TREO pin outputs a low-level signal after reset is deasserted and timer RE is reset by the TRERST bit in the TRECR1 register. The output level is retained by setting the TSTART bit to 0 (count stops). fC4 f32 4-bit counter 8-bit counter TRESEC TREMIN RCS2 = 1 RCS2 = 0 COMIE Timer RE interrupt Match signal = 00b = 01b = 10b = 11b RCS1 to RCS0 TRERST, TOENA: Bits in TRECR1 register COMIE: Bit in TRECR2 register RCS0 to RCS2, RCS4 to RCS6: Bits in TRECSR register TQ R Reset TRERST Data bus Comparison circuit RCS6 to RCS4 =000b =010b =100b =110b TOENA =001bfC TREO pin

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 454 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.3.1 Timer RE Counter Data Register (TRESEC) in Output Compare Mode

22.3.2 Timer RE Compare Data Register (TREMIN) in Output Compare Mode

B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit Function R/W b7 to b0 8-bit counter data can be read. Even if timer RE stops counting, the count value is retained. The TRESEC register is set to 00h at the compare match. R Address 0119h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit Function R/W b7 to b0 8-bit compare data is stored. R

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 455 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.3.3 Timer RE Control Register 1 (TRECR1) in Output Compare Mode

22.3.4 Timer RE Control Register 2 (TRECR2) in Output Compare Mode

Note: 1. Do not set multiple enable bits to 1 (interrupt enabled). Address 011Ch B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TSTART H12_H24 PM TRERST INT TOENA TCSTF — A f t e r R e s e t XXXXX0XX Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 TCSTF Timer RE count status flag 0: Count stopped 1: Counting R b2 TOENA TREO pin output enable bit 0: Clock output disabled 1: Clock output enabled R/W b3 INT Interrupt request timing bit Set to 0 in output compare mode. R/W b4 TRERST Timer RE reset bit When setting this bit to 0 after setting it to 1, the following will occur.

• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and TSTART in the TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and the 4-bit counter is set to 0h. R/W b6 H12_H24 Operating mode select bit Set to 0 in output compare mode. R/W b7 TSTART Timer RE count start bit 0: Count stops 1: Count starts R/W Address 011Dh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol COMIE WKIE DYIE HRIE MNIE SEIE SEIE05 SEIE025 A f t e r R e s e t XXXXXXXX Bit Symbol Bit Name Function R/W b0 SEIE025 Periodic interrupt triggered every 0.25 seconds enable bit (1) Set to 0 in output compare mode. R/W b1 SEIE05 Periodic interrupt triggered every 0.5 seconds enable bit (1) R/W b2 SEIE Periodic interrupt triggered every second enable bit (1) R/W b3 MNIE Periodic interrupt triggered every minute enable bit (1) R/W b4 HRIE Periodic interrupt triggered every hour enable bit (1) R/W b5 DYIE Periodic interrupt triggered every day enable bit (1) R/W b6 WKIE Periodic interrupt triggered every week enable bit (1) R/W b7 COMIE Compare match interrupt enable bit 0: Compare match interrupt disabled 1: Compare match interrupt enabled R/W

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 456 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.3.5 Timer RE Count Sour ce Select Register (TRECS R) in Output Compare

Notes: 1. Write to bits RCS0 to RCS1 when the TCSTF bit in the TRECR1 register is set to 0 (count stopped). 2. Write to bits RCS4 to RCS6 when the TOENA bit in the TRECR1 register is set to 0 (clock output disabled). Address 011Eh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — RCS6 RCS5 RCS4 RCS3 RCS2 RCS1 RCS0 A f t e r R e s e t 00001000 Bit Symbol Bit Name Function R/W b0 RCS0 Count source select bit (1) b1 b0 0 0: f4 0 1: f8 1 0: f32 1 1: fC4 R/W b1 RCS1 R/W b2 RCS2 4-bit counter select bit 0: Not used 1: Used R/W b3 RCS3 Real-time clock mode select bit Set to 0 in output compare mode. R/W b4 RCS4 Clock output select bit (2) b6 b5 b4 0 0 0: f2 0 0 1: fC 0 1 0: f4 1 0 0: f8 1 1 0: Compare output Other than above: Do not set. R/W b5 RCS5 R/W b6 RCS6 R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. —

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 457 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.3.6 Operating Example

Figure 22.5 Operating Example in Output Compare Mode 2 cycles of maximum count source 00h 8-bit counter content (hexadecimal number) Count starts Time TSTART bit in TRECR1 register IR bit in TREIC register The above applies under the following conditions: TOENA bit in TRECR1 register = 1 (clock output enabled) COMIE bit in TRECR2 register = 1 (compare match interrupt enabled) Bits RCS6 to RCS5 in TRECSR register = 11b (compare output) Set to 1 by a program. Set to 0 when an interrupt request is acknowledged or by a program. TREMIN register setting value Match TREO output “H” “L” TCSTF bit in TRECR1 register The output polarity is inverted at the compare match. Match Match

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 458 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.4 Notes on Timer RE

22.4.1 Reset

A reset input does not reset the timer RE data registers th at store data of seconds, minutes, hours, and days of the week. This requires the initial setting of all registers after power on.

22.4.2 Starting and Stopping Count

Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the TRECR1 register. When the TSTART bit is set to 1 (count starts), timer RE starts counting and the TCSTF bit is set to 1 (count starts). It takes up to two cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with timer RE (1) other than the TCSTF bit. Similarly, when the TSTART bit is set to 0 (count stops), timer RE stops counting and the TCSTF bit is set to 0 (count stops). It takes the time for up to two cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not ac cess registers associated with timer RE other than the TCSTF bit. Note: 1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and TRECSR

22.4.3 Register Setting

Write to the following registers or bits while timer RE is stopped.

• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24, PM, and INT in the TRECR1 register
• Bits RCS0 to RCS3 in the TRECSR register Timer RE is stopped while bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped). Set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the TRECR2 register. Figure 22.6 shows a Setting Example in Real-Time Clock Mode.

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 459 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 22.6 Setting Example in Real-Time Clock Mode Stop timer RE operation TCSTF in TRECR1 = 0? TSTART in TRECR1 = 0 TRERST in TRECR1 = 1 TRERST in TRECR1 = 0 Set registers TRECSR, TRESEC, TREMIN, TREHR, TREWK, and bits H12_H24, PM, and INT in the TRECR1 register Set TRECR2 TSTART in TRECR1 = 1 TCSTF in TRECR1 = 1? TREIC ← 00h (timer RE interrupt disabled) Set TREIC (IR bit ← 0, select the interrupt priority level) Reset the timer RE registers and the control circuit Select the clock output Select the clock source Seconds, minutes, hours, days of week, operating mode Set the a.m./p.m., interrupt timing Select the interrupt source Start timer RE operation TOENA in TRECR1 = 0 Disable the timer RE clock output (when necessary) TOENA in TRECR1 = 1 Enable the timer RE clock output (when necessary)

1. Timer RE REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 460 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

22.4.4 Time Reading Procedur e in Real-Time Clock Mode

In real-time clock mode, read registers TRESEC, TR EMIN, TREHR, and TREWK wh en time data is updated and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (data is not being updated). When reading several registers, an incorrect time will be read if data is updated before another register is read after reading any register. In order to prevent this, use the reading procedure shown below.

• Using an interrupt Read necessary contents of registers TRESEC, TR EMIN, TREHR, and TREWK and the PM bit in the TRECR1 register in the timer RE interrupt routine.
• Monitoring with a program 1 Monitor the IR bit in the TREIC register with a prog ram and read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC register is set to 1 (timer RE interrupt request generated).
• Monitoring with a program 2 (1) Monitor the BSY bit. (2) Monitor until the BSY bit is set to 0 after the BSY bi t is set to 1 (approximately 62.5 ms while the BSY bit is set to 1). (3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the BSY bit is set to 0.
• Using read results if they are the same value twice (1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register. (2) Read the same register as (1) and compare the contents. (3) Recognize as the correct value if the contents match. If the contents do not ma tch, repeat until the read contents match with the previous contents. Also, when reading several registers, read them as continuously as possible.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 461 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 23. Timer RG Timer RG is a 16-bit timer with two I/O pins.

23.1 Introduction

Timer RG uses either f1 or fOCO40M as its operating clock. Table 23.1 lists the Timer RG Operating Clocks. Figure 23.1 shows the Timer RG Block Diagram, and Table 23.2 lists the Timer RG Pin Configuration. Timer RG supports the following three modes:

• Timer mode - Input capture function: Count at the rising edge, falling edge, or both rising and falling edges - Output compare function: Low-level output, high-level output, or toggle output
• PWM mode: PWM output available with any duty
• Phase counting mode: Automatic measurement available for the counts of the two-phase encoder Table 23.1 Timer RG Operating Clocks Condition Timer RG Operating Clock The count source is f1, f2, f4, f8, f32, TRGCLKA input, or TRGCLKB input. (Bits TCK2 toTCK0 in the TRGCR register are set to 000b to 101b, and 111b.) The count source is fOCO40M. (Bits TCK2 toTCK0 in the TRGCR register are set to 110b.) fOCO40M

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 462 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 23.1 Timer RG Block Diagram Table 23.2 Timer RG Pin Configuration Pin Name Assigned Pin I/O Function TRGCLKA P13_5 Input • In phase counting mode A-phase input

• In other than phase counting mode External clock A input TRGCLKB P13_7 Input • In phase counting mode B-phase input
• In other than phase counting mode External clock B input TRGIOA P13_4 I/O • In timer mode (output compare function) TRGGRA output-compare output
• In timer mode (input capture function) TRGGRA input-capture input
• In PWM mode PWM output TRGIOB P13_6 I/O • In timer mode (output compare function) TRGGRB output-compare output
• In timer mode (input capture function) TRGGRB input-capture input Data bus Timer RG Control Circuit TRGCLKA TRGCLKB Count source selection circuit f1, f2, f4, f8, f32, fOCO40M TRGIOB TRGIOA Comparator TRGIER register TRG register TRGMR register TRGCNTC register TRGCR register TRGIOR register TRGGRB register TRGGRA register TRGGRD register TRGGRC register TRGSR register Timer RG interrupt request

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 463 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.2 Registers

23.2.1 Timer RG Mode Register (TRGMR)

MDF Bit (Phase Counting Mode Select Bit) When the MDF bit is set to 0, the counter counts the count source set by bits TCK0 to TCK2 in the TRGCR register. When the MDF bit is set to 1, the counter counts the phase of input signals from the TRGCLKj pin (j = A or B) as listed in Table 23.12 Increment and Decrement Conditions for TRG Register. Address 0170h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol TSTART — DFCK1 DFCK0 DFB DFA MDF PWM A f t e r R e s e t 01000000 Bit Symbol Bit Name Function R/W b0 PWM PWM mode select bit 0: Timer Mode 1: PWM mode R/W b1 MDF Phase counting mode select bit 0: Increment 1: Phase counting mode R/W b2 DFA Digital filer function select bit for TRGIOA pin 0: Digital filter function not used 1: Digital filter function used R/W b3 DFB Digital filer function select bit for TRGIOB pin 0: Digital filter function not used 1: Digital filter function used R/W b4 DFCK0 Digital filter function clock select bit b5 b4 0 0: f32 0 1: f8 1 0: f1 1 1: Clock selected by bits TCK0 to TCK2 in TRGCR register R/W b5 DFCK1 R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b7 TSTART TRG count start bit 0: Count stops 1: Count starts R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 464 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.2.2 Timer RG Count C ontrol Register (TRGCNTC)

The TRGCNTC register is used in phase counting mode. This register sets its count conditions. Address 0171h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol CNTEN7 CNTEN6 CNTEN5 CNTEN 4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 A f t e r R e s e t 0000000 0 Bit Symbol Bit Name Function R/W b0 CNTEN0 Counter enable bit 0 0: Disabled 1: Decrement When TRGCLKA input is high and at the rising edge of TRGCLKB input R/W b1 CNTEN1 Counter enable bit 1 0: Disabled 1: Decrement When TRGCLKB input is low and at the rising edge of TRGCLKA input R/W b2 CNTEN2 Counter enable bit 2 0: Disabled 1: Decrement When TRGCLKA input is low and at the falling edge of TRGCLKB input R/W b3 CNTEN3 Counter enable bit 3 0: Disabled 1: Decrement When TRGCLKB input is high and at the falling edge of TRGCLKA input R/W b4 CNTEN4 Counter enable bit 4 0: Disabled 1: Increment When TRGCLKB input is low and at the falling edge of TRGCLKA input R/W b5 CNTEN5 Counter enable bit 5 0: Disabled 1: Increment When TRGCLKA input is high and at the falling edge of TRGCLKB input R/W b6 CNTEN6 Counter enable bit 6 0: Disabled 1: Increment When TRGCLKB input is high and at the rising edge of TRGCLKA input R/W b7 CNTEN7 Counter enable bit 7 0: Disabled 1: Increment When TRGCLKA input is low and at the rising edge of TRGCLKB input R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 465 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.2.3 Timer RG Cont rol Register (TRGCR)

Note: 1. In phase counting mode, the settings of bits TCK0 to TCK2 and bits CKEG0 and CKEG1 are disabled and the operation of phase counting mode has priority. Address 0172h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 A f t e r R e s e t 10000000 Bit Symbol Bit Name Function R/W b0 TCK0 Count source select bit (1) b2 b1 b0 0 0 0: f1 0 0 1: f2 0 1 0: f4 0 1 1: f8 1 0 0: f32 1 0 1: TRGCLKA input 1 1 0: fOCO40M 1 1 1: TRGCLKB input R/W b1 TCK1 R/W b2 TCK2 R/W b3 CKEG0 External clock active edge select bit (1) b4 b3 0 0: Count at the rising edge 0 1: Count at the falling edge 1 0: Count at both the rising/falling edges 1 1: Do not set. R/W b4 CKEG1 R/W b5 CCLR0 TRG register clear source select bit b6 b5 0 0: Clear disabled 0 1: TRG register cleared by input capture or compare match with TRGGRA register 1 0: TRG register cleared by input capture or compare match with TRGGRB register 1 1: Do not set. R/W b6 CCLR1 R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. —

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 466 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.2.4 Timer RG Interrupt Enable Register (TRGIER)

B i t b 7b 6b 5b 4b 3b 2b 1b 0 S y m b o l ———— O V I E U D I E I M I E B I M I E A A f t e r R e s e t 11110000 Bit Symbol Bit Name Function R/W b0 IMIEA Input-capture/compare-match interrupt enable bit A 0: Interrupt by IMFA bit disabled 1: Interrupt by IMFA bit enabled R/W b1 IMIEB Input-capture/compare-match interrupt enable bit B 0: Interrupt by IMFB bit disabled 1: Interrupt by IMFB bit enabled R/W b2 UDIE Underflow interrupt enable bit 0: Interrupt by UDF bit disabled 1: Interrupt by UDF bit enabled R/W b3 OVIE Overflow interrupt enable bit 0: Interrupt by OVF bit disabled 1: Interrupt by OVF bit enabled R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b5 — b6 — b7 —

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 467 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.2.5 Timer RG Status Register (TRGSR)

Note: 1. The results of writing to these bits are as follows:

• The bit is set to 0 when it is first read as 1 and then 0 is written to it.
• The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it because its previous value is retained.)
• The bit’s value remains unchanged if 1 is written to it. Note: 1. Edge selected by bits IOj0 and IOj1 (j = A or B) in the TRGIOR register. Address 0174h B i t b 7b 6b 5b 4b 3b 2b 1 b 0 Symbol — — — DIRF OVF UDF IMFB IMFA A f t e r R e s e t 1110000 0 Bit Symbol Bit Name Function R/W b0 IMFA Input-capture/compare-match flag A [Condition for setting to 0] Write 0 after reading. (1) [Condition for setting to 1] Refer to Table 23.3 Conditions for Setting Bit of Each Flag to 1. R/W b1 IMFB Input-capture/compare-match flag B R/W b2 UDF Underflow flag R/W b3 OVF Overflow flag R/W b4 DIRF Count direction flag 0: TRG register is decremented 1: TRG register is incremented R b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — b6 — b7 — Table 23.3 Conditions for Setting Bit of Each Flag to 1 Bit Symbol Timer Mode PWM ModeInput Capture Function Output Compare Function IMFA TRGIOA pin input edge (1) When the values of registers TRG and TRGGRA match. IMFB TRGIOB pin input edge (1) When the values of registers TRG and TRGGRB match. UDF When the TRG register underflows. OVF When the TRG register overflows.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 468 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.2.6 Timer RG I/O Cont rol Register (TRGIOR)

Notes: 1. When the IOA2 bit is set to 0 (output compare function), the TRGGRA register functions as a compare match register. After a reset, the TRGIOA pin outputs a low-level signal until the first compare match occurs. 2. When the IOA2 bit is set to 1 (input capture function ), the TRGGRA register func tions as an input capture register. 3. When the IOB2 bit is set to 0 (output compare function), the TRGGRB register functions as a compare match register. After a reset, the TRGIOB pin outputs a low-level signal the until the first compare match occurs. 4. When the IOB2 bit is set to 1 (input capture function ), the TRGGRB register func tions as an input capture register. Address 0175h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BUFB IOB2 IOB1 IOB0 BUFA IOA2 IOA1 IOA0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 IOA0 TRGGRA control bit Function varies depending on the operating mode (function). R/W b1 IOA1 R/W b2 IOA2 TRGGRA mode select bit 0: Output compare function (1) 1: Input capture function (2) R/W b3 BUFA TRGGRC register function select bit 0: Not used as the buffer register of the TRGGRA register 1: Used as the buffer register of the TRGGRA register R/W b4 IOB0 TRGGRB control bit Function varies depending on the operating mode (function). R/W b5 IOB1 R/W b6 IOB2 TRGGRB mode select bit 0: Output compare function (3) 1: Input capture function (4) R/W b7 BUFB TRGGRD register function select bit 0: Not used as the buffer register of the TRGGRB register 1: Used as the buffer register of the TRGGRB register R/W

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23.2.7 Timer RG Counter (TRG)

The TRG register is connected to the CPU via the inte rnal 16-bit bus and should be always accessed in 16-bit units. This register operates incremen ting and can also operate free-running, period counting, or external event counting. It can be cleared to 0000h by a compare match with the corresponding TRGGRA or TRGGRB register, or an input capture to the TRGGRA or TRGGRB register (count clear function). When the TRGCR register overflows (FFFFh → 0000h), the OVF bit in the TRGSR register is set to 1. When the TRGCR register underflows (0000h → FFFFh), the UDF bit in the TRGSR register is set to 1. Address 0177h to 0176h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 00000000 Bit Function Setting Range R/W b15 to b0 In phase counting mode, count operation is increment/decrement. In other modes, count operation is increment. 0000h to FFFFh R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 470 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.2.8 Timer RG General Register A, B, C, D (TRGGRA, TRGGRB, TRGGRC,

TRGGRD) TRGGRA and TRGGRB are 16-bit readable/writable regist ers with both the output compare and input capture register functions. Switching between these functions is accomplished by means of a setting in the TRGIOR register. When registers TRGGRA and TRGGRB are used as output compare registers, the values of registers TRGGRA and TRGGRB and the value of the TRG register are always compared. When their values match (compare match), bits IMFA and IMFB in the TRGSR register are set to 1. Compar e match output can be selected by setting the TRGIOR register. When registers TRGGRA and TRGGRB are used as input capture registers, the valu e of the TRG register is stored when an externally input capture signals is detected. Bits IMFA and IMFB in the TRGSR register are set to 1 at this time. The detection edge of input capture signals is selected by setting the TRGIOR register. In PWM mode, the settings of the TRGIOR register are ignored. The TRGGRC register can also be used as the buff er register of the TRGGRA register, and the TRGGRD register can be used as the buffer register of th e TRGGRB register, respectively. These functions can be selected by setting bits BUFA and BUFB in the TRGIOR register. For example, when the TRGGRA register is set as an ou tput compare register and the TRGGRC register is set as the buffer register of the TRGGRA register, the value of the TRGGRC register is transferred to the TRGGRA register each time compare match A occurs. When the TRGGRA register is set as an input capture register and the TRGGRC register is set as the buffer register of the TRGGRA register, the value of the TRG re gister is transferred to the TRGGRA register and the value of the TRGGRA register value is transferred to the TRGGRC register each time an input capture occurs. Registers TRGGRA and TRGGRB are connected to the CPU via the internal 16-bit bus and should be accessed in 16-bit units. These registers are set as output compare registers (pin output disabled) after a reset. Address 0179h to 0178h (TRGGRA), 017Bh to 017Ah (TRGGRB), 017Dh to 017Ch (TRGGRC), 017Fh to 017Eh (TRGGRD) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 11111111 Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t 11111111 Bit Function R/W b15 to b0 Function varies depending on the operating mode. R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 471 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.2.9 Timer RG Pin Sel ect Register (TRGPSR)

The TRGPSR register selects which pin is assigned as th e timer RG input/output. To use the I/O pins for timer RG , set this register. Set the TRGPSR register before setting the timer RG associated registers. Also, do not change the setting value of this register during timer RG operation. Address 0187h B i t b 7b 6b 5b 4 b 3 b 2 b 1 b 0 Symbol TRGCLKBSEL0 TRGCLKASEL0 TRGIOBSEL0 TRGIOASEL0 — — — — After Reset 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 — b3 — b4 TRGIOASEL0 TRGIOA pin select bit 0: TRGIOA pin not used 1: TRGIOA pin used R/W b5 TRGIOBSEL0 TRGIOB pin select bit 0: TRGIOB pin not used 1: TRGIOB pin used R/W b6 TRGCLKASEL0 TRGCLKA pin select bit 0: TRGCLKA pin not used 1: TRGCLKA pin used R/W b7 TRGCLKBSEL0 TRGCLKB pin select bit 0: TRGCLKB pin not used 1: TRGCLKB pin used R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 472 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.3 Common Items for Multiple Modes

23.3.1 Count Sources

Table 23.4 lists the Count Source Selection, and Figure 23.2 shows the Count Source Block Diagram. When phase counting mode is selected, the settings of bits TCK0 to TCK2 and bits CKEG0 and CKEG1 in the TRGCR register are disabled. Figure 23.2 Count Source Block Diagram The pulse width of an external clock input to the TRGCLKj pin (j =A or B) should be set to three cycles or more of the timer RG operating clock. (See Table 23.1 Timer RG Operating Clocks.) Table 23.4 Count Source Selection Count Source Selection Method f1 f2, f4, f8, f32 The count source is selected by bits TCK0 to TCK2 in the TRGCR register. fOCO40M - The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on). - Bits TCK2 to TCK0 in the TRGCR register are set to 110b (fOCO40M). External signal input to TRGCLKA or TRGCLKB pin - Bits TCK2 to TCK0 in the TRGCR register are set to 101b (TRGCLKA input) or 111b (TRGCLKB input). - The active edge is selected by bits CKEG0 and CKEG1 in the TRGCR register. - The corresponding bit in the direction register is set to 0 (input mode). TCK2 to TCK0 TRG register TCK0 to TCK2: Bits in TRGCR register = 001b = 010b = 011b = 000b Count source TRGCLKA = 101b TRGCLKB = 111b f32 = 100b fOCO40M = 110b

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 473 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.3.2 Buffer Operation

The BUFA or BUFB bit in the TRGIOR register can be used to select the TRGGRC or TRGGRD register as the buffer register of the TRGGRA or TRGGRB register.

• Buffer register of TRGGRA register: TRGGRC register
• Buffer register of TRGGRB register: TRGGRD register Buffer operation differs depending on the mode. Table 23.5 lists the Buffer Operation in Each Mode, Figure 23.3 shows the Buffer Operation of Input Capture Function, and Figure 23.4 shows the Buffer Operation of Output Compare Function. Figure 23.3 Buffer Operation of Input Capture Function Table 23.5 Buffer Operation in Each Mode Function, Mode Transfer Timing Transfer Destination Register Input capture function Input capture si gnal input The content of the TRGGRA (TRGGRB) register is transferred to the buffer register. Output compare function Comp are match between the TRG register and the TRGGRA (TRGGRB) register The content of the buffer register is transferred to the TRGGRA (TRGGRB) register.PWM mode m Transfer n n-1 n+1 TRGIOA input TRG register The above applies under the following conditions:
• The BUFA bit in the TRGIOR register is set to 1 (TRGGRC register is used as the buffer register of the TRGGRA register).
• Bits IOA2 to IOA0 in the TRGIOR register are set to 100b (input capture at the rising edge). m Transfer n TRGGRC register TRGGRA register TRG TRGIOA input (input capture signal) TRGGRA register TRGGRC register (buffer)

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 474 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 23.4 Buffer Operation of Output Compare Function mnTRGGRA register m-1 m+1TRG register The above applies under the following conditions:

• The BUFA bit in the TRGIOR register is set to 1 (TRGGRC register is used as the buffer register of the TRGGRA register).
• Bits IOA2 to IOA0 in the TRGIOR register are set to 001b (low-level output at compare match). n Transfer TRGGRC register (buffer) m TRGIOA output TRGGRC register TRGGRA register Comparator TRG Compare match signal

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 475 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.3.3 Digital Filter

The input to TRGIOj (j = A or B) is sampled and the level is determined when three matches occur. The digital filter function and sampling clock are selected by using the TRGMR register. Figure 23.5 shows a Block Diagram of Digital Filter. Figure 23.5 Block Diagram of Digital Filter C DQ Latch C DQ Latch C DQ Latch Match detection circuit Edge detection circuit DFj Sampling clock IOA2 to IOA0 IOB2 to IOB0 DFCK1 to DFCK0 TRGIOj input signal Clock cycle selected by TCK2 to TCK0 (or DFCK1 to DFCK0) Sampling clock TRGIOj input signal Input signal after passing through digital filter If fewer than three matches occur, the matches are recognized as noise and no transmission is performed. Maximum signal transmission delay is five sampling clocks. Three matches occur and a signal change is confirmed. f32 j = A or B TCK0 to TCK2: Bits in TRGCR register DFCK0, DFCK1, DFj: Bits in TRGMR register IOA0 to IOA2, IOB0 to IOB2: Bits in TRGIOR register C DQ Latch C DQ Latch Timer RG operating clock f1 or fOCO40M Count source = 00b = 01b = 10b = 11b TCK2 to TCK0 = 001b = 010b = 011b = 000b = 100b = 101b f32 TRGCLKA fOCO40M = 110b TRGCLKB = 111b

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 476 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.4 Timer Mode (I nput Capture Function)

The value of the TRG register can be transferred to the TRGGRA or TRGGRB register when the input edge of the input capture/output compare pin (TRGI OA or TRGIOB) is detected. The detect ion edge can be selected from the rising edge, falling edge, or both edges. The input capture function can be used for measuring pulse widths and periods. Table 23.6 lists the Input Capture Function Specifications. j = A or B Table 23.6 Input Capture Function Specifications Item Specification Count sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRGCLKj pin (active edge selectable by a program) Count operation Increment Count period When bits CCLR1 to CCLR0 in the TRGCR register are set to 00b (free-running operation) 1/fk × 65,536 fk: Frequency of count source Count start condition 1 (count starts) is wri tten to the TSTART bit in the TRGMR register. Count stop condition 0 (count stops) is writ ten to the TSTART bit in the TRGMR register. Interrupt request generation timing

• Input capture (active edge of the TRGIOj input)
• TRG register overflow TRGIOA/TRGIOB pins function Programmable I/O port or input-capture input (selectable for each individual pin) TRGCLKA/TRGCLKB pins function Programmable I/O port or external clock input Read from timer The count value can be read by reading the TRG register. Write to timer The TRG register can be written to. Selectable functions • Input-c apture input pin selection Either one or both of pins TRGIOA and TRGIOB
• Active edge selection for input-capture input Rising edge, falling edge, or both rising and falling edges
• Timing for setting the TRG register to 0000h Overflow or input capture
• Buffer operation (Refer to 23.3.2 Buffer Operation.)
• Digital filter (Refer to 23.3.3 Digital Filter.)

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 477 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.4.1 Timer RG I/O Control Register (T RGIOR) in Timer Mode (Input Capture

Function) Notes: 1. When the IOA2 bit is set to 1 (input capture function ), the TRGGRA register func tions as an input capture register. 2. When the IOB2 bit is set to 1 (input capture function ), the TRGGRB register func tions as an input capture register. Address 0175h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BUFB IOB2 IOB1 IOB0 BUFA IOA2 IOA1 IOA0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 IOA0 TRGGRA control bit b1 b0 0 0: Input capture to TRGGRA at the rising edge 0 1: Input capture to TRGGRA at the falling edge 1 0: Input capture to TRGGRA at both edges 1 1: Do not set. R/W b1 IOA1 R/W b2 IOA2 TRGGRA mode select bit (1) Set to 1 (input capture) for the input capture function. R/W b3 BUFA TRGGRC register function select bit 0: Not used as the buffer register of the TRGGRA register 1: Used as the buffer register of the TRGGRA register R/W b4 IOB0 TRGGRB control bit b5 b4 0 0: Input capture to TRGGRB at the rising edge 0 1: Input capture to TRGGRB at the falling edge 1 0: Input capture to TRGGRB at both edges 1 1: Do not set. R/W b5 IOB1 R/W b6 IOB2 TRGGRB mode select bit (2) Set to 1 (input capture) for the input capture function. R/W b7 BUFB TRGGRD register function select bit 0: Not used as the buffer register of the TRGGRB register 1: Used as the buffer register of the TRGGRB register R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 478 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.4.2 Procedure Example for Sett ing Input Capture Operation

Figure 23.6 shows a Procedure Example for Setting Input Capture Operation. Figure 23.6 Procedure Example for Setting Input Capture Operation

23.4.3 Input Capture Signal Timing

The rising edge, falling edge, or both edges can be selected for input-capture input by setting the TRGIOR register. Figure 23.7 shows the Input-Capture Input Signal Timing. The pulse width of input-capture input signals should be 1.5 f1 or more for a single edge and 2.5 f1 or more for both edges. Figure 23.7 Input-Capture Input Signal Timing (1) Use the TRGIOR register to set TRGGRj (j = A or B) as an input capture register and select the input edge of input capture signals from the following three: the rising edge, falling edge, or both edges. (2) Set the TSTART bit in the TRGMR register to 1 to start the count operation of the TRG register. Input capture operation (1) (2) Select input-capture input Count operation starts Input selection N N TRGIOj input Input capture signal (internal signal) TRG register TRGGRj register j =A or B

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 479 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.4.4 Operating Example

Figure 23.8 shows an Operating Example of Input Capture. This example applies when both the rising and falling edges are selected as the input-capture input edge for the TRGIOA pin, the falling edge is selected as the input- capture input edge for the TRGIOB pin, and the TRG register is set to be cleared by the input capture to the TRGGRB register. (1) Use the TRGIOR register to set registers TRGGRA and TRGGRB as input capture registers and select the input edge of input capture signals from the following three: the rising edge, falling edge, or both edges. (2) Set the TSTART bit in TRGMR to 1 and start the count operation of the TRG register. Figure 23.8 Operating Example of Input Capture TRGGRB register TRGGRA register TRGIOA input TRGIOB input 0000h 0005h 0160h 0180h Time TRG register value 0005h 0160h 0180h TRGIOB

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 480 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.5 Timer Mode (Out put Compare Function)

This mode (output compare function) detects when the contents of the TRG register and the TRGGRA or TRGGRB register match (compare match). When a match occurs, a signal is output from the TRGIOA or TRGIOB pin at a given level. Table 23.7 lists the Output Compare Function Specifications. j = A or B Table 23.7 Output Compare Function Specifications Item Specification Count sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRGCLKj pin (active edge selectable by a program) Count operation Increment Count periods • When bits CCLR1 to CCLR0 in the TRGCR register are set to 00b (free-running operation) 1/fk × 65,536 fk: Frequency of count source

• When bits CCLR1 to CCLR01 in the TRGCR register are set to 01b or 10b (TRG is set to 0000h by a compare match with TRGGRj) 1/fk × (n+1) n: Value set in TRGGRj register Waveform output timing Compare match Count start condition 1 (count starts) is wri tten to the TSTART bit in the TRGMR register. Count stop condition 0 (count stops) is writ ten to the TSTART bit in the TRGMR register. Interrupt request generation timing
• Compare match (the contents of the TRG register and the TRGGRj register match)
• TRG register overflow TRGIOA/TRGIOB pins function Programmable I/O port or output-compare output (selectable for each individual pin) TRGCLKA/TRGCLKB pins function Programmable I/O port or external clock input Read from timer The count value can be read by reading the TRG register. Write to timer The TRG register can be written to. Selectable functions • Output-compare output pin selection Either one or both of pins TRGIOA and TRGIOB
• Output level selection at compare match Low-level output, high-level output, or inverted output level
• Timing for setting the TRG register to 0000h Overflow or compare match with the TRGGRj register
• Buffer operation (Refer to 23.3.2 Buffer Operation.)

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 481 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.5.1 Timer RG I/O Control Register (T RGIOR) in Timer Mode (Output Compare

Function) Notes: 1. When the IOA2 bit is set to 0 (output compare function), the TRGGRA register functions as a compare match register. After a reset, the TRGIOA pin outputs as follows until the first compare match occurs. IOA1 to IOA0 = 01b: High-level output 10b: Low-level output 11b: Low-level output 2. When the IOB2 bit is set to 0 (output compare function), the TRGGRB register functions as a compare match register. After a reset, the TRGIOB pin outputs as follows until the first compare match occurs. IOB1 to IOB0 = 01b: High-level output 10b: Low-level output 11b: Low-level output Address 0175h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol BUFB IOB2 IOB1 IOB0 BUFA IOA2 IOA1 IOA0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 IOA0 TRGGRA control bit b1 b0 0 0: Pin output by compare match is disabled (TRGIOA pin functions as a programmable I/O port) 0 1: Low-level output at compare match with TRGGRA 1 0: High-level output at compare match with TRGGRA 1 1: Toggle output at compare match with TRGGRA R/W b1 IOA1 R/W b2 IOA2 TRGGRA mode select bit (1) Set to 0 (output compare) for the output compare function. R/W b3 BUFA TRGGRC register function select bit 0: Not used as the buffer register of the TRGGRA register 1: Used as the buffer register of the TRGGRA register R/W b4 IOB0 TRGGRB control bit b5 b4 0 0: Pin output by compare match is disabled (TRGIOB pin functions as a programmable I/O port) 0 1: Low-level output at compare match with TRGGRB 1 0: High-level output at compare match with TRGGRB 1 1: Toggle output at compare match with TRGGRB R/W b5 IOB1 R/W b6 IOB2 TRGGRB mode select bit (2) Set to 0 (output compare) for the output compare function. R/W b7 BUFB TRGGRD register function select bit 0: Not used as the buffer register of the TRGGRB register 1: Used as the buffer register of the TRGGRB register R/W

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 482 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.5.2 Procedure Example for Setting Waveform Output by Compare Match

Figure 23.9 shows an Operating Example of Waveform Output by Compare Match. Figure 23.9 Operating Example of Waveform Output by Compare Match

23.5.3 Output-Compare Output Timing

A compare match signal is generated at the last st ate when the TRG register and the TRGGRA or TRGGRB register match (according to the timing for updating the count value that the TRG register matches). When a compare match signal is generated, the output value set by the TRGIOR register is output to the output-compare output pin (TRGIOA or TRGIOB). After the TRG regi ster and the TRGGRA or TRGGRB register match, no compare match signal is generated until the TRG input clock is generated. Figure 23.10 shows the Output-Compare Output Timing. Figure 23.10 Output-Compare Output Timing (1) Use the TRGIOR register to select the compare match output from the following three: low-level output, high-level output, or toggle output. When waveform output mode is selected, the ports function as the compare match output pins (TRGIOA and TRGIOB). The output levels of these pins depend on the settings of bits IOA0 and IOA1 and bits IOB0 and IOB1 in the TRGIOR register until the first compare match occurs. (2) Set the timing for generating a compare match in registers TRGGRA and TRGGRB. (3) Set the TSTART bit in the TRGMR register to 1 to start the count operation of the TRG register. Select waveform output mode Set the output timing Count operation starts Output selection Waveform output (1) (2) (3) N N N+1 TRG input clock TRG register TRGGRA register Compare match A signal (internal signal) TRGIOA output TRGIOB output N+2 N+1TRGGRB register Compare match B signal (internal signal)

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 483 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.5.4 Operating Example

Figure 23.11 shows an Operating Example of Low-Level Output and High-Level Output. This example applies when the TRG register is set fo r free-running operation, low-level output at compare match A is selected, and high-level ou tput at compare match B is selected. When the selected level and the pin level match, the pin level does not change. Figure 23.11 Operating Example of Low-Level Output and High-Level Output Figure 23.12 shows an Operating Example of Toggle Output. This example applies when the TRG register is set for period counting operation (counter clear by compare match B), and toggle output at both compare match A and B is selected. Use the TRGIOR register to select the compare match output from the following three: low-level output, high- level output, or toggle output. When waveform output mode is selected, the ports function as the compare match output pins (TRGIOA and TRGIOB). Set the timing for generating a compare match in registers TRGGRA and TRGGRB. Set the TSTART bit in the TRGMR register to 1 to start the count operation of the TRG register. Figure 23.12 Operating Example of Toggle Output TRG register value Time FFFFh TRGGRB register TRGGRA register 0000h TRGIOA output TRGIOB output High-level output Low-level outputNo changeNo change No changeNo change TRGGRB register TRGGRA register 0000h TRGIOB output TRGIOA output TRG register value Time Toggle output Toggle output Counter cleared by compare match with TRGGRB register

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 484 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.6 PWM Mode

In PWM mode, registers TRGGRA and TRGGRB are used as a pair and a PWM waveform is output from the TRGIOA output pin. The output setting in the TRGIOR regist er is invalid for the pins set to PWM mode. Set the high-level output timing for PWM waveforms in the TRGGRA register and the low-level output timing for PWM waveforms in the TRGGRB register. By selecting a compare match with ei ther the TRGGRA or TRGGRB register as the counter clear source for the TRG register, a PWM waveform with a duty of 0% to 100% can be output from the TRGIOA pin. Table 23.8 lists the PWM Mode Specifications, and Table 23.9 lists the Combination of PWM Output Pins and Registers. When the setting values of registers TRGGRA and TRGGRB are the same, the output value does not change even if a compare match occurs. j = A or B Table 23.8 PWM Mode Specifications Item Specification Count sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRGCLKj pin (active edge selectable by a program) Count operation Increment PWM waveform • The high-level output timing for PWM waveforms is set in the TRGGRA register.

• The low-level output timing for PWM waveforms is set in the TRGGRB register. Count start condition 1 (count starts) is wri tten to the TSTART bit in the TRGMR register. Count stop condition 0 (count stops) is writ ten to the TSTART bit in the TRGMR register. Interrupt request generation timing
• Compare match (the contents of the TRG register and the TRGRj register match)
• TRG register overflow TRGIOA pin function PWM output TRGIOB pin function Programmable I/O port TRGCLKA/TRGCLKB pins function Programmable I/O port or external clock input Read from timer The count value can be read by reading the TRG register. Write to timer The TRG register can be written to. Selectable functions • Timing for setting the TRG register to 0000h Overflow or compare match with the TRGGRj register
• Buffer operation (Refer to 23.3.2 Buffer Operation.) Table 23.9 Combination of PWM Output Pins and Registers Output Pin High-Level Output Low-Level Output TRGIOA TRGGRA TRGGRB TRGIOB I/O port function

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 485 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.6.1 Procedure Example for Setting PWM Mode

Figure 23.13 shows a Procedure Example for Setting PWM Mode. Figure 23.13 Procedure Example for Setting PWM Mode

23.6.2 Operating Example

Figure 23.14 shows an Operating Example in PWM Mode (1). When PWM mode is selected while th e TRGIOASEL0 bit in the TRGSR register is set to 1, the TRGIOA pin automatically functions as an output pin, high-level output at compare match wi th the TRGGRA register is selected, and low-level output at compare match with the TRGGRB register is selected. However, regardless of the setting of the TRGIOR register, the TRGIOB pin functions as an I/O port. This example applies when a compare match with the TRGGRA or TRGGRB register is set as the counter clear source for the TRG register. The initial status of the TRGIOA pin depends only on the counter clear sources. This correspondence is shown in Table 23.10. Table 23.10 Correspondence between Initial Status of TRGIOA Pin and Counter Clear Sources Counter Clear Source Initial Status of TRGIOA Pin Compare match with TRGGRA register High Compare match with TRGGRB register Low (1) Use bits TCK0 to TCK2 in the TRGCR register to select the count source. When an external clock is selected, use bits CKEG0 and CKEG1 in the TRGCR register to select the edge of the external clock. (2) Use bits CCLR0 and CCLR1 in the TRGCR register to select the counter clear source. (3) Set the high-level output timing for PWM output waveforms in the TRGGRA register. (4) Set the low-level output timing for PWM output waveforms in the TRGGRB register. (5) Use the PWM bit in the TRGMR register to select PWM mode. When PWM mode is selected, TRGGRA and TRGGRB are set as the output compare registers for setting the high-level output or low-level output timing for PWM output waveforms, regardless of the content of the TRGIOR register. While the TRGIOASEL0 bit in the TRGSR register is set to 1, the TRGIOA pin automatically functions as a PWM output pin. However, regardless of the setting of the TRGIOR register, the TRGIOB pin functions as an I/O port. (6) Set the TSTART bit in the TRGMR register to 1 to start the count operation of the TRG register. PWM mode (1) PWM mode Select the counter clock Select the counter clear source Set TRGGRA Set TRGGRB Set PWM mode Count operation starts (2) (3) (4) (5) (6)

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 487 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 23.15 Operating Example in PWM Mode (2) TRGIOA output TRG register value Time Counter cleared by compare match B TRGGRB register TRGGRA register 0000h (a) Duty 0% TRGGRA register setting value written TRGGRA register setting value written TRGIOA output TRG register value Time Counter cleared by compare match A TRGGRA register TRGGRB register 0000h (b) Duty 100% TRGGRB register setting value written TRGGRB register setting value written

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 488 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.7 Phase Counting Mode

In phase counting mode, the phase difference between th e external input signals from two pins TRGCLKA and TRGCLKB is detected and the TRG register is incremented or decremented. When phase counting mode is selected while the bits TRGC LKASEL0 and TRGCLKBSEL0 are set to 1, regardless of the settings of bits TCK0 to TCK2 and bits CKEG0 and CKEG1 in the TRGCR register, pins TRGCLKA and TRGCLKB automatically function as external clock input pins and the TRG register is incrermented or decremented by setting bits CNTEN0 to CNTEN7 in the TRGCNTC register. However, bits CCLR0 and CCLR1 in the TRGCR register and regi sters TRGIOR, TRGIER, TR GSR, TRGGRA, and TRGGRB are enabled, so the input capture/ou tput compare function, PWM output function, and interrupt sources can be used. The TRG register operates counting at both the risi ng and falling edges of the TRGCLKA or TRGCLKB pin by setting bits CNTEN0 to CNTEN7. Table 23.11 lists the Phase Counting Mode Specifications, and Table 23.12 lists the Increment and Decrement Conditions for TRG Register. j = A or B Table 23.11 Phase Counting Mode Specifications Item Specification Count source External signal input to the TRGCLKj pin Count operations Increment/decrement Count start condition 1 (count starts) is wri tten to the TSTART bit in the TRGMR register. Count stop condition 0 (count stops) is writ ten to the TSTART bit in the TRGMR register. Interrupt request generation timing

• Input capture (active edge of the TRGIOj input)
• Compare match (the contents of the TRG register and the TRGGRj register match)
• TRG register underflow
• TRG register overflow TRGIOA pin function Programmable I/O port, input -capture input, output-compare output, or PWM output TRGIOB pin function Programmable I/O port, in put-capture input, or output-compare output TRGCLKA/TRGCLKB pins function External clock input Read from timer The count value can be read by reading the TRG register. Write to timer The TRG register can be written to. Selectable functions • Selection of counter increment and decrement conditions Selectable by bits CNTEN7 to CNTEN0 bits in the TRGCNTC register.
• The input capture/output compare function and PWM function can be used. Table 23.12 Increment and Decrem ent Conditions for TRG Register TRGCLKB pin High Low High Low TRGCLKA pin Low High Low High Bits CNTEN7 to CNTEN0 in TRGCNTC register CNTEN7 CNTEN6 CNTEN5 CNTEN4 CNTEN3 CNTEN2 CNTEN1 CNTEN0 Value 01010101 01010101 Count

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 489 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.7.1 Timer RG Contro l Register (TRGCR) in Phase Counting Mode

23.7.2 Procedure Example for Setting Phase Counting Mode

Figure 23.16 shows a Procedure Example for Setting Phase Counting Mode. Figure 23.16 Procedure Example for Setting Phase Counting Mode Address 0172h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — CCLR1 CCLR0 CKEG1 CKEG0 TCK2 TCK1 TCK0 A f t e r R e s e t 10000000 Bit Symbol Bit Name Function R/W b0 TCK0 Count source select bit Disabled in phase counting mode. R/W b1 TCK1 R/W b2 TCK2 R/W b3 CKEG0 External clock active edge select bit Disabled in phase counting mode. R/W b4 CKEG1 R/W b5 CCLR0 TRG register clear select bit b6 b5 0 0: Clear disabled 0 1: TRG register cleared by input capture or compare match with TRGGRA 1 0: TRG register cleared by input capture or compare match with TRGGRB 1 1: Do not set. R/W b6 CCLR1 R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is 1. — Phase counting mode (1) (2) Phase counting mode Select phase counting mode Count operation starts (1) Set the MDF bit in the TRGMR register to 1 to select phase counting mode. (2) Set the TSTART bit in the TRGMR register to 1 to start count operation.

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 490 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.7.3 Operating Example

Figures 23.17 to 23.20 show operating examples in phase counting mode. Table 23.12 lists the Increment and Decrement Conditions for TRG Register. In phase counting mode, the TRG register is incremented or decremented at both the rising ( ) and falling ( ) edges of the TRGCLKA or TRGCLKB pin by setting bits CNTEN0 to CNTEN7 in the TRGCNTC register. Figure 23.17 Operating Example in Phase Counting Mode 1 Figure 23.18 Operating Example in Phase Counting Mode 2 TRG register value Time TRGCLKA input TRGCLKB input

• When the TRGCNTC register value is FFh Increment Decrement TRGCLKA input Time Increment Decrement TRGCLKB input TRG register value
• When the TRGCNTC register value is 24h

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 492 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.8 Timer RG Interrupt

Timer RG generates a timer RG interrupt request from four sources. The timer RG interrupt uses the single TRGIC register (bits IR and ILVL0 to ILVL2) and a single vector. Table 23.13 lists the Registers Associated with Timer RG Interrupt, and Figure 23.21 is a Block Diagram of Timer RG Interrupt. Figure 23.21 Block Diagra m of Timer RG Interrupt Like other maskable interrupts, the timer RG interrupt is controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because a single interrupt source (timer RG interrupt) is generated from multiple interrupt request sources.

• The IR bit in the TRGIC register is set to 1 (interrupt requested) when a bit in the TRGSR register is set to 1 and the corresponding bit in the TRGIER register is also set to 1 (interrupt enabled).
• The IR bit is set to 0 (no interrupt requested) when either the bit in the TRGSR register or the corresponding bit in the TRGIER register is set to 0, or both are set to 0. In other words, the interrupt request is not maintained even if the IR bit is once set to 1 but the interrupt is not acknowledged.
• If another interrupt source is triggered after the IR bit is set to 1, the IR bit remains set to 1 and does not change.
• If multiple bits in the TRGIER register are set to 1, use the TRGSR register to determine the source of the interrupt request.
• The bits in the TRGSR register are not automatically set to 0 when an interrupt is acknowledged. Set them to 0 within the interrupt routine. Refer to 23.2.5 Timer RG Status Register (TRGSR) , for the procedure for setting these bits to 0. Refer to 23.2.4 Timer RG Interrupt Enable Register (TRGIER), for details of the TRGIER register. Refer to 12.3 Interrupt Control, for details of the TRGIC register and 12.1.5.2 Relocatabl e Vector Tables, for information on interrupt vectors. Table 23.13 Registers Associated with Timer RG Interrupt Timer RG Status Register Timer RG Interrupt Enable Register Timer RG Interrupt Control Register TRGSR TRGIER TRGIC Timer RG interrupt request (IR bit in TRGIC register) IMFA bit IMIEA bit IMFB bit IMIEB bit UDF bit UDIE bit OVF bit OVIE bit IMFA, IMFB, UDF, OVF: Bits in TRGSR register IMIEA, IMIEB, UDIE, OVIE: Bits in TRGIER register

REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 493 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. 23. Timer RGR8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

23.9 Notes on Timer RG

23.9.1 Phase Difference, Overlap, a nd Pulse Width in Phase Counting Mode

The phase difference and overlap between the extern al input signals from pins TRGCLKA and TRGCLKB Difference, Overlap, and Pulse Width in Phase Counting Mode. Figure 23.22 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Overlap Overlap Phase difference Pulse width Pulse width TRGCLKB input TRGCLKA input Phase difference and overlap: 1.5 f1 or more Pulse width: 2.5 f1 or more Phase difference

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 494 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 24. Serial Interface (UARTi (i = 0 or 1)) The serial interface consists of three channels, UART0 to UART2. This chapter describes UARTi (i = 0 or 1).

24.1 Introduction

UART0 and UART 1 have a dedicated timer to generate a transfer clock and operate independently. Clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode) are supported. Figure 24.1 shows a Block Diagram of UARTi (i = 0 or 1) . Figure 24.2 shows a Block Diagram of UARTi (i = 0 or 1) Transmit/Receive Unit. Table 24.1 lists the Pin Configuration of UARTi (i = 0 or 1). Figure 24.1 Block Diagram of UARTi (i = 0 or 1) = 01bf8 = 10b CLK1 to CLK0 RXDi f32 1/(n0+1) UART reception UART transmission Clock synchronous type (internal clock selected) Clock synchronous type Reception control circuit Transmission control circuit CKDIR = 0 CKDIR = 1 Receive clock Transmit clock Transmit/ receive unit UiBRG register CKDIR = 0 Internal External CKDIR = 1 UARTi TXDi CLK polarity switch circuitCLKi Clock synchronous type Clock synchronous type (external clock selected)Clock synchronous type (internal clock selected) = 11bfC CKDIR: Bit in UiMR register CLK0, CLK1: Bits in UiC0 register i = 0 or 1 = 00b

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 495 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 24.2 Block Diagram of UARTi (i = 0 or 1) Transmit/Receive Unit Table 24.1 Pin Configuration of UARTi (i = 0 or 1) Pin Name Assigned Pin I/O Function TXD0 P13_1 Output Serial data output RXD0 P13_2 Input Serial data input CLK0 P13_3 I/O Transfer clock I/O TXD1 P4_0 Input Serial data output RXD1 P4_1 Output Serial data input CLK1 P4_2 I/O Transfer clock I/O RXDi 1SP 2SP SP SP PAR PRYE = 0 PAR disabled PAR enabled PRYE = 1 UART UART (9 bits) D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive register UiRB register0000000 D 8 MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits D7 D6 D5 D4 D3 D2 D1 D0 UiTB registerD8 TXDi 1SP 2SP SP SP PAR UARTi transmit register i = 0 or 1 SP: Stop bit PAR: Parity bit UART (7 bits) UART (8 bits) Clock synchronous type Clock synchronous type UART (7 bits) Clock synchronous type UART (7 bits) Clock synchronous type UART (8 bits) UART (9 bits) UART (7 bits) UART (8 bits) Clock synchronous type UART (9 bits) UART PRYE = 1 PAR enabled PAR disabled PRYE = 0 Clock synchronous type MSB/LSB conversion circuit UART (8 bits) UART (9 bits)

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 496 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

24.2 Registers

24.2.1 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 or 1)

24.2.2 UARTi Bit Rate Regist er (UiBRG) (i = 0 or 1)

Write to the UiBRG register while transmission and reception stop. Use the MOV instruction to write to this register. Set bits CLK0 and CLK1 in the UiC0 register before writing to the UiBRG register. Address 00A0h (U0MR), 0160h (U1MR) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — PRYE PRY STPS CKDIR SMD2 SMD1 SMD0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 SMD0 Serial I/O mode select bit b2 b1 b0 0 0 0: Serial interface disabled 0 0 1: Clock synchronous serial I/O mode 1 0 0: UART mode, transfer data 7 bits long 1 0 1: UART mode, transfer data 8 bits long 1 1 0: UART mode, transfer data 9 bits long Other than above: Do not set. R/W b1 SMD1 R/W b2 SMD2 R/W b3 CKDIR Internal/external clock select bit 0: Internal clock 1: External clock R/W b4 STPS Stop bit length select bit 0: One stop bit 1: Two stop bits R/W b5 PRY Odd/even parity select bit Enabled when PRYE = 1 0: Odd parity 1: Even parity R/W b6 PRYE Parity enable bit 0: Parity disabled 1: Parity enabled R/W b7 — Reserved bit Set to 0. R/W Address 00A1h (U0BRG), 0161h (U1BRG) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit Function Setting Range R/W b7 to b0 If the setting value is n, UiBRG divides the count source by n+1. 00h to FFh W

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 497 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

24.2.3 UARTi Transmit Buffer Re gister (UiTB) (i = 0 or 1)

When the transfer data is 9 bits long, write data to the high-order byte first, then low-order byte of the UiTB register. Use the MOV instruction to write to this register. Address 00A3h to 00A2h (U0TB), 0163h to 0162h (U1TB) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t XXXXXXXX Bit Symbol Function R/W b0 — Transmit data W b1 — b2 — b3 — b4 — b5 — b6 — b7 — b8 — b9 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b10 — b11 — b12 — b13 — b14 — b15 —

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 498 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

24.2.4 UARTi Transmit/Receive Control Register 0 (UiC0) (i = 0 or 1)

Note: 1. If the BRG count source is switched, set the UiBRG register again.

24.2.5 UARTi Transmit/Receive Control Register 1 (UiC1) (i = 0 or 1)

Notes: 1. The RI bit is set to 0 when the higher byte of the UiRB register is read. 2. In UART mode, set the UiRRM bit to 0 (continuous receive mode disabled). Address 00A4h (U0C0), 0164h (U1C0) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol UFORM CKPOL NCH — TXEPT — CLK1 CLK0 A f t e r R e s e t 00001000 Bit Symbol Bit Name Function R/W b0 CLK0 BRG count source select bit (1) b1 b0 0 0: f1 selected 0 1: f8 selected 1 0: f32 selected 1 1: fC selected R/W b1 CLK1 R/W b2 — Reserved bit Set to 0. R/W b3 TXEPT Transmit register empty flag 0: Data in the transmit register (transmission in progress) 1: No data in the transmit register (transmission completed) R b4 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b5 NCH Data output select bit 0: TXDi pin set as CMOS output 1: TXDi pin set as N-channel open-drain output R/W b6 CKPOL CLK polarity select bit 0: Transmit data output at the falling edge and receive data input at the rising edge of the transfer clock 1: Transmit data output at the rising edge and receive data input at the falling edge of the transfer clock R/W b7 UFORM Transfer format select bit 0: LSB first 1: MSB first R/W Address 00A5h (U0C1), 0165h (U1C1) B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — — UiRRM UiIRS RI RE TI TE A f t e r R e s e t 00000010 Bit Symbol Bit Name Function R/W b0 TE Transmission enable bit 0: Transmission disabled 1: Transmission enabled R/W b1 TI Transmit buffer empty flag 0: Data in the UiTB register 1: No data in the UiTB register R b2 RE Reception enable bit 0: Reception disabled 1: Reception enabled R/W b3 RI Reception complete flag (1) 0: No data in the UiRB register 1: Data in the UiRB register R b4 UiIRS UARTi transmit interrupt source select bit 0: Transmit buffer empty (TI = 1) 1: Transmission completed (TXEPT = 1) R/W b5 UiRRM UARTi continuous receive mode enable bit (2) 0: Continuous receive mode disabled 1: Continuous receive mode enabled R/W b6 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b7 —

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 499 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

24.2.6 UARTi Receive Buffer Regi ster (UiRB) (i = 0 or 1)

Note: 1. Bits SUM, PER, FER, and OER are set to 0 (no error) when either of the following is set: - Bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled). - The RE bit in the UiC1 register is set to 0 (reception disabled). The SUM bit is set to 0 (no error) when all of bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are also set to 0 when the high-order byte of the UiRB register is read. Always read the UiRB register in 16-bit units. Address 00A7h to 00A6h (U0RB), 0167h to 0166h (U1RB) B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit b15 b14 b13 b12 b11 b10 b9 b8 Symbol SUM PER FER OER — — — — A f t e r R e s e t XXXXXXXX Bit Symbol Bit Name Function R/W b0 — — Receive data (D7 to D0) R b1 — b2 — b3 — b4 — b5 — b6 — b7 — b8 — — Receive data (D8) R b9 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b10 — b11 — b12 OER Overrun error flag (1) 0: No overrun error 1: Overrun error R b13 FER Framing error flag (1) 0: No framing error 1: Framing error R b14 PER Parity error flag (1) 0: No parity error 1: Parity error R b15 SUM Error sum flag (1) 0: No error 1: Error R

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 500 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

24.2.7 UART0 Pin Select Register (U0SR)

The U0SR register selects which pin is assigned as the UART0 input/output. To use the I/O pins for UART0, set this register. Set the U0SR register before setting the UART0 associat ed registers. Also, do not change the setting value of this register during UART0 operation. Address 0188h B i t b 7 b 6 b 5b 4b 3b 2 b 1 b 0 Symbol — — — CLK0SEL0 — RXD0SEL0 RXD0SEL1 TXD0SEL0 A f t e r R e s e t 000 0 0 0 0 0 Bit Symbol Bit Name Function R/W b0 TXD0SEL0 TXD0 pin select bit 0: TXD0 pin not used 1: TXD0 pin used R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 RXD0SEL0 RXD0 pin select bit b3 b2 0 0: RXD0 pin not used 0 1: P13_2 assigned 1 0: P11_4 assigned 1 1: Do not set. R/W b3 RXD0SEL1 R/W b4 CLK0SEL0 CLK0 pin select bit 0: CLK0 pin not used 1: CLK0 pin used R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 — b7 —

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 501 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

24.2.8 UART1 Pin Select Register (U1SR)

The U1SR register selects which pin is assigned as the UART1 input/output. To use the I/O pins for UART1, set this register. Set the U1SR register before setting the UART1 associat ed registers. Also, do not change the setting value of this register during UART1 operation. Address 0189h B i t b 7 b 6 b 5b 4b 3b 2b 1b 0 Symbol — — — CLK1SEL0 — RXD1SEL0 — TXD1SEL0 A f t e r R e s e t 0 0 000000 Bit Symbol Bit Name Function R/W b0 TXD1SEL0 TXD1 pin select bit 0: TXD1 pin not used 1: TXD1 pin used R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 RXD1SEL0 RXD1 pin select bit 0: RXD1 pin not used 1: RXD1 pin used R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 CLK1SEL0 CLK1 pin select bit 0: CLK1 pin not used 1: CLK1 pin used R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 — b7 —

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 502 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

24.3 Clock Synchronous Serial I/O Mode

In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 24.2 lists the Clock Synchronous Serial I/O Mode Sp ecifications. Table 24.3 lists the Registers Used and Settings in Clock Synchronous Serial I/O Mode (1). i = 0 or 1 Notes: 1. When an external clock is selected, the requirem ents must be met in either of the following states: - The external clock is held high when the CKPOL bit in the UiC0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) - The external clock is held low when the CKPOL bit in the UiC0 register is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock) 2. If an overrun erro r occurs, the receive data (b0 to b8) in the UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged. Table 24.2 Clock Synchronous Serial I/O Mode Specifications Item Specification Transfer data format • Transfer data length: 8 bits Transfer clocks • The CKDIR bit in the UiMR regi ster is set to 0 (internal clock): fi/(2(n+1)) fi = f1, f8, f32, fC n = Value set in UiBRG register: 00h to FFh

• The CKDIR bit is set to 1 (external clock): Input from the CLKi pin Transmit start conditions • To start transmission, the following requirements must be met: (1) - The TE bit in the UiC1 register is set to 1 (transmission enabled). - The TI bit in the UiC1 register is set to 0 (data in the UiTB register). Receive start conditions • To start reception, the following requirements must be met: (1) - The RE bit in the UiC1 register is set to 1 (reception enabled). - The TE bit in the UiC1 register is set to 1 (transmission enabled). - The TI bit in the UiC1 register is set to 0 (data in the UiTB register). Interrupt request generation timing
• For transmission, one of the following can be selected. - The UiIRS bit is set to 0 (transmit buffer empty): When data is transferred from the UiTB register to the UARTi transmit register (at start of transmission). - The UiIRS bit is set to 1 (transmission completed): When data transmission from the UARTi transmit register is completed.
• For reception When data is transferred from the UARTi receive register to the UiRB register (at completion of reception). Error detection • Overrun error (2) This error occurs if the serial interface starts receiving the next unit of data before reading the UiRB register and receives the 7th bit of the next unit of data. Selectable functions • CLK polarity selection Transfer data input/output can be selected to occur synchronously with the rising or the falling edge of the transfer clock.
• LSB first, MSB first selection Whether data transmission/reception begins with bit 0 or begins with bit 7 can be selected.
• Continuous receive mode selection Reception is enabled immediately by reading the UiRB register.

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 503 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group i = 0 or 1 Note: 1. Set the bits not listed in this table to 0 when writing to the above registers in clock synchronous serial I/O mode. Table 24.3 Registers Used and Settings in Clock Synchronous Serial I/O Mode (1) Register Bit Function UiTB b0 to b7 Set data transmission. UiRB b0 to b7 Receive data can be read. OER Overrun error flag UiBRG b0 to b7 Set the transfer rate. UiMR SMD2 to SMD0 Set to 001b. CKDIR Select an internal clock or external clock. UiC0 CLK0, CLK1 Select the count source for the UiBRG register. TXEPT Transmit register empty flag NCH Select the output fo rmat of the TXDi pin. CKPOL Select the transfer clock polarity. UFORM Select LSB first or MSB first. UiC1 TE Set to 1 to enable transmission/reception TI Transmit buffer empty flag RE Set to 1 to enable reception. RI Reception complete flag UiIRS Select the UARTi transmit interrupt source. UiRRM Set to 1 to use continuous receive mode.

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 504 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 24.4 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. After UARTi (i = 0 or 1) operating mode is selected, the TXDi pin outputs a high-level signal until transfer starts. (When the NCH bit is set to 1 (N-channel open-drain output), this pin is in the high-impedance state.) Table 24.4 I/O Pin Functions in Clock Synchronous Serial I/O Mode Pin Name Function Selection Method TXD0 (P13_1) Serial data output TXD0SEL0 bit in U0SR register = 1 For reception only: P13_1 can be used as a port by setting TXD0SEL0 bit = 0. RXD0 (P13_2) Serial data input Bits RXD0SEL1 and RXD0SEL0 in U0SR register = 01b PD13_2 bit in PD3 register = 0 For transmission only: P13_2 can be used as a port by setting bits RXD0SEL1 to RXD0SEL0 = 00b. CLK0 (P13_3) Transfer clock output CLK0SEL0 bit in U0SR register = 1 CKDIR bit in U0MR register = 0 Transfer clock input CLK0SEL0 bit in U0SR register = 1 CKDIR bit in U0MR register = 1 PD13_3 bit in PD3 register = 0 TXD1 (P4_0) Serial data output TXD1 SEL0 bit in U1SR register = 1 For reception only: P4_0 can be used as a port by setting TXD1SEL0 bit = 0. RXD1 (P4_1) Serial data input Bits RXD0SEL1 and RXD0SEL0 in U1SR register = 10b PD4_1 bit in PD4 register = 0 For transmission only: P4_1 can be used as a port by setting bits RXD0SEL1 to RXD0SEL0 = 00b. CLK1 (P4_2) Transfer clock output CLK1SEL0 bit in U1SR register = 1 CKDIR bit in U1MR register = 0 Transfer clock input CLK1SEL0 bit in U1SR register = 1 CKDIR bit in U1MR register = 0 PD4_2 bit in PD4 register = 0

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 505 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 24.3 Transmit and Receive Timing in Clock Synchronous Serial I/O Mode Transfer clock TE bit in UiC1 register TXDi

• Transmit Timing Example (Internal Clock Selected) Data set in UiTB register Data transfer from UiTB register to UARTi transmit register TC CLKi TCLK Pulsing stops because TE bit is set to 0. D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 TC = TCLK = 2(n+1)/fi fi: Frequency of UiBRG count source (f1, f8, f32, fC) n: Value set in UiBRG register The above applies under the following conditions:
• CKDIR bit in UiMR register = 0 (internal clock)
• CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
• UiIRS bit in UiC1 register = 0 (interrupt request generation when the transmit buffer is empty) Set to 0 when an interrupt request is acknowledged or by a program. Dummy data set in UiTB register Data transfer from UiTB register to UARTi transmit register 1/fEXT D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 Received data capture Data read from UiRB registerData transfer from UARTi receive register to UiRB register TI bit in UiC1 register TXEPT bit in UiC0 register IR bit in SiTIC register Set to 0 when an interrupt request is acknowledged or by a program.
• Receive Timing Example (External Clock Selected) RE bit in UiC1 register TE bit in UiC1 register TI bit in UiC1 register RI bit in UiC1 register IR bit in SiRIC register CLKi RXDi The above applies under the following conditions:
• CKDIR bit in UiMR register = 1 (external clock)
• CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) The following should be met when a high-level is applied to the CLKi pin before receiving data:
• TE bit in UiC1 register = 1 (transmission enabled)
• RE bit in UiC1 register = 1 (reception enabled)
• Dummy data write to the UiTB register fEXT: Frequency of external clock i = 0 or 1

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 506 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

24.3.1 Polarity Select Function

Figure 24.4 shows the Transfer Clock Polarity. The CKPOL bi t in the UiC0 (i = 0 or 1) register can be used to select the transfer clock polarity. Figure 24.4 Transfer Clock Polarity

24.3.2 LSB First/MSB First Select Function

Figure 24.5 shows the Transfer Format. The UFORM bit in the UiC0 (i = 0 or 1) register can be used to select the transfer format. Figure 24.5 Transfer Format CLKi (1) D0TXDi

• CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock) D1 D2 Notes: 1. The CLKi pin level is high during no transfer. 2. The CLKi pin level is low during no transfer. D3 D4 D5 D6 D7 D0RXDi D1 D2 D3 D4 D5 D6 D7 CLKi (2) D0TXDi D1 D2 D3 D4 D5 D6 D7 D0RXDi D1 D2 D3 D4 D5 D6 D7
• CKPOL bit in UiC0 register = 1 (transmit data output at the rising edge and receive data input at the falling edge of the transfer clock) i = 0 or 1 CLKi D0TXDi
• UFORM bit in UiC0 register = 0 (LSB first) (1) D1 D2 D3 D4 D5 D6 D7 D0RXDi D1 D2 D3 D4 D5 D6 D7 CLKi D7TXDi D6 D5 D4 D3 D2 D1 D0 RXDi
• UFORM bit in UiC0 register = 1 (MSB first) (1) Note: 1. The above applies under the following condition: CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock). D7 D6 D5 D4 D3 D2 D1 D0 i = 0 or 1

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 507 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

24.3.3 Continuous Receive Mode

Continuous receive mode is selected by setting the UiRRM bit in the UiC1 register (i = 0 or 1) to 1 (continuous receive mode enabled). In this mode, reading the UiRB register sets the TI b it in the UiC1 register to 0 (data in the UiTB register). When the UiRRM bit is set to 1, do not write dummy data to the UiTB register by a program.

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 508 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

24.4 Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows data transmission and reception after setting the desired transfer rate and transfer data format. Table 24.5 lists the UART Mode Specifications, and Table 24.6 lists th e Registers Used and Settings in UART Mode. i = 0 or 1 Note: 1. If an overrun erro r occurs, the receive data (b0 to b8) in the UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged. Table 24.5 UART M ode Specifications Item Specification Transfer data formats • Character bits (trans fer data): Selectable from 7, 8 or 9 bits

• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bits: Selectable from 1 or 2 bits Transfer clocks • The CKDIR bit in the UiMR regi ster is set to 0 (internal clock): fj/(16(n+1)) fj = f1, f8, f32, fC n = Value set in UiBRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): fEXT/(16(n+1)) fEXT: Input from CLKi pin, n = Value set in UiBRG register: 00h to FFh Transmit start conditions • To start transmission, the following requirements must be met: - The TE bit in the UiC1 register is set to 1 (transmission enabled). - The TI bit in the UiC1 register is set to 0 (data in the UiTB register). Receive start conditions • To start reception, the following requirements must be met: - The RE bit in the UiC1 register is set to 1 (reception enabled). - Start bit detection Interrupt request generation timing
• For transmission, one of the following can be selected. - The UiIRS bit is set to 0 (transmit buffer empty): When data is transferred from the UiTB register to the UARTi transmit register (at start of transmission). - The UiIRS bit is set to 1 (transfer completed): When data transmission from the UARTi transmit register is completed.
• For reception When data is transferred from the UARTi receive register to the UiRB register (at completion of reception). Error detection • Overrun error (1) This error occurs if the serial interface starts receiving the next unit of data before reading the UiRB register and receive the bit one before the last stop bit of the next unit of data.
• F r a m i n g e r r o r This error occurs when the set number of stop bits is not detected.
• Parity error This error occurs when parity is enabled, and the number of 1’s in the parity and character bits do not match the set number of 1’s.
• Error sum flag This flag is set is set to 1 if an overrun, framing, or parity error occurs.

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 509 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group i = 0 or 1 Notes: 1. The bits used for transmissi on/receive data are as follows: - Bits b0 to b6 when transfer data is 7 bits long - Bits b0 to b7 when transfer data is 8 bits long - Bits b0 to b8 when transfer data is 9 bits long 2. The contents of the following are undefined: - Bits b7 and b8 when the transfer data is 7 bits long - Bit b8 when the transfer data is 8 bits long Table 24.6 Registers Used and Settings in UART Mode Register Bit Function UiTB b0 to b8 Set transmit data. (1) UiRB b0 to b8 Receive data can be read. (2) OER, FER, PER, SUM Error flag UiBRG b0 to b7 Set the transfer rate. UiMR SMD2 to SMD0 Set to 100b when transfer data is 7 bits long. Set to 101b when transfer data is 8 bits long. Set to 110b when transfer data is 9 bits long. CKDIR Select an internal clock or external clock. STPS Select the stop bit(s). PRY, PRYE Select whether parity is included and whether odd or even. UiC0 CLK0, CLK1 Select the count source for the UiBRG register. TXEPT Transmit register empty flag NCH Select the output format of the TXDi pin. CKPOL Set to 0. UFORM Select LSB first or MSB first wh en transfer data is 8 bits long. Set to 0 when transfer data is 7 bits or 9 bits long. UiC1 TE Set to 1 to enable transmission. TI Transmit buffer empty flag RE Set to 1 to enable reception. RI Reception complete flag UiIRS Select the UARTi transmit interrupt source. UiRRM Set to 0.

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 510 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Table 24.7 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 or 1) operating mode is selected, the TXDi pin output s a high-level signal until transfer starts. (When the NCH bit is set to 1 (N-channel open-drain output), this pin is in the high-impedance state.) Table 24.7 I/O Pin Functions in UART Mode Pin name Function Selection Method TXD0 (P13_1) Serial data output TXD0SEL0 bit in U0SR register = 1 For reception only: P13_1 can be used as a port by setting TXD0SEL0 bit = 0. RXD0 (P13_2) Serial data input RXD0SEL0 bit in U0SR register = 1 PD13_2 bit in PD3 register = 0 For transmission only: P13_2 can be used as a port by setting RXD0SEL0 bit = 0. CLK0 (P13_3) Programmable I/O port CLK0SEL0 bit in U0SR register = 0 (CLK0 pin not used) Transfer clock input CLK0SEL0 bit in U0SR register = 1 CKDIR bit in U0MR register = 1 PD13_3 bit in PD3 register = 0 TXD1 (P4_0) Serial data output TXD1 SEL0 bit in U1SR register = 1 For reception only: P4_0 can be used as a port by setting TXD1SEL0 bit = 0. RXD1 (P4_1) Serial data input RXD1SEL0 bit in U1SR register = 1 PD4_1 bit in PD4 register = 0 For transmission only: P4_1 can be used as a port by setting RXD1SEL0 bit = 0. CLK1 (P4_2) Programmable I/O port CLK1SEL0 bit in U1SR register = 0 (CLK1 pin not used) Transfer clock input CLK1SEL0 bit in U1SR register = 1 CKDIR bit in U1MR register = 0 PD4_2 bit in PD4 register = 0

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 511 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 24.6 Transmit Timing in UART Mode Data set in UiTB register Data set in UiTB register TC D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1ST TC D1 D2 D3 D4 D5 D6 D7 D8 SP SPST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SPST D0 D1ST Transfer clock TE bit in UiC1 register TXDi Set to 0 when an interrupt request is acknowledged or by a program.

• Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit) TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: Frequency of UiBRG count source (f1, f8, f32, fC) fEXT: Frequency of UiBRG count source (external clock) n: Value set in UiBRG register i = 0 or 1 The above applies under the following conditions:
• PRYE bit in UiMR register = 1 (parity enabled)
• STPS bit in UiMR register = 0 (one stop bit)
• UiIRS bit in UiC1 register = 1 (interrupt request generation when transmission is completed) Start bit Parity bit Pulsing stops because TE bit is set to 0. TXDi Data transfer from UiTB register to UARTi transmit register TI bit in UiC1 register TXEPT bit in UiC0 register IR bit in SiTIC register Stop bit
• Transmit Timing Example When Transfer Data is 9 Bits Long (Parity Disabled, Two Stop Bits) Stop bit Stop bitStart bit Transfer clock TE bit in UiC1 register TI bit in UiC1 register TXEPT bit in UiC0 register IR bit in SiTIC register Data transfer from UiTB register to UARTi transmit register TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: Frequency of UiBRG count source (f1, f8, f32, fC) fEXT: Frequency of UiBRG count source (external clock) n: Value set in UiBRG register i = 0 or 1 Set to 0 when an interrupt request is acknowledged or by a program. The above applies under the following conditions:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (two stop bits)
• UiIRS bit in UiC1 register = 0 (interrupt request generation when the transmit buffer is empty)

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 512 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 24.7 Receive Timing in UART Mode UiBRG output Set to 0 when an interrupt request is acknowledged or by a program.

• Receive Timing Example When Transfer Data is 8 Bits Long (Parity Disabled, One Stop Bit) The above applies under the following conditions:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 0 (one stop bit) i = 0 or 1 RE bit in UiC1 register Start bit Stop bit D0 D1 D7RXDi Transfer clock “L” is determined. Received data capture Reception starts when a transfer clock is generated at the falling edge of the start bit. Data transfer from UARTi receive register to UiRB register RI bit in UiC1 register IR bit in SiRIC register

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 513 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

24.4.1 Bit Rate

In UART mode, the bit rate is the frequency (divided by the UiBRG register (i = 0 or 1)) divided by 16. Figure 24.8 Formula for Calculating Setting Value of UiBRG Register (i = 0 or 1) i = 0 or 1 Note: 1. For the high-speed on-chip oscillator, th e correction value of the FRA4 register should be written into the FRA1 register and the correction value of the FRA5 register should be written into the FRA3 register. This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20 in the FRA2 register are set to 000b (divide-by-2 mode). Table 24.8 Bit Rate Setting Example in UART Mode (Internal Clock Selected) Bit Rate (bps) UiBRG Count Source System Clock = 20 MHz System Clock = 18.432 MHz (1) System Clock = 8 MHz UiBRG Setting Value Actual Time (bps) Setting Error (%) UiBRG Setting Value Actual Time (bps) Setting Error (%) UiBRG Setting Value Actual Time (bps) Setting Error (%) 115200 f1 10 (0Ah) 113636.36 -1.36 9 (09h) 115200.00 0.00 −− − UART mode

• Internal clock selected Setting value of UiBRG register = fj Bit rate × 16 − 1 fj: Count source frequency of UiBRG register (f1, f8, f32, or fC)
• External clock selected fEXT Bit rate × 16 − 1 fEXT: Count source frequency of UiBRG register (external clock) Setting value of UiBRG register = i = 0 or 1

1. Serial Interface (UARTi (i = 0 or 1)) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 514 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

24.5 Notes on Serial Interface (UARTi (i = 0 or 1))

• When reading data from the UiRB (i = 0 or 1) register either in clock synchronous serial I/O mode or in clock asynchronous serial I/O mode, always read data in 16-bit units. When the high-order byte of the UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0. To check receive errors, read the UiRB register and then use the read data. Program example to read the receive buffer register: MOV .W 00A6H,R0 ; Read the U0RB register
• When writing data to the UiTB regist er in clock asynchronous serial I/O mo de with 9-bit transfer data length, write data to the high-order byte first and then the low-order byte, in 8-bit units. Program example to write to the transmit buffer register: MOV .B #XXH,00A3H ; Write to the high-order byte of the U0TB register MOV .B #XXH,00A2H ; Write to the low-order byte of the U0TB register

1. Serial Interface (UART2) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 515 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 25. Serial Interface (UART2) The serial interface consists of three channels, UART0 to UART2. This chapter describes UART2.

25.1 Introduction

UART2 has a dedicated timer to generate a transfer clock and operate independently. Figure 25.1 shows a Block Diagram of UART2. Figure 25.2 shows a Block Diagram of UART2 Transmit/Receive Unit. Table 25.1 lists the UART 2 Pin Configuration. UART2 supports the following modes:

• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode)
• Special mode 1 (I 2C mode)
• Multiprocessor communication function Figure 25.1 Block Diagram of UART2 n: Value set in U2BRG register RXD2 1/(n+1) 1/16 U2BRG register Clock synchronous type (internal clock selected) Clock synchronous type Clock synchronous type (internal clock selected) Clock synchronous type (external clock selected) CLK2 Clock source selection f32 CKDIR internal CKDIR external RTS2 CTS2 Transmit/ receive unit TXD2 CLK polarity switch circuit CTS/RTS disabled CTS/RTS disabled CTS/RTS selected Receive clock TXD polarity switch circuit CLK1 to CLK0 = 00b = 01b = 10b CKPOL UART reception UART transmission Clock synchronous type CRS = 1 CRS = 0 RXD polarity switch circuit CRD = 0 VSS CKDIR = 0 CKDIR = 1 SMD2 to SMD0 = 010b, 100b, 101b, 110b = 001b CKDIR = 0 SMD0 to SMD2, CKDIR: Bits in U2MR register CLK0, CLK1, CKPOL, CRD, CRS: Bits in U2C0 register DF2EN: Bit in URXDF register CTS2/RTS2 DF2EN = 1 Digital filter DF2EN = 0 = 11b fC CKDIR = 1 = 010b, 100b, 101b, 110b = 001b Transmit clock CRD = 1 Reception control circuit Transmission control circuit

1. Serial Interface (UART2) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 516 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 25.2 Block Diagram of UART2 Transmit/Receive Unit Table 25.1 UART 2 Pin Configuration Pin Name Assigned Pin I/O Function TXD2 P11_1, P11_2 Output Serial data output RXD2 P11_1, P11_2 Input Serial data input CLK2 P11_0 I/O Transfer clock I/O CTS2 P11_3 Input Transmission control input RTS2 P11_3 Output Reception control input SCL2 P11_1, P11_2 I/O I2C mode clock I/O SDA2 P11_1, P11_2 I/O I2C mode data I/O UART (8 bits) UART (9 bits) U2ERE = 1 PAR disabled PAR enabled PRYE = 0 PRYE = 1 2SP STPS = 1 1SP SP SP PAR UART UART (7 bits) UART (8 bits) UART (7 bits) UART (9 bits) Clock synchronous type Data bus low-order bits TXD2 UART2 transmit register D8 D7 D6 D5 D4 D3 D2 D1 D0 SP: Stop bit PAR: Parity bit SMD0 to SMD2, STPS, PRYE, IOPOL, CKDIR: Bits in U2MR register CLK0, CLK1, CKPOL, CRD, CRS: Bits in U2C0 register U2ERE: Bit in U2C1 register U2TB register UART (8 bits) UART (9 bits) I2C Clock synchronous type U2RB register UART2 receive register PAR 1SP PAR enabled PAR disabled UART UART (7 bits) UART (8 bits) UART (7 bits) I2C Clock synchronous type Clock synchronous type RXD2 Data bus high-order bits Logic inversion circuit + MSB/LSB conversion circuit D7 D6 D5 D4 D3 D2 D1 D0D80000000 Inverted Not inverted Error signal output circuit TXD data inversion circuit Error signal output enabled Error signal output disabled Inverted Not inverted Logic inversion circuit + MSB/LSB conversion circuit IOPOL = 0 RXD data inversion circuit STPS = 0 SP 2SP PRYE = 0 SMD = 0 IOPOL = 0 I2C I2C I2C Clock synchronous type IOPOL = 1 SP STPS = 1 PRYE = 1 UART (9 bits) I2C Clock synchronous type U2ERE = 0 IOPOL = 1 STPS = 0 SMD = 1

1. Serial Interface (UART2) REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 517 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

25.2 Registers

25.2.1 UART2 Transmit/Recei ve Mode Register (U2MR)

25.2.2 UART2 Bit Rate Register (U2BRG)

Write to the U2BRG register while transmission and reception stop. Use the MOV instruction to write to this register. Set bits CLK1 to CLK0 in the U2C0 register before writing to the U2BRG register. Address 00A8h B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol IOPOL PRYE PRY STPS CKDIR SMD2 SMD1 SMD0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 SMD0 Serial I/O mode select bit b2 b1 b0 0 0 0: Serial interface disabled 0 0 1: Clock synchronous serial I/O mode 0 1 0: I2C mode 1 0 0: UART mode, transfer data 7 bits long 1 0 1: UART mode, transfer data 8 bits long 1 1 0: UART mode, transfer data 9 bits long Other than above: Do not set. R/W b1 SMD1 R/W b2 SMD2 R/W b3 CKDIR Internal/external clock select bit 0: Internal clock 1: External clock R/W b4 STPS Stop bit length select bit 0: One stop bit 1: Two stop bits R/W b5 PRY Odd/even parity select bit Enabled when PRYE = 1 0: Odd parity 1: Even parity R/W b6 PRYE Parity enable bit 0: Parity disabled 1: Parity enabled R/W b7 IOPOL TXD, RXD I/O polarity switch bit 0: Not inverted 1: Inverted R/W Address 00A9h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t XXXXXXXX Bit Function Setting Range R/W b7 to b0 If the setting value is n, U2BRG divides the count source by n+1. 00h to FFh W

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25.2.3 UART2 Transmit Bu ffer Register (U2TB)

Note: 1. Set bits b0 to b7 after setting the MPTB bit. Address 00ABh to 00AAh B i t b 7b 6b 5b 4b 3b 2b 1 b 0 A f t e r R e s e t XXXXXXX X Bit b15 b14 b13 b12 b11 b10 b9 b8 A f t e r R e s e t XXXXXXX X Bit Symbol Function R/W b0 — Transmit data (D7 to D0) W b1 — b2 — b3 — b4 — b5 — b6 — b7 — b8 MPTB Transmit data (D8) (1) [When the multiprocessor communication function is not used] Transmit data (D8) [When the multiprocessor communication function is used]

• To transfer an ID, set the MPTB bit to 1.
• To transfer data, set the MPTB bit to 0. W b9 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b10 — b11 — b12 — b13 — b14 — b15 —

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25.2.4 UART2 Transmit/Receive Control Register 0 (U2C0)

Notes: 1. If bits CLK1 to CLK0 are switched, set the U2BRG register again. 2. The UFORM bit is enabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode), or set to 101b (UART mode, transfer data 8 bits long). Set the UFORM bit to 1 when bits SMD2 to SMD0 are set to 010b (I2C mode), and to 0 when bits SMD2 to SMD0 are set to 100b (UART mode, transfer data 7 bits long) or 110b (UART mode, transfer data 9 bits long). Address 00ACh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol UFORM CKPOL NCH CRD TXEPT CRS CLK1 CLK0 A f t e r R e s e t 00001000 Bit Symbol Bit Name Function R/W b0 CLK0 U2BRG count source select bit (1) b1 b0 0 0: f1 selected 0 1: f8 selected 1 0: f32 selected 1 1: fC selected R/W b1 CLK1 R/W b2 CRS CTS /RTS function select bit Enabled when CRD = 0 0: CTS function selected 1: RTS function selected R/W b3 TXEPT Transmit register empty flag 0: Data in the transmit register (transmission in progress) 1: No data in the transmit register (transmission completed) R b4 CRD CTS /RTS disable bit 0: CTS /RTS function enabled 1: CTS/RTS function disabled R/W b5 NCH Data output select bit 0: Pins TXD2/SDA2, SCL2 set as CMOS output 1: Pins TXD2/SDA2, SCL2 set as N-channel open-drain output R/W b6 CKPOL CLK polarity select bit 0: Transmit data output at the falling edge and receive data input at the rising edge of the transfer clock 1: Transmit data output at the rising edge and receive data input at the falling edge of the transfer clock R/W b7 UFORM Transfer format select bit (2) 0: LSB first 1: MSB first R/W

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25.2.5 UART2 Transmit/Receive Control Register 1 (U2C1)

Note: 1. The U2LCH bit is enabled when bits SMD2 to SMD0 in the U2MR register are se t to 001b (clock synchronous serial I/O mode), 100b (UART mode, transfer data 7 bits long), or 101b (UART mode, transfer data 8 bits long). Set the U2LCH bit to 0 when bits SMD2 to SMD0 are set to 010b (I2C mode) or 110b (UART mode, transfer data 9 bits long). Address 00ADh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol U2ERE U2LCH U2RRM U2IRS RI RE TI TE A f t e r R e s e t 00000010 Bit Symbol Bit Name Function R/W b0 TE Transmission enable bit 0: Transmission disabled 1: Transmission enabled R/W b1 TI Transmit buffer empty flag 0: Data in the U2TB register 1: No data in the U2TB register R b2 RE Reception enable bit 0: Reception disabled 1: Reception enabled R/W b3 RI Reception complete flag 0: No data in the U2RB register 1: Data in the U2RB register R b4 U2IRS UART2 transmit interrupt source select bit 0: Transmit buffer empty (TI = 1) 1: Transmission completed (TXEPT = 1) R/W b5 U2RRM UART2 continuous receive mode enable bit 0: Continuous receive mode disabled 1: Continuous receive mode enabled R/W b6 U2LCH Data logic select bit (1) 0: Not inverted 1: Inverted R/W b7 U2ERE Error signal output enable bit 0: Output disabled 1: Output enabled R/W

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25.2.6 UART2 Receive Buff er Register (U2RB)

Notes: 1. The ABT bit is set to 0 by writing 0 by a program. (Writing 1 has no effect.) 2. When bits SMD2 to SMD0 in the U2MR register are set to 000b (serial interface disabled) or the RE bit in the U2C1 register is set to 0 (reception disabled), all of bits SUM, PER, FER, and OER are set to 0 (no error). The SUM bit is set to 0 (no error) when all of bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 by reading the lower byte of the U2RB register. 3. These error flags are disabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode) or to 010b (I2C mode). When read, the contents are undefined. Address 00AFh to 00AEh B i t b 7b 6b 5b 4b 3b 2b 1 b 0 A f t e r R e s e t XXXXXXX X Bit b15 b14 b13 b12 b11 b10 b9 b8 Symbol SUM PER FER OER ABT — — MPRB A f t e r R e s e t XXXXXXX X Bit Symbol Bit Name Function R/W b0 — — Receive data (D7 to D0) R b1 — b2 — b3 — b4 — b5 — b6 — b7 — b8 MPRB — Receive data (D8) (2) [When the multiprocessor communication function is not used] Receive data (D8) [When the multiprocessor communication function is used]

• When the MPRB bit is set to 0, received D0 to D7 are data fields.
• When the MPRB bit is set to 1, received D0 to D7 are ID fields. R b9 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b10 — b11 ABT Arbitration lost detect flag (1) 0: Not detected (won) 1: Detected (lost) R b12 OER Overrun error flag (2) 0: No overrun error 1: Overrun error R b13 FER Framing error flag (2, 3) 0: No framing error 1: Framing error R b14 PER Parity error flag (2, 3) 0: No parity error 1: Parity error R b15 SUM Error sum flag (2, 3) 0: No error 1: Error R

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25.2.7 UART2 Digital Filter Func tion Select Register (URXDF)

Note: 1. The RXD2 digital filter can be used only in clock a synchronous serial I/O (UART) mode. When bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode) or 010b (I 2C mode), set the DF2EN bit to 0 (RXD2 digital filter disabled).

25.2.8 UART2 Special Mode Register 5 (U2SMR5)

Note: 1. When the MP bit is set to 1 (multiprocessor communic ation enabled), the settings of bits PRY and PRYE in the U2MR register are disabled. If bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode), set the MP bit to 0 (multiprocessor communication disabled). Address 00B0h B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b1 — b2 DF2EN RXD2 digital filter enable bit (1) 0: RXD2 digital filter disabled 1: RXD2 digital filter enabled R/W b3 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b4 — b5 — b6 — b7 — Address 00BBh B i t b 7b 6b 5b 4b 3b 2b 1b 0 A f t e r R e s e t 00000000 Bit Symbol Bit Name Function R/W b0 MP Multiprocessor communication enable bit 0: Multiprocessor communication disabled 1: Multiprocessor communication enabled (1) R/W b1 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b2 — b3 — b4 MPIE Multiprocessor communication control bit When the MP bit is set to 1 (multiprocessor communication enabled), this bit is enabled. When the MPIE bit is set to 1, the following will result:

• Receive data in which the multiprocessor bit is 0 is ignored. The settings of the RI bit in the U2C1 register and bits OER and FER in the U2RB register to 1 are disabled.
• On receiving receive data in which the multiprocessor bit is 1, the MPIE bit is set to 0 and receive operation other than multiprocessor communication is performed. R/W b5 — Nothing is assigned. If necessary, set to 0. When read, the content is 0. — b6 — b7 — Reserved bit Set to 0. R/W

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25.2.9 UART2 Special Mode Register 4 (U2SMR4)

Note: 1. This bit is set to 0 when the condition is generated.

25.2.10 UART2 Special Mode Register 3 (U2SMR3)

Notes: 1. Bits DL2 to DL0 are used to generate a delay in SDA2 output digitally in I 2C mode. In other than I 2C mode, set these bits to 000b (no delay). 2. The amount of delay varies with the load on pins SC L2 and SDA2. When an external clock is used, the amount of delay increases by about 100 ns. Address 00BCh B i t b 7b 6b 5b 4b 3b 2 b 1 b 0 Symbol SWC9 SCLHI ACKC ACKD STSPSEL STPREQ RSTAREQ STAREQ A f t e r R e s e t 000000 0 0 Bit Symbol Bit Name Function R/W b0 STAREQ Start condition generate bit (1) 0: Clear 1: Start R/W b1 RSTAREQ Restart condition generate bit (1) 0: Clear 1: Start R/W b2 STPREQ Stop condition generate bit (1) 0: Clear 1: Start R/W b3 STSPSEL SCL, SDA output select bit 0: Start and stop conditions not output 1: Start and stop conditions output R/W b4 ACKD ACK data bit 0: ACK 1: NACK R/W b5 ACKC ACK data output enable bit 0: Serial interface data output 1: ACK data output R/W b6 SCLHI SCL output stop enable bit 0: Disabled 1: Enabled R/W b7 SWC9 SCL wait bit 3 0: SCL hold low disabled 1: SCL hold low enabled R/W Address 00BDh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol DL2 DL1 DL0 — NODC — CKPH — A f t e r R e s e t 000X0X0X Bit Symbol Bit Name Function R/W b0 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b1 CKPH Clock phase set bit 0: No clock delay 1: With clock delay R/W b2 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b3 NODC Clock output select bit 0: CLK2 set as CMOS output 1: CLK2 set as N-channel open-drain output R/W b4 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — b5 DL0 SDA2 digital delay setup bit (1, 2) b7 b6 b5 0 0 0: No delay 0 0 1: 1 or 2 cycles of U2BRG count source 0 1 0: 2 or 3 cycles of U2BRG count source 0 1 1: 3 or 4 cycles of U2BRG count source 1 0 0: 4 or 5 cycles of U2BRG count source 1 0 1: 5 or6 cycles of U2BRG count source 1 1 0: 6 or 7 cycles of U2BRG count source 1 1 1: 7 or 8 cycles of U2BRG count source R/W b6 DL1 R/W b7 DL2 R/W

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25.2.11 UART2 Special Mode Register 2 (U2SMR2)

25.2.12 UART2 Special Mo de Register (U2SMR)

Notes: 1. The BBS bit is set to 0 by writing 0 by a program (Writing 1 has no effect). 2. When a transfer begins, the SSS bit is set to 0 (not synchronized to RXD2). Address 00BEh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — SDHI SWC2 STAC ALS SWC CSC IICM2 After Reset X 0000000 Bit Symbol Bit Name Function R/W b0 IICM2 I2C mode select bit 2 Refer to Table 25.12 I2C Mode Functions. R/W b1 CSC Clock synchronization bit 0: Disabled 1: Enabled R/W b2 SWC SCL wait output bit 0: Disabled 1: Enabled R/W b3 ALS SDA output stop bit 0: Disabled 1: Enabled R/W b4 STAC UART2 initialization bit 0: Disabled 1: Enabled R/W b5 SWC2 SCL wait output bit 2 0: Transfer clock 1: Low-level output R/W b6 SDHI SDA output disable bit 0: Enabled 1: Disabled (high impedance) R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. — Address 00BFh B i t b 7b 6b 5b 4b 3b 2b 1b 0 Symbol — SSS ACSE ABSCS — BBS ABC IICM After Reset X 0000000 Bit Symbol Bit Name Function R/W b0 IICM I2C mode select bit 0: Other than I 2C mode 1: I2C mode R/W b1 ABC Arbitration lost detection flag control bit 0: Update per bit 1: Update per byte R/W b2 BBS Bus busy flag (1) 0: Stop condition detected 1: Start condition detected (busy) R/W b3 — Reserved bit Set to 0. R/W b4 ABSCS Bus collision de tection sampling clock select bit 0: Rising edge of transfer clock 1: Underflow signal of Timer RA (2) R/W b5 ACSE Auto clear function select bit of transmission enable bit 0: No auto clear function 1: Auto clear at bus collision occurrence R/W b6 SSS Transmit start condition sele ct bit 0: Not synchronized to RXD2 1: Synchronized to RXD2 (2) R/W b7 — Nothing is assigned. If necessary, set to 0. When read, the content is undefined. —

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25.2.13 UART2 Pin Select Register 0 (U2SR0)

The U2SR0 register selects which pin is assigned as the UART2 input/outp ut. To use the I/O pins for UART2, set this register. Set the U2SR0 register before setting the UART2 associated registers. Also, do not change the setting value of this register during UART2 operation. Address 018Ah B i t b 7 b 6b 5 b 4b 3b 2 b 1 b 0 Symbol — — RXD2SEL1 RXD2SEL0 — — TXD2SEL1 TXD2SEL0 A f t e r R e s e t 0 00 000 0 0 Bit Symbol Bit Name Function R/W b0 TXD2SEL0 TXD2/SDA2 pin select bit b1 b0 0 0: TXD2/SDA2 pin not used 0 1: P11_2 assigned 1 0: P11_1 assigned 1 1: Do not set. R/W b1 TXD2SEL1 R/W b2 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b3 — b4 RXD2SEL0 RXD2/SCL2 pin select bit b5 b4 0 0: RXD2/SCL2 pin not used 0 1: P11_1 assigned 1 0: P11_2 assigned 1 1: Do not set. R/W b5 RXD2SEL1 R/W b6 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b7 —

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25.2.14 UART2 Pin Select Register 1 (U2SR1)

The U2SR1 register selects which pin is assigned as the UART2 input/outp ut. To use the I/O pins for UART2, set this register. Set the U2SR1 register before setting the UART2 associated registers. Also, do not change the setting value of this register during UART2 operation. Address 018Bh B i t b 7b 6b 5 b 4 b 3b 2 b 1 b 0 Symbol — — — CTS2SEL0 — — — CLK2SEL0 A f t e r R e s e t 000 0 00 0 0 Bit Symbol Bit Name Function R/W b0 CLK2SEL0 CLK2 pin select bit 0: CLK2 pin not used 1: CLK2 pin used R/W b1 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b2 — b3 — b4 CTS2SEL0 CTS2 /RTS2 pin select bit 0: CTS2 /RTS2 pin not used 0: CTS2/RTS2 pin used R/W b5 — Nothing is assigned. If necessary, se t to 0. When read, the content is 0. — b6 — b7 —

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