R8C/20

R8C-20_1 RENESAS | Alldatasheet

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www.renesas.com All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). REJ09B0250-0200 R8C/20 Group, R8C/21 Group Hardware Manual RENESAS MCU R8C FAMILY / R8C/2x SERIES Rev.2.00 Revision Date: Aug 27, 2008

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. 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With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Notes regarding these materials

General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.

1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardwa re functions and electrical characteristics of the MCU. It is intended for users de signing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautio nary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section. The revision history summarizes the loca tions of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the R8C/20 Group and R8C/21 Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Document Type Description Document Title Document No. Datasheet Hardware overview and elec trical characteristics R8C/20 Group, R8C/21 Group Datasheet REJ03B0120 Hardware manual Hardware specifications (pin assignments, memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description Note: Refer to the application notes for details on using peripheral functions. R8C/20 Group, R8C/21 Group Hardware Manual This hardware manual Software manual Description of CPU instruction set R8C/Tiny Series Software Manual REJ09B0001 Application note Information on using peripheral functions and application examples Sample programs Information on writing programs in assembly language and C Available from Renesas Technology Web site. Renesas technical update Product specifications, updates on documents, etc.

1. Notation of Numbers and Symbols The notation conventions for register na mes, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,” or “pin” to distinguish the three categories. Examples the PM03 bit in the PM0 register P3_5 pin, VCC pin (2) Notation of Numbers The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: 11b Hexadecimal: EFA0h Decimal: 1234

1. Register Notation The symbols and terms used in register diagrams are described below. Blank: Set to 0 or 1 according to the application. 0: Set to 0. 1: Set to 1. X: Nothing is assigned. RW: Read and write. RO: Read only. WO: Write only. −: Nothing is assigned.

• Reserved bit Reserved bit. Set to specified value.
• Nothing is assigned Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value Operation is not guaranteed when a value is set.
• Function varies according to the operating mode. The function of the bit varies with the peripheral functi on mode. Refer to the regist er diagram for information on the individual modes. XXX Register Symbol Address After Reset XXX XXX 00h Bit NameBit Symbol RW b7 b6 b5 b4 b3 b2 b1 b0 XXX bits 1 0: XXX 0 1: XXX 1 0: Do not set. 1 1: XXX b1 b0 XXX1 XXX0 XXX4 Reserved bits XXX5 XXX7 XXX6 Function Nothing is assigned. If necessary, set to 0. When read, the content is undefined. XXX bit Function varies according to the operating mode. Set to 0. (b3) (b2) RW RW RW RW WO RW RO XXX bits 0: XXX 1: XXX

1. List of Abbrevia tions and Acronyms Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bps bits per second CRC Cyclic Redundancy Check DMA Direct Memory Access DMAC Direct Memory Access Controller GSM Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus I/O Input / Output IrDA Infrared Data Association LSB Least Significant Bit MSB Most Significant Bit NC Non-Connect PLL Phase Locked Loop PWM Pulse Width Modulation SIM Subscriber Identity Module UART Universal Asynchronous Receiver / Transmitter VCO Voltage Controlled Oscillator All trademarks and registered trademarks are the property of their respective owners.All trademarks and registered trademarks are the property of their respective owners.

12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts and I 2C bus Interface

21.9.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and

NOTE: 1. Blank columns are all reserved space. No access is allowed. Address Register Symbol Page 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 PM0 62 0005h Processor Mode Register 1 PM1 62 0006h System Clock Control Register 0 CM0 66 0007h System Clock Control Register 1 CM1 67 0008h 0009h 000Ah Protect Register PRCR 86 000Bh 000Ch Oscillation Stop Detection Register OCD 68 000Dh Watchdog Timer Reset Register WDTR 115 000Eh Watchdog Timer Start Register WDTS 115 000Fh Watchdog Timer Control Register WDC 114 0010h Address Match Interrupt Register 0 RMAD0 107 0011h 0012h 0013h Address Match Interrupt Enable Register AIER 107 0014h Address Match Interrupt Register 1 RMAD1 107 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch Count Source Protect Mode Register CSPR 115 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 69 0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 69 0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 70 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h Voltage Detection Register 1 VCA1 31 0032h Voltage Detection Register 2 VCA2 31, 70 0033h 0034h 0035h 0036h Voltage Monitor 1 Circuit Control Register VW1C 32 0037h Voltage Monitor 2 Circuit Control Register VW2C 33 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Address Register Symbol Page 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h Timer RD0 Interrupt Control Register TRD0IC 93 0049h Timer RD1 Interrupt Control Register TRD1IC 93 004Ah Timer RE Interrupt Control Register TREIC 92 004Bh 004Ch 004Dh Key Input Interrupt Control Register KUPIC 92 004Eh A/D Conversion Interrupt Control Register ADIC 92 004Fh SSU Interrupt Control Register/IIC Bus Interrupt Control Register SSUIC/IICIC 93 0050h 0051h UART0 Transmit Interrupt Control Register S0TIC 92 0052h UART0 Receive Interrupt Control Register S0RIC 92 0053h UART1 Transmit Interrupt Control Register S1TIC 92 0054h UART1 Receive Interrupt Control Register S1RIC 92 0055h INT2 Interrupt Control Register INT2IC 94 0056h Timer RA Interrupt Control Register TRAIC 92 0057h 0058h Timer RB Interrupt Control Register TRBIC 92 0059h INT1 Interrupt Control Register INT1IC 94 005Ah INT3 Interrupt Control Register INT3IC 94 005Bh 005Ch 005Dh INT0 Interrupt Control Register INT0IC 94 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh

NOTE: 1. Blank columns are all reserved space. No access is allowed. Address Register Symbol Page 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register U0MR 268 00A1h UART0 Bit Rate Register U0BRG 267 00A2h UART0 Transmit Buffer Register U0TB 267 00A3h 00A4h UART0 Transmit/Receive Control Register 0 U0C0 269 00A5h UART0 Transmit/Receive Control Register 1 U0C1 269 00A6h UART0 Receive Buffer Register U0RB 267 00A7h 00A8h UART1 Transmit/Receive Mode Register U1MR 268 00A9h UART1 Bit Rate Register U1BRG 267 00AAh UART1 Transmit Buffer Register U1TB 267 00ABh 00ACh UART1 Transmit/Receive Control Register 0 U1C0 269 00ADh UART1 Transmit/Receive Control Register 1 U1C1 269 00AEh UART1 Receive Buffer Register U1RB 267 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h SS Control Register H/IIC Bus Control Register 1 SSCRH/ICCR1 285, 315 00B9h SS Control Register L/IIC Bus Control Register 2 SSCRL/ICCR2 286, 316 00BAh SS Mode Register/IIC Bus Mode Register 1 SSMR/ICMR 287, 317 00BBh SS Enable Register/IIC Bus Interrupt Enable Register SSER/ICIER 288, 318 00BCh SS Status Register/IIC Bus Status Register SSSR/ICSR 289, 319 00BDh SS Mode Register 2/Slave Address Register SSMR2/SAR 290, 320 00BEh SS Transmit Data Register/IIC Bus Transmit Data Register SSTDR/ICDRT 291, 320 00BFh SS Receive Data Register/IIC Bus Receive Data Register SSRDR/ ICDRR 291, 321 Address Register Symbol Page 00C0h A/D Register AD 363 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Control Register 2 ADCON2 363 00D5h 00D6h A/D Control Register 0 ADCON0 362, 365, 368 00D7h A/D Control Register 1 ADCON1 363, 366, 369 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h Port P0 Register P0 48 00E1h Port P1 Register P1 48 00E2h Port P0 Direction Register PD0 48 00E3h Port P1 Direction Register PD1 48 00E4h Port P2 Register P2 48 00E5h Port P3 Register P3 48 00E6h Port P2 Direction Register PD2 48 00E7h Port P3 Direction Register PD3 48 00E8h Port P4 Register P4 48 00E9h 00EAh Port P4 Direction Register PD4 48 00EBh 00ECh Port P6 Register P6 48 00EDh 00EEh Port P6 Direction Register PD6 48 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h UART1 Function Select Register U1SR 270 00F6h 00F7h 00F8h Port Mode Register PMR 49, 270, 291, 321 00F9h External Input Enable Register INTEN 101 00FAh INT Input Filter Select Register INTF 102 00FBh Key Input Enable Register KIEN 105 00FCh Pull-Up Control Register 0 PUR0 49 00FDh Pull-Up Control Register 1 PUR1 49 00FEh 00FFh

NOTE: 1. Blank columns are all reserved space. No access is allowed. Address Register Symbol Page 0100h Timer RA Control Register TRACR 121 0101h Timer RA I/O Control Register TRAIOC 121, 124, 127, 129, 131, 134 0102h Timer RA Mode Register TRAMR 122 0103h Timer RA Prescaler Register TRAPRE 122 0104h Timer RA Register TRA 123 0105h 0106h LIN Control Register LINCR 347 0107h LIN Status Register LINST 348 0108h Timer RB Control Register TRBCR 138 0109h Timer RB One-Shot Control Register TRBOCR 138 010Ah Timer RB I/O Control Register TRBIOC 139, 141, 145, 148, 153 010Bh Timer RB Mode Register TRBMR 139 010Ch Timer RB Prescaler Register TRBPRE 140 010Dh Timer RB Secondary Register TRBSC 140 010Eh Timer RB Primary TRBPR 140 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h Timer RE Counter Data Register TRESEC 260 0119h Timer RE Compare Data Register TREMIN 260 011Ah 011Bh 011Ch Timer RE Control Register 1 TRECR1 261 011Dh Timer RE Control Register 2 TRECR2 261 011Eh Timer RE Count Source Select Register TRECSR 262 011Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h Timer RD Start Register TRDSTR 172, 186, 202, 215, 225, 239 0138h Timer RD Mode Register TRDMR 172, 186, 203, 216, 226, 240 0139h Timer RD PWM Mode Register TRDPMR 173, 187, 203 013Ah Timer RD Function Control Register TRDFCR 174, 188, 204, 216, 227, 240 013Bh Timer RD Output Master Enable Register 1 TRDOER1 189, 205, 217, 228, 241 013Ch Timer RD Output Master Enable Register 2 TRDOER2 189, 205, 217, 228, 241 013Dh Timer RD Output Control Register TRDOCR 190, 206, 242 013Eh Timer RD Digital Filter Function Select Register 0 TRDDF0 175 013Fh Timer RD Digital Filter Function Select Register 1 TRDDF1 175 Address Register Symbol Page 0140h Timer RD Control Register 0 TRDCR0 176, 191, 206, 218, 229, 243 0141h Timer RD I/O Control Register A0 TRDIORA0 177, 192 0142h Timer RD I/O Control Register C0 TRDIORC0 178, 193 0143h Timer RD Status Register 0 TRDSR0 179, 194, 207, 219, 230, 244 0144h Timer RD Interrupt Enable Register 0 TRDIER0 180, 195, 208, 220, 231, 245 0145h Timer RD PWM Mode Output Level Control Register 0 TRDPOCR0 209 0146h Timer RD Counter 0 TRD0 180, 195, 209, 220, 232, 2450147h 0148h Timer RD General Register A0 TRDGRA0 181, 196, 210, 221, 232, 2460149h 014Ah Timer RD General Register B0 TRDGRB0 181, 196, 210, 221, 232, 246014Bh 014Ch Timer RD General Register C0 TRDGRC0 181, 196, 210, 221, 246014Dh 014Eh Timer RD General Register D0 TRDGRD0 181, 196, 210, 221, 232, 246014Fh 0150h Timer RD Control Register 1 TRDCR1 176, 191, 206, 229 0151h Timer RD I/O Control Register A1 TRDIORA1 177, 192 0152h Timer RD I/O Control Register C1 TRDIORC1 178, 193 0153h Timer RD Status Register 1 TRDSR1 179, 194, 207, 219, 230, 244 0154h Timer RD Interrupt Enable Register 1 TRDIER1 180, 195, 208, 220, 231, 245 0155h Timer RD PWM Mode Output Level Control Register 1 TRDPOCR1 209 0156h Timer RD Counter 1 TRD1 180, 195, 209, 2320157h 0158h Timer RD General Register A1 TRDGRA1 181, 196, 210, 221, 232, 2460159h 015Ah Timer RD General Register B1 TRDGRB1 181, 196, 210, 221, 232, 246015Bh 015Ch Timer RD General Register C1 TRDGRC1 181, 196, 210, 221, 232, 246015Dh , 015Eh Timer RD General Register D1 TRDGRD1 181, 196, 210, 221, 232, 246015Fh 01B0h 01B1h 01B2h 01B3h Flash Memory Control Register 4 FMR4 388 01B4h 01B5h Flash Memory Control Register 1 FMR1 387 01B6h 01B7h Flash Memory Control Register 0 FMR0 386 01B8h 01B9h 01BAh 01BBh FFFFh Option Function Select Register OFS 23, 114, 381

Rev.2.00 Aug 27, 2008 Page 1 of 458 REJ09B0250-0200 R8C/20 Group, R8C/21 Group RENESAS MCU 1. Overview This MCU is built using the high-perfo rmance silicon gate CMOS process us ing the R8C CPU core and is packaged in a 48-pin plastic molded LQFP. This MCU operates using sophisticated in structions featuring a high level of instruction efficiency. With 1 Mbyte of address space, it is capable of executi ng instructions at high speed. This Furthermore, the data flash (1 KB x 2 blocks) is embedded in the R8C/21 Group. The difference between R8C/20 and R8C/21 Groups is only the existence of the data flash. Their peripheral functions are the same.

1.1 Applications

Automotive, etc. REJ09B0250-0200 Rev.2.00 Aug 27, 2008

R8C/20 Group, R8C/21 Group 1. Overview Rev.2.00 Aug 27, 2008 Page 2 of 458 REJ09B0250-0200

1.2 Performance Overview

Table 1.1 outlines the Functions and Specifications for R8C/20 Group and Ta ble 1.2 outlines the Functions and Specifications for R8C/21 Group. NOTES: 1. When using options, be sure to inquire about the specification. 2. I 2C bus is a registered trademark of Koninklijke Philips Electronics N.V. Table 1.1 Functions and Specifications for R8C/20 Group Item Specification CPU Number of fundamental in structions 89 instructions Minimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.3 Product Information for R8C/20 Group Peripheral Function Ports I/O ports: 41 pins, Input port: 3 pins Timers Timer RA: 8 bits x 1 channel, Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RD: 16 bits x 2 channel (Circuits of input capture and output compare) Timer RE: With compare match function Serial interface 1 channel (UART0) Clock synchronous I/O, UART 1 channel (UART1) UART Clock synchronous serial interface 1 channel I2C bus interface(2), Clock synchronous serial I/O with chip select LIN module Hardware LIN: 1 channel (timer RA, UART0) A/D converter 10-bit A/D conv erter: 1 circuit, 12 channels Watchdog timer 15 bits x 1 channel (with prescaler) Reset start selectable Interrupt Internal: 11 sources, Extern al: 5 sources, Software: 4 sources, Priority level: 7 levels Clock generation circuits 2 circuits XIN clock generation circuit (with on-chip feedback resistor) On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has frequency adjustment function. Oscillation stop detection function Stop detection of XIN clock oscillation Voltage detection circuit On-chip Power-on reset circuit include On-chip Electric Characteristics Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)(J version) VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz)(K version) VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) Current consumption Typ. 11.0 mA (VCC = 5 V, f(XIN) = 20 MHz, High-speed on- chip oscillator stopping) Typ. 5.3 mA (VCC = 5 V, f(XIN) = 10 MHz, High-speed on-chip oscillator stopping) Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure endurance 100 times Operating Ambient Temperature -40 to 85 °C -40 to 125°C (option (1)) Package 48-pin mold-plastic LQFP

R8C/20 Group, R8C/21 Group 1. Overview Rev.2.00 Aug 27, 2008 Page 3 of 458 REJ09B0250-0200 NOTES: 1. When using options, be sure to inquire about the specification. 2. I 2C bus is a registered trademark of Koninklijke Philips Electronics N.V. Table 1.2 Functions and Specifications for R8C/21 Group Item Specification CPU Number of fundamental in structions 89 instructions Minimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.4 Product Information for R8C/21 Group Peripheral Function Ports I/O ports: 41 pins, Input port: 3 pins Timers Timer RA: 8 bits x 1 channel, Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RD: 16 bits x 2 channel (Circuits of input capture and output compare) Timer RE: With compare match function Serial interface 1 channel (UART0) Clock synchronous I/O, UART 1 channel (UART1) UART Clock synchronous serial interface 1 channel I2C bus interface(2), Clock synchronous serial I/O with chip select LIN module Hardware LIN: 1 channel (Timer RA, UART0) A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits x 1 channel (with prescaler) Reset start selectable Interrupts Internal: 11 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels Clock generation circuits 2 circuits XIN clock generation circuit (with on-chip feedback resistor) On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has frequency adjustment function. Oscillation stop detection function Stop detection of XIN clock oscillation Voltage detection circuit On-chip Power-on reset circuit include On-chip Electric Characteristics Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)(J version) VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz)(K version) VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) Current consumption Typ. 11.0 mA (VCC = 5 V, f(XIN) = 20 MHz, High-speed on- chip oscillator stopping) Typ. 5.3 mA (VCC = 5 V, f(XIN) = 10 MHz, High-speed on-chip oscillator stopping) Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure endurance 10,000 times (data flash) 1,000 times (program ROM) Operating Ambient Temperature -40 to 85 °C -40 to 125°C (option (1)) Package 48-pin mold-plastic LQFP

R8C/20 Group, R8C/21 Group 1. Overview Rev.2.00 Aug 27, 2008 Page 4 of 458 REJ09B0250-0200

1.3 Block Diagram

Figure 1.1 shows a Block Diagram. Figure 1.1 Block Diagram R8C CPU core Timer Timer RA (8 bits) Timer RB (8 bits) Timer RD (16 bits × 2 channels) Timer RE (8 bits) A/D converter (10 bits × 12 channels) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator UART or clock synchronous serial I/O (8 bits × 1 channel) MemoryWatchdog timer (15 bits) ROM(1) RAM(2) Multiplier R0H R0L R1H R1L FB SB USP ISP INTB PC FLG I/O port NOTES: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. I2C bus interface or clock synchronous serial I/O with chip select (8 bits × 1 channel) Port P1 Port P3 3 3 Port P4 Port P0 Port P2 Port P6 UART (8 bits × 1 channel) LIN module (1 channel)

R8C/20 Group, R8C/21 Group 1. Overview Rev.2.00 Aug 27, 2008 Page 5 of 458 REJ09B0250-0200

1.4 Product Information

Table 1.3 lists Product Information for R8C/20 Group and Table 1.4 lists Product Information for R8C/21 Group. NOTE: 1. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger. Figure 1.2 Type Number, Memory Size, and Package of R8C/20 Group Table 1.3 Product Information for R8C/20 Group Current of Aug. 2008 Type No. ROM Capacity RAM Capacity Package Type Remarks R5F21206JFP 32 Kbytes 2 Kbytes PLQP0048KB-A J version Flash memory versionR5F21207JFP 48 Kbytes 2.5 Kbytes PLQP0048KB-A R5F21208JFP 64 Kbytes 3 Kbytes PLQP0048KB-A R5F2120AJFP 96 Kbytes 5 Kbytes PLQP0048KB-A R5F2120CJFP 128 Kbytes(1) 6 Kbytes PLQP0048KB-A R5F21206KFP 32 Kbytes 2 Kbytes PLQP0048KB-A K version R5F21207KFP 48 Kbytes 2.5 Kbytes PLQP0048KB-A R5F21208KFP 64 Kbytes 3 Kbytes PLQP0048KB-A R5F2120AKFP 96 Kbytes 5 Kbytes PLQP0048KB-A R5F2120CKFP 128 Kbytes(1) 6 Kbytes PLQP0048KB-A Part number R 5 F 21 20 6 J XXX FP Package type: FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body) ROM number Classification J: Operating ambient temperature -40°C to 85°C (J version) K: Operating ambient temperature -40°C to 125°C (K version) ROM capacity 6: 32 KB 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/20 Group R8C/2x Series Memory type F: Flash memory version Renesas MCU Renesas semiconductors

R8C/20 Group, R8C/21 Group 1. Overview Rev.2.00 Aug 27, 2008 Page 6 of 458 REJ09B0250-0200 NOTE: 1. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger. Figure 1.3 Type Number, Memory Size, and Package of R8C/21 Group Table 1.4 Product Information for R8C/21 Group Current of Aug. 2008 Type No. ROM Capacity RAM Capacity Package Type RemarksProgram ROM Data Flash R5F21216JFP 32 Kbytes 1 Kbyte X 2 2 Kbytes PLQP0048KB-A J version Flash memory version R5F21217JFP 48 Kbytes 1 Kbyte X 2 2.5 Kbytes PLQP0048KB-A R5F21218JFP 64 Kbytes 1 Kbyte X 2 3 Kbytes PLQP0048KB-A R5F2121AJFP 96 Kbytes 1 Kbyte X 2 5 Kbytes PLQP0048KB-A R5F2121CJFP 128 Kbytes(1) 1 Kbyte X 2 6 Kbytes PLQP0048KB-A R5F21216KFP 32 Kbytes 1 Kbyte X 2 2 Kbytes PLQP0048KB-A K version R5F21217KFP 48 Kbytes 1 Kbyte X 2 2.5 Kbytes PLQP0048KB-A R5F21218KFP 64 Kbytes 1 Kbyte X 2 3 Kbytes PLQP0048KB-A R5F2121AKFP 96 Kbytes 1 Kbyte X 2 5 Kbytes PLQP0048KB-A R5F2121CKFP 128 Kbytes (1) 1 Kbyte X 2 6 Kbytes PLQP0048KB-A Part number R 5 F 21 21 6 J XXX FP Package type: FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body) ROM number Classification J: Operating ambient temperature -40°C to 85°C (J version) K: Operating ambient temperature -40°C to 125°C (K version) ROM capacity 6: 32 KB 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/21 Group R8C/2x Series Memory type F: Flash memory version Renesas MCU Renesas semiconductors

R8C/20 Group, R8C/21 Group 1. Overview Rev.2.00 Aug 27, 2008 Page 7 of 458 REJ09B0250-0200

1.5 Pin Assignments

Figure 1.4 shows Pin Assignments (Top View). Figure 1.4 Pin Assignments (Top View) 48P3_7/SSO 47P0_0/AN7 46P0_1/AN6 45P0_2/AN5 44P0_3/AN4 43P6_1 42P6_2 41P6_0/TREO 40P4_2/VREF 39P0_4/AN3 38P0_5/AN2 37P0_6/AN1 P2_6/TRDIOC1 P2_5/TRDIOB1 P2_4/TRDIOA1 P2_3/TRDIOD0 P2_2/TRDIOC0 P2_1/TRDIOB0 P2_0/TRDIOA0/TRDCLK P1_7/TRAIO/INT1 P1_6/CLK0 P1_5/RXD0/(TRAIO)/(INT1)(2) P1_4/TXD0 P1_3/KI3/AN11 12P2_7/TRDIOD1 11VCC/AVCC 10P4_6/XIN 9VSS/AVSS 8(1)P4_7/XOUT 7RESET 6P4_4 5P4_3 4MODE 3P3_4/SDA/SCS 2P3_3/SSI 1P3_5/SCL/SSCK P4_5/INT0 P6_6/INT2/TXD1 P6_7/INT3/RXD1 P1_2/KI2/AN10 P1_1/KI1/AN9 P1_0/KI0/AN8 P3_1/TRBO P3_0/TRAO P6_5 P6_4 P6_3 P0_7/AN0 Pin assignments (top view) 0.5 mm pin pitch, 7 mm square body R8C/20 Group, R8C/21 Group NOTES: 1. P4_7 is an input-only port. 2. Can be assigned to the pin in parentheses by a program. 3. Confirm the pin 1 position on the package by referring to the package dimensions.

R8C/20 Group, R8C/21 Group 1. Overview Rev.2.00 Aug 27, 2008 Page 8 of 458 REJ09B0250-0200

1.6 Pin Functions

Table 1.5 lists the Pin Functions and Table 1.6 lists the Pin Name Information by Pin Number. I: Input O: Output I/ O: Input and output Table 1.5 Pin Functions Type Symbol I/O Type Description Power Supply Input VCC VSS I Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Analog Power Supply Input AVCC, AVSS I Applies the power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Reset Input RESET I Input “L” on this pin resets the MCU. MODE MODE I Connect this pin to VCC via a resistor. XIN Clock Input XIN I These pins are provided for the XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. XIN Clock Output XOUT O INT Interrupt Input INT0 to INT3 II N T interrupt input pins. INT0 Timer RD input pins. INT1 Timer RA input pins. Key Input Interrupt KI0 to KI3 I Key input interrupt input pins. Timer RA TRAIO I/O Timer RA I/O pin. TRAO O Timer RA output pin. Timer RB TRBO O Timer RB output pin. Timer RD TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 I/O Timer RD I/O ports. TRDCLK I External clock input pin. Timer RE TREO O Divided clock output pin. Serial Interface CLK0 I/O Transfer clock I/O pin. RXD0, RXD1 I Serial data input pins. TXD0, TXD1 O Serial data output pins. I 2C Bus Interface SCL I/O Clock I/O pin. SDA I/O Data I/O pin. Clock Synchronous Serial I/O with Chip Select SSI I/O Data I/O pin. SCS I/O Chip-select signal I/O pin. SSCK I/O Clock I/O pin. SSO I/O Data I/O pin. Reference Voltage Input VREF I Reference voltage input pin to A/D converter. A/D Converter AN0 to AN11 I Analog input pins to A/D converter. I/O Port P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, P6_0 to P6_7 I/O CMOS I/O ports. Each port contains an input/output select direction register, allowing each pin in that port to be directed for input or output individually. Any port set to input can select whether to use a pull-up resistor or not by a program. Input Port P4_2, P4_6, P4_7 I Input only ports.

R8C/20 Group, R8C/21 Group 1. Overview Rev.2.00 Aug 27, 2008 Page 9 of 458 REJ09B0250-0200 NOTE: 1. Can be assigned to the pin in parentheses by a program. Table 1.6 Pin Name Information by Pin Number Pin Number Control Pin Port I/O Pin Functions for of Peripheral Modules Interrupt Timer Serial Interface Clock Synchronous Serial I/O with Chip Select I2C Bus Interface A/D Converter

1 P3_5 SSCK SCL

2 P3_3 SSI

3P 3 _ 4 SCS SDA 4M O D E 5P 4 _ 3 6P 4 _ 4

7 RESET

8X O U T P 4 _ 7

9 VSS/AVSS

10 XIN P4_6

11 VCC/AVCC

12 P2_7 TRDIOD1

13 P2_6 TRDIOC1

14 P2_5 TRDIOB1

15 P2_4 TRDIOA1

16 P2_3 TRDIOD0

17 P2_2 TRDIOC0

18 P2_1 TRDIOB0

19 P2_0 TRDIOA0/TRDCLK

20 P1_7 INT1

21 P1_6 CLK0

22 P1_5 (INT1)(1) (TRAIO)(1) RXD0

23 P1_4 TXD0

24 P1_3 KI3 AN11

25 P4_5 INT0 INT0

26 P6_6 INT2 TXD1

27 P6_7 INT3 RXD1

28 P1_2 KI2 AN10

29 P1_1 KI1 AN9

30 P1_0 KI0 AN8

31 P3_1 TRBO

32 P3_0 TRAO

33 P6_5

34 P6_4

35 P6_3

36 P0_7 AN0

37 P0_6 AN1

38 P0_5 AN2

39 P0_4 AN3

40 VREF P4_2

41 P6_0 TREO

42 P6_2

43 P6_1

44 P0_3 AN4

45 P0_2 AN5

46 P0_1 AN6

47 P0_0 AN7

48 P3_7 SSO

R8C/20 Group, R8C/21 Group 2. Central Processing Unit (CPU) Rev.2.00 Aug 27, 2008 Page 11 of 458 REJ09B0250-0200

2.1 Data Registers (R 0, R1, R2 and R3)

R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register (R2R0). The same applies R3R1 as R2R0.

2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect a ddressing and address register relative addressing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A1 can be combined with A0 to be used a 32-bit address register (A1A0).

2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB, a 20-bit register, indicates the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC, 20 bits wide, indicates the address of an instruction to be executed.

2.6 User Stack Pointer (USP) a nd Interrupt Stack Pointer (ISP)

The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch between USP and ISP.

2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.

2.8 Flag Register (FLG)

FLG is a 11-bit register indicating the CPU status.

2.8.1 Carry Flag (C)

The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic and logic unit.

2.8.2 Debug Flag (D)

The D flag is for debug only. Set to 0.

2.8.3 Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation resulted in 0; otherwise, 0.

2.8.4 Sign Flag (S)

The S flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, 0.

2.8.5 Register Bank Select Flag (B)

The register bank 0 is selected when the B flag is 0. The register bank 1 is selected when this flag is set to 1.

2.8.6 Overflow Flag (O)

The O flag is set to 1 when the operation resulted in an overflow; otherwise, 0.

R8C/20 Group, R8C/21 Group 2. Central Processing Unit (CPU) Rev.2.00 Aug 27, 2008 Page 12 of 458 REJ09B0250-0200

2.8.7 Interrupt Enable Flag (I)

The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hard ware interrupt request is acknowledge d or the INT instruction of software interrupt numbers. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

R8C/20 Group, R8C/21 Group 3. Memory Rev.2.00 Aug 27, 2008 Page 13 of 458 REJ09B0250-0200 3. Memory

3.1 R8C/20 Group

Figure 3.1 shows a Memory Map of R8C/20 Group. The R8C/20 Group has 1 Mbyte of address space from address 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal RAM is allocated addresses 00400h to 00DFFh. Th e internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFR) are allocated addr esses 00000h to 002FFh. The peripheral function control registers are allocated here. All addr esses within the SFR, which have noth ing allocated are reserved for future user and cannot be accessed by users. Figure 3.1 Memory Map of R8C/20 Group Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer•oscillation stop detection•voltage detection Address break (Reserved) Reset FFFFFh 0FFFFh 0YYYYh 0XXXXh 00400h 002FFh 00000h Internal ROM (program ROM) Internal RAM SFR (Refer to 4. Special Function Registers (SFRs)) 0FFFFh 0FFDCh NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger. Reserved area 01300h 02000h Internal ROM(2) (program ROM) Part Number Internal ROM Size Address 0YYYYh Address ZZZZZh R5F21206JFP, R5F21206KFP R5F21207JFP, R5F21207KFP R5F21208JFP, R5F21208KFP R5F2120AJFP, R5F2120AKFP R5F2120CJFP, R5F2120CKFP

32 Kbytes

48 Kbytes

64 Kbytes

96 Kbytes

128 Kbytes

2 Kbytes

2.5 Kbytes

3 Kbytes

5 Kbytes

6 Kbytes

R8C/20 Group, R8C/21 Group 3. Memory Rev.2.00 Aug 27, 2008 Page 14 of 458 REJ09B0250-0200

3.2 R8C/21 Group

Figure 3.2 shows a Memory Map of R8C/21 Group. The R8C/21 Group has 1 Mbyte of address space from address 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal RAM is allocated addresses 00400h to 00DFFh. Th e internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFR) are allocated addr esses 00000h to 002FFh. The peripheral function control registers are allocated them. All addre sses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users. Figure 3.2 Memory Map of R8C/21 Group Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer•oscillation stop detection•voltage detection Address break (Reserved) Reset FFFFFh 0FFFFh 0YYYYh 0XXXXh 00400h 002FFh 00000h Internal ROM (program ROM) Internal RAM SFR (Refer to 4. Special Function Registers (SFRs)) 0FFFFh 0FFDCh 02BFFh 02400h Internal ROM (data flash)(1) Reserved area01300h 02000h Internal ROM(3) (program ROM)ZZZZZh NOTES: 1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown. 2. The blank regions are reserved. Do not access locations in these regions. 3. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger. Part Number Internal ROM Size Address 0YYYYh Address ZZZZZh R5F21216JFP, R5F21216KFP R5F21217JFP, R5F21217KFP R5F21218JFP, R5F21218KFP R5F2121AJFP, R5F2121AKFP R5F2121CJFP, R5F2121CKFP

R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) Rev.2.00 Aug 27, 2008 Page 15 of 458 REJ09B0250-0200 4. Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Table 4.1 to Table 4.6 list the SFR Information. Table 4.1 SFR Information (1) (1) X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect this register. 3. The LVD0ON bit in the OFS register is set to 1. 4. Power-on reset, voltage monitor 1 reset or the LVD0ON bit in the OFS register is set to 0. 5. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b2 and b3. 6. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b7. 7. Software reset, the watchdog timer rest, and the voltage monitor 2 reset do not affect other than the b0 and b6. 8. The CSPROINI bit in the OFS register is 0. Address Register Symbol After reset 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 PM0 00h 0005h Processor Mode Register 1 PM1 00h 0006h System Clock Control Register 0 CM0 01101000b 0007h System Clock Control Register 1 CM1 00100000b 0008h 0009h 000Ah Protect Register PRCR 00h 000Bh 000Ch Oscillation Stop Detection Register OCD 00000100b 000Dh Watchdog Timer Reset Register WDTR XXh 000Eh Watchdog Timer Start Register WDTS XXh 000Fh Watchdog Timer Control Register WDC 00X11111b 0010h Address Match Interrupt Register 0 RMAD0 00h 0011h 00h 0012h 00h 0013h Address Match Interrupt Enable Register AIER 00h 0014h Address Match Interrupt Register 1 RMAD1 00h 0015h 00h 0016h 00h 0017h 0018h 0019h 001Ah 001Bh 001Ch Count Source Protect Mode Register CSPR 00h 10000000b (8) 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h 0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping 0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h 0026h 0030h 0031h Voltage Detection Register 1 (2) VCA1 00001000b 0032h Voltage Detection Register 2(6) VCA2 00h(3) 01000000b(4) 0033h 0034h 0035h 0036h Voltage Monitor 1 Circuit Control Register (7) VW1C 0000X000b(3) 0100X001b(4) 0037h Voltage Monitor 2 Circuit Control Register(5) VW2C 00h 0038h 0039h 003Fh

R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) Rev.2.00 Aug 27, 2008 Page 16 of 458 REJ09B0250-0200 Table 4.2 SFR Information (2) (1) X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Selected by the IICSEL bit in the PMR register. Address Register Symbol After reset 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h Timer RD0 Interrupt Control Register TRD0IC XXXXX000b 0049h Timer RD1 Interrupt Control Register TRD1IC XXXXX000b 004Ah Timer RE Interrupt Control Register TREIC XXXXX000b 004Bh 004Ch 004Dh Key Input Interrupt Control Register KUPIC XXXXX000b 004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b 004Fh SSU Interrupt Control Register/IIC Bus Interrupt Control Register (2) SSUIC/IICIC XXXXX000b 0050h 0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b 0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b 0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b 0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b 0055h INT2 Interrupt Control Register INT2IC XX00X000b 0056h Timer RA Interrupt Control Register TRAIC XXXXX000b 0057h 0058h Timer RB Interrupt Control Register TRBIC XXXXX000b 0059h INT1 Interrupt Control Register INT1IC XX00X000b 005Ah INT3 Interrupt Control Register INT3IC XX00X000b 005Bh 005Ch 005Dh INT0 Interrupt Control Register INT0IC XX00X000b 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh

R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) Rev.2.00 Aug 27, 2008 Page 17 of 458 REJ09B0250-0200 Table 4.3 SFR Information (3) (1) X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Selected by the IICSEL bit in the PMR register. Address Register Symbol After reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register U0MR 00h 00A1h UART0 Bit Rate Register U0BRG XXh 00A2h UART0 Transmit Buffer Register U0TB XXh 00A3h XXh 00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b 00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b 00A6h UART0 Receive Buffer Register U0RB XXh 00A7h XXh 00A8h UART1 Transmit/Receive Mode Register U1MR 00h 00A9h UART1 Bit Rate Register U1BRG XXh 00AAh UART1 Transmit Buffer Register U1TB XXh 00ABh XXh 00ACh UART1 Transmit/Receive Control Register 0 U1C0 00001000b 00ADh UART1 Transmit/Receive Control Register 1 U1C1 00000010b 00AEh UART1 Receive Buffer Register U1RB XXh 00AFh XXh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h SS Control Register H/IIC Bus Control Register 1 (2) SSCRH/ICCR1 00h 00B9h SS Control Register L/IIC Bus Control Register 2(2) SSCRL/ICCR2 0 1111101b 00BAh SS Mode Register/IIC Bus Mode Register 1(2) SSMR/ICMR 00011000b 00BBh SS Enable Register/IIC Bus Interrupt Enable Register(2) SSER/ICIER 00h 00BCh SS Status Register/IIC Bus Status Register(2) SSSR/ICSR 00h/0000X000b 00BDh SS Mode Register 2/Slave Address Register(2) SSMR2/SAR 00h 00BEh SS Transmit Data Register/IIC Bus Transmit Data Register(2) SSTDR/ICDRT FFh 00BFh SS Receive Data Register/IIC Bus Receive Data Register(2) SSRDR/ICDRR FFh

R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) Rev.2.00 Aug 27, 2008 Page 18 of 458 REJ09B0250-0200 Table 4.4 SFR Information (4) (1) X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Address Register Symbol After reset 00C0h A/D Register AD XXh 00C1h XXh 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Control Register 2 ADCON2 00h 00D5h 00D6h A/D Control Register 0 ADCON0 00h 00D7h A/D Control Register 1 ADCON1 00h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h Port P0 Register P0 XXh 00E1h Port P1 Register P1 XXh 00E2h Port P0 Direction Register PD0 00h 00E3h Port P1 Direction Register PD1 00h 00E4h Port P2 Register P2 XXh 00E5h Port P3 Register P3 XXh 00E6h Port P2 Direction Register PD2 00h 00E7h Port P3 Direction Register PD3 00h 00E8h Port P4 Register P4 XXh 00E9h 00EAh Port P4 Direction Register PD4 00h 00EBh 00ECh Port P6 Register P6 XXh 00EDh 00EEh Port P6 Direction Register PD6 00h 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h UART1 Function Select Register U1SR XXh 00F6h 00F7h 00F8h Port Mode Register PMR 00h 00F9h External Input Enable Register INTEN 00h 00FAh INT Input Filter Select Register INTF 00h 00FBh Key Input Enable Register KIEN 00h 00FCh Pull-Up Control Register 0 PUR0 00h 00FDh Pull-Up Control Register 1 PUR1 XX00XX00b 00FEh 00FFh

R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) Rev.2.00 Aug 27, 2008 Page 19 of 458 REJ09B0250-0200 Table 4.5 SFR Information (5) (1) X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Address Register Symbol After reset 0100h Timer RA Control Register TRACR 00h 0101h Timer RA I/O Control Register TRAIOC 00h 0102h Timer RA Mode Register TRAMR 00h 0103h Timer RA Prescaler Register TRAPRE FFh 0104h Timer RA Register TRA FFh 0105h 0106h LIN Control Register LINCR 00h 0107h LIN Status Register LINST 00h 0108h Timer RB Control Register TRBCR 00h 0109h Timer RB One-Shot Control Register TRBOCR 00h 010Ah Timer RB I/O Control Register TRBIOC 00h 010Bh Timer RB Mode Register TRBMR 00h 010Ch Timer RB Prescaler Register TRBPRE FFh 010Dh Timer RB Secondary Register TRBSC FFh 010Eh Timer RB Primary TRBPR FFh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h Timer RE Counter Data Register TRESEC 00h 0119h Timer RE Compare Data Register TREMIN 00h 011Ah 011Bh 011Ch Timer RE Control Register 1 TRECR1 00h 011Dh Timer RE Control Register 2 TRECR2 00h 011Eh Timer RE Count Source Select Register TRECSR 00001000b 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h Timer RD Start Register TRDSTR 11111100b 0138h Timer RD Mode Register TRDMR 00001110b 0139h Timer RD PWM Mode Register TRDPMR 10001000b 013Ah Timer RD Function Control Register TRDFCR 10000000b 013Bh Timer RD Output Master Enable Register 1 TRDOER1 FFh 013Ch Timer RD Output Master Enable Register 2 TRDOER2 0 1111111b 013Dh Timer RD Output Control Register TRDOCR 00h 013Eh Timer RD Digital Filter Function Select Register 0 TRDDF0 00h 013Fh Timer RD Digital Filter Function Select Register 1 TRDDF1 00h

R8C/20 Group, R8C/21 Group 4. Special Function Registers (SFRs) Rev.2.00 Aug 27, 2008 Page 20 of 458 REJ09B0250-0200 Table 4.6 SFR Information (6) (1) X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a program. Use a flash programmer to write to it. Address Register Symbol After reset 0140h Timer RD Control Register 0 TRDCR0 00h 0141h Timer RD I/O Control Register A0 TRDIORA0 10001000b 0142h Timer RD I/O Control Register C0 TRDIORC0 10001000b 0143h Timer RD Status Register 0 TRDSR0 11100000b 0144h Timer RD Interrupt Enable Register 0 TRDIER0 11100000b 0145h Timer RD PWM Mode Output Level Control Register 0 TRDPOCR0 11111000b 0146h Timer RD Counter 0 TRD0 00h 0147h 00h 0148h Timer RD General Register A0 TRDGRA0 FFh 0149h FFh 014Ah Timer RD General Register B0 TRDGRB0 FFh 014Bh FFh 014Ch Timer RD General Register C0 TRDGRC0 FFh 014Dh FFh 014Eh Timer RD General Register D0 TRDGRD0 FFh 014Fh FFh 0150h Timer RD Control Register 1 TRDCR1 00h 0151h Timer RD I/O Control Register A1 TRDIORA1 10001000b 0152h Timer RD I/O Control Register C1 TRDIORC1 10001000b 0153h Timer RD Status Register 1 TRDSR1 11000000b 0154h Timer RD Interrupt Enable Register 1 TRDIER1 11100000b 0155h Timer RD PWM Mode Output Level Control Register 1 TRDPOCR1 11111000b 0156h Timer RD Counter 1 TRD1 00h 0157h 00h 0158h Timer RD General Register A1 TRDGRA1 FFh 0159h FFh 015Ah Timer RD General Register B1 TRDGRB1 FFh 015Bh FFh 015Ch Timer RD General Register C1 TRDGRC1 FFh 015Dh FFh 015Eh Timer RD General Register D1 TRDGRD1 FFh 015Fh FFh 01B0h 01B1h 01B2h 01B3h Flash Memory Control Register 4 FMR4 01000000b 01B4h 01B5h Flash Memory Control Register 1 FMR1 1000000Xb 01B6h 01B7h Flash Memory Control Register 0 FMR0 00000001b 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh FFFFh Option Function Select Register OFS (Note 2)

R8C/20 Group, R8C/21 Group 5. Resets Rev.2.00 Aug 27, 2008 Page 21 of 458 REJ09B0250-0200 5. Resets There are resets: hardware reset, power -on reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources. NOTE: 1. Because this product is under develo pment, specifications may be changed. Figure 5.1 Block Diagram of Reset Circuit Table 5.1 Reset Names and Sources Reset Name Source Hardware reset Input voltage of RESET pin is held “L” Power-on reset(1) VCC rises Voltage monitor 1 reset(1) VCC falls (monitor voltage: Vdet1) Voltage monitor 2 reset(1) VCC falls (monitor voltage: Vdet2) Watchdog timer reset Underflow of watchdog timer Software reset Write 1 to PM03 bit in PM0 register RESET Voltage monitor 1 reset SFR VCA26, VW1C0 and VW1C6 bits SFR VCA13, VCA27, VW1C1, VW1F0, VW1F1, VW1C7, VW2C2 and VW2C3 bits Pin, CPU and SFR bits other than those listed above VCC Hardware reset Voltage monitor 2 reset Watchdog timer reset Software reset VCA13: Bit in VCA1 register VCA26, VCA27: Bits in VCA2 register VW1C0, VW1C1, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register VW2C2, VW2C3 bits: Bits in VW2C register Voltage detection circuit Watchdog timer CPU Power-on reset circuit Power-on reset

R8C/20 Group, R8C/21 Group 5. Resets Rev.2.00 Aug 27, 2008 Page 22 of 458 REJ09B0250-0200 Table 5.2 lists the Pin Functions after Reset, Figure 5.2 shows CPU Register Status after Reset, Figure 5.3 shows Reset Sequence, and Figure 5.4 shows the OFS Register. Figure 5.2 CPU Register Status after Reset Table 5.2 Pin Functions after Reset Pin Name Pin Functions P0, P1, P2 Input port P3_0, P3_1, P3_3 to P3_5, P3_7 Input port P4_2 to P4_7 Input port P6 Input port b19 b0 Interrupt table register (INTB) Program counter (PC) User stack pointer (USP) Interrupt stack pointer (ISP) Static base register (SB) Content of addresses 0FFFEh to 0FFFCh Flag register (FLG) CIPL DZSBOIU b15 b0 b15 b0 b15 b0b8 b7 b15 b0 0000h 0000h 0000h 0000h 0000h 0000h 0000h Data register (R0) Data register (R1) Data register (R2) Data register (R3) Address register (A0) Address register (A1) Frame base register (FB) 00000h 0000h 0000h 0000h 0000h

R8C/20 Group, R8C/21 Group 5. Resets Rev.2.00 Aug 27, 2008 Page 24 of 458 REJ09B0250-0200

5.1 Hardware Reset

A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power supply voltage meets the recommended perf ormance condition, the pins, CPU, and SFR are reset (refer to Table 5.2 Pin Functions after Reset ). When the input level applied to the RESET pin changes “L” to “H”, the program is executed beginning with the address indicated by the rese t vector. After reset, the low-speed on-chip oscillator clock divided-by-8 is automatically selected for the CPU clock. Refer to 4. Special Function Registers (SFRs) for the status of the SFR after reset. The internal RAM is not reset. If the RESET pin is pulled “L” during writing to the internal RAM, the internal RAM will be in indeterminate state. Figure 5.5 shows the Example of Hardware Reset Circu it and Operation and Figure 5.6 shows the Example of Hardware Reset Circuit (Usage Example of External Supply V oltage Detection Circuit) and Operation.

5.1.1 When Power Supply is Stable

(1) Apply “L” to the RESET pin. (2) Wait for 10 µs or more. (3) Apply “H” to the RESET pin.

5.1.2 Power On

(1) Apply “L” to the RESET pin. (2) Let the power supply voltage increase until it meets the recommended performance condition. (3) Wait for td(P-R) or more to allow the in ternal power supply to stabilize (refer to 20. Electrical Characteristics). (4) Wait for 10 µs or more. (5) Apply “H” to the RESET pin.

R8C/20 Group, R8C/21 Group 5. Resets Rev.2.00 Aug 27, 2008 Page 25 of 458 REJ09B0250-0200 Figure 5.5 Example of Hardware Reset Circuit and Operation Figure 5.6 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation RESET VCC VCC RESET 2.7 V 0 V

0.2 VCC or below

NOTE: 1. Refer to 20. Electrical Characteristics. td(P-R) + 10 µs or more RESET VCC VCC RESET 2.7 V 0 V 0 V 5 V 5 V Example when VCC = 5 V Power supply voltage detection circuit NOTE: 1. Refer to 20. Electrical Characteristics. td(P-R) + 10 µs or more

R8C/20 Group, R8C/21 Group 5. Resets Rev.2.00 Aug 27, 2008 Page 26 of 458 REJ09B0250-0200

5.2 Power-On Reset Function (1)

When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises, the power-on reset function is enabled and the MCU resets it s pins, CPU, and SFR. When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more. When the input voltage to the VCC pin reaches to the Vdet0 level or above, the low-speed on-chip oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H” and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divide-by-8 is automatically selected for the CPU after reset. Refer to 4. Special Function Registers (SFRs) for the status of the SFR after power-on reset. The voltage monitor 0 reset is enabled after power-on reset. Figure 5.7 shows the Example of Power-On Reset Circuit and Operation. NOTE: 1. When using power-on reset function, set the LVD1ON bit to 0 (voltage monitor 1 reset enabled after reset). Figure 5.7 Example of Power-On Reset Circuit and Operation × 321 fOCO-S Vdet1(3) Vpor1 tw(por1) Vdet1(3) Vpor2

2.0 Vtrth trth

NOTES: 1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or higher during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit for details. 4. Refer to 20. Electrical Characteristics. 5. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0 (voltage monitor 1 reset enabled after reset), bits VW1C0 and VW1C6 in the VW1C register to 1 (enable) and the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). Internal reset signal (“L” valid) Sampling time(1, 2) td(Vdet1-A) × 321 fOCO-S RESET VCC 4.7 kΩ (reference)

R8C/20 Group, R8C/21 Group 5. Resets Rev.2.00 Aug 27, 2008 Page 27 of 458 REJ09B0250-0200

5.3 Voltage Monitor 1 Reset

A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet1. When the input voltage to the VCC pin reaches to the Vdet1 level or below, the pins, CPU, and SFR are reset. And when the input voltage to the VCC pin reaches to th e Vdet1 level or above, count operation of the low-speed on-chip oscillator clock starts. When the operation counts the low-speed on-chip oscillator clock for 32 times, the internal reset signal is held “H” and th e MCU enters the rese t sequence (refer to Figure 5.3). The low-speed on- chip oscillator clock divide-by-8 is automatically selected for the CPU after reset. The LVD1ON bit in the OFS register can select to enable or disable voltage monitor 1 reset after a reset. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0, bits VW1C0 and VW1C6 in the VW1C register to 1, the VCA bit in the VCA2 register to 1. The LVD1ON bit cannot be changed by a program. When setting the LVD1ON bit, write 0 (voltage monitor 1 reset enabled after reset) or 1 (voltage monitor 1 reset di sabled after reset) to the bit 6 of address 0FFFFh using a flash programmer. Refer to Figure 5.4 OFS Register for details of the OFS register. Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 1 reset. The internal RAM is not reset. When the input voltage to the VCC pin reaches to the Vdet1 level or below during writing to the internal RAM, the internal RAM is in indeterminate state. Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.

5.4 Voltage Monitor 2 Reset

A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet2. When the input voltage to the VCC pin drops to the Vdet2 level or below, the pins, CPU, and SFR are reset and the program is executed beginning with the address indicate d by the reset vector. After reset, the low-speed on-chip oscillator clock divide-by-8 is automatically selected for the CPU clock. The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. When the input voltage to the VCC pin reaches to the Vdet2 level or below during writing to the internal RAM, the internal RAM is in indeterminate state. Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.

5.5 Watchdog Timer Reset

When the PM12 bit in the PM 1 register is set to 1 (reset when watc hdog timer underflows), the MCU resets its pins, CPU, and SFR if the watchdog timer underflows. Th en the program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillat or clock divide-by-8 is automatically selected for the CPU clock. The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. When the watchdog timer underflows, the internal RAM is in indeterminate state. Refer to 13. Watchdog Timer for watchdog timer.

5.6 Software Reset

When the PM03 bit in the PM0 register is set to 1 (M CU reset), the MCU resets its pins, CPU, and SFR. The program is executed beginning with the address indicate d by the reset vector. After reset, the low-speed on-chip oscillator clock divide-by-8 is automatically selected for the CPU clock. The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset.

R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Rev.2.00 Aug 27, 2008 Page 28 of 458 REJ09B0250-0200 6. Voltage Detection Circuit The voltage detection circuit is a circuit to monitor the i nput voltage to the VCC pin. This circuit monitors the VCC input voltage by the program. And the voltage monitor 1 reset, voltage monitor 2 interrupt and voltage monitor 2 reset can be used. Table 6.1 lists the Specificati ons of V oltage Detection Circuit and Figures 6.1 to 6.3 show the Block Diagrams. Figures 6.4 to 6.6 show the Associated Registers. Table 6.1 Specifications of Voltage Detection Circuit Item Voltage Detection 1 Voltage Detection 2 VCC Monitor Voltage to monitor Vdet1 Vdet2 Detection target Whether passing through Vdet1 by rising or falling Whether passing through Vdet2 by rising or falling Monitor None VCA13 bit in VCA1 register Whether VCC is higher or lower than Vdet2 Process When Voltage Is Detected Reset Voltage monitor 1 reset Voltage monitor 2 reset Reset at Vdet1 > VCC; Restart CPU operation at VCC > Vdet1 Reset at Vdet2 > VCC Restart CPU operation after a specified time Interrupt None Voltage monitor 2 interrupt Interrupt request at Vdet2 > VCC and VCC > Vdet2 when digital filter is enabled; Interrupt request at Vdet2 > VCC or VCC > Vdet2 when digital filter is disabled Digital Filter Switch enabled/disabled Available Available Sampling time (Divide-by-n of fOCO-S) x 4 n: 1, 2, 4 and 8 (Divide-by-n of fOCO-S) x 4 n: 1, 2, 4 and 8

R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Rev.2.00 Aug 27, 2008 Page 30 of 458 REJ09B0250-0200 Figure 6.3 Block Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit 1/2 1/2 1/2 Voltage detection 2 circuit VCA27 VCC Internal reference voltage VCA13 Noise filter (Filter width: 200ns) Voltage detection 2 signal is held “H” when VCA27 bit is set to 0 (disabled) Voltage detection 2 signal fOCO-S VW2F1 to VW2F0 = 00b = 01b = 10b = 11b VW2C1 VW2C2 bit is set to 0 (not detected) by writing 0 by program. When VCA27 bit is set to 0 (voltage detection 2 circuit disabled), VW2C2 bit is set to 0 VW2C7VW2C3 Watchdog timer block Watchdog timer underflow signal This bit is set to 0 (not detected) by writing “0” by program. Voltage monitor 2 interrupt/reset generation circuit VW2C0 to VW2C3, VW2F2, VW2F1, VW2C6, VW2C7: Bits in VW2C register VCA13: Bit in VCA1 register VCA27: Bit in VCA2 register VW2C2 VW2C0 VW2C6 Voltage monitor 2 reset signal Non-maskable interrupt signal Voltage monitor 2 interrupt signal Watchdog timer interrupt signal Oscillation stop detection interrupt signal VW2C1 Digital filter

R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Rev.2.00 Aug 27, 2008 Page 31 of 458 REJ09B0250-0200 Figure 6.4 Registers VCA1 and VCA2 Voltage Detection Register 1 Symbol Address After Reset (2) VC A1 0031h 00001000b Bit Symbol Bit Name Function RW NOTES: The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). The VCA13 bit is set to 1 (VCC ≥ Vdet 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2 circuit disabled). (b7-b4) Reserved bits Set to 0 RW Set to 0 b7 b6 b5 b4 b3 b2 b1 b0 0000 The softw are reset, w atchdog timer reset and voltage monitor 2 reset do not affect the VCA1 register. VC A13 Voltage detection 2 signal monitor flag(1) (b2-b0) RW 0 : VC C < Vdet2 1 : VCC ≥ Vdet2 or voltage detection 2 circuit disabled RO Reserved bits Voltage Detection Register 2(1) Symbol Address VCA2 0032h Bit Symbol Bit Name Function RW NOTES: 5. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figur e 10.10 Procedure for Enabling Reduced Internal Pow er Consumption Using VCA20 bit . VC A20 Internal pow er low consumption enable bit (5) 0 : Disables low consumption 1 : Enables low consumption RW When using the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is from 0 to 1, the voltage detection circuit elapses for td(E-A) before starting operation. The VCA27 bit remains unchanged after softw are reset, w atchdog timer reset, and voltage monitor 2 reset. Voltage detection 1 enable bit (2) 0 : Voltage detection 1 circuit disabled 1 : Voltage detection 1 circuit enabled RW The LVD1ON bit in the OFS register is set to 1: 00h Power-on reset, v oltage monitor 1 reset or the LVD1ON bit in the OFS register is set to 0: 01000000b After R eset(4) Set the PRC3 bit in the PRCR register to 1 (enables w riting) before w riting to the VCA2 register. When using the voltage monitor 1 reset, set the VCA26 bit to 1. After the VCA26 bit is set from 0 to 1, the voltage detection circuit elapses for td(E-A) before starting operation. 000 (b5-b1) Res erv ed bits VC A27 Voltage detection 2 enable bit(3) 0 : Voltage detection 2 circuit disabled 1 : Voltage detection 2 circuit enabled RW Set to 0 RW VC A26 b7 b6 b5 b4 b3 b2 b1

R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Rev.2.00 Aug 27, 2008 Page 32 of 458 REJ09B0250-0200 Figure 6.5 VW1C Register Voltage Monitor 1 Circuit Control Register (1) Symbol Address VW1C 0036h Bit Symbol Bit Name Function RW NOTES: The LVD1ON bit in the OFS register is set to 1: 0000X000b Power-on reset, v oltage monitor 1 reset or the LVD1ON bit in the OFS register is set to 0: 0100X001b After R eset(2) b3 b2 VW1C 0 RWVoltage monitor 1 reset enable bit(3) 0 : Disable 1 : Enable b1 b0b7 b6 b5 b4 0 : Digital filter enabled mode (digital filter circuit enabled) 1 : Digital filter disabled mode (digital filter circuit disabled) RW VW1C2 Reserved bit VW1C 1 Voltage monitor 1 digital filter disable mode select bit Set to 0 RW (b3) Reserved bit VW1F1 RW Sampling clock select bits b5 b4 0 0 : fOCO-S divide-by-1 0 1 : fOCO-S divide-by-2 1 0 : fOCO-S divide-by-4 1 1 : fOCO-S divide-by-8 VW1F0 RW When read, the content is undefined. RO VW1C 6 Voltage monitor 1 circuit mode select bit When the VW1C0 bit is set to 1 (enables voltage monitor 1 reset), set to 1. RW VW1C 7 Voltage monitor 1 reset generation condition select bit(4) When the VW1C1 bit is set to 1 (digital filter disabled mode), set to 1. RW The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode). Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW1C register. The value other than the VW1CO and VW1C6 bits remains unchanged after softw are reset, w atchdog timer reset, and voltage monitor 2 reset. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled). Set the VW1C0 bit to 0 (disable), w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).

R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Rev.2.00 Aug 27, 2008 Page 33 of 458 REJ09B0250-0200 Figure 6.6 VW2C Register Voltage Monitor 2 Circuit Control Register (1) Symbol Address After Reset (8) VW2C 0037h 00h Bit Symbol Bit Name Function RW NOTES: b3 b2 0 : Not detected 1 : Vdet2 pass detected RW b1 b0b7 b6 b5 b4 VW2C 0 RWVoltage monitor 2 interrupt/reset enable bit(6) 0 : Disable 1 : Enable 0 : Digital filter enabled mode (digital filter circuit enabled) 1 : Digital filter disabled mode (digital filter circuit disabled) RW VW2C 2 Voltage change detection flag (3,4,8) VW2C 1 Voltage monitor 2 digital filter disabled mode select bit(2) VW2C 3 WDT detection flag(4,8) VW2F1 RW Sampling clock select bits b5 b4 0 0 : fOCO-S divide-by-1 0 1 : fOCO-S divide-by-2 1 0 : fOCO-S divide-by-4 1 1 : fOCO-S divide-by-8 VW2F0 RW 0 : Not detected 1 : Detected RW VW2C 6 Voltage monitor 2 circuit mode select bit (5) 0 : Voltage monitor 2 interrupt mode 1 : Voltage monitor 2 reset mode RW VW2C 7 Voltage monitor 2 interrupt/reset generation condition select bit (7,9) 0 : When VCC reaches Vdet2 or above 1 : When VCC reaches Vdet2 or below RW When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches to Vdet2 or below ) (do not set to 0). Set the PRC3 bit in the PRCR register to 1 (enables w riting) before w riting to the VW2C register. When w riting the VW2C register, the VW2C2 bit may be set to 1. Set the VW2C2 bit to 0 after w riting the VW2C register. When the voltage monitor 2 interrupt is used to exit stop mode and to return again, w rite 0 to the VW2C1 bit before w riting 1. This bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). Set this bit to 0 by a program. When w riting 0 by a program, it is set to 0 (it remains unchanged even if it is set to 1). This bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/enables reset). The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled). The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 (digital filter disabled mode). The VW2C2 and VW2C3 bits remain unchanged in the softw are reset, w atchdog timer reset and voltage monitor 2 reset.

R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Rev.2.00 Aug 27, 2008 Page 34 of 458 REJ09B0250-0200

6.1 VCC Input Voltage

6.1.1 Monitoring Vdet1

Vdet1 cannot be monitored.

6.1.2 Monitoring Vdet2

Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed (refer to 20. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA1 register.

R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Rev.2.00 Aug 27, 2008 Page 35 of 458 REJ09B0250-0200

6.2 Voltage Monitor 1 Reset

Table 6.2 lists the Procedure for Sett ing Bits Associated with V oltage Monitor 1 Reset and Figure 6.7 shows an Example of V oltage Monitor 1 Reset Operation. To use the voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter disabled). NOTE: 1. When the VW1C0 bit is set to 0, procedures 3, 4 and 5 can be executed simultaneously (with 1 instruction). Figure 6.7 Example of Voltage Monitor 1 Reset Operation Table 6.2 Procedure for Setting Bits Associated with Voltage Monitor 1 Reset Step When Using Digital Filter When Not Using Digital Filter

1 Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled)

2 Wait for td(E-A)

Select the sampling clock of the digital filter by the VW1F0 to VW1F1 bits in the VW1C register Set the VW1C7 bit in the VW1C register to (1) Set the VW1C1 bit in the VW1C register to “0” (digital filter enabled) Set the VW1C1 bit in the VW1C register to 1 (digital filter disabled) 5(1) Set the VW1C6 bit in the VW1C register to 1 (voltage monitor 1 reset mode)

6 Set the VW1C2 bit in the VW1C register to 0

7 Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on)

8 Wait for the sampling clock of the digital

− (no wait time)

9 Set the VW1C0 bit in the VW1C register to 1 (enables voltage monitor 1 reset)

The above applies to the following conditions.

• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (enables voltage monitor 1 reset )
• VW1C6 bit in VW1C register = 1 (voltage monitor 1 reset mode) When the internal reset signal is held “L”, the pins, CPU and SFR are reset. The internal reset signal is changed from “L” to “H”, the program is executed beginning with the address indicated by the reset vector. Refer to 4. Special Function Registers (SFRs) for the SFR status after reset. fOCO-S x 32Sampling clock of digital filter x 4 cycles When the VW1C1 bit is set to 0 (digital filter enabled) Internal reset signal When the VW1C1 bit is set to 1 (digital filter disabled) and the VW1C7 bit is set to 1 fOCO-S x 32 VW1C1 and VW1C7: Bits in VW1C register

R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Rev.2.00 Aug 27, 2008 Page 36 of 458 REJ09B0250-0200

6.3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset

Table 6.3 lists the Procedure for Setti ng Bits Associated with V oltage Monitor 2 Interrupt and Reset. Figure 6.8 shows an Example of V oltage Monitor 2 Interrupt and V oltage Monitor 2 Reset Operation. To use the voltage monitor 2 interrupt or voltage monitor 2 reset to exit st op mode, set the VW2C1 bit in the VW2C register to 1 (digital filter disabled). NOTES: 1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset. 2. When the VW2C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction). Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset Step When Using Digital Filter When Not Using Digital Filter Voltage Monitor 2 Interrupt Voltage Monitor 2 Reset Voltage Monitor 2 Interrupt Voltage Monitor 2 Reset

1 Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled)

Select the sampling clock of the digital filter by the VW2F0 to VW2F1 bits in the VW2C register Select the timing of the interrupt and reset request by the VW2C7 bit in the VW2C register (1) 4(2) Set the VW2C1 bit in the VW2C register to 0 (digital filter enabled) Set the VW2C1 bit in the VW2C register to 1 (digital filter disabled) 5(2) Set the VW2C6 bit in the VW2C register to 0 (voltage monitor 2 interrupt mode) Set the VW2C6 bit in the VW2C register to 1 (voltage monitor 2 reset mode) Set the VW2C6 bit in the VW2C register to 0 (voltage monitor 2 interrupt mode) Set the VW2C6 bit in the VW2C register to 1 (voltage monitor 2 reset mode)

6 Set the VW2C2 bit in the VW2C register to 0 (passing of Vdet2 is not detected)

(low-speed on-chip oscillator on)

8 Wait for the sampling clock of the digital filter

− (no wait time)

9 Set the VW2C0 bit in the VW2C register to 1 (enables voltage monitor 2 interrupt/reset)

R8C/20 Group, R8C/21 Group 6. Voltage Detection Circuit Rev.2.00 Aug 27, 2008 Page 37 of 458 REJ09B0250-0200 Figure 6.8 Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation Vdet2 VCA13 bit Internal reset signal (VW2C6 = 1) VCC The above applies to the following conditions.

• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (enables voltage monitor 2 interrupt and voltage monitor 2 reset) NOTE: 1. When the voltage monitor 1 reset is not used, set the power supply to VCC ≥ 2.7.

2.7 V(1)

Sampling clock of digital filter x 4 cycles VW2C2 bit When the VW2C1 bit is set to 0 (digital filter enabled) VW2C2 bit When the VW2C1 bit is set to 1 (digital filter disabled) and the VW2C7 bit is set to 0 (Vdet2 or above) VCA13 : Bit in VCA1 register VW2C1, VW2C2, VW2C6, VW2C 7 : Bit in VW2C register Set to 0 by interrupt request acknowledgement Set to 0 by a program Voltage monitor 2 interrupt request (VW2C6 = 0) Voltage monitor 2 interrupt request (VW2C6 = 0) VW2C2 bit When the VW2C1 bit is set to 1 (digital filter disabled) and the VW2C7 bit is set to 1 (Vdet2 or below) Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) Sampling clock of digital filter x 4 cycles Set to 0 by a program Set to 0 by interrupt request acknowledgement Set to 0 by a program Set to 0 by interrupt request acknowledgement

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 38 of 458 REJ09B0250-0200 7. Programmable I/O Ports There are 41 programmable Input/Output ports (I/O ports) P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, and P6. Also, P4_6 and P4_7 can be used as input-only ports if the XIN clock oscillation circuit is not used, and the P4_2 can be used as an input-only port if the A/D converter is not used. NOTES: 1. In input mode, whether the internal pull-up resistor is connected or not can be selected by the PUR0 and PUR1 registers. 2. When the A/D converter is no t used, these ports can be used as the input port only. 3. When the XIN clock oscillation circuit is not used, these ports can be used as the input port only.

7.1 Functions of Progr ammable I/O Ports

The PDi_j (i = 0 to 4, 6, j = 0 to 7) bit in the PDi regi ster controls I/O of the ports P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, and P6. The Pi register consists of a port latch to hold output data and a circuit to read pin state. Figures 7.1 to 7.7 show the Configurations of Progr ammable I/O Ports. Table 7.2 lists the Functions of Programmable I/O Ports. Also, Figure 7.9 shows the PDi (i = 0 to 4 and 6) Registers. Figure 7.10 shows the Pi (i = 0 to 4 and 6) Registers, Figure 7.11 shows the Registers PUR0 and PUR1 and Figure 7.12 shows the PMR Register. i = 0 to 4, 6, j = 0 to 7 NOTE: 1. Nothing is assigned to bits PD3_2, PD 3_6, PD4_0 to PD4_2, PD4_6, and PD4_7. Table 7.1 Overview of Programmable I/O Ports Ports I/O Type of Output I/O Setting Internal Pull-Up Resister P0 to P2, P6 I/O CMOS3 state Set every bit Set every 4 bits (1) P3_0, P3_1, P3_3 to P3_5, P3_7 I/O CMOS3 state Set every bit Set every 3 bits(1) P4_3 I/O CMOS3 state Set every bit Set every bit(1) P4_4, P4_5 I/O CMOS3 state Set every bit Set every 2 bits(1) P4_2(2) P4_6, P4_7(3) I (No output function) None None Table 7.2 Functions of Programmable I/O Ports Operation When Accessing Pi Register Value of PDi_j Bit in PDi Register(1) When PDi_j bit is set to 0 (input mode) W hen PDi_j bit is set to 1 (output mode) Reading Read pin input level Read the port latch Writing Write to the port latch Write to the port latch. The value written in the port latch, it is output from the pin.

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 39 of 458 REJ09B0250-0200

7.2 Effect on Peripheral Functions

Programmable I/O ports function as I/O of peripheral functions (refer to Table 1.6 Pin Name Information by Pin Number). Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 4, 6 j = 0 to 7). Refer to descriptions of each function for how to set peripheral functions.

7.3 Pins Other than Programmable I/O Ports

Figure 7.8 shows the Configuration of I/O Pins. Table 7.3 Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 4, 6 j = 0 to 7) I/O of Peripheral Functions PDi_j Bit Setting of Port shared with Pin Input Set this bit to 0 (input mode). Output This bit can be set to both 0 or 1 (output regardless of the port setting)

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 40 of 458 REJ09B0250-0200 Figure 7.1 Configuration of Programmable I/O Ports (1) P1_0 to P1_3 Output from each peripheral function Analog input Port latchData bus Pull-up selection Input to each peripheral function P1_4 Port latchData bus Pull-up selection Output from each peripheral function Port latch Direction register Data bus Pull-up selection Analog input Direction register Direction register (1) NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC. (1) (1) (1) (1) (1)

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 41 of 458 REJ09B0250-0200 Figure 7.2 Configuration of Programmable I/O Ports (2) Output from each peripheral function INT1 input Digital filter Input to each peripheral function P1_5 and P1_7 Port latchData bus Pull-up selection Direction register P1_6 and P2 Port latchData bus Pull-up selection Input to each peripheral function Output from each peripheral function Direction register (1) NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC. (1) (1) (1)

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 42 of 458 REJ09B0250-0200 Figure 7.3 Configuration of Programmable I/O Ports (3) P3_3 to P3_5 and P3_7 Port latchData bus Pull-up selection Input to each peripheral function Output from each peripheral function Direction register P3_0 and P3_1 Port latchData bus Pull-up selection Output from each peripheral function Direction register (1) NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC. (1) (1) (1)

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 43 of 458 REJ09B0250-0200 Figure 7.4 Configuration of Programmable I/O Ports (4) P4_3 and P4_4 Port latchData bus Pull-up selection P4_2/VREF Data bus Direction register (1) NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC. (1) (1) (1)

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 44 of 458 REJ09B0250-0200 Figure 7.5 Configuration of Programmable I/O Ports (5) P4_5 INT0 and input to each peripheral function Port latchData bus Pull-up selection Digital filter P4_6/XIN Data bus Clocked inverter(2) P4_7/XOUT Data bus (3) NOTES: 1. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC. 2. When CM05 = 1, CM10 = 1, or CM13 = 0, the clocked inverter is cutoff. 3. When CM10 = 1 or CM13 = 0, the feedback resistor is unconnected. 4. When CM05 = CM13 = 1 or CM10 = CM13 = 1, this pin is pulled up. (4) Direction register (1) (1) (1) (1) (1) (1)

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 45 of 458 REJ09B0250-0200 Figure 7.6 Configuration of Programmable I/O Ports (6) P6_1 to P6_5 Port latchData bus Pull-up selection P6_0 Port latch Direction register Data bus Pull-up selection Output from each peripheral function Direction register (1) NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC. (1) (1) (1)

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 46 of 458 REJ09B0250-0200 Figure 7.7 Configuration of Programmable I/O Ports (7) P6_7 P6_6 INT2 input Port latchData bus Pull-up selection Digital filter Output from each peripheral function Direction register INT3 input Port latchData bus Pull-up selection Digital filter Direction register Input to each peripheral function (1) NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC. (1) (1) (1)

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 47 of 458 REJ09B0250-0200 Figure 7.8 Configuration of I/O Pins MODE MODE signal input RESET RESET signal input (1) NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage on each port will not exceed VCC. (1)

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 50 of 458 REJ09B0250-0200

7.4 Port Settings

Table 7.4 to Table 7.47 list the port settings. X: 0 or 1 NOTE: 1. Pulled up by setting the PU00 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU00 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU00 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU00 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. Table 7.4 Port P0_0/AN7 Register PD0 ADCON0 FunctionBit PD0_0 CH2 CH1 CH0 ADGSEL0 Setting value 0XXXX Input port(1)

1 X X X X Output port

0 1 1 1 0 A/D converter input (AN7) Table 7.5 Port P0_1/AN6 Register PD0 ADCON0 FunctionBit PD0_1 CH2 CH1 CH0 ADGSEL0 Setting value 0XXXX Input port(1) 0 1 1 0 0 A/D converter input (AN6) Table 7.6 Port P0_2/AN5 Register PD0 ADCON0 FunctionBit PD0_2 CH2 CH1 CH0 ADGSEL0 Setting value 0XXXX Input port(1) 0 1 0 1 0 A/D converter input (AN5) Table 7.7 Port P0_3/AN4 Register PD0 ADCON0 FunctionBit PD0_3 CH2 CH1 CH0 ADGSEL0 Setting value 0XXXX Input port(1) 0 1 0 0 0 A/D converter input (AN4) Table 7.8 Port P0_4/AN3 Register PD0 ADCON0 FunctionBit PD0_4 CH2 CH1 CH0 ADGSEL0 Setting value 0XXXX Input port(1) 0 0 1 1 0 A/D converter input (AN3)

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 51 of 458 REJ09B0250-0200 X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. Table 7.9 Port P0_5/AN2 Register PD0 ADCON0 FunctionBit PD0_5 CH2 CH1 CH0 ADGSEL0 Setting value 0XXXX Input port(1) 0 0 1 0 0 A/D converter input (AN2) Table 7.10 Port P0_6/AN1 Register PD0 ADCON0 FunctionBit PD0_6 CH2 CH1 CH0 ADGSEL0 Setting value 0XXXX Input port(1) 0 0 0 1 0 A/D converter input (AN1) Table 7.11 Port P0_7/AN0 Register PD0 ADCON0 FunctionBit PD0_7 CH2 CH1 CH0 ADGSEL0 Setting value 0XXXX Input port(1) 0 0 0 0 0 A/D converter input (AN0) Table 7.12 Port P1_0/KI0 /AN8 Register PD1 KIEN ADCON0 FunctionBit PD1_0 KI0EN CH2 CH1 CH0 ADGSEL0 Setting value 0XXXXX Input port(1)

1 X X X X X Output port

0 X 1 0 0 1 A/D converter input (AN8)

Table 7.13 Port P1_1/KI1 /AN9 Register PD1 KIEN ADCON0 FunctionBit PD1_1 KI1EN CH2 CH1 CH0 ADGSEL0 Setting value 0XXXXX Input port(1)

0 X 1 0 1 1 A/D converter input (AN9)

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 52 of 458 REJ09B0250-0200 X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1. X: 0 or 1 NOTES: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. 2. N-channel open drain output by setting the NCH bit in the U0C0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. Table 7.14 Port P1_2/KI2 /AN10 Register PD1 KIEN ADCON0 FunctionBit PD1_2 KI2EN CH2 CH1 CH0 ADGSEL0 Setting value 0XXXXX Input port(1)

0 X 1 1 0 1 A/D converter input (AN10)

Table 7.15 Port P1_3/KI3 /AN11 Register PD1 KIEN ADCON0 FunctionBit PD1_3 KI3EN CH2 CH1 CH0 ADGSEL0 Setting value 0XXXXX Input port(1)

0 X 1 1 1 1 A/D converter input (AN11)

Table 7.16 Port P1_4/TXD0 Register PD1 U0MR FunctionBit PD1_4 SMD2 SMD1 SMD0 Setting value

0000 Input port(1)

X 001 TXD0 output(2)100 101 110 Table 7.17 Port P1_5/RXD0/(TRAIO)/(INT1 ) Register PD1 TRAIOC TRAMR INTEN FunctionBit PD1_5 TIOSEL TOPCR TMOD2 TMOD1 TMOD0 INT1EN Setting value 0XXXX X Input port(1)X1XXX X X Other than 001b 0XXXX X Output portX1XXX X X Other than 001b

0 X X Other than 001b X RXD0 input0X001

0 1 X Other than 001b X TRAIO input 0 1 X Other than 001b 1 TRAIO/INT1 input X 1 0 0 0 1 X TRAIO pulse output

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 53 of 458 REJ09B0250-0200 X: 0 or 1 NOTE: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU04 bit in the PUR0 register to 1. Table 7.18 Port P1_6/CLK0 Register PD1 U0MR FunctionBit PD1_6 SMD2 SMD1 SMD0 CKDIR Setting value

0 Other than 001b X

Input port(1) XXX1

1 Other than 001b X Output port

0 X X X 1 CLK0 (external clock) input

X 0 0 1 0 CLK0 (internal clock) output Table 7.19 Port P1_7/TRAIO/INT1 Register PD1 TRAIOC TRAMR INTEN FunctionBit PD1_7 TIOSEL TOPCR TMOD2 TMOD1 TMOD0 INT1EN Setting value 0XXXX X Input port(1)X1XXX X X Other than 001b 1XXXX X Output portX1XXX X X Other than 001b 0 0 X Other than 001b X TRAIO input 0 0 X Other than 001b 1 TRAIO/INT1 input X 0 0 0 0 1 X TRAIO pulse output Table 7.20 Port P2_0/TRDIOA0/TRDCLK Register PD2 TRDOER1 TRDFCR TRDIORA0 Function Bit PD2_0 EA0 CMD1 CMD0 STCLK PWM3 IOA2 IOA1 IOA0 Setting value 0 1 X XXX X X X Input port(1) 1 1 X X X X X X X Output port

0 X 0 0 0 1 1 X X Timer mode (input capture function)

0 X XX 1 1000 E x t e r n a l c l o c k i n p u t ( T RDCLK)

X 0 0 0 0 0 X X X PWM3 mode waveform output X00 0 0 1 001 Timer mode waveform output (output compare function)01X

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 54 of 458 REJ09B0250-0200 X: 0 or 1 NOTE: 1. Pulled up by setting the PU04 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU04 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU04 bit in the PUR0 register to 1. Table 7.21 Port P2_1/TRDIOB0 Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORA0 FunctionBit PD2_1 EB0 CMD1 CMD0 PWM3 PWMB0 IOB2 IOB1 IOB0 Setting value

01 X X X X X X X Input port(1)

1 1 X X X X X X X Output port

0 X 0 0 1 0 1 X X Timer mode (input capture function)

X0 10 X X X X X Complementary PWM mode waveform output11 X00 1 X X X X X Reset synchronous PWM mode waveform output X 0 0 0 0 X X X X PWM3 mode waveform output X 0 0 0 1 1 X X X PWM mode waveform output X00 0 1 0 001 Timer mode waveform output (output compare function)01X Table 7.22 Port P2_2/TRDIOC0 Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC0 FunctionBit PD2_2 EC0 CMD1 CMD0 PWM3 PWMC0 IOC2 IOC1 IOC0 Setting value 0 1 XXX X X X X Input port(1) 1 1 XXX X X X X O u t p u t p o r t X0 10 XX X X X Complementary PWM mode waveform output11 X00 1 X X X X X Reset synchronous PWM mode waveform output X 0 0 0 1 1 X X X PWM mode waveform output X 0 001 0 001 Timer mode waveform output (output compare function)01X Table 7.23 Port P2_3/TRDIOD0 Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC0 FunctionBit PD2_3 ED0 CMD1 CMD0 PWM3 PWMD0 IOD2 IOD1 IOD0 Setting value 0 1 XXX X X X X Input port(1) 1 1 XXX X X X X O u t p u t p o r t X0 10 XX X X X Complementary PWM mode waveform output11 X00 1 X X X X X Reset synchronous PWM mode waveform output X 0 0 0 1 1 X X X PWM mode waveform output X 0 001 0 001 Timer mode waveform output (output compare function)01X

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 55 of 458 REJ09B0250-0200 X: 0 or 1 NOTE: 1. Pulled up by setting the PU05 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU05 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU05 bit in the PUR0 register to 1. Table 7.24 Port P2_4/TRDIOA1 Register PD2 TRDOER1 TRDFCR TRDIORA1 FunctionBit PD2_4 EA1 CMD1 CMD0 PWM3 IOA2 IOA1 IOA0 Setting value 0 1 XXX X X X Input port(1) 1 1 XXX X X X O u t p u t p o r t

0 X 0 0 1 1 X X Timer mode (input capture function)

X0 10 X X X X Complementary PWM mode waveform output11 X 0 0 1 X X X X Reset synchronous PWM mode waveform output X 0 001 001 Timer mode waveform output (output compare function)01X Table 7.25 Port P2_5/TRDIOB1 Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORA1 FunctionBit PD2_5 EB1 CMD1 CMD0 PWM3 PWMB1 IOB2 IOB1 IOB0 Setting value 0 1 XXX X X X X Input port(1) 1 1 X X X X X X X Output port X0 10 X X X X X Complementary PWM mode waveform output11 X00 1 X X X X X Reset synchronous PWM mode waveform output X 0 0 0 1 1 X X X PWM mode waveform output X 0 001 0 001 Timer mode waveform output (output compare function)01X Table 7.26 Port P2_6/TRDIOC1 Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC1 FunctionBit PD2_6 EC1 CMD1 CMD0 PWM3 PWMC1 IOC2 IOC1 IOC0 Setting value 0 1 XXX X X X X Input port(1) 1 1 X X X X X X X Output port X0 10 X X X X X Complementary PWM mode waveform output11 X00 1 X X X X X Reset synchronous PWM mode waveform output X 0 0 0 1 1 X X X PWM mode waveform output X 0 001 0 001 Timer mode waveform output (output compare function)01X

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 56 of 458 REJ09B0250-0200 X: 0 or 1 NOTE: 1. Pulled up by setting the PU05 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. X: 0 or 1 NOTES: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. 2. N-channel open drain output by setting the SOOS bit in t he SSMR2 register to 1 when this pin functions as output. Table 7.27 Port P2_7/TRDIOD1 Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC1 FunctionBit PD2_7 ED1 CMD1 CMD0 PWM3 PWMD1 IOD2 IOD1 IOD0 Setting value 0 1 XXX X X X X Input port(1) 1 1 X X X X X X X Output port X0 10 X X X X X Complementary PWM mode waveform output11 X00 1 X X X X X Reset synchronous PWM mode waveform output X 0 0 0 1 1 X X X PWM mode waveform output X 0 001 0 001 Timer mode waveform output (output compare function)01X Table 7.28 Port P3_0/TRAO Register PD3 TRAIOC FunctionBit PD3_0 TOENA Setting value

00 Input port(1)

Table 7.29 Port P3_1/TRBO Register PD3 TRBMR TRBIOC FunctionBit PD3_1 TMOD1 TMOD0 TOCNT Setting value 000X Input port(1) 100X Output portX 01b 1 X Other than 00b 0 TRBO output Table 7.30 Port P3_3/SSI Register PD3 Clock Synchronous Serial I/O with Chip Select (Refer to Table 16.4 Association between Communication Modes and I/O Pins.) PMR Function Bit PD3_3 SSI output control SSI input control IICSEL Setting value 00 00 Input port(1) 0X X1 10 00 Output port(2) 1X X1 X 0 1 0 SSI input X1 00 SSI output(2)

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 57 of 458 REJ09B0250-0200 X: 0 or 1 NOTES: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. 2. N-channel open drain output by setting the CSOS bit in t he SSMR2 register to 1 when this pin functions as output. X: 0 or 1 NOTES: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. 2. N-channel open drain output by setting the CSOS bit in t he SSMR2 register to 1 when this pin functions as output. X: 0 or 1 NOTE: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. Table 7.31 Port P3_4/SDA/SCS Register PD3 SSMR2 PMR ICCR1 FunctionBit PD3_4 CSS1 CSS0 IICSEL ICE Setting value 0000X Input port(1) 000X0 1000X Output port(2) 100X0 X010X SCS input X 10 0X SCS output(2) X X X 1 1 SDA input/output Table 7.32 Port P3_5/SCL/SSCK Register PD3 Clock Synchronous Serial I/O with Chip Select (Refer to Table 16.4 Association between Communication Modes and I/O Pins.) PMR ICCR1 Function Bit PD3_5 SSCK output control SSCK input control IICSEL ICE Setting value 00 00 X Input port(1) 00 0X 0 10 00 X Output port(2) 10 0X 0 X 0 1 0 0 SSCK input X1 00 0 SSCK output(2) X 1 0 1 1 SCL input/output Table 7.33 Port P3_7/SSO Register PD3 Clock Synchronous Serial I/O with Chip Select (Refer to Table 16.4 Association between Communication Modes and I/O Pins.) SSMR2 PMR Function Bit PD3_7 SSO output control SSO input control SOOS IICSEL Setting value 00 0 X 0 Input port(1) 0X X X 1 10 0 0 0 Output port1X X 0 1 X 0 1 0 0 SSO input X 1 0 0 0 SSO output (CMOS output) X1 0 1 0 SSO output (N-channel open-drain output) Table 7.34 Port P4_2/VREF Register ADCON1 FunctionBit VCUT Setting value

0 Input port

1 Input port/VREF input

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 58 of 458 REJ09B0250-0200 NOTE: 1. Pulled up by setting the PU10 bit in the PUR0 register to 1. NOTE: 1. Pulled up by setting the PU11 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU11 bit in the PUR0 register to 1. X: 0 or 1 X: 0 or 1 Table 7.35 Port P4_3 Register PD4 FunctionBit PD4_3 Setting value

0 Input port(1)

1 Output port

Table 7.36 Port P4_4 Register PD4 FunctionBit PD4_4 Setting value Table 7.37 Port P4_5/INT0 Register PD4 INTEN FunctionBit PD4_5 INT0EN Setting value 0X Input port(1)

1 X Output port

01 INT0 input

Table 7.38 Port P4_6/XIN Register CM1 CM0 Circuit specifications FunctionBit CM13 CM10 CM05 Oscillation buffer Feedback resistor Setting value

0 X X OFF OFF Input port

1 0 0 ON ON XIN-XOUT oscillation 1 0 1 OFF ON External XIN input 1 1 0 OFF OFF XIN-XOUT oscillation stop 1 1 1 OFF OFF XIN-XOUT oscillation stop Table 7.39 Port P4_7/XOUT Register CM1 CM0 Circuit specifications FunctionBit CM13 CM10 CM05 Oscillation buffer Feedback resistor Setting value 1 0 0 ON ON XIN-XOUT oscillation 1 0 1 OFF ON XOUT is “H” pull-up 1 1 0 OFF OFF XIN-XOUT oscillation stop 1 1 1 OFF OFF XIN-XOUT oscillation stop

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 59 of 458 REJ09B0250-0200 X: 0 or 1 NOTE: 1. Pulled up by setting the PU14 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU14 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU14 bit in the PUR0 register to 1. NOTE: 1. Pulled up by setting the PU14 bit in the PUR0 register to 1. NOTE: 1. Pulled up by setting the PU15 bit in the PUR0 register to 1. NOTE: 1. Pulled up by setting the PU15 bit in the PUR0 register to 1. Table 7.40 Port P6_0/TREO Register PD6 TRECR1 FunctionBit PD6_0 TOENA Setting value Table 7.41 Port P6_1 Register PD6 FunctionBit PD6_1 Setting value Table 7.42 Port P6_2 Register PD6 FunctionBit PD6_2 Setting value Table 7.43 Port P6_3 Register PD6 FunctionBit PD6_3 Setting value Table 7.44 Port P6_4 Register PD6 FunctionBit PD6_4 Setting value Table 7.45 Port P6_5 Register PD6 FunctionBit PD6_5 Setting value

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 60 of 458 REJ09B0250-0200 X: 0 or 1 NOTE: 1. Pulled up by setting the PU15 bit in the PUR0 register to 1. X: 0 or 1 NOTE: 1. Pulled up by setting the PU15 bit in the PUR0 register to 1. Table 7.46 Port P6_6/INT2 /TXD1 Register PD6 PMR U1MR U1C0 INTEN FunctionBit PD6_6 U1PINSEL SMD2 SMD1 SMD0 NCH INT2EN Setting value

0 X 000 XX Input port(1)

1 X 000 X X Output port0X X X

0 X TXD1 output (CMOS output)100

1 X TXD1 output (N-channel open-drain output)100

Table 7.47 Port P6_7/INT3 /RXD1 Register PD6 PMR INTEN FunctionBit PD6_7 U1PINSEL INT3EN Setting value 0XX Input port(1)

1 X X Output port

R8C/20 Group, R8C/21 Group 7. Programmable I/O Ports Rev.2.00 Aug 27, 2008 Page 61 of 458 REJ09B0250-0200

7.5 Unassigned Pin Handling

Table 7.48 lists Unassigned Pin Handling. NOTES: 1. If these ports are set to output mode and left open, they remain input mode until they are switched to output mode by a program. The voltage level of these pins may be undefined and the power current may increase while the ports remain input mode. The content of the direction registers may change due to noise or program runaway caused by noise. In order to enhance program reliability, the program should periodically repeat the setting of the direction registers. 2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) as possible. 3. When power-on reset function is in use. Figure 7.13 Unassigned Pin Handling Table 7.48 Unassigned Pin Handling Pin Name Connection Ports P0 to P2, P3_0, P3_1, P3_3 to P3_7, P4_3 to P4_5, P6

• After setting to input mode, connect every pin to VSS via a resistor (pull- down) or connect every pin to VCC via a resistor (pull-up).(2)
• After setting to output mode, leave these pins open.(1, 2) Ports P4_6, P4_7 Connect to VCC via a resistor (pull-up)(2) Port P4_2/VREF Connect to VCC RESET(3) Connect to VCC via a resistor (pull-up)(2) MCU Port P0 to P2, P3_0, P3_1, P3_3 to P3_7, P4_3 to P4_5, P6 (Input mode ) (Input mode) (Output mode) Port P4_6, P4_7 RESET(1) Port P4_2/VREF Open NOTE: 1. When power-on reset function is in use.

R8C/20 Group, R8C/21 Group 8. Processor Mode Rev.2.00 Aug 27, 2008 Page 62 of 458 REJ09B0250-0200 8. Processor Mode

8.1 Processor Modes

Single-chip mode can be selected as processor mode. Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1 Register. Figure 8.1 PM0 Register Figure 8.2 PM1 Register Table 8.1 Features of Processor Mode Processor Mode Accessible Areas Pin s Assignable as I/O Port Pins Single-chip mode SFR, internal RAM, intern al ROM All pins are I/O ports or peripheral function I/O pins Processor Mode Register 0(1) Symbol Address After Reset PM0 0004h 00h Bit Symbol Bit Name Function RW NOTE: RWReserved bits Set to 0 Set the PRC1 bit in the PRCR register to 1 (enables w riting) before rew riting to the PM0 register. The MCU is reset w hen this bit is set to 1. When read, its content is 0. RW (b7-b4) PM03 Softw are reset bit Nothing is assigned. If necessary, set to 0. When read, the content is 0. b7 b6 b5 b4 b3 b2 b1 b0 000 (b2-b0) Processor Mode Register 1(1) Symbol Address After Reset PM1 0005h 00h Bit Symbol Bit Name Function RW NOTES : (b1-b0) RWReserved bits Set to 0 b7 b6 b5 b4 b3 b2 b1 b0 0 : Watchdog timer interrupt 1 : Watchdog timer reset(2) RW (b6-b3) PM12 WDT interrupt/reset sw itch bit Nothing is assigned. If necessary, set to 0. When read, the content is 0. The PM12 bit is set to 1 by a program (it remains unchanged even if it is set to 0). When the CSPRO bit in the CSPR register is set to 1 (selects count source protect mode), the PM12 bit is automatically set to 1. Reserved bit Set to 0 Set the PRC1 bit in the PRCR register to 1 (enables w riting) before rew riting to the PM1 register. (b7) RW

R8C/20 Group, R8C/21 Group 9. Bus Rev.2.00 Aug 27, 2008 Page 63 of 458 REJ09B0250-0200 9. Bus The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 9.1 lists Bus Cycles by Access Space of the R8C/20 Group and Table 9.2 lists Bus Cycles by Access Space of the R8C/21 Group. The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word-(16 bits) unit, these area are accessed twice in 8-bit unit. Table 9.3 lists Access Unit and Bus Operations. Table 9.3 Access Unit and Bus Operations However, only following SFRs are connected with the 16-bit bus: Timer RD: registers TRDi (i = 0, 1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi Therefore, they are accessed once in 16-bit units. The bus operation is the same as “Area: SFR, data flash, even address byte access” in Table 9.3 Access Unit and Bus Operations, and 16-bit data is accessed at a time. Table 9.1 Bus Cycles by Access Space of the R8C/20 Group Access Area Bus Cycle SFR 2 cycles of CPU clock ROM/RAM 1 cycle of CPU clock Table 9.2 Bus Cycles by Access Space of the R8C/21 Group Access Area Bus Cycle SFR/Data flash 2 cycles of CPU clock Program ROM/RAM 1 cycle of CPU clock Area SFR, data flash Even address byte access ROM (program ROM), RAM Odd address byte access Even address word access Odd address word access CPU clock Data Data Data Data DataData Data Data Data Even Even Odd Odd Even + 1Even Odd + 1Odd Address Even + 1 Odd + 1Odd Data Data Even Data CPU clock Data Address CPU clock Data Address CPU clock Data Address Data CPU clock Address Data CPU clock Address Data CPU clock Address Data CPU clock Address Data

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 64 of 458 REJ09B0250-0200 10. Clock Generation Circuit The clock generation circuit has:

• XIN clock oscillation circuit
• Low-speed on-chip oscillator
• High-speed on-chip oscillator Table 10.1 lists Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation Circuit. Figures 10.2 to 10.7 show clock-associated registers. NOTES: 1. These pins can be used as P 4_6 and P4_7 when using the on-chip oscillator clock as the CPU clock while the XIN clock oscillation circuit is not used. 2. Set the CM05 bit in the CM0 register to 1 (main clock stops) and the CM13 bit in the CM1 register to 1 (XIN-XOUT pin) when the external clock is input. 3. The clock frequency is automatica lly set to up to 20 MHz by a driver when using the high-speed on- chip oscillator as the CPU clock source. Table 10.1 Specifications of Clock Generation Circuit Item XIN Clock Oscillation Circuit On-Chip Oscillator High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator Use of Clock • CPU clock source
• Peripheral function clock source
• CPU clock source
• Peripheral function clock source
• CPU and peripheral function clock sources when XIN clock stops oscillating
• CPU clock source
• Peripheral function clock source
• CPU and peripheral function clock sources when XIN clock stops oscillating Clock Frequency 0 to 20 MHz Approx. 40 MHz (3) Approx. 125 kHz Connectable Oscillator
• C e r a m i c resonator
• Crystal oscillator Oscillator Connect Pins XIN, XOUT(1) −(1) −(1) Oscillation Stop, Restart Function Usable Usable Usable Oscillator Status After Reset Stop Stop Oscillate Others Externally generated clock can be input(2)

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 65 of 458 REJ09B0250-0200 Figure 10.1 Clock Generation Circuit a b c d e g f32 h S Q R S Q R FRA00 FRA01 = 1 FRA01 = 0 CM14 Power-on reset CPU clock OCD2 = 0 OCD2 = 1 Divider Oscillation stop detection XIN clock XOUT CM13 CM05 XIN CM02 WAIT instruction CM10 = 1 (stop mode) a dc h b CM06 = 0 CM17 to CM16 = 11b CM06 = 1 CM06 = 0 CM17 to CM16 = 10b CM06 = 0 CM17 to CM16 = 01b CM06 = 0 CM17 to CM16 = 00b Details of divider Oscillation stop detection circuit Pulse generation circuit for clock edge detection and charge, discharge control circuit XIN clock Forcible discharge when OCD0 = 0 Charge, discharge circuit Oscillation stop detection interrupt generation circuit detection Watchdog timer interrupt OCD1 OCD2 bit switch signal CM14 bit switch signal Oscillation stop detection, watchdog timer, voltage monitor 2 interrupt CM02, CM05, CM06: Bits in CM0 register CM10, CM13, CM14, CM16, CM17: Bits in CM1 register OCD0, OCD1, OCD2: Bits in OCD register FRA00, FRA01: Bits in FRA0 register e g UART0 A/D converterTimer RDTimer RBTimer RA FRA2 register fOCO fOCO-S INT0 SSU/IIC Voltage watch 2 interrupt Watchdog timer System clock Low-speed on-chip oscillator FRA1 register Frequency adjustable CM13 UART1 Divider fOCO40M On-chip oscillator clock Timer RE High-speed on-chip oscillator fOCO-F Divider (1/128) fOCO128 Voltage detection circuit RESET Power-on reset Software reset Interrupt request

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 66 of 458 REJ09B0250-0200 Figure 10.2 CM0 Register System Clock Control Register 0 (1) Symbol Address After Reset CM0 0006h 01101000b Bit Symbol Bit Name Function RW NOTES: b7 b6 b5 b4 b3 b2 b1 b0 00 1 0 0 (b1-b0) Reserved bits Set to 0 RW CM02 WAIT peripheral function clock stop bit 0 : Peripheral function clock does not stop in w ait mode 1 : Peripheral function clock stops in w ait mode RW (b3) Reserved bit Set to 1 RW (b4) Reserved bit Set to 0 RW CM05 XIN clock (XIN-XOUT) stop bit(2,4) 0 : XIN clock oscillates 1 : XIN clock stops(3) RW CM06 System clock division select bit 0(5) 0 : Enables CM16, CM17 1 : Divide-by-8 mode RW (b7) Reserved bit Set to 0 RW When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode). Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the CM0 register. The CM05 bit is to stop the XIN clock w hen the high-speed on-chip oscillator mode, low -speed on-chip oscillator mode is selected. Do not use this bit for w hether the XIN clock is stopped. To stop the XIN clock, set the bits in the follow ing orders: (a) Set the OCD0 and OCD1 bits in the OCD register to 00b. (b) Set the OCD2 bit to 1 (selects on-chip oscillator clock). During external clock input, only the clock oscillation buffer is turned off and clock input is acknow ledged. P4_6 and P4_7 can be used as input ports w hen the CM05 bit is set to 1 (XIN clock stops) and the CM13 bit in the CM1 register is set to 0 (P4_6, P4_7).

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 67 of 458 REJ09B0250-0200 Figure 10.3 CM1 Register System Clock Control Register 1 (1) Symbol Address After Reset CM1 0007h 00100000b Bit Symbol Bit Name Function RW NOTES: 9. Once the CM13 bit is set to 1, it can not to 0 in a program. When entering stop mode, the CM15 bit is set to 1 (drive capacity high). Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the CM1 register. b7 b6 b5 b4 b3 b2 b1 b0 CM10 All clock stop control bit(4,7,8) 0 : Oscillates clock 1 : Stops all clocks (stop mode) RW (b2-b1) Reserved bits Set to 0 RW CM13 Port XIN-XOUT s w itc h bit(7,9) 0 : Input ports P4_6, P4_7 1 : XIN-XOUT pin RW CM14 Low -speed on-chip oscillation stop bit(5,6,8) 0 : Low -speed on-chip oscillator on 1 : Low -speed on-chip oscillator off RW CM15 XIN-XOUT drive capacity select bit(2) 0 : Low 1 : High RW CM17 RW b7 b6 0 0 : No division mode 0 1 : Divide-by-2 mode 1 0 : Divide-by-4 mode 1 1 : Divide-by-16 mode System clock division select bits 1 (3) CM16 RW When the CM10 bit is set to 1 (stop mode) and the CM13 bit is set to 1 (XIN-XOUT pin), the XOUT (P4_7) pin becomes “H”. When the CM13 bit is set to 0 (input ports, P4_6, P4_7), the P4_7 (XOUT) enters input mode. In count source protect mode (Refer to 13.2 Count Source Protection Mode E nabled ), the value rem ains unchanged even if the CM10 and CM14 bits are set. When the CM06 bit is set to 0 (CM16, CM17 bits enabled), the CM16 to CM17 bits become enabled. If the CM10 bit is 1 (stop mode), the internal feedback resistor becomes disabled. When the OCD2 bit is set to 0 (selects XIN clock), the CM14 bit is set to 1 (stops low -speed on-chip oscillator). When the OCD2 bit is set to 1 (selects on-chip oscillator clock), the CM14 bit is set to 0 (low -speed on-chip oscillator on). It remains unchanged even if it is set to 1. When using the low voltage 2 detection interrupt (w hen using the digital filter), set the CM14 bit to 0 (low -speed on- chip oscillator on).

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 68 of 458 REJ09B0250-0200 Figure 10.4 OCD Register Oscillation Stop Detection Register (1) Symbol Address After Reset OCD 000Ch 00000100b Bit Symbol Bit Name Function RW NOTES: b7 b6 b5 b4 b3 b2 b1 b0 0000 OCD1 RW OCD0 RW Oscillation stop detection enable bit(7) 0 : Oscillation stop detection function disabled (2) 1 : Oscillation stop detection function enabled 0 : Disable(2) 1 : Enable Oscillation stop detection interrupt enable bit OCD2 System clock select bit(4) 0 : Selects XI N clock(7) 1 : Selects on-chip oscillator clock(3) RW OCD3 Clock monitor bit(5,6) 0 : XIN clock oscillates 1 : XIN clock stops RO (b7-b4) Reserved bits Set to 0 RW The OCD3 bit remains 0 (XIN clock oscillates) if the OCD1 to OCD0 bits are set to 00b. The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (selects on-chip oscillator clock). Ref er to Figure 10.13 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN Clock for the sw itching procedure w hen the XIN clock re-oscillates after detecting an oscillation stop. Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the OCD register. The OCD2 bit is automatically set to 1 (selects on-chip oscillator clock) if a XIN clock oscillation stop is detected w hile the OCD1 to OCD0 bits are set to 11b. If the OCD3 bit is set to 1 (XIN clock stops), the OCD2 bit remains unchanged w hen w riting 0 (selects XIN clock). The OCD3 bit is enabled w hen the OCD0 bit is set to 1 (oscillation stop detection function enabled). Set the OCD1 to OCD0 bits to 00b before entering stop and high-speed on-chip oscillator mode, low -speed on-chip oscillator mode (XIN clock stops). Set the OCD1 to OCD0 bits to 00b w hen the FRA01 bit in the FRA0 register is set to 1 (selects high-speed on-chip oscillator).

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 69 of 458 REJ09B0250-0200 Figure 10.5 Registers FRA0 and FRA1 High-Speed On-Chip Oscillator Control Register 0(1) Symbol Address After Reset FRA0 0023h 00h Bit Symbol Bit Name Function RW NOTES: b7 b6 b5 b4 b3 b2 b1 b0 000000 FRA00 RW FRA01 RW High-speed on-chip oscillator enable bit 0 : High-speed on-chip oscillator off 1 : High-speed on-chip oscillator on High-speed on-chip oscillator select bit(2) 0 : Selects low -speed on-chip oscillator(3) 1 : Selects high-speed on-chip oscillator Change the FRA01 bit under the follow ing conditions.

• FRA00 = 1 (high-speed on-chip oscillation)
• The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on)
• Bits FRA22 to FRA20 in the FRA2 register All divide ratio mode settings are supported w hen VCC = 3.0 V to 5.5 V (J version) 000b to 111b Divide ratio of 4 or more w hen VCC = 2.7 V to 5.5 V and K version 010b to 111b When setting the FRA01 bit to 0 (selects low -speed on-chip oscillator), do not set the FRA00 bit to 0 (40MHz on-chip oscillator off) at the same time. Set the FRA00 bit to 0 after setting the FRA01 bit to 0. (b7-b2) Reserved bits Set to 0 RW Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the FRA0 register. High-Speed On-Chip Oscillator Control Register 1(1) Symbol Address After Reset FRA1 0024h When Shipping RW NOTES: b7 b0 When changing the values of the FRA1 register, adjust the FRA1 register so that the frequency of the high-speed on-chip oscillator clock w ill be 40 MHz or less. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to the FRA1 register. When adjusting the FRA1 register, set the value of the FRA1 register to 40 MHz and below . RW Function The frequency of high-speed on-chip osc illator is adjusted w ith bits 0 to 7. High-speed on-chip oscillator frequency = 40 MHz (FRA1 register = value w hen shipping) Set the value of the FRA1 register to smaller, the frequency will be higher Set the value of the FRA1 register to larger, the frequency w ill be low er(2)

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 71 of 458 REJ09B0250-0200 The following describes the clocks generated by the clock generation circuit.

10.1 XIN Clock

This clock is supplied by a XI N clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The XIN clock oscillation circuit is configured by connecting a resonator between the XIN and XOUT pins. The XIN clock oscillation circuit cont ains a feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed in the chip. The XIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN pin. Figure 10.8 shows Examples of XIN Clock Connection Circuit. During or after reset, the XIN clock stops. The XIN clock starts oscillating when the CM05 bit in the CM0 register is set to 0 (XIN clock on) after setting the CM13 bit in the CM1 register to 1 (XIN- XOUT pin). To use the XIN clock for the CPU clock source, set the OCD2 bit in the OCD register to 0 (select XIN clock) after the XIN clock is oscillating stably. The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 (stop XIN clock) if the OCD2 bit is set to 1 (select on-chip oscillator clock). When the clocks externally generated to the XIN pin are input, a XIN clock does not stop if setting the CM05 bit to 1. If necessary, use an external circuit to stop the clock. In stop mode, all clocks including the XIN clock stop. Refer to 10.4 Power Control for details. Figure 10.8 Examples of XI N Clock Connection Circuit XIN XOUT MCU (built-in feedback resistor) Rd(1) COUTCIN XIN XOUT MCU (built-in feedback resistor) Externally derived clock VCC VSS NOTE: 1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Use high drive when oscillation starts and, if it is necessary to switch the oscillation drive capacity, do so after oscillation stabilizes. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction. Open Ceramic resonator external circuit External clock input clock Rf(1)

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 72 of 458 REJ09B0250-0200

10.2 On-Chip Oscillator Clocks

This clock is supplied by an on-chip oscillator. The on-chip oscillator contains a high-speed on-chip oscillator and a low-speed on-chip oscillator. Either an on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register.

10.2.1 Low-Speed On-Chi p Oscillator Clock

The clock generated by the low-speed on-chip oscillator is used as th e clock source for the CPU clock, peripheral function clock, fOCO, and fOCO-S. After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator by divide-by-8 is selected for the CPU clock. If the XIN clock stops oscillating when the OCD1 to OCD0 bits in the OCD register are set to 11b, the low- speed on-chip oscillator automatically starts operating, supplying the necessary clock for the MCU. The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating ambient temperature. The applicatio n products must be designed with su fficient margin to accommodate the frequency range.

10.2.2 High-Speed On-Chip Oscillator Clock

The clock generated by the high-speed on-chip oscill ator is used as the clock source for the CPU clock, peripheral function clock, fOCO, fOCO-F and fOCO40M. To use the high-speed on-chip oscillator clock as the cl ock source of the CPU clock, peripheral clock, fOCO, and fOCO-F, set bits FRA20 to FRA22 in the FRA2 register as follows; All divide ratio mode settings are supported when VCC = 3.0 V to 5.5 V (J version)000b to 111b Divide ratio of 4 or more when VCC = 2.7 V to 5.5 V and K version 010b to 111b After reset, the on-chip oscillator clock generated by the high-speed on-chip osci llator stops. The oscillation starts by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). The frequency can be adjusted by the FRA1 and FRA2 registers. Since there are differences in the amount of frequency adjustment among the bits in the FRA1 register, make adjustments by changing the settings of individual bits. Adjust the amount of high-speed on-chip oscillator frequency to 40 MHz and below by setting the FRA1 register.

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 73 of 458 REJ09B0250-0200

10.3 CPU Clock and Peri pheral Function Clock

There are two type clocks: a CPU clock to operate th e CPU and a peripheral func tion clock to operate the peripheral functions. Refer to Figure 10.1 Clock Generation Circuit.

10.3.1 System Clock

The system clock is a clock source for the CPU and peripheral function clocks. The XIN clock or on-chip oscillator clock can be selected.

10.3.2 CPU Clock

The CPU clock is an operating clock for the CPU and watchdog timer. The system clock can be the divide-by-1 (no division), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register to select the value of the division. After reset, the low-speed on-chip oscillator clock divided-by-8 provides the CPU clock. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).

10.3.3 Peripheral Function Clo ck (f1, f2, f4, f8 and f32)

The peripheral function clock is operating clock for the peripheral functions. The clock fi (i = 1, 2, 4, 8, 32) is generated by the system clock divided-by-i. The clock fi is used for timers RA, RB, RD, RE, serial interface and A/D converter. When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral function clock stops in wait mode), the clock fi stop. 10.3.4 fOCO fOCO is operating clocks for the peripheral functions. The fOCO run at the same frequency as the on-chip oscillator clock and can be used as the source for the timer RA. When the WAIT instruction is executed, the clocks fOCO does not stop. 10.3.5 fOCO40M fOCO40M is used as the count source for the timer RD. The fOCO40M is generated by the high-speed on-chip oscillator and provided by setting the FRA00 bit to 1. When the WAIT instruction is executed, the clock fOCO40M does not stop. fOCO40M can be used with supply voltage VCC = 3.0 to 5.5V . 10.3.6 fOCO-F fOCO-F is used as the count source for the AD converte r. The fOCO-F is generated by the high-speed on-chip oscillator and provided by setting the FRA00 bit to 1. When the WAIT instruction is executed, the clock fOCO-F does not stop. 10.3.7 fOCO-S fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. When setting the CM14 bit to 0 (low-speed on-chip oscillator on) using the clock generated by the low-speed on-chip oscillator, the fOCO- S can be provided. When the WAIT instruction is execu ted or in count source protect mode of the watchdog timer, the clock fOCO-S does not stop. 10.3.8 fOCO128 fOCO128 is generated by fOCO divided-by-128. The cloc k fOCO128 is used for capture signal of timer RD (channel 0).

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 74 of 458 REJ09B0250-0200

10.4 Power Control

There are three power control modes. All modes other th an wait and stop modes are referred to as standard operating mode.

10.4.1 Standard Operating Mode

Standard operating mode is further separated into three modes. In standard operating mode, the CPU clock and the peri pheral function clock are supp lied to operate the CPU and the peripheral function clocks. Power consumption control is enab led by controlling the CPU clock frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the more power consumption decreases . When unnecessary oscillator circuits stop, power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source after switching needs to be stabilized and oscillated. If the new clock source is th e XIN clock, allow sufficient wait time in a program until an oscillation is stabilized before exiting. −: can be 0 or 1, no change in outcome.

10.4.1.1 High-Speed Clock Mode

The XIN clock divided-by-1 (no division), -2, -4, -8, or -16 provides the CPU clock. Set the CM06 bit to 1 (divide-by-8 mode) when transiting to high-speed on-chip oscillator mode, low-speed on-chip oscillator mode. If the CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on), the fOCO can be used for timers RA. When the FRA00 bit is set to 1, fOCO40M can be used for timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the watchdog timer and voltage detection circuit.

10.4.1.2 High-Speed On -Chip Oscillator Mode

The high-speed on-chip oscillator is used as the on-chip oscillator clock when the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The on- chip oscillator divided-by-1 (no division), -2, -4, -8 or -16 provides the CPU clock. Set the CM06 bit to 1 (divide-by-8) when transiting to high-speed clock mode. If the FRA00 bit is set to 1, fOCO40M can be used for timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the watchdog timer and voltage detection circuit. Table 10.2 Settings and Modes of Clock Associated Bits Modes OCD Register CM1 Register CM0 Register FRA0 Register OCD2 CM17, CM16 CM14 CM13 CM06 CM05 FRA01 FRA00 High-speed clock mode No division 0 00b − 100 −− Divide-by-2 0 01b − 100 −− Divide-by-4 0 10b − 100 −− Divide-by-8 0 −− 110 −− Divide-by-16 0 11b − 100 −− High-speed on-chip oscillator mode No division 1 00b −− 0 − 11 Divide-by-2 1 01b −− 0 − 11 Divide-by-4 1 10b −− 0 − 11 Divide-by-8 1 −− − 1 − 11 Divide-by-16 1 11b −− 0 − 11 Low-speed on-chip oscillator mode No division 1 00b 0 − 0 − 0 − Divide-by-2 1 01b 0 − 0 − 0 − Divide-by-4 1 10b 0 − 0 − 0 − Divide-by-8 1 − 0 − 1 − 0 − Divide-by-16 1 11b 0 − 0 − 0 −

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10.4.1.3 Low-Speed On-Chip Oscillator Mode

If the CM14 bit in the CM1 register is set to 0 (low-s peed on-chip oscillator on) or the FRA01bit in the FRA0 register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock. The on-chip oscillator clock divided-by-1 (no division), -2, -4, -8 or -16 provides the CPU clock. The on-chip oscillator clock is also the clock so urce for the peripheral function clocks. Set the CM06 bit to 1 (divide-by-8 mode) when transiting to high-speed clock mode. When the FRA00 bit is set to 1, fOCO40M can be used for timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the watchdog timer and voltage detection circuit. In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4 register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation. To enter wait mode from low-speed clock mode, settin g the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled) enables lower consumption current in wait mode. When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.10 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.

10.4.2 Wait Mode

Since the CPU clock stops in wait mode, the CPU operated in the CPU clock and the watchdog timer when count source protection mode is disabled stops. The XIN clock and on-chip oscillator clock do not stop and the peripheral functions using these clocks maintain operating.

10.4.2.1 Peripheral Functi on Clock Stop Function

If the CM02 bit is set to 1 (periphera l function clock stops in wait mode), the f1, f2, f4, f8 and f32 clocks stop in wait mode. The power consumption can be reduced.

10.4.2.2 Entering Wait Mode

The MCU enters wait mode when the WAIT instruction is executed. When the OCD2 bit in the OCD register is set to 1 (o n-chip oscillator selected as system clock), set the OCD1bit in the OCD register to 0 (oscillation stop dete ction interrupt disabled) before executing the WAIT instruction. If the MCU enters wait mode while the OCD1 bit is set to 1 (oscillation stop detection interrupt enabled), current consumption is not reduced because the CPU clock does not stop.

10.4.2.3 Pin Status in Wait Mode

The I/O port is the status before wait mode was entered is maintained.

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10.4.2.4 Exiting Wait Mode

The MCU exits wait mode by a hardware reset or peripheral function interrupt. When using a hardware reset to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to 000b (interrupts disabled) before executing the WAIT instruction. The peripheral function interrupts are affected by the CM02 bit. When th e CM02 bit is set to 0 (peripheral function clock does not stop in wait mode), all periph eral function interrupts can be used to exit wait mode. When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the peripheral function clock stop operating and the periphera l functions operated by ex ternal signals can be used to exit wait mode. Table 10.3 lists Interrupts to Exit Wait Mode and Usage Conditions. Figure 10.9 shows the Time from Wait Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set the interrupt priority level to the ILVL2 to ILVL0 bits in the interrupt control register of the peripheral function interrupts to use for exiting wait mode. Set the ILVL2 to ILVL0 bits of the peripheral function interrupts not to use for exiting wait mode to 000b (disables interrupt). (2) Set the I flag to 1. (3) Operate the peripheral function to use for exiting wait mode. When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register as described in Figure 10.9. The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock when the WAIT instruction is executed. Table 10.3 Interrupts to Exit Wait Mode and Usage Conditions Interrupt CM02 = 0 CM02 = 1 Serial Interface Interrupt Usable when operating with internal or external clock Usable when operating with external clock Clock Synchronous Serial I/O with Chip Select Interrupt / I 2C Bus Interface Interrupt Usable in all modes − (Do not use) Key Input Interrupt Usable Usable A/D Conversion Interrupt Usable in one-shot mode − (Do not use) Timer RA Interrupt Usable in all modes Can be used if there is no filter in event counter mode. Usable by selecting fOCO as count source. Timer RB Interrupt Usable in all modes − (Do not use) Timer RD Interrupt Usable in all modes Usable by selecting fOCO40M as count source Timer RE Interrupt Usable in all modes − (Do not use) INT Interrupt Usable Usable (INT0 to INT3 can be used if there is no filter.) Voltage Monitor 2 Interrupt Usable Usable Oscillation Stop Detection Interrupt Usable − (Do not use)

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 77 of 458 REJ09B0250-0200 Figure 10.9 Time from Wait Mode to Interrupt Routine Execution FMR0 Register FMSTP Bit Time until Flash Memory is Activated (T1) Time until CPU Clock is Supplied (T2) Time for Interrupt Sequence (T3) Remarks (flash memory operates) Period of system clock × 12 cycles + 30 µs (max.) Period of CPU clock × 6 cycles Period of CPU clock × 20 cycles Following total time is the time from wait mode until an interrupt routine is executed. (flash memory stops) Period of system clock × 12 cycles Same as above Same as above Wait mode Flash memory activation sequence CPU clock restart sequence Interrupt sequence T1 T2 T3 Interrupt request generated

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10.4.2.5 Reducing Intern al Power Consumption

Internal power consumption can be reduced by using low-speed on-chip oscillator mode. Figure 10.10 shows the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit. When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.10 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit. Figure 10.10 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit NOTES: 1. Execute this handling to all interrupt handlings generated around the WAIT instruction. If it is not necessary to start the high-speed clock or the high-speed on-chip oscillator in the interrupt handling, it does not need to be started. 2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposit e. 3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode). 4. When entering wait mode, follow 10.6.2 Wait Mode. Handling procedure of internal power low consumption enabled by VCA20 bit Enter low-speed on-chip oscillator mode Stop XIN clock and high-speed on-chip oscillator clock VCA20 ← 1 (internal power low consumption enabled)(2) Enter wait mode(4) VCA20 ← 0 (internal power low consumption disabled)(2) Start XIN clock or high-speed on-chip oscillator clock (Wait until XIN clock oscillation stabilizes) Enter high-speed clock mode or high-speed on-chip oscillator mode In interrupt handling routine VCA20 ← 0 (internal power low consumption disabled)(2) Start XIN clock or high-speed on-chip oscillator clock Enter high-speed clock mode or high-speed on-chip oscillator mode Enter low-speed on-chip oscillator mode Exit wait mode by interrupt Stop XIN clock and high-speed on-chip oscillator clock VCA20 ← 1 (internal power low consumption enabled)(2,3) Interrupt handling completed Step (1) Step (2) Step (3) Step (4) Step (5) Step (6) Step (7) Step (8) Step (5) Step (6) Step (7) Step (8) (Wait until XIN clock oscillation stabilizes) Step (1) Step (2) Step (3) If it is necessary to start the high-speed clock or the high-speed on-chip oscillator in the interrupt handling routine, execute steps (5) to (7) in the interrupt routine. If the high-speed clock or high-speed on-chip oscillator is started in the interrupt handling routine, execute steps (1) to (3) at the last of the interrupt routine. (Note 1) Interrupt handling VCA20: Bit in VCA2 register

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10.4.3 Stop Mode

Since the oscillator circuits stop in wait mode, the CP U clock and peripheral function clock stop and the CPU and peripheral functions clocked by these clocks stop operating. The least power required to operate the MCU is in stop mode. If the voltage applied to the VCC pin is VRAM or more, the internal RAM is maintained. The peripheral functions clocked by external signals maintain operating. Table 10.4 lists Interrupts to Exit Stop Mode and Usage Conditions.

10.4.3.1 Entering Stop Mode

The MCU enters stop mode by setting the CM10 bit in the CM1 register to 1 (all clocks stop). At the same time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode) and the CM15 bit in the CM10 register is set to 1 (drive capability HIGH of XIN clock oscillator circuit). When using stop mode, set the OCD1 to OCD0 bits to 00b before entering stop mode.

10.4.3.2 Pin Status in Stop Mode

The status before entering wait mode is maintained. However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pins), the XOUT(P4_7) pin is held “H”. When the CM13 bit is set to 0 (input port P4_6 and P4_7), the P4_7(XOUT) is held in input status.

10.4.3.3 Exiting Stop Mode

The MCU exits stop mode by a reset or peripheral function interrupt. When using a reset to exit stop mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to 000b (disables interrupts) before setting the CM10 bit to 1. Figure 10.11 shows the Time from Stop Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to 1. (1) Set the interrupt priority level to the ILVL2 to ILVL 0 bits of the peripheral function interrupts to use for exiting stop mode. Set the ILVL2 to ILVL0 bits of the peripheral function interrupts not to use for exiting stop mode to 000b (disables interrupt). (2) Set the I flag to 1. (3) Operates the peripheral function to use for exiting stop mode. When exiting by a peripheral function interrupt, th e interrupt sequence is executed when an interrupt request is generated and the CPU clock supply is started. If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral function interrupt, the CPU clock becomes the previous system clock divided by 8. Table 10.4 Interrupts to Exit Stop Mode and Usage Conditions Interrupt Usage Conditions Key Input Interrupt − INT0 to INT3 Interrupt Can be used if there is no filter Timer RA Interrupt When there is no filter and external pulse is counted in event counter mode Serial Interface Interrupt When external clock is selected Voltage Monitor 2 Interrupt Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set to 1)

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 80 of 458 REJ09B0250-0200 Figure 10.11 Time from Stop Mode to Interrupt Routine Execution Time until Flash Memory is Activated (T2) Time until CPU Clock is Supplied (T3) Time for Interrupt Sequence (T4) Remarks (flash memory operates) Period of system clock × 12 cycles + 30 µs (max.) Period of CPU clock × 6 cycles Period of CPU clock × 20 cycles Following total time of T0 to T4 is the time from wait mode until an interrupt routine is executed. (flash memory stops) Period of system clock × 12 cycles Same as above Same as above Stop mode Flash memory activation sequence CPU clock restart sequence Interrupt sequence T2 T3 T4 Interrupt request generated Oscillation period of the CPU clock source used immediately before stop mode Internal power stability time 150 µs (max.) FMR0 Register FMSTP Bit

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10.5 Oscillation Stop Detection Function

The oscillation stop detection function is a function to det ect the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register. Table 10.5 lists the Specifications of Oscillation Stop Detection Function. When the XIN clock is the CPU clock so urce and the OCD1 to OCD0 bits are set to 11b, the system is placed in the following state if the XIN clock stops.

• OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)
• OCD3 bit in OCD register = 1 (XIN clock stops)
• CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)
• Oscillation stop detection interrupt request is generated

10.5.1 How to Use Oscillat ion Stop Detection Function

• The oscillation stop detection interrupt shares the vector with the voltage monitor 2 interrupt and the watchdog timer interrupt. When using the oscillation stop detection interrupt and watchdog timer interrupt, the interrupt cause needs to be determined. Table 10.6 lists the Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, V oltage Monitor 1, and V oltage Monitor 2 Interrupts. Figure 10.14 shows an Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, V oltage Monitor 1, or V oltage Monitor 2 Interrupt.
• When the XIN clock is re-oscillated after oscillation stop, switch the XIN clock to the clock source of the CPU clock and peripheral functions by a program. Figure 10.13 shows the Procedure for Switching Clock Source from Low-Speed On-Chi p Oscillator to XIN Clock.
• To enter wait mode while using the oscillation stop detection function, set the CM02 bit to 0 (peripheral function clock does not stop in wait mode).
• Since the oscillation stop detection function is a function preparing to stop the XIN clock by the external cause, set the OCD1 to OCD0 bits to 00b when the XIN clock stops or oscillates in the program, that is stop mode is selected or the CM05 bit is changed.
• This function cannot be used when the XIN clock fre quency is less than 2 MHz. Set the OCD1 to OCD0 bits to 00b.
• When using the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions after detecting the oscillation stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on- chip oscillator selected) and the OCD1 to OCD0 bits to 11b. When using the high-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions after detecting the oscillation stop, set the FRA00 bit to 1 (high-speed on-chip oscillator on) and the FRA01 bit to 1 (high-speed on-chip oscillator selected) and the OCD1 to OCD0 bits to 11b. Table 10.5 Specifications of Oscillation Stop Detection Function Item Specification Oscillation Stop Detection Clock and Frequency Bandwidth f(XIN) ≥ 2 MHz Enabled Condition for Oscillation Stop Detection Function Set OCD1 to OCD0 bits to 11b Operation at Oscillation Stop Detection Oscillation stop dete ction interrupt is generated

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 83 of 458 REJ09B0250-0200 Figure 10.13 Procedure for Switching Clock Sour ce from Low-Speed On-Chip Oscillator to XIN Clock Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, and Voltage Monitor 2 Interrupts Generated Interrupt Source Bit Showing Interrupt Cause Oscillation Stop Detection ((a) or (b)) (a) OCD3 bit in OCD register = 1 (b) OCD1 to OCD0 bits in OCD register = 11b and the OCD2 bit = 1 Watchdog Timer VW2C3 bit in VW2C register = 1 Voltage Monitor 2 VW2C2 bit in VW2C register = 1 Set OCD1 to OCD0 bits to 00b Determine several times that the OCD bit is 0 (XIN clock oscillates) Yes Set OCD2 bit to 0 (select XIN Clock) End Switch to XIN clock OCD3 to OCD0 bits: Bits in OCD register No

R8C/20 Group, R8C/21 Group 10. Clock Generation Circuit Rev.2.00 Aug 27, 2008 Page 84 of 458 REJ09B0250-0200 Figure 10.14 Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt NOTE: 1. This disables multiple oscillation stop detection interrupts. OCD1 to OCD3: Bits in OCD register VW2C3: Bit in VW2C register Interrupt sources judgment OCD3 = 1? (XIN clock stops) OCD1 = 1 (Oscillation stop detection interrupt enable), and OCD2=1 (Selects on-chip oscillator clock)? VW2C3 = 1? (Watchdog time underflows) Jump to oscillation stop detection interrupt process routine. Jump to voltage monitor 2 Interrupt process routine. Jump to watchdog timer interrupt process routine. NO YES NO YES NO YES OCD1 = 0 (Oscillation stop detection interrupt disable) (1)

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10.6 Notes on Clock Generation Circuit

10.6.1 Stop Mode

When entering stop mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and the CM10 bit to “1” (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit in the CM1 register to “1” (stop mode) and the program stops. Insert at l east 4 NOP instructions following the JMP.B instruction immediately after the instruction which sets the CM10 bit to “1”.

• Example to enter stop mode BCLR 1,FMR0 ; CPU rewrite mode disabled BSET 0,PRCR ; Protect disabled FSET I ; Enable interrupt BSET 0,CM1 ; Stop mode JMP.B LABEL_001 LABEL_001: NOP NOP NOP NOP

10.6.2 Wait Mode

When entering wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT inst ruction and the program stops. Insert at least 4 NOP instructions after the WAIT instruction.

• Example to execute the WAIT instruction BCLR 1,FMR0 ; CPU rewrite mode disabled FSET I ; Enable interrupt WAIT ; Wait mode NOP NOP NOP NOP

10.6.3 Oscillation Stop Detection Function

Since the oscillation stop detection function cannot be us ed if the XIN clock frequency is less than 2 MHz, set the OCD1 to OCD0 bits to 00b.

10.6.4 Oscillation Circuit Constants

Ask the maker of the oscillator to specify the beat oscillation circuit constants on your system.

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12.1 Interrupt Overview

12.1.1 Types of Interrupts

Figure 12.1 shows the Interrupts. Figure 12.1 Interrupts

• Maskable interrupt: The interrupt enable flag (I flag) enables or disabl es these interrupt. The interrupt priority order can be changed based on the interrupt priority level.
• Non-maskable interrupt: The interrupt enable flag (I flag) does not enab le or disable an interrupt. The interrupt priority order based on interrupt priority level cannot be changed. Interrupt (non-maskable interrupt) Hardware Software (non-maskable interrupt) (maskable interrupt) Special Peripheral function(1) Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Watchdog timer Oscillation stop detection Voltage monitor 2 Single step (2) Address break(2) Address match NOTES: 1. Peripheral function interrupts in the MCU are used to generate the peripheral interrupt. 2. Do not use this interrupt. This is for use with development tools only.

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12.1.2 Software Interrupts

A software interrupt is generated when an instruction is executed. The software interrupts are non-maskable interrupts.

12.1.2.1 Undefined Instruction Interrupt

The undefined instruction interrupt is generated when the UND instruction is executed.

12.1.2.2 Overflow Interrupt

The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO instruction is executed. Instructions to set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV , DIVU, DIVX, NEG , RMPA, SBB, SHA, SUB

12.1.2.3 BRK Interrupt

A BRK interrupt is generated when the BRK instruction is executed.

12.1.2.4 INT Instruction Interrupt

An INT instruction interrupt is generated when the INT instruction is executed. The INT instruction can select software interrupt numbers 0 to 63. Software interrupt numbers 3 to 31 are assigned to the peripheral function interrupt. Therefore, the MCU executes the same interr upt routine when the INT in struction is executed as when a peripheral function interrupt is generated. In software interrupt numbers 0 to 31, the U flag is saved to the stack during instruction execution and set the U flag to 0 (ISP sele cted) before execu ting an interrupt sequence. The U flag is restored from the stack when returning from the interrupt routine. In software interrupt numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.

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12.1.3 Special Interrupts

Special interrupts are non-maskable interrupts.

12.1.3.1 Watchdog Timer Interrupt

The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer.

12.1.3.2 Oscillation Stop Detection Interrupt

Oscillation Stop Detection Interrupt is generated by the oscillation stop detection f unction. For details of the oscillation stop detection function, refer to 10. Clock Generation Circuit.

12.1.3.3 Voltage Monitor 2 Interrupt

The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage detection circuit, refer to 6. Voltage Detection Circuit.

12.1.3.4 Single-Step Interrupt, and Address Break Interrupt

Do not use the single-step interrupt. For development tools only.

12.1.3.5 Address Match Interrupt

The address match interrupt is generated immediately before executing an instruction that is stored into an address indicated by the RMAD0 to RMAD1 registers when the AIER0 or AIER1 bit in the AIER register which is set to 1 (address match interrupt enable). For details of the address match interrupt, refer to 12.4 Address Match Interrupt.

12.1.4 Peripheral Function Interrupt

The peripheral function interrupt is generated by the internal peripheral function of the MCU and a maskable interrupt. Refer to Table 12.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For details of the peripheral function, refer to the description of each peripheral function.

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12.1.5 Interrupts and Interrupt Vector

There are 4 bytes in one vector. Set the starting address of interrupt routine in each vector table. When an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector. Figure 12.2 shows the Interrupt Vector. Figure 12.2 Interrupt Vector

12.1.5.1 Fixed Vector Tables

The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh. Table 12.1 lists the Fixed Vector Tables. The vector ad dresses (H) of fixed vectors are used by the ID code check function. For details, refer to 19.3 Functions to Prevent Rewriting of Flash Memory. NOTE: 1. Do not use the single-step interr upt. For development tools only. Table 12.1 Fixed Vector Tables Interrupt Source Vector Addresses Address (L) to (H) Remarks Reference Undefined Instruction 0FFDCh to 0FFDFh Inte rrupt on UND instruction R8C/Tiny Series software manual Overflow 0FFE0h to 0FFE 3h Interrupt on INTO instruction BRK Instruction 0FFE4h to 0FFE7h If the content of address 0FFE7h is FFh, program execution starts from the address shown by the vector in the relocatable vector table. Address Match 0FFE8h to 0FFEBh 12.4 Address Match Interrupt Single Step (1) 0FFECh to 0FFEFh Watchdog Timer Oscillation Stop Detection Voltage Monitor 2 0FFF0h to 0FFF3h 13. Watchdog Timer 10. Clock Generation Circuit 6. Voltage Detection Circuit Address Break (1) 0FFF4h to 0FFF7h (Reserved) 0FFF8h to 0FFFBh Reset 0FFFCh to 0FFFFh 5. Resets Vector address (L) Vector address (H) MSB LSB Low address Mid address High address0 0 0 0 0 0 0 0 0 0 0 0

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12.1.5.2 Relocatable Vector Tables

The relocatable vector tables occupy 256 bytes from the starting address set in the INTB register. Table 12.2 lists the Relocatable Vector Tables. NOTES: 1. These addresses are relative to those in the INTB register. 2. The IICSEL bit in the PMR register switches functions. 3. The I flag does not disable these interrupts. Table 12.2 Relocatable Vector Tables Interrupt Source Vector Address(1) Address (L) to Address (H) Software Interrupt Number Interrupt Control Register Reference BRK Instruction(3) +0 to +3 (0000h to 0003h) 0 − R8C/Tiny Series Software Manual − (Reserved) 1 to 7 − Timer RD (Channel 0) +32 to +35 (0020h to 0023h) 8 TRD0IC 14.3 Timer RD Timer RD (Channel 1) +36 to +39 (0024h to 0027h) 9 TRD1IC Timer RE +40 to +43 (0028h to 002Bh) 10 TREIC 14.4 Timer RE − (Reserved) 11 to 12 −− Key Input +52 to +55 (0034h to 0037h) 13 KUPIC 12.3 Key Input Interrupt A/D +56 to +59 (0038h to 003Bh) 14 ADIC 18. A/D Converter Clock Synchronous Serial I/O with Chip Select/I2C bus Interface(2) +60 to +63 (003Ch to 003Fh) 15 SSUIC/IICIC 16.2 Clock Synchronous Serial I/O with Chip Select (SSU),

16.3 I2C Bus Interface

− (Reserved) 16 −− UART0 Transmit +68 to +71 (0044h to 0047h) 17 S0TIC 15. Serial Interface UART0 Receive +72 to +75 (0048h to 004Bh) 18 S0RIC UART1 Transmit +76 to +79 (004Ch to 004Fh) 19 S1TIC UART1 Receive +80 to +83 (0050h to 0053h) 20 S1RIC INT2 +84 to +87 (0054h to 0057h) 21 INT2IC 12.2 INT Interrupt Timer RA +88 to +91 (0058h to 005Bh) 22 TRAIC 14.1 Timer RA − (Reserved) 23 −− Timer RB +96 to +99 (0060h to 0063h) 24 TRBIC 14.2 Timer RB INT1 +100 to +103 (0064h to 0067h) 25 INT1IC 12.2 INT Interrupt INT3 +104 to +107 (0068h to 006Bh) 26 INT3IC − (Reserved) 27 −− − (Reserved) 28 −− INT0 +116 to +119 (0074h to 0077h) 29 INT0IC 12.2 INT Interrupt − (Reserved) 30 −− − (Reserved) 31 −− Software Interrupt(3) +128 to +131 (0080h to 0083h) to +252 to +255 (00FCh to 00FFh) 32 to 63 − R8C/Tiny Series Software Manual

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12.1.6 Interrupt Control

The following describes enable/disable the maskable interrupts and set the priority order to acknowledge. The contents explained does not apply to the nonmaskable interrupts. Use the I flag in the FLG register, IPL and the ILVL2 to ILVL0 bits in each interrupt control register to enable/ disable the maskable interrupts. Whethe r an interrupt is request ed is indicated by the IR bit in each interrupt control register. Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRD0IC, TRD1IC, SSUIC, and IICIC and Figure 12.5 shows the Registers INT0IC to INT3IC. Figure 12.3 Interrupt Control Register Interrupt Control Register(2) Symbol Address After Reset TREIC 004Ah XXXXX000b KUPIC 004Dh XXXXX000b AD I C 004Eh XXXXX000b S0TIC 0051h XXXXX000b S0RIC 0052h XXXXX000b S1TIC 0053h XXXXX000b S1RIC 0054h XXXXX000b TRAIC 0056h XXXXX000b TRBIC 0058h XXXXX000b Bit Symbol Bit Name Function RW NOTES: 2. Rew rite the interrupt control register, rew rite it w hen the interrupt request w hich is applicable for its register is not generated. Refer to 12.6.5 Changing Interrupt Control Register Contents . b7 b6 b5 b4 b3 b2 b1 b0 ILV L0 RW Interrupt priority level select bits b2 b1 b0 0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 ILV L1 RW ILV L2 RW IR Interrupt request bit 0 : Requests no interrupt 1 : Requests interrupt RW (1) (b7-b4) —Nothing is assigned. If necessary, set to 0. When read, the content is indeterminate. Only 0 can be w ritten to the IR bit. Do not w rite 1.

R8C/20 Group, R8C/21 Group 12. Interrupts Rev.2.00 Aug 27, 2008 Page 93 of 458 REJ09B0250-0200 Figure 12.4 Registers TRD0IC, TRD1IC, SSUIC, and IICIC Interrupt Control Register(1) Symbol Address After Reset TRD0IC 0048h XXXXX000b TRD1IC 0049h XXXXX000b SSUIC/IICIC(2) 004Fh XXXXX000b Bit Symbol Bit Name Function RW NOTES: (b7-b4) —Nothing is assigned. If necessary, set to 0. When read, the content is undefined. IR Interrupt request bit 0 : Requests no interrupt 1 : Requests interrupt RO ILV L0 RW Interrupt priority level select bits b2 b1 b0 0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 ILV L1 RW ILV L2 RW The IICSEL bit in the PMR register sw itches functions. To rew rite the interrupt control register, rew rite it w hen the interrupt request w hich is applicable for its register is not generated. Refer to 12.6.5 Changing Interrupt Control Register Contents . b7 b6 b5 b4 b3 b2 b1 b0

R8C/20 Group, R8C/21 Group 12. Interrupts Rev.2.00 Aug 27, 2008 Page 94 of 458 REJ09B0250-0200 Figure 12.5 Registers INT0IC to INT3IC INTi Interrupt Control Register (i = 0 to 3)(2) Symbol Address After Reset INT2IC 0055h XX00X000b INT1IC 0059h XX00X000b INT3IC 005Ah XX00X000b INT0IC 005Dh XX00X000b Bit Symbol Bit Name Function RW NOTES: To rew rite the interrupt control register, rew rite it w hen the interrupt request w hich is applicable for its register is not generated. Refer to 12.6.5 Changing Interrupt Control Register Contents . If the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge). The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to 12.6.4 Changing Interrupt Sources . b7 b6 b5 b4 b3 b2 b1 b0 ILV L0 RW Interrupt priority level select bits b2 b1 b0 0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 ILV L1 RW ILV L2 RW IR Interrupt request bit 0 : Requests no interrupt 1 : Requests interrupt RW (1) POL Polarity sw itch bit(4) 0 : Selects falling edge 1 : Selects rising edge(3) RW (b5) Reserved bit Set to 0 RW (b7-b6) —Nothing is assigned. If necessary, set to 0. When read, the content is undefined. Only 0 can be w ritten to the IR bit. (Do not w rite 1.)

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12.1.6.1 I Flag

The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (enabled) enables the maskable interrupt. Setting the I flag to 0 (disabled) disables all maskable interrupts.

12.1.6.2 IR Bit

The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is acknowledged and the CPU branches to the co rresponding interrupt vector, the IR bit is set to 0 (= interrupt not requested). The IR bit can be set to 0 by a program. Do not write 1 to this bit. Operations of the IR bit vary by Timer RD interrupt, cl ock synchronous serial I/O interrupt with chip select or I 2C bus interface interrupt. For details, refer to 12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts and I2C bus Interface Interrupts (Interrupts with Multiple Interrupt Request Sources).

12.1.6.3 Bits ILVL2 to ILVL0 and IPL

Interrupt priority levels can be set using the ILVL2 to ILVL0 bits. Table 12.3 lists the Settings of Interrupt Priority Leve ls and Table 12.4 lists the Interrupt Priority Levels Enabled by IPL. The following are conditions under which an interrupt is acknowledged:

• I flag = 1
• IR bit = 1
• Interrupt priority level > IPL The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. They do not affect one another. Table 12.3 Settings of Interrupt Priority Levels ILVL2 to ILVL0 Bits Interrupt Priority Level Priority Order 000b Level 0 (inter rupt disabled) − 001b Level 1 Low 010b Level 2 011b Level 3 100b Level 4 101b Level 5 110b Level 6 111b Level 7 High Table 12.4 Interrupt Priority Levels Enabled by IPL IPL Enabled Interrupt Priority Levels 000b Interrupt level 1 and above 001b Interrupt level 2 and above 010b Interrupt level 3 and above 011b Interrupt level 4 and above 100b Interrupt level 5 and above 101b Interrupt level 6 and above 110b Interrupt level 7 and above 111b All maskable interrupts are disabled

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12.1.6.4 Interrupt Sequence

An interrupt sequence is performed between an in terrupt request acknowledgeme nt and interrupt routine execution. When an interrupt request is genera ted while an instruction is executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle. However, in regards to the SMOVB, SMOVF, SST R or RMPA instruction, if an interrupt request is generated while executing the instruction, the MCU susp ends the instruction to start the interrupt sequence. The interrupt sequence is performed as follows. Figure 12.6 shows the Time Required for Executing Interrupt Sequence. (1) The CPU gets interrupt information (interrupt nu mber and interrupt request level) by reading the address 00000h. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested) (2). (2) The FLG register immediately before entering the interrupt sequence is saved to the CPU internal temporary register(1). (3) The I, D and U flags in the FLG register are set as follows: The I flag is set to 0 (disables interrupts). The D flag is set to 0 (disables single-step interrupt). The U flag is set to 0 (ISP selected). However, the U flag does not change state if an IN T instruction for software interrupt number 32 to 63 is executed. (4) The CPU’s internal temporary register (1) is saved to the stack. (5) The PC is saved to the stack. (6) The interrupt priority level of the acknowledged interrupt is set in the IPL. (7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, the instructions are NOTES: 1. This register cannot be used by user. Figure 12.6 Time Required for Executing Interrupt Sequence 2. For operations of the IR bit, refer to 12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts and I 2C bus Interface Interrupts (Interrupts with Multiple Interrupt Request Sources). 123456789 1 0 11 12 13 14 15 16 17 18 19 20 CPU clock Address bus Data bus RD WR Address 0000h Indeterminate Indeterminate Indeterminate Interrupt information SP-2 SP-1 SP-4 SP-3 VEC VEC+1 VEC+2 PC SP-2

contents

NOTE: 1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to acknowledge instructions.

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12.1.6.5 Interrupt Response Time

Figure 12.7 shows an Interrupt Response Time. The interr upt response time is the period between an interrupt request generation and the execution of the first instruction in an interrupt routine. An interrupt response time includes the period between an interrupt request genera tion and the completed execution of an instruction (refer to (a) in Figure 12.7) and the period required to perform an interrupt sequence (20 cycles, refer to (b) in Figure 12.7). Figure 12.7 Interrupt Response Time

12.1.6.6 IPL Change when Inte rrupt Request is Acknowledged

When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the acknowledged interrupt is set in the IPL. When a software interrupt and special interrupt request are acknowledged, the level listed in Table 12.5 is set to the IPL. Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged. Table 12.5 IPL Value When Software or Special Interrupt Is Acknowledged Interrupt Sources Value Set to IPL Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 2, Address Break 7 Software, Address Match, Single-Step Not changed Interrupt request is generated Interrupt request is acknowledged Instruction Interrupt sequence Instruction in interrupt routine Time (a) 20 Cycles (b) Interrupt response time (a) Period between an interrupt request generation and the completed execution of an instruction. The length of this time varies depending on the instruction being executed. The DIVX instruction requires the longest time; 30 cycles (no wait and when the register is set as the divisor) (b) 21 cycles for address match and single-step interrupts.

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12.1.6.7 Saving a Register

In the interrupt sequence, the FLG register and PC are saved to the stack. After 4 high-order bits in the PC and 4 high-order (IPL ) and 8 low-order bits in the FLG register, extended to 16 bits, are saved to the stack, the 16 low-order bits in the PC are saved. Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request. The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM instruction can save several registers in the register bank being currently used (1) with 1 instruction. NOTE: 1. Selectable from the R0, R1, R2, R3, A0, A1, SB and FB registers. Figure 12.8 Stack State Before and After Acknowledgement of Interrupt Request The register saving operation which is performed in the interrupt sequence is saved in 8 bits every 4 steps. Figure 12.9 shows the Register Saving Operation. Figure 12.9 Register Saving Operation Stack [SP] SP value before interrupt is generated Content of previous stack LSBMSB Address Content of previous stack m−4 m−3 m−2 m−1 m m+1 Stack state before interrupt request is acknowledged [SP] New SP value Content of previous stack LSBMSB Content of previous stack m m+1 Stack state after interrupt request is acknowledged PCL PCM FLGL FLGH PCH m−4 m−3 m−2 m−1 StackAddress PCH : High-order 4 bits of PC PCM : Middle-order 8 bits of PC PCL : Low-order 8 bits of PC FLGH : High-order 4 bits of FLG FLGL : Low-order 8 bits of FLG NOTE: 1. When executing the software number 32 to 63 INT instructions, this SP is specified by the U flag. Otherwise it is ISP. Stack Completed saving registers in four operations. Address [SP]−5 [SP] PCL PCM FLGL FLGH PCH (3) (4) (1) (2) Saved, 8 bits at a time Sequence in which order registers are saved NOTE: 1. [SP] indicates the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. When executing the software number 32 to 63 INT instructions, this SP is specified by the U flag. Otherwise it is ISP. [SP]−4 [SP]−3 [SP]−2 [SP]−1 PCH : High-order 4 bits of PC PCM : Middle-order 8 bits of PC PCL : Low-order 8 bits of PC FLGH : High-order 4 bits of FLG FLGL : Low-order 8 bits of FLG

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12.1.6.8 Returning from an Interrupt Routine

When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically returned. Th e program, executed before the interrupt request has been acknowledged, starts running again. Return the register saved by a program in an interrupt routine using the POPM instruction or others before the REIT instruction.

12.1.6.9 Interrupt Priority

If two or more interrupt requests ar e generated while executing one instru ction, the interrupt with the higher priority is acknowledged. Set the ILVL2 to ILVL0 bits to select the desired prio rity level for maskable interrupts (peripheral functions). However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the higher priority interrupt acknowledged in hardware. The priority levels of special interrupts such as reset (reset has the highest priority) and watchdog timer are set by hardware. Figure 12.10 shows the Priority Levels of Hardware Interrupts. The interrupt priority does not affect software interr upts. The MCU jumps to the interrupt routine when the instruction is executed. Figure 12.10 Priority Levels of Hardware Interrupts Reset Watchdog timer Oscillation stop detection Voltage monitor 2 Peripheral function Single step Address match High Low Address break

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12.1.6.10 Interrupt Prio rity Judgement Circuit

The interrupt priority judgement circuit selects the highest priority interrupt. Figure 12.11 shows the Interrupt Priority Level Judgement Circuit. Figure 12.11 Interrupt Priority Level Judgement Circuit INT3 Timer RB Timer RA INT0 INT1 UART1 receive UART0 receive A/D conversion SSU/I2C bus(1) Key Input IPL Priority level of each interrupt Level 0 (default value) Lowest Highest Priority of peripheral function interrupts (if priority levels are same) Interrupt request level judgment output signal Interrupt request acknowledgedI flag Address match Watchdog timer Oscillation stop detection Voltage monitor 2 NOTE: 1. The IICSEL bit in the PMR register switches functions. UART0 transmit INT2 UART1 transmit Timer RE Timer RD0 Timer RD1

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12.2 INT Interrupt

12.2.1 INTi Interrupt (i = 0 to 3)

The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN register is set to 1 (enable). The e dge polarity is selected using the INTiPL bit in the INTEN register and the POL bit in the INTiIC register. Inputs can be passed through a digital filter with three different sampling clocks. The INT0 pin is shared with the pulse outp ut forced cutoff of timer RD and shared with the external trigger input pin of timer RB. Figure 12.12 shows the INTEN Register. Figure 12.13 shows the INTF Register. Figure 12.12 INTEN Register External Input Enable Register Symbol Address After Reset INTEN 00F9h 00h Bit Symbol Bit Name Function RW INT0 input enable bit INT0 input polarity select bit(1,2) INT1 input enable bit INT1 input polarity select bit(1,2) INT2 input enable bit INT2 input polarity select bit(1,2) INT3 input enable bit INT3 input polarity select bit(1,2) NOTES: 0 : Disable 1 : Enable RW INT2EN 0 : Disable 1 : Enable RW INT2PL 0 : One edge 1 : Both edges RW When setting the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling edge). The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 12.6.4 Changing Interrupt Sources . 0 : Disable 1 : Enable 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges RW INT0PL RW INT1EN 0 : Disable 1 : Enable RW INT0EN RW INT1PL 0 : One edge 1 : Both edges RW INT3EN INT3PL b3 b2 b1 b0b7 b6 b5 b4

R8C/20 Group, R8C/21 Group 12. Interrupts Rev.2.00 Aug 27, 2008 Page 102 of 458 REJ09B0250-0200 Figure 12.13 INTF Register INT Input Filter Select Register Symbol Address After Reset INTF 00FAh 00h Bit Symbol Bit Name Function RW INT0 input filter select bits INT1 input filter select bits INT2 input filter select bits INT3 input filter select bits INT0F0 RW INT0F1 RW b7 b6 b5 b4 b3 b2 b1 b0 RW b1 b0 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW b7 b6 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 samplingINT3F1 INT3F0 INT1F0 b3 b2 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW INT1F1 RW INT2F0 b5 b4 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling RW INT2F1 RW

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12.2.2 INTi Input Filter (i = 0 to 3)

The INTi input contains a digital filter. The sampling clock is selected by the INTiF1 to INTiF0 bits in the INTF register. The IR bit in the INTiIC register is set to 1 (interrupt requested) when the INTi level is sampled for every sampling clock and the sampled input level matches three times. Figure 12.14 shows the Configuration of INTi Input Filter. Figure 12.15 show s Operating Example of INTi Input Filter. Figure 12.14 Configuration of INTi Input Filter Figure 12.15 Operating Example of INTi Input Filter i = 0 to 3 INTiF0, INTiF1: Bits in INTF register INTiEN, INTiPL: Bits in INTEN register = 01b INTi Port direction register(1) Sampling clock Digital filter (input level matches 3x) INTi interrupt = 10b = 11bf32 INTiF1 to INTiF0 INTiEN Other than INTiF1 to INTiF0 = 00b =00b INTiPL = 0 INTiPL = 1 NOTE: 1. INT0: Port P4_5 direction register INT1: Port P1_5 direction register when using P1_5 pin P1_7 direction register when using P1_7 pin INT2: Port P6_6 direction register INT3: Port P6_7 direction register Both Edges Detection Circuit INTi input Sampling timing IR bit in INTiIC register Set to 0 in program NOTE: 1. This is an operation example when the INTiF1 to INTiF0 bits in the INTiF register is set to 01b, 10b, or 11b (passing digital filter). i = 0 to 3

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12.3 Key Input Interrupt

A key input interrupt request is generated by one of the input edges of the K10 to K13 pins. The key input interrupt can be used as a key-on wake-up function to exit wait or stop mode. The KIiEN (i = 0 to 3) bit in the KIEN register can select whether the pins are used as KIi input. The KIiPL bit in the KIEN register can select the input polarity. When inputting “L” to the KIi pin which sets the KIiPL bit to 0 (falling edge), the input of the other K10 to K13 pins are not detected as interrupts. Also, when inputting “H” to the KIi pin which sets the KIiPL bit to 1 (rising edge), the input of the other K10 to K13 pins are not detected as interrupts. Figure 12.16 shows a Block Diagram of Key Input Interrupt. Figure 12.16 Block Diagram of Key Input Interrupt KI3 Pull-up transistor KI2 Pull-up transistor KI3PL = 0 KI3PL = 1 PD1_3 bit KI3EN bit PU02 bit in PUR0 register PD1_3 bit in PD1 register KUPIC register Interrupt control circuit Key input interrupt request KI2PL = 0 KI2PL = 1 PD1_2 bit KI2EN bit KI1 Pull-up transistor KI1PL = 0 KI1PL = 1 PD1_1 bit KI1EN bit KI0 Pull-up transistor KI0PL = 0 KI0PL = 1 PD1_0 bit KI0EN bit KI0EN, KI1EN, KI2EN, KI3EN, KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register

R8C/20 Group, R8C/21 Group 12. Interrupts Rev.2.00 Aug 27, 2008 Page 105 of 458 REJ09B0250-0200 Figure 12.17 KIEN Register Key Input Enable Register(1) Symbol Address After Reset KIEN 00FBh 00h Bit Symbol Bit Name Function RW NOTE: RW KI0 input polarity select bit 0 : Falling edge 1 : Rising edge KI1 input enable bit 0 : Disable 1 : Enable b3 b2 RW KI2EN RW KI1PL KI1 input polarity select bit 0 : Falling edge 1 : Rising edge KI2 input enable bit 0 : Disable 1 : Enable b7 b6 b5 b4 b1 b0 The IR bit in the KUPIC register may be set to 1 (requests interrupt) w hen the KIEN register is rew ritten. Ref er to 12.6.4 Changing Interrupt Sources . KI1EN RW KI3EN KI3 input enable bit KI3PL RW KI2PL KI2 input polarity select bit 0 : Falling edge 1 : Rising edge KI3 input polarity select bit 0 : Falling edge 1 : Rising edge KI0EN RW KI0PL RW KI0 input enable bit 0 : Disable 1 : Enable RW 0 : Disable 1 : Enable

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12.4 Address Match Interrupt

An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i = 0 or 1). This interrupt is used for a break function of the debugger. When using the on-chip debugger, do not set an address match interrupt (the AIER, RMAD0 to RMAD1 registers, and relocatable vector tables) in a user system. Set the starting address of any instruction in the RM ADi register. The AIER0 and AIER1 bits in the AIER0 register can select to enable or disable the interrupt. The I flag and IPL do not affect the address match interrupt. The value of the PC (refer to 12.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when an address match interrupt is acknowle dged varies depending on the instruc tion at the address indicated by the RMADi register (the appropriate return address is not pushed on the stack). When returning from the address match interrupt, return by one of the following:

• Change the content of the stack and use the REIT instruction.
• Use an instruction such as POP to restore the stack as it was before an interrupt request was acknowledged. And then use a jump instruction. Table 12.6 lists the Value of PC Saved to Stack when Address Match Interrupt is Acknowledged. Figure 12.18 shows the Registers AIER and RMAD0 to RMAD1. NOTES: 2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001). Chapter 4. Instruction Code/Number of Cycles contains diagrams showing operation code below each syntax. Operation code is shown in the bold frame in the diagrams. Table 12.6 Value of PC Saved to Stack when Address Match Interrupt is Acknowledged Address Indicated by RMADi Register (i = 0 or 1) PC Value Saved(1)
• Instruction with 2-byte operation code(2)
• Instruction with 1-byte operation code(2) ADD.B:S #IMM8,dest SUB.B:S #I MM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B: S #IMM8,dest STZ #IMM8,dest STNZ #IMM8,dest S TZX #IMM81,#IMM82,dest CMP .B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (However, dest = A0 or A1) Address indicated by RMADi register + 2 Instructions other than the above Address indicated by RMADi register + 1 Table 12.7 Correspondence Between Address Match Interrupt Sources and Associated Registers Address Match Interrupt Source Address Match Inte rrupt Enable Bit Address Match Interrupt Register Address Match Interrupt 0 AIER0 RMAD0 Address Match Interrupt 1 AIER1 RMAD1

R8C/20 Group, R8C/21 Group 12. Interrupts Rev.2.00 Aug 27, 2008 Page 107 of 458 REJ09B0250-0200 Figure 12.18 Registers AI ER and RMAD0 to RMAD1 Address Match Interrupt Enable Register Symbol Address After Reset AI E R 0013h 00h Bit Symbol Bit Name Function RW (b7-b2) —N othing is assigned. I f necessary, set to 0. When read, the content is 0. b7 b6 b5 b4 0 : Disable 1 : Enable RW b3 b2 b1 b0 Address match interrupt 0 enable bit 0 : Disable 1 : Enable RW AI E R 1 Address match interrupt 1 enable bit AI E R 0 Address Match Interrupt Register i (i = 0 or 1) Symbol Address After Reset RMA D0 0012h-0010h 000000h RMA D1 0016h-0014h 000000h Setting Range RW (b16) (b19) (b23) RW (b7-b4) Nothing is assigned. If necessary, set to 0. When read, the content is 0. Address setting register for address match interrupt (b15) (b8) b0 b7 00000h to FFFFFh Function

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12.5 Timer RD Interrupt, Clock Synchronous Se rial I/O with Chip Select Interrupts

and I2C bus Interface Interrupts (Interrupt s with Multiple Interrupt Request Sources) Timer RD (channel 0), timer RD (channel 1), clock synchronous serial I/O with chip select and I 2C bus interface have several interrupt request sources and an interrupt request is gene rated by the logical OR of several interrupt request sources and the logical OR is reflected in the IR bit in the interrupt control register. Therefore, these peripheral functions which have the status register of its own interrupt request sources (status register) and the enable register of the interrupt requ est sources (enable register) control th e generations of the interrupt request (change of the IR bit in the interrupt control register). Table 12.8 lists the Regist ers Associated with Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupt, and I 2C bus Interface Interrupt and Figure 12.19 shows the Block Diagram of Timer RD Interrupt. Figure 12.19 Block Diagram of Timer RD Interrupt Table 12.8 Registers Associated with Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupt, and I2C bus Interface Interrupt Status Register of Interrupt Request Source Enable Register of Interrupt Request Source Interrupt Control Register Timer RD Channel 0 TRDSR0 TRDIER0 TRD0IC Channel 1 TRDSR1 TRDIER1 TRD1IC Clock Synchronous Serial I/O with Chip Select SSSR SSER SSUIC I2C Bus Interface ICSR ICIER IICIC Timer RD (channel i) Interrupt request (IR bit in TRDiIC register) IMFA bit IMIEA bit IMFB bit IMIEB bit IMFC bit IMIEC bit IMFD bit IMIED bit UDF bit OVF bit OVIE bit i = 0 or 1 IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register Channel i

R8C/20 Group, R8C/21 Group 12. Interrupts Rev.2.00 Aug 27, 2008 Page 109 of 458 REJ09B0250-0200 Controlling an interrupt with the I flag, IR bit, ILVL0 to ILVL2 bits and IPL by Timer RD (channel 0), Timer RD (channel 1), clock synchronous serial I/O with chip select and I 2C bus interface is the same as that by other maskable interrupts. However, since an interrupt source is generated based on multiple interrupt request sources, there are the following differences from other maskable interrupts:

• When bits in the enable register corresponding to set b its in the status register to 1 are set to 1 (enable interrupt), the IR bit in the interrupt control register is set to 1 (interrupt requested).
• When either bits in the status register or bits in the enable register corresponding to bits in the status register, or both of them are set to 0, the IR bit is set to 0 (int errupt not requested). Basically, even though the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be maintained. Also, the IR bit is not set to 0 although 0 is written to the IR bit.
• Since each bit in the status register is not automatically set to 0 ev en if the interrupt is acknowledged. Therefore, the IR bit is not also automatically set to 0 when the interr upt is acknowledged. Set each bit in the status register to 0 in the interrupt routine. Refer to the status register figure how to set each bit in the status register to 0.
• When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is set to 1, the IR bit remains 1.
• When multiple bits in the enable register are set to 1, determine by the status register which request source causes an interrupt. Refer to chapters of each peripheral function ( 14.3 Timer RD , 16.2 Clock Synchronous Serial I/O with Chip Select (SSU) and 16.3 I2C Bus Interface) for the status register and enable register. Refer to 12.1.6 Interrupt Control for the interrupt control register.

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12.6 Notes on Interrupts

12.6.1 Reading Address 00000h

Do not read the address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to 0. If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause a problem that the interrupt is canceled, or an unexpected interrupt is generated.

12.6.2 SP Setting

Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an interrupt is acknowledged before setting any value in the SP, the program may run out of control.

12.6.3 External Interrupt and Key Input Interrupt

Either an “L” level or an “H” level of width shown in the Electrical Characteristic s is necessary for the signal input to the INT0 to INT3 pins and KI0 to KI3 pins regardless of the CPU clocks. For details, refer to Table 20.19 External Interrupt INTi (i = 0 to 3) Input, Table 20.25 External Interrupt INTi (i = 0 to 3) Input.

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12.6.4 Changing Interrupt Sources

The IR bit in the interrupt control register may be se t to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source. In addition, the changes of interrupt sources include al l sources that change the in terrupt sources assigned to individual software interrupt numbers, polarities, and timin g. Therefore, when a mode change of the peripheral functions involves interrupt sources, edge polarities, and timing, Set the IR bit to 0 (no interrupt requested) after the change. Refer to each peripheral function for the interrupts caused by the peripheral functions. Figure 12.20 shows an Example of Procedure for Changing Interrupt Sources. Figure 12.20 Example of Procedure for Changing Interrupt Sources NOTES: 1. Execute the above settings individually. Do not execute two or more settings at once (by one instruction). 2. To prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 of the interrupt whose source is changed. 3. Refer to 12.6.5 Changing Interrupt Control Register Contents for the instructions to be used and usage notes. Interrupt source change Disable interrupts(2, 3) Set the IR bit to 0 (interrupt not requested) using the MOV instruction(3) Change interrupt source (including mode of peripheral function) Enable interrupts(2, 3) Change completed IR bit: The interrupt control register bit of an interrupt whose source is changed.

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12.6.5 Changing Interrupt C ontrol Register Contents

(a) Each interrupt control re gister can only be changed while inte rrupt requests corr esponding to that register are not generated. If interrupt requests may be generated, disable the interrupts before changing the interrupt control register. (b) When changing any interrupt control register after disabling interrupts, be careful with the instructions to be used. When changing any bit other than IR bit If an interrupt request corresponding to that register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and th e interrupt request may be ignored. If this causes a problem, use the following instructions to change the register. Instructions to use: AND, OR, BCLR, BSET When changing IR bit If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction to be used. Therefore, use the MOV instruction to set the IR bit to 0. (c) When disabling interrupts using the I flag, set the I flag accordin g to the following sample programs. Refer to (b) for the change of interrupt control registers in the sample programs. Sample programs 1 to 3 are preventing the I flag from being set to 1 (interrupt enables) before changing the interrupt control register for reasons of the internal bus or the instruction queue buffer. Example 1: Use NOP instruct ions to prevent I flag being set to 1 before interrupt control register is changed INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts Example 2: Use dummy read to have FSET instruction wait INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h MOV .W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use POPC instruction to change I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h POPC FLG ; Enable interrupts

R8C/20 Group, R8C/21 Group 13. Watchdog Timer Rev.2.00 Aug 27, 2008 Page 114 of 458 REJ09B0250-0200 Figure 13.2 Registers OFS and WDC Watchdog Timer Control Register Symbol Address After Reset WDC 000Fh 00X11111b Bit Symbol Bit Name Function RW (b5) Reserved bits Set to 0. When read, the content is undefined. RW RW High-order bits of w atchdog timer b3 b2 b1 b0 (b4-b0) RO b7 b6 b5 b4 RW WDC7 (b6) Reserved bits Set to 0 P rescaler select bit 0 : D ivide-by-16 1 : Divide-by-128 Option Function Select Register(1) Symbol Address Before Shipment OFS 0FFFFh FFh (3) Bit Symbol Bit Name Function RW Reserved bit NOTES: b7 b6 b5 b4 b3 b2 b1 b0 11 1 (b1) Set to 1 RW WDTON Watchdog timer start select bit 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset RW ROMCR ROM code protect disabled bit 0 : ROM code protect disabled 1 : ROMCP1 enabled RW ROMCP1 ROM code protect bit 0 : ROM code protect enabled 1 : ROM code protect disabled RW RW (b5-b4) Reserved bits Set to 1 RW If the block including the OFS register is erased, FFh is set to the OFS register. To use the pow er-on reset, set the LVD1ON bit to 0 (voltage monitor 1 reset enabled after reset). LVD1ON Voltage detection circuit start bit(2) 0 : Voltage monitor 1 reset enabled after reset 1 : Voltage monitor 1 reset disabled after reset RW The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not w rite additions to the OFS register. CSPROINI Count source protect mode after reset select bit 0 : Count source protect mode enabled after reset 1 : Count source protect mode disabled after reset

R8C/20 Group, R8C/21 Group 13. Watchdog Timer Rev.2.00 Aug 27, 2008 Page 115 of 458 REJ09B0250-0200 Figure 13.3 Registers WDTR, WDTS, and CSPR Watchdog Timer Reset Register Symbol Address After Reset WDTR 000Dh Indeterminate RW NOTES: Function When w riting 00h before w riting FFh, the w atchdog timer is reset.(1) The default value of the w atchdog timer is set to 7FFFh w hen count source protection mode is disabled and 0FFFh when count source protection mode is enabled.(2) b7 b0 Do not generate an interrupt betw een 00h and the FFh w ritings. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled), 0FFFh is set to the w atchdog timer. WO Watchdog Timer Start Register Symbol Address After Reset WDTS 000Eh Indeterminate RW WO Function The w atchdog timer starts counting after a w rite instruction to this register. b0b7 Count Source Protection Mode Register Symbol Address After Reset (1) CSPR 001Ch 00h Bit Symbol Bit Name Function RW NOTES: (b6-b0) RW Write 0 before w riting 1 to set the CSPRO bit to 1. 0 cannot be set by a program. When w riting 0 to the CSPROINI bit in the OFS register, the value after reset is set to 10000000b. Reserved bits Set to 0 b3 b2 b1 b0b7 b6 b5 b4 RW 0000 CSPRO Count source protection mode select bit(2) 0 : Count source protection mode disabled 1 : Count source protection mode enabled

R8C/20 Group, R8C/21 Group 13. Watchdog Timer Rev.2.00 Aug 27, 2008 Page 116 of 458 REJ09B0250-0200

13.1 Count Source Protect ion Mode Disabled

The count source of the watchdog timer is the CPU clock when count source protection mode is disabled. Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled). NOTES: 1. The watchdog timer is reset when writing 00h to the WDTR register before writing FFh. The prescaler is reset after the MCU is reset. Some errors occur by the prescaler for the period of the watchdog timer. 2. The WDTON bit cannot be changed by a program. When setting the WDTON bit, write 0 to the bit 0 of the address 0FFFFh using a flash programmer. Table 13.2 Watchdog Timer Specifications (with Count Source Protection Mode Disabled) Item Specification Count Source CPU clock Count Operation Decrement Period Division ratio of prescaler(n) x count value of watchdog timer(32768) (1) CPU clock n: 16 or 128 (selected by WDC7 bit in WDC register) e.g.When the CPU clock is 16 MHz and prescaler is divided by 16, the period is approximately 32.8 ms Count Start Condition The WDTON bit (2) in the OFS register (0FFFFh) selects the operation of watchdog timer after reset

• When the WDTON bit is set to 1 (watchdog timer is in stop state after reset) The watchdog timer and prescaler stop after reset and the count starts by writing to the WDTS register
• When the WDTON bit is set to 0 (watchdog timer starts automatically after exiting) The watchdog timer and prescaler start counting automatically after reset Reset Condition of Watchdog Timer
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow Count Stop Condition Stop and wait modes (inherit the count from the held value after exiting modes) Operation at the Time of Underflow
• When the PM12 bit in the PM1 register is set to 0 Watchdog timer interrupt
• When the PM12 bit in the PM1 register is set to 1 Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)

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13.2 Count Source Protect ion Mode Enabled

The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when the program is out of control, the clock can be supplied to the watchdog timer. Table 13.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled). NOTES: 1. The WDTON bit cannot be changed by a program. When setting the WDTON bit, write 0 to the bit 0 of the address 0FFFFh using a flash programmer. 2. Even if writing 0 to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI bit cannot be changed by a program. When setting the CSPROINI bit, write 0 to the bit 7 of the address 0FFFFh using a flash programmer. Table 13.3 Watchdog Timer Specifications (with Count Source Protection Mode Enabled) Item Specification Count Source Low-speed on -chip oscillator clock Count Operation Decrement Period Count value of watchdog timer (4096) Low-speed on-chip oscillator clock e.g. Period is approximately 32.8 ms when the low-speed on-chip oscillator clock is 125 kHz Count Start Condition The WDTON bit(1) in the OFS register (0FFFFh) selects the operation of the watchdog timer after reset.

• When the WDTON bit is set to 1 (watchdog timer is in stop state after reset) The watchdog timer and prescaler stop after reset and the count starts by writing to the WDTS register
• When the WDTON bit is set to 0 (watchdog timer starts automatically after reset) The watchdog timer and prescaler start counting automatically after reset Reset Condition of Watchdog Timer
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow Count Stop Condition None (the count does not st op in wait mode after the count starts. The MCU does not enter stop mode) Operation at the Time of Underflow Watchdog timer reset (refer to 5.5 Watchdog Timer Reset) Register, Bit • When setting the CSPPRO bit in the CSPR register to 1 (count source protection mode is enabled) (2), the following are set automatically - Set 0FFFh to the watchdog timer - Set the CM14 bit in the CM1 register to 0 (low-speed on-chip oscillator on) - Set the PM12 bit in the PM1 register to 1 (The watchdog timer is reset when watchdog timer underflows)
• The following states are held in count source protection mode - Writing to the CM10 bit in the CM1 register disables (It remains unchanged even if it is set to 1. The MCU does not enter stop mode) - Writing to the CM14 bit in the CM1 register disables (It remains unchanged even if it is set to 1. The low-speed on-chip oscillator does not stop)

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 118 of 458 REJ09B0250-0200 14. Timers The MCU contains two 8-bit timers with 8-bit prescaler, two 16-bit timers, and a timer with a 4-bit counter, and an 8- bit counter. The two 8-bit timers with the 8-bit prescaler contain timer RA and timer RB. These timers contain a reload register to memorize the default value of the counter. The 16-bit timer is timer RD which contains the input capture and output compare. The 4 and 8-bit counters are timer RE which contains the outp ut compare. All these timers operate independently. Table 14.1 lists Functional Comparison of Timers.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 119 of 458 REJ09B0250-0200 NOTE: 1. The underflow interrupt can be set to channel 1. Table 14.1 Functional Comparison of Timers Item Timer RA Timer RB Timer RD Timer RE Configuration 8-bit timer with 8-bit prescaler (with reload register) 8-bit timer with 8-bit prescaler (with reload register) 16-bit free-run timer X 2 (with input capture and output compare) 4-bit counter 8-bit counter Count Decrement Decrement Increment / Decrement Increment Count Sources • f1

• f 2
• f 8
• fOCO
• f 1
• f 2
• f 8
• T i m e r R A underflow
• f 1
• f 2
• f 4
• f 8
• f 3 2
• f O C O 4 0 M
• TRDIOA0
• f 4
• f 8
• f 3 2 Function Timer mode provided provided provided (input capture function, output compare function) not provided Pulse output mode provided not pr ovided not provided not provided Event counter mode provided not provided not provided not provided Pulse width measurement mode provided not provided not provided not provided Pulse period measurement mode provided not provided not provided not provided Programmable waveform generation mode not provided provided no t provided not provided Programmable one- shot generation mode not provided provided no t provided not provided Programmable wait one-shot generation mode not provided provided no t provided not provided Input capture mode not provided not provided provided not provided Output compare mode not provided not provided provided provided PWM mode not provided not provided provided not provided Reset synchronized PWM mode not provided not provided provided not provided Complementary PWM mode not provided not provided provided not provided PWM3 mode not provided not pr ovided provided not provided Input Pin TRAIO INT0 INT0, TRDCLK TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 Output Pin TRAO TRAIO TRBO TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 TREO Related Interrupt Timer RA int INT1 int Timer RB int INT0 int Compare match / input capture A0 to D0 int Compare match / input capture A1 to D1 int Overflow int Underflow int (1) INT0 int Timer RE int Timer Stop provided provided provided provided

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14.1 Timer RA

Timer RA is an 8-bit timer with an 8-bit prescaler. The prescaler and timer consist of the re load register and counter. The reload register and counter are allocated at the same address. When accessing the TRAPRE and TRA registers, the reload register and counter can be accessed (refer to Table 14.2 to 14.6 the Specification of Each Modes). The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting and reloading. Figure 14.1 shows the Block Diagram of Timer RA. Figures 14.2 to 14.4 show the registers associated with Timer RA. Timer RA contains five operation modes listed as follows:

• Timer mode: The timer counts an internal count source.
• Pulse output mode: The timer counts an internal count source and outputs the pulses which invert the polarity by underflow of the timer.
• Event counter mode: The timer counts external pulses.
• Pulse width measurement mode: The timer measures the pulse width of an external pulse.
• Pulse period measurement mode: The timer measures the pulse period of an external pulse. Figure 14.1 Block Diagram of Timer RA TCSTF bit TCKCUT bit = 000b = 001b = 011bf2 = 010bfOCO TCK2 to TCK0 bit Counter Reload register TRAPRE register (Prescaler) Peripheral data bus Timer RA interrupt Write to TRAMR register Write to TSTOP bit 1 TCSTF, TSTOP: TRACR register TEDGSEL, TOPCR, TOENA, TIOSEL, TIPF1, TIPF0: TRAIOC register TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: TRAMR register Toggle flip-flop Q Q CLR CK TOENA bit TRAO pin INT1/TRAIO (P1-5) pin TMOD2 to TMOD0 = 011b or 100b Polarity switching Digital filter Counter Reload register TRA register (Timer) TIPF1 to TIPF0 bit = 00b = 10bf8 = 11bf32 TIOSEL = 0 TIOSEL = 1 Count control circle TMOD2 to TMOD0 = 001b TOPCR bit Underflow signal Measurement completion signal TIPF1 to TIPF0 bit = Except 00b = 00b INT1/TRAIO (P1-7) pin TEDGSEL = 1 TEDGSEL = 0 TMOD2 to TMOD0 = Except 010b TMOD2 to TMOD0 = 010b

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 121 of 458 REJ09B0250-0200 Figure 14.2 Registers TRACR and TRAIOC Timer RA Control Register(4) Symbol Address After Reset TRACR 0100h 00h Bit Symbol Bit Name Function RW NOTES: RW TCSTF When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TRAPRE and TRA are set to the values after a reset. 0 : Stops counting 1 : Counting N othing is assigned. I f necessary, set to 0. When read, the content is 0. N othing is assigned. I f necessary, set to 0. When read, the content is 0. RO (b7-b6) — Ref er to 14.1.6 Notes on Timer RA . RWTimer RA underflow flag(3,5) 0 : No underflow 1 : Underflow b3 b2 When this bit is set to 1, the count is forcibly stopped. When read, the content is 0. (b3) b1 b0b7 b6 b5 b4 RW TUNDF Timer RA count start bit(1) Timer RA count forcible stop bit(2) Active edge reception flag (3,5) TSTA RT In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them. Set to 0 in timer mode, pulse output mode, and event counter mode. Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains unchanged w hen 1 is w ritten. 0 : Stops counting 1 : Starts counting Timer RA count status flag(1) TSTOP RW TEDGF 0 : Active edge not received 1 : Active edge received (end of measurement period) Timer RA I/O Control Register Symbol Address After Reset TRAIOC 0101h 00h Bit Symbol Bit Name Function RW RW TIPF0 TOENA RW TRAIO input filter select bits TIPF1 RW RW Function varies depending on operation mode TEDGSEL RW TOPCR RW TRAIO polarity sw itch bit N othing is assigned. I f necessary, set to 0. When read, the content is 0. (b7-b6) TRAIO output control bit INT1 /TR AI O select bit TRAO output enable bit b7 b6 b5 b4 b3 b2 TIOSEL b1 b0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 122 of 458 REJ09B0250-0200 Figure 14.3 Registers TRAMR and TRAPRE Timer RA Mode Register(1) Symbol Address After Reset TRAMR 0102h 00h Bit Symbol Bit Name Function RW NOTE: RW TCK0 RW When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register. RW Tim er R A count source cutoff bit 0 : Provides count source 1 : Cuts off count source TCK2 RW TMOD1 RW TMOD0 Timer RA operation mode select bits b2 b1 b0 0 0 0 : Timer mode 0 0 1 : Pulse output mode 0 1 0 : Event counter mode 0 1 1 : Pulse w idth measurement mode 1 0 0 : Pulse period measurement mode 1 0 1 : 1 1 0 : Do not set 1 1 1 : b7 b6 b5 b4 RW Tim er R A count source select bits b6 b5 b4 0 0 0 : f1 0 0 1 : f8 0 1 0 : fOCO 0 1 1 : f2 1 0 0 : 1 0 1 : Do not set 1 1 0 : 1 1 1 : Nothing is assigned. If necessary, set to 0. When read, the content is 0. TMOD2 RW TCKCUT TCK1 b3 b2 (b3) b1 b0 Timer RA Prescaler Register Symbol Address After Reset TRA PRE 0103h FFh (1) Mode Function Setting Range RW NOTE: 1. When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh. Event Counter Mode Counts an external count source 00h to FFh RW Counts an internal count source 00h to FFh RW Puls e Per iod Measurement Mode Counts an internal count source Pulse Output Mode RWCounts an internal count source 00h to FFh RWCounts an internal count source 00h to FFh 00h to FFh RW Pulse Width Measurement Mode Timer Mode

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 123 of 458 REJ09B0250-0200 Figure 14.4 TRA Register Timer RA Register Symbol Address After Reset TRA 0104h FFh (1) Mode Function Setting Range RW NOTE: 00h to FFh When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh. All Modes Counts of an underflow of the TRAPRE register RW

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14.1.1 Timer Mode

In this mode, the timer counts an in ternally generated count source (see Table 14.2 Timer Mode Specifications). Figure 14.5 shows the TRAIOC Register in Timer Mode. Figure 14.5 TRAIOC Register in Timer Mode Table 14.2 Timer M ode Specifications Item Specification Count Sources f1, f2, f8, fOCO Count Operations • Decrement

• When the timer underflows, the contents in the reload register is reloaded and the count is inherited Divide Ratio 1/(n+1)(m+1) n: setting value of TRAPRE register, m: setting value of TRA register Count Start Condition Write 1 (count starts ) to the TSTART bit in the TRACR register Count Stop Conditions • Write 0 (count stops) to the TSTART bit in the TRACR register
• Write 1 (count forcibly stops) to the TSTOP bit in the TRACR register Interrupt Request Generation Timing When Timer RA underflows [Timer RA interrupt] INT1 /TRAIO Pin Function Programmable I/O port or INT1 interrupt input TRAO Pin Function Programmable I/O port Read from Timer The count value can be read by reading the TRA and TRAPRE registers Write to Timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). Timer RA I/O Control Register Symbol Address After Reset TRAIOC 0101h 00h Bit Symbol Bit Name Function RW INT1/ TRAIO select bit 0 : INT1 /TRAIO pin (P1_7) 1 : INT1 /TRAIO pin (P1_5) b3 b2 TIOSEL b1 b0 b7 b6 b5 b4 Nothing is assigned. If necessary, set to 0. When read, the content is 0. 00 0 (b7-b6) TEDGSEL TRAO output enable bit TRAIO input filter select bits TOPCR RW TOENA RW RW TIPF0 TIPF1 RW RW Set to 0 in timer mode RWTR AI O polarity sw itch bit TRAIO output control bit Set to 0 in timer mode

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14.1.1.1 Timer Write Control during Count Operation

Timer RA has a prescaler and a time r (which counts the prescaler unde rflows). The prescaler and timer each consist of a reload register and a coun ter. When writing to the prescaler or timer, values are written to both the reload register and counter. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed. Figure 14.6 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count Operation. Figure 14.6 Operating Example of Timer RA when Counter Value is Rewritten during Count Operation Count source Reloads register of timer RA prescaler IR bit in TRAIC register 0 Counter of timer RA prescaler Reloads register of timer RA Counter of timer RA Set 01h to the TRAPRE register and 25h to the TRA register by a program. After writing, the reload register is written to at the first count source. Reload at second count source Reload at underflow After writing, the reload register is written to at the first underflow.Reload at the second underflow The IR bit remains unchanged until underflow is generated by a new value. 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h New value (01h)Previous value New value (25h)Previous value 03h 24h 02h 25h The above applies under the following conditions. Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count).

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14.1.2 Pulse Output Mode

Pulse output mode is mode to count the count source internally generated and outputs the pulse which inverts the polarity from the TRAIO pin each time the timer underflows (see Table 14.3 Pulse Output Mode Specifications). Figure 14.7 shows the TRAIOC Register in Pulse Output Mode. NOTE: 1. The level of output pulse turn into the level w hen the pulse output starts by writing the TRAMR register. Table 14.3 Pulse Output Mode Specifications Item Specification Count Sources f1, f2, f8, fOCO Count Operations • Decrement

• When the timer underflows, the contents in the reload register is reloaded and the count is inherited Divide Ratio 1/(n+1)(m+1) n: setting value of TRAPRE register, m: setting value of TRA register Count Start Condition Write 1 (count starts) to the TSTART bit in the TRACR register Count Stop Conditions • Write 0 (count stops) to the TSTART bit in the TRACR register
• Write 1 (count forcibly stops) to the TSTOP bit in the TRACR register Interrupt Request Generation Timing When timer RA underflows [timer RA interrupt] INT1/TRAIO Pin Function Pulse output, programmable output port, or INT1 interrupt(1) TRAO Pin Function Programmable I/O port or inverted output of TRAIO(1) Read from Timer The count value can be read by reading the TRA and TRAPRE registers Write to Timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). Select Functions • TRAIO output polarity switch function The TEDGSEL bit in the TRAIOC register can select the polarity level when the pulse output starts(1)
• Inverted pulse output function The pulse which inverts the polarity of the TRAIO output can be output from the TRAO pin (selected by the TOENA bit in the TRAIOC register)
• Pulse output stop function The pulse output from the TRAIO pin can be stopped by the TOPCR bit.
• I N T 1/TRAIO pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 127 of 458 REJ09B0250-0200 Figure 14.7 TRAIOC Register in Pulse Output Mode Timer RA I/O Control Register Symbol Address After Reset TRAIOC 0101h 00h Bit Symbol Bit Name Function RW INT1 /TRAIO select bit 0 : INT1 /TRAIO pin (P1_7) 1 : INT1 /TRAIO pin (P1_5) RW RW 0 : TRAIO output 1 : Port P1_7 or P1_5 Nothing is assigned. If necessary, set to 0. When read, the content is 0. TRAO output enable bit TRAIO input filter select bits Set to 0 in pulse output mode TEDGSEL RWTR AI O polarity sw itch bit TIPF1 (b7-b6) — TOPCR RW TOENA RW RW TIPF0 TRAIO output control bit b7 b6 b5 b4 b3 b2 0 : Port P3_0 1 : TRAO output (Inverted TRAIO output from P3_0) TIOSEL b1 b0 0 : TRAIO output starts at “H” 1 : TRAIO output starts at “L”

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14.1.3 Event Counter Mode

Event counter mode is mode to count an external signal which inputs from the INT1 /TRAIO pin (see Table 14.4 Event Counter Mode Specifications). Figure 14.8 shows the TRAIOC Register in Event Counter Mode. NOTE: 1. The level of output pulse turn into the level w hen the pulse output starts by writing the TRAMR register. Table 14.4 Event Counter Mode Specifications Item Specification Count Source External signal which is input to TRAIO pin (active edge is selectable by a program) Count Operations • Decrement

• When the timer underflows, the contents in the reload register is reloaded and the count is inherited Divide Ratio 1/(n+1)(m+1) n: setting value of TRAPRE register, m: setting value of TRA register Count Start Condition Write 1 (count starts) to the TSTART bit in the TRACR register Count Stop Conditions
• Write 0 (count stops) to the TSTART bit in the TRACR register
• Write 1 (count forcibly stops) to the TSTOP bit in the TRACR register Interrupt Request Generation Timing When timer RA underflows [timer RA interrupt] INT1 /TRAIO Pin Function Count source input (INT1 interrupt input) TRAO Pin Function Programmable I/O port(1) Read from Timer The count value can be read by reading the TRA and TRAPRE registers Write to Timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). Select Functions •I N T 1 input polarity switch function The TEDGSEL bit in the TRAIOC register can select the active edge of the count source.
• Count source input pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Pulse output function The pulse which inverts the polarity can be output from the TRAO pin each time the timer underflows. (selected by the TOENA bit in the TRAIOC register)(1)
• Digital filter function Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter and select the sampling frequency.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 129 of 458 REJ09B0250-0200 Figure 14.8 TRAIOC Register in Event Counter Mode Timer RA I/O Control Register Symbol Address After Reset TRAIOC 0101h 00h Bit Symbol Bit Name Function RW INT1 /TRAI O select bit 0 : I N T1 /TRAIO pin (P1_7) 1 : INT1 /TRAIO pin (P1_5) NOTE: When the same value from the TRAIO pin is sampled three times continuously, the input is determined. TRAIO output control bit Set to 0 in event counter mode Nothing is assigned. If necessary, set to 0. When read, the content is 0. TRAO output enable bit TRAIO input filter select bits(1) b5 b4 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 samplingTIPF1 (b7-b6) RW TEDGSEL RW TRAIO polarity sw itch bit RW TIPF0 RW TOPCR RW b3 b2b7 b6 b5 b4 0 : Port P3_0 1 : TRAO output TIOSEL b1 b0 0 : Starts counting at rising edge of the TRAIO input or TRAIO starts output at “L” 1 : Starts counting at falling edge of the TRAIO input or TRAIO starts output at “H” TOENA

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 130 of 458 REJ09B0250-0200

14.1.4 Pulse Width Measurement Mode

Pulse width measurement mode is mode to measure the pulse width of an external signal which inputs from the INT1 /TRAIO pin (see Table 14.5 Pulse Width Measurement Mode Specifications). Figure 14.9 shows the TRAIOC Register in Pulse Width Measurement Mode and Figure 14.10 shows the Operating Example of Pulse Width Measurement Mode. Table 14.5 Pulse Width Measurement Mode Specifications Item Specification Count Sources f1, f2, f8, fOCO Count Operations • Decrement

• Continuously counts the selected signal only when measurement pulse is “H” level, or conversely only “L” level.
• When the timer underflows, the contents in the reload register is reloaded and the count is inherited Count Start Condition Write 1 (count starts ) to the TSTART bit in the TRACR register Count Stop Conditions • Write 0 (count stops) to the TSTART bit in the TRACR register
• Write 1 (count forcibly stops) to the TSTOP bit in the TRACR register Interrupt Request Generation Timing
• When timer RA underflows [timer RA interrupt]
• Rising or falling of the TRAIO input (end of measurement period) [timer RA interrupt] INT1 /TRAIO Pin Function Measurement pulse input (INT1 interrupt input) TRAO Pin Function Programmable I/O port Read from Timer The count value can be read by reading the TRA and TRAPRE registers. Write to Timer • When registers TRAPRE and TR A are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). Select Functions • Measurement level select The TEDGSEL bit in the TRAIOC register can select during “H” or “L” level
• Measurement pulse input pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter and select the sampling frequency.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 131 of 458 REJ09B0250-0200 Figure 14.9 TRAIOC Register in Pulse Width Measurement Mode Timer RA I/O Control Register Symbol Address After Reset TRAIOC 0101h 00h Bit Symbol Bit Name Function RW INT1 /TRAIO select bit 0 : INT1 /TRAIO pin (P1_7) 1 : INT1 /TRAIO pin (P1_5) NOTE: RW RW When the same value from the TRAIO pin is sampled three times continuously, the input is determined. b3 b2 TIOSEL b1 b0 0 : TRAIO input starts at “L” 1 : TRAIO input starts at “H” b7 b6 b5 b4 TOPCR RW TOENA RW RW TIPF0 TRAIO output control bit TEDGSEL RWTRAIO polarity sw itch bit TIPF1 (b7-b6) Nothing is assigned. If necessary, set to 0. When read, the content is 0. TRAO output enable bit TRAIO input filter select bits(1) b5 b4 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling Set to 0 in pulse w idth measurement mode

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 132 of 458 REJ09B0250-0200 Figure 14.10 Operating Example of Pulse Width Measurement Mode FFFFh n 0000h Content of counter (hex) n = high-level: the contents of TRA register, low-level: the contents of TRAPRE register Count start Count stop Underflow Period TSTART bit in TRACR register Measurement pulse (TRAIO pin input) TEDGF bit in TRACR register TUNDF bit in TRACR register The above applies under the following conditions.

• “H” level width of measured pulse is measured. (TEDGSEL = 1)
• TRAPRE = FFh Set to 1 by program IR bit in TRAIC register Set to 0 by program Count stop Count start Set to 0 when interrupt request is acknowledged, or set by program Count start Set to 0 by program

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 133 of 458 REJ09B0250-0200

14.1.5 Pulse Period Measurement Mode

Pulse period measurement mode is m ode to measure the pulse period of an external signal which inputs from the INT1/TRAIO pin (see Table 14.6 Pulse Period Measurement Mode Specifications). Figure 14.11 shows the TRAIOC Register in Pulse Period Measurement Mode and Figure 14.12 shows the Operating Example of Pulse Period Measurement Mode. NOTE: 1. Input the pulse whose period is longer than twice of the timer RA prescaler period. Input the longer pulse for “H” width and “L” width than the timer RA prescaler period. If the shorter pulse than the period is input to the TRAIO pin, the input may be disabled. Table 14.6 Pulse Period Measurement Mode Specifications Item Specification Count Sources f1, f2, f8, fOCO Count Operations • Decrement

• After an active edge of measurement pulse is input, contents for the read-out buffer are retained at the first underflow of timer RA prescaler. Then timer RA reloads contents in the reload register at the second underflow of timer RA prescaler and continues counting. Count Start Condition Write 1 (count start) to the TSTART bit in the TRACR register Count Stop Conditions • Write 0 (count stop ) to TSTART bit in the TRACR register
• Write 1 (count forcibly stops) to the TSTOP bit in the TRACR register Interrupt Request Generation Timing
• When timer RA underflows or reloads [timer RA interrupt]
• Rising or falling of the TRAIO input (end of measurement period) [timer RA interrupt] INT1 /TRAIO Pin Function Measurement pulse input(1) (INT1 interrupt input) TRAO Pin Function Programmable I/O port Read from Timer The count value can be re ad by reading the TRA and TRAPRE registers. Write to Timer • When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). Select Functions • Measurement level select The TEDGSEL bit in the TRAIOC register can select the measurement period of input pulse.
• Measurement pulse input pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter and select the sampling frequency.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 134 of 458 REJ09B0250-0200 Figure 14.11 TRAIOC Register in Pulse Period Measurement Mode Timer RA I/O Control Register Symbol Address After Reset TRAIOC 0101h 00h Bit Symbol Bit Name Function RW INT1 /TRAIO select bit 0 : INT1 /TRAIO pin (P1_7) 1 : INT1 /TRAIO pin (P1_5) NOTE: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined. b3 b2 TIOSEL b1 b0 0 : Measures measurement pulse from one rising edge to next rising edge 1 : Measures measurement pulse from one falling edge to next falling edge b7 b6 b5 b4 RW TRAIO polarity sw itch bit TOPCR RW TOENA RW RW TIPF0 TRAO output enable bit TRAIO input filter select bits(1) b5 b4 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling TEDGSEL TRAIO output control bit Set to 0 in pulse period measurement mode RW RWTIPF1 (b7-b6) Nothing is assigned. If necessary, set to 0. When read, the content is 0.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 135 of 458 REJ09B0250-0200 Figure 14.12 Operating Example of Pulse Period Measurement Mode Underflow signal of timer RA prescaler NOTES: 1. The contents of the read-out buffer can be read when the TRA register is read in pulse period measurement mode. 2. After an active edge of measurement pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer RA prescaler underflows for the second time. 3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge found). The content in the read-out buffer is retained until the TRA register is read. If the TRA register is not read before the next active edge is input, the measured result of the previous period is retained. 4. When set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the TUNDF bit in the TRACR register. 5. When set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit. 6. The TUNDF and TEDGF bits are both set to 1 if the timer RA underflows and reloads on an active edge simultaneously. 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh 01h 00h 0Fh 0Eh0Fh 0Dh0Fh 0Bh 0Ah 0Dh 01h 00h 0Fh 0Eh09h TSTART bit in TRACR register TEDGF bit in TRACR register Measurement pulse (TRAIO pin input) Contents of TRA Contents of read-out buffer(1) IR bit in TRAIC register TUNDF bit in TRACR register Set to 1 by program Starts counting TRA reloads TRA read(3) Retained (4) (2) (2) Set to 0 by program (5) (6) Conditions: A period from one rising edge to the next rising edge of measurement pulse is measured (TEDGSEL = 0) with the default value of the TRA register as 0Fh. 0Eh TRA reloads Retained Set to 0 when interrupt request is acknowledged, or set by program Set to 0 by program

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14.1.6 Notes on Timer RA

• Timer RA stops counting after reset. Set the value to timer RA and timer RA prescaler before the count starts.
• Even if the prescaler and timer RA is read out in 16-bit units, these registers are read by 1 byte in the MCU. Consequently, the timer value may be updated during the period these two registers are being read.
• In pulse width measurement mode and pulse period measurement mode, the TEDGF and TUNDF bits in the TRACR register can be set to 0 by writing 0 to th ese bits by a program. However, these bits remain unchanged when 1 is written. When using the READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 alth ough these bits are set to 1 while the instruction is executed. At the time, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
• When changing to pulse width measurement mode and pulse period measurement mode from other mode, the contents of the TEDGF and TUNDF bits are in determinate. Write 0 to the TEDGF and TUNDF bits before the count starts.
• The TEDGF bit may be set to 1 by timer RA prescaler underflow which is generated for the first time since the count starts.
• When using the pulse peri od measurement mode, leave two periods or more of timer RA prescaler immediately after count starts, and set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1 (count starts) while the count stops. During this time, do not access re gisters associated with timer RA (1) other than the TCSTF bit. Timer RA starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count). The TCSTF bit retains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is performing. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA (1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, TRA
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval.

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14.2 Timer RB

Timer RB is an 8-bit timer with an 8-bit prescaler. The prescaler and timer consist of the re load register and counter. (Refer to Table 14.7 to 14.10 the Specification of Each Modes). Timer RB contains the timer RB primary and timer RB secondary as the reload register. The count source for timer RB is the opera ting clock that regulates the timing of timer operations such as counting and reloading. Figure 14.13 shows the Block Diagram of Timer RB. Figur es 14.14 and 14.16 show the registers associated with timer RB. Timer RB contains four operation modes listed as follows:

• Timer mode: The timer counts an internal count source (peripheral function clock or timer RA underflows).
• Programmable waveform generation mode: The time r outputs pulses of a given width successively.
• Programmable one-shot generation mode: The timer outputs one-shot pulse.
• Programmable wait one-shot generation mode: The timer outputs delayed one-shot pulse. Figure 14.13 Block Diagram of Timer RB INT0PL bit = 00b = 01b = 11b = 10bTimer RA underflow TCK1 to TCK0 bit TSTART bit TRBPRE register (Prescaler) Timer RB interrupt INT0 interrupt TCSTF bit Toggle flip-flop Q Q CLR CK TOPL = 1 TOPL = 0 TRBO pin TOCNT = 0 TOCNT = 1 P3_1 bit in P3 register TMOD1 to TMOD0 bit = 10b or 11b TOSSTF bit Polarity select INOSEG bit Input polarity selected to be one edge or both edges Digital filterINT0 pin INT0EN bitTMOD1 to TMOD0 bit = 01b, 10b, 11b TMOD1 to TMOD0 bit = 01b, 10b, 11b Counter Reload register Counter (timer RB) Reload register TRBPR register Peripheral data bus TRBSC register Reload register TCKCUT bit INOSTG bit TSTART, TCSTF: TRBCR register TOSST: TRBOCR register TOPL, TOCNT, INOSTG, INOSEG: TRBIOC register TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: TRBMR register (Timer)

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 138 of 458 REJ09B0250-0200 Figure 14.14 Registers TRBCR and TRBOCR Timer RB Control Register Symbol Address After Reset TRBCR 0108h 00h Bit Symbol Bit Name Function RW NOTES: 3. Indicates that count operation is in progress in timer mode or programmable w aveform mode. In programmable one- shot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has been acknow ledged. When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit in the TRBOCR register are set to values after a reset. 0 : Stops counting 1 : Counting(3) Nothing is assigned. If necessary, set to 0. When read, the content is 0. RO (b7-b3) — Timer RB count start bit (1) Timer RB count forcible stop bit(1,2) Ref er to 14.2.5 Notes on Timer RB . TSTART RW TCSTF Timer RB count status flag(1) TSTOP RW b3 b2 When this bit is set to 1, the count is forcibly stopped. When read, the content is 0. b1 b0 0 : Stops counting 1 : Starts counting b7 b6 b5 b4 Timer RB One-Shot Control Register(2) Symbol Address After Reset TRBOCR 0109h 00h Bit Symbol Bit Name Function RW NOTES: Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RB one-shot status flag(1) When 1 is set to the TSTOP bit in the TRBCR register, the TOSSTF bit is set to 0. This register is enabled w hen bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot generation mode) or 10b (programmable w ait one-shot generation mode). RO (b7-b3) — RW RWTimer RB one-shot start bit When this bit is set to 1, the one-shot trigger generated. When read, the content is 0. Timer RB one-shot stop bit When this bit is set to 1, the one-shot pulses (including programmable w ait one-shot pulses) stops. When read, the content is 0. b7 b6 b5 b4 b3 b2 0 : One-shot stopping 1 : One-shot operating (including w ait period) b1 b0 TOSSP TOSSTF TOSST

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 139 of 458 REJ09B0250-0200 Figure 14.15 Registers TRBIOC and TRBMR Timer RB I/O Control Register Symbol Address After Reset TRBIOC 010Ah 00h Bit Symbol Bit Name Function RW TOPL Timer RB output level select bit Timer RB output sw itch bit b7 b6 b5 b4 b3 b2 INOSEG b1 b0 INOSTG TOCNT N othing is assigned. I f necessary, set to 0. When read, the content is 0. One-shot trigger polarity select bit (b7-b4) — Function varies depending on operating mode RW RW RW RW One-shot trigger control bit Timer RB Mode Register Symbol Address After Reset TRBMR 010Bh 00h Bit Symbol Bit Name Function RW NOTES: b3 b2 TWRC b1 b0 (b2) TMOD0 RW TMOD1 RW Timer RB operating mode select bits(1) b1 b0 0 0 : Timer mode 0 1 : Programmable w aveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable w ait one-shot generation mode b7 b6 b5 b4 RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RB w rite control bit(2) 0 : Write to reload register and counter 1 : Write to reload register only The TWRC bit can be set to either 0 or 1 in timer mode. In programmable w aveform generation mode, programmable one-shot generation mode, or programmable w ait one-shot generation mode, the TWRC bit must be set to 1 (w rite to reload register only). TCK0 RW Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT w hen both the TSTART and TCSTF bits in the TRBCR register set to 0 (count stops). RW Timer RB count source cutoff bit(1) 0 : Provides count source 1 : Cuts off count source RWTCKCUT (b6) — Timer RB count source select bits (1) b5 b4 0 0 : f1 0 1 : f8 1 0 : Timer RA underflow 1 1 : f2TCK1 Nothing is assigned. If necessary, set to 0. When read, the content is 0.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 140 of 458 REJ09B0250-0200 Figure 14.16 Registers T RBPRE, TRBSC, and TRBPR Timer RB Prescaler Register(1) Symbol Address After Reset TRBPRE 010Ch FFh Mode Function Setting Range RW NOTE: 1. When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh. Programmable w aveform generation mode RW00h to FFh Programmable one-shot generation mode 00h to FFh RW Programmable w ait one-shot generation mode RW00h to FFhCounts an internal count source or a timer RA underflow 00h to FFh RW Timer mode Timer RB Secondary Register(3,4) Symbol Address After Reset TRBSC 010Dh FFh Mode Function Setting Range RW NOTES: 4. To w rite to the TRBSC register, perform the follow ing steps. (1) Write the value to the TRBSC register. (2) Write the value to the TRBPR register. (If the value does not change, w rite the same value second time.) The count value can be read out by reading the TRBPR register even w hen the secondary period is being counted. Programmable w ait one-shot generation mode Counts a timer RB prescaler underflow (one-shot w idth is counted) 00h to FFh WO (2) Each value in the TRBPR register and TRBSC register is reloaded to the counter alternately and counted. When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh. WO(2)Counts a timer RB prescaler underflow(1) 00h to FFh Programmable one-shot generation mode Disable 00h to FFh — Programmable w aveform generation mode b7 b0 Timer mode —Disable 00h to FFh Timer RB Primary Register(2) Symbol Address After Reset TRBPR 010Eh FFh Mode Function Setting Range RW NOTES: 2. When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh. Programmable w aveform generation mode RWCounts a timer RB prescaler underflow (1) 00h to FFh Programmable one-shot generation mode Counts a timer RB prescaler underflow (one-shot w idth is counted) 00h to FFh RW Each value in the TRBPR register and TRBSC register is reloaded to the counter alternately and counted. Timer mode RWCounts a timer RB prescaler underflow 00h to FFh b7 b0 Programmable w ait one-shot generation mode Counts a timer RB prescaler underflow (w ait period w idth is counted) 00h to FFh RW

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14.2.1 Timer Mode

Timer mode is mode to count a count source which is internally generated or timer RA underflow (see Table 14.7 Timer Mode Specifications). The TRBOCR and TRBSC registers are unused in timer mode. Figure 14.17 shows the TRBIOC Register in Timer Mode. Figure 14.17 TRBIOC Register in Timer Mode Table 14.7 Timer M ode Specifications Item Specification Count Sources f1, f2, f8, Timer RA underflow Count Operations • Decrement

• When the timer underflows, it reloads the reload register contents before the count continues (when timer RB underflows, the contents of timer RB primary reload register is reloaded) Divide Ratio 1 /(n+1)(m+1) n: setting value in TRBPRE register, m: setting value in TRBPR register Count Start Condition Write 1 (count starts) to the TSTART bit in the TRBCR register Count Stop Conditions • Write 0 (count stops) to the TSTART bit in the TRBCR register
• Write 1 (count forcibly stop) to the TSTOP bit in the TRBCR register Interrupt Request Generation Timing When timer RB underflows [timer RB interrupt] TRBO Pin Function Programmable I/O port INT0 Pin Function Programmable I/O port or INT0 interrupt input Read from Timer The count value can be read out by reading the TRBPR and TRBPRE registers Write to Timer • When registers TRBPRE and TRBP R are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written to while count operation is in progress: If the TWRC bit in the TRBMR register is set to 0, the value is written to both the reload register and the counter. If the TWRC bit is set to 1, the value is written to the reload register only. (Refer to 14.2.1.1 Timer Write Control during Count Operation.) Timer RB I/O Control Register Symbol Address After Reset TRBIOC 010Ah 00h Bit Symbol Bit Name Function RW TOPL Timer RB output level select bit Timer RB output sw itch bit b7 b6 b5 b4 b3 b2 INOSEG b1 b0 INOSTG TOCNT N othing is assigned. I f necessary, set to 0. When read, the content is 0. One-shot trigger polarity select bit (b7-b4) — Set to 0 in timer mode RW RW RW RW One-shot trigger control bit

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14.2.1.1 Timer Write Control during Count Operation

Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a co unter. In timer mode, the TWRC bit in the TRBMR register can be used to select whether writing to the prescaler or timer during count operation is performed to both the reload register and counter or only to the reload register. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload register and counter, the counter va lue is not updated immediately after the WRITE instruction is executed. In addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be shifted if the prescaler value changes. Figure 14.18 shows an Operating Example of Timer RB when Counter Value is Rewritten during Count Operation.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 143 of 458 REJ09B0250-0200 Figure 14.18 Operating Example of Timer RB when Counter Value is Rewritten during Count Operation Count source Reloads register of timer RB prescaler IR bit in TRBIC register 0 Counter of timer RB prescaler Reloads register of timer RB Counter of timer RB Set 01h to the TRBPRE register and 25h to the TRBPR register by a program. After writing, the reload register is written with the first count source. Reload with the second count source Reload on underflow After writing, the reload register is written on the first underflow. Reload on the second underflow The IR bit remains unchanged until underflow is generated by a new value. When the TWRC bit is set to 0 (write to reload register and counter) Count source Reloads register of timer RB prescaler IR bit in TRBIC register Counter of timer RB prescaler Reloads register of timer RB Counter of timer RB Set 01h to the TRBPRE register and 25h to the TRBPR register by a program. After writing, the reload register is written with the first count source. Reload on underflow After writing, the reload register is written on the first underflow. Reload on underflow Only the prescaler values are updated, extending the duration until timer RB underflow. When the TWRC bit is set to 1 (write to reload register only) 05h 04h 03h 02h 01h 00h 01h 00h 01h 00h06h 01h 00h 01h 03h 00h 02h 01h 25h New value (25h)Previous value New value (01h)Previous value New value (01h)Previous value 05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h New value (25h)Previous value 03h 24h 02h 25h The above applies under the following conditions. Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).

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14.2.2 Programmable Waveform Generation Mode

Programmable waveform generation mode is mode to invert the signal output from the TRBO pin each time the counter underflows, while the values in the TRBPR and TRBSC registers are counted alternately (see Table 14.8 Programmable Waveform Generation Mode Specifications). A counting starts by counting the setting value in the TRBPR register. The TRBOCR register is unused in this mode. Figure 14.19 shows the TRBIOC Register in Programma ble Waveform Generation Mode. Figure 14.20 shows the Operation Example of Timer RB in Programmable Waveform Generation Mode. NOTES: 1. Even when counting the secondary pe riod, read out the TRBPR register. 2. The set values are reflected to the waveform output beginning with the following primary period after writing to the TRBPR register. 3. The value written to the TOCNT bit is enabled by the following.

• When count starts.
• When the timer RB interrupt request is generated. The contents after the TOCNT bit is changed are reflected from the output of the following primary period. Table 14.8 Programmable Waveform Generation Mode Specifications Item Specification Count Sources f1, f2, f8, timer RA underflow Count Operations • Decrement
• When the timer underflows, it reloads the contents of the primary reload and secondary reload registers alternately before the count continues. Width and Period of Output Waveform Primary period: (n+1)(m+1)/fi Secondary period: (n+1)(p+1)/fi Period: (n+1){(m+1)+(p+1)}/fi fi: Count source frequency n: Setting value in TRBPRE register m: Setting value in TRBPR register p: Setting value in TRBSC register Count Start Condition Write 1 (count start) to the TSTART bit in the TRBCR register Count Stop Conditions
• Write 0 (count stop) to the TSTART bit in the TRBCR register
• Write 1 (count forcibly stop) to the TSTOP bit in the TRBCR register Interrupt Request Generation Timing In half of count source, after timer RB underflows during secondary period (at the same time as the TRBO output change) [timer RB interrupt] TRBO Pin Function Programmable output port or pulse output INT0 Pin Function Programmable I/O port or INT0 interrupt input Read from Timer The count value can be read out by reading the TRBPR and TRBPRE registers(1) Write to Timer • When register s TRBPRE, TRBSC, and TRBPR are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count operation, values are written to the reload registers only.(2) Select Functions • Output level select function The TOPL bit can select the output level during primary and secondary periods.
• TRBO pin output switch function Timer RB pulse output or P3_1 latch output is selected by the TOCNT bit in the TRBIOC register.(3)

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 145 of 458 REJ09B0250-0200 Figure 14.19 TRBIOC Register in Programmable Waveform Generation Mode Timer RB I/O Control Register Symbol Address After Reset TRBIOC 010Ah 00h Bit Symbol Bit Name Function RW b3 b2 INOSEG b1 b0 INOSTG b7 b6 b5 b4 RW TOCNT RW TOPL Timer RB output level select bit 0 : Outputs “H” for primary period Outputs “L” for secondary period Outputs “L” w hen the timer is stopped 1 : Outputs “L” for primary period Outputs “H” for secondary period Outputs “H” w hen the timer is stopped Timer RB output sw itch bit 0 : Outputs timer RB w aveform 1 : Outputs value in P3_1 port latch RW RW One-shot trigger control bit Nothing is assigned. If necessary, set to 0. When read, the content is 0. One-shot trigger polarity select bit (b7-b4) — Set to 0 in programmable w aveform generation mode

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 146 of 458 REJ09B0250-0200 Figure 14.20 Operation Example of Timer RB in Programmable Waveform Generation Mode IR bit in TRBIC register Count source Timer RB prescaler underflow signal Counter of timer RB TRBO pin output TOPL bit in TRBIO register Set to 1 by program Set to 0 when interrupt request is acknowledged, or set by program The above applies to the following conditions. TSTART bit in TRBCR register 01h 00h 02h Timer RB secondary reloads Timer RB primary reloads Set to 0 by program TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin) 02h 01h 00h 01h 00h Primary period Primary period Secondary period Waveform output starts Waveform output inverts Waveform output starts Initial output is the same level as during secondary period.

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14.2.3 Programmable One-shot Generation Mode

Programmable one-shot generation mo de is mode to output the one-shot pulse from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (see Table 14.9 Programmable One-Shot Generation Mode Specifications ). When a trigger is generated, the timer starts operating from the point only once for a given period equal to the set value in th e TRBPR register. The TRBSC register is unused in this mode. Figure 14.21 shows the TRBIOC Register in Program mable One-Shot Generation Mode. Figure 14.22 shows the Operation Example of Programmable One-Shot Generation Mode. NOTES: 1. The set value is reflected at the following one- shot pulse after writing to the TRBPR register. 2. Do not set both the TRBPRE and TRBPR registers to 00h. Table 14.9 Programmable One-Shot Generation Mode Specifications Item Specification Count Sources f1, f2, f8, timer RA underflow Count Operations • Decrement the setting value in the TRBPR register

• When the timer underflows, it reloads the contents of the reload register before the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When a count stops, the timer reloads the contents of the reload register before it stops. One-Shot Pulse Output Time (n+1)(m+1)/fi fi: Count source frequency, n: Setting value in TRBPRE register, m: Setting value in TRBPR register (2) Count Start Conditions
• The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts)
• Input trigger to the INT0 pin Count Stop Conditions
• When reloading completes after Timer RB underflows during primary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops)
• When the TSTART bit in the TRBCR register is set to 0 (stops counting)
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting) Interrupt Request Generation Timing In half cycles of count source, after the timer underflows (at the same time as the TRBO output ends) [timer RB interrupt] TRBO Pin Function Pulse output INT0 Pin Functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled), programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled), external trigger (INT0 interrupt input) Read from Timer The count value can be read out by reading the TRBPR and TRBPRE registers. Write to Timer • When registers TRBPRE and TR BPR are written while the count is stopped, values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written during the count, values are written to the reload register only (the data is transferred to the counter at the following reload)(1) Select Functions • Output level select function The TOPL bit in the TRBIOC register can select the output level of the one-shot pulse waveform.
• One-shot trigger select function Refer to 14.2.3.1 One-Shot Trigger Selection.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 148 of 458 REJ09B0250-0200 Figure 14.21 TRBIOC Register in Programmable One-Shot Generation Mode Timer RB I/O Control Register Symbol Address After Reset TRBIOC 010Ah 00h Bit Symbol Bit Name Function RW 0 : INT0 pin one-shot trigger disabled 1 : INT0 pin one-shot trigger enabled NOTE: RW RW One-shot trigger control bit(1) 0 : Falling edge trigger 1 : Rising edge trigger RW TOCNT RW TOPL Timer RB output level select bit 0 : Outputs one-shot pulse “H” Outputs “L” w hen the timer is stopped 1 : Outputs one-shot pulse “L” Outputs “H” w hen the timer is stopped Timer RB output sw itch bit Set to 0 in programmable one-shot generation mode b7 b6 b5 b4 b3 b2 INOSEG b1 b0 INOSTG Nothing is assigned. If necessary, set to 0. When read, the content is 0. One-shot trigger polarity select bit(1) (b7-b4) — Ref er to 14.2.3.1 One-shot Trigger Selection .

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 149 of 458 REJ09B0250-0200 Figure 14.22 Operation Example of Programmable One-Shot Generation Mode TOSSTF bit in TRBOCR register INT0 pin input IR bit in TRBIC register Count source Timer RB prescaler underflow signal Counter of timer RB TRBIO pin output TOPL bit in TRBIOC register Set to 1 by program Set to 1 by program Set to 0 when interrupt request is acknowledged, or set by program The above applies to the following conditions. TSTART bit in TRBCR register 01h 00h 01h 00h 01h Count starts Timer RB primary reloads Count starts Timer RB primary reloads Set to 0 by program Waveform output starts Waveform output ends Waveform output starts Waveform output ends Set to 0 when counting ends Set to 1 by INT0 pin input trigger TRBPRE = 01h, TRBPR = 01h TRBIOC register TOPL = 0, TOCNT = 0 INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at rising edge)

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14.2.3.1 One-Shot Trigger Selection

In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts). A one-shot trigger can be generated by either of the following causes:

• 1 is written to the TOSST bit in the TRBOCR register by a program.
• Trigger input from the INT0 pin. When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation mode, count operation starts for the wait period.) If a one- shot trigger occurs while the TOSSTF bit is set to 1, no retriggering occurs. To use trigger input from the INT0 pin, input the trigger after making the following settings:
• Set the PD4_5 bit in the PD4 register to 0 (input port).
• Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register.
• Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select falling or rising edge with the INOSEG bit in TRBIOC register.
• Set the INT0EN bit in the INTEN register to 0 (enabled).
• After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger enabled). Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.
• Processing to handle the interrupts is required. Refer to 12. Interrupts for details.
• If one edge is selected, use the POL bit in the INT0 IC register to select falling or rising edge. (The INOSEG bit in the TRBIOC register does not affect INT0 interrupts).
• If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the value of the IR bit in the INT0IC register changes.

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14.2.4 Programmable Wait One-shot Generation Mode

Programmable wait one-shot generation mode is mode to output the one-shot puls e from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (see Table 14.10 Programmable Wait One-Shot Generation Mode Specifications ). When a trigger is generated from this point, the timer starts outputting pulses only once for a given length of time equal to the setting value in the TRBSC re gister after waiting for a given length of time equal to the setting value in the TRBPR register. Figure 14.23 shows the TRBIOC Register in Programm able Wait One-Shot Generation Mode. Figure 14.24 shows the Operation Example of Programmable Wait One-Shot Generation Mode.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 152 of 458 REJ09B0250-0200 NOTES: 1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR. 2. Do not set both the TRBPRE and TRBPR registers to 00h. Table 14.10 Programmable Wait One-Shot Generation Mode Specifications Item Specification Count Sources f1, f2, f8, timer RA underflow Count Operations • Decrement the se tting value in timer RB primary

• When a count of timer RB primary underflows, the timer reloads the contents of the timer RB secondary before the count continues.
• When a count of timer RB secondary underflows, the timer reloads the contents of the timer RB primary before the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When a count stops, the timer reloads the contents of the reload register before it stops. Wait Time (n+1)(m+1)/fi fi: Count source frequency n: Setting value in the TRBPRE register, m: Setting value in the TRBPR register(2) One-Shot Pulse Output Time (n+1)(p+1)/fi fi: Count source frequency n: Setting value in the TRBPRE register, p: Setting value in the TRBSC register Count Start Conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts)
• Input trigger to the INT0 pin Count Stop Conditions • When reloading completes after timer RB underflows during secondary period
• When the TOSSP bit in the TRBOCR register is set to 0 (one-shot stops)
• When the TSTART bit in the TRBCR register is set to 0 (starts counting)
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting) Interrupt Request Generation Timing In half cycles of the count source after timer RB underflows during secondary period (complete at the same time as waveform output from the TRBO pin) [timer RB interrupt] TRBO Pin Function Pulse output INT0 Pin Functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled), programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled), external trigger (INT0 interrupt input) Read from Timer The count value can be read out by reading the TRBPR and TRBPRE registers. Write to Timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count stops, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count operation, values are written to the reload registers only.(1) Select Functions • Output level select function The TOPL bit in the TRBIO register can select the output level of the one-shot pulse waveform.
• One-shot trigger select function Refer to 14.2.3.1 One-Shot Trigger Selection.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 153 of 458 REJ09B0250-0200 Figure 14.23 TRBIOC Register in Progra mmable Wait One-Shot Generation Mode Timer RB I/O Control Register Symbol Address After Reset TRBIOC 010Ah 00h Bit Symbol Bit Name Function RW 0 : INT0 pin one-shot trigger disabled 1 : INT0 pin one-shot trigger enabled NOTE: Nothing is assigned. If necessary, set to 0. When read, the content is 0. One-shot trigger polarity select bit(1) (b7-b4) — Ref er to 14.2.3.1 One-shot Trigger Selection . b3 b2 INOSEG b1 b0 INOSTG b7 b6 b5 b4 RW TOCNT RW TOPL Timer RB output level select bit 0 : Outputs one-shot pulse “H” Outputs “L” w hen the timer is stopped or during w ait 1 : Outputs one-shot pulse “L” Outputs “H” w hen the timer is stopped or during w ait Timer RB output sw itch bit Set to 0 in programmable w ait one-shot generation mode RW RW One-shot trigger control bit (1) 0 : Falling edge trigger 1 : Rising edge trigger

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 154 of 458 REJ09B0250-0200 Figure 14.24 Operation Example of Programmable Wait One-Shot Generation Mode TOSSTF bit in TRBOCR register INT0 pin input IR bit in TRBIC register Count source Timer RB prescaler underflow signal Counter of timer RB TRBIO pin output TOPL bit in TRBIOC register Set to 1 by program Set to 1 by setting 1 to TOSST bit in TRBOCR register, or INT0 pin input trigger Set to 0 when interrupt request is acknowledged, or set by program The above applies to the following conditions. TSTART bit in TRBCR register 01h 00h 00h 01h Count starts Timer RB secondary reloads Timer RB primary reloads Set to 0 by program Wait starts Waveform output starts Waveform output ends Set to 0 when counting ends TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at rising edge) 04h 03h 02h 01h Wait (primary period) One-shot pulse (secondary period)

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14.2.5 Notes on Timer RB

• Timer RB stops counting after reset. Set the value to timer RB and timer RB prescaler before the count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read by 1 byte in the MCU. Consequently, the timer value may be updated during the period these two registers are being read.
• In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the TRBOCR register to 1 (stops one-shot), the timer reload s the value of reload register and stops. Therefore, read the timer count value in programmable one-shot generation mode and programmable wait one-shot generation mode before the timer stops.
• The TCSTF bit retains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1 (count starts) while the count stops. During this time, do not access registers associated with timer RB(1) other than the TCSTF bit. The TCSTF bit retains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is performing. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, TRBPR
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the T RBOCR register, the value of the TOSSTF bit changes after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the period between when the TOSSP bit is written to 1 and when th e TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1.

14.2.5.1 Timer mode

The following workaround should be performed in timer mode. To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points:

• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, al low three or more cycles of the prescaler underflow for each write interval.

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14.2.5.2 Programmable waveform generation mode

The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during c ount operation (TCSTF bit is set to 1), note the following points:

• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. (2) To change registers TRBPRE and TRBPR during coun t operation (TCSTF bit is set to 1), synchronize the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period A shown in Figures 14.25 and 14.26. The following shows the detailed workaround examples.
• Workaround example (a): As shown in Figure 14.25, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These write operations must be completed by the beginning of period A. Figure 14.25 Workaround Example (a) When Timer RB Interrupt is Used TRBO pin output Count source/ prescaler underflow signal Primary period Period A IR bit in TRBIC register Secondary period (b) Interrupt sequence Instruction in interrupt routine Interrupt request is acknowledged(a) Interrupt request is generated Ensure sufficient time Set the secondary and then the primary register immediately (a) Period between interrupt request generation and the completion of execution of an instruction. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 20 cycles. 21 cycles for address match and single-step interrupts.

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• Workaround example (b): As shown in Figure 14.26 detect the start of the primary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A. If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is set to 0 (input mode), the read value indicates the TRBO pin output value. Figure 14.26 Workaround Example (b) When TRBO Pin Output Value is Read (3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case, registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.

14.2.5.3 Programmable one-shot generation mode

The following two workarounds should be performed in programmable one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during c ount operation (TCSTF bit is set to 1), note the following points:

• When the TRBPRE register is written continuously du ring count operation (TCSTF bit is set to 1), allow three or more cycles of the count source for each write interval.
• When the TRBPR register is writte n continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. TRBO pin output Count source/ prescaler underflow signal Primary period Period A Read value of the port register’s bit corresponding to the TRBO pin (when the bit in the port direction register is set to 0) Secondary period (i) The TRBO output inversion is detected at the end of the secondary period. Ensure sufficient time Upon detecting (i), set the secondary and then the primary register immediately. (ii) (iii)

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14.2.5.4 Programmable wait one-shot generation mode

The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during c ount operation (TCSTF bit is set to 1), note the following points:

• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. (3) Set registers TRBSC and TRBP R using the following procedure. (a) To use “INT0 pin one-shot trigger enabled” as the count start condition Set the TRBSC register an d then the TRBPR register. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before trigger input from the INT0 pin. (b) To use “writing 1 to TOSST bit” as the start condition Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the TOSST bit.

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14.3 Timer RD

Timer RD has 2 16-bit timers (channels 0 and 1). Each channel has 4 I/O pins. The operation clock of Timer RD is f1 or fOCO40M. Table 14.11 lists the Timer RD Operation Clocks. Figure 14.27 shows the Block Diagram of Timer RD. Timer RD has 5 modes:

• Timer mode - Input capture function Transfer the counter value to a register as a trigger of the external signal - Output compare function Detect the register value match with a counter (Pin output can be changed at detection) The following 4 modes using the output compare function.
• PWM mode Output any-wide pulse continuously
• Reset synchronous PWM mode Output three-phase waveforms (6) without sawtooth wave modulation and dead time
• Complementary PWM mode Output three-phase waveforms (6) with triangular wave modulation and dead time
• PWM3 mode Output PWM waveform (2) with same period In the input capture function, output compare functi on and PWM mode, Channels 0 and 1 have the equivalent functions, and functions or modes can be selected every pin. Also, a combination of these functions and modes can be used in 1 channel. In reset synchronous PWM mode, complementary PWM mo de and PWM3 mode, a waveform is output with a combination of counters and registers in Channels 0 and 1. Tables 14.12 to 14.20 lists the Pin Functions of timer RD. Table 14.11 Timer RD Operation Clocks Condition Operation Clock of Timer RD The count source is f1, f2, f4, f8, f32 and TRDCLK input. (The TCK2 to TCK0 bits in the TRDCR0 and TRDCR1 registers are set to 000b to 101b.) The count source is fOCO40M. (The TCK2 to TCK0 bits in the TRDCR0 and TRDCR1 registers are set to 110b.) fOCO40M

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 160 of 458 REJ09B0250-0200 X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_0 bit in the PD2 register to 0 (input mode) at time r mode trigger input (input capture function) and external clock input (TRDCLK). X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_1 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function). X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_2 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function). Table 14.12 Pin Functions TRDIOA0/TRDCLK(P2_0) Register TRDOER1 TRDFCR TRDIORA0 Function Bit EA0 PWM3 STCLK CMD1, CMD0 IOA3 IOA2_IOA0 Setting value 0 0 0 00b X XXXb PWM3 mode waveform output 0 1 0 00b 1 001b, 01Xb Timer mode waveform output (output compare function) X 1 0 00b X 1XXb Timer mode trigger input (input capture function)(1) 1 1 XXb X 000b External clock input (TRDCLK)(1) Other than above I/O port Table 14.13 Pin Functions TRDIOB0(P2_1) Register TRDOER1 TRDFCR TRDPMR TRDIORA0 Function Bit EB0 PWM3 CMD1, CMD0 PWMB0 IOB2_IOB0 Setting value 0X 1Xb X XXXb Complementary PWM mode waveform output

0 X 01b X XXXb Reset synchronous PWM mode waveform output

0 0 00b X XXXb PWM3 mode waveform output 0 1 00b 1 XXXb PWM mode waveform output 0 1 00b 0 001b, 01Xb Timer mode waveform output (output compare function) X 1 00b 0 1XXb Timer mode trigger input (input capture function)(1) Other than above I/O port Table 14.14 Pin Functions TRDIOC0(P2_2) Register TRDOER1 TRDFCR TRDPMR TRDIORC0 Function Bit EC0 PWM3 CMD1, CMD0 PWMC0 IOC2_IOC0 Setting value 0X 1Xb X XXXb Complementary PWM mode waveform output 0 1 00b 1 XXXb PWM mode waveform output 0 1 00b 0 001b, 01Xb Timer mode waveform output (output compare function) X 1 00b 0 1XXb Timer mode trigger input (input capture function)(1) Other than above I/O port

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 161 of 458 REJ09B0250-0200 X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_3 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function). X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_4 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function). X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_5 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function). Table 14.15 Pin Functions TRDIOD0(P2_3) Register TRDOER1 TRDFCR TRDPMR TRDIORC0 Function Bit ED0 PWM3 CMD1, CMD0 PWMD0 IOD2_IOD0 Setting value 0X 1Xb X XXXb Complementary PWM mode waveform output 0 1 00b 1 XXXb PWM mode waveform output 0 1 00b 0 001b, 01Xb Timer mode waveform output (output compare function) X 1 00b 0 1XXb Timer mode trigger input (input capture function)(1) Other than above I/O port Table 14.16 Pin Functions TRDIOA1(P2_4) Register TRDOER1 TRDFCR TRDIORA1 Function Bit EA1 PWM3 CMD1, CMD0 IOA2_IOA0 Setting value 0X 1Xb XXXb Complementary PWM mode waveform output

0 X 01b XXXb Reset synchronous PWM mode waveform output

0 1 00b 001b, 01Xb Timer mode waveform output (output compare function) X 1 00b 1XXb Timer mode trigger input (input capture function)(1) Other than above I/O port Table 14.17 Pin Functions TRDIOB1(P2_5) Register TRDOER1 TRDFCR TRDPMR TRDIORA1 Function Bit EB1 PWM3 CMD1, CMD0 PWMB1 IOB2_IOB0 Setting value 0X 1Xb X XXXb Complementary PWM mode waveform output 0 1 00b 1 XXXb PWM mode waveform output 0 1 00b 0 001b, 01Xb Timer mode waveform output (output compare function) X 1 00b 0 1XXb Timer mode trigger input (input capture function)(1) Other than above I/O port

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 162 of 458 REJ09B0250-0200 X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_6 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function). X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_7 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function). X: can be 0 or 1, no change in outcome Table 14.18 Pin Functions TRDIOC1(P2_6) Register TRDOER1 TRDFCR TRDPMR TRDIORC1 Function Bit EC1 PWM3 CMD1, CMD0 PWMC1 IOC2_IOC0 Setting value 0X 1Xb X XXXb Complementary PWM mode waveform output 0 1 00b 1 XXXb PWM mode waveform output 0 1 00b 0 001b, 01Xb Timer mode waveform output (output compare function) X 1 00b 0 1XXb Timer mode trigger input (input capture function)(1) Other than above I/O port Table 14.19 Pin Functions TRDIOD1(P2_7) Register TRDOER1 TRDFCR TRDPMR TRDIORC1 Function Bit ED1 PWM3 CMD1, CMD0 PWMD1 IOD2_IOD0 Setting value 0X 1Xb X XXXb Complementary PWM mode waveform output 0 1 00b 1 XXXb PWM mode waveform output 0 1 00b 0 001b, 01Xb Timer mode waveform output (output compare function) X 1 00b 0 1XXb Timer mode trigger input (input capture function)(1) Other than above I/O port Table 14.20 Pin Functions INT0 (P4_5) Register TRDOER2 INTEN PD4 Function Bit PTO INT0PL INT0EN PD4_5 Setting value 10 1 0 Pulse output forced cutoff signal input Other than above I/O port or INT0 interrupt input

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 163 of 458 REJ09B0250-0200 Figure 14.27 Block Diagram of Timer RD TRDi register Data bus TRDGRAi register TRDGRBi register TRDGRCi register TRDGRDi register TRDCRi register TRDIORAi register TRDIORCi register TRDSRi register TRDIERi register TRDPOCRi register TRDSTR register TRDMR register TRDPMR register TRDFCR register TRDOER1 register TRDOER2 register TRDOCR register Timer RD control circuit INT0 TRDIOA0/TRDCLK TRDIOB0 TRDIOC0 TRDIOD0 TRDIOB1 TRDIOC1 TRDIOD1 TRDIOA1 Count source select circuit f1, f2, f4, f8, f32, fOCO40M Channel 0 interrupt request Channel 1 interrupt request A/D trigger Channel i i = 0 or 1 TRDDFi register

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 164 of 458 REJ09B0250-0200

14.3.1 Count Source

The count source selection can be used in all modes. However, in PWM3 mode, the external clock cannot be selected. i = 0 or 1 NOTE: 1. The count source fOCO40M can be used with VCC = 3.0 to 5.5 V. Figure 14.28 Block Diagram of Count Source Set the pulse width of the external clock which inputs to the TRDCLK pin to 3 cycles or above of the operation clock of Timer RD (refer to Table 14.11 Timer RD Operation Clocks). When selecting fOCO40M for the count source, set the FRA00 bit in th e FRA0 register to 1 (high-speed on- chip oscillator on) before setting the TCK2 to TCK0 bits in the TRDCRi register (i = 0 or 1) to 110b (fOCO40M). Table 14.21 Count Source Selection Count Source Selection f1, f2, f4, f8, f32 The coun t source is selected by bits TCK2 to TCK0 in the TRDCRi register. fOCO40M(1) The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator frequency). Bits TCK2 to TCK0 in the TRDCRi register is set to 110b (fOCO40M). External Signal Input to TRDCLK Pin The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). The TCK2 to TCK0 bits in the TRDCRi register are set to 101b (count source: external clock). The valid edge selected by the CKEG1 to CKEG0 bits in the TRDCRi register. The PD2_0 bit in the PD2 register is set to 0 (input mode). TRDCLK/ TRDIOA0 TCK2 to TCK0 TRDi register i = 0 or 1 TCK2 to TCK0, CKEG1 to CKEG0: Bits in TRDCRi register STCLK: Bit in TRDFCR register f32 = 001b = 010b = 011b = 000b = 101b = 100b Valid edge selected CKEG1 to CKEG0 TRDIOA0 I/O or programmable I/O port Count source STCLK = 1 STCLK = 0 fOCO40M = 110b

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 165 of 458 REJ09B0250-0200

14.3.2 Buffer Operation

The TRDGRCi register can be used as the buffer register of the TRDGRAi register, and the TRDGRDi register can be used as the buffer register of the TRDGRBi register by the BFCi and BFDi bits in the TRDMR register.

• TRDGRAi buffer register: TRDGRCi register
• TRDGRBi buffer register: TRDGRDi register Buffer operation depends on modes. Table 14.22 lists the Buffer Operation in Each Mode. Figure 14.29 shows the Buffer Operation in Input Capture Function, and Figure 14.30 shows the Buffer Operation in Output Compare Function. i = 0 or 1 Figure 14.29 Buffer Operation in Input Capture Function Table 14.22 Buffer Operation in Each Mode Function and Mode Transfer Timing Transfer Register Input Capture Function Input capture sign al input Transfer content in TRDGRAi (TRDGRBi) register to buffer register Output Compare Function Compare match with TRDi register and TRDGRAi (TRDGRBi) register Transfer content in buffer register to TRDGRAi (TRDGRBi) registerPWM Mode Reset Synchronous PWM Mode Compare match withTRD0 register and TRDGRA0 register Transfer content in buffer register to TRDGRAi (TRDGRBi) register Complementary PWM Mode
• Compare match with TRD0 register and TRDGRA0 register
• TRD1 register underflow Transfer content in buffer register to TRDGRB0, TRDGRA1 and TRDGRB1 registers PWM3 Mode Compare match with TRD0 register and TRDGRA0 register Transfer content in buffer register to TRDGRA0, TRDGRB0, TRDGRA1 and TRDGRB1 registers m Transfer nTRDGRAi register n-1 n+1 TRDIOAi input TRDi register i = 0 or 1 The above applies to the following conditions:
• The BFCi bit in the TRDMR register is set to 1. (The TRDGRCi register is used as the buffer register of the TRDGRAi register.)
• The IOA2 to IOA0 bits in the TRDIORAi register are set to 100b (input capture at the falling edge). m Transfer TRDGRCi register (buffer) n TRDGRCi register (buffer) TRDGRAi register TRDi TRDIOAi input (input capture signal)

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 166 of 458 REJ09B0250-0200 Figure 14.30 Buffer Operation in Output Compare Function Perform the following for the timer mode (input capture and output compare functions). When using the TRDGRCi (i = 0 or 1) register as the buffer register of the TRDGRAi register

• Set the IOC3 bit in the TRDIORCi register to 1 (general register or buffer register).
• Set the IOC2 bit in the TRDIORCi register to the same as the IOA2 bit in the TRDIORAi register. When using the TRDGRDi register as the buffer register of the TRDGRBi register
• Set the IOD3 bit in the TRDIORDi register to 1 (general register or buffer register).
• Set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. Bits IMFC and IMFD in the TRDSRi register are set to 1 at the input edge of the TRDIOCi pin when also using registers TRDGRCi and TRDGRDi as the buffer register in the input capture function. When using the TRDGRCi and TRDGRDi registers for the buffer register in output compare function, reset synchronous PWM mode, complementary PWM mode an d PWM3 mode, the IMFC and IMFD bits in the TRDSRi register are set to 1 by the compare match with the TRDi register. mnTRDGRAi register m-1 m+1TRDi register i = 0 or 1 The above applies to the following conditions:
• BFCi bit in the TRDMR register is set to 1. (The TRDGRCi register is used as the buffer register of the TRDGRAi register.)
• IOA2 to IOA0 bits in the TRDIORAi register are set to 001b (“L” output by the compare match). n Transfer TRDGRCi register (buffer) m TRDIOAi output TRDGRCi register (buffer) TRDGRAi register Comparator TRDi Compare match signal

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 167 of 458 REJ09B0250-0200

14.3.3 Synchronous Operation

The TRD1 register is synchronized with the TRD0 register.

• Synchronous preset When the SYNC bit in the TRDMR regi ster is set to 1 (synchronous operation), the data is written to both the TRD0 and TRD1 registers after writing to the TRDi register.
• Synchronous clear When the SYNC bit in the TRDMR register is set to 1 and the CCLR2 to CCLR0 bits in the TRDCRi register are set to 011b (synchronous clear), and the TRD0 register is set to 0000h at the same time as the TRD1 register is set to 0000h. Also, when the SYNC bit in the TRDMR register is set to 1 and the CCLR2 to CCLR0 bits in the TRDCRi register are set to 011b (synchronous clear), and the TRD1 register is set to 0000h at the same time as the TRD0 register is set to 0000h. Figure 14.31 Synchronous Operation Value in TRD0 register TRDIOA0 input n n is set n writing Value in TRD1 register n Set to 0000h with TRD0 register Set to 0000h by input capture The above applies to the following conditions:
• The SYNC bit in the TRDMR register is set to 1 (synchronous operation).
• The CCLR2 to CCLR0 bits in the TRDCR0 register are set to 001b (set the TRD0 register to 0000h in input capture). The CCLR2 to CCLR0 bits in the TRDCR1 register are set to 011b. (Set the TRD1 register to 0000h synchronizing with the TRD0 register.)
• The IOA2 to IOA0 bits in the TRDIORA0 register are set to 100b.
• The CMD1 to CMD0 bits in the TRDFCR register are set to 00b. (Input capture at the rising edge of the TRDIOA0 input) The PWM 3 bit in the TRDFCR register is set to 1. n is set

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 168 of 458 REJ09B0250-0200

14.3.4 Pulse Output Forced Cutoff

In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode and PWM3 mode, the TRDIOji output pin can be forcibly set to the programmable I/O port by the INT0 pin input, and pulse output can be cut off. The used pins for the output in these functions or modes can function as the output pin of Timer RD when setting the applicable bit in the TRDOER1 register to 0 (enable Timer RD output). When the PTO bit in the TRDOER2 register to 1 (INT0 of pulse output forced cutoff signal input enabled), all bits in the TRDOER1 register are set to 1 (disable Timer RD output, the TRDIOji output pin is used as the programmable I/O port) after “L” is applied to the INT0 pin. The TRDIOji output pin is set to the programmable I/O port after “L” is applied to the INT0 pin and waiting for 1 to 2 cycles of the Timer RD operation clock (refer to Table 14.11 Timer RD Operation Clocks). Set as below when using this function:

• Set the pin status (high impedance, “L” or “H” output ) with the pulse output for ced cutoff by the P2 and PD2 registers.
• Set the INT0EN bit in the INTEN register to 1 (enable INT0 input) and the INT0PL bit to 0 (one edge).
• Set the PD4_5 bit in the PD4 register to 0 (input mode).
• Set the INT0 digital filter by the INT0F1 to INT0F0 bits in the INTF register.
• Set the PTO bit in the TRDOER2 register to 1 (enable pulse output forced cutoff signal input INT0). According to the selection of the POL bit in the INT0IC register and change of the INT0 pin input, the IR bit in the INT0IC register is set to 1 (interrupt request). Refer to 12. Interrupts for details of interrupts.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 169 of 458 REJ09B0250-0200 Figure 14.32 Pulse Output Forced Cutoff INT0 input TRDIOA0 PTO bit D S Q EA0 bit TRDIOB0 D S Q EB0 bit TRDIOC0 D S Q EC0 bit TRDIOD0 D S Q ED0 bit TRDIOA1 D S Q EA1 bit TRDIOB1 D S Q EB1 bit TRDIOC1 D S Q EC1 bit TRDIOD1 D S Q ED1 bit Port P2_0 output data Port P2_0 input data Port P2_1 output data Port P2_1 input data Port P2_2 output data Port P2_2 input data Port P2_3 output data Port P2_3 input data Port P2_4 output data Port P2_4 input data Port P2_5 output data Port P2_5 input data Port P2_6 output data Port P2_6 input data Port P2_7 output data Port P2_7 input data PTO: Bit in TRDOER2 register EA0, EB0, EC0, ED0, EA1, EB1, EC1, ED1: Bits in TRDOER1 register EA0 bit writing value EB0 bit writing value EC0 bit writing value ED0 bit writing value EA1 bit writing value EB1 bit writing value EC1 bit writing value ED1 bit writing value Timer RD output data Timer RD output data Timer RD output data Timer RD output data Timer RD output data Timer RD output data Timer RD output data Timer RD output data

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 170 of 458 REJ09B0250-0200

14.3.5 Input Capture Function

The input capture function is to meas ure the external signal width and peri od. The content in the TRDi register (counter) is transferred to the TRDGRji register as a trigger of the TRDIOji (i = 0 or 1, j = either A, B, C or D) pin external signal (input cap ture). Since this function is enabled with a combination of the TRDIOji pin and TRDGRji register, any of the input capture function, other modes or functions can be selected every pin. The TRDGRA0 register can also select fOCO128 signal as input-capture trigger input. Figure 14.33 shows the Block Diagram of Input Capture Function, Table 14.23 lists the Input Capture Function Specifications. Figures 14.34 to 14.44 show the Regist ers Associated with Input Capture Function and Figure 14.45 shows the Operating Example of Input Capture Function. Figure 14.33 Block Diagram of Input Capture Function i = 0 or 1 NOTES: 1. When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the TRDGRAi register). 2. When the BFDi bit in the TRDMR register is set to 1 (the TRDGRDi register is used as the buffer register of the TRDGRBi register). 3. The trigger input of the TRDGRA0 register can select the TRDIOA0 pin input or fOCO128 signal. TRDGRAi register TRDi register Input capture signal TRDIOAi(3) TRDGRCi register TRDGRBi register Input capture signal TRDGRDi register TRDIOBi (Note 1) (Note 2) TRDIOCi TRDIODi TRDIOA0 Divided by 128 IOA3 = 0 IOA3 = 1 fOCO fOCO128 Input capture signal Input capture signal Input capture signal

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 171 of 458 REJ09B0250-0200 i = 0 or 1, j = either A, B, C or D Table 14.23 Input Capture Function Specifications Item Specification Count Sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Count Operations Increment Count Period When the CCLR2 to CCLR0 bits in the TRDCRi register are set to 000b (free-running operation). 1/fk × 65536 fk: Frequency of count source Count Start Condition Write 1 (count starts) to the TSTARTi bit in the TRDSTR register. Count Stop Condition Write 0 (count stops) to the TSTARTi bit in the TRDSTR register when the CSELi bit in the TRDSTR register is set to 1. Interrupt Request Generation Timing

• Input capture (valid edge of TRDIOji input or fOCO128 signal edge)
• TRDi register overflows TRDIOA0 Pin Function Programmable I/O port, inpu t-capture input, or TRDCLK (external clock) input TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 Pin Functions Programmable I/O port, or input-capture input (Select every pin) INT0 Pin Function Programmable I/O port or INT0 interrupt input Read from Timer The count value can be read by reading the TRDi register. Write to Timer • When the SYNC bit in the TRDMR register is set to 0 (channels 0 and 1 operate independently).
• Data can be written to the TRDi register.
• When the SYNC bit in the TRDMR register is set to 1 (channels 0 and 1 operate synchronously.)
• Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi register. Selection Functions • Input-capture input pin selected Either 1 pin or multiple pins of the TRDIOAi, TRDIOBi, TRDIOCi or TRDIODi pin.
• Input-capture input valid edge selected The rising edge, falling edge or both the rising and falling edges
• The timing when the TRDi register is set to 0000h At overflow or input capture
• Buffer operation (refer to 14.3.2 Buffer Operation)
• Synchronous operation (refer to 14.3.3 Synchronous Operation)
• Digital filter The TRDIOji input is sampled, and when the sampled input level match 3 times, its level is assumed as a determination.
• Input-capture trigger selected fOCO128 can be selected for input-capture trigger input of the TRDGRA0 register.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 172 of 458 REJ09B0250-0200 Figure 14.34 Registers TRDSTR and TRDMR in Input Capture Function Timer RD Start Register(1) Symbol Address After Reset TRDSTR 0137h 11111100b Bit Symbol Bit Name Function RW NOTE: b3 b2 CSEL1 b1 b0 Set to 1 in the input capture function TRD1 count operation select bit Set to 1 in the input capture function Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1 TRDSTR Re gis te r of Notes on Timer RD. RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 1. — TRD0 count operation select bit b7 b6 b5 b4 (b7 - b4) CSEL0 TSTART0 RW TSTART1 RWTRD1 count start flag 0 : Count stops 1 : Count starts TRD0 count start flag 0 : Count stops 1 : Count starts Timer RD Mode Register Symbol Address After Reset TRDMR 0138h 00001110b Bit Symbol Bit Name Function RW b3 b2 BFD0 b1 b0 SYNC b7 b6 b5 b4 RW (b3 - b1) — Timer RD synchronous bit 0 : TRD0 and TRD1 registers operate independently 1 : TRD0 and TRD1 registers operate synchronously Nothing is assigned. If necessary, set to 0. When read, the content is 1. RWTRDGRD0 register function selection bit 0 : General register 1 : Buffer register of TRDGRB0 register TRDGRC1 register function selection bit 0 : General register 1 : Buffer register of TRDGRA1 register RW TRDGRC0 register function selection bit 0 : General register 1 : Buffer register of TRDGRA0 registerBFC0 RW RW BFC1 BFD1 TRDGRD1 register function selection bit 0 : General register 1 : Buffer register of TRDGRB1 register

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 173 of 458 REJ09B0250-0200 Figure 14.35 TRDPMR Register in Input Capture Function Timer RD PWM Mode Register Symbol Address After Reset TRDPMR 0139h 10001000b Bit Symbol Bit Name Function RW (b7) — PWMB1 PWMC1 RW N othing is assigned. I f necessary, set to 0. When read, the content is 1. PWM mode of TRDIOC1 selection bit Set to 0 (timer mode) in the input capture function. PWMD1 PWM mode of TRDIOD1 selection bit PWM mode of TRDIOB1 selection bit Set to 0 (timer mode) in the input capture function. RW RW N othing is assigned. I f necessary, set to 0. When read, the content is 1. Set to 0 (timer mode) in the input capture function. PWM mode of TRDIOD0 selection bit Set to 0 (timer mode) in the input capture function.PWMD0 RW RW PWMC0 RW PWM mode of TRDIOB0 selection bit Set to 0 (timer mode) in the input capture function. PWM mode of TRDIOC0 selection bit Set to 0 (timer mode) in the input capture function. 000 b7 b6 b5 b4 b3 b2 (b3) b1 b0 000 PWMB0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 174 of 458 REJ09B0250-0200 Figure 14.36 TRDFCR Register in Input Capture Function Timer RD Function Control Register Symbol Address After Reset TRDFCR 013Ah 10000000b Bit Symbol Bit Name Function RW NOTES: 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. b3 b2 OLS1 b1 b0 001 b7 b6 b5 b4 RW CMD1 RW Combination mode selection bit(1) Set to 00b (timer mode, PWM mode, or PWM3 mode) in the input capture function.CMD0 Normal-phase output level selection bit (in reset synchronous PWM mode or complementary PWM mode) This bit is disabled in the input capture function. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). OLS0 RW RW Counter-phase output level selection bit (in reset synchronous PWM mode or complementary PWM mode) This bit is disabled in the input capture function. A/D trigger enable bit (in complementary PWM mode) This bit is disabled in the input capture function. RW PWM3 RW AD TR G AD E G A/D trigger edge selection bit (in complementary PWM mode) This bit is disabled in the input capture function. RW PWM3 mode selection bit(2) Set this bit to 1 (other than PWM3 mode) in the input capture function. STCLK External clock input selection bit 0 : External clock input disabled 1 : External clock input enabled RW

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 175 of 458 REJ09B0250-0200 Figure 14.37 Registers TRDDF0 to TRDDF1 in Input Capture Function Timer RD Digital Filter Function Selection Register i (i = 0 or 1) Symbol Address After Reset TRDDF0 TRDDF1 013Eh 013Fh 00h 00h Bit Symbol Bit Name Function RW (b5 - b4) DFCK0 RW b3 b2 DFD b1 b0 DFC b7 b6 b5 b4 RW DFB RW DFA TRDIOA pin digital filter function selection bit 0 : Function is not used 1 : Function is used TRDIOB pin digital filter function selection bit 0 : Function is not used 1 : Function is used RW RWTRDIOD pin digital filter function selection bit 0 : Function is not used 1 : Function is used TRDIOC pin digital filter function selection bit 0 : Function is not used 1 : Function is used Nothing is assigned. If necessary, set to 0. When read, the content is 0. Clock selection bit for digital filter function DFCK1 RW b7 b6 0 0 : f32 0 1 : f8 1 0 : f1 1 1 : Count source (clock selected by the TCK2 to TCK0 bits in the TRDCRi register)

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 176 of 458 REJ09B0250-0200 Figure 14.38 Registers TRDCR0 to TRDCR1 in Input Capture Function Timer RD Control Register i (i = 0 or 1) Symbol Address After Reset TRDCR0 TRDCR1 0140h 0150h 00h 00h Bit Symbol Bit Name Function RW NOTES: RW TCK1 RW TCK0 RW RW RW CCLR2 CCLR1 RW Count source selection bit b2 b1 b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : TRDCLK input (1) 1 1 0 : fOCO40M 1 1 1 : Do not set External clock edge selection bit(2) b4 b3 0 0 : Count at the rising edge 0 1 : Count at the falling edge 1 0 : Count at both edges 1 1 : Do not set b7 b6 b5 b4 b3 b2 CKEG0 b1 b0 TCK2 This bit is enabled w hen the SYNC bit in the TRDMR register is set to 1 (TRD0 and TRD1 registers operate synchronously). This bit is enabled w hen the TCK2 to TCK0 bits are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). RW CKEG1 CCLR0 RW b7 b6 b5 0 0 0 : Disable clear (free-running operation) 0 0 1 : Clear by the input capture in the TRDGRAi register 0 1 0 : Clear by the input capture in the TRDGRBi register 0 1 1 : Synchronous clear (clear simultaneously w ith other channel counter) (3) 1 0 0 : Do not set 1 0 1 : Clear by the input capture in the TRDGRCi register 1 1 0 : Clear by the input capture in the TRDGRDi register 1 1 1 : Do not set TR D i counter clear selection bit This bit is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 177 of 458 REJ09B0250-0200 Figure 14.39 Registers TRDIORA0 to TRDIORA1 in Input Capture Function Timer RD I/O Control Register Ai (i = 0 or 1) Symbol Address After Reset TRDIORA0 TRDIORA1 0141h 0151h 10001000b 10001000b Bit Symbol Bit Name Function RW NOTES: Nothing is assigned. If necessary, set to 0. When read, the content is 1. — IOB0 TRDGRB mode selection bit(2) b3 b2 IOA 3 b1 b0 IOA 2 b7 b6 b5 b4 RW IOA 1 IOA 0 TRDGRA control bit b1 b0 0 0 : Input capture to the TRDGRAi register at the rising edge 0 1 : Input capture to the TRDGRAi register at the falling edge 1 0 : Input capture to the TRDGRAi register at both edges 1 1 : Do not set RW Set to 1 (input capture) in the input capture function When selecting 1 (The TRDGRDi register is used as a buffer register of TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. RW RW (b7) IOB2 RW TRDGRB control bit b5 b4 0 0 : Input capture to the TRDGRBi register at the rising edge 0 1 : Input capture to the TRDGRBi register at the falling edge 1 0 : Input capture to the TRDGRBi register at both edges 1 1 : Do not set The IOA3 bit in the only TRDIORA0 register is enabled. Set to the IOA3 bit in the TRDIORA1 to 1. The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function). TRDGRA mode selection bit (1) Set to 1 (input capture) in the input capture function RW Input capture input sw itch bit(3,4) 0 : fOCO128 Signal 1 : TRDIOA0 pin RW When selecting 1 (The TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. IOB1

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 178 of 458 REJ09B0250-0200 Figure 14.40 Registers TRDIORC0 to TRDIORC1 in Input Capture Function Timer RD I/O Control Register Ci (i = 0 or 1) Symbol Address After Reset TRDIORC0 TRDIORC1 0142h 0152h 10001000b 10001000b Bit Symbol Bit Name Function RW NOTES: 2. When selecting 1 (The TRDGRDi register is used as a buffer register of TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. RW IOD0 IOD1 RW Set to 1 (general register or buffer register) in the input capture function When selecting 1 (The TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. TRDGRD mode selection bit(2) Set to 1 (input capture) in the input capture function RW IOD3 IOD2 RW TRDGRD control bit b5 b4 0 0 : Input capture to the TRDGRDi register at the rising edge 0 1 : Input capture to the TRDGRDi register at the falling edge 1 0 : Input capture to the TRDGRDi register at both edges 1 1 : Do not set TRDGRD register function selection bit b3 b2 IOC3 b1 b0 IOC2 b7 b6 b5 b4 RW RW IOC1 IOC0 TRDGRC control bit b1 b0 0 0 : Input capture to the TRDGRCi register at the rising edge 0 1 : Input capture to the TRDGRCi register at the falling edge 1 0 : Input capture to the TRDGRCi register at both edges 1 1 : Do not set TRDGRC mode selection bit (1) Set to 1 (input capture) in the input capture function RW TRDGRC register function selection bit Set to 1 (general register or buffer register) in the input capture function RW

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 179 of 458 REJ09B0250-0200 Figure 14.41 Registers TRDSR0 to TRDSR1 in Input Capture Function Timer RD Status Register i (i = 0 or 1) Symbol Address After Reset TRDSR0 TRDSR1 0143h 0153h 11100000b 11000000b Bit Symbol Bit Name Function RW NOTES: 4. Edge selected by bits IOk1 to IOk0 (k = C or D) in the TRDIORCi register. Including w hen the BFki bit in the TRDMR register is set to 1 (TRDGRki is used as the buffer register). Edge selected by bits IOj1 to IOj0 (j = A or B) in the TRDIORAi register. The w riting results are as follow s:

• This bit is set to 0 w hen the read result is 1 and w riting 0 to the same bit.
• This bit remains unchanged even if the read result is 0 and w riting 0 to the same bit. (This bit remains 1 even if this bit is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged w hen w riting 1. b3 b2 IMFD b1 b0b7 b6 b5 b4 RW IMFB RW Input capture/compare match flag A [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] TRDSR0 register: fOCO128 signal edge w hen the IOA3 bit in the TRDIORA0 register is set to 0 (fOCO128 signal) TRDIOA0 pin input edge w hen the IOA3 bit in the TRDIORA0 register is set to 1 (TRDIOA0 input) (3) TRDSR1 register: Input edge of TRDIOA1 pin.(3) Input capture/compare match flag B [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] Input edge of TRDIOBi pin.(3) IMFA Input capture/compare match flag C [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] Input edge of TRDIOCi pin.(4) Nothing is assigned to the b5 in the TRDSR0 register. When w riting to the b5, w rite 0. When reading, its content is 1. IMFC RW RW Input capture/compare match flag D [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] Input edge of TRDIODi pin.(4) Overflow flag [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the TRDi register overflow s (b7 - b6) —Nothing is assigned. If necessary, set to 0. When read, the content is 1. RWOVF UDF Underflow flag(1) This bit is disabled in the input capture function. RW

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 181 of 458 REJ09B0250-0200 Figure 14.44 Registers TRDGRAi , TRDGRBi, TRDGRCi and TRDGRDi in Input Capture Function The following registers are disabled in the input capture function: TRDOER1, TRDOER2, TRDOCR, TRDPOCR0 and TRDPOCR1 i = 0 or 1, j = either A, B, C or D BFCi, BFDi: Bits in TRDMR Register Set the pulse width of the input capture signal applied to the TRDIOji pin to 3 cycles or more of the Timer RD operation clock (refer to Table 14.11 Timer RD Operation Clocks ) for “no digital filter” (the DFj bit in the TRDDFi register is set to 0). Table 14.24 TRDGRji Register Functions in Input Capture Function Register Setting Register Function Input-Capture Input Pin TRDGRAi − General register The value in the TRDi register can be read at the input capture. TRDIOAi TRDGRBi TRDIOBi TRDGRCi BFCi = 0 General register The value in the TRDi register can be read at the input capture. TRDIOCi TRDGRDi BFDi = 0 TRDIODi TRDGRCi BFCi = 1 Buffer register The value in the TRDi register can be read at the input capture. (Refer to 14.3.2 Buffer Operation) TRDIOAi TRDGRDi BFDi = 1 TRDIOBi Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1)(1) Symbol Address After Reset TRDGRA 0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA 1 TRDGRB1 TRDGRC1 TRDGRD1 0149h-0148h 014Bh-014Ah 014Dh-014Ch 014Fh-014Eh 0159h-0158h 015Bh-015Ah 015Dh-015Ch 015Fh-015Eh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh RW NOTE: (b8) (b15) b7 b0b7 RW Function Ref er to Table 14.24 TRDGRji Register Functions in Input Capture Function Access the TRDGRAi to TRDGRDi registers in 16-bit units. Do not access them in 8-bit units.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 182 of 458 REJ09B0250-0200 Figure 14.45 Operating Example of Input Capture Function Set to 0 by a program Transfer i = 0 or 1 The above applies to the following conditions: The CCLR2 to CCLR0 bits in the TRDCRi register are set to 001b. (Set the TRDi register to 0000h by the TRDGRAi register input capture.) The TCK2 to TCK0 bits in the TRDCRi register are set to 101b (TRDCLK input for the count source). The CKEG1 to CKEG0 bits in the TRDCRi register are set to 01b (count at the falling edge for the count source). The IOA2 to IOA0 bits in the TRDIORAi register are set to 101b (input capture at the falling edge of the TRDIOAi input). The BFCi bit in the TRDMR register is set to 1. (The TRDGRCi register is used as the buffer register of the TRDGRAi register.) Count value in TRDi register FFFFh 0009h 0006h TSTARTi bit in TRDSTR register 65536 TRDGRAi register 0000h TRDIOAi input TRDGRCi register IMFA bit in TRDSRi register OVF bit in TRDSRi register 0009h0006h 0006h TRDCLK input count source Transfer

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 183 of 458 REJ09B0250-0200

14.3.5.1 Digital Filter

The TRDIOji input is sampled, and when the sampled in put level matches 3 times, its level is assumed as a determination. Select the digital filter function and sampling clock by the TRDDFi register. Figure 14.46 Block Diagram of Digital Filter C DQ Latch C DQ Latch C DQ Latch Match detection circuit Edge detection circuit DFj Sampling clock IOA2 to IOA0 IOB2 to IOB0 IOC3 to IOC0 IOD3 to IOD0 DFCK1 to DFCK0 TRDIOji input signal Clock period selected by the TCK2 to TCK0 bits or DFCK1 to DFCK0 bits Sampling clock TRDIOji input signal Input signal through digital filtering Transmission cannot be performed without 3-times match because the input signal is assumed as noise. Signal transmission delayed up to 5-sampling clock Recognition of the signal change with 3-time match f32 i = 0 or 1, j = either A, B, C or D TCK0 to TCK2: Bits in TRDCRi register DFCK0 to DFCK1 and DFj: Bits in TRDDF register IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register C DQ Latch C DQ Latch Timer RD operation clock f1, fOCO40M Count source =101b =100b =011b =110b =010b =001b fOCO40M f32 TRDCLK f1 =000b =00b =01b =10b =11b TCK2 to TCK0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 184 of 458 REJ09B0250-0200

14.3.6 Output Compare Function

This function is to detect the match (compare match) of the content in the TRDGRji (j = either A, B, C and D) register with the content in the TRDi (i = 0 or 1) re gister. When the content matches, any level is output from the TRDIOji pin. Since this function is enabled with a combination of the TRDIOj i pin and TRDGRji register, any of the output compare function, other modes or functions can be selected every pin. Figure 14.47 shows the Block Diagram of Output Compar e Function, Table 14.25 lists the Output Compare Function Specifications. Figures 14.48 to 14.59 list th e Registers Associated with Output Compare Function and Figure 14.60 shows the Operating Example of Output Compare Function. Figure 14.47 Block Diagram of Output Compare Function TRDIOA0 Output control Comparator TRDGRA0 TRD0 TRDIOC0 Output control Comparator TRDGRC0 Compare match signal TRDIOB0 Output control Comparator TRDGRB0 TRDIOD0 Output control Comparator TRDGRD0 Channel 0 TRDIOA1 Output control Comparator TRDGRA1 TRD1 TRDIOC1 Output control Comparator TRDGRC1 TRDIOB1 Output control Comparator TRDGRB1 TRDIOD1 Output control Comparator TRDGRD1 Channel 1 Compare match signal Compare match signal Compare match signal Compare match signal Compare match signal Compare match signal Compare match signal IOC3 = 0 in TRDIORC0 register IOC3 = 1 IOD3 = 0 in TRDIORD0 register IOD3 = 1 IOC3 = 0 in TRDIORC1 register IOC3 = 1 IOD3 = 0 in TRDIORD1 register IOD3 = 1

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 185 of 458 REJ09B0250-0200 i = 0 or 1, j = either A, B, C or D Table 14.25 Output Compare Function Specifications Item Specification Count Sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Count Operations Increment Count Period • When the CCLR2 to CCLR0 bits in the TRDCRi register are set to 000b (free- running operation) 1/fk × 65536 fk: Frequency of count source

• The CCLR1 to CCLR0 bits in the TRDCRi register are set to 01b or 10b (set the TRDi register to 0000h at the compare match in the TRDGRji register.) Frequency of count source x (n + 1) n: Setting value in the TRDGRji register Waveform Output Timing Compare match Count Start Condition Write 1 (count starts) to the TSTARTi bit in the TRDSTR register. Count Stop Conditions • Write 0 (count stops) to the TSTARTi bit in the TRDSTR register when the CSELi bit in the TRDSTR register is set to 1. The output compare output pin holds output level before the count stops.
• When the CSELi bit in the TRDSTR register is set to 0, the count stops at the compare match in the TRDGRAi register. The output compare output pin holds level after output change by the compare match. Interrupt Request Generation Timing
• Compare match (the content in the TRDi register matches with the content in the TRDGRji register.)
• TRDi register overflows TRDIOA0 Pin Function Programmable I/O port, output-c ompare output or TRDCLK (external clock) input TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 Pin Functions Programmable I/O port or output-compare output (select every pin) INT0 Pin Function Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input Read from Timer The count value can be read by reading the TRDi register. Write to Timer • When the SYNC bit in the TRDMR register is set to 0 (channels 0 and 1 operate independently) Data can be written to the TRDi register.
• When the SYNC bit in the TRDMR register is set to 1 (channels 0 and 1 operate synchronously). Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi register. Selection Functions • Output-compare output pin selected Either 1 pin or multiple pins of the TRDIOAi, TRDIOBi, TRDIOCi or TRDIODi pin.
• Output level at the compare match selected “L” output, “H” output or output level inversed
• Initial output level selected Set the level at period from the count start to the compare match.
• Timing to set the TRDi register to 0000h Overflow or compare match in the TRDGRAi register
• Buffer operation (refer to 14.3.2 Buffer Operation)
• Synchronous operation (refer to 14.3.3 Synchronous Operation)
• Output pin in the TRDGRCi and TRDGRDi registers changed The TRDGRCi register can be used as output control of the TRDIOAi pin and the TRDGRDi register can be used as output control of the TRDIOBi pin.
• Pulse output forced cutoff signal input (refer to 14.3.4 Pulse Output Forced Cutoff)
• Timer RD can be used as the internal timer without output.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 186 of 458 REJ09B0250-0200 Figure 14.48 Registers TRDSTR and TRDMR in Output Compare Function Timer RD Start Register(1) Symbol Address After Reset TRDSTR 0137h 11111100b Bit Symbol Bit Name Function RW NOTES: Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1 TRDSTR Re gis te r of Notes on Timer RD . TRD0 count operation select bit 0 : Count stops at the compare match w ith the TRDGRA0 register after the count clear 1 : Count continues at the compare match w ith the TRDGRA0 register after the count clear CSEL0 RW RW TRD1 count operation select bit 0 : Count stops at the compare match w ith the TRDGRA1 register after the count clear 1 : Count continues at the compare match w ith the TRDGRA1 register after the count clear (b7 - b4) RW TSTART1 RWTRD1 count start flag (5) 0 : Count stops(3) 1 : Count starts TRD0 count start flag(4) 0 : Count stops(2) 1 : Count starts Nothing is assigned. If necessary, set to 0. When read, the content is 1. b7 b6 b5 b4 b3 b2 CSEL1 b1 b0 TSTART0 When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit. When the CSEL0 bit is set to 0 and generating the compare match signal (TRDIOA0), this bit is set to 0 (count stops). When the CSEL1 bit is set to 0 and generating the compare match signal (TRDIOA1), this bit is set to 0 (count stops). Timer RD Mode Register Symbol Address After Reset TRDMR 0138h 00001110b Bit Symbol Bit Name Function RW NOTE: 1. When selecting 0 (change the TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi (i = 0 or 1) register, set the BFji bit in the TRDMR register to 0. RWBFC1 BFD1 TRDGRD1 register function selection bit(1) 0 : General register 1 : Buffer register of TRDGRB1 register RW TRDGRC0 register function selection bit (1) 0 : General register 1 : Buffer register of TRDGRA0 registerBFC0 RW RWTRDGRD0 register function selection bit (1) 0 : General register 1 : Buffer register of TRDGRB0 register TRDGRC1 register function selection bit (1) 0 : General register 1 : Buffer register of TRDGRA1 register RW (b3 - b1) — Timer RD synchronous bit 0 : TRD0 and TRD1 registers operate independently 1 : TRD0 and TRD1 registers operate synchronously N othing is assigned. I f necessary, set to 0. When read, the content is 1. b7 b6 b5 b4 b3 b2 BFD0 b1 b0 SYNC

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 187 of 458 REJ09B0250-0200 Figure 14.49 TRDPMR Register in Output Compare Function Timer RD PWM Mode Register Symbol Address After Reset TRDPMR 0139h 10001000b Bit Symbol Bit Name Function RW b3 b2 (b3) b1 b0 000 PWMB0 b7 b6 b5 b4 000 RW PWMC0 RW PWM mode of TRDIOB0 selection bit Set to 0 (timer mode) in the output compare function PWM mode of TRDIOC0 selection bit Set to 0 (timer mode) in the output compare function PWM mode of TRDIOB1 selection bit Set to 0 (timer mode) in the output compare function RW RW N othing is assigned. I f necessary, set to 0. When read, the content is 1. Set to 0 (timer mode) in the output compare function PWM mode of TRDIOD0 selection bit Set to 0 (timer mode) in the output compare functionPWMD0 RW (b7) — PWMB1 PWMC1 RW N othing is assigned. I f necessary, set to 0. When read, the content is 1. PWM mode of TRDIOC1 selection bit Set to 0 (timer mode) in the output compare function PWMD1 PWM mode of TRDIOD1 selection bit

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 188 of 458 REJ09B0250-0200 Figure 14.50 TRDFCR Register in Output Compare Function Timer RD Function Control Register Symbol Address After Reset TRDFCR 013Ah 10000000b Bit Symbol Bit Name Function RW NOTES: 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. b3 b2 OLS1 b1 b0 001 b7 b6 b5 b4 RW CMD1 RW Combination mode selection bit(1) Set to 00b (timer mode, PWM mode, or PWM3 mode) in the output compare function. CMD0 Normal-phase output level selection bit (in reset synchronous PWM mode or complementary PWM mode) This bit is disabled in the output compare function. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). OLS0 RW RW Counter-phase output level selection bit (in reset synchronous PWM mode or complementary PWM mode) This bit is disabled in the output compare function. A/D trigger enable bit (in complementary PWM mode) This bit is disabled in the output compare function. RW PWM3 RW AD TR G AD E G A/D trigger edge selection bit (in complementary PWM mode) This bit is disabled in the output compare function. RW PWM3 mode selection bit(2) Set this bit to 1 (other than PWM3 mode) in the output compare function. STCLK External clock input selection bit 0 : External clock input disabled 1 : External clock input enabled RW

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 189 of 458 REJ09B0250-0200 Figure 14.51 Registers TRDOER1 to TRDOER2 in Output Compare Function Timer RD Output Master Enable Register 1 Symbol Address After Reset TRDOER1 013Bh FFh Bit Symbol Bit Name Function RW b3 b2 ED0 b1 b0 EA 0 b7 b6 b5 b4 RW EB0 RW TRDIOA0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOA0 pin is used as a programmable I/O port.) TRDIOB0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOB0 pin is used as a programmable I/O port.) TRDIOC0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOC0 pin is used as a programmable I/O port.) EC0 RW RW TRDIOA1 output disable bit 0 : Enable output 1 : Disable output (The TRDIOA1 pin is used as a programmable I/O port.) RW RW TRDIOD0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOD0 pin is used as a programmable I/O port.) TRDIOC1 output disable bit 0 : Enable output 1 : Disable output (The TRDIOC1 pin is used as a programmable I/O port.) EC1 RW EA 1 EB1 RW TRDIOD1 output disable bit 0 : Enable output 1 : Disable output (The TRDIOD1 pin is used as a programmable I/O port.) TRDIOB1 output disable bit 0 : Enable output 1 : Disable output (The TRDIOB1 pin is used as a programmable I/O port.) EC1 Timer RD Output Master Enable Register 2 Symbol Address After Reset TRDOER2 013Ch 01111111b Bit Symbol Bit Name Function RW INT0 of pulse output forced 0 : Pulse output forced cutoff input disabled cutoff signal input enabled 1 : Pulse output forced cutoff input enabled bit(1) (All bits in the TRDOER1 register are set to 1 (disable output) w hen “L” is applied to the INT0 pin) NOTE: b3 b2 b1 b0b7 b6 b5 b4 Ref er to 14.3.4 Pulse Output Forced Cutoff . (b6 - b0) Nothing is assigned. If necessary, set to 0. When read, the content is 1. RWPTO

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 190 of 458 REJ09B0250-0200 Figure 14.52 TRDOCR Register in Output Compare Function Timer RD Output Control Register(1,2) Symbol Address After Reset TRDOCR 013Dh 00h Bit Symbol Bit Name Function RW NOTES: TOA 1 TOB1 RW TRDIOD1 initial output level selection bit 0 : “L” 1 : “H” TRDIOB1 initial output level selection bit TOC1 TRDIOC1 initial output level selection bit TRDIOC0 initial output level selection bit Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). TOC0 RW RW TRDIOA1 initial output level selection bit RW RW TRDIOD0 initial output level selection bit TOD1 RW RW TOB0 RW TRDIOA0 output level selection bit 0 : Initial output “L” 1 : Initial output “H” TRDIOB0 output level selection bit 0 : Initial output “L” 1 : Initial output “H” TOA 0 b7 b6 b5 b4 When the pin functions are w aveform output (refer to Table 14.12 to 14.19) and the TRDOCR register is set, the initial output level is output. b3 b2 TOD0 b1 b0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 191 of 458 REJ09B0250-0200 Figure 14.53 Registers T RDCR0 to TRDCR1 in Output Compare Function Timer RD Control Register i (i = 0 or 1) Symbol Address After Reset TRDCR0 TRDCR1 0140h 0150h 00h 00h Bit Symbol Bit Name Function RW NOTES: RW TCK1 RW TCK0 RW RW RW CCLR2 CCLR1 RW Count source selection bit b2 b1 b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : TRDCLK input (1) 1 1 0 : fOCO40M 1 1 1 : Do not set External clock edge selection bit(2) b4 b3 0 0 : Count at the rising edge 0 1 : Count at the falling edge 1 0 : Count at both edges 1 1 : Do not set b7 b6 b5 b4 b3 b2 CKEG0 b1 b0 TCK2 This bit is enabled w hen the SYNC bit in the TRDMR register is set to 1 (TRD0 and TRD1 operate synchronously). This bit is enabled w hen the TCK2 to TCK0 bits are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). RW CKEG1 CCLR0 RW b7 b6 b5 0 0 0 : Disable clear (free-running operation) 0 0 1 : Clear by the compare match in the TRDGRAi register 0 1 0 : Clear by the compare match in the TRDGRBi register 0 1 1 : Synchronous clear (clear simultaneously w ith other channel counter) (3) 1 0 0 : Do not set 1 0 1 : Clear by the compare match in the TRDGRCi register 1 1 0 : Clear by the compare match in the TRDGRDi register 1 1 1 : Do not set TRDi counter clear selection bit This bit is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 192 of 458 REJ09B0250-0200 Figure 14.54 Registers TRDIORA0 to TRDIORA1 in Output Compare Function Timer RD I/O Control Register Ai (i = 0 or 1) Symbol Address After Reset TRDIORA 0 TRDIORA 1 0141h 0151h 10001000b 10001000b Bit Symbol Bit Name Function RW NOTES: Input capture input sw itch bit Set to 1 RW Nothing is assigned. If necessary, set to 0. When read, the content is 1. RW RW IOA 1 IOA 0 TRDGRA c ontrol bit b1 b0 0 0 : Disable pin output by the compare match (TRDIOAi pin functions as programmable I/O port) 0 1 : “L” output by the compare match in the TRDGRAi register 1 0 : “H” output by the compare match in the TRDGRAi register 1 1 : Toggle output by the compare match in the TRDGRAi register TR D GRA m ode selection bit (1) Set to 0 (output compare) in the output compare function RW IOB2 RW TRDGRB control bit b5 b4 0 0 : Disable pin output by the compare match (TRDIOBi pin functions as programmable I/O port) 0 1 : “L” output by the compare match in the TRDGRBi register 1 0 : “H” output by the compare match in the TRDGRBi 1 1 : Toggle output by the compare match in the TRDGRBi register b7 b6 b5 b4 b3 b2 IOA 3 b1 b0 IOA 2 When selecting 1 (The TRDGRDi register is used as a buffer register of TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same as the IOB2 bit in the TRDIORAi register. IOB0 IOB1 RW When selecting 1 (The TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same as the IOA2 bit in the TRDIORAi register. TRDGRB mode selection bit(2) Set to 0 (output compare) in the output compare function RW (b7)

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 193 of 458 REJ09B0250-0200 Figure 14.55 Registers TRDIORC0 to TRDIORC1 in Output Compare Function Timer RD I/O Control Register Ci (i = 0 or 1) Symbol Address After Reset TRDIORC0 TRDIORC1 0142h 0152h 10001000b 10001000b Bit Symbol Bit Name Function RW NOTES: 2. When selecting 1 (The TRDGRDi register is used as a buffer register of TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same as the IOB2 bit in the TRDIORAi register. TR DGR C m ode selection bit(1) Set to 0 (output compare) in the output compare function RW TRDGRC register function selection bit (1) 0 : TRDIOA output register (Refer to

14.3.6.1 Changing Output Pins in

Registers TRDGRCi (i = 0 or 1) and TRDGRDi) 1 : General register or buffer register RW IOD0 IOD1 RW RW RW IOC1 IOC0 TRDGRC c ontrol bit b1 b0 0 0 : Disable pin output by the compare match 0 1 : “L” output by the compare match in the TRDGRCi register 1 0 : “H” output by the compare match in the TRDGRCi register 1 1 : Toggle output by the compare match in the TRDGRCi register RW TRDGRD c ontrol bit b5 b4 0 0 : Disable pin output by the compare match 0 1 : “L” output by the compare match in the TRDGRDi register 1 0 : “H” output by the compare match in the TRDGRDi register 1 1 : Toggle output by the compare match in the TRDGRDi register b7 b6 b5 b4 b3 b2 IOC3 b1 b0 IOC2 When selecting 1 (The TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same as the IOA2 bit in the TRDIORAi register. TR DGR D m ode selection bit(2) Set to 0 (output compare) in the output compare function IOD3 IOD2 RW TRDGRD register function selection bit 0 : TRDIOB output register (Refer to Registers TRDGRCi (i = 0 or 1) and TRDGRDi) 1 : General register or buffer register RW

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 194 of 458 REJ09B0250-0200 Figure 14.56 Registers TRDSR0 to TRDSR1 in Output Compare Function Timer RD Status Register i (i = 0 or 1) Symbol Address After Reset TRDSR0 TRDSR1 0143h 0153h 11100000b 11000000b Bit Symbol Bit Name Function RW NOTES: 3. Including w hen the BFji bit (j = C or D) in the TRDMR register is set to 1 (TRDGRji is used as the buffer register). The w riting results are as follow s:

• This bit is set to 0 w hen the read result is 1 and w riting 0 to the same bit.
• This bit remains unchanged even if the read result is 0 and w riting 0 to the same bit. (This bit remains 1 even if this bit is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged w hen w riting 1. b3 b2 IMFD b1 b0b7 b6 b5 b4 RW IMFB RW Input capture/compare match flag A [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRAi register. Input capture/compare match flag B [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRBi register. IMFA Input capture/compare match flag C [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRCi register. (3) Nothing is assigned to the b5 in the TRDSR0 register. When w riting to the b5, w rite 0. When reading, its content is 1. IMFC RW RW Input capture/compare match flag D [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRDi register. (3) Overflow flag [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the TRDi register overflow s. (b7 - b6) —Nothing is assigned. If necessary, set to 0. When read, the content is 1. RWOVF UDF Underflow flag(1) This bit is disabled in the output compare function. RW

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 196 of 458 REJ09B0250-0200 Figure 14.59 Registers TRDGRAi, TRDGRBi, TRDGRCi and TRDGRDi in Output Compare Function The following registers are disabled in the output compare function: TRDDF0, TRDDF1, TRDPOCR0 and TRDPOCR1 i = 0 or 1, j = either A, B, C or D BFji: Bit in TRDMR register IO j3: Bit in TRDIORCi register Table 14.26 TRDGRji Register Functions in Output Compare Function Register Setting Register Function Output-Compare Output PinBFji IOj3 TRDGRAi −− General register. Write the compare value. TRDIOAi TRDGRBi TRDIOBi TRDGRCi 0 1 General register. Write the compare value. TRDIOCi TRDGRDi TRDIODi TRDGRCi 1 1 Buffer register. Write the next compare value (refer to 14.3.2 Buffer Operation.) TRDIOAi TRDGRDi TRDIOBi TRDGRCi 0 0 TRDIOAi output control (refer to 14.3.6.1 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi.) TRDIOAi TRDGRDi TRDIOBi Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1)(1) Symbol Address After Reset TRDGRA 0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA 1 TRDGRB1 TRDGRC1 TRDGRD1 0149h-0148h 014Bh-014Ah 014Dh-014Ch 014Fh-014Eh 0159h-0158h 015Bh-015Ah 015Dh-015Ch 015Fh-015Eh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh RW NOTE: RW Function Ref er to Table 14.26 TRDGRji Register Functions in Output Compare Function Access the TRDGRAi to TRDGRDi registers in 16-bit units. Do not access them in 8-bit units. b0b7 (b8) (b15)

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 197 of 458 REJ09B0250-0200 Figure 14.60 Operating Example of Output Compare Function m n p Value in TRDi register m + 1 m + 1 TSTARTi bit in TRDSTR register TRDIOAi output IMFA bit in TRDSRi register n + 1 TRDIOBi output IMFB bit in TRDSRi register TRDIOCi output IMFC bit in TRDSRi register Initial output “H” “L” output by compare match Set to “0” by a program Count source i = 0 or 1 m: Setting value in TRDGRAi register n: Setting value in TRDGRBi register p: Setting value in TRDGRCi register The above applies to the following conditions: The CSELi bit in the TRDSTR register is set to 1. (The TRDi register is not stopped by the compare match.) The BFCi and BFDi bits in the TRDMR register are set to 0. (The TRDGRCi and TRDGRDi registers are not used as the buffer regist er.) The EAi, EBi and ECi bits in the TRDOER1 register are set to 0. (Enable the TRDIOAi, TRDIOBi and TRDIOCi pin outputs.) The CCLR2 to CCLR0 bits in the TRDCRi register are set to 001b. (S et the TRDi register to 000h by the compare match in the TRDG RAi register.) The TOAi and TOBi bits in the TRDOCR register is set to 0. (ini tial output “L” to the compare match), the TOCi bit is set to 1. (initial output “H” to the compare match. The IOA2 to IOA0 bits in the TRDIORAi register are set to 0 11b. (TRDIOAi output inversed at the TRDGRAi register compare match. ) The IOB2 to IOB0 bits in the TRDIORAi register are set to 0 10b. (TRDIOBi “H” output at the TRDGRBi register compare match.) The IOC3 to IOC0 bits in the TRDIORCi register are set to 10 01b. (TRDIOCi “L” output at the TRDGRCi register compare match.) The IOD3 bit in the TRDIORCi register is set to 1. (TRDGRDi register does not control TRDIOBi pin output.) m n p n + 1 P + 1 Count stop Count restarts Output level held Output level held Output level held Set to 0 by a program Set to 0 by a program “H” output by compare match Output inversed by compare match Initial output “L” Initial output “L”

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 198 of 458 REJ09B0250-0200

14.3.6.1 Changing Output Pi ns in Registers TRDGRCi (i = 0 or 1) and TRDGRDi

The TRDGRCi register can be used as output contro l of the TRDIOAi pin and the TRDGRDi register can be used as output control of the TRDIOBi pin. Therefore, each pin output can be controlled as follows:

• TRDIOAi output is controlled by the values in the TRDGRAi and TRDGRCi registers.
• TRDIOBi output is controlled by the values in the TRDGRBi and TRDGRDi registers. Figure 14.61 Changing Output Pins in Registers TRDGRCi and TRDGRDi Change output pins in the TRDGRCi and TRDGRDi registers as below:
• Select 0 (change TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi register.
• Set the BFji bit in the TRDMR register to 0 (general register).
• Set the different value in the TRDGRCi register and the TRDGRAi register. Also, set the different value in the TRDGRDi register and the TRDGRBi register. TRDIOA0 Output control Comparator TRDGRA0 TRD0 TRDIOC0 Output control Comparator TRDGRC0 Compare match signal TRDIOB0 Output control Comparator TRDGRB0 TRDIOD0 Output control Comparator TRDGRD0 Channel 0 TRDIOA1 Output Control Comparator TRDGRA1 TRD1 TRDIOC1 Output Control Comparator TRDGRC1 TRDIOB1 Output Control Comparator TRDGRB1 TRDIOD1 Output Control Comparator TRDGRD1 Channel 1 Compare match signal Compare match signal Compare match signal Compare match signal Compare match signal Compare match signal Compare match signal IOC3 = 0 in TRDIORC0 register IOC3 = 1 IOD3 = 0 in TRDIORD0 register IOD3 = 1 IOC3 = 0 in TRDIORC1 register IOC3 = 1 IOD3 = 0 in TRDIORD1 register IOD3 = 1

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 200 of 458 REJ09B0250-0200

14.3.7 PWM Mode

PWM mode is to output a PWM waveform. Up to 3 PWM waveforms with the same period can be output by 1 channel. Also, Up to 6 PWM waveforms with the same period can be output by synchronizing Channels 0 and 1. Since this mode functions by a combination of the TR DIOji (i = 0 or 1, j = B, C or D) pin and TRDGRji register, any of PWM mode, other modes or functions can be selected every pin. (However, since the TRDGRAi register is used when using any pin for PWM mode, the TRDGRAi register cannot be used for other modes.) Figure 14.63 shows the Block Diagram of PWM Mode , Table 14.27 lists the PW M Mode Specifications. Figures 14.64 to 14.73 show the Registers Associated with PWM Mode and Figures 14.74 to 14.75 show the Operations of PWM Mode. Figure 14.63 Block Diagram of PWM Mode TRDIOBi Output control TRDGRAi TRDi Compare match signal TRDGRBiTRDIOCi TRDGRCi TRDGRDi TRDIODi (Note 1) (Note 2) i = 0 or 1 NOTES: 1. When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the TRDGRAi register). 2. When the BFDi bit in the TRDMR register is set to 1 (the TRDGRDi register is used as the buffer register of the TRDGRBi register). Compare match signal Compare match signal Compare match signal Comparator Comparator Comparator Comparator

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 201 of 458 REJ09B0250-0200 i = 0 or 1, j = either B, C or D, h = either A, B, C or D Table 14.27 PWM Mode Specifications Item Specification Count Sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Count Operations Increment PWM Waveform PWM period: 1/fk x (m+1) Active level width: 1/fk x (m-n) Inactive level width: 1/fk x (n+1) fk: Frequency of count source m: Setting value in the TRDGRAi register n: Setting value in the TRDGRji register Count Start Condition Write 1 (count starts) to the TSTARTi bit in the TRDSTR register. Count Stop Conditions • Write 0 (count stops) to the TSTARTi bit in the TRDSTR register when the CSELi bit in the TRDSTR register is set to 1.

• The PWM output pin holds output level before the count stops.
• When the CSELi bit in the TRDSTR register is set to 0, the count stops at the compare match in the TRDGRAi register.
• The PWM output pin holds level after output change by the compare match. Interrupt Request Generation Timing
• Compare match (the content in the TRDi register matches with the content in the TRDGRhi register.)
• TRDi register overflows TRDIOA0 Pin Function Programmable I/O port or TRDCLK (external clock) input TRDIOA1 Pin Function Programmable I/O port TRDIOB0, TRDIOC0, TRDIOD0, TRDIOB1, TRDIOC1, TRDIOD1 Pin Functions Programmable I/O port or pulse output (select every pin) INT0 Pin Function Programmable I/O port, pulse out put forced cutoff signal input or INT0 interrupt input Read from Timer The coun t value can be read by reading the TRDi register. Write to Timer The value can be written to the TRDi register. Selection Functions • 1 to 3 PWM output pins selected per 1 channel
• Either 1 pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi pin.
• The active level selected every pin.
• Initial output level selected every pin.
• Synchronous operation (refer to 14.3.3 Synchronous Operation.)
• Buffer operation (refer to 14.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (refer to 14.3.4 Pulse Output Forced Cutoff.) m + 1 n + 1 m - n (When “L” is selected for the active level)

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 202 of 458 REJ09B0250-0200 Figure 14.64 TRDSTR Register in PWM Mode Timer RD Start Register(1) Symbol Address After Reset TRDSTR 0137h 11111100b Bit Symbol Bit Name Function RW NOTES: Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1 TRDSTR Re gis te r of Note s on Tim e r RD. TRD0 count operation select bit 0 : Count stops at the compare match w ith the TRDGRA0 register 1 : Count continues at the compare match w ith the TRDGRA0 register CSEL0 RW RW TRD1 count operation select bit 0 : Count stops at the compare match w ith the TRDGRA1 register 1 : Count continues at the compare match w ith the TRDGRA1 register (b7 - b4) RW TSTART1 RWTRD1 count start flag (5) 0 : Count stops(3) 1 : Count starts TRD0 count start flag(4) 0 : Count stops(2) 1 : Count starts Nothing is assigned. When w rite, set to 0. When read, its content is 1. b7 b6 b5 b4 b3 b2 CSEL1 b1 b0 TSTART0 When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit. When the CSEL0 bit is set to 0 and generating the compare match signal (TRDIOA0), this bit is set to 0 (count stops). When the CSEL1 bit is set to 0 and generating the compare match signal (TRDIOA1), this bit is set to 0 (count stops).

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 203 of 458 REJ09B0250-0200 Figure 14.65 Registers TRDMR and TRDPMR in PWM Mode Timer RD Mode Register Symbol Address After Reset TRDMR 0138h 00001110b Bit Symbol Bit Name Function RW RW BFC1 BFD1 TRDGRD1 register function selection bit 0 : General register 1 : Buffer register of TRDGRB1 register RWTRDGRD0 register function selection bit 0 : General register 1 : Buffer register of TRDGRB0 register TRDGRC1 register function selection bit 0 : General register 1 : Buffer register of TRDGRA1 register RW TRDGRC0 register function selection bit 0 : General register 1 : Buffer register of TRDGRA0 registerBFC0 RW RW (b3 - b1) — Timer RD synchronous bit 0 : TRD0 and TRD1 registers operate independently 1 : TRD0 and TRD1 registers operate synchronously Nothing is assigned. If necessary, set to 0. When read, the content is 1. b7 b6 b5 b4 b3 b2 BFD0 b1 b0 SYNC Timer RD PWM Mode Register Symbol Address After Reset TRDPMR 0139h 10001000b Bit Symbol Bit Name Function RW Nothing is assigned. If necessary, set to 0. When read, the content is 1. PWM mode of TRDIOC1 selection bit 0 : Timer mode 1 : PWM mode PWMD1 PWM mode of TRDIOD1 selection bit 0 : Timer mode 1 : PWM mode (b7) — PWMB1 PWMC1 RW Nothing is assigned. If necessary, set to 0. When read, the content is 1. PWM mode of TRDIOD0 selection bit 0 : Timer mode 1 : PWM modePWMD0 RW PWM mode of TRDIOB1 selection bit 0 : Timer mode 1 : PWM mode RW RW RW PWMC0 RW PWM mode of TRDIOB0 selection bit 0 : Timer mode 1 : PWM mode PWM mode of TRDIOC0 selection bit 0 : Timer mode 1 : PWM mode b7 b6 b5 b4 b3 b2 (b3) b1 b0 PWMB0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 204 of 458 REJ09B0250-0200 Figure 14.66 TRDFCR Register in PWM Mode Timer RD Function Control Register Symbol Address After Reset TRDFCR 013Ah 10000000b Bit Symbol Bit Name Function RW NOTES: 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. b3 b2 OLS1 b1 b0 001 b7 b6 b5 b4 RW CMD1 RW Combination mode selection bit(1) Set to 00b (timer mode, PWM mode, or PWM3 mode) in PWM mode.CMD0 Normal-phase output level selection bit (in reset synchronous PWM mode or complementary PWM mode) This bit is disabled in PWM mode. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). OLS0 RW RW Counter-phase output level selection bit (in reset synchronous PWM mode or complementary PWM mode) This bit is disabled in PWM mode. A/D trigger enable bit (in complementary PWM mode) This bit is disabled in PWM mode. RW PWM3 RW AD TR G AD E G A/D trigger edge selection bit (in complementary PWM mode) This bit is disabled in PWM mode. RW PWM3 mode selection bit(2) Set this bit to 1 (other than PWM3 mode) in PWM mode. STCLK External clock input selection bit 0 : External clock input disabled 1 : External clock input enabled RW

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 205 of 458 REJ09B0250-0200 Figure 14.67 Registers TRDOER1 to TRDOER2 in PWM Mode Timer RD Output Master Enable Register 1 Symbol Address After Reset TRDOER1 013Bh FFh Bit Symbol Bit Name Function RW b3 b2 ED0 b1 b0 EA 0 b7 b6 b5 b4 RW EB0 RW TRDIOA0 output disable bit Set this bit to 1 (The TRDIOA0 pin is used as a programmable I/O mode) in PWM mode. TRDIOB0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOB0 pin is used as a programmable I/O mode.) RW TRDIOA1 output disable bit Set this bit to 1 (The TRDIOA0 pin is used as a programmable I/O mode) in PWM mode. RW RW TRDIOD0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOD0 pin is used as a programmable I/O mode.) TRDIOC1 output disable bit 0 : Enable output 1 : Disable output (The TRDIOC1 pin is used as a programmable I/O mode.) TRDIOC0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOC0 pin is used as a programmable I/O mode.) EC0 RW ED1 RW EA 1 EB1 RW TRDIOD1 output disable bit 0 : Enable output 1 : Disable output (The TRDIOD1 pin is used as a programmable I/O mode.) TRDIOB1 output disable bit 0 : Enable output 1 : Disable output (The TRDIOB1 pin is used as a programmable I/O mode.) EC1 Timer RD Output Master Enable Register 2 Symbol Address After Reset TRDOER2 013Ch 01111111b Bit Symbol Bit Name Function RW INT0 of pulse output forced 0 : Pulse output forced cutoff input disabled 1 : Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (disable output) w hen “L” is applied to the INT0 pin) NOTE: b3 b2 b1 b0b7 b6 b5 b4 Ref er to 14.3.4 Pulse Output Forced Cutoff . (b6 - b0) Nothing is assigned. When w rite, set to 0. When read, its content is 1. RWPTO cutoff signal input enabled bit(1)

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 206 of 458 REJ09B0250-0200 Figure 14.68 Registers TRDOCR and TRDCR0 to TRDCR1 in PWM Mode Timer RD Output Control Register(1) Symbol Address After Reset TRDOCR 013Dh 00h Bit Symbol Bit Name Function RW NOTES: TOA 1 TOB1 RW TRDIOD1 initial output level selection bit(2) TRDIOB1 initial output level selection bit(2) TOC1 TRDIOC1 initial output level selection bit (2) 0 : Initial output is inactive level 1 : Initial output is active level Set this bit to 0 (enable output) in PWM mode Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). TOC0 RW RW TRDIOA1 initial output level selection bit RW RW 0 : Inactive level 1 : Active level TRDIOD0 initial output level selection bit(2) TOD1 RW RW TOB0 RW TRDIOA0 output level selection bit Set this bit to 0 (enable output) in PWM mode TRDIOB0 output level selection bit(2) TRDIOC0 initial output level selection bit(2) TOA 0 b7 b6 b5 b4 When the pin functions are w aveform output (refer to Table 14.13 to 14.15; Table 14.17 to 14.19) and the TRDOCR register is set, the initial output level is output. b3 b2 TOD0 b1 b0 Timer RD Control Register i (i = 0 or 1) Symbol Address After Reset TRDCR0 TRDCR1 0140h 0150h 00h 00h Bit Symbol Bit Name Function RW NOTES: 2. This bit is enabled w hen the TCK2 to TCK0 bits are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). RW CKEG1 CCLR0 RWSet to 001b (the TRDi register clear at the compare match w ith TRDGRAi register) in PWM mode. TRDi counter clear selection bit This bit is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). b3 b2 CKEG0 b1 b0 TCK2 001 b7 b6 b5 b4 RW RW RW CCLR2 CCLR1 RW Count source selection bit b2 b1 b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : TRDCLK input (1) 1 1 0 : fOCO40M 1 1 1 : Do not set External clock edge selection bit(2) b4 b3 0 0 : Count at the rising edge 0 1 : Count at the falling edge 1 0 : Count at both edges 1 1 : Do not set RW TCK1 RW TCK0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 207 of 458 REJ09B0250-0200 Figure 14.69 Registers TRDSR0 to TRDSR1 in PWM Mode Timer RD Status Register i (i = 0 or 1) Symbol Address After Reset TRDSR0 TRDSR1 0143h 0153h 11100000b 11000000b Bit Symbol Bit Name Function RW NOTES: (b7 - b6) —Nothing is assigned. If necessary, set to 0. When read, the content is 1. RWOVF UDF Underflow flag(1) This bit is disabled in PWM mode. RW Input capture/compare match flag C [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRCi register.(3) Nothing is assigned to the bit 5 in the TRDSR0 register. When w riting to the bit 5, w rite 0. When reading, its content is IMFC RW RW Input capture/compare match flag D [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRDi register.(3) Overflow flag [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the TRDi register overflow s. RW IMFB RW Input capture/compare match flag A [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRAi register. Input capture/compare match flag B [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRBi register. IMFA b7 b6 b5 b4 Including w hen the BFji bit (j = C or D) in the TRDMR register is set to 1 (TRDGRji is used as the buffer register). The w riting results are as follow s:

• This bit is set to 0 w hen the read result is 1 and w riting 0 to the same bit.
• This bit remains unchanged even if the read result is 0 and w riting 0 to the same bit. (This bit remains 1 even if this bit is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged w hen w riting 1. b3 b2 IMFD b1 b0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 208 of 458 REJ09B0250-0200 Figure 14.70 Registers TRDIER0 to TRDIER1 in PWM Mode Timer RD Interrupt Enable Register i (i = 0 or 1) Symbol Address After Reset TRDIER0 TRDIER1 0144h 0154h 11100000b 11100000b Bit Symbol Bit Name Function RW RWOVIE (b7 - b5) —Nothing is assigned. If necessary, set to 0. When read, the content is 1. Input capture/compare match interrupt enable bit C 0 : Disable an interrupt (IMIC) by the IMFC bit 1 : Enable an interrupt (IMIC) by the IMFC bit IMIEC RW RW Input capture/compare match interrupt enable bit D 0 : Disable an interrupt (IMID) by the IMFD bit 1 : Enable an interrupt (IMID) by the IMFD bit Overflow /underflow interrupt enable bit 0 : Disable an interrupt (OVI) by the OVF bit 1 : Enable an interrupt (OVI) by the OVF bit RW IMIEB RW Input capture/compare match interrupt enable bit A 0 : Disable an interrupt (IMIA) by the IMFA bit 1 : Enable an interrupt (IMIA) by the IMFA bit Input capture/compare match interrupt enable bit B 0 : Disable an interrupt (IMIB) by the IMFB bit 1 : Enable an interrupt (IMIB) by the IMFB bit IMIEA b7 b6 b5 b4 b3 b2 IMIED b1 b0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 210 of 458 REJ09B0250-0200 Figure 14.73 Registers T RDGRAi, TRDGRBi, TRDGRCi and TRDGRDi in PWM Mode The following registers are disabled in the PWM mode: TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDIORA1 and TRDIORC1 i = 0 or 1 BFCi, BFDi: Bits in TRDMR register Table 14.28 TRDGRji Register Functions in PWM Mode Register Setting Register Function PWM Output Pin TRDGRAi − General register. Set the PWM period. − TRDGRBi − General register. Set the changing point of PWM output TRDIOBi TRDGRCi BFCi = 0 General register. Set th e changing point of PWM output TRDIOCi TRDGRDi BFDi = 0 TRDIODi TRDGRCi BFCi = 1 Buffer register. Set the next PWM period (refer to 14.3.2 Buffer Operation.) TRDGRDi BFDi = 1 Buffer register. Set the changing point of the next PWM output (refer to 14.3.2 Buffer Operation.) TRDIOBi Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1)(1) Symbol Address After Reset TRDGRA 0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA 1 TRDGRB1 TRDGRC1 TRDGRD1 0149h-0148h 014Bh-014Ah 014Dh-014Ch 014Fh-014Eh 0159h-0158h 015Bh-015Ah 015Dh-015Ch 015Fh-015Eh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh RW NOTE: (b8) (b15) b7 b0 b7 RW Function Ref er to Table 14.28 TRDGRji Register Functions in PWM Mode Access the TRDGRAi to TRDGRDi registers in 16-bit units. Do not access them in 8-bit units.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 211 of 458 REJ09B0250-0200 Figure 14.74 Operating Example of PWM Mode m n p Value in TRDi register Count source m + 1 n + 1 TRDIOCi output q m - n p + 1 m - p m - qq + 1 TRDIODi output m: Setting value in TRDGRAi register n: Setting value in TRDGRBi register p: Setting value in TRDGRCi register q: Setting value in TRDGRDi register Inactive Level “L”Active level “H” Inactive Level “H” Active level “L” Initial output “L” to compare match Initial output “H” to compare match Set to 0 by a program Set to 0 by a program Set to 0 by a program TRDIOBi output IMFA bit in TRDSRi register IMFB bit in TRDSRi register IMFC bit in TRDSRi register IMFD bit in TRDSRi register i = 0 or 1 Set to 0 by a program The above applies to the following conditions: The BFCi and BFDi bits in the TRDMR register are set to 0. (The TRDGRCi and TRDGRDi registers are not used as the buffer regist er.) The EBi, ECi and EDi bits in the TRDOER1 register are set to 0. (Enable TRDIOBi, TRDIOCi and TRDIODi pin outputs.) The TOBi and TOCi bits in the TRDOCR register are set to 0 (inactive level), the TODi bit is set to 1. (active level) The POLB bit in the TRDPOCRi register is set to 1 (active level “H”), the POLC and POLD bits are set to 0. (active level “L”) Initial output “L” to compare match

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 212 of 458 REJ09B0250-0200 Figure 14.75 Operating Example of PWM Mode (Duty 0%, Duty 100%) m p q Value in TRDi register n m: Setting value in TRDGRAi register Set to 0 by a program Rewrite by a program 0000h q Duty 0 % TRDGRBi register IMFA bit in TRDSRi register IMFB bit in TRDSRi register TSTARTi bit in TRDSTR register TRDIOBi output p (p > m)n Since the compare match in the TRDGRBi register is not generated, “L” is not applied to TRDIOBi output m p Value in TRDi register n 0000h TRDGRBi register IMFA bit in TRDSRi register IMFB bit in TRDSRi register TSTARTi bit in TRDSTR register TRDIOBi output pn “L” is applied to TRDIOBi output by the compare match in the TRDGRBi register with no change. m i = 0 or 1 The above applies to the following conditions: The EBi bit in the TRDOER1 register is set to 0. (Enable TRDIOBi output.) The POLB bit in the TRDPOCRi register is set to 0. (active level “L”) Rewrite by a program Set to 0 by a program Set to 0 by a program When the compare matches in the TRDGRAi and TRDGRBi registers are generated simultaneously, the compare match in t he TRDGRBi register has a priority. “L” is applied to TRDIOBi output without any change. Duty 100 % Set to 0 by a program

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 213 of 458 REJ09B0250-0200

14.3.8 Reset Synchronous PWM Mode

Output 3 normal-phases and 3 counter-phases of the PW M waveform with the same period (no three-phase, sawtooth wave modulation and dead time). Figure 14.76 shows the Block Diagram of Reset Synchronous PWM Mode, Table 14.29 lists the Reset Synchronous PWM Mode Specifications. Figures 14.77 to 14.84 show the Register s Associated with Reset Synchronous PWM Mode and Figure 14.85 shows the Operating Example of Reset Synchronous PWM Mode. Refer to Figure 14.75 Operating Example of PWM Mode (Duty 0%, Duty 100%) for the operation example in PWM Mode of duty 0% and duty 100%. Figure 14.76 Block Diagram of Reset Synchronous PWM Mode Period TRDIOC0 TRDIOB0 TRDIOD0 TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1 PWM1 PWM2 PWM3 Waveform control TRDGRB0 register TRDGRA1 register TRDGRB1 register Normal-phase Counter-phase TRDGRA0 register TRDGRD0 register TRDGRC1 register TRDGRD1 register TRDGRC0 register Buffer(1) Normal-phase Counter-phase Normal-phase Counter-phase NOTE: 1. When the BFC0, BFD0, BFC1 and BFD1 bits in the TRDMR register are set to 1 (buffer register).

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 214 of 458 REJ09B0250-0200 j = either A, B, C or D Table 14.29 Reset Synchronous PWM Mode Specifications Item Specification Count Sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Count Operations The TRD0 register is incremented (The TRD1 register is not used.) PWM Waveform PWM period: 1/fk × (m + 1) Active level width of normal-phase: 1/fk × (m - n) Active level width of counter-phase:1/fk × (n + 1) fk:Frequency of count source m:Setting value in the TRDGRA0 register n: Setting value in the TRDGRB0 register (PWM output 1), Setting value in the TRDGRA1 register (PWM output 2), Setting value in the TRDGRB1 register (PWM output 3) Count Start Condition Write 1 (count starts) to the TSTART0 bit in the TRDSTR register. Count Stop Conditions • Write 0 (count stops) to the TSTART0 bit in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1.

• The PWM output pin holds output level before the count stops
• When the CSEL0 bit in the TRDSTR register is set to 0, the count stops at the compare match in the TRDGRA0 register.
• The PWM output pin holds level after output change by the compare match. Interrupt Request Generation Timing
• Compare match (the content in the TRD0 register matches with the content in the TRDGRj0, TRDGRA1 and TRDGRB1 registers.)
• The TRD0 register overflows TRDIOA0 Pin Function Programmable I/O po rt or TRDCLK (external clock) input TRDIOB0 Pin Function PWM output 1 normal-phase output TRDIOD0 Pin Function PWM output 1 counter-phase output TRDIOA1 Pin Function PWM output 2 normal-phase output TRDIOC1 Pin Function PWM output 2 counter-phase output TRDIOB1 Pin Function PWM output 3 normal-phase output TRDIOD1 Pin Function PWM output 3 counter-phase output TRDIOC0 Pin Function Output in verted every period of PWM INT0 Pin Function Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input Read from Timer The count value can be read by reading the TRD0 register. Write to Timer The value can be written to the TRD0 register. Selection Functions • The active level of normal-phase and counter-phase and initial output level selected individually.
• Buffer operation (refer to 14.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (refer to 14.3.4 Pulse Output Forced Cutoff.) m + 1 Normal-phase n + 1 (When “L” is selected for the active level) Counter-phase m - n

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 215 of 458 REJ09B0250-0200 Figure 14.77 TRDSTR Register in Reset Synchronous PWM Mode Timer RD Start Register(1) Symbol Address After Reset TRDSTR 0137h 11111100b Bit Symbol Bit Name Function RW NOTES: (b7 - b4) N othing is assigned. I f necessary, set to 0. When read, the content is 1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1 TRDSTR Re gis te r of Note s on Tim e r RD. RW TRD1 count operation select bit 0 : Count stops at the compare match w ith the TRDGRA1 register 1 : Count continues at the compare match w ith the TRDGRA1 register TRD0 count operation select bit 0 : Count stops at the compare match w ith the TRDGRA0 register 1 : Count continues at the compare match w ith the TRDGRA0 register CSEL0 RW RW TSTART1 RW TRD1 count start flag (5) [This bit is not used in reset synchronous PWM mode] 0 : Count stops(3) 1 : Count starts TRD0 count start flag(4) 0 : Count stops(2) 1 : Count starts b7 b6 b5 b4 b3 b2 CSEL1 b1 b0 TSTART0 When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit. When the CSEL0 bit is set to 0 and generating the compare match signal(TRDIOA0), this bit is set to 0 (count stops). When the CSEL1 bit is set to 0 and generating the compare match signal(TRDIOA1), this bit is set to 0 (count stops).

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 216 of 458 REJ09B0250-0200 Figure 14.78 Registers TRDMR and TRDFCR in Reset Synchronous PWM Mode Timer RD Mode Register Symbol Address After Reset TRDMR 0138h 00001110b Bit Symbol Bit Name Function RW RW BFC1 BFD1 TRDGRD1 register function selection bit 0 : General register 1 : Buffer register of TRDGRB1 register TRDGRC0 register function selection bit 0 : General register 1 : Buffer register of TRDGRA0 registerBFC0 RW RWTRDGRD0 register function selection bit 0 : General register 1 : Buffer register of TRDGRB0 register TRDGRC1 register function selection bit 0 : General register 1 : Buffer register of TRDGRA1 register RW RW (b3 - b1) — Timer RD synchronous bit Set this bit to 0 (the TRD and TRD1 registers operate independently.) in reset synchronous PWM mode. N othing is assigned. I f necessary, set to 0. When read, the content is 1. b7 b6 b5 b4 b3 b2 BFD0 b1 b0 SYNC Timer RD Function Control Register Symbol Address After Reset TRDFCR 013Ah 10000000b Bit Symbol Bit Name Function RW NOTES: 3. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. b3 b2 OLS1 b1 b0 b7 b6 b5 b4 RW CMD1 RW Combination mode selection bit(1,2) Set to 01b (reset synchronous PWM mode) in reset synchronous PWM mode. CMD0 Normal-phase output level selection bit (in reset synchronous PWM mode or complementary PWM mode) 0 : Initial output “H” Active level “L” 1 : Initial output “L” Active level “H” Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). OLS0 RW RW Counter-phase output level selection bit (in reset synchronous PWM mode or complementary PWM mode) 0 : Initial output “H” Active level “L” 1 : Initial output “L” Active level “H” A/D trigger enable bit (in complementary PWM mode) This bit is disabled in reset synchronous PWM mode. RW PWM3 RW AD TR G AD E G A/D trigger edge selection bit (in complementary PWM mode) This bit is disabled in reset synchronous PWM mode. RW PWM3 mode selection bit(3) This bit is disabled in reset synchronous PWM mode. When bits CMD1 to CMD0 are set to 01b, 10b, or 11b, the MCU enters reset synchronous PWM mode or complementary PWM mode in spite of the setting of the TRDPMR register. STCLK External clock input selection bit 0 : External clock input disabled 1 : External clock input enabled RW

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 217 of 458 REJ09B0250-0200 Figure 14.79 Registers TRDOER1 to TRDOER2 in Reset Synchronous PWM Mode Timer RD Output Master Enable Register 1 Symbol Address After Reset TRDOER1 013Bh FFh Bit Symbol Bit Name Function RW ED1 RW EA 1 EB1 RW TRDIOD1 output disable bit 0 : Enable output 1 : Disable output (the TRDIOD1 pin is used as a programmable I/O port.) TRDIOB1 output disable bit 0 : Enable output 1 : Disable output (the TRDIOB1 pin is used as a programmable I/O port.) EC1 RW TRDIOA1 output disable bit 0 : Enable output 1 : Disable output (the TRDIOA1 pin is used as a programmable I/O port.) RW RW TRDIOD0 output disable bit 0 : Enable output 1 : Disable output (the TRDIOD0 pin is used as a programmable I/O port.) TRDIOC1 output disable bit 0 : Enable output 1 : Disable output (the TRDIOC1 pin is used as a programmable I/O port.) TRDIOC0 output disable bit 0 : Enable output 1 : Disable output (the TRDIOC0 pin is used as a programmable I/O port.) EC0 RW RW EB0 RW TRDIOA0 output disable bit Set this bit to 1 (the TRDIOA0 pin is used as a programmable I/O port) in reset synchronous PWM mode. TRDIOB0 output disable bit 0 : Enable output 1 : Disable output (the TRDIOB0 pin is used as a programmable I/O port.) b7 b6 b5 b4 b3 b2 ED0 b1 b0 EA 0 Timer RD Output Master Enable Register 2 Symbol Address After Reset TRDOER2 013Ch 01111111b Bit Symbol Bit Name Function RW INT0 of pulse output forced 0 : Pulse output forced cutoff input disabled 1 : Pulse output forced cutoff input enabled (all bits in the TRDOER1 register are set to 1 (disable output) w hen “L” is applied to the INT0 pin) NOTE: b3 b2 b1 b0b7 b6 b5 b4 Ref er to 14.3.4 Pulse Output Forced Cutoff . (b6 - b0) Nothing is assigned. If necessary, set to 0. When read, the content is 1. RWPTO cutoff signal input enabled bit(1)

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 218 of 458 REJ09B0250-0200 Figure 14.80 TRDCR0 Register in Reset Synchronous PWM Mode Timer RD Control Register 0(3) Symbol Address After Reset TRDCR0 0140h 00h Bit Symbol Bit Name Function RW NOTES: RW TCK1 RW TCK0 RW RW RW CCLR2 CCLR1 RW Count source selection bit b2 b1b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : TRDCLK input (1) 1 1 0 : fOCO40M 1 1 1 : Do not set External clock edge selection bit (2) b4 b3 0 0 : Count at the rising edge 0 1 : Count at the falling edge 1 0 : Count at both edges 1 1 : Do not set b7 b6 b5 b4 001 b3 b2 CKEG0 b1 b0 TCK2 The TRDCR1 register is not used in reset synchronous PWM mode. This bit is enabled w hen the TCK2 to TCK0 bits are set to “101b” (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). RW CKEG1 CCLR0 RWSet to 001b (TRD0 register clear at the compare match w ith TRDGRA0 register) in reset synchronous PWM mode. TRD0 counter clear selection bit This bit is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 219 of 458 REJ09B0250-0200 Figure 14.81 Registers TRDSR0 to TRDSR1 in Reset Synchronous PWM Mode Timer RD Status Register i (i = 0 or 1) Symbol Address After Reset TRDSR0 TRDSR1 0143h 0153h 11100000b 11000000b Bit Symbol Bit Name Function RW NOTES: (b7 - b6) —Nothing is assigned. If necessary, set to 0. When read, the content is 1. RWOVF UDF Underflow flag (1) This bit is disabled in reset synchronous PWM mode. RW Input capture/compare match flag C [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRCi register.(3) Nothing is assigned to the b5 in the TRDSR0 register. When w riting to the b5, w rite 0. When reading, its content is 1. IMFC RW RW Input capture/compare match flag D [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRDi register. (3) Overflow flag [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the TRDi register overflow s. RW IMFB RW Input capture/compare match flag A [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRAi register. Input capture/compare match flag B [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRBi register. IMFA b7 b6 b5 b4 Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register). The w riting results are as follow s:

• This bit is set to 0 w hen the read result is 1 and w riting 0 to the same bit.
• This bit remains unchanged even if the read result is 0 and w riting 0 to the same bit. (This bit remains 1 even if this bit is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged w hen w riting 1. b3 b2 IMFD b1 b0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 221 of 458 REJ09B0250-0200 Figure 14.84 Registers TRDGRAi , TRDGRBi, TRDGRCi and TRDGRDi in Reset Synchronous PWM Mode The following registers are disabled in the reset synchronous PWM mode: TRDPMR, TRDOCR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1 and TRDPOCR1 BFC0, BFD0, BFC1, BFD1: Bits in TRDMR Register Table 14.30 TRDGRji Register Functions in Reset Synchronous PWM Mode Register Setting Register Function PWM Output Pin TRDGRA0 − General register. Set the PWM period. (Output inverted every period of TRDIOC0 and PWM pins) TRDGRB0 − General register. Set the changing point of PWM1 output. TRDIOB0 TRDIOD0 TRDGRC0 BFC0 = 0 (These registers are not used in reset synchronous PWM mode.) TRDGRD0 BFD0 = 0 TRDGRA1 − General register. Set the changing point of PWM2 output. TRDIOA1 TRDIOC1 TRDGRB1 − General register. Set the changing point of PWM3 output. TRDIOB1 TRDIOD1 TRDGRC1 BFC1 = 0 (These points are not used in reset synchronous PWM mode.) TRDGRD1 BFD1 = 0 TRDGRC0 BFC0 = 1 Buffer register. Set the next PWM period. (Refer to 14.3.2 Buffer Operation) (Output inverted every period of TRDIOC0 and PWM pins) TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of the next PWM1 output. (Refer to 14.3.2 Buffer Operation) TRDIOB0 TRDIOD0 TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of the next PWM2 output. (Refer to 14.3.2 Buffer Operation) TRDIOA1 TRDIOC1 TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of the next PWM3 output. (Refer to 14.3.2 Buffer Operation) TRDIOB1 TRDIOD1 Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1)(1) Symbol Address After Reset TRDGRA 0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA 1 TRDGRB1 TRDGRC1 TRDGRD1 0149h-0148h 014Bh-014Ah 014Dh-014Ch 014Fh-014Eh 0159h-0158h 015Bh-015Ah 015Dh-015Ch 015Fh-015Eh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh RW NOTE: RW Function Ref er to Table 14.30 TRDGRji Register Functions in Reset Synchronous PWM Mode Access the TRDGRAi to TRDGRDi registers in 16-bit units. Do not access them in 8-bit units. b0b7 (b8) (b15)

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 222 of 458 REJ09B0250-0200 Figure 14.85 Operating Example of Reset Synchronous PWM Mode Initial output “H” Active level “L” m n p Value in TRD0 register Count source m + 1 TRDIOD0 output q m - n TRDIOD1 output m: Setting value in TRDGRA0 register n: Setting value in TRDGRB0 register p: Setting value in TRDGRA1 register q: Setting value in TRDGRB1 register Active level “L” Set to 0 by a program TRDIOB0 output IMFA bit in TRDSR0 register IMFB bit in TRDSR0 register IMFA bit in TRDSR1 register IMFB bit in TRDSR1 register TSTARTi bit in TRDSTR register n + 1 TRDIOC1 output TRDIOA1 output m - q m - p TRDIOB1 output TRDIOC0 output p + 1 Initial output “H” i = 0 or 1 The above applies to the following conditions: The OLS1 and OLS0 bits in the TRDFCR register are set to 0. (initial output level “H”, active level “L”) 0000h Set to 0 by a program Set to 0 by a program Set to 0 by a program Transfer from the buffer register to the general register at the buffer operation Transfer from the buffer register to the general register at the buffer operation q + 1

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 223 of 458 REJ09B0250-0200

14.3.9 Complementary PWM Mode

Output 3 normal-phases and 3 counter -phases of the PWM waveform with the same period (with three-phase, triangular wave modulation and dead time). Figure 14.86 shows the Block Diagram of Complementary PWM Mode, Table 14.31 lists the Complementary PWM Mode Specifications. Figures 14.87 to 14.95 show the Registers Associated with Complementary PWM Mode, Figure 14.96 shows the Output Model of Complementary PWM Mode and Figure 14.97 shows the Operating Example of Complementary PWM Mode. Figure 14.86 Block Diagram of Complementary PWM Mode Period TRDIOC0 TRDIOB0 TRDIOD0 TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1 PWM1 PWM2 PWM3 Waveform control TRDGRB0 register TRDGRA1 register TRDGRB1 register Normal-phase Counter-phase TRDGRA0 register TRDGRD0 register TRDGRC1 register TRDGRD1 register Buffer Normal-phase Counter-phase Normal-phase Counter-phase

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 224 of 458 REJ09B0250-0200 i = 0 or 1, j = either A, B, C or D NOTE: 1. After a count starts, the PWM period is stable. Table 14.31 Complementary PWM Mode Specifications Item Specification Count Sources f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Set the TCK2 to TCK0 bits in the TRDCR1 register to the same value (same count source) as the TCK2 to TCK0 bits in the TRDCR0 register. Count Operations Increment or decrement The TRD0 and TRD1 registers are decremented with the compare match in the TRD0 and TRDGRA0 registers during increment. The TRD1 register is set from 0000h to FFFFh during decrement, the TRD0 and TRD1 registers are incremented. PWM Operations PWM period: 1/fk × (m + 2 - p) × 2 (1) Dead time: p Active level width of normal-phase: 1/fk × (m - n - p + 1) × 2 Active level width of counter-phase: 1/fk × (n + 1 - p) × 2 fk: Frequency of count source m: Setting value in the TRDGRA0 register n: Setting value in the TRDGRB0 register (PWM output 1) Setting value in the TRDGRA1 register (PWM output 2) Setting value in the TRDGRB1 register (PWM output 3) p: Setting value in the TRD0 register Count Start Condition Write 1 (count starts) to the TSTART0 and TSTART1 bits in the TRDSTR register. Count Stop Conditions Write 0 (count stops) to the TSTART0 and TSTART1 bits in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1. (The PWM output pin holds output level before the count stops.) Interrupt Request Generation Timing

• Compare match (the content in the TRDi register matches with the content in the TRDGRji register.)
• The TRD1 register undeflows TRDIOA0 Pin Function Programmable I/O port or TRDCLK (external clock) input TRDIOB0 Pin Function PWM output 1 normal-phase output TRDIOD0 Pin Function PWM output 1 counter-phase output TRDIOA1 PIn Function PWM output 2 normal-phase output TRDIOC1 Pin Function PWM output 2 counter-phase output TRDIOB1 Pin Function PWM output 3 normal-phase output TRDIOD1 Pin Function PWM output 3 counter-phase output TRDIOC0 Pin Function Output inversed every 1/2 period of PWM INT0 Pin Function Programmable I/O port, pulse ou tput forced cutoff signal input or INT0 interrupt input Read from Timer The count value can be read by reading the TRDi register. Write to Timer The value can be written to the TRDi register. Selection Functions • Pulse output forced cutoff signal input (refer to

14.3.4 Pulse Output Forced

Cutoff)

• The active level of normal-phase and counter-phase and initial output level selected individually.
• Transfer timing from the buffer register selected
• A/D trigger generated n + 1 Normal-phase (When “L” is selected for the active level) Counter-phase m + 2 - p n + 1 - p p m - p - n + 1

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 225 of 458 REJ09B0250-0200 Figure 14.87 TRDSTR Register in Complementary PWM Mode Timer RD Start Register(1) Symbol Address After Reset TRDSTR 0137h 11111100b Bit Symbol Bit Name Function RW NOTES: When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit. When the CSEL0 bit is set to 0 and generating the compare match signal(TRDIOA0), this bit is set to 0 (count stops). When the CSEL1 bit is set to 0 and generating the compare match signal(TRDIOA1), this bit is set to 0 (count stops). Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1 TRDSTR Re gis te r of Notes on Timer RD. TRD0 count operation select bit 0 : Count stops at the compare match w ith the TRDGRA0 register 1 : Count continues at the compare match w ith the TRDGRA0 register CSEL0 RW RW TRD1 count operation select bit 0 : Count stops at the compare match w ith the TRDGRA1 register 1 : Count continues at the compare match w ith the TRDGRA1 register (b7 - b4) RW TSTART1 RWTRD1 count start flag (5) 0 : Count stops(3) 1 : Count starts TRD0 count start flag(4) 0 : Count stops(2) 1 : Count starts Nothing is assigned. If necessary, set to 0. When read, the content is 1. b7 b6 b5 b4 b3 b2 CSEL1 b1 b0 TSTART0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 226 of 458 REJ09B0250-0200 Figure 14.88 TRDMR Register in Complementary PWM Mode Timer RD Mode Register Symbol Address After Reset TRDMR 0138h 00001110b Bit Symbol Bit Name Function RW RWBFC1 BFD1 TRDGRD1 register function selection bit 0 : General register 1 : Buffer register of TRDGRB1 register RW TRDGRC0 register function selection bit Set this bit to 0 (general register) in complementary PWM mode.BFC0 RW RWTRDGRD0 register function selection bit 0 : General register 1 : Buffer register of TRDGRB0 register TRDGRC1 register function selection bit 0 : General register 1 : Buffer register of TRDGRA1 register RW (b3 - b1) — Timer RD synchronous bit Set this bit to 0 (The TRD0 and TRD1 registers operate independently.) in complementary PWM mode. Nothing is assigned. If necessary, set to 0. When read, the content is 1. b7 b6 b5 b4 b3 b2 BFD0 b1 b0 SYNC

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 227 of 458 REJ09B0250-0200 Figure 14.89 TRDFCR Register in Complementary PWM Mode Timer RD Function Control Register Symbol Address After Reset TRDFCR 013Ah 10000000b Bit Symbol Bit Name Function RW NOTES: 4. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. b3 b2 OLS1 b1 b0b7 b6 b5 b4 RW CMD1 RW Combination mode selection bit(1,2) b1 b0 1 0 : Complementary PWM mode (transfer from the buffer register to the general register at the underflow in the TRD1 register.) 1 1 : Complementary PWM mode (transfer from the buffer register to the general register at the compare match w ith the TRD0 and TRDGRA0 registers.) Other than above : Do not set CMD0 Normal-phase output level selection bit (in reset synchronous PWM mode or complementary PWM mode) 0 : Initial output “H” Active level “L” 1 : Initial output “L” Active level “H” Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). OLS0 RW RW Counter-phase output level selection bit (in reset synchronous PWM mode or complementary PWM mode) 0 : Initial output “H” Active level “L” 1 : Initial output “L” Active level “H” A/D trigger enable bit (in complementary PWM mode) 0 : Disable A/D trigger 1 : Enable A/D trigger (3) RW PWM3 RW AD TR G AD E G A/D trigger edge selection bit (in complementary PWM mode) 0 : A/D trigger is generated at the compare match in the TRD0 and TRDGRA0 register 1 : A/D trigger is generated at the underflow in the TRD1 register RW PWM3 mode selection bit (4) This bit is disabled in complementary PWM mode. Set the ADCAP bit in the ADC0N0 register to 1 (starts by timer RD). When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the setting of the TRDPMR register. STCLK External clock input selection bit 0 : External clock input disabled 1 : External clock input enabled RW

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 228 of 458 REJ09B0250-0200 Figure 14.90 Registers TRDOER1 to TRDOER2 in Complementary PWM Mode Timer RD Output Master Enable Register 1 Symbol Address After Reset TRDOER1 013Bh FFh Bit Symbol Bit Name Function RW 0 : Enable output 1 : Disable output (The TRDIOB1 pin is used as a programmable I/O port.) EC1 TRDIOC1 output disable bit 0 : Enable output 1 : Disable output (The TRDIOC1 pin is used as a programmable I/O port.) TRDIOD0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOD0 pin is used as a programmable I/O port.) ED1 RW EA 1 EB1 RW TRDIOD1 output disable bit 0 : Enable output 1 : Disable output (The TRDIOD1 pin is used as a programmable I/O port.) TRDIOB1 output disable bit TRDIOC0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOC0 pin is used as a programmable I/O port.) EC0 RW RW TRDIOA1 output disable bit 0 : Enable output 1 : Disable output (The TRDIOA1 pin is used as a programmable I/O port.) RW RW RW EB0 RW TRDIOA0 output disable bit Set this bit to 1 (The TRDIOA0 pin is used as a programmable I/O port) in complementary PWM mode. TRDIOB0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOB0 pin is used as a programmable I/O port.) b7 b6 b5 b4 b3 b2 ED0 b1 b0 EA 0 Timer RD Output Master Enable Register 2 Symbol Address After Reset TRDOER2 013Ch 01111111b Bit Symbol Bit Name Function RW INT0 of pulse output forced 0 : Pulse output forced cutoff input disabled cutoff signal input enabled bit(1) 1 : Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (disable output) w hen “L” is applied to the INT0 pin) NOTE: (b6 - b0) Nothing is assigned. If necessary, set to 0. When read, the content is 1. RWPTO b7 b6 b5 b4 Ref er to 14.3.4 Pulse Output Forced Cutoff . b3 b2 b1 b0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 229 of 458 REJ09B0250-0200 Figure 14.91 Registers TRDCR0 to TRDCR1 in Complementary PWM Mode Timer RD Control Register i (i = 0 or 1) Symbol Address After Reset TRDCR0 TRDCR1 0140h 0150h 00h 00h Bit Symbol Bit Name Function RW NOTES: RW TCK1 RW TCK0 RW RW RW CCLR2 CCLR1 RW Count source selection bit (2) b2 b1 b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : TRDCLK input (1) 1 1 0 : fOCO40M 1 1 1 : Do not set External clock edge selection bit(2,3) b4 b3 0 0 : Count at the rising edge 0 1 : Count at the falling edge 1 0 : Count at both edges 1 1 : Do not set b7 b6 b5 b4 000 b3 b2 CKEG0 b1 b0 TCK2 This bit is enabled w hen the TCK2 to TCK0 bits are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). RW CKEG1 CCLR0 RWSet to 000b (disable clear (free-running operation)) in complementary PWM mode. TRDi counter clear selection bit This bit is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). Set the TCK2 to TCK0 bits and CKEG1 to CKEG0 bits in the TRDCR0 and TRDCR1 registers to the same values.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 230 of 458 REJ09B0250-0200 Figure 14.92 Registers TRDSR0 to TRDSR1 in Complementary PWM Mode Timer RD Status Register i (i = 0 or 1) Symbol Address After Reset TRDSR0 TRDSR1 0143h 0153h 11100000b 11000000b Bit Symbol Bit Name Function RW NOTES: b3 b2 IMFD b1 b0b7 b6 b5 b4 RW IMFB RW Input capture/compare match flag A [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRAi register. Input capture/compare match flag B [Source for setting this bit to 0] Write 0 after read. (2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRBi register. IMFA Input capture/compare match flag C [Source for setting this bit to 0] Write 0 after read. (2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRCi register.(3) Nothing is assigned to the bit 5 in the TRDSR0 register. When w riting to the bit 5, w rite 0. When reading, its content is IMFC RW RW Input capture/compare match flag D [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRDi register.(3) Overflow flag [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the TRDi register overflow s. RWOVF UDF Underflow flag(1) [Source for setting this bit to 0] Write 0 after read.(2) [Source for setting this bit to 1] When the TRD1 register underflow s. RW Including w hen the BFji (j = C or D) bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register). (b7 - b6) —Nothing is assigned. If necessary, set to 0. When read, the content is 1. The w riting results are as follow s:

• This bit is set to 0 w hen the read result is 1 and w riting 0 to the same bit.
• This bit remains unchanged even if the read result is 0 and w riting 0 to the same bit. (This bit remains 1 even if this bit is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged w hen w riting 1.

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 231 of 458 REJ09B0250-0200 Figure 14.93 Registers TRDIER0 to TRDIER1 in Complementary PWM Mode Timer RD Interrupt Enable Register i (i = 0 or 1) Symbol Address After Reset TRDIER0 TRDIER1 0144h 0154h 11100000b 11100000b Bit Symbol Bit Name Function RW RWOVIE (b7 - b5) —Nothing is assigned. If necessary, set to 0. When read, the content is 1. Input capture/compare match interrupt enable bit C 0 : Disable an interrupt (IMIC) by the IMFC bit 1 : Enable an interrupt (IMIC) by the IMFC bit IMIEC RW RW Input capture/compare match interrupt enable bit D 0 : Disable an interrupt (IMID) by the IMFD bit 1 : Enable an interrupt (IMID) by the IMFD bit Overflow /underflow interrupt enable bit 0 : Disable an interrupt (OVI) by the OVF and UDF bits 1 : Enable an interrupt (OVI) by the OVF and UDF bits RW IMIEB RW Input capture/compare match interrupt enable bit A 0 : Disable an interrupt (IMIA) by the IMFA bit 1 : Enable an interrupt (IMIA) by the IMFA bit Input capture/compare match interrupt enable bit B 0 : Disable an interrupt (IMIB) by the IMFB bit 1 : Enable an interrupt (IMIB) by the IMFB bit IMIEA b7 b6 b5 b4 b3 b2 IMIED b1 b0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 233 of 458 REJ09B0250-0200 BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register Since values cannot be written to the TRDGRB0, TRDGRA1, or TRDGRB1 register directly after count operation starts (prohibited item), use the TRDGRD0, TRDGRC1, or TRDGRD1 register as a buffer register. However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register). Table 14.32 TRDGRji Register Functions in Complementary PWM Mode Register Setting Register Function PWM Output Pin TRDGRA0 − General register. Set the PWM period at initialization. Setting range: Setting value or above in TRD0 register FFFFh - TRD0 register setting value or below Do not write when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). (Output inversed every half period of TRDIOC0 pin) TRDGRB0 − General register. Set the changing point of PWM1 output at initialization. Setting range: Setting value or above in TRD0 register TRDGRA0 register - TRD0 register setting value or below Do not write when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). TRDIOB0 TRDIOD0 TRDGRA1 − General register. Set the changing point of PWM2 output at initialization. Setting range: Setting value or above in TRD0 register TRDGRA0 register - TRD0 register setting value or below Do not write when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). TRDIOA1 TRDIOC1 TRDGRB1 − General register. Set the changing point of PWM3 output at initialization. Setting range: Setting value or above in TRD0 register TRDGRA0 register - TRD0 register setting value or below Do not write when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). TRDIOB1 TRDIOD1 TRDGRC0 − These registers not used in complementary PWM mode. − TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of next PWM1 output. (Refer to 14.3.2 Buffer Operation) Setting range: Setting value or above in TRD0 register TRDGRA0 register - TRD0 register setting value or below Set this register to the same value as the TRDGRB0 register for the initialization. TRDIOB0 TRDIOD0 TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of next PWM2 output. (Refer to

14.3.2 Buffer Operation)

Setting range: Setting value or above in TRD0 register TRDGRA0 register - TRD0 register setting value or below Set this register to the same value as the TRDGRA1 register for the initialization. TRDIOA1 TRDIOC1 TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of next PWM3 output. (Refer to Setting range: Setting value or above in TRD0 register TRDGRA0 register - TRD0 register setting value or below Set this register to the same value as the TRDGRB1 register for the initialization. TRDIOB1 TRDIOD1

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 234 of 458 REJ09B0250-0200 Figure 14.96 Output Model of Complementary PWM Mode Value in TRDi register TRDIOD0 output 0000h Value in TRDGRA0 register Value in TRDGRB0 register Value in TRDGRA1 register Value in TRDGRB1 register TRDIOB0 output TRDIOC1 output TRDIOA1 output TRDIOD1 output TRDIOB1 output TRDIOC0 output Value in TRD0 register Value in TRD1 register i = 0 or 1

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 235 of 458 REJ09B0250-0200 Figure 14.97 Operating Example of Complementary PWM Mode m + 2 - p p n + 1 n + 1 - p p n + 1 - p n n n m - p - n + 1 m n Value in TRDi register Count source TRDIOD0 output p m: Setting Value in TRDGRA0 register n: Setting Value in TRDGRB0 register p: Setting Value in TRD0 register TRDIOB0 output IMFA bit in TRDSR0 register TRDGRB0 register TSTART0 and TSTART1 bits in TRDSTR register TRDIOC0 output 0000h m + 1 Width of normal- phase active level Dead time (n + 1 - p) × 2 Width of counter-phase active level Set to FFFFh UDF bit in TRDSR1 register Following data Modify with a program TRDGRD0 register Transfer (When the CMD1 to CMD0 bits are set to 11b) Transfer (When the CMD1 to CMD0 bits are set to 10b) Value in TRD1 register Value in TRD0 register CMD0, CMD1: Bits in TRDFCR register i = 0 or 1 The above applies to the following conditions: The OLS1 and OLS0 bits in the TRDFCR are set to 0 (initial output level “H”, active level “L” for normal-phase and counter-phase) Set to 0 by a program Active level “L” Initial output “H” Initial output “H” Set to 0 by a program Set to 0 by a programIMFB bit in TRDSR0 register

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 236 of 458 REJ09B0250-0200

14.3.9.1 Transfer Timing from Buffer Register

• Transfer from the TRDGRD0, TRDGRC1 and TRDGRD1 registers to the TRDGRB0, TRDGRA1 and TRDGRB1 registers When the CMD1 to CMD0 bits in the TRDFCR register are set to 10b, the content is transferred when the TRD1 register underflows. When the CMD1 to CMD0 bits are set to 11b, the content is transferred at the compare match in the TRD0 and TRDGRA0 registers.

14.3.9.2 A/D Trigger Generation

The compare match in the TRD0 and TRDGRA0 regist ers and the TRD1 underflow can be used as a conversion start trigger of the A/D converter. It can be selected by the ADEG and ADTRG bits in the TRDFCR register. Also, set the ADCAP bit in the ADCON0 register to 1 (starts in Timer RD).

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 237 of 458 REJ09B0250-0200

14.3.10 PWM3 Mode

Output 2 PWM waveforms with the same period. Figure 14.98 shows the Block Diagram of PWM3 Mode, Table 14.33 lists the PWM3 Mode Specifications. Figures 14.99 to 14.107 show the Registers Associated with PWM3 Mode and Figure 14.108 shows the Operating Example of PWM3 Mode. Figure 14.98 Block Diagram of PWM3 Mode TRDIOA0 Output control TRDGRC0 Compare match signal TRDIOB0 Output control Comparator TRDGRA0TRD0 TRDGRC1 Compare match signal Comparator TRDGRA1 TRDGRD0Comparator TRDGRB0 TRDGRD1Comparator TRDGRB1 Compare match signal Compare match signal Buffer

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 238 of 458 REJ09B0250-0200 i = 0 or 1, j = either A, B, C or D Table 14.33 PWM3 Mode Specifications Item Specification Count Sources f1, f2, f4, f8, f32, fOCO40M Count Operations The TRD0 register is incremented. (The TRD1 is not used.) PWM Waveform PWM period: 1/fk × (m + 1) Active level width of TRDIOA0 output: 1/fk × (m - n) Active level width of TRDIOB0 output: 1/fk × (p - q) fk: Frequency of count source m: Setting value in the TRDGRA0 register n: Setting value in the TRDGRA1 register p: Setting value in the TRDGRB0 register q: Setting value in the TRDGRB1 register Count Start Condition Write 1 (count starts) to the TSTART0 bit in the TRDSTR register. Count Stop Conditions • Write 0 (count stops) to the TSTART0 bit in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1.

• The PWM output pin holds output level before the count stops
• When the CSEL0 bit in the TRDSTR register is set to 0, the count stops at the compare match in the TRDGRA0 register.
• The PWM output pin holds level after output change by the compare match. Interrupt Request Generation Timing
• Compare match (the content in the TRDi register matches with the content in the TRDGRji register.)
• The TRD0 register overflows TRDIOA0, TRDIOB0 Pin Functions PWM output TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 Pin Functions Programmable I/O port INT0 Pin Function Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input Read from Timer The count value can be read by reading the TRD0 register. Write to Timer The value can be written to the TRD0 register. Selection Functions • Pulse output forced cutoff signal input (refer to 14.3.4 Pulse Output Forced Cutoff)
• Select the active level every pin.
• Buffer operation (refer to 14.3.2 Buffer Operation) m + 1 TRDIOA0 output TRDIOB0 output (When “H” is selected for the active level) p - q m - n n + 1 p + 1 q + 1

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 239 of 458 REJ09B0250-0200 Figure 14.99 TRDSTR Register in PWM3 Mode Timer RD Start Register(1) Symbol Address After Reset TRDSTR 0137h 11111100b Bit Symbol Bit Name Function RW NOTES: (b7 - b4) Nothing is assigned. If necessary, set to 0. When read, the content is 1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1 TRDSTR Re gis te r of Notes on Timer RD. RW TRD1 count operation select bit 0 : Count stops at the compare match w ith the TRDGRA1 register 1 : Count continues at the compare match w ith the TRDGRA1 register TRD0 count operation select bit 0 : Count stops at the compare match w ith the TRDGRA0 register 1 : Count continues at the compare match w ith the TRDGRA0 register CSEL0 RW RW TSTART1 RWTRD1 count start flag (5) Set this bit to 0 (count stops) in PWM3 mode(3) TRD0 count start flag(4) 0 : Count stops(2) 1 : Count starts b7 b6 b5 b4 b3 b2 CSEL1 b1 b0 TSTART0 When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit. When the CSEL0 bit is set to 0 and generating the compare match signal(TRDIOA0), this bit is set to 0 (count stops). When the CSEL1 bit is set to 0 and generating the compare match signal(TRDIOA1), this bit is set to 0 (count stops).

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 240 of 458 REJ09B0250-0200 Figure 14.100 Registers TRDMR and TRDFCR in PWM3 Mode Timer RD Mode Register Symbol Address After Reset TRDMR 0138h 00001110b Bit Symbol Bit Name Function RW b3 b2 BFD0 b1 b0 SYNC b7 b6 b5 b4 RW (b3 - b1) — Timer RD synchronous bit This bit is disabled in PWM3 mode. Nothing is assigned. If necessary, set to 0. When read, the content is 1. RWTRDGRD0 register function selection bit 0 : General register 1 : Buffer register of TRDGRB0 register TRDGRC1 register function selection bit 0 : General register 1 : Buffer register of TRDGRA1 register RW TRDGRC0 register function selection bit 0 : General register 1 : Buffer register of TRDGRA0 registerBFC0 RW RW BFC1 BFD1 TRDGRD1 register function selection bit 0 : General register 1 : Buffer register of TRDGRB1 register Timer RD Function Control Register Symbol Address After Reset TRDFCR 013Ah 10000000b Bit Symbol Bit Name Function RW NOTES: STCLK External clock input selection bit Set this bit to 0 (external clock input disabled) in PWM3 mode. RW RW PWM3 RW AD TR G AD E G A/D trigger edge selection bit (enabled in complementary PWM mode) This bit is disabled in PWM3 mode. RW PWM3 mode selection bit (2) Set this bit to 0 (PWM3 mode) in PWM3 mode. Normal-phase output level selection bit (enabled in reset synchronous PWM mode or complementary PWM mode) This bit is disabled in PWM3 mode. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). OLS0 RW RW Counter-phase output level selection bit (enabled in reset synchronous PWM mode or complementary PWM mode) This bit is disabled in PWM3 mode. A/D trigger enable bit (enabled in complementary PWM mode) This bit is disabled in PWM3 mode. RW CMD1 RW Combination mode selection bit(1) Set to 00b (timer mode, PWM mode, or PWM3 mode) in PWM3 mode.CMD0 b7 b6 b5 b4 When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled. b3 b2 OLS1 b1 b0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 241 of 458 REJ09B0250-0200 Figure 14.101 Registers TRDOER1 to TRDOER2 in PWM3 Mode Timer RD Output Master Enable Register 1 Symbol Address After Reset TRDOER1 013Bh FFh Bit Symbol Bit Name Function RW ED1 RW EA 1 EB1 RW TRDIOD1 output disable bit TRDIOB1 output disable bit EC1 TRDIOC1 output disable bit TRDIOD0 output disable bit RW TRDIOA1 output disable bit RW RW Set these bits to 1 (programmable I/O port) in PWM3 mode. TRDIOC0 output disable bitEC0 RW RW EB0 RW TRDIOA0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOA0 pin is used as a programmable I/O port.) TRDIOB0 output disable bit 0 : Enable output 1 : Disable output (The TRDIOB0 pin is used as a programmable I/O port.) 1111 b7 b6 b5 b4 b3 b2 ED0 b1 b0 EA 0 Timer RD Output Master Enable Register 2 Symbol Address After Reset TRDOER2 013Ch 01111111b Bit Symbol Bit Name Function RW INT0 of pulse output forced 0 : Pulse output forced cutoff input disabled 1 : Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (disable output) w hen “L” is applied to the INT0 pin) NOTE: 1. Refer to 14.3.4 Pulse Output Forced Cutoff . (b6 - b0) Nothing is assigned. If necessary, set to 0. When read, the content is 1. RWPTO cutoff signal input enabled bit(1) b7 b6 b5 b4 b3 b2 b1 b0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 242 of 458 REJ09B0250-0200 Figure 14.102 TRDOCR Register in PWM3 Mode Timer RD Output Control Register(1) Symbol Address After Reset TRDOCR 013Dh 00h Bit Symbol Bit Name Function RW NOTES: 2. When the pin functions are w aveform output (refer to Table 14.12 and 14.13) and the TRDOCR register is set, the initial output level is output. TOA1 TOB1 RW TRDIOD1 initial output level selection bit TRDIOB1 initial output level selection bit TOC1 TRDIOC1 initial output level selection bit This bit is disabled in PWM3 mode.TRDIOC0 initial output level selection bit Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). TOC0 RW RW TRDIOA1 initial output level selection bit RW RW TRDIOD0 initial output level selection bit TOD1 RW RW TOB0 RW TRDIOA0 output level selection bit(2) 0 : Active level “H”, initial output “L”, output “H” by the compare match in the TRDGRA1register, output “L” by the compare match in the TRDGRA0 register 1 : Active level “L”, initial output “H”, output “L” by the compare match in the TRDGRA1register, output “H” by the compare match in the TRDGRA0 register TRDIOB0 output level selection bit (2) 0 : Active level “H”, initial output “L”, output “H” by the compare match in the TRDGRB1register, output “L” by the compare match in the TRDGRB0 register 1 : Active level “L”, initial output “H”, output “L” by the compare match in the TRDGRB1register, output “H” by the compare match in the TRDGRB0 register b7 b6 b5 b4 b3 b2 TOD0 b1 b0 TOA0

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 243 of 458 REJ09B0250-0200 Figure 14.103 TRDCR0 Register in PWM3 Mode Timer RD Control Register i (i = 0 or 1)(2) Symbol Address After Reset TRDCR0 0140h 00h Bit Symbol Bit Name Function RW NOTES: RW TCK1 RW TCK0 RW RW RW CCLR2 CCLR1 RW Count source selection bit b2 b1b0 0 0 0 : f1 0 0 1 : f2 0 1 0 : f4 0 1 1 : f8 1 0 0 : f32 1 0 1 : Do not set 1 1 0 : fOCO40M 1 1 1 : Do not set External clock edge selection bit (1) This bit is disabled in PWM3 mode. b7 b6 b5 b4 001 b3 b2 CKEG0 b1 b0 TCK2 The TRDCR1 register is not used in PWM3 mode. RW CKEG1 CCLR0 RWSet to 001b (the TRD0 register clear at the compare match w ith TRDGRA0 register) in PWM3 mode. TRD0 counter clear selection bit This bit is enabled w hen the TCK2 to TCK0 bits are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 244 of 458 REJ09B0250-0200 Figure 14.104 Registers TRDSR0 and TRDSR1 in PWM3 Mode Timer RD Status Register i (i = 0 or 1) Symbol Address After Reset TRDSR0 0143h 11100000b TRDSR1 0153h 11000000b Bit Symbol Bit Name Function RW NOTES: IMFD b1 b0 RW b7 b6 b5 b4 b3 RW IMFB RW Input capture/compare match flag A [Source for setting this bit to 0] Write 0 after read.(1) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRAi register. Input capture/compare match flag B [Source for setting this bit to 0] Write 0 after read. (1) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRBi register. IMFA OVF Input capture/compare match flag C [Source for setting this bit to 0] Write 0 after read. (1) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRCi register. (2) IMFC Overflow flag [Source for setting this bit to 0] Write 0 after read.(1) [Source for setting this bit to 1] When the TRDi register overflow s. RW RW Input capture/compare match flag D [Source for setting this bit to 0] Write 0 after read.(1) [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRDi register. (2) Including w hen the BFji bit (j = C or D) in the TRDMR register is set to 1 (TRDGRji is used as the buffer register). (b7 - b6) —Nothing is assigned. If necessary, set to 0. When read, the content is 1. The w riting results are as follow s:

• This bit is set to 0 w hen the read result is 1 and w riting 0 to the same bit.
• This bit remains unchanged even if the read result is 0 and w riting 0 to the same bit. (This bit remains 1 even if this bit is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged w hen w riting 1. UDF Underflow flag (1) This bit is disabled in PWM3 mode. RW

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 246 of 458 REJ09B0250-0200 Figure 14.107 Registers T RDGRAi, TRDGRBi, TRDGRCi and TRDGRDi in PWM3 Mode The following registers are disabled in PWM3 mode: TRDPMR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1 and TRDPOCR1 Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1)(1) Symbol Address After Reset TRDGRA 0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA 1 TRDGRB1 TRDGRC1 TRDGRD1 0149h-0148h 014Bh-014Ah 014Dh-014Ch 014Fh-014Eh 0159h-0158h 015Bh-015Ah 015Dh-015Ch 015Fh-015Eh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh RW NOTE: RW Function Ref er to Table 14.34 TRDGRji Register Functions in PWM3 Mode Access the TRDGRAi to TRDGRDi registers in 16-bit units. Do not access them in 8-bit units. b0b7 (b8) (b15)

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 247 of 458 REJ09B0250-0200 BFC0, BFD0, BFC1, BFD1: Bits in TRDMR Register Registers TRDGRC0, TRDGRC1, TRDGRD0 , and TRDGRD1 are not used in PWM3 mode. To use them as buffer registers, set bits BFC0, BFC1, BFD0, and BFD1 to 0 (general register) and write a value to the TRDGRC0, TRDGRC1, TRDGRD0, or TRDGRD1 register. After this, bits BFC0, BFC1, BFD0, and BFD1 may be set to 1 (buffer register). Table 14.34 TRDGRji Register Functions in PWM3 Mode Register Setting Register Function PWM Output Pin TRDGRA0 − General register. Set the PWM period. Setting range: Value set in TRDGRA1 register or above TRDIOA0 TRDGRA1 General register. Set the changing point (the active level timing) of PWM output. Setting range: Value set in TRDGRA0 register or below TRDGRB0 General register. Set the changing point (the timing that returns to initial output level) of PWM output. Setting range: Value set in TRDGRB1 register or above Value set in TRDGRA0 register or below TRDIOB0 TRDGRB1 General register. Set the changing point (active level timing) of PWM output. Setting range: Value set in TRDGRB0 register or below TRDGRC0 BFC0 = 0 (These registers are not used in PWM3 mode) − TRDGRC1 BFC1 = 0 TRDGRD0 BFD0 = 0 TRDGRD1 BFD1 = 0 TRDGRC0 BFC0 = 1 Buffer register. Set the next PWM period. (Refer to 14.3.2 Buffer Operation.) Setting range: Value set in TRDGRC1 register or above TRDIOA0 TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of next PWM output. (Refer to 14.3.2 Buffer Operation.) Setting range: Value set in TRDGRC0 register or below TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of next PWM output. (Refer to 14.3.2 Buffer Operation.) Setting range: Value set in TRDGRD1 register or above, setting value or below in TRDGRC0 register. TRDIOB0 TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of next PWM output. (Refer to 14.3.2 Buffer Operation.) Setting range: Value set in TRDGRD0 register or below

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 248 of 458 REJ09B0250-0200 Figure 14.108 Operating Example of PWM3 Mode Value in TRD0 register Count source TRDIOA0 output 0000h FFFFh TRDIOB0 output m: Setting value in TRDGRA0 register n: Setting value in TRDGRA1 register p: Setting value in TRDGRB0 register q: Setting value in TRDGRB1 register m n p q TSTART0 bit in TRDSTR register Set to 0 by a program Set to 0 by a program m + 1 n + 1 m - n p + 1 q + 1 p - q Count stop Output “H” by the compare match in the TRDGRA1 register Set to 0 by a programSet to 0 by a program Set to 0 by a program Transfer m m Following data Transfer m Output “L” by the compare match in the TRDGRA0 register Transfer from the buffer register to general register Transfer from the buffer register to general register Initial output “L” j = either A or B The above applies to the following conditions:

• Both the TOA0 and TOB0 bits in the TRDOCR register are set to 0 (initial output level “L”, output “H” by the compare match in the TRDGRj1 register, output “L” by the compare match in the TRDGRj0 register)
• The BFC0 bit in the TRDMR register is set to 1 (the TRDGRC0 register is used as the buffer register of the TRDGRA0 register). CSEL0 bit in TRDSTR register IMFA bit in TRDSR0 register IMFB bit in TRDSR0 register TRDGRA0 register TRDGRC0 register

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14.3.11 Timer RD Interrupt

Timer RD generates the Timer RD interrupt request based on 6 sources every channel. The Timer RD interrupt has 1 TRDiIC register (IR bit, ILVL0 to ILVL2 bits) every channel, and 1 vector. Table 14.35 lists the Registers Associated with Timer RD Interrupt and Figure 14.109 shows the Block Diagram of Timer RD Interrupt. Figure 14.109 Block Diagram of Timer RD Interrupt As with other maskable interrupts, the timer RD interrupt is controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since the inte rrupt source (timer RD interrupt) is generated by a combination of multiple interrupt request sources, the following differences from other maskable interrupts apply:

• When bits in the TRDSRi register corresponding to bits set to 1 in the TRDIERi register are set to 1 (enable interrupt), the IR bit in the TRDiIC register is set to 1 (interrupt requested).
• When either bits in the TRDSRi register or bits in the TRDIERi register corresponding to bits in the TRDSRi register, or both of them, are set to 0, the IR bit is set to 0 (interrupt not requested). Therefore, even though the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be maintained.
• When the conditions of other request sources are met, the IR bit remains 1.
• When multiple bits in the TRDIERi register are se t to 1, which request source causes an interrupt is determined by the TRDSRi register.
• Since each bit in the TRDSRi register is not automatically set to 0 even if the interrupt is acknowledged, set each bit to 0 in the interrupt routine. For information on how to set these bits to 0, refer to the descriptions Table 14.35 Registers Associat ed with Timer RD Interrupt Timer RD Status Register Timer RD Interrupt Enable Register Timer RD Interrupt Control Register Channel 0 TRDSR0 TRDIER0 TRD0IC Channel 1 TRDSR1 TRDIER1 TRD1IC Timer RD (channel i) Interrupt request (IR bit in TRDiIC register) IMFA bit IMIEA bit IMFB bit IMIEB bit IMFC bit IMIEC bit IMFD bit IMIED bit UDF bit OVF bit OVIE bit i = 0 or 1 IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register Channel i

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 250 of 458 REJ09B0250-0200 14.104) for the TRDSRi register. Refer to TRDIER0 to TRDIER1 Registers in each mode (Figures 14.42, interrupt vector.

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14.3.12 Notes on Timer RD

14.3.12.1 TRDSTR Register

• Set the TRDSTR register using the MOV instruction.
• When the CSELi (i = 0 or 1) is set to 0 (the co unt stops at compare matc h of registers TRDi and TRDGRAi), the count does not stop and the TSTARTi b it remains unchanged even if 0 (count stops) is written to the TSTARTi bit. Therefore, set the TSTARTi bit to 0 to change othe r bits without changing the TSTARTi bit when the CSELi bit is set to 0. To stop counting by a program, set the TSTARTi bit to 0 after setting the CSELi bit to 1. Although the CSELi bit is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 instruction), the count cannot be stopped.
• Table 14.36 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops to use the TRDIOji pin with the timer RD output.

14.3.12.2 TRDi Register (i = 0 or 1)

• When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register is set to 1 (count starts), avoid to overlap with the timing to set the TRDi register to 0000h, and then write. When the timing to set the TRDi register to 0000h overlaps with the timing to write the value to the TRDi register, the value is not written and the TRDi register is set to 0000h. These precautions are applicable when selecting the following by the CCLR2 to CCLR0 bits in the TRDCRi register. - 001b (clear by the TRDi register at the compare match with the TRDGRAi register) - 010b (clear by the TRDi register at the compare match with the TRDGRBi register.) - 011b (synchronous clear) - 101b (clear by the TRDi register at the compare match with the TRDGRCi register.) - 110b (clear by the TRDi register at the compare match with the TRDGRDi register.)
• When writing the value to the TRDi register and continuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program Example MOV .W #XXXXh, TRD0 ;Writing JMP.B L1 ;JMP.B L1: MOV .W TRD0,DATA ;Reading

14.3.12.3 TRDSRi Register (i = 0 or 1)

When writing the value to the TRDSRi register and con tinuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program Example MOV .B #XXh, TRDSR0 ;Writing JMP.B L1 ;JMP.B L1: MOV .B TRDSR0,DA TA ;Reading Table 14.36 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops Count Stop TRDIOji Pin Output when Count Stops When the CSELi bit is set to 1, set the TSTARTi bit to 0 and the count stops. Hold the output level immediately before the count stops. When the CSELi bit is set to 0, the count stops at compare match of registers TRDi and TRDGRAi. Hold the output level after output changes by compare match.

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14.3.12.4 Count Source Switch

• When switching the count source, switch it after the count stops. Change procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change the TCK2 to TCK0 bits in the TRDCRi register.
• When changing the count source fr om fOCO40M to the other and stopping fOCO40M, wait 2 cycles or more of f1 after setting the clock switch, and then stop fOCO40M. Change procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change the TCK2 to TCK0 bits in the TRDCRi register. (3) Wait 2 cycles or more of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator stops).

14.3.12.5 Input Capture Function

• Set the pulse width of input capture si gnal to 3 cycles or more of the Timer RD operation clock. (Refer to Table 14.11 Timer RD Operation Clocks.)
• The value in the TRDi register is transferred to the TRDGRji register after 2 to 3 cycles of the Timer RD operation clock since the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C or D) (no digital filter).

14.3.12.6 Reset Synchronous PWM Mode

• When reset synchronous PWM mode is used for motor control, use it with OLS0 = OLS1.
• Set to reset synchronous PWM mode in the following procedure: Change procedure (1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops). (2) Set the CMD1 to CMD0 bits in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode). (3) Set the CMD1 to CMD0 bits to 01b (reset synchronous PWM mode). (4) Set the registers associated with other Timer RD again.

14.3.12.7 Complementary PWM Mode

• When complementary PWM mode is used for motor control, use it with OLS0 = OLS1.
• Change the CMD1 to CMD0 bits in the TRDFCR register in the following procedure. Change procedure: When setting to complementary PWM mode (including re-set), or changing the transfer timing from the buffer register to the general register in complementary PWM mode. (1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops). (2) Set the CMD1 to CMD0 bits in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode) (3) Set the DMD1 to CMD0 bits to 10b or 11b (complementary PWM mode). (4) Set the registers associated with other Timer RD again. Change procedure: When stopping complementary PWM mode (1) Set both the TSTART0 and CSEL1 bits in the TRDSTR register to 0 (count stops). (2) Set the CMD1 to CMD bits to 00b (other than reset synchronous PWM mode, complementary PWM mode)
• Do not write to the TRDGRA0, TRDGRB0, TRDGRA1 and TRDGRB1 registers during operation. When changing the PWM waveform , transfer the value written to the TRDGRD0, TRDGRC1 and TRDGRD1 registers to the TRDGRB0, TRDGRA1 and TRDGRB1 registers using the buffer operation. However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register). The PWM period cannot be changed.

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• When the value in the TRDGRA0 register is assumed as m, the TRD0 register counts order of m - 1, m, m + 1, m, m - 1 when changing from increment to decrement. When changing from m to m + 1, the IMFA bit is set to 1. Also, the CMD1 to CMD0 bits in the TRDFCR register are set to 11b (complementary PWM mode, bu ffer data transferred by the compare match in the TRD0 and TRDGRA0 registers), the content in the buffer register (TRDGRD0, TRDGRC1, TRDGRD1) is transferred to the general register (TRDGRB0, TRDGRA1, TRDGRB1). For the order of m + 1, m, m - 1 operation, the IMFA bit remains unchanged and data are not transferred to the register such as the TRDGRA0 register. Figure 14.110 Operation at Compare Match between Registers TRD0 and TRDGRA0 in Complementary PWM Mode No change IMFA bit in TRDSR0 register Transferred from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register Count value in TRD0 register Setting value in TRDGRA0 register m m + 1 Set to 0 by a program Not transferred from buffer register When the CMD1 to CMD0 bits in the TRDFCR register are set to 11b. (Transfer from the buffer register to the general register at the compare match of the TRD0 register and TRDGRA0 register)

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• The TRD1 register counts the order of 1, 0, FFFFh, 0, 1 when changing from decrement to increment. The UDF bit is set to 1 by the order of 1, 0, FFFFh operation. Also, when the CMD1 to CMD0 bits in the TRDFCR register are set to 10b (c omplementary PWM mode, buffer data transferred by the underflow in the TRD1 register), the content in the buffer re gister (TRDGRD0, TRDGRC1, TRDGRD1) is transferred to the general register (TRDGRB0 , TRDGRA1, TRDGRB1). For the orde r of FFFFh, 0, 1 operation, data are not transferred to the register such as the TRDG RB0 register. Also, at this time, the OVF bit remains unchanged. Figure 14.111 Operation When TRD1 Register Underflows in Complementary PWM Mode No change UDF bit in TRDSR0 register Transferred from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register Count value in TRD0 register Set to 0 by a program Not transferred from buffer register When the CMD1 to CMD0 bits in the TRDFCR register are set to 10b. (Transfer from the buffer register to the general register when the TRD1 register underflows) OVF bit in TRDSR0 register FFFFh

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• Select with the CMD1 to CMD0 bits for the data transfer timing from the buffer register to the general register. However, transfer with the following timing in spite of the value of the CMD1 to CMD0 bits for the following cases: Value in buffer register ≥ Value in TRDGRA0 register: Transfer at the underflow in the TRD1 register. And then, when setting the buffer register to 0001h or above and the smaller value than the one in the TRDGRA0 register, and the TRD1 register underflows in the fist time after setting, the value is transferred to the general register. After that, transfer the value with the timing selected by the CMD1 to CMD0 bits. Figure 14.112 Operation When Value in Buffer Register ≥ Value in TRDGRA0 Register in Complementary PWM Mode 0000h TRDGRD0 register TRDIOB0 output n3n2 m + 1 n2 n1 n3n2 n2 n1n1TRDGRB0 register Transfer Transfer by underflow in TRD1 register because of n3 > m Transfer by underflow in TRD1 register because of first setting to n2 < m TRDIOD0 output m: Setting Value in TRDGRA0 Register The above applies to the following conditions:
• The CMD1 to CMD0 bits in the TRDFCR register are set to 11b. (Data in the buffer register is transferred at the com pare match in the TRD0 and TRDGRA0 registers in complementary PWM mode.)
• Both the OSL0 and OLS1 bits in the TRDFCR are set to 1. (active ‘H” for normal-phase and counter-phase) Count value in TRD0 register Count value in TRD1 register Transfer with timing set by CMD1 to CMD0 bits Transfer with timing set by CMD1 to CMD0 bits Transfer Transfer Transfer

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 256 of 458 REJ09B0250-0200 When the value in the buffer register is set to 0000h: Transfer by the compare match in the TRD0 and TRDGRA0 registers. And then, when setting the buffer register to 0001h or above and the smaller value than the one in the TRDGRA0 register, and the compare match in the TR D0 and TRDGRA0 registers in the fist time after setting, the value is transferred to the general register. After that, transfer the value with the timing selected by the CMD1 to CMD0 bits. Figure 14.113 Operation When Value in Buffer Re gister Is Set to 0000h in Complementary PWM Mode

14.3.12.8 Count Source fOCO40M

The count source fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V . For supply voltage other than that, do not set bits TCK2 to TCK0 in registers TR DCR0 and TRDCR to 110b (select fOCO40M as the count source). 0000h TRDGRD0 register TRDIOB0 output m + 1 n 2 0000h n1 0000hn1 n1n2TRDGRB0 register Transfer Transfer by compare match in TRD0 and TRDGRA0 registers because content in TRDGRD0 register is set to 0000h. Transfer by compare match in TRD0 and TRDGRA0 registers because of first setting to 0001h ≤ n1 < m Transfer with timing set by CMD1 to CMD0 bits TRDIOD0 output m: Setting Value in TRDGRA0 Register The above applies to the following conditions:

• The CMD1 to CMD0 bits in the TRDFCR register are set to 10b. (Data in the buffer register is transferred at the underflow in the TRD1 register in PWM mode.)
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to “1” (active “H” for normal-phase and counter-phase). Count value in TRD0 register Count value in TRD1 register Transfer with timing set by CMD1 to CMD0 bits Transfer Transfer Transfer

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14.4 Timer RE

Timer RE has the 4-bit counter and 8-bit counter. Timer RE has the following mode:

• Output compare mode Count a count so urce and detect the compare match The count source for timer RE is the operating clock that regulates the timing of timer operations.

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14.4.1 Output Compare Mode

The output compare mode is to count the internal count source divided-by-2 using the 4-bit or 8-bit counter and detect the compare value match with the 8-bit counter. Figure 14.114 shows the Block Diagram of Output Compare Mode and Table 14.37 lists the Output Compare Mode Specifications. Figures 14.115 to 14.119 show the Registers Associated with Output Compare Mode and Figure 14.120 shows the Operation in Output Compare Mode. Figure 14.114 Block Diagram of Output Compare Mode TOENA TREO pin f32 4-bit counter 8-bit counter TRESEC Comparison circuit TREMIN RCS2 = 1 RCS2 = 0 COMIE Timer RE interrupt Match signal = 00b = 01b = 10b RCS1 to RCS0 RCS6 to RCS5 = 00b = 01b = 10b = 11b TOENA, TRERST: Bits in TRECR1 register COMIE: Bit in TRECR2 register RCS0 to RCS2, RCS5 to RCS6: Bits in TRECSR register TQ R Reset TRERST bit Data bus

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 259 of 458 REJ09B0250-0200 Table 14.37 Output Compare Mode Specifications Item Specification Count Source f4, f8, f32 Count Operation • Increment

• When the 8-bit counter content matches with the TREMIN register content, the value returns to 00h and count continues. The count value is held while count stops. Count Period • When RCS2 = 0 (4-bit counter is not used) 1/fi x 2 x (n + 1)
• When RCS2 = 1 (4-bit counter is used) 1/fi x 32 x (n + 1) fi: Frequency of count source n: Setting value of TREMIN register Count Start Condition Write 1 (count starts) to the TSTART bit in the TRECR1 register Count Stop Condition Write 0 (count stops) to the TSTART bit in the TRECR1 register Interrupt Request Generation Timing When the 8-bit counter content matches with the TREMIN register content TREO Pin Function Select any one of the followings:
• Programmable I/O ports
• Output any one of f2, f4 and f8
• Compare output Read from Timer When reading the TRESEC r egister, the 8-bit counter value can be read. When reading the TREMIN register, the compare value can be read. Write to Timer Writing to the TRESEC register is disabled. When the TSTART and TCSTF bits in the TRECR1 register are set to 0 (timer stops), writing to the TREMIN register is enabled. Select Functions • Select use of 4-bit counter
• Compare output function Every time the 8-bit counter value matches with the TREMIN register value, TREO output polarity is reversed. The TREO pin outputs “L” after reset is deasserted and the Timer RE reset by the TRERST bit in the TRECR1 register. Output level is held by setting the TSTART bit to 0 (count stops).

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 262 of 458 REJ09B0250-0200 Figure 14.119 TRECSR Register in Output Compare Mode Timer RE Count Source Select Register Symbol Address After Reset TRECSR 011Eh 08h Bit Symbol Bit Name Function RW NOTE: b3 b2 (b3) b1 b0 RCS0 b7 b6 b5 b4 RW RCS1 RW Count source select bit b1 b0 0 0 : f4 0 1 : f8 1 0 : f32 1 1 : Do not set 4-bit counter select bit 0 : Not used 1 : Used Write to the RCS5 to RCS6 bits w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output). RCS2 RW RW (b7) — Reserved bit Set to 0 Nothing is assigned. If necessary, set to 0. When read, the content is 0. RW RCS6 RW RCS5 (b4) Nothing is assigned. If necessary, set to 0. When read, the content is 0. Clock output select bit (1) b6 b5 0 0 : f2 0 1 : f4 1 0 : f8 1 1 : Compare output

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 263 of 458 REJ09B0250-0200 Figure 14.120 Operation in Output Compare Mode 2 cycles of maximum count source 00h 8-bit counter content (hexadecimal number) Count starts Time TSTART bit in TRECR1 register IR bit in TREIC register The above applies to the following conditions. TOENA bit in TRECR1 register = 1 (enable clock output) COMIE bit in TRECR2 register = 1 (enable compare match interrupt) RCS6 to RCS5 bits in TRECSR register = 11b (compare output) Set to 1 by a program Set to 0 by acknowledgement of interrupt request or a program TREMIN register setting value Matched TREO output 1 TCSTF bit in TRECR1 register Output polarity is reversed when the compare matches Matched Matched

R8C/20 Group, R8C/21 Group 14. Timers Rev.2.00 Aug 27, 2008 Page 264 of 458 REJ09B0250-0200

14.4.2 Notes on Timer RE

14.4.2.1 Starting and Stopping Count

Timer RE has the TSTART bit for instructing count start or stop, and the TCSTF bit which indicates count start or stop. The TSTART and TCSTF bits are in the TRECR1 register. Timer RE starts counting when setting the TSTART bit to 1 (count starts) and the TCSTF bit is set to 1 (count starts). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with Timer RE (1) other than the TCSTF bit. Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0 (count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF bit. NOTE: 1. Registers associated with Timer RE:TRESEC, TREMIN, TRECR1, TRECR2, TRECSR

14.4.2.2 Register Setting

Write to the following registers or bits while timer RE stops.

• TRESEC and TRECR2 registers
• The INT bit in TRECR1 register
• RCS0 to RCS2 bits in TRECSR register The state while Timer RE stops is indicated as the state where the TSTART and TCSTF bits in the TRECR1 register are set to 0 (timer RE stops). Also, set all above-mentioned registers and bits (immedia tely before timer RE count starts) before setting the TRECR2 register.

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 266 of 458 REJ09B0250-0200 Figure 15.2 UARTi (i = 0 or 1) Transmit/Receive Unit RXDi 1SP 2SP SP SP PAR PRYE = 0 PAR disabled PAR enabled PRYE = 1 UART UART (9 bits) D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive register UiRB register0000000 D 8 MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits D7 D6 D5 D4 D3 D2 D1 D0 UiTB registerD8 TXDi 1SP 2SP SP SP PAR UARTi transmit register i = 0 or 1 SP: Stop bit PAR: Parity bit NOTE: 1. Clock synchronous type is provide in UART0 only. UART (7 bits) UART (8 bits) Clock synchronous type Clock synchronous type UART (7 bits) Clock synchronous type UART (7 bits) Clock synchronous type UART (8 bits) UART (9 bits) UART (7 bits) UART (8 bits) Clock synchronous type UART (9 bits) UART PRYE = 1 PAR enabled PAR disabled PRYE = 0 Clock synchronous type MSB/LSB conversion circuit UART (8 bits) UART (9 bits)

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 267 of 458 REJ09B0250-0200 Figure 15.3 Registers UiTB, Ui RB, and UiBRG (i = 0 or 1) UARTi Transmit Buffer Register (i = 0 or 1)(1,2) Symbol Address After Reset U0TB 00A3h-00A2h Indeterminate U1TB 00ABh-00AAh Indeterminate RW NOTES: (b15) (b8) b0 b0b7 Use the MOV instruction to w rite to this register. WO —Nothing is assigned. If necessary, set to 0. When read, the content is indeterminate. (b15-b9) When the transfer data length is 9-bit long, w rite to high-byte data first then low -byte data. FunctionBit Symbol (b8-b0) Transmit data UARTi Receive Buffer Register (i = 0 or 1)(1) Symbol After Reset U0RB Indeterminate U1RB Indeterminate RW NOTES: (b7-b0) — Function Receive data (D7 to D0) RO Receive data (D8) RO— (b8) — b0b7 (b15) (b8) Bit Symbol Bit Name Address 00A7h-00A6h 00AFh-00AEh OER Overrun error flag(2) 0 : No overrun error 1 : Overrun error RO 0 : No parity error 1 : P arity error RO FER Framing error flag(2) 0 : No framing error 1 : Framing error RO Nothing is assigned. If necessary, set to 0. When read, the content is indeterminate. (b11-b9) Read out the UiRB register in 16-bit unit. The SUM, PER, FER and OER bits are set to 0 (no error) w hen the SMD2 to SMD0 bits in the UiMR register are set to 000b (serial interface disabled) or the RE bit in the U0C1 register is set to 0 (receive disable). The SUM bit is set to 0 (no error) w hen the PER, FER and OER bits are set to 0 (no error). Also, the PER and FER bits are set to 0 w hen the higher byte of the UiRB register is read out. ROSUM E rror sum flag (2) 0 : No error 1 : E rror PER P arity error flag(2) UARTi Bit Rate Register (i = 0 or 1)(1,2,3) Symbol Address After Reset U0BRG 00A1h Indeterminate U1BRG 00A9h Indeterminate Setting Range RW NOTES: Assuming that set value is n, UiBRG divides the count source by n+1 After setting the CLK0 to CLK1 bits in the UiC0 register, w rite to the UiBRG register. Use the MOV instruction to w rite to this register. WO Write to this register w hile the serial interface is neither transmitting nor receiving. 00h to FFh Function

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 268 of 458 REJ09B0250-0200 Figure 15.4 UiMR Register (i = 0 or 1) UARTi Transmit/Receive Mode Register (i = 0 or 1) Symbol Address After Reset U0MR 00A0h 00h U1MR 00A8h 00h Bit Symbol Bit Name Function RW NOTES: Do not set bits SMD2 to SMD0 in the U1MR register to any values other than 000b, 100b, 101b and 110b. Set the CKDIR bit to 0 (internal clock) in UART1. The SMD2 to SMD1 bits can not select clock synchronous serial I/O mode in UART1. Internal/external clock select bit (3) 0 : Internal clock 1 : External clock (1) Stop bit length select bit (b7) Reserved bit RW Odd/even parity select bit PRY E Parity enable bit 0 : Parity disabled 1 : Parity enabled PRY RW Set to 0 Set the PD1_6 bit in the PD1 register to 0 (input). SMD2 RW RW STPS RW0 : 1 stop bit 1 : 2 stop bits CKDIR RW RW Serial I/O mode select bit(2,4) b2 b1 b0 0 0 0 : Serial interface disabled 0 0 1 : Clock synchronous serial I/O mode 1 0 0 : UART mode transfer data 7 bits long 1 0 1 : UART mode transfer data 8 bits long 1 1 0 : UART mode transfer data 9 bits long Other than above : Do not set SMD1 Enables w hen PRYE = 1 0 : Odd parity 1 : Even parity b7 b6 b5 b4 b3 b2 b1 b0 SMD0 RW

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 269 of 458 REJ09B0250-0200 Figure 15.5 Registers UiC0 and UiC1 (i = 0 or 1) UARTi Transmit/Receive Control Register 0 (i = 0 or 1) Symbol Address After Reset U0C0 00A4h 00001000b U1C0 00ACh 00001000b Bit Symbol Bit Name Function RW NOTE: RW RW If the BRG count source is sw itched, set the UiBRG register again. RW Data output select bit 0 : TXDi pin is a pin of CMOS output 1 : TXDi pin is a pin of N-channel open drain output UFORM Transfer format select bit 0 : LSB first 1 : MSB first NCH CLK polarity select bit 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Set to 0 Transmit register empty flag 0 : Data in transmit register (during transmit) 1 : No data in transmit register (transmit completed) Nothing is assigned. If necessary, set to 0. When read, the content is 0. (b2) CKPOL CLK1 RW BR G count source select bit (1) b1 b0 0 0 : Selects f1 0 1 : Selects f8 1 0 : Selects f32 1 1 : Do not set RW RW RO (b4) — Res erv ed bit b7 b6 b5 b4 b3 b2 TXEPT b1 b0 CLK0 UARTi Transmit/Receive Control Register 1 (i = 0 or 1) Symbol Address After Reset U0C1 00A5h 00000010b U1C1 00ADh 00000010b Bit Symbol Bit Name Function RW NOTES: 2. Set the UiRRM bit to 0 (disables continuous receive mode) in UART mode. RW RW UiRRM UARTi continuous receive mode enable bit (2) RI R eceive com plete flag(1) 0 : No data in UiRB register 1 : Data in UiRB register RO UiIRS The RI bit is set to 0 w hen the higher byte of the UiRB register is read out. RW TI RO0 : Data in UiTB register 1 : No data in UiTB register TE RE (b7-b6) — b7 b6 b5 b4 Nothing is assigned. If necessary, set to 0. When read, the content is 0. Transmit enable bit 0 : Disables transmit 1 : Enables transmit Transmit buffer empty flag 0 : Disables receive 1 : Enables receive 0 : Disables continuous receive mode 1 : Enables continuous receive mode 0 : Transmit buffer empty (TI = 1) 1 : Transmit completed (TXEPT = 1) Receive enable bit RW b3 b2 b1 b0 UARTi transmit interrupt cause select bit

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 270 of 458 REJ09B0250-0200 Figure 15.6 Registers U1SR and PMR UART1 Function Select Register Symbol Address After Reset U1SR 00F5h Indeterminate RW WO Function Set to 03h w hen using UART1. As a result, UART1 can be used as the clock asynchronous serial I/O. Do not set values other than 03h. When read, its content is indeterminate. Port Mode Register Symbol Address After Reset PMR 00F8h 00h Bit Symbol Bit Name Function RW IICSEL RW0 : SSU function selects 1 : I2C bus function selects Set to 0 0 : I/O port P6_6, P6_7 1 : TXD1, RXD1 Set to 0 —Res erv ed bits SSU/I2C bus sw itch bit RW —Res erv ed bits U1PINSEL P ort TXD 1/RXD 1 sw itch bit (b3-b0) (b6-b5) b3 b2 b7 b6 b5 b4

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 271 of 458 REJ09B0250-0200

15.1 Clock Synchronous Serial I/O Mode

The clock synchronous serial I/O mode is mode to transmit and receive data using a tr ansfer clock. This mode is selected in UART0 only. Table 15.1 lists the Clock Synchronous Serial I/O Mode Sp ecifications. Table 15.2 lists the Registers Used and Settings in Clock Synchronous Serial I/O Mode (1). NOTES: 1. When an external clock is selected, meet the condit ions while the CKPOL bit in the U0C0 register is set to 0 (transmit data output at the falling edge and the receive data input at the rising edge of the transfer clock), the external clock is held “H”; if the CKPOL bit in the U0C0 register is set to 1 (transmit data output at the rising edge and the receive data input at the falling edge of the transfer clock), the external clock is held “L”. 2. If an overrun er ror occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR bit in the S0RIC register remains unchanged. Table 15.1 Clock Synchronous Serial I/O Mode Specifications Item Specification Transfer Data Format • Transfer data length: 8 bits Transfer Clocks • CKDIR bit in U0MR register is set to 0 (internal clock): fi/(2(n + 1)) fi = f1, f8, f32 n = setting value in U0BRG register: 00h to FFh

• The CKDIR bit is set to 1 (external clock): input from CLK0 pin Transmit Start Conditions • Before transmit starts, the following requirements are required (1) - The TE bit in the U0C1 register is set to 1 (transmit enabled) - The TI bit in the U0C1 register is set to 0 (data in the U0TB register) Receive Start Conditions • Before receive starts, the following requirements are required(1) - The RE bit in the U0C1 register is set to 1 (receive enabled) - The TE bit in the U0C1 register is set to 1 (transmit enabled) - The TI bit in the U0C1 register is set to 0 (data in the U0TB register) Interrupt Request Generation Timing
• When transmit, one of the following conditions can be selected - The U0IRS bit is set to 0 (transmit buffer empty): when transferring data from the U0TB register to UART0 transmit register (when transmit starts) - The U0IRS bit is set to 1 (transmit completes): when completing transmit data from UARTi transmit register
• When receive When transferring data from the UART0 receive register to the U0RB register (when receive completes) Error Detection • Overrun error (2) This error occurs if serial interface starts receiving the following data before reading the U0RB register and receives the 7th bit of the following data Select Functions • CLK polarity selection Transfer data input/output can be selected to occur synchronously with the rising or the falling edge of the transfer clock
• LSB first, MSB first selection Whether transmitting or receiving data beginning with the bit 0 or beginning with the bit 7 can be selected
• Continuous receive mode selection Receive is enabled immediately by reading the U0RB register

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 272 of 458 REJ09B0250-0200 NOTE: 1. Set bits which are not in this table to 0 when writing to the registers in clock synchronous serial I/O mode. Table 15.3 lists the I/O Pin Functions in Clock Synchr onous Serial I/O Mode. The TXD0 pin outputs “H” level between the operating mode se lection of UART0 and transfer start, an “H” (If th e NCH bit is set to 1 (the N- channel open-drain output), this pin is in a high-impedance state.) Table 15.2 Registers Used and Settings in Clock Synchronous Serial I/O Mode(1) Register Bit Function U0TB 0 to 7 Set transmit data U0RB 0 to 7 Receive data can be read OER Overrun error flag U0BRG 0 to 7 Set bit rate U0MR SMD2 to SMD0 Set to 001b CKDIR Select the internal clock or external clock U0C0 CLK1 to CLK0 Sele ct the count source in the U0BRG register TXEPT Transmit register empty flag NCH Select TXD0 pin output mode CKPOL Select the transfer clock polarity UFORM Select the LSB first or MSB first U0C1 TE Set this bit to 1 to enable transmit/receive TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U0IRS Select the UART0 transmit interrupt source U0RRM Set this bit to 1 to use continuous receive mode Table 15.3 I/O Pin Functions in Clock Synchronous Serial I/O Mode Pin Name Function Selection Method TXD0(P1_4) Output serial data (Outputs dummy data when performing receive only) RXD0(P1_5) Input serial data The PD1_5 bit in the PD1 register = 0 (P1_5 can be used as an input port when performing transmit only) CLK0(P1_6) Output transfer clock The CKDIR bit in the U0MR register = 0 Input transfer clock The CKDIR bit in the U0MR register = 1 PD1_6 bit in PD1 register = 0

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 273 of 458 REJ09B0250-0200 Figure 15.7 Transmit and Receive Timing Ex ample in Clock Synchronous Serial I/O Mode Transfer clock TE bit in U0C1 register TXD0

• Example of transmit timing (when internal clock is selected) Set data in U0TB register Transfer from U0TB register to UART0 transmit register TC CLK0 TCLK Stop pulsing because the TE bit is set to 0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 TC = TCLK = 2(n+1)/fi fi: Frequency of UiBRG count source (f1, f8, f32) n: Setting value to UiBRG registerThe above applies under the following settings:
• CKDIR bit in U0MR register = 0 (internal clock)
• CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
• U0IRS bit in U0C1 register = 0 (an interrupt request is generated when the transmit buffer is empty) Set to 0 when interrupt request is acknowledged, or set by a program Write dummy data to U0TB register Transfer from U0TB register to UART0 transmit register 1/fEXT D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 Receive data is taken in Read out from U0RB registerTransfer from UART0 receive register to U0RB register TI bit in U0C1 register TXEPT bit in U0C0 register IR bit in S0TIC register Set to 0 when interrupt request is acknowledged, or set by a program
• Example of receive timing (when external clock is selected) RE bit in U0C1 register TE bit in U0C1 register TI bit in U0C1 register RI bit in U0C1 register IR bit in S0RIC register CLK0 RXD0 The above applies under the following settings:
• CKDIR bit in U0MR register = 1 (external clock)
• CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) The following conditions are met when “H” is applied to the CLK0 pin before receiving data:
• TE bit in U0C1 register = 1 (enables transmit)
• RE bit in U0C1 register = 1 (enables receive)
• Write dummy data to the U0TB register fEXT: Frequency of external clock

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 274 of 458 REJ09B0250-0200

15.1.1 Polarity Select Function

Figure 15.8 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer clock polarity. Figure 15.8 Transfer Clock Polarity

15.1.2 LSB First/MSB First Select Function

Figure 15.9 shows the Transfer Format. Use the UFORM bit in the U0C0 register to select the transfer format. Figure 15.9 Transfer Format CLK0(1) D0TXD0

• When the CKPOL Bit in the U0C0 Register = 0 (output transmit data at the falling edge and input the receive data at the rising edge of the transfer clock) D1 D2 NOTES: 1. When not transferring, the CLK0 pin level is “H”. 2. When not transferring, the CLK0 pin level is “L”. D3 D4 D5 D6 D7 D0RXD0 D1 D2 D3 D4 D5 D6 D7 CLK0(2) D0TXD0 D1 D2 D3 D4 D5 D6 D7 D0RXD0 D1 D2 D3 D4 D5 D6 D7
• When the CKPOL Bit in the U0C0 Register = 1 (output transmit data at the rising edge and input the receive data at the falling edge of the transfer clock) CLK0 D0TXD0
• When UFORM Bit in U0C0 Register = 0 (LSB first)(1) D1 D2 D3 D4 D5 D6 D7 D0RXD0 D1 D2 D3 D4 D5 D6 D7 CLK0 D7TXD0 D6 D5 D4 D3 D2 D1 D0 RXD0
• When UFORM Bit in U0C0 Register = 1 (MSB first)(1) NOTE: 1. The above applies when the CKPOL bit in the U0C0 register is set to 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock). D7 D6 D5 D4 D3 D2 D1 D0

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 275 of 458 REJ09B0250-0200

15.1.3 Continuous Receive Mode

Continuous receive mode is held by setting the U0RRM bit in the U0C1 register to 1 (enables continuous receive mode). In this mode, reading U0RB register sets the TI bit in the U0C1 regi ster to 0 (data in the U0TB register). When the U0RRM bit is set to 1, do not write dummy data to the U0TB register in a program.

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 276 of 458 REJ09B0250-0200

15.2 Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmit and receive data after setting the desired bit rate and transfer data format. Table 15.4 lists the UART Mode Specifications. Table 15.5 lists the Registers Used and Settings for UART Mode. i = 0 or 1 NOTE: 1. If an overrun er ror occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR bit in the S0RIC register remains unchanged. Table 15.4 UART M ode Specifications Item Specification Transfer Data Formats • Character bit (transfer data): selectable from 7, 8 or 9 bits

• Start bit: 1 bit
• Parity bit: selectable from odd, even, or none
• Stop bit: selectable from 1 or 2 bits Transfer Clocks • CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n + 1)) fj = f1, f8, f32 n = setting value in U0BRG register: 00h to FFh
• CKDIR bit is set to 1 (external clock): fEXT/(16(n + 1)) fEXT: Input from CLK0 pin n = setting value in UiBRG register: 00h to FFh Transmit Start Conditions • Before transmit starts, the following are required - TE bit in UiC1 register is set to 1 (transmit enabled) - TI bit in UiC1 register is set to 0 (data in UiTB register) Receive Start Conditions • Before receive starts, the following are required - RE bit in UiC1 register is set to 1 (receive enabled) - Detects start bit Interrupt Request Generation Timing
• When transmitting, one of the following conditions can be selected - UiIRS bit is set to 0 (transmit buffer empty): when transferring data from the UiTB register to UARTi transmit register (when transmit starts) - UiIRS bit is set to 1 (transfer ends): when serial interface completes transmitting data from the UARTi transmit register
• When receiving When transferring data from the UARTi receive register to UiRB register (when receive ends) Error Detection •O v e r r u n e r r o r (1) This error occurs if serial interface starts receiving the following data before reading the UiRB register and receiving the bit one before the last stop bit of the following data
• Framing error This error occurs when the number of stop bits set are not detected
• Parity error This error occurs when parity is enabled, the number of 1’s in parity and character bits do not match the number of 1’s set
• Error sum flag This flag is set is set to 1 when any of the overrun, framing, and parity errors is generated

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 277 of 458 REJ09B0250-0200 i = 0 or 1 NOTES: 1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7-bit long; bits 0 to 7 when transfer data is 8-bit long; bits 0 to 8 when transfer data is 9-bit long. 2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer data is 8 bits long. 3. External clock can be selected in UART0 only. Table 15.6 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 or 1) operating mode is selected, the TXDi pin outputs “H” level (if the NCH bit is set to 1 (N-channel open-drain outputs), this pin is in a high- impedance state) until transfer starts. Table 15.5 Registers Used and Settings for UART Mode Register Bit Function UiTB 0 to 8 Set transmit data (1) UiRB 0 to 8 Receive data can be read(1, 2) OER,FER,PER,SUM Error flag UiBRG 0 to 7 Set a bit rate UiMR SMD2 to SMD0 Set to 100b when transfer data is 7-bit long Set to 101b when transfer data is 8-bit long Set to 110b when transfer data is 9-bit long CKDIR Select the internal clock or external clock(3) STPS Select the stop bit PRY, PRYE Select whether parity is included and odd or even UiC0 CLK0, CLK1 Select the count source for the UiBRG register TXEPT Transmit register empty flag NCH Select TXDi pin output mode CKPOL Set to 0 UFORM LSB first or MSB first can be selected when transfer data is 8-bit long. Set to 0 when transfer data is 7- or 9-bit long. UiC1 TE Set to 1 to enable transmit TI Transmit buffer empty flag RE Set to 1 to enable receive RI Receive complete flag UiIRS Select the UARTi transmit interrupt source UiRRM Set to 0 Table 15.6 I/O Pin Functions in UART Mode Pin name Function Selection Method TXD0(P1_4) Output serial data (Cannot be used as a port when performing receive only) RXD0(P1_5) Input serial data The PD1_5 bit in the PD1 register = 0 (P1_5 can be used as an input port when performing transmit only) CLK0(P1_6) Programmable I/O port The CKDIR bit in the U0MR register = 0 Input transfer clock The CKDIR bit in the U0MR register = 1 The PD1_6 bit in the PD1 register = 0 TXD1(P6_6) Output serial data U1PINSEL bit in PMR register = 1 (Cannot be used as a port when performing receive only) RXD1(P6_7) Input serial data U1PINSEL bit in PMR register = 1 The PD6_7bit in the PD6 register = 0 (P6_7 can be used as an input port when performing transmit only)

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 278 of 458 REJ09B0250-0200 Figure 15.10 Transmit Timing in UART Mode TC D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1ST TC D1 D2 D3 D4 D5 D6 D7 D8 SP SPST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SPST D0 D1ST Transfer clock TE bit in UiC1 register TXDi Set to 0 when interrupt request is acknowledged, or set by a program

• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit) Write data to UiTB register TC=16 (n + 1) / fj or 16 (n + 1) / fEXT fj: Frequency of UiBRG count source (f1, f8, f32) fEXT: Frequency of UiBRG count source (external clock) n: Setting value to UiBRG register i = 0 or 1 The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 1 (parity enabled)
• STPS bit in UiMR register = 0 (1 stop bit)
• UiIRS bit in UiC1 register = 1 (an interrupt request is generated when transmit completes) Start bit Parity bit Stop pulsing because the TE bit is set to 0 TXDi Write data to UiTB register Transfer from UiTB register to UARTi transmit register TI bit in UiC1 register TXEPT bit in UiC0 register IR bit SiTIC register Stop bit
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits) Stop bit Stop bit Start bit Transfer clock TE bit in UiC1 register TI bit in UiC1 register TXEPT bit in UiC0 register IR bit in SiTIC register Transfer from UiTB register to UARTi transmit register TC=16 (n + 1) / fj or 16 (n + 1) / fEXT fj: Frequency of UiBRG count source (f1, f8, f32) fEXT: Frequency of UiBRG count source (external clock) n: Setting value to UiBRG register i = 0 or 1 Set to 0 when interrupt request is acknowledged, or set by a program The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (2 stop bits)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when transmit buffer is empty)

R8C/20 Group, R8C/21 Group 15. Serial Interface Rev.2.00 Aug 27, 2008 Page 279 of 458 REJ09B0250-0200 Figure 15.11 Receive Timi ng Example in UART Mode UiBRG output Set to 0 when interrupt request is accepted, or set by a program

• Example of Receive Timing when Transfer Data is 8 Bits Long (parity disabled, one stop bit) The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit) i = 0 or 1 UiC1 register RE bit Start bit Stop bit D0 D1 D7RXDi Transfer clock Determined “L” Receive data taken in Reception triggered when transfer clock is generated by falling edge of start bit Transferred from UARTi receive register to UiRB register UiC1 register RI bit SiRIC register RI bit

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15.2.1 Bit Rate

Divided-by-16 of frequency by the UiBRG (i = 0 or 1) register in UART mode is a bit rate. Figure 15.12 Calculation Formula of UiBRG (i = 0 or 1) Register Setting Value i = 0 or 1 Table 15.7 Bit Rate Setting Example in UART Mode (Internal Clock Selected) Bit Rate (bps) UiBRG Count Source System Clock = 20 MHz System Clock = 8 MHz UiBRG Setting Value Actual Time (bps) Setting Error(%) UiBRG Setting Value Actual Time (bps) Setting Error(%) 1200 f8 129 (81h) 1201.92 0.16 51 (33h) 1201.92 0.16 2400 f8 64 (40h) 2403.85 0.16 25 (19h) 2403.85 0.16 4800 f8 32 (20h) 4734.85 -1.36 12 (0Ch) 4807.69 0.16 9600 f1 129 (81h) 9615.38 0.16 51 (33h) 9615.38 0.16 14400 f1 86 (56h) 14367.82 -0.22 34 (22h) 14285.71 -0.79 19200 f1 64 (40h) 19230.77 0.16 25 (19h) 19230.77 0.16 28800 f1 42 (2Ah) 29069.77 0.94 16 (10h) 29411.76 2.12 31250 f1 39 (27h) 31250.00 0.00 15 (0Fh) 31250.00 0.00 38400 f1 32 (20h) 37878.79 -1.36 12 (0Ch) 38461.54 0.16 51200 f1 23 (17h) 52083.33 1.73 9 (09h) 50000.00 -2.34 <UART Mode>

• When selecting internal clock Setting value to the UiBRG register = fj Bit Rate × 16 - 1 fj: Count source frequency of the UiBRG register (f1, f8 and f32)
• When selecting external clock fEXT Bit Rate × 16 - 1 fEXT: Count source frequency of the UiBRG register (external clock) i = 0 or 1 Setting value to the UiBRG register =

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15.3 Notes on Serial Interface

• When reading data from the UiRB (i = 0 or 1) register even in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode. Ensure to read data in 16-bit unit. When the high-order byte of the UiRB register is read, the PER and FER bits in the UiRB register and the RI bit in the UiC1 register are set to 0. To check receive errors, read the UiRB register and then use the read data. Example (when reading receive buffer register): MOV .W 00A6H,R0 ; Read the U0RB register
• When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data length, write data high-order byte first, then low-order byte in 8-bit units. Example (when reading transmit buffer register): MOV .B #XXH,00A3H ; Write the high-order byte of U0TB register MOV .B #XXH,00A2H ; Write the low-order byte of U0TB register

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 282 of 458 REJ09B0250-0200 16. Clock Synchronous Serial Interface The clock synchronous serial interface is configured as follows. Clock Synchronous Serial Interface The clock synchronous serial interface us es the registers of addresses 00B8h to 00BFh. Registers, bits, symbols and functions vary even in the same addresses depending on the modes. Refer to registers of each function for details. Also, the differences between clock synchronous communi cation mode and clock synchronous serial mode are the options of the transfer clock, clock output format and data output format.

16.1 Mode Selection

The clock synchronous serial interface contains 4 modes. Table 16.1 lists the Mode Selections. Refer to 16.2 Clock Synchronous Serial I/O with Chip Select (SSU) or after for details of each mode. Clock synchronous serial I/O with chip select (SSU) Clock synchronous communication mode 4-wire bus communication mode I 2C bus interface I 2C bus interface mode Clock synchronous serial mode Table 16.1 Mode Selections IICSEL Bit in PMR Register Bit 7 in 00B8h (ICE Bit in ICCR1 Register) Bit 0 in 00BDh (SSUMS Bit in SSMR2 Register, FS Bit in SAR Register) Function Mode 0 0 0 Clock synchronous serial I/O with chip select Clock synchronous communication mode 0 0 1 4-wire bus communication mode 11 0 I2C bus interface I 2C bus interface mode 1 1 1 Clock synchronous serial mode

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16.2 Clock Synchronous Serial I/ O with Chip Select (SSU)

The serial data of the clock synchronous can communicate for the clock synchronous serial I/O with chip select. Table 16.2 lists the Clock Synchronous Serial I/O with Ch ip Select Specifications a nd Figure 16.1 shows a Block Diagram of Clock Synchronous Serial I/O with Chip Select. Figures 16.2 to 16.9 show Clock Synchronous Serial I/O with Chip Select Associated Registers. NOTE: 1. The interrupt vector table is one of the clock sy nchronous serial I/O with chip select specification. Table 16.2 Clock Synchronous Serial I/ O with Chip Select Specifications Item Specification Transfer Data Format • Transfer-data length 8 bits Continuous transmit and receive of serial data are enabled since both transmitter and receiver have buffer structure. Operating Mode • Clock synchronous communication mode

• 4-wire bus communication mode (including bidirectional communication) Master / Slave Device Selectable I/O Pin SSCK (I/O): Clock I/O pin SSI (I/O): Data I/O pin SSO (I/O): Data I/O pin SCS (I/O): Chip-select I/O pin Transfer Clock • When the MSS bit in the SSCRH register is set to 0 (operates as slave device), external clock can be selected.
• When the MSS bit in the SSCRH register is set to 1 (operates as master device), internal clock (selects from f1/256, f1/128, f1/64, f1/32, f1/16, f1/8 and f1/4 and outputs from SSCK pin) can be selected.
• Clock polarity and phase of SSCK can be selected. Receive Error Detection • Overrun error Overrun error occurs during receive and completes by error. While the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and completing the next serial data receive, the ORER bit is set to 1. Multimaster Error Detection
• Conflict error While the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device) and when starting a serial communication, the CE bit in the SSSR register is set to 1 if “L” applies to the SCS pin input. When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication mode), the MSS bit in the SSCRH register is set to 0 (operates as slave device) and the SCS pin input changes state from “L” to “H”, the CE bit in the SSSR register is set to 1. Interrupt Request 5 interrupt re quests (transmit-end, transmit-data-empty, receive-data-full, overrun error and conflict error).(1) Select Function • Data transfer direction Selects MSB-first or LSB-first
• SSCK clock polarity Selects “L” or “H” level when clock stops
• SSCK clock phase Selects edge of data change and data download

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 284 of 458 REJ09B0250-0200 Figure 16.1 Block Diagram of Clock Sync hronous Serial I/O with Chip Select SSMR register Data bus Transmit/receive control circuit SSCRL register SSCRH register SSER register SSSR register SSMR2 register SSTDR register SSRDR register Selector Multiplexer SSO SSI SCS SSCK Interrupt requests (TXI, TEI, RXI, OEI and CEI) Internal clock generation circuit Internal clock(f1/i) i = 4, 8, 16, 32, 64, 128 and 256 SSTRSR register

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 285 of 458 REJ09B0250-0200 Figure 16.2 SSCRH Register SS Control Register H Symbol Address After Reset SSCRH 00B8h 00h Bit Symbol Bit Name Function RW NOTES: The SSCK pin functions as the transfer clock output pin w hen the MSS bit is set to 1 (operates as master device). The MSS bit is set to 0 (operates as slave device) w hen the CE bit in the SSSR register is set to 1 (conflict error occurs). RSSTP Receive single stop bit (3) 0 : Maintains receive operation after receiving 1-byte data 1 : Completes receive operation after receiving 1-byte data RW (b7) Nothing is assigned. If necessary, set to 0. When read, the content is 0. The set clock is used w hen the internal clock is selected. Master/slave device select bit (2) 0 : Operates as slave device 1 : Operates as master device RWMSS (b4-b3) —Nothing is assigned. If necessary, set to 0. When read, the content is 0. CKS1 CKS2 Transfer clock rate select bit(1) b2 b1 b0 0 0 0 : f1/256 0 0 1 : f1/128 0 1 0 : f1/64 0 1 1 : f1/32 1 0 0 : f1/16 1 0 1 : f1/8 1 1 0 : f1/4 1 1 1 : Do not set CKS0 RW RW RW The RSSTP bit is disabled w hen the MSS bit is set to 0 (operates as slave device). b7 b6 b5 b4 b3 b2 b1 b0

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 286 of 458 REJ09B0250-0200 Figure 16.3 SSCRL Register SS Control Register L Symbol Address After Reset SSCRL 00B9h 01111101b Bit Symbol Bit Name Function RW NOTES: 3. Do not w rite to the SOL bit during the data transfer. The data output after the serial data is output can be changed w hen w riting to the SOL bit before or after transfer. When w riting to the SOL bit, set the SOLP bit to 0 and then w rite to bits SOLP and SOL by the MOV instruction. SSCRH, SSCRL, SSMR, SSER, SSSR, SSMR2, SSTDR and SSRDR registers. SOL Serial data output value setting bit When read, 0 : The last bit of the serial data output is set to “L” 1 : The last bit of the serial data output is set to “H” When w rite,(2,3) 0 : The data outputs “L” after the serial data output 1 : The data outputs “H” after the serial data output RW (b6) Nothing is assigned. If necessary, set to 0. When read, the content is 1. — (b7) Nothing is assigned. If necessary, set to 0. When read, the content is 0. — (b3-b2) Nothing is assigned. If necessary, set to 0. When read, the content is 1. — SOLP SOL w rite protect bit (2) The output level can be changed by the SOL bit w hen this bit is set to 0. The SOLP bit remains unchanged even if 1 is w ritten to it. When read, its content is 1. RW b7 b6 b5 b4 b3 b2 b1 b0 (b0) —Nothing is assigned. If necessary, set to 0. When read, the content is 1. SRES Clock synchronous serial I/O w ith chip select control part reset bit When this bit is set to 1, the clock synchronous serial I/O w ith chip select control part and SSTRSR register are reset. The values of the registers(1) in the clock synchronous serial I/O w ith chip select register are maintained. RW

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 287 of 458 REJ09B0250-0200 Figure 16.4 SSMR Register SS Mode Register Symbol Address After Reset SSMR 00BAh 00011000b Bit Symbol Bit Name Function RW Reserved bit NOTE: b3 b2 b1 b0 MSB first/LSB first select bit b7 b6 b5 b4 0 : Change data at odd edge (dow nloads data at even edge) 1 : Change data at even edge (dow nloads data at odd edge) CPOS SSC K clock polarity select bit (1) 0 : “H” w hen clock stops 1 : “L” w hen clock stops (b3) (b4) CPHS SSCK clock phase select bit(1) RO BC1 BC2 Bit counter 2 to 0 b2 b1 b0 0 0 0 : 8-bit left 0 0 1 : 1-bit left 0 1 0 : 2-bit left 0 1 1 : 3-bit left 1 0 0 : 4-bit left 1 0 1 : 5-bit left 1 1 0 : 6-bit left 1 1 1 : 7-bit left BC0 RO RO Ref er to

16.2.1.1 Association betw een Transfer Clock Polarity, Phase, and Data for the setting of the CPHS

and CPOS bits. Set to 1. When read, its content is 1. RW RW RW RW 0 : Transfers data at MSB first 1 : Transfers data at LSB firstMLS Nothing is assigned. If necessary, set to 0. When read, the content is 1.

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 288 of 458 REJ09B0250-0200 Figure 16.5 SSER Register SS Enable Register Symbol Address After Reset SSER 00BBh 00h Bit Symbol Bit Name Function RW b0b3 b2 b1b7 b6 b5 b4 RW RW RW Conflict error interrupt enable bit 0 : Disables conflict error interrupt request 1 : Enables conflict error interrupt request (b2-b1) Nothing is assigned. If necessary, set to 0. When read, the content is 0. CEIE 0 : Disables transmit data empty interrupt request 1 : Enables transmit data empty interrupt request 0 : Disables transmit end interrupt request 1 : Enables transmit end interrupt request RW RE TE TEIE Transmit end interrupt enable bit RW RIE RW Receive enable bit 0 : Disables receive 1 : Enables receive Transmit enable bit 0 : Disables transmit 1 : Enables transmit 0 : Disables receive data full and overrun error interrupt request 1 : Enables receive data full and overrun error interrupt request Receive interrupt enable bit TIE Transmit interrupt enable bit

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 289 of 458 REJ09B0250-0200 Figure 16.6 SSSR Register SS Status Register (7) Symbol Address After Reset SSSR 00BCh 00h Bit Symbol Bit Name Function RW NOTES: When reading 1 and w riting 0, the CE, ORER, RDRF, TEND and TDRE bits are set to 0. Indicates overrun error occurs and receive completes by error w hen receive. When the next serial data receive is completed w hile the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1. After the ORER bit is set to 1 (overrun error occurs), do not transmit or receive w hile the ORER bit is set to 1. Nothing is assigned. If necessary, set to 0. When read, the content is 0. TDRE Transmit data empty(1,5,6) 0 : Data is not transferred from the SSTDR to SSTRSR registers 1 : Data is transferred from the SSTDR to SSTRSR registers RW b3 b2 b1b7 b6 b5 b4 RDRF Receive data register full (1,4) (b1) Nothing is assigned. If necessary, set to 0. When read, the content is 0. 0 : No data in SSRDR register 1 : Data in SSRDR register RW ORER (b4-b3) CE RW RW Conflict error flag(1) 0 : No conflict error occurs 1 : Conflict error occurs(2) The TDRE bit is set to 1 w hen setting the TE bit in the SSER register to 0 (disables transmit). The RDRF bit is set to 0 w hen reading out the data from the SSRDR register. Overrun error flag(1) 0 : No overrun error occurs 1 : Overrun error occurs (3) The TEND and TDRE bits are set to “0” w hen w riting the data to the SSTDR register. TEND Transmit end(1,5) 0 : The TDRE bit is set to 0 w hen transmitting the end of the bit in transmit data 1 : The TDRE bit is set to 1 w hen transmitting the end of the bit in transmit data RW When accessing the SSSR register continuously, insert one or more NOP instructions betw een the instructions to access it. changes the level from “L” to “H” during transfer, the CE bit is set to 1. When the serial communication is started w hile the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device), the CE bit is set to 1 if “L” is applied to the SCS pin input. Refer to 16.2.7 SCS Pin Control and Arbitration for m ore inform ation. SSCRH register is set to 0 (operates as slave device) is set to 0 (operates as slave device) and the SCS pin input When the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus communication mode), the MSS bit in the

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 290 of 458 REJ09B0250-0200 Figure 16.7 SSMR2 Register SS Mode Register 2 Symbol Address After Reset SSMR2 00BDh 00h Bit Symbol Bit Name Function RW SCS pin open drain output select 0 : CMOS output 1 : N-channel open drain output SCS pin select bit(2) b5 b4 0 0 : Functions as port 0 1 : Function as SCS input pin 1 0 : Function as SCS output pin(3) 1 1 : Functions as SCS output pin(3) NOTES: The BIDE bit is disabled w hen the SSUMS bit is set to 0 (clock synchronous communication mode). RWBIDE Bidirectional mode enable bit(1,4) 0 : Standard mode (communicates using 2 pins of data input and data output) 1 : Bidirectional mode (communicates using 1 pin of data input and data output) This bit functions as the SCS input pin before starting transfer. set to 0 (clock synchronous communication mode). The SSI pin and SSO pin corresponding port direction bits are set to 0 (input mode) w hen the SOOS bit is set to 0 (CMOS output). RW RW RW RW RW RW 0 : Clock synchronous communication mode 1 : Four-w ire bus communication mode SSCK pin open drain output select bit 0 : CMOS output 1 : N-channel open drain output CSS1 Clock synchronous serial I/O w ith chip select mode select bit(1) SSO pin open drain output select bit(1) 0 : CMOS output(5) 1 : N-channel open drain output CSS0 SOOS SCKOS SSUMS CSOS b2 b1b7 b6 b5 b4 b0 Ref er to 16.2.2.1 Association betw een Data I/O Pins and SS Shift Register for the combination of the data I/O pin. The SCS pin functions as a port, regardless of the contents of the CSS0 and CSS1 bits w hen the SSUMS bit is SCKS SSCK pin select bit 0 : Functions as port 1 : Functions as serial clock pin RW

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16.2.1 Transfer Clock

A transfer clock can be selected from 7 internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8 and f1/4) and an external clock. When using the clock synchronous serial I/O with chip select, set the SCKS bit in the SSMR2 register to 1 and select the SSCK pin as the serial clock pin. When the MSS bit in the SSCRH register is set to 1 (operates as master device), an internal clock can be selected and the SSCK pin functions as output. When tran sfer is started, the SSCK pin outputs clocks of the transfer rate selected in the CKS0 to CKS2 bits in the SSCRH register. When the MSS bit in the SSCRH register is set to 0 (operates as slave device), an external clock can be selected and the SSCK pin functions as input.

16.2.1.1 Association between Transf er Clock Polarity, Phase, and Data

Association between transfer clock polarity, phase and data changes according to a combination of the SSUMS bit in the SSMR2 register and the CPHS and CPOS bits in the SSMR register. Figure 16.10 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data. Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register. When the MLS bit is set to 1, transfer is started from the LSB to MSB. When the MLS bit is set to 0, transfer is started from the MSB to LSB.

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 293 of 458 REJ09B0250-0200 Figure 16.10 Association between Transfer Clock Polarity, Phase, and Transfer Data SSCK b0SSO, SSI

• When SSUMS bit = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd edge) and CPOS bit = 0 (“H” when clock stops) b1 b2 b3 b4 b5 b6 b7 SSCK CPOS = 0 (“H” when clock stops) b0SSO, SSI
• When SSUMS bit = 1 (4-wire bus communication mode) and CPHS bit = 0 (data change at odd edge) b1 b2 b3 b4 b5 b6 b7 SSCK CPOS = 1 (“L” when clock stops) SCS SSCK CPOS = 0 (“H” when clock stops) SSO, SSI
• When SSUMS bit = 1 (4-wire bus communication mode), CPHS bit = 1 (data download at odd edge) SSCK CPOS = 1 (“L” when clock stops) SCS b0 b1 b2 b3 b4 b5 b6 b7 CPHS and CPOS: bits in SSMR register, SSUMS: Bits in SSMR2 register

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16.2.2 SS Shift Register (SSTRSR)

The SSTRSR register is the shift register to transmit and receive the serial data. When the transmit data is transferre d from the SSTDR register to the SSTR SR register and the MLS bit in the SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to the bit 0 in the SSTRSR register. When the MLS bit is set to 1 (LSB-first), the bit 7 in the SSTDR register is transferred to the bit 0 in the SSTRSR register.

16.2.2.1 Association between Data I/O Pins and SS Shift Register

Connecting association between the da ta I/O pin and SSTRSR register (S S shift register) changes according to a combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. Also, connecting association changes according to the BIDE bit in the SSMR2 register. Figure 16.11 shows an Association between Data I/O Pins and SSTRSR Register. Figure 16.11 Association between Da ta I/O Pins and SSTRSR Register SSTRSR Register SSO SSI

• When SSUMS bit = 0 (clock synchronous communication mode) SSTRSR Register SSO SSI
• When SSUMS bit = 1 (4-wire bus communication mode), BIDE bit = 0 (standard mode) and MSS bit = 0 (operates as slave device) SSTRSR Register SSO SSI
• When SSUMS bit = 1 (4-wire bus communication mode), BIDE bit = 0 (standard mode) and MSS bit = 1 (operates as master device) SSTRSR Register SSO SSI
• When SSUMS bit = 1 (4-wire bus communication mode), BIDE bit = 1 (bidirectional mode)

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16.2.3 Interrupt Requests

Clock synchronous serial I/O with chip select has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error and conflict error. Since these interrupt requests are assigned to the clock synchronous serial I/O with chip select interrupt vector table, determining interrupt sources by flags is required. Table 16.3 shows the Clock Synchronous Serial I/O with Chip Select Interrupt Requests. CEIE, RIE, TEIE and TIE: Bits in SSER register ORER, RDRF, TEND and TDRE: Bits in SSSR register Generation conditions of Table 16.3 are met, a clock synchronous serial I/O with chip select interrupt request is generated. Set the each interrupt source to 0 by a clock synchronous serial I/O with chip select interrupt routine. However, the TDRE and TEND bits are automatically set to 0 by writing the transmit data to the SSTDR register and the RDRF bit is automatically set to 0 by reading the SSRDR register. When writing the transmit data to the SSTDR register, at the same time the TDRE bit is set to 1 (data is transmitted from the SSTDR to SSTRSR registers) again and when setting the TDRE bit to 0 (data is not transmitted from the SSTDR to SSTRSR registers), additional 1-byte data may be transmitted. Table 16.3 Clock Synchronous Serial I/O with Chip Select Interrupt Requests Interrupt Request Abbreviation Generation Condition Transmit Data Empty TXI TIE = 1, TDRE = 1 Transmit End TEI TEIE = 1, TEND = 1 Receive Data Full RXI RIE = 1, RDRF = 1 Overrun Error OEI RIE = 1, ORER = 1 Conflict Error CEI CEIE = 1, CE = 1

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16.2.4 Communication Mo des and Pin Functions

Clock synchronous serial I/O with chip select switch es functions of the I/O pin in each communication mode according to the setting of the MSS bit in the SSCRH register and the RE and TE bits in the SSER register. Table 16.4 shows the Association between Communication Modes and I/O Pins. NOTES: 1. This pin can be used as programmable I/O port. 2. Do not set both the TE and RE bits to 1 in 4-wire bus (bidirectional) communication mode. SSUMS and BIDE: Bits in SSMR2 register MSS: Bit in SSCRH register TE and RE: Bits in SSER register Table 16.4 Association between Communication Modes and I/O Pins Communication Mode Bit Setting Pin State SSUMS BIDE MSS TE RE SSI SSO SSCK Clock Synchronous Communication Mode

0 Disabled 0 0 1 Input −

(1) Input 10 −(1) Output Input

1 Input Output Input

101 I n p u t −(1) Output

10 −(1) Output Output

1 Input Output Output

1 0 001 −(1) Input Input 1 0 Output −(1) Input

1 Output Input Input

10 −(1) Output Output (Bidirectional) Communication Mode(2) 1 1 001 −(1) Input Input 10 −(1) Output Input 101 −(1) Input Output 10 −(1) Output Output

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16.2.5 Clock Synchronous Communication Mode

16.2.5.1 Initialization in Cl ock Synchronous Communication Mode

Figure 16.12 shows an Initialization in Clock Synchronous Communication Mode. Set the TE bit in the SSER register to 0 (disables transmit) and the RE bit to 0 (disables receive) before da ta transmit / receive as an initialization. When communication mode and format are changed, set the TE bit to 0 and the RE bit to 0 before changing. Setting the RE bit to 0 does not change the contents of the RDRF and ORER flags, and the contents of the SSRDR register. Figure 16.12 Initialization in Cl ock Synchronous Communication Mode Start SSMR2 register SSUMS bit ← 0 SSCRH register Set CKS0 to CKS2 bits Set RSSTP bit SSSR register ORER bit ← 0(1) SSER register RE bit ← 1 (When receive) TE bit ← 1 (When transmit) Set RIE, TEIE and TIE bits End NOTE: 1. Write 0 after reading 1 to set the ORER bit to 0. SSER register RE bit ← 0 TE bit ← 0 SSMR2 register SCKS bit ← 1 Set SOOS bit SSCRH register Set MSS bit SSMR register CPHS bit ← 0 CPOS bit ← 0 Set MLS bit

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16.2.5.2 Data Transmission

Figure 16.13 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data Transmission (Clock Synchronous Communication Mode). During the data transmit, the clock synchronous serial I/O with chip select operates as described below. When the clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and data. When the clock synchronous serial I/O with chip select is set as a slave device, it outputs data synchronized with the input clock. When setting the TE bit to 1 (enables transmit) before writing the transmit data to the SSTDR register, the TDRE bit is automatically set to 0 (data is not transferred from the SSTDR to SSTRSR registers) and the data is transferred from the SSTDR to SSTRSR registers. After the TDRE bit is set to 1 (data is transferred from the SSTDR to SSTRSR regist ers), a transmit is started. When the TIE bit in the SSER register is set to 1, the TXI interrupt request is generated. When one frame of data is transferred while the TDRE bit is set to 0, da ta is transferred from the SSTDR to SSTRSR registers and a transmit of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set to 1, the TEND bit in the SSSR register is set to 1 (the TDRE bit is set to 1 when the last bit of the transmit data is transmitted) and the state is retained. The TEI interrupt request is generate d when the TEIE bit in the SSER register is set to 1 (enables transmit-end interrupt request). The SSCK pin is retained “H” after transmit-end. Transmit can not be performed while the ORER bit in the SSSR register is set to 1 (overrun error occurs). Confirm that the ORER bit is set to 0 before transmit. Figure 16.14 shows a Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode). Figure 16.13 Example of Clock Synchronous Serial I/O with Chip Select Operation for Data Transmission (Clock Synchronous Communication Mode) SSCK b0SSO

• When SSUMS bit = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd numbers) and CPOS bit = 0 (“H” when clock stops) b1 b7b0 b1b7 1 frame TDRE bit in SSSR register 0 TEND bit in SSSR register 0 TEI interrupt request generation Write data to SSTDR registerProcess by program 1 frame TXI interrupt request generation

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 299 of 458 REJ09B0250-0200 Figure 16.14 Sample Flowchart of Data Transmis sion (Clock Synchronous Communication Mode) Start Initialization Read TDRE bit in SSSR register SSSR register TEND bit ← 0(1) End TDRE = 1 ? Write transmit data to SSTDR register Data transmit continued? Read TEND bit in SSSR register TEND = 1 ? No Yes Yes No No Yes SSER register TE bit ← 0 (1) (2) (3) (1) After reading the SSSR register and confirming that the TDRE bit is set to 1, write the transmit data to the SSTDR register. When write the transmit data to the SSTDR register, the TDRE bit is automatically set to 0. (2) Determine whether data transmit is continued (3) When the data transmit is completed, the TEND bit is set to 1. Set the TEND bit to 0 and the TE bit to 0 and complete transmit mode. NOTE: 1. Write 0 after reading 1 to set the TEND bit to 0.

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16.2.5.3 Data Reception

Figure 16.15 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data Reception (Clock Synchronous Communication Mode). During the data receive, the clock synchronous serial I/ O with chip select operates as described below. When the clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and inputs data. When the clock synchronous serial I/O with chip select is set as a salve device, it outputs data synchronized with the input clock. When the clock synchronous serial I/O with chip select is set as a master device, it outputs a receive clock and starts receiving by performing dummy read on the SSRDR register. After the 8-bit data is received, the RD RF bit in the SSSR register is set to 1 (data in the SSRDR register) and receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (enables RXI and OEI interrupt request), the RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is automatically set to 0 (no data in the SSRDR register). Read the receive data after setting the RSSTP bit in th e SSCRH register to 1 (after receiving 1-byte data, the receive operation is completed). The clock synchronous serial I/O with chip select outputs a clock for receiving 8-bit data and stops. After that, set the RE bit in the SSER register to 0 (disables receive) and the RSSTP bit to 0 (receive operation is continued after receiving th e 1-byte data) and read the receive data. If the SSRDR register is read while the RE bit is set to 1 (enables receive), a receive clock is output again. When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun error occurs: OEI) and the oper ation is stopped. When the ORER bit is set to 1, receive can not be performed. Confirm that the ORER bit is set to 0 before restarting receive. Figure 16.16 shows a Sample Flowchart of Data Re ception (MSS = 1) (Clock Synchronous Communication Mode). Figure 16.15 Example of Clock Synchronous Serial I/O with Chip Select Operation for Data Reception (Clock Synchronous Communication Mode) SSCK b0SSI

• When SSUMS bit = 0 (clock synchronous commun ication mode), CPHS bit = 0 (data download at even edges) and CPOS bit = 0 (“H” when clock stops) b0b7 1 frame RDRF bit in SSSR register RSSTP bit in SSCRH register 0 Dummy read in SSRDR register Process by program RXI interrupt request generation b0b7 b7 1 frame RXI interrupt request generation Read data in SSRDR register Read data in SSRDR register Set RSSTP bit to 1 RXI interrupt request generation

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 301 of 458 REJ09B0250-0200 Figure 16.16 Sample Flowchart of Data Recepti on (MSS = 1) (Clock Synchronous Communication Mode) Start Initialization Dummy read on SSRDR register Read receive data in SSRDR register Read ORER bit in SSSR register Last data received? Read RDRF bit in SSSR register RDRF = 1 ? No Yes Yes No No Yes (1) (2) (3) (1) After setting each register in the clock synchronous serial I/O with chip select register, dummy read on the SSRDR register is performed and receive operation is started. (2) Determine whether the last 1-byte data is received. When the last 1-byte data is received, set to stop after the data is received. (3) When a receive error occurs, perform an error (6) process after reading the ORER bit. Then set the ORER bit to 0. Transmit/receive can not be restarted while the ORER bit is set to 1. (4) Confirm that the RDRF bit is set to 1. If the RDRF bit is set to 1, read the receive data in the SSRDR register. If the SSRDR register is read, the RDRF bit is automatically set to 0. ORER = 1 ? End Read receive data in SSRDR register Read ORER bit in SSSR register Read RDRF in SSSR register RDRF = 1 ? No Yes ORER = 1 ? SSER register RE bit ← 0 SSCRH register RSSTP bit ← 0 SSCRH register RSSTP bit ← 1 Overrun error process No Yes (4) (5) (6) (7) (7) Confirm that the RDRF bit is set to 1. When the receive operation is completed, set the RSSTP bit to 0 and the RE bit to 0 before reading the last 1-byte data. If the SSRDR register is read before setting the RE bit to 0, the receive operation is restarted again. (5)Before the last 1-byte data is received, set the RSSTP bit to 1 and stop after the data is received.

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16.2.5.4 Data Transmission/Reception

Data transmit/receive is a combined opera tion of data transmit and recei ve which are described before. Transmit/receive is started by writing data in the SSTDR register. When the 8th clock rises or the ORER bit is set to 1 (ove rrun error occurs) while the TDRE bit is set to 1 (data is transferred from the SSTDR to SSTRSR registers), the transmit/receive operation is stopped. When switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (Te = RE =1), set the TE bit to 0 and RE bit to 0 before switching. After confirming that the TEND bit is set to 0 (the TDRE bit is set to 0 when the last bit of the transmit data is transmitted), the RERF bit is set to 0 (no data in the SSRDR register) and the ORER bit is set to 0 (no overrun error), set the TE and RE bits to 1. Figure 16.17 shows a Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication Mode). When exiting transmit/receive mode after this mode is used (TE = RE = 1), a clock may be output if transmit/ receive mode is exited after reading the SSRDR register. To avoid any cl ock outputs, perform either of the following:

• First set the RE bit to 0, and then set the TE bit to 0.
• Set bits TE and RE at the same time. When subsequently switching to receive mode (TE = 0 and RE = 1), first set the SRES bit to 1, and set this bit to 0 to reset the clock synchronous serial interface control unit and the SSTRSR register. Then, set the RE bit to

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 303 of 458 REJ09B0250-0200 Figure 16.17 Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication Mode) Start Initialization Read TDRE bit in SSSR register SSSR register TEND bit ← 0(1) End TDRE=1 ? Write transmit data to SSTDR register Data transmit continued? No Yes Yes No SSER register RE bit ← 0 TE bit ← 0 (1) (2) (3) (1) After reading the SSSR register and confirming that the TDRE bit is set to 1, write the transmit data in the SSTDR register. When writing the transmit data to the SSTDR register, the TDRE bit is automatically set to 0. (5) Set the TEND bit to 0 and (6) the RE and TE bits in the SSER register to 0 before ending transmit/receive mode. Read receive data in SSRDR register Read RDRF bit in SSSR register RDRF=1 ? No Yes (4) (2) Confirm that the RDRF bit is set to 1. If the RDRF bit is set to 1, read the receive data in the SSRDR register. When reading the SSRDR register, the RDRF bit is automatically set to 0. (3) Determine whether the transmit data is continued. (5) NOTE: 1. Write 0 after reading 1 to set the TEND bit to 0. Read TEND bit in SSSR register TEND=1 ? Yes No (6) (4) When the data transmit is completed, the TEND bit in the SSSR register is set to 1.

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16.2.6 Operation in 4-Wire Bus Communication Mode

4-wire bus communication mode is a mode which communi cates with the 4-wire bus; a clock line, data input line, data output line and chip select line. This mode includes bidirectional mode in which the data input line and data output line function as a single pin. The data input line and output line are changed according to the setting of the MSS bit in the SSCRH register and the BIDE bit in the SSMR2 register. For details, refer to 16.2.2.1 Association between Data I/O Pins and SS Shift Register. In this mode, association between the clock polarity, phase and data can be set by the CPOS and CPHS bits in the SSMR register. For details, refer to 16.2.1.1 Association between Transfer Clock Polarity, Phase, and Data. When the clock synchronous serial I/O with chip select is set as a master device, the chip select line controls output. When the clock synchronous serial I/O with chip select is set as a slave device, the chip select line controls input. When the clock synchronous serial I/O with chip select is set as master device, the chip select line controls output of the SCS pin or controls output of a general port by setting the CSS1 bit in the SSMR2 register. When the clock synchronous serial I/O with chip se lect is set as a slave device, the chip select line set the SCS pin as an input pin by setting the CSS1 and CSS0 bits in the SSMR2 register to 01b. In 4-wire bus communication mode, the MLS bit in th e SSMR register is set to 0 and communication is performed using the MSB-first.

16.2.6.1 Initialization in 4-Wire Bus Communication Mode

Figure 16.18 shows an Initialization in 4-Wire Bus Comm unication Mode. Before the data transit/receive, set the TE bit in the SSER register to 0 (disables transmit) and the RE bit in the SSER register to 0 (disables receive) and initialize the clock synchronous serial I/O with chip select. When communication mode and format are changed, set the TE bit to 0 and the RE bit to 0 before changing. Setting the RE bit to 0 does not change the contents of the RDRF and ORER flags, and the contents of the SSRDR register.

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 305 of 458 REJ09B0250-0200 Figure 16.18 Initialization in 4-Wire Bus Communication Mode Start SSMR2 register SSUMS bit ← 1 SSSR register ORER bit ← 0(1) SSER register RE bit ← 1 (receive) TE bit ← 1 (transmit) Set bits RIE, TEIE, and TIE End SSER register RE bit ← 0 TE bit ← 0 (2) Set the BIDE bit to 1 in bidirectional mode and set the I/O of the SCS pin by bits CSS0 and CSS1. (1) (1) The MLS bit is set to 0 for MSB-first transfer. The clock polarity and phase are set by bits CPHS and CPOS. (2) NOTE: 1. Write 0 after reading 1 to set the ORER bit to 0. SSMR2 register SCKS bit ← 1 Set bits SOOS, CSS0 to CSS1, and BIDE SSCRH register Set MSS bit SSMR register Set bits CPHS and CPOS MLS bits ← 0 SSCRH register Set bits CKS0 to CKS2 Set RSSTP bit

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16.2.6.2 Data Transmission

Figure 16.19 shows an Example of Clock Synchronous Se rial I/O with Chip Select Operation during Data Transmission (4-Wire Bus Communication Mode). During th e data transmit, the clock synchronous serial I/O with chip select operates as described below. When the clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and data. When the UUSA is set as a slave device, it outputs data in synchronized with the input clock while “L” applies to the SCS pin. When writing the transmit data to the SSTDR register after setting the TE bit to 1 (enables transmit), the TDRE bit is automatically set to 0 (data is not transferre d from the SSTDR to SSTRSR registers) and the data is transferred from the SSTDR to SSTRSR registers. After the TDRE bit is set to 1 (data is transferred from the SSTDR to SSTRSR registers), a transmit is started. When the TIE bit in the SSER register is set to 1, the TXI interrupt request is generated. When the 1-frame data is transferred while the TDRE bit is set to 0, the data is transferred from the SSTDR to SSTRSR registers and the next frame transmit is started. If the 8th bit is transmitted while the TDRE is set to 1, the TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted, the TDRE bit is set to 1) and the state is retained. If the TEIE bit in the SSER register is set to 1 (enables transmit-end interrupt request), the TEI interrupt request is generated. The SS CK pin is retained “H” after transmit-end and the SCS pin is held “H”. When the SCS pin is transmitted When transmitting continuously while the SCS pin is held “L”, write the next transmit data to the SSTDR register before transmitting the 8th bit. Transmit can not be performed while the ORER bit in the SSSR register is set to 1 (overrun error occurs). Confirm that the ORER bit is set to 0 before transmit. The difference from the clock synchronous communication mode is that the SSO pin is placed in high- impedance state while the SCS pin is placed in high-impedance state when operating as a master device and the SSI pin is placed in high-i mpedance state while the SCS pin is placed in “H” input state when operating as a slave device. A sample flowchart is the same as the cloc k synchronous communication mode (refer to Figure 16.14 Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)).

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 307 of 458 REJ09B0250-0200 Figure 16.19 Example of Clock Synchronous Serial I/O with Chip Select Operation during Data Transmission (4-Wire Bus Communication Mode) TDRE bit in SSSR register TEND bit in SSSR register 0 Data write to SSTDR registerProcess by program SSCK b0SSO

• When CPHS bit = 0 (data change at even edges), CPOS bit = 0 (“H” when clock stops) SCS (Output) SSCK
• When CPHS bit = 1 (data change at even edges), CPOS bit = 0 (“H” when clock stops) CPHS, CPOS: Bits in SSMR register 1 frame TDRE bit in SSSR register 0 TEND bit in SSSR register 0 Data write to SSTDR registerProcess by program 1 frame High-impedance b0b7 High-impedance SCS (output) TXI interrupt request is generated b7 b0SSO 1 frame 1 frame b6 b6 TXI interrupt request is generated TEI interrupt request is generated b6 b7 b0b6 TEI interrupt request is generated TXI interrupt request is generated TXI interrupt request is generated

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16.2.6.3 Data Reception

Figure 16.20 shows an Example of Clock Synchronous Se rial I/O with Chip Select Operation during Data Reception (4-Wire Bus Communication Mode). During the data receive, the clock synchronous serial I/O with chip select operates as described below. When the clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and inputs data. When the clock synchronous serial I/O with chip select is set as a salve device, it outputs data synchronized with the input clock while the SCS pin is held “L” input. When the clock synchronous serial I/O with chip select is set as a master device, it output s a receive clock and starts receiving by performing dummy read on the SSRDR register. After the 8-bit data is received, the RD RF bit in the SSSR register is set to 1 (data in the SSRDR register) and receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (enables RXI and OEI interrupt request), the RXI interrupt request is gene rated. If the SSRDR register is read, the RDRF bit is automatically set to 0 (no data in the SSRDR register). Read the receive data after setting the RSSTP bit in th e SSCRH register to 1 (after receiving 1-byte data, the receive operation is completed). The clock synchronous serial I/O with chip select outputs a clock for receiving 8-bit data and stops. After that, set the RE bit in the SSER register to 0 (disables receive) and the RSSTP bit to 0 (receive operation is continued after receiving 1-byte data) and read the receive data. If the SSRDR register is read while the RE bit is set to 1 (enables receive), a receive clock is output again. When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun error occurs: OEI) and the oper ation is stopped. When the ORER bit is set to 1, receive can not be performed. Confirm that the ORER bit is set to 0 before restarting receive. When the RDRF and ORER bits are set to 1, it varies depending on setting the CPHS bit in the SSMR register. Figure 16.20 shows when the RDRF and ORER bits are set to 1. When the CPHS bit is set to 1 (data download at the odd edges), the RDRF and ORER bits are set to 1 at one point of a frame. A sample flowchart is the same as the cloc k synchronous communication mode (refer to Figure 16.16 Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)).

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 309 of 458 REJ09B0250-0200 Figure 16.20 Example of Clock Synchronous Serial I/O with Chip Select Operation during Data Reception (4-Wire Bus Communication Mode) SSCK b0SSI

• When CPHS bit = 0 (data download at even edges) and CPOS bit = 0 (“H” when clock stops) SCS (Output) SSCK
• When CPHS bit = 1 (data download at odd edges) and CPOS bit = 0 (“H” when clock stops) CPHS and CPOS: Bit in SSMR register 1 frame RDRF bit in SSSR register 0 RSSTP bit in SSCRH register 0 Dummy read in SSRDR register Process by program 1 frame High-impedance b0b7 High-impedance SCS (Output) b7 b0 Data read in SSRDR register RXI interrupt request is generated RXI interrupt request is generated Data read in SSRDR register RXI interrupt request is generated b0b7b0b7b7 b0SSI 1 frame RDRF bit in SSSR register 0 RSSTP bit in SSCRH register 0 Dummy read in SSRDR register Process by program 1 frame Data read in SSRDR register RXI interrupt request is generated RXI interrupt request is generated RXI interrupt request is generated Set RSSTP bit to 1 Data read in SSRDR register Set RSSTP bit to 1

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16.2.7 SCS Pin Control and Arbitration

When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode), and the CSS1 bit in the SSMR2 register to 1 (functions as SCS output pin), Set the MSS bit in the SSCRH register to 1 (operates as a master device) and check the arbitration of the SCS pin before starting serial transfer. If the clock synchronous serial I/O with chip select detects that the synchronized internal SCS signal is held “L” in this period, the CE bit in the SSSR register to 1 (a conflict error occurs) and the MSS bit is automa tically set to 0 (operates as a slave device). Figure 16.21 shows an Arbitration Check Timing. A future transmit operation is not performed while the CE bit is set to 1. Set the CE bit to 0 (a conflict error does not occur) before a transmit is started. Figure 16.21 Arbitration Check Timing Data write to SSTDR register Maximum time of SCS internal synchronization During arbitration detection High-impedance SCS input Internal SCS (synchronization) MSS bit in SSCRH register Transfer start CE SCS output

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16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select

Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use the clock synchronous serial I/O with chip select.

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16.3 I 2C Bus Interface

The I2C bus interface is the circuit which is used for a serial communication based on the data transfer format of the Philips I2C bus. Table 16.5 lists a I 2C bus Interface Specifications, Figur e 16.22 shows a Block Diagram of I 2C bus Interface and Figure 16.23 shows the External Circuit Connection Example of Pins SCL and SDA. Figures 16.24 to 16.31 show the registers associated with the I2C bus interface. * I2C bus is a trademark of Koninklijke Philips Electronics N. V . NOTE: 1. The interrupt sources can use the only I 2C bus interface interrupt vector table. Table 16.5 I 2C Bus Interface Specifications Item Specification Communication Formats

• I2C bus format - Selectable for master / slave device - Continuous transmit / receive (since the shift register, transmit data register and receive data register are independent) - Start / stop conditions are automatically generated in master mode - Automatic loading of acknowledge bit when transmit - Bit synchronization / wait function (in master mode, the state of the SCL signal is monitored per bit and the timing is synchronized automatically. If the transfer is not possible yet, stand by to set the SCL signal to “L”. - Direct drive of the SCL and SDA pins (N-channel open drain output) is enabled
• Clock synchronous serial format - Continuous transmit / receive (since the shift register, transmit data register and receive data register are independent) I/O Pins SCL (I/O): Serial clock I/O pin SDA (I/O): Serial data I/O pin Transfer Clocks • When the MST bit in the ICCR1 register is set to 0 The external clock (input from the SCL pin)
• When the MST bit in the ICCR1 register is set to 1 The internal clock selected by the CKS0 to CKS3 bits in the ICCR1 register (output from the SCL pin) Receive Error Detection • Detects overrun error (clock synchronous serial format) An overrun error occurs during receive. When the last bit of the following data is received while the RDRF bit in the ICSR register is set to 1 (data in the ICDRR register), the AL bit is set to 1. Interrupt Sources •I Transmit data empty (including when slave address matches), transmit ends, receive data full (including when slave address matches), arbitration lost, NACK detection and stop condition detection. Transmit data empty, transmit ends, receive data full and overrun error Select Functions •I2C bus format - Selectable for the output level of the acknowledge signal when receive
• Clock synchronous serial format - Selectable for the MSB-first or LSB-first to the data transfer direction

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 313 of 458 REJ09B0250-0200 Figure 16.22 Block Diagram of I 2C Bus Interface ICCR1 register Data bus ICCR2 register ICMR register ICDRT register SAR register ICSR register Address comparison circuit Output control SCL Interrupt request (TXI, TEI, RXI, STPI, NAKI) Transfer clock generation circuit ICDRS register ICDRR register Bus state judgment circuit Arbitration judgment circuit ICIER register Interrupt generation circuit Transmit / receive control circuit Noise rejection circuit SDA Output control Noise rejection circuit

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 314 of 458 REJ09B0250-0200 Figure 16.23 External Circuit Connect ion Example of Pins SCL and SDA SCL SDA SCL input SCL output SDA input SDA output (Master) VCC VCC SCL SDA SCL input SCL output SDA input SDA output (Slave 1) SCL SDA SCL input SCL output SDA input SDA output SCL SDA (Slave 2)

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 315 of 458 REJ09B0250-0200 Figure 16.24 ICCR1 Register IIC Bus Control Register 1 Symbol Address After Reset ICCR1 00B8h 00h Bit Symbol Bit Name Function RW NOTES: M aster / slave select bit(5,6) In master mode w ith the I2C bus format, w hen arbitration is lost, the MST and TRS bits are set to 0 and the IIC enters slave receive mode. When an overrun error occurs in master receive mode of the clock synchronous serial format, the MST bit is set to 0 and the IIC enters slave receive mode. Rew rite the TRS bit betw een the transfer frame. RCV D Receive disable bit After reading the ICDRR register w hile the TRS bit is set to 0 0 : Maintains the follow ing receive operation 1 : Disables the follow ing receive operation RW b3 b2 RW RW b1b7 b6 b5 b4 CKS2 CKS3 CKS0 CKS1 RW TRS Transmit clock select bit 3 to 0(1) b3 b2 b1 b0 0 0 0 0 : f1/28 0 0 0 1 : f1/40 0 0 1 0 : f1/48 0 0 1 1 : f1/64 0 1 0 0 : f1/80 0 1 0 1 : f1/100 0 1 1 0 : f1/112 0 1 1 1 : f1/128 1 0 0 0 : f1/56 1 0 0 1 : f1/80 1 0 1 0 : f1/96 1 0 1 1 : f1/128 1 1 0 0 : f1/160 1 1 0 1 : f1/200 1 1 1 0 : f1/224 1 1 1 1 : f1/256 b5 b4 0 0 : Slave receive mode(4) 0 1 : Slave transmit mode 1 0 : Master receive mode 1 1 : Master transmit mode RW MST RW RW Transfer / receive select bit (2,3,6) In multimaster operation use the MOV instruction to set bits TRS and MST. When the first 7 bits, after the start condition in slave receive mode, match w ith the slave address set in the SAR register and the 8th bit is set to 1, the TRS bit is set to 1. RWICE I2C bus interface enable bit 0 : This module is halted (SCL and SDA pins are set to port function) 1 : This module is enabled for transfer operations (SCL and SDA pins are bus drive state) Set according to the necessary transfer rate in master mode. Refer to Table 16.6 Transfer R ate E xamples for the transfer rate. This bit is used for maintaining of the setup time in transmit mode. The time is 10Tcyc w hen the CKS3 bit is set to 0 and 20Tcyc w hen the CKS3 bit is set to 1. (1Tcyc = 1/f1(s))

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 316 of 458 REJ09B0250-0200 Figure 16.25 ICCR2 Register IIC Bus Control Register 2 Symbol Address After Reset ICCR2 00B9h 01111101b Bit Symbol Bit Name Function RW NOTES: (b0) N othing is assigned. I f necessary, set to 0. When read, the content is 1. — IICRST RW RO RW IIC control part reset bit b0b3 b2 b1b7 b6 b5 b4 When hang-up occurs due to communication failure during I2C bus interface operation and w rite 1, reset control part of I2C bus interface w ithout setting port and initializing register. (b2) N othing is assigned. I f necessary, set to 0. When read, the content is 1. SCLO SCL monitor flag 0 : SCL pin is set to “L” 1 : SCL pin is set to “H” Do not w rite during transfer operation. SDAOP SDAO RW When read 0 : SDA pin output is held “L” 1 : SDA pin output is held “H” When w rite(1,2) 0 : SDA pin output is changed to “L” 1 : SDA pin output is changed to high-impedance (“H” output is external pull-up resistor) SDA output value control bit SDAO w rite protect bit When rew rite to SDAO bit, w rite 0 simultaneously. (1) When read, its content is 1. BBSY Bus busy bit(4) SCP Start / stop condition generation disable bit When w rite to BBSY bit, w rite 0 simultaneously.(3) When read, its content is 1. Writing 1 is disabled. RW When read 0 : Bus is in released state (SDA signal changes from “L” to “H” w hile SCL signal is in “H” state) 1 : Bus is in occupied state (SDA signal changes from “H” to “L” w hile SCL signal is in “H” state) When w rite (3) 0 : Generates stop condition 1 : Generates start condition RW This bit is disabled w hen the clock synchronous serial format is used. This bit is enabled in master mode. When w rite to the BBSY bit, w rite 0 to the SCP bit using the MOV instruction simultaneously. Execute the same w ay w hen the start condition is regenerating. When w riting to the SDAO bit, w rite 0 to the SDAOP bit using the MOV instruction simultaneously.

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 317 of 458 REJ09B0250-0200 Figure 16.26 ICMR Register IIC Bus Mode Register Symbol Address After Reset ICMR 00BAh 00011000b Bit Symbol Bit Name Function RW MSB-first / LSB-first select NOTES: 6. Set to 0 w hen the I 2C bus format is used. When w rite to the BC0 to BC2 bits, w rite 0 to the BCWP bit using the MOV instruction. (b4) N othing is assigned. I f necessary, set to 0. When read, the content is 1. — Rew rite betw een transfer frames. When w rite values other than 000b, w rite w hen the SCL signal is “L”. After data including the acknow ledge bit is transferred, bits b2 to b0 are automatically set to 000b. When the start condition is detected, these bits are automatically set to 000b. Do not rew rite w hen the clock synchronous serial format is used. Reserved bit When rew rite to the BC0 to BC2 bits, w rite 0 simultaneously.(2,4) When read, its content is 1. RW The setting value is enabled in master mode of the I2C bus format. It is disabled in slave mode of the I2C bus format or w hen the clock synchronous serial format is used. 0 : No w ait (Transfer data and acknow ledge bit consecutively) 1 : Wait (After the falling of the clock for the final data bit, “L” period is extended for tw o transfer clocks) Set to 0 RW RW 0 : Data transfer by MSB-first (6) 1 : Data transfer by LSB-first (b5) WAIT b3 b2 b1 b0b7 b6 b5 b4 Wait insertion bit(5) BCWP BC w rite protect bit RW MLS RW RW BC1 BC2 Bit counter 2 to 0 I 2C bus format (remaining transfer bit numbers w hen read out and data bit numbers of transfer to the next w hen w rite)(1,2) b2 b1 b0 0 0 0 : 9 bits(3) 0 0 1 : 2 bits 0 1 0 : 3 bits 0 1 1 : 4 bits 1 0 0 : 5 bits 1 0 1 : 6 bits 1 1 0 : 7 bits 1 1 1 : 8 bits Clock synchronous serial format (w hen read, read the remaining transfer bit numbers and w hen w rite, w rite 000b.) b2 b1 b0 0 0 0 : 8 bits 0 0 1 : 1 bit 0 1 0 : 2 bits 0 1 1 : 3 bits 1 0 0 : 4 bits 1 0 1 : 5 bits 1 1 0 : 6 bits 1 1 1 : 7 bits BC0 RW

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 318 of 458 REJ09B0250-0200 Figure 16.27 ICIER Register IIC Bus Interrupt Enable Register Symbol Address After Reset ICIER 00BBh 00h Bit Symbol Bit Name Function RW NOTES: b3 b2 b1 NA KIE Transmit acknow ledge select bit 0 : 0 is transmitted as acknow ledge bit in receive mode 1 : 1 is transmitted as acknow ledge bit in receive mode b0b7 b6 b5 b4 AC KE Transmit end interrupt enable bit STIE AC KBT RW RW ROAC KBR RW Receive acknow ledge bit 0 : Acknow ledge bit w hich is received from receive device in transmit mode is set to 0 1 : Acknow ledge bit w hich is received from receive device in transmit mode is set to 1 RW An overrun error interrupt request is generated w hen the clock synchronous format is used. RIE Receive interrupt enable bit 0 : Disables receive data full and overrun error interrupt request 1 : Enables receive data full and overrun error interrupt request(1) RW TIE Transmit interrupt enable bit 0 : Disables transmit data empty interrupt request 1 : Enables transmit data empty interrupt request TEIE Set the STIE bit to 1 (enable stop condition detection interrupt request) w hen the STOP bit in the ICSR register is set to 0. 0 : Disables transmit end interrupt request 1 : Enables transmit end interrupt request RW Acknow ledge bit judgment select bit 0 : Value of receive acknow ledge bit is ignored and continuous transfer is performed 1 : When receive acknow ledge bit is set to 1, continuous transfer is halted RW Stop condition detection interrupt enable bit 0 : Disables stop condition detection interrupt request 1 : Enables stop condition detection interrupt request (2) 0 : Disables NACK receive interrupt request and arbitration lost / overrun error interrupt request 1 : Enables NACK receive interrupt request and arbitration lost / overrun error interrupt request (1) NACK receive interrupt enable bit

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 319 of 458 REJ09B0250-0200 Figure 16.28 ICSR Register IIC Bus Status Register(7) Symbol Address After Reset ICSR 00BCh 0000X000b Bit Symbol Bit Name Function RW NOTES: STOP Stop condition detection flag(1) When the stop condition is detected after the frame is transferred, this flag is set to 1 RW The RDRF bit is set to 0 when reading data f rom the ICDRR register. The TEND and TDRE bits are set to 0 when writing data to the ICDRT register. When two or more master dev ices attempt to occupy the bus at nearly the same time, if the I 2C bus Interf ace monitors the SDA pin and the data which the IIC transmits is dif f erent, the AL f lag is set to 1 and the bus is occupied by the other masters. RWRDRF Receive data register full(1,5) When the 9th clock of the SCL signal w ith the I2C bus format w hile the TDRE bit is set to 1, this flag is set to 1 This flag is set to 1 w hen the final bit of the transmit frame is transmitted w ith the clock synchronous format No acknow ledge detection flag (1,4) This f lag is enabled in slav e receiv e mode of the I 2C bus format. Each bit is set to 0 when reading 1 bef ore writing 0. NA CKF When no acknow ledge is detected from receive device w hen transmit, this flag is set to 1 RW RW When receive data is transferred from ICDRS to ICDRR registers, this flag is set to 1 TEND Transmit end(1,6) RW RW General call address recognition flag(1,2) When detecting the general call address, this flag is set to 1. Arbitration lost flag / overrun error flag (1) When the I2C bus format is used, this flag indicates that arbitration is lost in master mode. In the follow ing case, this flag is set to 1.(3)

• When the internal SDA signal and SDA pin level do not match at the rise of the SCL signal in master transmit mode
• When the start condition is detected and the SDA pin is held “H” in master transmit / receive mode This flag indicates that an overrun error occurs w hen the clock synchronous format is used In the follow ing case, this flag is set to 1.
• When the last bit of the follow ing data is received w hile the RDRF bit is set to 1 Slave address recognition flag (1) This flag is set to 1 w hen the first frame follow ing start condition matches the SVA0 to SVA6 bits in the SAR register in slave receive mode. (Detect the slave address and generate call address) RWAAS AL AD Z b2 b1b7 b6 b5 b4 When accessing the ICSR register continuously , insert one or more NOP instructions between the instructions to access it. The NACKF bit is enabled when the ACKE bit in the ICIER register is set to 1 (when the receiv e acknowledge bit is set to 1, tra nsf er is halted) TDRE Transmit data empty(1,6) I n the follow ing cases, this flag is set to 1
• Data is transferred from ICDRT to ICDRS registers and ICDRT register is empty
• When setting the TRS bit in the ICCR1 register to 1 (transmit mode)
• When generating the start condition (including retransmit)
• When changing from slave receive mode to slave transmit mode RW

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 320 of 458 REJ09B0250-0200 Figure 16.29 Registers SAR and ICDRT Slave Address Register Symbol Address After Reset SAR 00BDh 00h Bit Symbol Bit Name Function RW RW Slave address 6 to 0 Set the different address from the other slave devices w hich are connected to the I2C bus. When the 7 high-order bits of the first frame transmitted after the starting condition match the SVA0 to SVA6 bits in slave mode of the I bus format, the MCU operates as a slave device. RW RW RW RW SVA3 SVA6 SVA5 SVA4 RW RW FS Form at select bit 0 : I 2C bus format 1 : Clock synchronous serial format RW SVA2 SVA0 SVA1 b7 b6 b0 b1b5 b3 b2b4 IIC Bus Transmit Data Register Symbol Address After Reset ICDRT 00BEh FFh RW RW Function Store transmit data When detecting that the ICDRS register is empty, the stored transmit data is transferred to the ICDRS register and the starts transmit data. When the next transmit data is w ritten to the ICDRT register during transmitting the data of the ICDRS register, continuous transmit is enabled. When the MLS bit in the ICMR register is set to 1 (data transferred by LSB-first) and after the data is w ritten to the ICDRT register, the MSB and LSB inverted data is read. b0b7

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16.3.1 Transfer Clock

When the MST bit in the ICCR1 register is set to 0, the transfer clock is the external clock input from the SCL pin. When the MST bit in the ICCR1 register is set to 1, the transfer clock is the in ternal clock selected by the CKS0 to CKS3 bits in the ICCR1 register and the transfer clock is output from the SCL pin. Table 16.6 lists the Transfer Rate Examples. Table 16.6 Transfer Rate Examples ICCR1 Register Transfer Clock Transfer Rate CKS3 CKS2 CKS1 CKS0 f1 = 5 MHz f1 = 8 MHz f1 = 10 MHz f1 = 16 MHz f1 = 20 MHz 0 0 0 0 f1/28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz 1 f1/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz 1 0 f1/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz 1 f1/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 1 0 0 f1/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 f1/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz 200 kHz 1 0 f1/112 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz 179 kHz 1 f1/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz 1 0 0 0 f1/56 89.3 kHz 143 kHz 179 kHz 286 kHz 357 kHz 1 f1/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 0 f1/96 52.1 kHz 83.3 kHz 104 kHz 167 kHz 208 kHz 1 f1/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz 1 0 0 f1/160 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz 125 kHz 1 f1/200 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz 100 kHz

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16.3.2 Interrupt Requests

The interrupt request of the I2C bus interface contains 6 types when the I2C bus format is used and 4 types when the clock synchronous serial format is used. Table 16.7 lists the Interrupt Requests of I2C Bus Interface. Since these interrupt requests are allocated at the I2C bus interface interrupt vector table, determining the source by each bit is necessary. STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register When the generation conditions on the Table 16.7 are met, the I 2C bus interface interrupt request is generated. Set the interrupt generation conditions to 0 by the I 2C bus interface interrupt routin e. However, the TDRE and TEND bits are automatically set to 0 by writing transm it data to the ICDRT register and the RDRF bit is automatically set to 0 by reading the ICDRR register. Wh en writing transmit data to the ICDRT register, the TDRE bit is set to 0. When data is transferred from the ICDRT to ICDRS registers, the TDRE bit is set to 1 and when further setting the TDRE bit to 0, extra 1 byte may be transmitted. Also, set the STIE bit to 1 (enable stop condition detection interrupt request) when the STOP bit is set to 0. Table 16.7 Interrupt Requests of I 2C Bus Interface Interrupt Request Generation Condition Format I2C bus Clock Synchronous Serial Transmit Data Empty TXI TIE = 1 and TDRE = 1 Enabled Enabled Transmit Ends TEI TEIE = 1 and TEND = 1 Enabled Enabled Receive Data Full RXI RIE = 1 and RDRF = 1 Enabled Enabled Stop Condition Detection STPI STIE = 1 and STOP = 1 Enabled Disabled NACK Detection NAKI NAKIE = 1 and AL = 1 (or NAKIE = 1 and NACKF = 1) Enabled Disabled Arbitration Lost / Overrun Error Enabled Enabled

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16.3.3 I 2C Bus Interface Mode

16.3.3.1 I 2C Bus Format

Setting the FS bit in the SAR register to 0 communicates in I2C bus format. Figure 16.32 shows the I 2C Bus Format and Bus Timing. The 1st frame following start condition consists of 8 bits. Figure 16.32 I 2C Bus Format and Bus Timing SDA SCL S SLA R/W A DATA A DATA A P 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 (2) I2C bus timing Explanation of symbols S : Start condition The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”. SLA : Slave address R/W : Indicates the direction of data transmit/receive Data is transmitted from the slave device to the master device when R/ W value is 1 and from the master device to the slave device when R/W value is 0. A : Acknowledge The receive device sets the SDA signal to “L”. DATA : Transmit / receive data P : Stop condition The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”. S R/W A DATA A A/A P 1 7 1 1 n 1 1 1 1 m (a) I2C bus format (FS = 0) Transfer bit numbers (n = 1 to 8) Transfer frame numbers (m = from 1) S R/W A DATA A/A P 1 7 1 1 n1 1 1 1 m1 (b) I2C bus format (when start condition is retransmitted, FS = 0) Upper: Transfer bit numbers (n1, n2 = 1 to 8) Lower: Transfer frame numbers (m1, m2 = from 1 ) SLA SLA A/A S R/W A DATA 7 1 1 n2 SLA 1 m2 (1) I2C bus Format

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16.3.3.2 Master Transmit Operation

In master transmit mode, the master device outputs th e transmit clock and data, and the slave device returns an acknowledge signal. Figure 16.33 and Figure 16.34 show the Operation Timing in Master Transmit Mode (I2C Bus Interface Mode). The transmit procedure and operation in master transmit mode are shown below. (1) Set the STOP bit in the ICSR register to 0 to reset it. And then set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set the WAIT and MLS bits in the ICMR register and set the CKS0 to CKS3 bits in the ICCR1 register (initial setting). (2) Read the BBSY bit in the ICCR2 re gister to confirm that the bus is free. Set the TRS and MST bits in the ICCR1 register to master transmit mode. The st art condition is generated by writing 1 to the BBSY bit and 0 to the SCP bit by the MOV instruction. (3) After confirming that the TDRE b it in the ICSR register is set to 1 (data is transferred from the ICDRT to ICDRS registers), write transmit data to the IC DRT register (data in which a slave address and R/W are shown at the 1st byte). At this time, the TDRE bit is automatically set to 0 and data is transferred from the ICDRT to ICDRS registers, the TDRE bit is set to 1 again. (4) When the transmit of 1-byte data is completed while the TDRE bit is set to 1, the TEND bit in the ICSR register is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in the ICIER register, and confirm that the slave is selected. Write the 2nd-byte data to the ICDRT register. Since the slave device is not acknowledged when the ACKBR bit is set to 1, generate the stop condition. The stop condition is generated by the writing 0 to the BBSY bit and 0 to the SCP bit by the MOV instruction. The SCL signal is held “L” until data is available and the stop condition is generated. (5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1. (6) When writing the number of bytes to be transmitte d to the ICDRT register, wait until the TEND bit is set to 1 while the TDRE bit is set to 1. Or wait for NACK (the NACKF bit in the ICSR register is set to 1) from the receive device while the ACKE bit in the ICIER register is set to 1 (when the receive acknowledge bit is set to 1, transfer is halted). And generate the stop condition before setting the TEND and NACKF bits to 0. (7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode.

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16.3.3.3 Master Receive Operation

In master receive mode, the master device outputs the r eceive clock, receives data from the slave device, and returns an acknowledge signal. Figure 16.35 and Figure 16.36 show the Operation Timing in Master Receive Mode (I2C Bus Interface Mode). The receive procedure and operation in master receive mode are shown below. (1) After setting the TEND bit in th e ICSR register to 0, switch fr om master transmit mode to master receive mode by setting the TRS bit in the ICCR1 register. And set the TDRE bit in the ICSR register to (2) When performing the dumm y-read of the ICDRR register and starting receive, output the receive clock synchronizing with the internal cl ock and receive data. The master de vice outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the 9th clock of the receive clock. (3) The 1-frame data receive is completed and the RDRF bit in the ICSR register is set to 1 at the rise of the 9th clock. At this time, when r eading the ICDRR register, the received data can be read and the RDRF bit is set to 0 simultaneously. (4) The continuous receive is enabled by reading the ICDRR register every time the RDRF bit is set to 1. If the 8th clock falls after reading th e ICDRR register by the other processes while the RDRF bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read. (5) If the following frame is the last receive frame and the RCVD b it in the ICCR1 register is set to 1 (disables the next receive operation) before reading the ICDRR register, the stop condition generation is enabled after the following receive. (6) When the RDRF bit is set to 1 at the rise of the 9th clock of th e receive clock, generate the stop condition. (7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register. And set the RCVD bit to 0 (maintain the following receive operation). (8) Return to slave receive mode.

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 328 of 458 REJ09B0250-0200 Figure 16.35 Operating Timing in Master Receive Mode (I 2C Bus Interface Mode) (1) SDA (master output) SCL (master output) 1896 7 453 b7 b6 b5 b4 b3 b2 b1 b0 b7 SDA (slave output) TDRE bit in ICSR register TEND bit in ICSR register ICDRR register ICDRS register Data 1 Processing by program (1) Set TEND and TRS bits to 0 before setting TDRE bits to 0 A (2) Read ICDRR register Data 1 TRS bit in ICCR1 register RDRF bit in ICSR register A (3) Read ICDRR register Master transmit mode Master receive mode

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 329 of 458 REJ09B0250-0200 Figure 16.36 Operating Timing in Master Receive Mode (I 2C Bus Interface Mode) (2) SDA (master output) SCL (master output) 12 8967453 b7 b6 b5 b4 b3 b2 b1 b0SDA (slave output) RCVD bit in ICCR1 register ICDRR register ICDRS register Data n-1 Processing by program (6) Stop condition generation A/A (8) Set to slave receive mode A Data n RDRF bit in ICSR register Data n Data n-1 (5) Set RCVD bit to 1 before reading ICDRR register (7) Read ICDRR register before setting RCVD bit to 0

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16.3.3.4 Slave Transmit Operation

In slave transmit mode, the slave device outputs the tran smit data while the master device outputs the receive clock and returns an acknowledge signal. Figure 16.37 and Figure 16.38 show the Operation Timing in Slave Transmit Mode (I2C Bus Interface Mode). The transmit procedure and operation in slave transmit mode are shown below. (1) Set the ICE bit in the ICCR1 register to 1 (trans fer operation enabled). Set the WAIT and MLS bits in the ICMR register and CKS0 to CKS3 bits in the ICCR1 register (initial setting). Set the TRS and MST bits in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode. (2) When the slave address matches at the 1st frame after detecting the start condition, the slave device outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock. At this time, if the 8-bit data (R/W ) is set to 1, the TRS and TDRE bit in the ICSR register are set to 1, the mode is switched to slave transmit mode auto matically. When writing transmit data to the ICDRT register every time the TDRE bit is set to 1, the continuous transmit is enabled. (3) When the TDRE bit in the ICDRT register is set to 1 after writing the last transmit data to the ICDRT register, wait until the TEND bit in the ICSR register is set to 1 while the TDRE bit is set to 1. When the TEND bit is set to 1, set the TEND bit to 0. (4) The SCL signal is released by setting the TRS bit to 0 and performing the dummy-read of the ICDRR register for the end process. (5) Set the TDRE bit to 0.

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 331 of 458 REJ09B0250-0200 Figure 16.37 Operating Timing in Slave Transmit Mode (I 2C Bus Interface Mode) (1) SDA (master output) SCL (master output) 1896 7 453 b7 b6 b5 b4 b3 b2 b1 b0 b7 SDA (slave output) TDRE bit in ICSR register TEND bit in ICSR register ICDRR register ICDRS register Data 1 Process by program A Data 2 TRS bit in ICCR1 register A Slave transmit modeSlave receive mode SCL (slave output) ICDRT register Data 1 (1) Data write to ICDRT register (data 1) (2) Data write to ICDRT register (data 2) Data 2 (2) Data write to ICDRT register (data 3) Data 3

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 332 of 458 REJ09B0250-0200 Figure 16.38 Operating Timing in Slave Transmit Mode (I 2C Bus Interface Mode) (2) SDA (slave output) SCL (master output) 12 8967453 b7 b6 b5 b4 b3 b2 b1 b0 SDA (master output) TDRE bit in ICSR register TEND bit in ICSR register ICDRT register ICDRS register Data n Process by program (3) Set the TEND bit to 0 A A Data n Slave receive mode Slave transmit mode TRS bit in ICCR1 register ICDRR register (4) Dummy-read of ICDRR register after setting TRS bit to 0 (5) Set TDRE bit to 0 SCL (slave output)

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16.3.3.5 Slave Receive Operation

In slave receive mode, the master de vice outputs the transmit clock and data, and the slave device returns an acknowledge signal. Figure 16.39 and Figure 16.40 show the Operation Timing in Slave Receive Mode (I2C Bus Interface Mode). The receive procedure and operation in slave receive mode are shown below. (1) Set the ICE bit in the ICCR1 register to 1 (trans fer operation enabled). Set the WAIT and MLS bits in the ICMR register and CKS0 to CKS3 bits in the ICCR1 register (initial setting). Set the TRS and MST bits in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode. (2) When the slave address matches at the 1st frame after detecting the start condition, the slave device outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock. Since the RDRF bit in the ICSR register is set to 1 simultaneously, perform the dummy-read (the read data is unnecessary because of showing slave address and R/W (3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock falls while the RDRF bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of the acknowledge signal which returns to master device before reading the ICDRR register reflects the following transfer frame. (4) Reading the last byte is performed by reading the ICDRR register as well.

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16.3.4 Clock Synchronous Serial Mode

16.3.4.1 Clock Synchronous Serial Format

When setting the FS bit in the SAR register to 1, the clock synchronous serial format is used to communicate. Figure 16.41 shows the Transfer Format of Clock Synchronous Serial Format. When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin and when the MST bit is set to 0, the external clock is input. The transfer data is output between the fall and the foll owing fall of the SCL clock, and data is determined by the rise of the SCL clock. The MSB-first or LSB-first can be selected for the order of the data transfer by setting the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register during the transfer standby. Figure 16.41 Transfer Format of Clock Synchronous Serial Format SCL b0SDA b1 b2 b3 b4 b5 b6 b7

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16.3.4.2 Transmit Operation

In transmit mode, transmit data is output from the SDA pin synchronizing with the fall of the transfer clock. The transfer clock is output when the MST bit in the IC CR1 register is set to 1 and input when the MST bit is set to 0. Figure 16.42 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mode). The transmit procedure and operation in transmit mode are shown below. (1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set the CKS0 to CKS3 bits in the ICCR1 register and set the MST bit (initial setting). (2) The TDRE bit in the ICSR register is set to 1 by selecting transmit mode after setting the TRS bit in the ICCR1 register to 1. (3) Data is transferred from the ICDRT to ICDRS regi sters and the TDRE bit is automatically set to 1 by writing transmit data to the ICDRT register after confirming that the TDRE bit is set to 1. When writing data to the ICDRT register every time the TDRE bit is set to 1, the continuous transmit is enabled. When switching from transmit to receive modes, set the TRS bit to 0 while the TDRE bit is set to 1. Figure 16.42 Operating Timing in Transmit Mode (Clock Synchronous Serial Mode) SDA (output) SCL 87 b7b1b0 ICDRT register ICDRS register Process by program 17 81 b6 b7 b0 b6 b0 TDRE bit in ICSR register TRS bit in ICCR1 register Data 1 Data 2 Data 3 Data 1 Data 2 Data 3 (2) Set TRS bit to 1 (3) Data write to ICDRT register (3) Data write to ICDRT register (3) Data write to ICDRT register (3) Data write to ICDRT register

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16.3.4.3 Receive Operation

In receive mode, data is latched at the rise of the tran sfer clock. The transfer cloc k is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0. Figure 16.43 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode). The receive procedure and operation in receive mode are shown below. (1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set the CKS0 to CKS3 bits in the ICCR1 register and set the MST bit (initial setting). (2) The output of the receive clock stars by setting the MST bit to 1 when the transfer clock is output. (3) Data is transferred from the ICDRS to ICDRR regist ers and the RDRF bit in th e ICSR register is set to 1, when the receive is completed. Since the following-byte data is enabled to receive when the MST bit is set to 1, the continuo us clock is output. The continuous r eceive is enabled by reading the ICDRR register every time the RDRF bit is set to 1. An overrun is detected at the rise of the 8th clock while the RDRF bit is set to 1, the AL bit in the ICSR register is set to 1. At this time, the former receive data is retained in the ICDRR register. (4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (disables the following receive operation) and read the ICDRR register. The SCL signal is fixed “H” after the receive of the following-byte data is completed. Figure 16.43 Operating Timing in Receive Mode (Clock Synchronous Serial Mode) SDA (input) SCL 87 b7b1b0 ICDRR register ICDRS register Process by program 17 81 b6 b7 b0 b6 b0 RDRF bit in ICSR register MST bit in ICCR1 Data 1 Data 2 (2) Set MST bit to 1 (when transfer clock is output) (3) Read ICDRR register TRS bit in ICCR1 Data 2 Data 3Data 1 (3) Read ICDRR register

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16.3.5 Noise Canceller

The state of the SCL and SDA pins are routed through the noise rejection circuit before being latched internally. Figure 16.44 shows the Block Diagram of Noise Canceller. The noise rejection circuit consists of two cascaded latch and match detect or circuits. When the SCL pin input signal (or SDA pin input signal) is sampled on f1 and 2 latch outputs match, the level is passed forward to the next circuit. When they do not match, the former value is retained. Figure 16.44 Block Diagram of Noise Canceller C DQ Latch C DQ Latch Match detection circuit SCL or SDA input signal Internal SCL or SDA signal f1 (sampling clock) Period of f1 f1 (sampling clock)

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16.3.6 Bit Synchronization Circuit

When setting the I2C bus interface in master mode.

• When the SCL signal is driven to “L” by the slave device.
• Since the “H” period may become shorter while the SCL signal is driven to “L” by the slave device and the rising speed of the SCL signal is lowered by the load (load capacity an d pull-up resistor) of the SCL line, the SCL signal is monitored and the communication synchronizes per bit. Figure 16.45 shows the Timing of Bit Synchronous Circui t and Table 16.8 lists the Time between Changing SCL Signal from “L” Output to High-Impedance and Monitoring of SCL Signal. Figure 16.45 Timing of Bit Synchronous Circuit

1 Tcyc = 1/f1(s)

Table 16.8 Time between Changing SCL Signal from “L” Output to High-Impedance and Monitoring of SCL Signal ICCR1 Register Time for Monitoring SCLCKS3 CKS2 0 0 7.5 Tcyc 1 19.5 Tcyc 1 0 17.5 Tcyc 1 41.5 Tcyc VIH Basis clock of SCL monitor timing SCL Internal SCL

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16.3.7 Examples of Register Setting

Figure 16.46 to Figure 16.49 show the Examples of Register Setting When Using I2C Bus Interface. Figure 16.46 Example of Register Setting in Master Transmit Mode (I 2C Bus Interface Mode) Start Initial setting Read BBSY bit in ICCR2 register End BBSY = 0 ? Write transmit data to ICDRT register Transmit mode ? Master receive mode TEND = 1 ? No Yes Yes No (1) Judge the state of the SCL and SDA lines (2) Set to master transmit mode (3) Generate the start condition (4) Set the transmit data of the 1st byte (slave address + R/W) (5) Wait for 1 byte to be transmitted (6) Judge the ACKBR bit from the specified slave device (7) Set the transmit data after 2nd byte (except the last byte) (8) Wait the ICDRT register is empty (9) Set the transmit data of the last byte (10) Wait for the transmit end of the last byte (11) Set the TEND bit to 0 (12) Set the STOP bit to 0 (13) Generate the stop condition (14) Wait the stop condition is generated (15) Set to slave receive mode Set the TDRE bit to 0 ICCR1 register TRS bit ← 1 MST bit ← 1 ICCR2 register SCP bit ← 0 BBSY bit ← 1 Read TEND bit in ICSR register No Read ACKBR bit in ICIER register Yes ACKBR = 0 ? Write transmit data to ICDRT register TDRE = 1 ? Read TDRE bit in ICSR register Last byte ? Write transmit data to ICDRT register TEND = 1 ? Read TEND bit in ICSR register ICSR register TEND bit ← 0 ICSR register STOP bit ← 0 ICCR2 register SCP bit ← 0 BBSY bit ← 0 Read STOP bit in ICSR register STOP = 1 ? ICCR1 register TRS bit ← 0 MST bit ← 0 ICSR register TDRE bit ← 0 No Yes No Yes No Yes No Yes No Yes (1) (2) (3) (4) (5) (6) (7) (8) (12) (10) (13) (14) (11) (9) (15) - Set the STOP bit in the ICSR register to 0. - Set the IICSEL bit in the PMR register to 1.

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 341 of 458 REJ09B0250-0200 Figure 16.47 Example of Register Setting in Master Receive Mode (I 2C Bus Interface Mode) End RDRF = 1 ? Master receive mode No Yes (1) Set the TEND bit to 0 and set to master receive mode. Set the TDRE bit to 0(1,2) (2) Set the ACKBT bit to the transmit device(1) (3) Dummy-read to the ICDRR register(1) (4) Wait for 1 byte to be received (5) Judge (last receive - 1) (6) Read the receive data (7) Set the ACKBT bit of the last byte and set to disable the continuous receive (RCVD = 1)(2) (8) Read the receive data of (last byte - 1) (9) Wait the last byte is received (10) Set the STOP bit to 0 (11) Generate the stop condition (12) Wait the stop condition is generated (13) Read the receive data of the last byte (14) Set the RCVD bit to 0 (15) Set to slave receive mode ICCR1 register TRS bit ← 0 Dummy-read in ICDRR register Read RDRF bit in ICSR register Last receive - 1 ? ICSR register TEND bit ← 0 ICSR register STOP bit ← 0 ICCR2 register SCP bit ← 0 BBSY bit ← 0 Read STOP bit in ICSR register STOP = 1 ? ICSR register TDRE bit ← 0 No (1) (2) (3) (4) (5) (6) (7) (8) (12) (10) (13) (14) (11) (9) (15) ICIER register ACKBT bit ← 0 No Yes Read ICDRR register ICIER register ACKBT bit ← 1 ICCR1 register RCVD bit ← 1 Read ICDRR register Read RDRF bit in ICSR register RDRF = 1 ? Read ICDRR register ICCR1 register RCVD bit ← 0 ICCR1 register MST bit ← 0 No Yes Yes NOTES: 1. Do not generate the interrupt during the process of step (1) to (3). 2. When receiving 1 byte, skip step (2) to (6) after (1) and jump to process of step (7). Process of step (8) is dummy-read in the ICDRR register.

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 342 of 458 REJ09B0250-0200 Figure 16.48 Example of Register Setting in Slave Transmit Mode (I 2C Bus Interface Mode) End Write transmit data to ICDRT register Slave transmit mode No Yes (1) Set the AAS bit to 0 (2) Set the transmit data (except the last byte) (3) Wait the ICDRT register is empty (4) Set the transmit data of the last byte (5) Wait the last byte is transmitted (6) Set the TEND bit to 0 (7) Set to slave receive mode (8) Dummy-read in the ICDRR register to release the SCL signal (9) Set the TDRE bit to 0 TDRE = 1 ? Read TDRE bit in ICSR register Last byte ? Write transmit data to ICDRT register TEND = 1 ? Read TEND bit in ICSR register ICSR register TEND bit ← 0 ICSR register AAS bit ← 0 ICCR1 register TRS bit ← 0 ICSR Register TDRE Bit ← 0 No Yes No Yes (1) (2) (3) (4) (5) (6) (7) (8) (9) Dummy-read in ICDRR register

R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface Rev.2.00 Aug 27, 2008 Page 343 of 458 REJ09B0250-0200 Figure 16.49 Example of Register Se tting in Slave Receive Mode (I2C Bus Interface Mode) End RDRF = 1 ? Slave receive mode No Yes (1) Set the AAS bit to 0(1) (2) Set the ACKBT bit to the transmit device (3) Dummy-read to the ICDRR register (4) Wait 1 byte is received (5) Judge (last receive - 1) (6) Read the receive data (7) Set the ACKBT bit of the last byte (1) (8) Read the receive data of (last byte - 1) (9) Wait the last byte is received (10) Read the receive data of the last byte Dummy-read in ICDRR register Read RDRF bit in ICSR register Last receive - 1 ? (1) (2) (3) (4) (5) (6) (7) (8) (10) (9) ICIER register ACKBT bit ← 0 No Yes Read ICDRR register ICIER register ACKBT bit ← 1 Read ICDRR register Read RDRF bit in ICSR register RDRF = 1 ? Read ICDRR register No Yes NOTE: 1. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to process of step (7). Process of step (8) is dummy-read in the ICDRR register. ICSR register AAS bit ← 0

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16.3.8 Notes on I 2C Bus Interface

Set the IICSEL bit in the PMR register to 1 (select I2C bus interface function) to use I2C bus interface.

16.3.8.1 Multimaster Operation

The following actions must be performed to use the I2C bus interface in multimaster operation.

• Transfer rate Set the transfer rate by 1/1.8 or faster than the fastes t rate of the other masters. For example, if the fastest transfer rate of the other masters is set to 400 kbps, the I 2C-bus transfer rate in this MCU should be set to 223 kbps (= 400/1.18) or more.
• Bits MST and TRS in the ICCR1 register setting (a) Use the MOV instruction to set bits MST and TRS. (b) When arbitration is lost, confirm the contents of b its MST and TRS. If the contents are other than the MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0 again.

16.3.8.2 Master Receive Mode

Either of the following actions must be performed to use the I2C bus interface in master receive mode. (a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register before the rising edge of the 8th clock. (b) In master receive mode, set the RCVD bit in th e ICCR1 register to 1 (disables the next receive operation) to perform 1-byte communications.

R8C/20 Group, R8C/21 Group 17. Hardware LIN Rev.2.00 Aug 27, 2008 Page 345 of 458 REJ09B0250-0200 17. Hardware LIN The hardware LIN performs LIN communication in cooperation with timer RA and UART0.

17.1 Features

The hardware LIN has the following features. Figure 17.1 shows a Block Diagram of Hardware LIN. [Master mode]

• Generates Synch Break
• Detects bus collision [Slave mode]
• Detects Synch Break
• Measures Synch Field
• Controls Synch Break and Synch Field signal inputs to UART0
• Detects bus collision NOTE: 1. The WakeUp function is detected by INT1. Figure 17.1 Block Diagram of Hardware LIN Timer RA UART0 Interrupt control circuitBus collision detection circuit Synch Field control circuit RXD0 pin TXD0 pin LSTART bit SBE bit LINE bit Timer RA interrupt TIOSEL = 0 Hardware LIN TIOSEL = 1 RXD data Timer RA underflow signal BCIE, SBIE, and SFIE bits UART0 transfer clock UART0 TE bit Timer RA output pulse UART0 TXD data MST bit [Legend] LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: LINCR register bits TIOSEL: TRAIOC register bit TE: U0C1 register bit RXD0 input control circuit

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17.2 Input/Output Pins

Table 17.1 lists the Pin Configuration of the hardware LIN. Table 17.1 Pin Configuration Name Abbreviation Input/Output Function Receive Data Input RXD0 Input Receive data input pin of the hardware LIN Transmit Data Output TXD0 Output Transmit data output pin of the hardware LIN

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17.3 Register Configuration

The hardware LIN contains the following registers.

• LIN Control Register (LINCR)
• LIN Status Register (LINST) Figure 17.2 and Figure 17.3 show the LINCR and LINST Registers. Figure 17.2 LINCR Register LIN Control Register Symbol Address After Reset LINCR 0106h 00h Bit Symbol Bit Name Function RW NOTES: 3. Input to timer RA and UART0 are prohibited immediately after the LINE bit is set to 1(Causes LIN to start operating). Ref er to Figure 17.5 Example of Header Field Transmission Flow chart (1) and Figure 17.9 E xample of H eader F ield R ece ption Flow chart (2). After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts. SBIE BCIE RXDSF LSTART 0 : Unmasked after Synch Break is detected 1 : Unmasked after Synch Field measurement is completed Synch Break detection interrupt enable bit 0 : Disables bus collision detection interrupt 1 : Enables bus collision detection interrupt 0 : RXD0 input enabled 1 : RXD0 input disabled When this bit is set to 1, Timer RA input is enabled and RXD0 input is disabled. When read, its content is 0. RxD0 input status flag Synch Break detection start bit(1) SFIE 0 : Disables Synch Break detection interrupt 1 : Enables Synch Break detection interrupt 0 : Disables Synch Field measurement- completed interrupt 1 : Enables Synch Field measurement- completed interrupt RW RW RW WO RO RW RxD0 input unmasking timing select bit (effective in only slave mode) b3 b2 b1 b0 SBE Bus collision detection interrupt enable bit b7 b6 b5 b4 Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0). Synch Field measurement- completed interrupt enable bit MST RW LINE LIN operation start bit 0 : Causes LIN to stop 1 : Causes LIN to start operating(3) RW LIN operation mode setting bit(2) 0 : Slave mode (Synch Break detection circuit actuated) 1 : Master mode (timer RA output OR’ed w ith TxD0)

R8C/20 Group, R8C/21 Group 17. Hardware LIN Rev.2.00 Aug 27, 2008 Page 348 of 458 REJ09B0250-0200 Figure 17.3 LINST Register LIN Status Register Symbol Address After Reset LINST 0107h 00h Bit Symbol Bit Name Function RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. B2CLR SBDCT BCDCT B0CLR B1CLR When this bit is set to 1, BCDCT bit is set to0. When read, its content is 0. Synch Break detection flag Bus collision detection flag SFDCT flag clear bit RO SBDCT flag clear bit BCDCT flag clear bit 1 show s Synch Break detected or Synch Break generation completed 1 show s Bus collision detected When this bit is set to 1, SFDCT bit is set to 0. When read, its content is 0. When this bit is set to 1, SBDCT bit is set to 0. When read, its content is 0. b7 b6 b5 b4 b3 b2 b1 b0 (b7-b6) — 1 show s Synch Field measurement completed.SFDCT Synch Field measurement- completed flag RO WO WO WO RO

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17.4 Functional Description

17.4.1 Master Mode

Figure 17.4 shows a Typical Operation when Sending a Header Field. Figure 17.5 and Figure 17.6 show an Example of Header Field Transmission Flowchart. When transmitting a header field, the hardware LIN operates as described below. (1) When the TSTART bit in the TRACR register fo r timer RA is set by writing 1 in a program, the hardware LIN outputs a low-level signal from the TXD0 pin for the period that is set in the TRAPRE and TRA registers for timer RA. (2) When timer RA underflo ws upon reaching the terminal count, th e hardware LIN reverses the output of the TXD0 pin and sets the SBDCT flag in the LINST re gister to 1. Furthermore, if the SBIE bit in the LINCR register is set to 1, it generates a timer RA interrupt. (3) The hardware LIN transmits 55h via UART0. (4) The hardware LIN transmits an ID field via UART0 after it finished sending 55h. (5) The hardware LIN performs communication for a re sponse field after it finished sending the ID field. Figure 17.4 Typical Operation when Sending a Header Field TXD0 pin Synch Break SBDCT flag in the LINST register IR bit in the TRAIC register Synch Field IDENTIFIER Set by writing 1 to the B1CLR bit in the LINST register Cleared to 0 upon acceptance of interrupt request or by a program

• When LINE bit = 1 (Causes LIN to start operating), MST bit = 1 (Master mode), SBIE bit = 1 (Enables Synch Break detection interrupt)

R8C/20 Group, R8C/21 Group 17. Hardware LIN Rev.2.00 Aug 27, 2008 Page 350 of 458 REJ09B0250-0200 Figure 17.5 Example of Header Fi eld Transmission Flowchart (1) Timer RA Set to timer mode TMOD0 to 2 bits in TRAMR register ← 000b Timer RA Set the pulse output level from low to start TEDGSEL bit in TRAIOC register ← 1 Timer RA Set the INT1/TRAIO pin to P1_5 TIOSEL bit in TRAIOC register ← 1 Timer RA Set the count source (f1, f2, f8, fOCO) TCK0 to 2 bits in TRAMR register Timer RA Set the Synch Break width TRAPRE register TRA register Hardware LIN Set to master mode MST bit in LINCR register ← 1 Hardware LIN Set the LIN operation to start LINE bit in LINCR register ← 1 Hardware LIN Set the register to enable interrupts (Bus collision detection, Synch Break detection, Synch Field measurement) BCIE, SBIE, SFIE bits in LINCR register Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) B2CLR, B1CLR, B0CLR bits in LINST register ← 1 Set the count source and the TRA and TRAPRE registers as suitable for the Synch Break period. During master mode, the Synch Field measurement- completed interrupt cannot be used. A Set the TIOSEL bit in the TRAIOC register to 1 in the hardware LIN function. UART0 Set to transmit/receive mode (Transfer data length: 8 bits, Internal clock, 1 stop bit, Parity disabled) U0MR register UART0 UART0 Set the BRG count source (f1, f8, f32) U0C0CLK0 to 1 bit UART0 UART0 Set the bit rate U0BRG register Hardware LIN Set the LIN operation to stop LINE bit in LINCR register ← 0 Set the BRG count source and U0BRG register as appropriate for the bit rate.

R8C/20 Group, R8C/21 Group 17. Hardware LIN Rev.2.00 Aug 27, 2008 Page 351 of 458 REJ09B0250-0200 Figure 17.6 Example of Header Fi eld Transmission Flowchart (2) Timer RA Set the timer to start counting TSTART bit in TRACR register ← 1 Timer RA Read the count status flag TCSTF flag in TRACR register Hardware LIN Read the Synch Break detection flag SBDCT flag in LINST register Timer RA Set the timer to stop counting START bit in TRACR register ← 0 Timer RA Read the count status flag TCSTF flag in TRACR register UART0 Communication via UART0 TE bit in U0C1 register 1 U0TB register 0055h The timer RA interrupt may be used to terminate generation of Synch Break. Transmit the ID field. A TCSTF = 1? SBDCT = 1? YES TCSTF = 0? YES UART0 Communication via UART0 U0TB register ID field NO YES NO NO If the TRAPRE and TRA registers for timer RA do not need to be read or the register settings do not need to be changed after writing 0 to the TSTART bit, the procedure for reading TCSTF flag = 0 can be omitted. Zero to one cycle of the timer RA count source is required after timer RA stops counting before the TCSTF flag is set to 0. Transmit the Synch Field. After timer RA Synch Break is generated, the timer should be made to stop counting. If the TRAPRE and TRA registers for timer RA do not need to be read or the register settings do not need to be changed after writing 1 to the TSTART bit, the procedure for reading TCSTF flag = 1 can be omitted. Timer RA generates Synch Break. Zero to one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1. One to two cycles of the CPU clock are required after Synch Break generation completes before the SBDCT flag is set to 1.

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17.4.2 Slave Mode

Figure 17.7 shows a Typical Operation when Receiving a Header Field. Figure 17.8 through Figure 17.10 show an Example of Header Field Reception Flowchart. When receiving a header field, the hardware LIN operates as described below. (1) Synch Break detection is enabled by writing 1 to th e LSTART bit in the LINCR register of the hardware LIN. (2) When a low-level signal is input for a duration equa l to or greater than the period set in timer RA, the hardware LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1. Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA interrupt. Then it goes to Synch Field measurement. (3) The hardware LIN receives a Synch Fi eld (55h). At this time, it measures the period of the start bit and bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal to RxD0 of UART0 by setting the SBE bit in the LINCR register accordingly. (4) The hardware LIN sets the SFDCT flag in the LINS T register to 1 when it finished measuring the Synch Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt. (5) After it finished measuring the Synch Field, the ha rdware LIN calculates a tran sfer rate from the count value of timer RA and sets the result in UART0 a nd sets the TRAPRE and TRA registers of the timer RA back again. Then it receives an ID field via UART0. (6) The hardware LIN performs communication for a resp onse field after it finished receiving the ID field. Figure 17.7 Typical Operation when Receiving a Header Field RXD0 pin Synch Break RXD0 input for UART0 RXDSF flag in the LINCR register Synch Field IDENTIFIER SBDCT flag in the LINST register SFDCT flag in the LINST register IR bit in the TRAIC register Set by writing 1 to the B0CLR bit in the LINST register Cleared to 0 when Synch Field measurement finishes Measure this period Set by writing 1 to the B1CLR bit in the LINST register Cleared to 0 upon acceptance of interrupt request or by a program Set by writing 1 to the LSTART bit in the LINCR register

• When LINE bit = 1 (Causes LIN to start operating), MST bit = 0 (Slave mode), SBIE bit = 1 (Enables Synch Break detection interrupt), SFIE bit = 1 (Enables Synch Field measurement completed interrupt)

R8C/20 Group, R8C/21 Group 17. Hardware LIN Rev.2.00 Aug 27, 2008 Page 353 of 458 REJ09B0250-0200 Figure 17.8 Example of Header Field Reception Flowchart (1) Timer RA Set to pulse width measurement mode Bits TMOD0 to TMOD2 in the TRAMR register ← 011b Timer RA Set the pulse width measurement level low TEDGSEL bit in the TRAIOC register ← 0 Timer RA Set the INT1/TRAIO pin to P1_5 TIOSEL bit in the TRAIOC register ← 1 Timer RA Set the count source (f1, f2, f8, fOCO) TCK0 to 2 bits in the TRAMR register Timer RA Set the Synch Break width TRAPRE register TRA register Hardware LIN Set to slave mode MST bit in the LINCR register ← 0 Hardware LIN Set the LIN operation to start LINE bit in the LINCR register ← 1 Hardware LIN Set the RXD0 input unmasking timing (After Synch Break detection, or after Synch Field measurement) SBE bit in the LINCR register Hardware LIN Set the register to enable interrupts (Bus collision detection, Synch Break detection, Synch Field measurement) Bits BCIE, SBIE, SFIE in the LINCR register Set the count source and the TRA and TRAPRE registers as suitable for the Synch Break period. Select the timing at which to unmask the RXD0 input for UART0. If the RXD0 input is chosen to be unmasked after detection of Synch Break, the Synch Field signal too is input to UART0. A Hardware LIN Set the LIN operation to stop LINE bit in the LINCR register ← 0

R8C/20 Group, R8C/21 Group 17. Hardware LIN Rev.2.00 Aug 27, 2008 Page 354 of 458 REJ09B0250-0200 Figure 17.9 Example of Header Field Reception Flowchart (2) Timer RA Set to start a pulse width measurement TSTART bit in the TRACR register ← 1 Timer RA Read the count status flag TCSTF flag in the TRACR register Hardware LIN Set to start Synch Break detection LSTART bit in the LINCR register ← 1 Hardware LIN Read the RXD0 input status flag RXDSF flag in the LINCR register A TCSTF = 1? YES RXDSF = 1? YES NO NO Timer RA waits until the timer starts counting. Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1 Hardware LIN Read the Synch Break detection flag SBDCT flag in the LINST register SBDCT = 1? YES NO B Hard ware LIN detect a Synch Break. The interrupt of timer RA may be used. When Synch Break is detected, timer RA is reloaded with the initially set count value. Even if the duration of the input “L” level is shorter than the set period, timer RA is reloaded with the initially set count value and waits until the next “L” level is input. One to two cycles of the CPU clock are required after Synch Break detection before the SBDCT flag is set to 1. When the SBE bit in the LINCR register is set to 0 (Unmasked after Synch Break is detected), timer RA may be used in timer mode after the SBDCT flag in the LINST register is set to 1 and the RXDSF flag in the LINCR register is set to 0. Hard ware LIN wait until the RXD0 input for UART0 is masked. Do not apply “L” level to the RXD pin until the RXDSF flag reads 1 after writing 1 to the LSTART bit. This is because the signal applied during this time is input directly to UART0. One to two cycles of the CPU clock and zero to one cycle of the timer RA count source are required after the LSTART bit is set to 1 before the RXDSF flag is set to 1. After this, input to timer RA and UART0 is enabled. Zero to one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1.

R8C/20 Group, R8C/21 Group 17. Hardware LIN Rev.2.00 Aug 27, 2008 Page 355 of 458 REJ09B0250-0200 Figure 17.10 Example of Header Field Reception Flowchart (3) Hardware LIN Read the Synch Field measurement- completed flag SFDCT flag in the LINST register UART0 Set the UART0 communication rate U0BRG register Communication via UART0 (The SBDCT flag is set when timer RA counter underflows upon reaching the terminal count.) B SFDCT = 1? YES UART0 Communication via UART0 Clock asynchronous serial interface (UART) mode Receive ID field NO Hardware LIN measure the Synch Field. The interrupt of timer RA may be used. (The SBDCT flag is set when the timer RA counter underflows upon reaching the terminal count.) When the SBE bit in the LINCR register is set to 1 (Unmasked after Synch Field measurement is completed), timer RA may be used in timer mode after the SFDCT bit in the LINST register is set to 1. Set a communication rate based on the Synch Field measurement result. YES Timer RA Set the Synch Break width back again TRAPRE register TRA register

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17.4.3 Bus Collision Detection Function

The bus collision detection function can be used when UART0 is enabled for transmission (TE bit in the U0C1 register = 1). Figure 17.11 shows a Typical Operation when a Bus Collision is Detected. Figure 17.11 Typical Operation when a Bus Collision is Detected TXD0 pin 1 RXD0 pin 1 Transfer clock 1 LINE bit in the LINCR register TE bit in the U0C1 register BCDCT flag in the LINST register IR bit in the TRAIC register Cleared to 0 upon acceptance of interrupt request or by a program Set by writing 1 to the B2CLR bit in the LINST register Set to 1 by a program Set to 1 by a program

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17.4.4 Hardware LI N End Processing

Figure 17.12 shows an Example of Hardware LIN Communication Completion Flowchart. Use the following timing for hardware LIN end processing:

• If the hardware bus collision detection function is used Perform hardware LIN end processing after checksum transmission completes.
• If the bus collision detection function is not used Perform hardware LIN end processing after header field transmission and reception complete. Figure 17.12 Example of Hardware LIN Communication Completion Flowchart Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1 Timer RA Read the count status flag TCSTF flag in TRACR register UART0 Complete transmission via UART0 When the bus collision detection function is not used, end processing for the UART0 transmission is not required. TCSTF = 0 ? YES NO Set the timer to stop counting. Zero to one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1. After clearing hardware LIN status flag, stop the hardware LIN operation. Timer RA Set the timer to stop counting TSTART bit in TRACR register ← 0 Hardware LIN Set the LIN operation to stop LINE bit in the LINCR register ← 0

R8C/20 Group, R8C/21 Group 17. Hardware LIN Rev.2.00 Aug 27, 2008 Page 358 of 458 REJ09B0250-0200

17.5 Interrupt Requests

There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break generation completed, Synch Field measurement, and bus co llision detection. These interrupts are shared with the timer RA interrupt. Table 17.2 lists the Interrupt Requests of Hardware LIN. Table 17.2 Interrupt Requests of Hardware LIN Interrupt Request Status Flag Cause of Interrupt Synch Break Detection SBDCT Generated when timer RA has underflowed after measuring the low level duration of RXD0 input, or when a low-level signal is input for a duration longer than the Synch Break period during communication. Synch Break Generation Completed Generated when timer RA has completed outputting a low- level signal to TXD0 for set period. Synch Field Measurement SFDCT Generated when me asurement for 8 bits of the Synch Field by timer RA is completed. Bus Collision Detection BCDCT Generated when the RXD0 input and TXD0 output values differed at data latch timing while UART0 is enabled for transmission.

R8C/20 Group, R8C/21 Group 17. Hardware LIN Rev.2.00 Aug 27, 2008 Page 359 of 458 REJ09B0250-0200

17.6 Notes on Hardware LIN

For the time-out processing of the header and response fi elds, use another timer to measure the duration of time with respect to a Synch Break detection interrupt as the starting point.

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 360 of 458 REJ09B0250-0200 18. A/D Converter The A/D converter consists of one 10- bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog input shares the pins with P0_0 to P0_7, P1_0 to P1_3. Therefore, when using these pins, ensure the corresponding port direction bits are set to 0 (input mode). When not using the A/D converter, set the VCUT bit in th e ADCON1 register to 0 (Vre f unconnected), so that no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip. The result of A/D conversion is stored in the AD register. Table 18.1 lists the Performance of A/D Converter. Figur e 18.1 shows the Block Diagram of A/D Converter. Figure 18.2 and Figure 18.3 show the A/D converter-related registers. NOTES: 1. Analog input voltage does not depend on use of sample and hold function. When analog input voltage exceeds reference voltage, A/D conversion result is 3FFh in 10-bit mode, FFh in 8-bit mode. 2. The frequency of φAD must be 10 MHz or below. Without sample and hold function, the φAD frequency should be 250 kHz or above. With the sample and hold function, the φAD frequency should be 1 MHz or above. 3. In repeat mode, only 8-bit mode can be used. Table 18.1 Performance of A/D Converter Item Performance A/D Conversion Method Successive approximat ion (with capacitive coupling amplifier) Analog Input Voltage (1) 0 V to AVCC Operating Clock φAD(2) 4.2 V ≤ AVCC ≤ 5.5 V f1, f2, f4, fOCO-F 2.7 V ≤ AVCC < 4.2 V f2, f4, fOCO-F Resolution 8 bit or 10 bit is selectable Absolute Accuracy AVCC = Vref = 5 V, φAD = 10MHz

• 8-bit resolution ±2 LSB
• 10-bit resolution ±3 LSB AVCC = Vref = 3.3 V, φAD = 10MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB Operating Mode One-shot and repeat modes (3) Analog Input Pin 12 pins (AN0 to AN11) A/D Conversion Start Condition • Software trigger Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts)
• C a p t u r e Timer RD interrupt request is generated while the ADST bit is set to 1 Conversion Rate Per Pin • Without sample and hold function 8-bit resolution: 49φAD cycles, 10-bit resolution: 59φAD cycles
• With sample and hold function 8-bit resolution: 28φAD cycles, 10-bit resolution: 33φAD cycles

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 361 of 458 REJ09B0250-0200 Figure 18.1 Block Diagram of A/D Converter Comparator AVSS Data bus øAD Resistor ladder VCUT = 0 VCUT = 1 VREF Successive conversion register AD register ADCON0 Vcom VIN P1_0/AN8 CH2 to CH0 = 100b P1_1/AN9 CH2 to CH0 = 101b P1_2/AN10 CH2 to CH0 = 110b P1_3/AN11 CH2 to CH0 = 111b ADGSEL0 = 1 CH0 to CH2, ADGSEL, CKS0: Bits in ADCON0 register CKS1, VCUT: Bits in ADCON1 register A/D conversion rate selection ADGSEL0 = 0 ADCAP = 1 Software trigger Timer RD interrupt request ADCAP = 0 Trigger P0_7/AN0 CH2 to CH0 = 000b P0_6/AN1 CH2 to CH0 = 001b P0_5/AN2 CH2 to CH0 = 010b P0_4/AN3 CH2 to CH0 = 011b P0_3/AN4 CH2 to CH0 = 100b P0_2/AN5 CH2 to CH0 = 101b P0_1/AN6 CH2 to CH0 = 110b P0_0/AN7 CH2 to CH0 = 111b Decoder CKS0 = 1 CKS1 = 1 CKS1 = 0 CKS0 = 0 CKS0 = 0 fOCO-F CKS0 = 1

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 362 of 458 REJ09B0250-0200 Figure 18.2 ADCON0 Register A/D Control Register 0(1) Symbol Address After Reset ADCON0 00D6h 00h Bit Symbol Bit Name Function RW NOTES: ADGSEL0 = 0 ADGSEL0 = 1 AN 0 AN 1 AN 2 AN 3 AN 4 AN 8 AN 5 AN 9 AN 6 AN 10 AN 7 AN 11 100b 101b 110b 111b CH2 to CH0 000b Do not set 001b 010b 011b Set øAD frequency to 10 MHz or below . The analog input pin can be select according to a combination of the CH0 to CH2 bits and the ADGSEL0 bit. CKS0 Frequency select bit 0 [When CKS1 in ADCON1 register = 0] 0 : Select f4 1 : Select f2 [When CKS1 in ADCON1 register = 1] 0 : Select f1 (3) 1 : Select fOCO-F RW If the ADCON0 register is rew ritten during A/D conversion, the conversion result is indeterminate. When changing A/D operation mode, set the analog input pin again. AD ST A/D conversion start flag 0 : Disables A/D conversion 1 : Starts A/D conversion RW A DCA P A/D conversion automatic start bit 0 : Starts in softw are trigger (ADST bit) 1 : Starts in timer RD (complementary PWM mode) RW 0 : On-shot mode 1 : Repeat mode RW RW AD GSE L0 RWA/D input group select bit(4) 0 : Selects port P0 group (AN0 to AN7) 1 : Selects port P1 group (AN8 to AN11) CH1 RW CH0 CH2 RW Analog input pin select bit Refer to (4) MD A/D operation mode select bit(2) b7 b6 b5 b4 b3 b2 b1 b0

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 363 of 458 REJ09B0250-0200 Figure 18.3 Registers ADCON1, ADCON2, and AD A/D Control Register 1(1) Symbol Address After Reset A DCON1 00D7h 00h Bit Symbol Bit Name Function RW NOTES: 3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting A/D conversion. b3 b2 VC U T b1 b0 Refer to a description of the CKS0 bit in the ADCON0 register function b7 b6 b5 b4 (b2-b0) 00 0 If the ADCON1 register is rew ritten during A/D conversion, the conversion result is indeterminate. CKS1 RW RW RW— (b7-b6) Reserved Bit Vref connect bit (3) 0 : Vref not connected 1 : Vref connected Set the BITS bit to 0 (8-bit mode) in repeat mode. Reserved bit Set to 0 8/10-bit mode select bit(2) 0 : 8-bit mode 1 : 10-bit mode RW Set to 0 Frequency select bit 1 BITS RW A/D Control Register 2(1) Symbol Address After Reset ADCON2 00D4h 00h Bit Symbol Bit Name Function RW NOTE: 000 b3 b2 b1 Reserved bit Set to 0 b7 b6 b5 b4 0 : Without sample and hold 1 : With sample and hold RW If the ADCON2 register is rew ritten during A/D conversion, the conversion result is indeterminate. SMP A/D conversion method select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0. (b7-b4) — (b3-b1) RW A/D Register Symbol Address After Reset AD 00C1h-00C0h Indeterminate RWFunction RO When BITS bit in ADCON1 register is set to 1 (10-bit mode) When BITS bit in ADCON1 register is set to 0 (8-bit mode) 8 low -order bits in A/D conversion result A/D conversion result RW RO N othing is assigned. I f necessary, set to 0. When read, the content is 0. — 2 high-order bits in A/D conversion result When read, its content is indeterminate b0b7 (b8) (b15)

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 364 of 458 REJ09B0250-0200

18.1 One-Shot Mode

In one-shot mode, the input voltage on one selected pin is A/D converted once. Table 18.2 lists the One-Shot Mode Specifications. Figur e 18.4 shows the ADCON0 Register in One-Shot Mode and Figure 18.5 shows the ADCON1 Register in One-Shot Mode. Table 18.2 One-Shot Mode Specifications Item Specification Function The input voltage on one selected pin by bits CH2 to CH0 and ADGSEL0 is A/D converted once Start Condition • When the ADCAP bit is set to 0 (software trigger), Set the ADST bit to 1 (A/D conversion starts)

• When the ADCAP bit is set to 1 (starts in timer RD (complementary PWM mode)), The compare match in the TRD0 and TRDGRA0 registers or the TRD1 underflow is generated while the ADST bit is set to 1 Stop Condition • A/D conversion completes (When the ADCAP bit is set to 0 (software trigger), the ADST bit is set to 0)
• Set the ADST bit to 0 Interrupt Request Generation Timing A/D conversion completes Input Pin Select one of AN0 to AN11 Reading of A/D Conversion Result Read the AD register

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 365 of 458 REJ09B0250-0200 Figure 18.4 ADCON0 Register in One-Shot Mode A/D Control Register 0(1) Symbol Address After Reset ADCON0 00D6h 00h Bit Symbol Bit Name Function RW NOTES: ADGSEL0 = 0 ADGSEL0 = 1 AN 0 AN 1 AN 2 AN 3 AN 4 AN 8 AN 5 AN 9 AN 6 AN 10 AN 7 AN 11 100b 101b 110b 111b CH2 to CH0 000b Do not set 001b 010b 011b b3 b2 b1 MD A/D operation mode select bit(2) b7 b6 b5 b4 CH2 RW Analog input pin select bit Refer to (4) 0 : One-shot mode RW RW AD GSE L0 RWA/D input group select bit(4) 0 : Selects port P0 group (AN0 to AN7) 1 : Selects port P1 group (AN8 to AN11) CH1 RW CH0 A DCA P A/D conversion automatic start bit 0 : Starts in softw are trigger (ADST bit) 1 : Starts in timer RD (complementary PWM mode) RW AD ST A/D conversion start flag 0 : Disables A/D conversion 1 : Starts A/D conversion RW Set øAD frequency to 10 MHz or below . The analog input pin can be select according to a combination of the CH0 to CH2 bits and the ADGSEL0 bit. CKS0 Frequency select bit 0 [When CKS1 in ADCON1 register = 0] 0 : Select f4 1 : Select f2 [When CKS1 in ADCON1 register = 1] 0 : Select f1 (3) 1 : Select fOCO-F RW If the ADCON0 register is rew ritten during A/D conversion, the conversion result is indeterminate. When changing A/D operation mode, set the analog input pin again.

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 366 of 458 REJ09B0250-0200 Figure 18.5 ADCON1 Register in One-Shot Mode A/D Control Register 1(1) Symbol Address After Reset A DCON1 00D7h 00h Bit Symbol Bit Name Function RW NOTES: 2. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting A/D conversion. b3 b2 V CUT b1 b0 Refer to a description of the CKS0 bit in the ADCON0 register function b7 b6 b5 b4 (b2-b0) 001 0 BITS RW If the ADCON1 register is rew ritten during A/D conversion, the conversion result is indeterminate. CKS1 RW RW RW— (b7-b6) Reserved bit Vref connect bit (2) RW Set to 0 Frequency select bit 1 1 : Vref connected Reserved bit Set to 0 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 367 of 458 REJ09B0250-0200

18.2 Repeat Mode

In repeat mode, the input voltage on one selected pin is A/D converted repeatedly. Table 18.3 lists the Repeat Mode Specifications. Figure 18.6 shows the ADCON0 Register in Repeat Mode and Figure 18.7 shows the ADCON1 Register in Repeat Mode. Table 18.3 Repeat Mode Specifications Item Specification Function The Input voltage on one pin selected by CH2 to CH0 and ADGSEL0 bits is A/D converted repeatedly Start Condition • When the ADCAP bit is set to 0 (software trigger) Set the ADST bit to 1 (A/D conversion starts)

• When the ADCAP bit is set to 1 (starts in timer RD (complementary PWM mode)), The compare match in the TRD0 and TRDGRA0 registers or the TRD1 underflow is generated while the ADST bit is set to 1 Stop Condition Set the ADST bit to 0 Interrupt Request Generation Timing Not generated Input Pin Select one of AN0 to AN11 Reading of Result of A/D Converter Read the AD register

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 368 of 458 REJ09B0250-0200 Figure 18.6 ADCON0 Register in Repeat Mode A/D Control Register 0(1) Symbol Address After Reset ADCON0 00D6h 00h Bit Symbol Bit Name Function RW NOTES: ADGSEL0 = 0 ADGSEL0 = 1 AN 0 AN 1 AN 2 AN 3 AN 4 AN 8 AN 5 AN 9 AN 6 AN 10 AN 7 AN 11 100b 101b 110b 111b CH2 to CH0 000b Do not set 001b 010b 011b Set øAD frequency to 10 MHz or below . The analog input pin can be select according to a combination of the CH0 to CH2 bits and the ADGSEL0 bit. CKS0 Frequency select bit 0 [When CKS1 in ADCON1 register = 0] 0 : Select f4 1 : Select f2 [When CKS1 in ADCON1 register = 1] 0 : Select f1 (3) 1 : Do not set RW If the ADCON0 register is rew ritten during A/D conversion, the conversion result is indeterminate. When changing A/D operation mode, set the analog input pin again. AD ST A/D conversion start flag 0 : Disables A/D conversion 1 : Starts A/D conversion RW A DCA P A/D conversion automatic start bit 0 : Starts in softw are trigger (ADST bit) 1 : Starts in timer RD (complementary PWM mode) RW 1 : Repeat mode RW RW AD GSE L0 RWA/D input group select bit(4) 0 : Selects port P0 group (AN0 to AN7) 1 : Selects port P1 group (AN8 to AN11) CH1 RW CH0 CH2 RW Analog input pin select bit Refer to (4) MD A/D operating mode select bit(2) b7 b6 b5 b4 b3 b2 b1 b0

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 369 of 458 REJ09B0250-0200 Figure 18.7 ADCON1 Register in Repeat Mode A/D Control Register 1(1) Symbol Address After Reset A DCON1 00D7h 00h Bit Symbol Bit Name Function RW NOTES: 3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting A/D conversion. b3 b2 VC U T b1 b0 000 Refer to a description of the CKS0 bit in the ADCON0 register function b7 b6 b5 b4 (b2-b0) 001 0 BITS RW If the ADCON1 register is rew ritten during A/D conversion, the conversion result is indeterminate. CKS1 RW RW RW— (b7-b6) Reserved bit Set the BITS bit to 0 (8-bit mode) in repeat mode. Vref connect bit (3) 1 : Vref connected Reserved bit Set to 0 8/10-bit mode select bit(2) 0 : 8-bit mode RW Set to 0 Frequency select bit 1

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 370 of 458 REJ09B0250-0200

18.3 Sample and Hold

When the SMP bit in the ADCON2 register is set to 1 (with sample and hold function), A/D conversion rate per pin increases. The sample and hold func tion is available in all operating modes. Start the A/D conversion after selecting whether the sample and hold circuit is to be used or not. Figure 18.8 shows the Timing Diagram of A/D Conversion. Figure 18.8 Timing Diagram of A/D Conversion Sampling time 4ø AD cycle Sample & hold disabled Conversion time at the 1st bit at the 2nd bit Comparison time Sampling time 2.5ø AD cycle Comparison time Sampling time 2.5ø AD cycle Comparison time * Repeat until conversion ends Sampling time 4ø AD cycle Sample & hold enabled Conversion time at the 1st bit at the 2nd bit Comparison time Comparison time Comparison time * Repeat until conversion ends Comparison time

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 371 of 458 REJ09B0250-0200

18.4 A/D Conversion Cycles

Figure 18.9 shows the A/D Conversion Cycles. Figure 18.9 A/D Conversion Cycles A/D Conversion Mode Without Sample & Hold Without Sample & Hold With Sample & Hold With Sample & Hold 8 bits 10 bits 8 bits 10 bits Conversion Time Comparison Time Comparison Time End processSampling Time End processConversion time at the 1st bit Sampling Time Conversion time at the 2nd bit and the follows 49φAD 4 φAD 2.0 φAD 2.5 φAD 2.5 φAD 8.0 φAD 59φAD 4 φAD 2.0 φAD 2.5 φAD 2.5 φAD 8.0 φAD 28φAD 4 φAD 2.5 φAD 0.0 φAD 2.5 φAD 4.0 φAD 33φAD 4 φAD 2.5 φAD 0.0 φAD 2.5 φAD 4.0 φAD

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 372 of 458 REJ09B0250-0200

18.5 Internal Equivalent Circuit of Analog Input

Figure 18.10 shows the Internal Equivalent Circuit of Analog Input. Figure 18.10 Internal Equivalent Circuit of Analog Input VCC Parasitic Diode Chopper-type Amplifier A/D Successive Conversion Register Comparison voltage b1b2 b0 VCC VSS AN0 VSS i = 12 AN11 VREF AVSS Vref Comparison reference voltage (Vref) generator SW1 SW2 AVCC AMP SW3 AVSS VIN SW4 SW5 SW1 Parasitic Diode ON Resistor Approx. 2kΩ Wiring Resistor Approx. 0.2k Ω ON Resistor Approx. 0.6k Ω ON Resistor Approx. 2kΩ Wiring Resistor Approx. 0.2k Ω i Ladder-type Switches A/D Control Register 0 ON Resistor Approx. 0.6k f Analog Input Voltage Sampling Control Signal ON Resistor Approx. 5kΩ C = Approx.1.5pF A/D Conversion Interrupt Request SW1 conducts only on the ports selected for analog input. SW2 and SW3 are open when A/D conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left. SW4 conducts only when A/D conversion is not in progress. SW5 conducts when A/D conversion is Comparison. Control signal for SW2 Control signal for SW3 Sampling Comparison Connect to Connect to Connect to Connect to NOTE: 1. Use only as a standard for designing this data. Mass production may cause some changes in device characteristics. i Ladder-type Wiring Resistors Resistor ladder Reference Control Signal

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 373 of 458 REJ09B0250-0200

18.6 Output Impedance of Se nsor Under A/D Conversion

To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 18.11 has to be completed within a specified period of time. T (sampling time) as the specified time. Let ou tput impedance of sensor equivalent circuit be R0, internal resistance of microcom puter be R, precision (error) of the A/D converter be X, and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). Figure 18.11 shows Analog Input Pin and External Sensor Equivalent Circuit. When the difference between VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN (0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop du e to insufficient capacitor ch arge is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1LSB. When f(XIN) = 10 MHz, T = 0.25 µs in the A/D conversion mode without sample & hold. Output impedance R0 for sufficiently charging capacitor C within time T is determined as follows. Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less, is approximately 1.7 kΩ maximum. Figure 18.11 Analog Input Pin and Exte rnal Sensor Equivalent Circuit VC is generally VC = VIN 1 - e And when t = T, VC = VIN - VIN = VIN 1 - e = = 1n Hence, R0 = - -R - t1 C(R0 + R) X Y X Y X Y X Y - T1 C(R0 + R) - T1 C(R0 + R) T C 1 nX Y R0 = - 6.0 × 10-12 1n 0.1 1024 0.25 × 10-6 MCU Sensor equivalent circuit R(2.8kΩ) C(6.0pF) VIN VC NOTE: 1. The capacity of the terminal is assumed to be 4.5 pF

R8C/20 Group, R8C/21 Group 18. A/D Converter Rev.2.00 Aug 27, 2008 Page 374 of 458 REJ09B0250-0200

18.7 Notes on A/D Converter

• Write to each bit (other than bit 6) in the ADCON0 register, each b it in the ADCON1 register, or the SMP bit in the ADCON2 register when the A/D conversion stops (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from 0 (VREF no t connected) to 1 (VREF connected), wait for at least 1 µs or longer before the A/D conversion starts.
• When changing A/D operating mode, select an analog input pin again.
• When using in one-shot mode. Ensure that the A/D c onversion is completed and read the AD register. The IR bit in the ADIC register or the ADST bit in the AD CON0 register can determine whether the A/D conversion is completed.
• When using the repeat mode, select the frequency of the A/D converter operating clock φAD or more for the CPU clock during A/D conversion. Do not select the fOCO-F for the φAD.
• If setting the ADST bit in the ADCON0 register to 0 (A/D conversion stops) by a program and the A/D conversion is forcibly terminated during the A/D c onversion operation, the conversion result of the A/D converter will be indeterminate. If the ADST bit is set to 0 by a program, do not use the value of AD register.
• Connect 0.1 µF capacitor between the P4_2/VREF pin and A VSS pin.
• Do not enter stop mode during A/D conversion.
• Do not enter wait mode when the CM02 bit in the CM0 re gister is set to 1 (peripheral function clock stops in wait mode) during A/D conversion.

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 375 of 458 REJ09B0250-0200 19. Flash Memory

19.1 Overview

In the flash memory version, rewrite operations to the flash memory can be performed in three modes ; CPU rewrite, standard serial I/O, parallel I/O modes. Table 19.1 lists the Flash Memory Performance (see Table 1.1 and Table 1.2 Performance for the items not listed on Table 19.1). NOTES: 1. Definition of programming and erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1-Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. When performing 100 or more rewrites, the actual erasure endurance can be reduced by executing programming operations in such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular blocks and try to average out the programming and erasure endurance of the blocks. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 2. Blocks A and B are embedded only in the R8C/21 Group. Table 19.1 Flash Me mory Performance Item Specification Flash Memory Operating Mode 3 modes (CPU rewrite, standard serial I/O, and parallel I/O mode) Division of Erase Block See Figure 19.1 and Figure 19.2 Program Method Byte unit Erase Method Block erase Program, Erase Control Method Program and erase control by software command Rewrite Control Method Rewrite control for blocks 0 and 1 by FMR02 bit in FMR0 register Rewrite control for block 0 by FMR16 bit and block 1 by FMR16 bit Number of Commands 5 commands Programming and erase endurance (1) Blocks 0 and 1 (Program ROM) R8C/20 Group: 100 times; R8C/21 Group: 1,000 times Blocks A and B (Data Flash)(2) 10,000 times ID Code Check Function Standard serial I/O mode supported ROM Code Protect For para llel I/O mode supported

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 376 of 458 REJ09B0250-0200 Table 19.2 Flash Memory Rewrite Modes Flash Memory Rewrite Mode CPU Rewrite Mode Standard Seri al I/O Mode Parallel I/O Mode Function User ROM area is rewritten by executing software commands from the CPU. EW0 mode: Rewritable in the RAM EW1 mode: Rewritable in flash memory User ROM area is rewritten by using a dedicated serial programmer. User ROM area is rewritten by using a dedicated parallel programmer. Areas which can be rewritten User ROM area User ROM area User ROM area Operating mode Single chip mo de Boot mode Parallel I/O mode ROM programmer None Serial programmer Parallel programmer

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 377 of 458 REJ09B0250-0200

19.2 Memory Map

The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 19.1 shows the Flash Memory Block Diagram for R8C/20 Group. Figure 19.2 shows the Flash Memory Block Diagram for R8C/21 Group. The user ROM area of R8C/21 Group contains an area which stores a MC U operating program (program ROM) and the 1-Kbyte block A and B (data flash). The user ROM area is divided into several blocks. Th e user ROM area can be rewritten in CPU rewrite and standard serial I/O and parallel I/O modes. When rewriting the block 0 and block 1 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite enables), and when setting the FMR15 bit in the FMR1 regi ster to 0 (rewrite enables), block 0 is rewritable. When setting the FMR16 bit to 0 (rewrite enables), block 1 is rewritable. When rewriting the block 2 and block 3 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite enables). The rewrite control program for standard serial I/O mode is stored in boot ROM ar ea before shipment. The boot ROM area and the user ROM area share the same address, but have an another memory.

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 378 of 458 REJ09B0250-0200 Figure 19.1 Flash Memory Block Diagram for R8C/20 Group User ROM area Block 0: 32 Kbytes(1) 0C000h 13FFFh

64 Kbytes ROM product

Block 1: 32 Kbytes(1) User ROM area Block 0: 32 Kbytes(1) 0C000h 13FFFh

96 Kbytes ROM product

Block 1: 32 Kbytes(1) Block 2: 32 Kbytes(2) 14000h 1BFFFh User ROM area Block 0: 32 Kbytes(1) 0C000h 13FFFh

128 Kbytes ROM product

Block 1: 32 Kbytes(1) Block 2: 32 Kbytes(2) 14000h 1BFFFh Block 3: 32 Kbytes(2, 3) 1C000h 23FFFh User ROM area Block 0: 16 Kbytes(1) 0C000h

48 Kbytes ROM product

Block 1: 32 Kbytes(1) User ROM area Block 0: 16 Kbytes(1) 0C000h

32 Kbytes ROM product

Block 1: 16 Kbytes(1) Program ROM Boot ROM area (reserved area)(4)

8 Kbytes

NOTES: 1. When setting the FMR02 bit in the FMR0 register to 1 (enables to rewrite) and the FMR15 bit in the FMR1 register to 0 (enable to rewrite), Block 0 is rewritable. When setting the FMR16 bit to 0 (enables to rewrite), Block 1 is rewritable (only for CPU rewrite mode). 2. When setting the FMR02 bit in the FMR0 register to 1 (enables to rewrite), Block 2 and Block 3 are rewritable (only for CPU rewrite mode). 3. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger. 4. This area is to store the boot program provided by Renesas Technology.

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 379 of 458 REJ09B0250-0200 Figure 19.2 Flash Memory Block Diagram for R8C/21 Group User ROM area Block 0: 32 Kbytes(1) 0C000h 13FFFh Block 1: 32 Kbytes(1) User ROM area Block 0: 32 Kbytes(1) 0C000h 13FFFh Block 1: 32 Kbytes(1) Block 2: 32 Kbytes(2) 14000h 1BFFFh User ROM area Block 0: 32 Kbytes(1) 0C000h 13FFFh Block 1: 32 Kbytes(1) Block 2: 32 Kbytes(2) 14000h 1BFFFh Block 3: 32 Kbytes(2, 3) 1C000h 23FFFh User ROM area Block 0: 16 Kbytes(1) 0C000h Block 1: 32 Kbytes(1) User ROM area Block 0: 16 Kbytes(1) 0C000h Block 1: 16 Kbytes(1) Program ROM Boot ROM area (reserved area)(4) Block B: 1 Kbyte Block A: 1 Kbyte02400h 02BFFh Block B: 1 Kbyte Block A: 1 Kbyte02400h 02BFFh Block B: 1 Kbyte Block A: 1 Kbyte02400h 02BFFh Block B: 1 Kbyte Block A: 1 Kbyte02400h 02BFFh Block B: 1 Kbyte Block A: 1 Kbyte02400h 02BFFh NOTES: 1. When setting the FMR02 bit in the FMR0 register to 1 (enables to rewrite) and the FMR15 bit in the FMR1 register to 0 (enables to rewrite), Block 0 is rewritable. When setting the FMR16 bit to 0 (enables to rewrite), Block 1 is rewritable (only for CPU rewrite mode). 2. When setting the FMR02 bit in the FMR0 register to 1 (enables to rewrite), Block 2 and Block 3 are rewritable (only for CPU rewrite mode). 3. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger. 4. This area is to store the boot program provided by Renesas Technology.

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19.3 Functions to Prevent Re writing of Flash Memory

Standard serial I/O mode co ntains an ID code check function, and th e parallel I/O mode contains a ROM code protect function to prevent the flash memory from reading or rewriting easily.

19.3.1 ID Code Check Function

Use this function in standard serial I/O mode. Unless th e flash memory is blank, th e ID codes sent from the programmer and the ID codes written in the flash memory are determined wh ether they match. If the ID codes do not match, the commands sent from the programmer are not acknowledged. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 00FFDFh, 00FFE3h, 00FFEBh, 00FFEFh, 00FFF3h, 00FFF7h, and 00FFFBh. Write a program in which the ID codes are set at these addresses and write them in the flash memory. Figure 19.3 Address for Stored ID Code 4 bytes Address 00FFDFh to 00FFDCh Undefined instruction vector NOTE: 1. The OFS register is assigned to 00FFFFh. Refer to Figure 19.4 OFS Register for the OFS register details. Overflow vector00FFE3h to 00FFE0h 00FFE7h to 00FFE4h BRK instruction vector Address match vector00FFEBh to 00FFE8h 00FFEFh to 00FFECh Oscillation stop detection/watchdog timer/voltage monitor 2 vector00FFF3h to 00FFF0h 00FFF7h to 00FFF4h Address break 00FFFBh to 00FFF8h Reset vector00FFFFh to 00FFFCh (Reserved) ID1 ID2 ID3 ID4 ID5 ID6 ID7 (1) Single step vector

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19.3.2 ROM Code Protect Function

The ROM code protect function disables to read and ch ange the internal flash memory by the OFS register in parallel I/O mode. Figure 19.4 shows the OFS Register. The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit and disables to read and change the internal flash memory. Once the ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O mode. When the ROM code protect is disabled, erase the block including the OFS register with CPU rewrite mode or standard serial I/O mode. Figure 19.4 OFS Register Option Function Select Register(1) Symbol Address Before Shipment OFS 0FFFFh FFh (3) Bit Symbol Bit Name Function RW Reserved bit NOTES: b7 b6 b5 b4 b3 b2 b1 b0 11 1 (b1) Set to 1 RW WDTON Watchdog timer start select bit 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset RW ROMCR ROM code protect disabled bit 0 : ROM code protect disabled 1 : ROMCP1 enabled RW ROMCP1 ROM code protect bit 0 : ROM code protect enabled 1 : ROM code protect disabled RW RW (b5-b4) Reserved bits Set to 1 RW If the block including the OFS register is erased, FFh is set to the OFS register. To use the pow er-on reset, set the LVD1ON bit to 0 (voltage monitor 1 reset enabled after reset). LVD1ON Voltage detection circuit start bit(2) 0 : Voltage monitor 1 reset enabled after reset 1 : Voltage monitor 1 reset disabled after reset RW The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not w rite additions to the OFS register. CSPROINI Count source protect m ode after reset select bit 0 : Count source protect mode enabled after reset 1 : Count source protect mode disabled after reset

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19.4 CPU Rewrite Mode

In CPU rewrite mode, user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten di rectly while the MCU is mounted on a board without using such as a ROM programmer. Execute the program and block erase commands only to each block in user ROM area. When an interrupt request is generated during an erase operation in CPU rewrite mode , the flash module contains an erase-suspend function which performs the interrupt pr ocess after the erase operati on is halted temporarily. During the erase-suspend, user ROM area can be read by a program. When an interrupt request is generated during the auto-program operation in CPU rewrite mode, the flash module contains a program-suspend function which performs th e interrupt process after th e auto-program operation suspends. During the program-suspend, user ROM area can be read by a program. CPU rewrite mode contains erase write 0 mode (EW0 mode) and erase write 1 mode (EW1 mode). Table 19.3 lists the Differences between EW0 Mode and EW1 Mode. NOTE: 1. When setting the FMR02 bit in the FMR0 register to 1 (rewrite enables) and rewriting block 0 is enabled by setting the FMR15 bit in the FMR1 register to 0 (rewrite enables). Rewriting block 1 is enabled by setting the FMR16 bit to 0 (rewrite enables). Table 19.3 Differences between EW0 Mode and EW1 Mode Item EW0 Mode EW1 Mode Operating Mode Single chip mode Single chip mode Areas in which a Rewrite Control Program Can be Located User ROM area User ROM area Areas in which a Rewrite Control Program can be Executed Necessary to transfer to any areas other than the flash memory (e.g., RAM) before executing Executing directly in user ROM or RAM area possible Areas which can be Rewritten User ROM area User ROM area However, other than the blocks which contain a rewrite control program (1) Software Command Restriction None • Program and block erase commands Cannot be run on any block which contains a rewrite control program

• Read status register command Cannot be executed Modes After Program or Erase Read status register mode Read array mode Modes After Read Status Register Read status register mode Do not execute this command CPU Status During Auto- write and Auto-erase Operating Hold state (I/O ports hold state before the command is executed) Flash Memory Status Detection
• Read the FMR00, FMR06, and FMR07 bits in the FMR0 register by a program
• Execute the read status register command and read the SR7, SR5, and SR4 bits in the status register. Read the FMR00, FMR06, and FMR07 bits in the FMR0 register by a program Conditions for Transition to Erase-suspend Set the FMR40 and FMR41 bits in the FMR4 register to 1 by a program. The FMR40 bit in the FMR4 register is set to 1 and the interrupt request of the enabled maskable interrupt is generated Conditions for Transitions to Program-suspend Set the FMR40 and FMR42 bits in the FMR4 register to 1 by a program. The FMR40 bit in the FMR4 register is set to 1 and the interrupt request of the enabled maskable interrupt is generated CPU Clock 5 MHz or below No restriction to the following (clock frequency to be used)

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19.4.1 EW0 Mode

The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since th e FMR11 bit in the FMR1 register is set to 0, EW0 mode is selected. Use software commands to control a program and erase operations. The FMR0 register or the status register can determine status when program and erase operation complete. When entering an erase-suspend, se t the FMR40 bit to 1 (enables suspen d) and the FMR41 bit to 1 (requests erase-suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (enables reading) before accessing the user ROM area. The auto-erase operation restarts by setting the FMR41 bit to 0 (erase restarts). When entering a program-suspend durin g the auto-program, set the FMR40 bit to 1 (enables suspend) and the FMR42 bit to 1 (requests program-suspend). Wait for td(S R-SUS) and ensure that the FMR46 bit is set to 1 (enables reading) before accessing the user ROM area. The auto-program operatio n restarts by setting the FMR42 bit to 0 (program restarts).

19.4.2 EW1 Mode

The MCU enters EW1 mode by setting the FMR11 bit to 1 (EW1 mode) after setting the FMR01 bit to 1 (CPU rewrite mode enabled). The FMR0 register can determine status when pr ogram and erase operation complete. Do not execute commands of the read status register in EW1 mode. To enable the erase-suspend function during the auto-erase, execute the block erase command after setting the FMR40 bit to 1 (enables suspend). The interrupt to enter an erase-suspend should be in interrupt enabled status. After passing td(SR-SUS) since the block erase command is executed, an interrupt request is acknowledged. When an interrupt request is generated, the FMR41 bit is automatically set to 1 (requests erase-suspend) and the auto-erase operation is halted. If the auto-erase operation does not complete (FMR00 bit is 0) when the interrupt process completes, the auto-erase operation restarts by setting the FMR41 bit to 0 (erase restarts) To enable the program-suspend function during the au to-program, execute the pr ogram command after setting the FMR40 bit to 1 (enables suspend). The interrupt to enter a program-suspend should be in interrupt enabled status. After waiting for td(SR-SUS) since the prog ram command is executed, an interrupt request is acknowledged. When an interrupt request is generated, the FMR42 bit is automatically set to 1 (requests program-suspend) and the auto-program oper ation suspends. When the auto-program operation does not complete (FMR00 bit is 0) after the interrupt process completes, the auto-pr ogram operation restarts by setting the FMR42 bit to 0 (program restarts).

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 384 of 458 REJ09B0250-0200 Figure 19.5 shows the FMR0 Register, Figure 19.6 shows the FMR1 Register and Figure 19.7 shows the FMR4 Register.

19.4.2.1 FMR00 Bit

This bit indicates the operating status of the flash memory. The bit is 0 during programming, erasing (including suspend periods), or erase-suspend mode; otherwise, the bit is 1.

19.4.2.2 FMR01 Bit

The MCU is made ready to accept commands by setting the FMR01 bit to 1 (CPU rewrite mode).

19.4.2.3 FMR02 Bit

The block0, block1, block2 and block3 do not accept the program and block erase commands if the FMR02 bit is set to 0 (rewrite disabled). The block0 and block1 are controlled rewriting in the FMR15 and FMR16 bits if the FMR02 bit is set to 1 (rewrite enabled).

19.4.2.4 FMSTP Bit

This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of current consumed in the flash memory. The flash memory is disabled against access by setting the FMSTP bit to 1. Therefore, the FMSTP bit must be written to by a program transferred to the RAM. In the following cases, set the FMSTP bit to 1:

• When flash memory access resulted in an error whil e erasing or programming in EW0 mode (FMR00 bit not reset to 1 (ready))
• When entering high-speed on-chip oscillator mode, low-speed on-chip oscillator mode (XIN clock stop) Figure 19.11 shows a Process to Reduce Power Consum ption in High-Speed On-Chip Oscillator Mode, Low- Speed On-Chip Oscillator Mode (XIN Clock Stops) and Low-Speed Clock Mode (XIN Clock Stops). Note that when going to stop or wait mode while the CPU rewrite mode is disabled, the FMR0 register does not need to be set because the power for the flash memory is automatically turned off and is turned back on again after returning from stop or wait mode.

19.4.2.5 FMR06 Bit

This is a read-only bit indicating the status of auto program operation. The bit is set to 1 when a program error occurs; otherwise, it is cleared to 0. For details, refer to the description of the 19.4.5 Full Status Check.

19.4.2.6 FMR07 Bit

This is a read-only bit indicating the status of auto erase operation. The bit is set to 1 when an erase error occurs; otherwise, it is set to 0. Refer to 19.4.5 Full Status Check for the details.

19.4.2.7 FMR11 Bit

Setting this bit to 1 (EW1 mode) places the MCU in EW1 mode.

19.4.2.8 FMR15 Bit

When the FMR02 bit is set to 1 (rewri te enabled) and the FMR15 bit is se t to 0 (rewrite enabled), the block0 accepts the program command and block erase command.

19.4.2.9 FMR16 Bit

When the FMR02 bit is set to 1 (rewri te enabled) and the FMR16 bit is se t to 0 (rewrite enabled), the block1 accepts the program command and block erase command.

19.4.2.10 FMR40 Bit

The suspend function is enabled by setting the FMR40 bit to 1 (enable).

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19.4.2.11 FMR41 Bit

In EW0 mode, the MCU enters erase-suspend mode wh en setting the FMR41 bit to 1 by a program. The FMR41 bit is automatically set to 1 (requests erase-suspend) when an interrupt request of an enabled interrupt is generated in EW1 mode, and then the MCU enters erase-suspend mode. Set the FMR41 bit to 0 (erase restart) when the auto-erase operation restarts.

19.4.2.12 FMR42 Bit

In EW0 mode, the MCU enters program-suspend mode wh en setting the FMR42 bit to 1 by a program. The FMR42 bit is automatically set to 1 (requests program- suspend) when an interrupt request of an enabled interrupt is generated in EW1 mode, and then the MCU enters program-suspend mode. Set the FMR42 bit to 0 (program restarts) when the auto-program operation restarts.

19.4.2.13 FMR43 Bit

When the auto-erase operation starts, the FMR43 bit is set to 1 (during erase execution). The FMR43 bit remains 1 (during erase execution) during erase-suspend operation. When the auto-erase operation ends, the FMR43 bit is set to 0 (erase not executed).

19.4.2.14 FMR44 Bit

When the auto-program starts, the FMR44 bit is set to 1 (during program execution). The FMR44 bit remains 1 (during program execution) during program-suspend operation. When the auto-program operation ends, the FMR44 bit is set to 0 (program not executed).

19.4.2.15 FMR46 Bit

The FMR46 bit is set to 0 (reading disabled) during auto -program or auto-erase execution and set to 1 (reading enabled) in suspend mode. Do not access the flash memory while this bit is set to 0.

19.4.2.16 FMR47 Bit

Power consumption when reading the flash memory can be reduced by set ting the FMR47 bit to 1 (enabled) in low-speed on-chip oscillator mode (XIN clock stops).

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 386 of 458 REJ09B0250-0200 Figure 19.5 FMR0 Register Flash Memory Control Register 0 Symbol Address After Reset FMR0 01B7h 00000001b Bit Symbol Bit Name Function RW RY /BY ____ status flag NOTES: FMR07 b3 b2 b1 b0 (b5-b4) FMR00 FMSTP FMR02 0 : Disables rew rite 1 : Enables rew rite Flash memory stop bit(3,5) 0 : Enables flash memory operation 1 : Stops flash memory (Enters low -pow er consumption state and flash memory is reset) FMR01 Block 0, 1, 2, 3 rew rite enable bit (2,6) 0 : Busy (During w riting or erasing) 1 : Ready CPU rew rite mode select bit(1) b7 b6 b5 b4 RO Reserved bit Set to 0 RW 0 : C om pleted successfully 1 : Terminated by error RW RO RO RW RW 0 : CPU rew rite mode disabled 1 : CPU rew rite mode enabled When setting the FMR01 bit to 0 (CPU rew rite mode disabled), the FMR02 bit is set to 0 (disables rew rite). This bit is set to 0 by executing the clear status command. This bit is enabled w hen the FMR01 bit is set to 1 (CPU rew rite mode enabled). When the FMR01 bit is set to 0 and w riting 1 to the FMSTP bit, the FMSTP bit is set to 1. The flash memory does not enter low -pow er consumption stat FMR06 When setting this bit to 1, set to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. Enter read array mode and set this bit to 0. Set this bit to 1 immediately after setting this bit first to 0 w hile the FMR01 bit is set to 1. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. Set this bit by a program transferred to the RAM. Program status flag(4) 0 : C om pleted successfully 1 : Terminated by error Erase status flag(4)

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 387 of 458 REJ09B0250-0200 Figure 19.6 FMR1 Register Flash Memory Control Register 1 Symbol Address After Reset FMR1 01B5h 1000000Xb Bit Symbol Bit Name Function RW NOTES: b3 b2 Set to 0 b1 b0 FMR11 (b4-b2) b7 b6 b5 b4 RW FMR15 (b0) Reserved bit When read, its content is indeterminate. EW1 mode select bit(1,2) 0 : EW0 mode 1 : EW1 mode Block 0 rew rite disable bit(2,3) 0 : Enables rew rite 1 : Disables rew rite When the FMR01 bit is set to 1 (CPU rew rite mode enabled), the FMR15 and FMR16 bits can be w ritten. When setting this bit to 0, set to 0 immediately after setting it first to 1. When setting this bit to 1, set it to 1. (b7) RW RW RW RO RW Reserved bit 0 : Enables rew rite 1 : Disables rew riteFMR16 Block 1 rew rite disable bit(2,3) When setting this bit to 1, set to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode enable) . Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. This bit is set to 0 by setting the FMR01 bit to 0 (CPU rew rite mode disabled). Reserved bit Set to 1

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 388 of 458 REJ09B0250-0200 Figure 19.7 FMR4 Register Flash Memory Control Register 4 Symbol Address After Reset FMR4 01B3h 01000000b Bit Symbol Bit Name Function RW NOTES: When setting this bit to 1, set to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. This bit is enabled w hen the FMR40 bit is set to 1 (enable) and this bit can be w ritten during the period betw een issuing an erase command and completing an erase (This bit is set to 0 during the periods other than above.) In EW0 mode, this can be set to 0 or 1 by a program. In EW1 mode, this bit is automatically set to 1 if a maskable interrupt is generated during an erase operation w hile the FMR40 bit is set to 1. Do not set this bit to 1 by a program (0 can be w ritten). b3 b2 Set to 0 b1 b0 FMR41 (b5-b2) FMR40 FMR42 FMR44 b7 b6 b5 b4 RW RW Erase-suspend function enable bit(1) 0 : Disables reading 1 : Enables reading Reserved bit 0 : Disable 1 : Enable Erase-suspend request bit (2) 0 : Erase restart 1 : Erase-suspend request RO RO RW FMR43 Erase command flag 0 : Erase not executed 1 : During erase execution RO 0 : Disable 1 : Enable FMR46 Program-suspend request bit(3) 0 : Program restart 1 : Program-suspend request Set the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled) in low -pow er-consumption read mode. In high-speed clock mode and high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled). Program command flag 0 : Program not executed 1 : During program execution RO The FMR42 bit is enabled only w hen the FMR40 bit is set to 1 (enable) and programming to the FMR42 bit is enabled until the auto-program ends since the program command is generated. (This bit is set to 0 during periods other than above.) In EW0 mode, 0 or 1 can be programmed to the FMR42 bit by a program. In EW1 mode, the FMR42 bit is automatically set to 1 by generating a maskable interrupt during the auto-program w hen the FMR40 bit is set to 1. 1 cannot be programmed to the FMR42 bit by a program. FMR47 Read status flag RWLow -pow er consumption read mode enable bit (1,4)

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 391 of 458 REJ09B0250-0200 Figure 19.11 Process to Reduce Power Consumpt ion in High-Speed On-Chip Oscillator Mode, Low-Speed On-Chip Oscillator Mode (XIN Clock Stops) and Low-Speed Clock Mode (XIN Clock Stops) Transfer a high-speed on-chip oscillator mode, low- speed on-chip oscillator mode (XIN clock stops) program to the RAM Jump to the high-speed on-chip oscillator mode, low- speed on-chip oscillator mode (XIN clock stops) program which has been transferred to the RAM. (The subsequent processing is executed by a program in the RAM.) Write 0 to the FMR01 bit before writing 1 (CPU rewrite mode enabled) Switch the clock source for the CPU clock. Turn XIN off Process in high-speed on-chip oscillator mode, low-speed on-chip oscillator mode (XIN clock stops) Write 0 to the FMR01 bit (CPU rewrite mode disabled) Jump to a specified address in the flash memory High-speed on-chip oscillator mode, low-speed on-chip oscillator mode (XIN clock stops) program NOTES: 1. Set the FMR01 bit to 1 (CPU rewrite mode enabled) before setting the FMSTP bit to 1 . 2. Before the clock source for CPU clock can be changed, the clock to which to be changed must be stable. 3. Insert a 30 µs wait time in a program. Do not access to the flash memory during this wait time. Write 1 to the FMSTP bit (Flash memory stops. Low power consumption state)(1) Wait until the flash memory circuit stabilizes (30 µs)(3) Write 0 to the FMSTP bit (flash memory operation) Turn XIN clock on →wait until oscillation stabilizes →switch the clock source for CPU clock(2)

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19.4.3 Software Commands

Software commands are described below. Read or write commands and data from or to in 8-bit units. SRD: Status register data (D7 to D0) WA: Write address (Ensure the address specified in the first bus cycle is the same address as the write address specified in the second bus cycle.) WD: Write data (8 bits) BA: Given block address ×: Any specified address in the user ROM area

19.4.3.1 Read Array Command

The read array command reads the flash memory. The MCU enters read array mode by writing FFh in the first bus cycle. If entering the read address after the following bus cycles, the content of the specified address can be read in 8-bit units. Since the MCU remains in read array mode until another command is written, the contents of multiple addresses can be read continuously. In addition, the MCU enters read array mode after a reset.

19.4.3.2 Read Status Register Command

The read status register command reads the status register. If writing 70h in the first bus cycle, the status register can be read in the second bus cycle. (Refer to 19.4.4 Status Registers) When reading the status register, specify an address in the user ROM area. Do not execute this command in EW1 mode. The MCU remains in read status register mode until the next read array command is written.

19.4.3.3 Clear Status Register Command

The clear status register command sets the status register to 0. If writing 50h in the first bus cycle, the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 in the status register will be set to 0. Table 19.4 Software Commands Command First Bus Cycle Second Bus Cycle Mode Address Data (D7 to D0) Mode Address Data (D7 to D0) Read Array Write × FFh Read Status Register Write × 70h Read × SRD Clear Status Register Write × 50h Program Write WA 40h Write WA WD Block Erase Write × 20h Write BA D0h

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19.4.3.4 Program Command

The program command writes data to the flash memory in 1-byte units. By writing 40h in the first bus cycle and data in the second bus cycle to the write address, and an auto program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle. The FMR00 bit in the FMR0 register can determine whether auto programming has completed. When suspend function disabled, the FMR00 bit is set to 0 during auto-programming and set to 1 when auto- programming completes. When suspend function enabled, the FMR44 bit is set to 1 during auto-programming and set to 0 when auto- programming completes. The FMR06 bit in the FMR0 register can determine the result of auto programming after it has been finished. (Refer to 19.4.5 Full Status Check) When the FMR02 bit in the FMR0 register is set to 0 (disable rewriting), program commands targeting block 0 to 3 are not acknowledged. When the FMR02 bit is set to 1 (rewrite enables) and the FMR15 bit in the FMR1 register is set to 1 (disable rewriting), program comm ands targeting block 0 are not acknowledged. When the FMR16 bit is set to 1 (disable rewriting), program commands targeting block 1 are not acknowledged. Figure 19.12 shows the Program Command (When Susp end Function Disabled). Figure 19.14 shows the Program Command (When Suspend Function Enabled). In EW1 mode, do not execute this command on any address at which the rewrite control program is allocated. In EW0 mode, the MCU enters read status register mode at the same time auto programming starts and the status register can be read. The status register bit 7 (S R7) is set to 0 at the same time auto programming starts and set back to 1 when auto programming completes. In this case, the MCU remains in read status register mode until a read array command is wr itten next. Reading the status regist er can determine the result of auto programming after auto programming has completed. Figure 19.12 Program Command (When Suspend Function Disabled) Start Write the command code 40h to the write address Write data to the write address FMR00 = 1? Full status check Program completed No Yes

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 394 of 458 REJ09B0250-0200 Figure 19.13 Program Command (When Suspend Function Enabled) Start Write the command code 40h to the write address Write data to the write address FMR44 = 0 ? Full status check Program completed No Yes EW0 Mode FMR40 = 1 Start Write the command code 40h Write data to the write address FMR44 = 0 ? Full status check Program completed No Yes EW1 Mode FMR40 = 1 Maskable interrupt (2) REIT Access flash memory FMR42 = 0 NOTES: 1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area. 2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend should be in interrupt enabled status. 3. When no interrupt is used, the instruction to enable interrupts is not needed. 4. td(SR-SUS) is needed until program is suspended after the FMR42 bit in the FMR4 register is set to 1. Maskable interrupt(1) FMR46 = 1 ? REIT Yes FMR42 = 1(4) FMR42 = 0 Access flash memory FMR44 = 1 ? Yes No Access flash memory No I = 1 (enable interrupt) I = 1 (enable interrupt)(3)

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19.4.3.5 Block Erase

If writing 20h in the first bus cycle and D0h to the given address of a block in the second bus cycle, and an auto erase operation (erase and verify) will start. The FMR00 bit in the FMR0 register can determine whether auto erasing has completed. The FMR00 bit is set to 0 during auto erasing and set to 1 when auto erasing completes. The FMR07 bit in the FMR0 register can determine the re sult of auto erasing after auto erasing has completed. (Refer to 19.4.5 Full Status Check) When the FMR02 bit in the FMR0 register is set to 0 (d isable rewriting) or the FMR02 bit is set to 1 (rewrite enables) and the FMR15 bit in the FMR1 register is se t to 1 (disable rewriting) , the block erase command on block 0 is not acknowledged. When the FMR16 bit is se t to 1 (disable rewriting), the block erase command on block 1 is not acknowledged. Do not use the block erase command during program-suspend. Figure 19.14 shows the Block Erase Command (When Er ase-Suspend Function Disabled). Figure 19.15 shows the Block Erase Command (When Erase-Suspend Function Enabled). In EW1 mode, do not execute this command on any address at which the rewrite control program is allocated. In EW0 mode, the MCU enters read status register mode at the same time auto erasing starts and the status register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto erasing starts and set back to 1 when auto erasing completes. In this case, the MCU rema ins in read status register mode until the read array command is written next. Figure 19.14 Block Erase Command (When Erase-Suspend Function Disabled) Start Write the command code 20h Write ‘D0h’ to the given block address FMR00 = 1? Full status check Block erase completed No Yes

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 396 of 458 REJ09B0250-0200 Figure 19.15 Block Erase Command (When Erase-Suspend Function Enabled) Start Write the command code 20h Write D0h to any block address FMR00 = 1 ? Full status check Block erase completed No Yes EW0 Mode FMR40 = 1 Start Write the command code 20h Write D0h to any block address FMR00 = 1 ? Full status check Block erase completed No Yes EW1 Mode I = 1 (enable interrupt) Maskable interrupt (2) REIT Access flash memory FMR41 = 0 NOTES: 1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area. 2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend should be in interrupt enabled status. 3. When no interrupt is used, the instruction to enable interrupts is not needed. 4. td(SR-SUS) is needed until erase is suspended after the FMR41 bit in the FMR4 register is set to 1. Maskable interrupt(1) FMR46 = 1 ? REIT Yes FMR41 = 1(4) FMR41 = 0 Access flash memory FMR43 = 1 ? Yes No Access flash memory No I = 1 (enable interrupt)(3) FMR40 = 1

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19.4.4 Status Registers

The status register indicates the operating status of the flash memory and whether an erasing or programming operation completes normally or in error. Status of the status register can be read by the FMR00, FMR06, and FMR07 bits in the FMR0 register. Table 19.5 lists the Status Register Bits. In EW0 mode, the status register can be read in the following cases:

• When a given address in the user ROM area is read after writing the read status register command
• When a given address in the user ROM area is read after executing the program or block erase command but before executing the read array command.

19.4.4.1 Sequencer Status (Bits SR7 and FMR00)

The sequencer status indicates operating status of the flash memory. SR7 = 0 (busy) during auto programming and auto erasing, and is set to 1 (ready) at the same time the operation completes.

19.4.4.2 Erase Status (Bits SR5 and FMR07)

Refer to 19.4.5 Full Status Check.

19.4.4.3 Program Status (Bits SR4 and FMR06)

Refer to 19.4.5 Full Status Check.

• D0 to D7: Indicates the data bus which is read wh en the read status register command is executed.
• The FMR07 (SR5) to FMR06 bits (SR4) are set to 0 by executing the clear status register command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the program and block erase command cannot be accepted. Table 19.5 Status Register Bits Status Register Bit FMR0 Register Bit Status Name Description Value after Reset01 SR0 (D0) − Reserved −−− SR1 (D1) − Reserved −−− SR2 (D2) − Reserved −−− SR3 (D3) − Reserved −−− SR4 (D4) FMR06 Program status Completed normally Error 0 SR5 (D5) FMR07 Erase status Completed normally Error 0 SR6 (D6) − Reserved −−− SR7 (D7) FMR00 Sequencer status Busy Ready 1

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19.4.5 Full Status Check

When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to 1, indicating occurrence of each specific error. Therefore, checking these status bits (full status check) can determine the executed result. Table 19.6 lists the Errors and FMR0 Register Status. Figure 19.16 shows the Full Status Check and Handling Procedure for Individual Errors. NOTE: 1. The MCU enters read array mode by writing FFh in the second bus cycle of these commands, at the same time the command code written in the first bus cycle will disabled. Table 19.6 Errors and FMR0 Register Status FMR0 Register (Status Register) Status Error Error Occurrence Condition FMR07(SR5) FMR06(SR4) 1 1 Command sequence error

• When any command is not written correctly
• When invalid data other than those that can be written in the second bus cycle of the block erase command is written (i.e., other than D0h or FFh) (1)
• When executing the program command or block erase command while rewriting is disabled using the FMR02 bit in the FMR0 register, the FMR15 or FMR16 bit in the FMR1 register.
• When inputting and erasing the address in which the Flash memory is not allocated during the erase command input
• When executing to erase the block which disables rewriting during the erase command input.
• When inputting and writing the address in which the Flash memory is not allocated during the write command input.
• When executing to write the block which disables rewriting during the write command input. 1 0 Erase error • When the block erase command is executed but not automatically erased correctly 0 1 Program error • When the program command is executed but not automatically programmed correctly.

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 399 of 458 REJ09B0250-0200 Figure 19.16 Full Status Check and Ha ndling Procedure for Individual Errors NOTE: 1. To rewrite to the address where the program error occurs, check if the full status check is complete normally and write to the address after the block erase command is executed. Full status check FMR06 = 1 and FMR07 = 1? FMR07 = 1? FMR06 = 1? Full status check completed No Yes Yes No Yes No Command sequence error Erase error Program error Command sequence error Execute the clear status register command (set these status flags to 0) Check if command is properly input Re-execute the command Erase error Execute the clear status register command (set these status flags to 0) Erase command re-execution times ≤ 3 times? Re-execute block erase command Program error Execute the clear status register command (set these status flags to 0) Specify the other address besides the write address where the error occurs for the program address(1) Re-execute program command Block targeting for erasure cannot be used No Yes

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19.5 Standard Serial I/O Mode

In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a serial programmer which is applicable for the MCU. There are three types of Standard serial I/O modes:

• Standard serial I/O mode 1 . . . . Clock synchronous serial I/O used to connect with a serial programmer
• Standard serial I/O mode 2 . . . . Clock asynchronous serial I/O used to connect with a serial programmer
• Standard serial I/O mode 3 . . . . Special clock asynchronous serial I/O used to connect with a serial programmer This MCU uses Standard serial I/O mode 2 and Standard serial I/O mode 3. Refer to Appendix 2. Connection Examples between S erial Writer and On-Chip Debugging Emulator . Contact the manufacturer of your serial programmer for serial programmer. Refer to the user’s manual of your serial programmer for details on how to use it. Table 19.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2), Table 19.8 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 3), Figure 19.17 shows Pin Connections for Standard Serial I/O Mode 3. After processing the pins shown in Table 19.8 and rewriting a flash memory using a writer, apply “H” to the MODE pin and reset a hardware if a program is operated on the flash memory in single-chip mode.

19.5.1 ID Code Check Function

The ID code check function determines whether the ID codes sent from the serial programmer and those written in the flash memory match (refer to 19.3 Functions to Prevent Rewriting of Flash Memory). Table 19.7 Pin Functions (Flash Memory Standard Serial I/O Mode 2) Pin Name I/O Description VCC,VSS Power input Apply the voltage guaranteed for programming and erasure to the VCC pin and 0 V to the VSS pin. RESET Reset input I Rese t input pin. P4_6/XIN P4_6 input/clock input I Connect a ceramic resonator or crystal oscillator between the XIN and XOUT pins. P4_7/XOUT P4_7 input/clock output I/O P0_0 to P0_7 Input port P0 I Input “H” or “L” level signal or leave the pin open. P1_0 to P1_7 Input port P1 I Input “H” or “L” level signal or leave the pin open. P2_0 to P2_7 Input port P2 I Input “H” or “L” level signal or leave the pin open. P3_0, P3_1, P3_3 to P3_5, P3_7 Input port P3 I Input “H” or “L” level signal or leave the pin open. P4_2, P4_5 Input port P4 I Input “H” or “L” level signal or leave the pin open. P6_0 to P6_5 Input port P6 I Input “H” or “L” level signal or leave the pin open. MODE MODE I Input “L”. P6_6 TXD output O Serial data input pin. P6_7 RXD input I Serial data output pin.

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 401 of 458 REJ09B0250-0200 Table 19.8 Pin Functions (Flash Memory Standard Serial I/O Mode 3) Pin Name I/O Description VCC,VSS Power input Apply the voltage guaranteed for programming and erasure to the VCC pin and 0 V to the VSS pin. RESET Reset input I Re set input pin. P4_6/XIN P4_6 input/clock input I Connect ceramic resonator or crystal oscillator between XIN and XOUT pins when connecting external oscillator. Apply “H” and “L” or leave the pin open when using as input port P4_7/XOUT P4_7 input/clock output I/O P0_0 to P0_7 Input port P0 I Input “H” or “L” level signal or leave the pin open. P1_0 to P1_7 Input port P1 I Input “H” or “L” level signal or leave the pin open. P2_0 to P2_7 Input port P2 I Input “H” or “L” level signal or leave the pin open. P3_0, P3_1, P3_3 to P3_5, P3_7 Input port P3 I Input “H” or “L” level signal or leave the pin open. P4_2 to P4_5 Input port P4 I Input “H” or “L” level signal or leave the pin open. P6_0 to P6_7 Input port P6 I Input “H” or “L” level signal or leave the pin open. MODE MODE I/O Serial data I/O pin. connect to the flash programmer.

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 402 of 458 REJ09B0250-0200 Figure 19.17 Pin Connections for Standard Serial I/O Mode 3 NOTE: 1. No need to connect an oscillating circuit when operating with on-chip oscillator clock. VSSMODE Connect oscillator circuit(1) VCC R8C/20 Group, R8C/21 Group Mode setting Signal Value MODE RESET Voltage from programmer VSS → VCC

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19.5.1.1 Example of Circuit Applicati on in the Standard Serial I/O Mode

Figure 19.18 shows an example of Pin Processing in Standard Serial I/O Mode 2 and Figure 19.19 shows an example of Pin Processing in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the programmer, refer to the manual of your serial programmer. Figure 19.18 Pin Processing in Standard Serial I/O Mode 2 Figure 19.19 Pin Processing in Standard Serial I/O Mode 3 NOTES: 1. In this example, modes are switched between single-chip mode and standard serial I/O mode by controlling the MODE input with a switch. 2. Connecting the oscillation is necessary. Set the main clock frequency 1 MHz to 20 MHz. Refer to Appendix Figure 2.1 Connection Example with M16C Flash Starter (M3A-0806). MCU TXD RXD Data output Data input MODE NOTES: 1. Controlled pins and external circuits vary depending on the programmer. Refer to the programmer manual for details. 2. In this example, modes are switched between single-chip mode and standard serial I/O mode by connecting a programmer. 3. When operating with on-chip oscillator clock, connecting the oscillating circuit is not necessary. MCU MODE RESET User reset signal MODE I/O Reset input

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19.6 Parallel I/O Mode

Parallel I/O mode is used to input and output the required software command, address and data parallel to controls (read, program and erase) for internal flash memory. Use a parallel programmer which supports this MCU. Contact the manufacturer of your parallel programmer about the parallel programmer and refer to the user’s manual of your parallel programmer for details on how to use it. User ROM area can be rewritten shown in Figure 19.1 and Figure 19.2 in parallel I/O mode.

19.6.1 ROM Code Protect Function

The ROM code protect function disables to r ead and rewrite the flash memory. (Refer to 19.3 Functions to Prevent Rewriting of Flash Memory.)

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19.7 Notes on Flash Memory

19.7.1 CPU Rewrite Mode

19.7.1.1 Operating Speed

Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register. This usage note is not needed for EW1 mode.

19.7.1.2 Prohibited Instructions

The following instructions cannot be used in EW0 mode because the flash memory inte rnal data is referenced: UND, INTO, and BRK instructions.

19.7.1.3 Interrupts

Table 19.9 lists the EW0 Mode Interrupts and Table 19.10 lists the EW1 Mode Interrupts. NOTES: 1. Do not use the address match interrupt while the command is executed because the vector of the address match interrupt is allocated on ROM. 2. Do not use the non-maskable interrupt while bl ock 0 is automatically erased because the fixed vector is allocated block 0. Table 19.9 EW0 Mode Interrupts Mode Status When Maskable Interrupt Request is Acknowledged When Watchdog Timer, Oscillation Stop Detection and Voltage Monitor 2 Interrupt Request are Acknowledged EW0 During automatic erasing Any interrupt can be used by allocating a vector to RAM Once an interrupt request is acknowledged, the auto-programming or auto-erasing is forcibly stopped immediately and resets the flash memory. An interrupt process starts after the fixed period and the flash memory restarts. Since the block during the auto- erasing or the address during the auto- programming is forcibly stopped, the normal value may not be read. Execute the auto-erasing again and ensure the auto- erasing is completed normally. Since the watchdog timer does not stop during the command operation, the interrupt request may be generated. Reset the watchdog timer regularly. Automatic writing

R8C/20 Group, R8C/21 Group 19. Flash Memory Rev.2.00 Aug 27, 2008 Page 406 of 458 REJ09B0250-0200 NOTES: 1. Do not use the address match interrupt while the command is executed because the vector of the address match interrupt is allocated on ROM. 2. Do not use the non-maskable interrupt while bl ock 0 is automatically erased because the fixed vector is allocated block 0.

19.7.1.4 How to Access

Write 0 to the corresponding bits before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt between writing 0 and 1.

19.7.1.5 Rewriting User ROM Area

In EW0 mode, if the power supply voltage drops while rewriting any block in which the rewrite control program is stored, the flash memory may not be able to be rewritten because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode.

19.7.1.6 Program

Do not write additions to the already programmed address. Table 19.10 EW1 Mode Interrupts Mode Status When Maskable Interrupt Request is Acknowledged When Watchdog Timer, Oscillation Stop Detection and Voltage Monitor 2 Interrupt Request are Acknowledged EW1 During automatic erasing (erase- suspend function is enabled) The auto-erasing is suspended after td(SR-SUS) and the interrupt process is executed. The auto-erasing can be restarted by setting the FMR41 bit in the FMR4 register to 0 (erase restart) after the interrupt process completes. Once an interrupt request is acknowledged, the auto- programming or auto-erasing is forcibly stopped immediately and resets the flash memory. An interrupt process starts after the fixed period and the flash memory restarts. Since the block during the auto-erasing or the address during the auto- programming is forcibly stopped, the normal value may not be read. Execute the auto-erasing again and ensure the auto-erasing is completed normally. Since the watchdog timer does not stop during the command operation, the interrupt request may be generated. Reset the watchdog timer regularly using the erase-suspend function. During automatic erasing (erase- suspend function is disabled) The auto-erasing has a priority and the interrupt request acknowledgement is waited. The interrupt process is executed after the auto-erasing completes. During automatic programming (program suspend function enabled) The auto-programming is suspended after td(SR-SUS) and the interrupt process is executed. The auto- programming can be restarted by setting the FMR42 bit in the FMR4 register to 0 (program restart) after the interrupt process completes. Auto programming (program suspend function disabled) The auto-programming has a priority and the interrupt request acknowledgement is waited. The interrupt process is executed after the auto- programming completes.

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19.7.1.7 Entering Stop Mode or Wait Mode

Do not enter stop mode or wait mode during erase-suspend.

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 408 of 458 REJ09B0250-0200 20. Electrical Characteristics NOTES: 1. V CC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified. 2. The average output current indicates the av erage value of current measured during 100 ms. Table 20.1 Absolute Maximum Ratings Symbol Parameter Condition Rated value Unit VCC/AVCC Supply voltage -0.3 to 6.5 V VI Input voltage -0.3 to V CC+0.3 V VO Output voltage -0.3 to V CC+0.3 V Pd Power dissipation -40 °C ≤ Topr ≤ 85°C 300 mW 85°C < Topr ≤ 125°C 125 mW Topr Operating ambient temperature -40 to 85 (J version) / -40 to 125 (K version) Tstg Storage temperature -65 to 150 °C Table 20.2 Recommended Operating Conditions Symbol Parameter Conditions Standard UnitMin. Typ. Max. VCC/AVCC Supply voltage 2.7 − 5.5 V VSS/AVCC Supply voltage − 0 − V VIH Input “H” voltage 0.8V CC − VCC V VIL Input “L” voltage 0 − 0.2VCC V IOH(sum) Peak sum output “H” current Sum of all Pins IOH (peak) −− -60 mA IOH(peak) Peak output “H” current −− -10 mA IOH(avg) Average output “H” current −− -5 mA IOL(sum) Peak sum output “L” currents Sum of all Pins IOL (peak) −− 60 mA IOL(peak) Peak output “L” currents −− 10 mA IOL(avg) Average output “L” current −− 5m A f(XIN) XIN clock input oscillation frequency 3.0 V ≤ VCC ≤ 5.5 V -40°C ≤ Topr ≤ 85°C 0 − 20 MHz 3.0 V ≤ VCC ≤ 5.5 V -40°C ≤ Topr ≤ 125°C 0 − 16 MHz 2.7 V ≤ VCC < 3.0 V 0 − 10 MHz − System clock OCD2 = 0 When XIN clock is selected. 3.0 V ≤ VCC ≤ 5.5 V -40°C ≤ Topr ≤ 85°C 0 − 20 MHz 3.0 V ≤ VCC ≤ 5.5 V -40°C ≤ Topr ≤ 125°C 0 − 16 MHz 2.7 V ≤ VCC < 3.0 V 0 − 10 MHz OCD2 = 1 When on-chip oscillator clock is selected. FRA01 = 0 When low-speed on- chip oscillator clock is selected. − 125 − kHz FRA01 = 1 When high-speed on- chip oscillator clock is selected. 3.0 V ≤ VCC ≤ 5.5 V -40°C ≤ Topr ≤ 85°C −− 20 MHz FRA01 = 1 When high-speed on- chip oscillator clock is selected. −− 10 MHz

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 409 of 458 REJ09B0250-0200 NOTES: 1. V CC = AVCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified. 2. When analog input voltage exceeds reference voltage, A/D conv ersion result is 3FFh in 10-bit mode, FFh in 8-bit mode. Figure 20.1 Ports P0 to P4, P6 Timing Measurement Circuit Table 20.3 A/D Converter Characteristics Symbol Parameter Conditions Standard UnitMin. Typ. Max. − Resolution V ref = AVCC −− 10 Bits − Absolute Accuracy 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V −− ±3 LSB 8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V −− ±2 LSB 10-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V −− ±5 LSB 8-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V −− ±2 LSB Rladder Resistor ladder V ref = AVCC 10 − 40 k Ω tconv Conversion time 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 3.3 −− µ s 8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 2.8 −− µ s Vref Reference voltage 2.7 − AVCC V VIA Analog input voltage(2) 0 − AVCC V − A/D operating clock frequency Without sample & hold 0.25 − 10 MHz With sample & hold 1 − 10 MHz 30pF

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 410 of 458 REJ09B0250-0200 NOTES: 1. V CC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations , the actual erasure endurance can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failur e rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. Table 20.4 Flash Memory (Program ROM) Electrical Characteristics Symbol Parameter Conditions Standard UnitMin. Typ. Max. − Program/erase endurance(2) R8C/20 Group 100(3) −− times R8C/21 Group 1,000(3) −− times − Byte program time − 50 400 µs − Block erase time − 0.4 9 s td(SR-SUS) Time delay from suspend request until erase suspend −− 97 + CPU clock × 6 cycle µs − Interval from erase start/restart until following suspend request 650 −− µ s − Interval from program start/restart until following suspend request 0 −− ns − Time from suspend until program/erase restart −− 3 + CPU clock × 4 cycle µs − Program, erase voltage 2.7 − 5.5 V − Read voltage 2.7 − 5.5 V − Program, erase temperature 0 − 60 °C − Data hold time(7) Ambient temperature = 55°C2 0 −− year

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 411 of 458 REJ09B0250-0200 NOTES: 1. V CC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. MInimum endurance to guarantee all electrical characteristics after program and erase (1 to Min. value can be guaranteed). 4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times are the same as that in program ROM. 5. In a system that executes multiple programming operations , the actual erasure endurance can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 6. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failur e rate information should contact their Renesas technical support representative. 8. 125 °C for K version. 9. The data hold time includes time that the power supply is off or the clock is not supplied. Table 20.5 Flash Memory (Data Flash Block A, Block B) Electrical Characteristics(4) Symbol Parameter Conditions Standard UnitMin. Typ. Max. − Program/erase endurance(2) 10,000(3) −− times − Byte program time (Program/erase endurance ≤ 1,000 times) − 50 400 µs − Byte program time (Program/erase endurance > 1,000 times) − 65 −µ s − Block erase time (Program/erase endurance ≤ 1,000 times) − 0.2 9 s − Block erase time (Program/erase endurance > 1,000 times) − 0.3 − s td(SR-SUS) Time delay from suspend request until erase suspend −− 97 + CPU clock × 6 cycle µs − Interval from erase start/restart until following suspend request 650 −− µ s − Interval from program start/restart until following suspend request 0 −− ns − Time from suspend until program/erase restart −− 3 + CPU clock × 4 cycle µs − Program, erase voltage 2.7 − 5.5 V − Read voltage 2.7 − 5.5 V − Program, erase temperature -40 − 85(8) °C − Data hold time(9) Ambient temperature = 55°C2 0 −− year

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 412 of 458 REJ09B0250-0200 Figure 20.2 Time de lay until Suspend NOTES: 1. The measurement condition is V CC = 2.7 V to 5.5 V and Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version). 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 3. Hold V det2 > Vdet1. 4. This parameter shows the voltage detection level when the power supply drops. The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 V. 5. Time until the voltage monitor 1 rese t is generated after the voltage passes Vdet1 when VCC falls. When using the digital filter, its sampling time is added to td(Vdet1-A). When using the voltage monitor 1 reset, maintain this time until VCC = 2.0 V after the voltage passes Vdet1 when the power supply falls. NOTES: 1. The measurement condition is V CC = 2.7 V to 5.5 V and Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version). 2. Time until the voltage monitor 2 reset/interrupt request is generated since the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. 4. Hold V det2 > Vdet1. 5. When using the digital filter, its sampling time is added to t d(Vdet2-A). When using the voltage monitor 2 reset, maintain this time until VCC = 2.0 V after the voltage passes Vdet2 when the power supply falls. Table 20.6 Voltage Detection 1 Circuit Electrical Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. Vdet1 Voltage detection level(3, 4) 2.70 2.85 3.00 V td(Vdet1-A) Voltage monitor 1 reset generation time(5) − 40 200 µs − Voltage detection circuit self power consumption VCA26 = 1, V CC = 5.0 V − 0.6 −µ A td(E-A) Waiting time until voltage detection circuit operation starts(2) −− 100 µs Vccmin MCU operating voltage minimum value 2.70 −− V Table 20.7 Voltage Detection 2 Circuit Electrical Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. Vdet2 Voltage detection level(4) 3.3 3.6 3.9 V td(Vdet2-A) Voltage monitor 2 reset/interrupt request generation time(2, 5) − 40 200 µs − Voltage detection circuit self power consumption VCA27 = 1, V CC = 5.0V − 0.6 −µ A td(E-A) Waiting time until voltage detection circuit operation starts(3) −− 100 µs FMR46 Suspend request (Maskable interrupt request) Fixed time td(SR-SUS) Clock-dependent time Access restart

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 413 of 458 REJ09B0250-0200 NOTES: 1. Topr = -40 °C to 85°C (J version) / -40°C to 125°C (K version), unless otherwise specified. 2. This condition (the minimum value of external power VCC rise gradient) does not apply if Vpor2 ≥ 1.0 V. 3. To use the power-on reset function, enable voltage monitor 1 rese t by setting the LVD1ON bit in the OFS register to 0, the VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register to 1. 4. t w(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30s or more if -20°C ≤ Topr ≤ 125°C, maintain tw(por1) for 3,000s or more if -40°C ≤ Topr < -20°C. Figure 20.3 Power-on Reset Circuit Electrical Characteristics Table 20.8 Power-on Reset Circuit, Voltage Moni tor 1 Reset Circuit Electrical Characteristics(3) Symbol Parameter Condition Standard Unit Min. Typ. Max. Vpor1 Power-on reset valid voltage(4) −− 0.1 V Vpor2 Power-on reset or voltage monitor 1 valid voltage 0 − Vdet1 V trth External power V CC rise gradient V CC ≤ 3.6 V 20(2) −− mV/msec VCC > 3.6 V 20(2) − 2,000 mV/msec × 321 fOCO-S Vdet1(3) Vpor1 tw(por1) Vdet1(3) Vpor2 (“L” valid) Sampling time(1, 2) td(Vdet1-A) × 321 fOCO-S NOTES: 1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or higher during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit for details.

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 414 of 458 REJ09B0250-0200 NOTES: 1. V CC = 2.7 V to 5.5 V, Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version), unless otherwise specified. 2. The standard value shows when the reset is deasserted for the FRA1 register. NOTE: 1. V CC = 2.7 V to 5.5 V, Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version), unless otherwise specified. NOTES: 1. The measurement condition is V CC = 2.7 to 5.5 V and Topr = -40°C to 85°C (J version) / -40°C to 125°C (K version), unless otherwise specified. 2. Waiting time until the internal power s upply generation circuit stabilizes during power-on. 3. Time until CPU clock supply starts since t he interrupt is acknowledged to exit stop mode. Table 20.9 High-Speed On-Chip Oscillator Circuit Electrical Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. fOCO40M High-speed on-chip oscill ator frequency temperature

• supply voltage dependence VCC = 4.75 V to 5.25 V, 0°C ≤ Topr ≤ 60°C(2) 39.2 40 40.8 MHz VCC = 3.0 V to 5.25 V, -20°C ≤ Topr ≤ 85°C(2) 38.8 40 41.2 MHz VCC = 3.0 V to 5.5 V, -40°C ≤ Topr ≤ 85°C(2) 38.4 40 41.6 MHz VCC = 3.0 V to 5.5 V, -40°C ≤ Topr ≤ 125°C(2) 38.0 40 42.0 MHz VCC = 2.7 V to 5.5 V, -40°C ≤ Topr ≤ 125°C(2) 37.6 40 42.4 MHz − The value of the FRA1 register when the reset is deasserted 08h 40 F7h − − High-speed on-chip oscillator adjustment range Adjust the FRA1 register to -1 bit (the value when the reset is deasserted) − + 0.3 − MHz − Oscillation stability time − 10 100 µs − Self power consumption when high-speed on-chip oscillator oscillating VCC = 5.0 V, Topr = 25°C − 600 −µ A Table 20.10 Low-Speed On-Chip Oscillator Circuit Electrical Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. fOCO-S Low-speed on-chip oscillator frequency 40 125 250 kHz − Oscillation stability time − 10 100 µs − Self power consumption when low-speed on-chip oscillator oscillating VCC = 5.0 V, Topr = 25°C − 15 −µ A Table 20.11 Power Supply Circuit Timing Characteristics Symbol Parameter Condition Standard UnitMin. Typ. Max. td(P-R) Time for internal power supply stabilization during power-on(2) 1 − 2000 µs td(R-S) STOP exit time(3) −− 150 µs

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 415 of 458 REJ09B0250-0200 NOTES: 1. V CC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified. 2. 1t CYC = 1/f1(s) Table 20.12 Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1) Symbol Parameter Conditions Standard UnitMin. Typ. Max. tSUCYC SSCK clock cycle time 4 −− tCYC(2) tHI SSCK clock “H” width 0.4 − 0.6 t SUCYC tLO SSCK clock “L” width 0.4 − 0.6 t SUCYC tRISE SSCK clock rising time Master −− 1 tCYC(2) Slave −− 1 µs tFALL SSCK clock falling time Master −− 1 tCYC(2) Slave −− 1 µs tSU SSO, SSI data input setup time 100 −− ns tH SSO, SSI data input hold time 1 −− tCYC(2) tLEAD SCS setup time Slave 1t CYC + 50 −− ns tLAG SCS hold time Slave 1t CYC + 50 −− ns tOD SSO, SSI data output delay time −− 1 tCYC(2) tSA SSI slave access time −− 1tCYC + 100 ns tOR SSI slave out open time −− 1tCYC + 100 ns

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 416 of 458 REJ09B0250-0200 Figure 20.4 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master) VIH or VOH VIH or VOH tHI tLO tHI tFALL tRISE tLO tSUCYC tOD tHtSU SCS (output) SSCK (output) (CPOS = 1) SSCK (output) (CPOS = 0) SSO (output) SSI (input) 4-wire bus communication mode, Master, CPHS = 1 VIH or VOH VIH or VOH tHI tLO tHI tFALL tRISE tLO tSUCYC tOD tHtSU SCS (output) SSCK (output) (CPOS = 1) SSCK (output) (CPOS = 0) SSO (output) SSI (input) 4-wire bus communication mode, Master, CPHS = 0 CPHS, CPOS: Bits in SSMR register

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 417 of 458 REJ09B0250-0200 Figure 20.5 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave) VIH or VOH VIH or VOH SCS (input) SSCK (input) (CPOS = 1) SSCK (input) (CPOS = 0) SSO (input) SSI (output) 4-wire bus communication mode, Slave, CPHS = 1 VIH or VOH VIH or VOH tHI tLO tHI tFALL tRISE tLO tSUCYC tHtSU SCS (input) SSCK (input) (CPOS = 1) SSCK (input) (CPOS = 0) SSO (input) SSI (output) 4-wire bus communication mode, Slave, CPHS = 0 tOD tLEAD tSA tLAG tOR tHI tLO tHI tFALL tRISE tLO tSUCYC tHtSU tOD tLEAD tSA tLAG tOR CPHS, CPOS: Bits in SSMR register

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 418 of 458 REJ09B0250-0200 Figure 20.6 I/O Timing of Clock Synchr onous Serial I/O with Chip Select (Clock Synchronous Communication Mode) VIH or VOH tHI tLO tSUCYC tOD tHtSU SSCK SSO (output) SSI (input) VIH or VOH

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 419 of 458 REJ09B0250-0200 NOTES: 1. V CC = 2.7 to 5.5 V, VSS = 0V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified. 2. 1t CYC = 1/f1(s) Figure 20.7 I/O Timing of I 2C Bus Interface Table 20.13 Timing Requirements of I 2C Bus Interface(1) Symbol Parameter Conditions Standard UnitMin. Typ. Max. tSCL SCL input cycle time 12t CYC + 600(2) −− ns tSCLH SCL input “H” width 3t CYC + 300(2) −− ns tSCLL SCL input “L” width 5t CYC + 300(2) −− ns tsf SCL, SDA input falling time −− 300 ns tSP SCL, SDA input spike pulse rejection time −− 1tCYC(2) ns tBUF SDA input bus-free time 5tCYC(2) −− ns tSTAH Start condition input hole time 3tCYC(2) −− ns tSTAS Retransmit start condition input setup time 3tCYC(2) −− ns tSTOP Stop condition input setup time 3tCYC(2) −− ns tSOAS Data input setup time 1t CYC + 20(2) −− ns tSDAH Data input hold time 0 −− ns SDA SCL tBUF VIH VIL P(2) S(1) tSTAH tSCLH tSCLL tSf tSr tSCL tSDAH Sr(3) P(2) tSDAS tSTAS tSP tSTOP NOTES: 1. Start condition 2. Stop condition 3. Retransmit “Start” condition

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 420 of 458 REJ09B0250-0200 NOTE: 1. V CC = 4.2 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), f(XIN) = 20 MHz, unless otherwise specified. Table 20.14 Electrical Characteristics (1) [V CC = 5 V] Symbol Parameter Condition Standard UnitMin. Typ. Max. VOH Output “H” Voltage Except XOUT I OH = -5 mA V CC − 2.0 − VCC V IOH = -200 µAV CC − 0.3 − VCC V XOUT Drive capacity HIGH IOH = -1 mA V CC − 2.0 − VCC V Drive capacity LOW IOH = -500 µAV CC − 2.0 − VCC V VOL Output “L” Voltage Except XOUT I OL = 5 mA −− 2.0 V IOL = 200 µA −− 0.45 V XOUT Drive capacity HIGH IOL = 1 mA −− 2.0 V Drive capacity LOW IOL = 500 µA −− 2.0 V VT+-VT- Hysteresis INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, SSI, SCL, SDA, SSO 0.1 0.5 − V RESET 0.1 1.0 − V IIH Input “H” current VI = 5 V, V CC = 5 V −− 5.0 µA IIL Input “L” current VI = 0 V, V CC = 5 V −− -5.0 µA RPULLUP Pull-Up Resistance VI = 0 V, V CC = 5 V 30 50 167 k Ω RfXIN Feedback Resistance XIN − 1.0 − MΩ VRAM RAM Hold Voltage During stop mode 2.0 −− V

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 421 of 458 REJ09B0250-0200 Table 20.15 Electrical Characteristics (2) [V CC = 5 V] (Topr = -40 to 85°C (J version) / -40 to 125°C (K version), Unless Otherwise Specified.) Symbol Parameter Condition Standard UnitMin. Typ. Max. ICC Power supply current (VCC = 3.3 to 5.5 V) In single-chip mode, the output pins are open and other pins are V SS High-clock mode XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division − 11.0 22.0 mA XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division − 8.8 17.6 mA XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division − 5.8 − mA XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 5.0 − mA XIN = 16MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 3.8 − mA XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 2.8 − mA High-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division − 5.8 11.6 mA XIN clock off High-speed on-chip oscillator on fOCO= 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 2.5 − mA Low-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 FMR47 = 1 − 143 286 µA Wait mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA20 = 0 VCA26 = VCA27 = 0 − 53 106 µA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA20 = 0 VCA26 = VCA27 = 0 − 38 76 µA Stop mode Topr = 25°C XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 − 0.8 3.0 µA Stop mode Topr = 85°C XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 − 1.2 −µ A Stop mode Topr = 125°C XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 − 4.0 −µ A

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 424 of 458 REJ09B0250-0200 NOTE: 1. V CC = 2.7 to 3.3 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), f(XIN) = 10 MHz, unless otherwise specified. Table 20.20 Electrical Characteristics (3) [V CC = 3 V] Symbol Parameter Condition Standard UnitMin. Typ. Max. VOH Output “H” voltage Except XOUT I OH = -1 mA V CC − 0.5 − VCC V XOUT Drive capacity HIGH IOH = -0.1 mA V CC − 0.5 − VCC V Drive capacity LOW IOH = -50 µAV CC − 0.5 − VCC V VOL Output “L” voltage Except XOUT I OL = 1 mA −− 0.5 V XOUT Drive capacity HIGH IOL = 0.1 mA −− 0.5 V Drive capacity LOW IOL = 50 µA −− 0.5 V VT+-VT- Hysteresis INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, SSI, SCL, SDA, SSO 0.1 0.3 − V RESET 0.1 0.4 − V IIH Input “H” current VI = 3 V, V CC = 3 V −− 4.0 µA IIL Input “L” current VI = 0 V, V CC = 3 V −− -4.0 µA RPULLUP Pull-up resistance VI = 0 V, V CC = 3 V 66 160 500 k Ω RfXIN Feedback resistance XIN − 3.0 − MΩ VRAM RAM hold voltage During stop mode 2.0 −− V

R8C/20 Group, R8C/21 Group 20. Electrical Characteristics Rev.2.00 Aug 27, 2008 Page 425 of 458 REJ09B0250-0200 Table 20.21 Electrical Characteristics (4) [V CC = 3 V] (Topr = -40 to 85°C (J version) / -40 to 125°C (K version), Unless Otherwise Specified.) Symbol Parameter Condition Standard UnitMin. Typ. Max. ICC Power supply current (VCC = 2.7 to 3.3 V) In single-chip mode, the output pins are open and other pins are V SS High-clock mode XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division − 10.5 21.0 mA XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division − 8.3 16.6 mA XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division − 5.3 10.6 mA XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 4.5 − mA XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 3.3 − mA XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 2.3 − mA High-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division − 5.6 11.2 mA XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 − 2.4 − mA Low-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 FMR47 = 1 − 138 276 µA Wait mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA20 = 0 VCA26 = VCA27 = 0 − 48 96 µA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA20 = 0 VCA26 = VCA27 = 0 − 35 70 µA Stop mode Topr = 25°C XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 − 0.7 3.0 µA Stop mode Topr = 85°C XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 − 1.1 −µ A Stop mode Topr = 125°C XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 − 3.8 −µ A

R8C/20 Group, R8C/21 Group 21. Usage Notes Rev.2.00 Aug 27, 2008 Page 428 of 458 REJ09B0250-0200 21. Usage Notes

21.1 Notes on Clock Generation Circuit

21.1.1 Stop Mode

When entering stop mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and the CM10 bit to “1” (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit in the CM1 register to “1” (stop mode) and the program stops. Insert at l east 4 NOP instructions following the JMP.B instruction immediately after the instruction which sets the CM10 bit to “1”.

• Example to enter stop mode BCLR 1,FMR0 ; CPU rewrite mode disabled BSET 0,PRCR ; Protect disabled FSET I ; Enable interrupt BSET 0,CM1 ; Stop mode JMP.B LABEL_001 LABEL_001: NOP NOP NOP NOP

21.1.2 Wait Mode

When entering wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT inst ruction and the program stops. Insert at least 4 NOP instructions after the WAIT instruction.

• Example to execute the WAIT instruction BCLR 1,FMR0 ; CPU rewrite mode disabled FSET I ; Enable interrupt WAIT ; Wait mode NOP NOP NOP NOP

21.1.3 Oscillation Stop Detection Function

Since the oscillation stop detection function cannot be us ed if the XIN clock frequency is less than 2 MHz, set the OCD1 to OCD0 bits to 00b.

21.1.4 Oscillation Circuit Constants

Ask the maker of the oscillator to specify the beat oscillation circuit constants on your system.

R8C/20 Group, R8C/21 Group 21. Usage Notes Rev.2.00 Aug 27, 2008 Page 429 of 458 REJ09B0250-0200

21.2 Notes on Interrupts

21.2.1 Reading Address 00000h

Do not read the address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to 0. If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause a problem that the interrupt is canceled, or an unexpected interrupt is generated.

21.2.2 SP Setting

Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an interrupt is acknowledged before setting any value in the SP, the program may run out of control.

21.2.3 External Interrupt and Key Input Interrupt

Either an “L” level or an “H” level of width shown in the Electrical Characteristic s is necessary for the signal input to the INT0 to INT3 pins and KI0 to KI3 pins regardless of the CPU clocks. For details, refer to Table 20.19 External Interrupt INTi (i = 0 to 3) Input, Table 20.25 External Interrupt INTi (i = 0 to 3) Input.

R8C/20 Group, R8C/21 Group 21. Usage Notes Rev.2.00 Aug 27, 2008 Page 430 of 458 REJ09B0250-0200

21.2.4 Changing Interrupt Sources

The IR bit in the interrupt control register may be se t to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source. In addition, the changes of interrupt sources include al l sources that change the in terrupt sources assigned to individual software interrupt numbers, polarities, and timin g. Therefore, when a mode change of the peripheral functions involves interrupt sources, edge polarities, and timing, Set the IR bit to 0 (no interrupt requested) after the change. Refer to each peripheral function for the interrupts caused by the peripheral functions. Figure 21.1 shows an Example of Procedure for Changing Interrupt Sources. Figure 21.1 Example of Procedure for Changing Interrupt Sources NOTES: 1. Execute the above settings individually. Do not execute two or more settings at once (by one instruction). 2. To prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 of the interrupt whose source is changed. 3. Refer to 12.6.5 Changing Interrupt Control Register Contents for the instructions to be used and usage notes. Interrupt source change Disable interrupts(2, 3) Set the IR bit to 0 (interrupt not requested) using the MOV instruction(3) Change interrupt source (including mode of peripheral function) Enable interrupts(2, 3) Change completed IR bit: The interrupt control register bit of an interrupt whose source is changed.

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21.2.5 Changing Interrupt C ontrol Register Contents

(a) Each interrupt control re gister can only be changed while inte rrupt requests corr esponding to that register are not generated. If interrupt requests may be generated, disable the interrupts before changing the interrupt control register. (b) When changing any interrupt control register after disabling interrupts, be careful with the instructions to be used. When changing any bit other than IR bit If an interrupt request corresponding to that register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and th e interrupt request may be ignored. If this causes a problem, use the following instructions to change the register. Instructions to use: AND, OR, BCLR, BSET When changing IR bit If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction to be used. Therefore, use the MOV instruction to set the IR bit to 0. (c) When disabling interrupts using the I flag, set the I flag accordin g to the following sample programs. Refer to (b) for the change of interrupt control registers in the sample programs. Sample programs 1 to 3 are preventing the I flag from being set to 1 (interrupt enables) before changing the interrupt control register for reasons of the internal bus or the instruction queue buffer. Example 1: Use NOP instruct ions to prevent I flag being set to 1 before interrupt control register is changed INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts Example 2: Use dummy read to have FSET instruction wait INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h MOV .W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use POPC instruction to change I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h POPC FLG ; Enable interrupts

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21.3 Notes on Timers

21.3.1 Notes on Timer RA

• Timer RA stops counting after reset. Set the value to timer RA and timer RA prescaler before the count starts.
• Even if the prescaler and timer RA is read out in 16-bit units, these registers are read by 1 byte in the MCU. Consequently, the timer value may be updated during the period these two registers are being read.
• In pulse width measurement mode and pulse period measurement mode, the TEDGF and TUNDF bits in the TRACR register can be set to 0 by writing 0 to th ese bits by a program. However, these bits remain unchanged when 1 is written. When using the READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 alth ough these bits are set to 1 while the instruction is executed. At the time, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
• When changing to pulse width measurement mode and pulse period measurement mode from other mode, the contents of the TEDGF and TUNDF bits are in determinate. Write 0 to the TEDGF and TUNDF bits before the count starts.
• The TEDGF bit may be set to 1 by timer RA prescaler underflow which is generated for the first time since the count starts.
• When using the pulse peri od measurement mode, leave two periods or more of timer RA prescaler immediately after count starts, and set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1 (count starts) while the count stops. During this time, do not access re gisters associated with timer RA (1) other than the TCSTF bit. Timer RA starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count). The TCSTF bit retains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is performing. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA (1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, TRA
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval.

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21.3.2 Notes on Timer RB

• Timer RB stops counting after reset. Set the value to timer RB and timer RB prescaler before the count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read by 1 byte in the MCU. Consequently, the timer value may be updated during the period these two registers are being read.
• In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the TRBOCR register to 1 (stops one-shot), the timer reload s the value of reload register and stops. Therefore, read the timer count value in programmable one-shot generation mode and programmable wait one-shot generation mode before the timer stops.
• The TCSTF bit retains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1 (count starts) while the count stops. During this time, do not access registers associated with timer RB(1) other than the TCSTF bit. The TCSTF bit retains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is performing. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, TRBPR
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the T RBOCR register, the value of the TOSSTF bit changes after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the period between when the TOSSP bit is written to 1 and when th e TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1.

21.3.2.1 Timer mode

The following workaround should be performed in timer mode. To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points:

• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, al low three or more cycles of the prescaler underflow for each write interval.

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21.3.2.2 Programmable waveform generation mode

The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during c ount operation (TCSTF bit is set to 1), note the following points:

• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. (2) To change registers TRBPRE and TRBPR during coun t operation (TCSTF bit is set to 1), synchronize the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period A shown in Figures 21.2 and 21.3. The following shows the detailed workaround examples.
• Workaround example (a): As shown in Figure 21.2, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These write operations must be completed by the beginning of period A. Figure 21.2 Workaround Example (a) When Timer RB Interrupt is Used TRBO pin output Count source/ prescaler underflow signal Primary period Period A IR bit in TRBIC register Secondary period (b) Interrupt sequence Instruction in interrupt routine Interrupt request is acknowledged(a) Interrupt request is generated Ensure sufficient time Set the secondary and then the primary register immediately (a) Period between interrupt request generation and the completion of execution of an instruction. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 20 cycles. 21 cycles for address match and single-step interrupts.

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• Workaround example (b): As shown in Figure 21.3 detect the start of the pr imary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A. If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is set to 0 (input mode), the read value indicates the TRBO pin output value. Figure 21.3 Workaround Example (b) When TRBO Pin Output Value is Read (3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case, registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.

21.3.2.3 Programmable one-shot generation mode

The following two workarounds should be performed in programmable one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during c ount operation (TCSTF bit is set to 1), note the following points:

• When the TRBPRE register is written continuously du ring count operation (TCSTF bit is set to 1), allow three or more cycles of the count source for each write interval.
• When the TRBPR register is writte n continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. TRBO pin output Count source/ prescaler underflow signal Primary period Period A Read value of the port register’s bit corresponding to the TRBO pin (when the bit in the port direction register is set to 0) Secondary period (i) The TRBO output inversion is detected at the end of the secondary period. Ensure sufficient time Upon detecting (i), set the secondary and then the primary register immediately. (ii) (iii)

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21.3.2.4 Programmable wait one-shot generation mode

The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during c ount operation (TCSTF bit is set to 1), note the following points:

• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously, al low three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. (3) Set registers TRBSC and TRBP R using the following procedure. (a) To use “INT0 pin one-shot trigger enabled” as the count start condition Set the TRBSC register an d then the TRBPR register. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before trigger input from the INT0 pin. (b) To use “writing 1 to TOSST bit” as the start condition Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the TOSST bit.

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21.3.3 Notes on Timer RD

21.3.3.1 TRDSTR Register

• Set the TRDSTR register using the MOV instruction.
• When the CSELi (i = 0 or 1) is set to 0 (the co unt stops at compare matc h of registers TRDi and TRDGRAi), the count does not stop and the TSTARTi b it remains unchanged even if 0 (count stops) is written to the TSTARTi bit. Therefore, set the TSTARTi bit to 0 to change othe r bits without changing the TSTARTi bit when the CSELi bit is set to 0. To stop counting by a program, set the TSTARTi bit to 0 after setting the CSELi bit to 1. Although the CSELi bit is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 instruction), the count cannot be stopped.
• Table 21.1 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops to use the TRDIOji pin with the timer RD output.

21.3.3.2 TRDi Register (i = 0 or 1)

• When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register is set to 1 (count starts), avoid to overlap with the timing to set the TRDi register to 0000h, and then write. When the timing to set the TRDi register to 0000h overlaps with the timing to write the value to the TRDi register, the value is not written and the TRDi register is set to 0000h. These precautions are applicable when selecting the following by the CCLR2 to CCLR0 bits in the TRDCRi register. - 001b (clear by the TRDi register at the compare match with the TRDGRAi register) - 010b (clear by the TRDi register at the compare match with the TRDGRBi register.) - 011b (synchronous clear) - 101b (clear by the TRDi register at the compare match with the TRDGRCi register.) - 110b (clear by the TRDi register at the compare match with the TRDGRDi register.)
• When writing the value to the TRDi register and continuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program Example MOV .W #XXXXh, TRD0 ;Writing JMP.B L1 ;JMP.B L1: MOV .W TRD0,DATA ;Reading

21.3.3.3 TRDSRi Regi ster (i = 0 or 1)

When writing the value to the TRDSRi register and con tinuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program Example MOV .B #XXh, TRDSR0 ;Writing JMP.B L1 ;JMP.B L1: MOV .B TRDSR0,DA TA ;Reading Table 21.1 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops Count Stop TRDIOji Pin Output when Count Stops When the CSELi bit is set to 1, set the TSTARTi bit to 0 and the count stops. Hold the output level immediately before the count stops. When the CSELi bit is set to 0, the count stops at compare match of registers TRDi and TRDGRAi. Hold the output level after output changes by compare match.

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21.3.3.4 Count Source Switch

• When switching the count source, switch it after the count stops. Change procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change the TCK2 to TCK0 bits in the TRDCRi register.
• When changing the count source fr om fOCO40M to the other and stopping fOCO40M, wait 2 cycles or more of f1 after setting the clock switch, and then stop fOCO40M. Change procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change the TCK2 to TCK0 bits in the TRDCRi register. (3) Wait 2 cycles or more of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator stops).

21.3.3.5 Input Capture Function

• Set the pulse width of input capture si gnal to 3 cycles or more of the Timer RD operation clock. (Refer to Table 14.11 Timer RD Operation Clocks.)
• The value in the TRDi register is transferred to the TRDGRji register after 2 to 3 cycles of the Timer RD operation clock since the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C or D) (no digital filter).

21.3.3.6 Reset Synchronous PWM Mode

• When reset synchronous PWM mode is used for motor control, use it with OLS0 = OLS1.
• Set to reset synchronous PWM mode in the following procedure: Change procedure (1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops). (2) Set the CMD1 to CMD0 bits in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode). (3) Set the CMD1 to CMD0 bits to 01b (reset synchronous PWM mode). (4) Set the registers associated with other Timer RD again.

21.3.3.7 Complementary PWM Mode

• When complementary PWM mode is used for motor control, use it with OLS0 = OLS1.
• Change the CMD1 to CMD0 bits in the TRDFCR register in the following procedure. Change procedure: When setting to complementary PWM mode (including re-set), or changing the transfer timing from the buffer register to the general register in complementary PWM mode. (1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops). (2) Set the CMD1 to CMD0 bits in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode) (3) Set the DMD1 to CMD0 bits to 10b or 11b (complementary PWM mode). (4) Set the registers associated with other Timer RD again. Change procedure: When stopping complementary PWM mode (1) Set both the TSTART0 and CSEL1 bits in the TRDSTR register to 0 (count stops). (2) Set the CMD1 to CMD bits to 00b (other than reset synchronous PWM mode, complementary PWM mode)
• Do not write to the TRDGRA0, TRDGRB0, TRDGRA1 and TRDGRB1 registers during operation. When changing the PWM waveform , transfer the value written to the TRDGRD0, TRDGRC1 and TRDGRD1 registers to the TRDGRB0, TRDGRA1 and TRDGRB1 registers using the buffer operation. However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register). The PWM period cannot be changed.

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• When the value in the TRDGRA0 register is assumed as m, the TRD0 register counts order of m - 1, m, m + 1, m, m - 1 when changing from increment to decrement. When changing from m to m + 1, the IMFA bit is set to 1. Also, the CMD1 to CMD0 bits in the TRDFCR register are set to 11b (complementary PWM mode, bu ffer data transferred by the compare match in the TRD0 and TRDGRA0 registers), the content in the buffer register (TRDGRD0, TRDGRC1, TRDGRD1) is transferred to the general register (TRDGRB0, TRDGRA1, TRDGRB1). For the order of m + 1, m, m - 1 operation, the IMFA bit remains unchanged and data are not transferred to the register such as the TRDGRA0 register. Figure 21.4 Operation at Compare Match between Registers TRD0 and TRDGRA0 in Complementary PWM Mode No change IMFA bit in TRDSR0 register Transferred from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register Count value in TRD0 register Setting value in TRDGRA0 register m m + 1 Set to 0 by a program Not transferred from buffer register When the CMD1 to CMD0 bits in the TRDFCR register are set to 11b. (Transfer from the buffer register to the general register at the compare match of the TRD0 register and TRDGRA0 register)

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• The TRD1 register counts the order of 1, 0, FFFFh, 0, 1 when changing from decrement to increment. The UDF bit is set to 1 by the order of 1, 0, FFFFh operation. Also, when the CMD1 to CMD0 bits in the TRDFCR register are set to 10b (c omplementary PWM mode, buffer data transferred by the underflow in the TRD1 register), the content in the buffer re gister (TRDGRD0, TRDGRC1, TRDGRD1) is transferred to the general register (TRDGRB0 , TRDGRA1, TRDGRB1). For the orde r of FFFFh, 0, 1 operation, data are not transferred to the register such as the TRDG RB0 register. Also, at this time, the OVF bit remains unchanged. Figure 21.5 Operation When TRD1 Register Underflows in Complementary PWM Mode No change UDF bit in TRDSR0 register Transferred from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register Count value in TRD0 register Set to 0 by a program Not transferred from buffer register When the CMD1 to CMD0 bits in the TRDFCR register are set to 10b. (Transfer from the buffer register to the general register when the TRD1 register underflows) OVF bit in TRDSR0 register FFFFh

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• Select with the CMD1 to CMD0 bits for the data transfer timing from the buffer register to the general register. However, transfer with the following timing in spite of the value of the CMD1 to CMD0 bits for the following cases: Value in buffer register ≥ Value in TRDGRA0 register: Transfer at the underflow in the TRD1 register. And then, when setting the buffer register to 0001h or above and the smaller value than the one in the TRDGRA0 register, and the TRD1 register underflows in the fist time after setting, the value is transferred to the general register. After that, transfer the value with the timing selected by the CMD1 to CMD0 bits. Figure 21.6 Operation When Value in Buffer Register ≥ Value in TRDGRA0 Register in Complementary PWM Mode 0000h TRDGRD0 register TRDIOB0 output n3n2 m + 1 n2 n1 n3n2 n2 n1n1TRDGRB0 register Transfer Transfer by underflow in TRD1 register because of n3 > m Transfer by underflow in TRD1 register because of first setting to n2 < m TRDIOD0 output m: Setting Value in TRDGRA0 Register The above applies to the following conditions:
• The CMD1 to CMD0 bits in the TRDFCR register are set to 11b. (Data in the buffer register is transferred at the com pare match in the TRD0 and TRDGRA0 registers in complementary PWM mode.)
• Both the OSL0 and OLS1 bits in the TRDFCR are set to 1. (active ‘H” for normal-phase and counter-phase) Count value in TRD0 register Count value in TRD1 register Transfer with timing set by CMD1 to CMD0 bits Transfer with timing set by CMD1 to CMD0 bits Transfer Transfer Transfer

R8C/20 Group, R8C/21 Group 21. Usage Notes Rev.2.00 Aug 27, 2008 Page 442 of 458 REJ09B0250-0200 When the value in the buffer register is set to 0000h: Transfer by the compare match in the TRD0 and TRDGRA0 registers. And then, when setting the buffer register to 0001h or above and the smaller value than the one in the TRDGRA0 register, and the compare match in the TR D0 and TRDGRA0 registers in the fist time after setting, the value is transferred to the general register. After that, transfer the value with the timing selected by the CMD1 to CMD0 bits. Figure 21.7 Operation When Value in Buffer Regi ster Is Set to 0000h in Complementary PWM Mode

21.3.3.8 Count Source fOCO40M

The count source fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V . For supply voltage other than that, do not set bits TCK2 to TCK0 in registers TR DCR0 and TRDCR to 110b (select fOCO40M as the count source). 0000h TRDGRD0 register TRDIOB0 output m + 1 n 2 0000h n1 0000hn1 n1n2TRDGRB0 register Transfer Transfer by compare match in TRD0 and TRDGRA0 registers because content in TRDGRD0 register is set to 0000h. Transfer by compare match in TRD0 and TRDGRA0 registers because of first setting to 0001h ≤ n1 < m Transfer with timing set by CMD1 to CMD0 bits TRDIOD0 output m: Setting Value in TRDGRA0 Register The above applies to the following conditions:

• The CMD1 to CMD0 bits in the TRDFCR register are set to 10b. (Data in the buffer register is transferred at the underflow in the TRD1 register in PWM mode.)
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to “1” (active “H” for normal-phase and counter-phase). Count value in TRD0 register Count value in TRD1 register Transfer with timing set by CMD1 to CMD0 bits Transfer Transfer Transfer

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21.3.4 Notes on Timer RE

21.3.4.1 Starting and Stopping Count

Timer RE has the TSTART bit for instructing count start or stop, and the TCSTF bit which indicates count start or stop. The TSTART and TCSTF bits are in the TRECR1 register. Timer RE starts counting when setting the TSTART bit to 1 (count starts) and the TCSTF bit is set to 1 (count starts). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with Timer RE (1) other than the TCSTF bit. Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0 (count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF bit. NOTE: 1. Registers associated with Timer RE:TRESEC, TREMIN, TRECR1, TRECR2, TRECSR

21.3.4.2 Register Setting

Write to the following registers or bits while timer RE stops.

• TRESEC and TRECR2 registers
• The INT bit in TRECR1 register
• RCS0 to RCS2 bits in TRECSR register The state while Timer RE stops is indicated as the state where the TSTART and TCSTF bits in the TRECR1 register are set to 0 (timer RE stops). Also, set all above-mentioned registers and bits (immedia tely before timer RE count starts) before setting the TRECR2 register.

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21.4 Notes on Serial Interface

• When reading data from the UiRB (i = 0 or 1) register even in the clock asynchronous serial I/O mode or in the clock synchronous serial I/O mode. Ensure to read data in 16-bit unit. When the high-order byte of the UiRB register is read, the PER and FER bits in the UiRB register and the RI bit in the UiC1 register are set to 0. To check receive errors, read the UiRB register and then use the read data. Example (when reading receive buffer register): MOV .W 00A6H,R0 ; Read the U0RB register
• When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data length, write data high-order byte first, then low-order byte in 8-bit units. Example (when reading transmit buffer register): MOV .B #XXH,00A3H ; Write the high-order byte of U0TB register MOV .B #XXH,00A2H ; Write the low-order byte of U0TB register

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21.5 Clock Synchronous Serial Interface

21.5.1 Notes on Clock Synchronous Serial I/O with Chip Select

Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use the clock synchronous serial I/O with chip select.

21.5.2 Notes on I 2C Bus Interface

Set the IICSEL bit in the PMR register to 1 (select I2C bus interface function) to use I2C bus interface.

21.5.2.1 Multimaster Operation

The following actions must be performed to use the I2C bus interface in multimaster operation.

• Transfer rate Set the transfer rate by 1/1.8 or faster than the fastes t rate of the other masters. For example, if the fastest transfer rate of the other masters is set to 400 kbps, the I 2C-bus transfer rate in this MCU should be set to 223 kbps (= 400/1.18) or more.
• Bits MST and TRS in the ICCR1 register setting (a) Use the MOV instruction to set bits MST and TRS. (b) When arbitration is lost, confirm the contents of b its MST and TRS. If the contents are other than the MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0 again.

21.5.2.2 Master Receive Mode

Either of the following actions must be performed to use the I2C bus interface in master receive mode. (a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register before the rising edge of the 8th clock. (b) In master receive mode, set the RCVD bit in th e ICCR1 register to 1 (disables the next receive operation) to perform 1-byte communications.

R8C/20 Group, R8C/21 Group 21. Usage Notes Rev.2.00 Aug 27, 2008 Page 446 of 458 REJ09B0250-0200

21.6 Notes on Hardware LIN

For the time-out processing of the head er and response fields, use another timer to measure the duration of time with respect to a Synch Break detection interrupt as the starting point.

R8C/20 Group, R8C/21 Group 21. Usage Notes Rev.2.00 Aug 27, 2008 Page 447 of 458 REJ09B0250-0200

21.7 Notes on A/D Converter

• Write to each bit (other than bit 6) in the ADCON0 register, each b it in the ADCON1 register, or the SMP bit in the ADCON2 register when the A/D conversion stops (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from 0 (VREF no t connected) to 1 (VREF connected), wait for at least 1 µs or longer before the A/D conversion starts.
• When changing A/D operating mode, select an analog input pin again.
• When using in one-shot mode. Ensure that the A/D c onversion is completed and read the AD register. The IR bit in the ADIC register or the ADST bit in the AD CON0 register can determine whether the A/D conversion is completed.
• When using the repeat mode, select the frequency of the A/D converter operating clock φAD or more for the CPU clock during A/D conversion. Do not select the fOCO-F for the φAD.
• If setting the ADST bit in the ADCON0 register to 0 (A/D conversion stops) by a program and the A/D conversion is forcibly terminated during the A/D c onversion operation, the conversion result of the A/D converter will be indeterminate. If the ADST bit is set to 0 by a program, do not use the value of AD register.
• Connect 0.1 µF capacitor between the P4_2/VREF pin and A VSS pin.
• Do not enter stop mode during A/D conversion.
• Do not enter wait mode when the CM02 bit in the CM0 re gister is set to 1 (peripheral function clock stops in wait mode) during A/D conversion.

R8C/20 Group, R8C/21 Group 21. Usage Notes Rev.2.00 Aug 27, 2008 Page 448 of 458 REJ09B0250-0200

21.8 Notes on Flash Memory

21.8.1 CPU Rewrite Mode

21.8.1.1 Operating Speed

Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit in the CM0 register and the CM16 to CM17 bits in the CM1 register. This usage note is not needed for EW1 mode.

21.8.1.2 Prohibited Instructions

The following instructions cannot be used in EW0 mode because the flash memory inte rnal data is referenced: UND, INTO, and BRK instructions.

21.8.1.3 Interrupts

Table 21.2 lists the EW0 Mode Interrupts and Table 21.3 lists the EW1 Mode Interrupts. NOTES: 1. Do not use the address match interrupt while the command is executed because the vector of the address match interrupt is allocated on ROM. 2. Do not use the non-maskable interrupt while bl ock 0 is automatically erased because the fixed vector is allocated block 0. Table 21.2 EW0 Mode Interrupts Mode Status When Maskable Interrupt Request is Acknowledged When Watchdog Timer, Oscillation Stop Detection and Voltage Monitor 2 Interrupt Request are Acknowledged EW0 During automatic erasing Any interrupt can be used by allocating a vector to RAM Once an interrupt request is acknowledged, the auto-programming or auto-erasing is forcibly stopped immediately and resets the flash memory. An interrupt process starts after the fixed period and the flash memory restarts. Since the block during the auto- erasing or the address during the auto- programming is forcibly stopped, the normal value may not be read. Execute the auto-erasing again and ensure the auto- erasing is completed normally. Since the watchdog timer does not stop during the command operation, the interrupt request may be generated. Reset the watchdog timer regularly. Automatic writing

R8C/20 Group, R8C/21 Group 21. Usage Notes Rev.2.00 Aug 27, 2008 Page 449 of 458 REJ09B0250-0200 NOTES: 1. Do not use the address match interrupt while the command is executed because the vector of the address match interrupt is allocated on ROM. 2. Do not use the non-maskable interrupt while bl ock 0 is automatically erased because the fixed vector is allocated block 0.

21.8.1.4 How to Access

Write 0 to the corresponding bits before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt between writing 0 and 1.

21.8.1.5 Rewriting User ROM Area

In EW0 mode, if the power supply voltage drops while rewriting any block in which the rewrite control program is stored, the flash memory may not be able to be rewritten because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode.

21.8.1.6 Program

Do not write additions to the already programmed address. Table 21.3 EW1 Mode Interrupts Mode Status When Maskable Interrupt Request is Acknowledged When Watchdog Timer, Oscillation Stop Detection and Voltage Monitor 2 Interrupt Request are Acknowledged EW1 During automatic erasing (erase- suspend function is enabled) The auto-erasing is suspended after td(SR-SUS) and the interrupt process is executed. The auto-erasing can be restarted by setting the FMR41 bit in the FMR4 register to 0 (erase restart) after the interrupt process completes. Once an interrupt request is acknowledged, the auto- programming or auto-erasing is forcibly stopped immediately and resets the flash memory. An interrupt process starts after the fixed period and the flash memory restarts. Since the block during the auto-erasing or the address during the auto- programming is forcibly stopped, the normal value may not be read. Execute the auto-erasing again and ensure the auto-erasing is completed normally. Since the watchdog timer does not stop during the command operation, the interrupt request may be generated. Reset the watchdog timer regularly using the erase-suspend function. During automatic erasing (erase- suspend function is disabled) The auto-erasing has a priority and the interrupt request acknowledgement is waited. The interrupt process is executed after the auto-erasing completes. During automatic programming (program suspend function enabled) The auto-programming is suspended after td(SR-SUS) and the interrupt process is executed. The auto- programming can be restarted by setting the FMR42 bit in the FMR4 register to 0 (program restart) after the interrupt process completes. Auto programming (program suspend function disabled) The auto-programming has a priority and the interrupt request acknowledgement is waited. The interrupt process is executed after the auto- programming completes.

R8C/20 Group, R8C/21 Group 21. Usage Notes Rev.2.00 Aug 27, 2008 Page 450 of 458 REJ09B0250-0200

21.8.1.7 Entering Stop Mode or Wait Mode

Do not enter stop mode or wait mode during erase-suspend.

R8C/20 Group, R8C/21 Group 21. Usage Notes Rev.2.00 Aug 27, 2008 Page 451 of 458 REJ09B0250-0200

21.9 Notes on Noise

21.9.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a

Countermeasure against Noise and Latch-up Connect the bypass capacitor (at least 0.1 µF) using the shortest and thickest as possible.

21.9.2 Countermeasures against Noise Er ror of Port Control Registers

During severe noise testing, mainly power supply system noise, and introduction of external noise, the data of port related registers may be changed. As a firmware countermeasure, it is recommended to periodically reset the port registers, port direction registers and pull-up control registers. However, examine fully before introducing the reset routine as conflicts may be created between this reset routine and interrupt routines.

R8C/20 Group, R8C/21 Group 22. Notes on On-Chip Debugger Rev.2.00 Aug 27, 2008 Page 452 of 458 REJ09B0250-0200 22. Notes on On-Chip Debugger When using the on-chip debugger to develop the R8C/20 and R8C/21 Groups program and debug, pay the following attention. (1) Do not access the related UART1 registers. (2) Some of the user flash memory and RAM areas ar e used by the on-ship debugger. These areas cannot be accessed by the user. Refer to the on-chip debugger manual for which areas are used. (3) Do not set the address match interrupt (the register s of AIER, RMAD0, RMAD1 and the fixed vector tables) in a user system. (4) Do not use the BRK instruction in a user system. Connecting and using the on-chip debugger has some peculiar restrictions. Refer to each on-chip debugger manual for on-chip debugger details.

R8C/20 Group, R8C/21 Group 23. Notes on Emulator Debugger Rev.2.00 Aug 27, 2008 Page 453 of 458 REJ09B0250-0200 23. Notes on Emulator Debugger When using the emulator debugger to develop the R8C/20 and R8C/21 Groups program and debug, pay the following attention. (1) Do not use the following flash memory areas becau se these areas are used for the emulator debugger. When debugging of these areas, intensive evaluation on the real chip is required. ROM 128 KB Product (R5F2120CJFP, R5F2120CKFP, R5F2121CJFP, R5F2121CKFP) addresses 20000h to 23FFFh Connecting and using the emulator debugg er has some peculiar restrictions. Re fer to each emulator debugger manual for emulator debugger details.

R8C/20 Group, R8C/21 Group Ap pendix 1. Package Dimensions Rev.2.00 Aug 27, 2008 Page 454 of 458 REJ09B0250-0200 Appendix 1. Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. Terminal cross section bp c DO NOT INCLUDE MOLD FLASH. NOTE) DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Detail F c A L A1 A2 F 36 25 121 x Index mark y ZE ZD bpe HE HD D E Previous CodeJEITA Package Code RENESAS Code PLQP0048KB-A 48P6Q-A MASS[Typ.] 0.2gP-LQFP48-7x7-0.50 1.0 0.125 0.20 0.75 0.75 0.08 0.200.1450.09 0.270.220.17 MaxNomMin Dimension in Millimeters Symbol Reference 7.17.06.9D 7.17.06.9E 1.4A2 9.29.08.8 9.29.08.8 1.7A 0.20.10 0.650.50.35L x 8°0° c 0.5e 0.10y HD HE bp ZD ZE

R8C/20 Group, R8C/21 Group Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator Rev.2.00 Aug 27, 2008 Page 455 of 458 REJ09B0250-0200 Appendix 2. Connection Examples b etween Serial Writer and On-Chip Debugging Emulator Appendix Figure 2.1 shows the Connection Example with M 16C Flash Starter (M3A-0806) and Appendix Figure 2.2 shows the Connection Example with E8 Emulator (R0E000080KCE00). Appendix Figure 2.1 Connection Example with M16C Flash Starter (M3A-0806) Appendix Figure 2.2 Connection Example with E8 Emulator (R0E000080KCE00) VSS VCC RXD 4

7 VSS

1 VCC

(M3A-0806) RXD TXD TXD RESET R8C/20 Group, R8C/21 Group MODE NOTE: 1. An oscillation circuit must be connected, even when operating with the on-chip oscillator clock. Connect oscillation circuit(1) Emulator E8 (R0E000080KCE00) MODE 4.7 kO ± 10% RESET12 VSS

7 MODE

R8C/20 Group, R8C/21 Group VSS VCC NOTE: 1. No need to connect an oscillation circuit when operating with the on-chip oscillator clock. Connect oscillation circuit(1) 4.7 kO or more User logic Open-collector buffer

R8C/20 Group, R8C/21 Group Appendix 3. Example of Oscillation Evaluation Circuit Rev.2.00 Aug 27, 2008 Page 456 of 458 REJ09B0250-0200 Appendix 3. Example of Osc illation Evaluation Circuit Appendix Figure 3.1 shows the Example of Oscillation Evaluation Circuit. Appendix Figure 3.1 Example of Oscillation Evaluation Circuit VSSConnect oscillation circuit VCC RESET R8C/20 Group, R8C/21 Group NOTE: 1. After reset, the XIN clock stops. Write a program to oscillate the XIN clock.

R8C/20 Group, R8C/21 Group Index Rev.2.00 Aug 27, 2008 Page 457 of 458 REJ09B0250-0200 Index [ A ] [ C ] [ F ] [ I ] [ K ] [ L ] [ O ] [ P ] [ R ] [ S ] [ T ]

R8C/20 Group, R8C/21 Group Index Rev.2.00 Aug 27, 2008 Page 458 of 458 REJ09B0250-0200 [ U ] [ V ] [ W ]

R8C/20 Group, R8C/21 Group Hardware Manual Rev. Date

Description

0.10 Sep 29, 2005 − First Edition issued

0.20 Jun 28, 2006 All pages • Symbol name revised.

• Bit Symbol name revised. “TSTOP0” → “CSEL0” in the TRDSTR register “TSTOP1” → “CSEL1” in the TRDSTR register “TPSC0” → “TCK0” in the TRDCRi register (i=0 or 1) “TPSC1” → “TCK1” in the TRDCRi register (i=0 or 1) “TPSC2” → “TCK2” in the TRDCRi register (i=0 or 1)
• Pin name revised.
• Register name revised. “Timer RE Comparison Reigster” → “Timer RE Compare Data Register” 1 1. Overview, on the 5th and 6th lines; “data flash” added. 2 Table 1.1 Functions and Specific ations for R8C/20 Group revised 3 Table 1.2 Functions and Specific ations for R8C/21 Group revised 4 Figure 1.1 Block Diagram; “System Clock Generation” → “System clock generation circuit” revised 5 Table 1.3 Product Information of R8C/20 Group revised. Figure 1.2 Type Number, Memory Size, and Package of R8C/20 Group revised. 6 Table 1.4 Product Information of R8C/21 Group revised Figure 1.3 Type Number, Memory Size, and Package of R8C/21 Group revised. 7 Figure 1.4 Pin Assignments (Top View); “TCLK” → “TRDCLK” revised 8 Table 1.5 Pin Functions; “Analog Power Supply Input” revised 9 Table 1.6 Pin Name Information by Pin Number revised. NOTE added. 11 2.8.1 Carry Flag (C)

“2.8.5 Rgister Bank Select Flag (B Flag)” → “2.8.5 Register Bank Select Flag (B)” revised.

REVISION HISTORY

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 0.20 Jun 28, 2006 12 2.8.7 Interrupt Enable Flag (I) “2.8.7 Interrupt Enable Flag (I Flag)” → “2.8.7 Interrupt Enable Flag (I)” revised. “2.8.8 Stack Pointer Select Flag (U Flag)” → “2.8.8 Stack Pointer Select Flag (U)” revised. 13 Figure 3.1 Memory Map of R8C/20 Group; “Internal ROM” → “Internal ROM (program ROM)” revised Address “1ZZZZh” added. NOTE revised. Part Number revised. 14 Figure 3.2 Memory Map of R8C/21 Group; “Internal ROM” → “Internal ROM (program ROM)” revised. “Data area” → “Data flash” “program area” → “program ROM” revised Address “1ZZZZh” added. NOTE2 added. Part Number revised. 15 Table 4.1 SFR Information (1); 001Ch: 00h → 00h, 1000000b 0024h: TBD → Value when shipping NOTES revised. 24 Figure 5.4 OFS Register, Fu nction of the LVD1ON bit; “~ after Hardware reset” → “~ after reset” revised. NOTES revised. 25 5.1.1 When Power Supply is Stable (2) revised. 5.1.2 Power On (4) revised. 26 Figure 5.5 Example of Hardware Reset Circuit and Operation and Figure

5.6 Example of Hardware Reset Circuit (Usage Example of External

Supply Voltage Detection Circuit) and Operation revised. 27 5.2 Power-On Reset Function, on the 2nd line; “When a capacitor is ~ or more.” added. Figure 5.7 Example of Power-On Reset Circuit and Operation revised. NOTES revised. 28 5.3 Voltage Monitor 1 Reset(1); on the 8th line; The LVD1ON bit in the OFS register can select to~ “after a reset” added. 29 to 62 “6. Programmable I/O Ports” → “6. Voltage Detection Circuit” and “7. Voltage Detection Circuit” → “7. Programmable I/O Ports” revised. 32 Figure 6.4 Registers VCA1 and VCA2; VCA2 register revised. 33 Figure 6.5 VW1C Register revised. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 0.20 Jun 28, 2006 35 6.1 VCC Input Voltage; “6.1 Monitoring VCC Input Voltage” → “6.1 VCC Input Voltage” revised. 42 Figure 7.2 Configuration of Pr ogrammable I/O Ports (2) revised. 43 Figure 7.3 Configuration of Pr ogrammable I/O Ports (3) revised. 45 Figure 7.5 Configuration of Pr ogrammable I/O Ports (5) revised. 47 Figure 7.7 Configuration of Pr ogrammable I/O Ports (7) revised. 49 Figure 7.9 PDi (i = 0 to 4 and 6) Registers; NOTE3 added. Figure 7.10 Pi (i = 0 to 4 and 6) Registers; P6 Address “00EEh” → “00ECh” corrected. 51 to 61 7.4 Port Settings added. 63 8.1 Processor Modes “8.1 Type of Processor Mode” → “8.1 Processor Modes” revised. 64 9. Bus revised; Table 9.2 Bus Cycles by Access Space of the R8C/21 Group added. Table 9.3 Access Unit and Bus Operations; “SFR” → “SFR, data flash” “ROM/RAM” → “ROM (program ROM), RAM” below the Table.9.3 “However, only following ~ at a time.” added. 67 Figure 10.2 CM0 Register; NOTE6 deleted. 69 Figure 10.4 OCD Register; “System clock select bet(3)” → “System clock select bet(4)” “1:Selects on-chip oscillator clock(4)” → “1:Selects on-chip oscillator clock(3)” corrected. 70 Figure 10.5 Registers FRA0 and FRA1; NOTE2 in the FRA0 register revised. 71 Figure 10.7 VCA2 Register added. 72 Figure 10.8 Examples of XIN Clock Connection Circuit; NOTE revised. 73 10.2.2 High-Speed On-Chi p Oscillator Clock, on the 3rd and 8th lines; “To use the high-speed ~ (divide-by-4 mode or more).” added. “Since the difference ~ each bit” → “Since there are ~ individual bits.” revised. 74 10.3.5 fOCO40M; “fOCO40M can be used with supply voltage VCC = 3.0 to 5.5V.” added. 75 Table 10.2 Settings and Modes of Clock Associated Bits; “-: can be 0 or 1, no change in outcome.” added. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 0.20 Jun 28, 2006 146 Table 14.8 Programmable Waveform Generation Mode Specifications, “Write to Timer” in the item; “TRAPRE” → “TRBPRE” corrected. 149 Table 14.9 Programmable One-Shot Generation Mode Specifications, “Write to Timer” in the item; “TRAPRE” → “TRBPRE” corrected. 153 Table 14.10 Programmable Wait One-Shot Generation Mode Specifications, “Write to Timer” in the item; “TRAPRE” → “TRBPRE” corrected. 157 Table 14.11 Timer RD Operation Clocks; On the 5th line below the Table 14.11; “(Pin output ~ detection)” added. 158 to 160 Table 14.12 Pin Functions TRDIOA0/TRDCLK(P2_0) Table 14.13 Pin Functions TRDIOB0(P2_1) Table 14.14 Pin Functions TRDIOC0(P2_2) Table 14.15 Pin Functions TRDIOD0(P2_3) Table 14.16 Pin Functions TRDIOA1(P2_4) Table 14.17 Pin Functions TRDIOB1(P2_5) Table 14.18 Pin Functions TRDIOC1(P2_6) Table 14.19 Pin Functions TRDIOD1(P2_7) Table 14.20 Pin Functions INT0(P4_5) added. 162 14.3.1 Mode Selection deleted Table 14.21 Count Source Selection; Selection of f1, f2, f4, f8, f32, and fOCO40M revised. Figure 14.29 Block Diagram of Count Source; “TPSC2 to TPSC0” → “TCK2 to TCK0” revised. 163 Figure 14.30 Buffer Operation in Input Capture Function revised. 164 Figure 14.31 Buffer Operation in Output Compare Function revised. On the 4th line below the Figure 14.31; “IOC2 to IOC0 bits” → “IOC2 bit” and “IOA2 to IOA0 bits” → “IOA2 bit” revised. On the 7th line below the Figure 14.31; “IOD2 to IOD0 bits” → “IOD2 bit” and “IOB2 to IOB0 bits” → “IOB2 bit” revised. On the 8th line below the Figure 14.31; “Bits IMFC ~ capture function” added. 165 Below the Figure 14.32 Synchronous Operation; “For the synchronous ~ register=110b)” deleted. 166 14.3.4 Pulse Output Forced Cutoff, on the 13th line; On the 15th line; “P4_5 bit in the P4D register” → “PD4_5 bit in the PD4 register” corrected. On the 2nd line from the bottom; “According to ~ of interrupts” added. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 0.20 Jun 28, 2006 168 14.3.5 Input Ca pture Function, on the 5th line; “The TRDGRA0 register ~ trigger input.” added. Figure 14.34 Block Diagram of Input Capture Function; NOTES revised. 169 Table 14.23 Input Capture Func tion Specifications revised. 170 Figure 14.35 Registers TRDSTR an d TRDMR in Input Capture Function; The TRDSTR register revised. 171 Figure 14.36 TRDPMR Register in Input Capture Function revised. 172 Figure 14.37 TRDFCR Register in Input Capture Function revised. 174 Figure 14.39 Registers TRDCR0 to TRDCR1 in Input Capture Function revised. 175 Figure 14.40 Registers TRDIORA0 to TRDIORA1 in Input Capture Function revised. 176 Figure 14.41 Registers TRDIORC0 to TRDIORC1 in Input Capture Function revised. 177 Figure 14.42 Registers TRDSR0 to TRDSR1 in Input Capture Function revised. 183 Table 14.25 Output Compare Functi on Specifications, on the 5 to 6th lines from the bottom; “TRCIOAi” → “TRDIOAi” and “TRCIOBi” → “TRDIOBi” corrected. 184 Figure 14.49 Registers TRDSTR and TRDMR in Output Compare Function revised. 185 Figure 14.50 TRDPMR Register in Output Compare Function revised. 186 Figure 14.51 TRDFCR Register in Output Compare Function revised. 187 Figure 14.52 Registers TRDOER1 to TRDOER2 in Output Compare Function; NOTE in the TRDOER2 register added. 189 Figure 14.54 Registers TRDCR0 to TRDCR1 in Output Compare Function revised. 190 Figure 14.55 Registers TRDIORA0 to TRDIORA1 in Output Compare Function revised. 191 Figure 14.56 Registers TRDIORC0 to TRDIORC1 in Output Compare Function revised. 192 Figure 14.57 Registers TRDSR0 to TRDSR1 in Output Compare Function revised. 200 Figure 14.65 TRDSTR Register in PWM Mode revised 201 Figure 14.66 Registers TRDMR and TRDPMR in PWM Mode revised 202 Figure 14.67 TRDFCR Regist er in PWM Mode revised 203 Figure 14.68 Registers TRDOER1 to TRDOER2 in PWM Mode; NOTE in the TRDOER2 register added. 204 Figure 14.69 Registers TRDOCR and TRDCR0 to TRDCR1 in PWM Mode revised. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 0.20 Jun 28, 2006 205 Figure 14.70 Registers TRDSR0 to TRDSR1 in PWM Mode revised. 212 Table 14.29 Reset Synchronous PWM Mode Specifications revised. 213 Figure 14.78 TRDSTR Register in Reset Synchronous PWM Mode revised. 214 Figure 14.79 Registers TRDMR and TRDFCR in Reset Synchronous PWM Mode revised. 215 Figure 14.80 Registers TRDOER1 to TRDOER2 in Reset Synchronous PWM Mode; NOTE in the TRDOER2 register added. 216 Figure 14.81 TRDCR0 Register in Reset Synchronous PWM Mode revised. 217 Figure 14.82 Registers TRDSR0 to TRDSR1 in Reset Synchronous PWM Mode revised. 223 Figure 14.88 TRDSTR Register in Complementary PWM Mode revised. 224 Figure 14.89 TRDMR Register in Complementary PWM Mode revised. 225 Figure 14.90 TRDFCR Register in Complementary PWM Mode revised. 226 Figure 14.91 Registers TRDOER 1 to TRDOER2 in Complementary PWM Mode; NOTE in the TRDOER2 register added. 227 Figure 14.92 Registers TRDCR0 to TRDCR1 in Complementary PWM Mode revised. 228 Figure 14.93 Registers TRDSR0 to TRDSR1 in Complementary PWM Mode revised. 231 Below the Table 14.32; “Since values ~ (buffer register).” added. 235 Figure 14.99 Block Diagram of PWM3 Mode ; “Buffer” added. 236 Table 14.33 PWM3 Mode Specifications revised. 237 Figure 14.100 TRDSTR Register in PWM3 Mode revised. 238 Figure 14.101 Registers TRDMR and TRDFCR in PWM3 Mode revised. 239 Figure 14.102 Registers TRDOER1 to TRDOER2 in PWM3 Mode; NOTE in the TRDOER2 register added. 241 Figure 14.104 TRDCR0 Register in PWM3 Mode revised. 242 Figure 14.105 Registers TRDSR0 and TRDSR1 in PWM3 Mode added. 243 Figure 14.106 Registers TRDI ER0 and TRDIER1 in PWM3 Mode revised. 245 Table 14.34 TRDGRji Register Functions in PWM3 Mode revised. On the 4th line from the bottom; “Registers TRDGRC0, ~ (buffer register).” added. 246 Figure 14.109 Operating Example of PWM3 Mode revised. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 0.20 Jun 28, 2006 249 14.3.12 Notes on Timer RD; “14.3.13 Precautions on Timer RD” → “14.3.12 Notes on Timer RD” revised. 14.3.12.1 TRDSTR Register (i = 0 or 1) added. 250 14.3.12.6 Reset Synchronous PWM Mode revised. 14.3.12.7 Complementary PWM Mode revised. 254 14.3.13.7 PWM3 mode deleted. 14.3.12.8 Count Source fOCO40M added. 255 14.4 Timer RE, on the 3rd line; “The count source ~ timer operations.” added. 262 14.4.2 Notes on Timer RE; 267 Figure 15.5 Registers UiC0 and UiC1 (i = 0 or 1); The UiC0 register (i=0 or 1) revised. 275 Table 15.5 Registers Used and Settings for UART Mode revised. Table 15.6 I/O Pin Functions in UART Mode revised. 276 Figure 15.10 Transmit Timing in UART Mode revised. 277 Figure 15.11 Receive Timing Example in UART Mode revised. 279 15.3 Notes on Serial Interface; “15.3 Precautions on Serial Interface” → “15.3 Notes on Serial Interface” revised. 280 16. Clock Synchronous Serial Interface, on the 3rd line; “(SSU)” added. 281 16.2 Clock Synchronous Serial I/O with Chip Select (SSU); “(SSU)” added. Table 16.2 Clock Synchronous Serial I/O with Chip Select Specifications; NOTE2 deleted. 285 Figure 16.4 SSMR Register revised. 288 Figure 16.7 SSMR2 Register revised. 289 Figure 16.8 Registers SSTDR and SSRDR; NOTE in the SSTDR register revised. 290 16.2.1 Transfer Clock; 296 16.2.5.2 Data Transmission;

16.2.5.2 Data Transmission, on the 4th line from the bottom;

“When setting the ~ transmit is enabled.” deleted. 297 Figure 16.14 Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode); NOTE revised. 298 16.2.5.3 Data Reception; Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 0.20 Jun 28, 2006 300 16.2.5.4 Data Transmission/Reception; Reception” revised.

16.2.5.4 Data Transmission/Reception, on the 5th line from the bottom;

“When setting the ~ transmit is enabled.” deleted. 301 Figure 16.17 Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication Mode) revised. 304 16.2.6.2 Data Transmission;

16.2.6.2 Data Transmission, on the 9th line from the bottom;

“When setting the ~ transmit is enabled.” deleted. 306 16.2.6.3 Data Reception; 309 16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select; “16.2.8 Precautions on Clock Synchronous Serial I/O with Chip Select” → “16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select” revised. 338 Figure 16.46 Example of Register Setting in Master Transmit Mode (I2C Bus Interface Mode); “Figure 16.46 Example of Register Setting in Master Transmit Mode (Clock Synchronous Serial)” → “Figure 16.46 Example of Register Setting in Master Transmit Mode (I2C Bus Interface Mode)” revised. 339 Figure 16.47 Example of Register Setting in Master Receive Mode (I2C Bus Interface Mode); “Figure 16.47 Example of Register Setting in Master Receive Mode (Clock Synchronous Serial)” → “Figure 16.47 Example of Register Setting in Master Receive Mode (I2C Bus Interface Mode)” revised. 340 Figure 16.48 Example of Register Setting in Slave Transmit Mode (I2C Bus Interface Mode); “Figure 16.48 Example of Register Setting in Slave Transmit Mode (Clock Synchronous Serial)” → “Figure 16.48 Example of Register Setting in Slave Transmit Mode (I2C Bus Interface Mode)” revised. 341 Figure 16.49 Example of Register Setting in Slave Receive Mode (I2C Bus Interface Mode); “Figure 16.49 Example of Register Setting in Slave Receive Mode (Clock Synchronous Serial)” → “Figure 16.49 Example of Register Setting in Slave Receive Mode (I2C Bus Interface Mode)” revised. 342 16.3.8 Notes on I2O Bus Interface; “16.3.8 Precautions on I2O Bus Interface” → “16.3.8 Notes on I2O Bus Interface” revised. 343 to 385 17. Hardware LIN; “Sync” → “Synch” revised. 345 Figure 17.2 LINCR Register revised. 346 Figure 17.3 LINST Register revised. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 0.20 Jun 28, 2006 347 Figure 17.4 Typical Operation when Sending a Header Field ; “RAIC” → “TRAIC” corrected. 348 Figure 17.5 Example of Header Field Transmission Flowchart (1) revised. 349 Figure 17.6 Example of Header Field Transmission Flowchart (2) revised. 350 Figure 17.7 Typical Operation when Receiving a Header Field ; “RAIC” → “TRAIC” corrected. 351 Figure 17.8 Example of Header Field Reception Flowchart (1) revised. 352 Figure 17.9 Example of Header Field Reception Flowchart (2) revised. 353 Figure 17.10 Example of Header Field Reception Flowchart (3) revised. 354 Figure 17.11 Typical Operation when a Bus Collision is Detected ; “RAIC” → “TRAIC” corrected. 355 17.5 Interrupt Requests, on the 2nd line; “Synch Break generation competed” added. 357 Table 18.1 Performance of A/D converter revised. 358 Figure 18.1 Block Diagram of A/D Converter ; “ADGSEL” → “ADGSEL0” corrected. 361 Table 18.2 One-Shot Mode Specifications, Input pin; 367 18.3 Sample and Hold, on the 2nd and 5th lines ; “to 28 φ AD cycles ~ 10-bit resolution.” deleted. “When performing ~ the microcomputer.” deleted. 368 18.4 A/D Conversion Cycles added. 369 18.5 Internal Equivalent Circuit of Analog Input added. 370 18.6 Output Impedance of Sensor Under A/D Conversion added. 371 18.7 Notes on A/D Converter “18.7 Precautions on A/D Converter” → “18.7 Notes on A/D Converter” revised. 372 19. Flash Memory ; “19. Flash Memory Version” → “19. Flash Memory” revised. Table 19.1 Flash Memory Performance, Program and Erase Endurance; “Program Area” → “Program ROM” “Data Area” → “Data ROM” revised. 374 19.2 Memory Map, on the 4th and 5th lines ; “(program ROM)” and “(data flash)” added. Figure 19.1 Flash Memory Block Diagram for R8C/20 Group revised. 375 Figure 19.2 Flash Memory Block Diagram for R8C/21 Group revised. 376 19.3 Functions to Prevent Rewriting of Flash Memory ; “19.3 Functions to prevent Flash Memory from Rewriting” → “19.3 Functions to Prevent Rewriting of Flash Memory” revised.

19.3.2 ROM Code Protect Function, on the 5th and 7th lines;

“The ROM code ~ flash memory.” deleted. “write 0 to the ROMCR bit” → “erase the block including the OFS register” revised. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 0.20 Jun 28, 2006 377 Figure 19.4 OFS Register revised. 379 19.4.2 EW1 Mode, on the 3rd line ; “Do not execute software command ~” → “Do not execute command ~” revised. 380 19.4.2.1 FMR00 Bit, on the 1st line ; “(including suspend periods)” added. 381 19.4.2.16 FMR47 Bit revised. 382 Figure 19.5 FMR0 Register; NOTE6 added. 384 Figure 19.7 FMR4 Register; NOTES revised. 385 Figure 19.8 Timing of Suspend Operation revised. 389 19.4.3.4 Program Command, on the 5th line ; “The FMR00 bit is ~ completes.” → “When suspend function ~ auto- programming completes.” revised. 390 Figure 19.13 Program Command (When Suspend Function Enabled) added. 391 19.4.3.5 Block Erase, on the 11th line ; “The block erase ~ program suspend.” → “Do not use ~ program- suspend” revised. 392 Figure 19.15 Block Erase Command (When Erase-Suspend Function Enabled) revised. 393 Table 19.5 Status Register Bits, Value after Reset of SR7 (D7) 396 19.5 Standard Serial I/O Mode, on the 3rd line ; “Standard serial I/O ~ interface” → “There are three ~ serial I/O mode 3.” revised. Table 19.7 Pin Functions (Flash Memory Standard Serial I/O Mode 2) revised. 398 Figure 19.17 Pin Connections for Standard Serial I/O Mode 3; “Figure 19.17 Pin Connections for Standard Serial I/O Mode” → “Figure 19.17 Pin Connections for Standard Serial I/O Mode 3” revised. 399 Figure 19.18 Pin Processing in Standard Serial I/O Mode 2 added. Figure 19.19 Pin Processing in Standard Serial I/O Mode 3; “Figure 19.19 Pin Processing in Standard Serial I/O Mode” → “Figure 19.19 Pin Processing in Standard Serial I/O Mode 3” revised. 401 19.7 Notes on Flash Memory ; “19.7 Precautions on Flash Memory Version” → “19.7 Notes on Flash Memory” revised. 404 to 423 20. Electrical Characteristics revised. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 0.20 Jun 28, 2006 424 21. Usage Notes; “21. Precautions” → “21. Usage Notes” revised. 21.1.1 Stop Mode and Wait Mode revised. 21.1.3 Oscillation Circuit Constants revised. 430 21.3.3.1 TRDSTR Register (i = 0 or 1) added. 431 21.3.3.6 Reset Synchronous PWM Mode; (2) revised.

21.3.3.7 Complementary PWM Mode;

(2) revised. On the 3rd line from the bottom; “However, to write data ~ to 1 (buffer register).” added. 435 21.3.3.7 PWM3 Mode deleted. 21.3.3.8 Count Source fOCO40M added. 445 22. Notes on On-Chip Debugger; “22. Precaution for On-chip Debugger” → “22. Notes on On-Chip Debugger” revised. (2) and (3) added. 446 Appendix 1. Package Dimensions; “Diagrams shows ~ website.” added. 447 Appendix Figure 2.1 Connection Exampl e with M16C Flash Starter (M3A-0806); NOTES revised. 448 Appendix Figure 3.1 Example of Oscillation Evaluation Circuit revised.

1.00 Nov 15, 2006 All pages “Preliminary” and “Under development” deleted

2 Table 1.1 Functions and Specifications for R8C/20 Group revised. NOTE1 deleted. 3 Table 1.2 Functions and Specifications for R8C/21 Group revised. NOTE1 deleted. 5 Table 1.3 Product Information for R8C/20 Group; “R5F2120AJFP (D)”, “R5F2120CJFP (D)”, “R5F2120AKFP (D)”, “R5F2120CKFP (D)”, and NOTE added. Figure 1.2 Type Number, Memory Size, and Package of R8C/20 Group; “A: 96 KB” and “C: 128 KB” added. 6 Table 1.4 Product Information for R8C/21 Group; “R5F2121AJFP (D)”, “R5F2121CJFP (D)”, “R5F2121AKFP (D)”, “R5F2121CKFP (D)”, and NOTE added. Figure 1.3 Type Number, Memory Size, and Package of R8C/21 Group; “A: 96 KB” and “C: 128 KB” added. 13 Figure 3.1 Memory Map of R8C/20 Group revised. 14 Figure 3.2 Memory Map of R8C/21 Group revised. 15 Table 4.1 SFR Information (1)(1); NOTE8; “The CSPROINI bit in the OFS register is set to 0.” → “The CSPROINI bit in the OFS register is 0.” revised. 22 Table 5.2 Title of Table revised Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 1.00 Nov 15, 2006 23 Figure 5.4 OFS Register; NOTE2; “LVD0ON” → “LVD1ON” revised. 26 5.2 Power-On Reset Function(1); NOTE1 deleted. NOTE2 revised. Figure 5.7 Example of Power-On Reset Circuit and Operation revised. 27 5.3 Voltage Monitor 1 Reset, on the 9th line; “To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0, bits VW1C0 and VW1C6 in the VW1C register to 1, the VCA bit in the VCA2 register to 1.” added. NOTE1 deleted.

5.4 Voltage Monitor 2 Reset;

NOTE1 deleted. 28 6. Voltage Detection Circuit; NOTE1 deleted. 31 Figure 6.4 Registers VCA1 and VCA2; Voltage Detection Register 2(1) revised. NOTE5 added. 40 to 46 Figure 7.1 to Figure 7.3 Configuration of Programmable I/O Ports; NOTE1 added 48 Figure 7.9 PDi (i = 0 to 4 and 6) Registers; Bit Names revised. Figure 7.10 Pi (i = 0 to 4 and 6) Registers; Bit Names revised. 64 Table 10.1 Specifications of Clock Generation Circuit; NOTE3; “10 MHz” → “20 MHz” revised. 68 Figure 10.4 OCD Register; NOTE7; “Figure 10.12” → “Figure 10.14” corrected. 69 Figure 10.5 Registers FRA0 and FRA1; High-Speed On-Chip Oscillator Control Register 0(1); NOTE2 revised. High-Speed On-Chip Oscillator Control Register 1(1); NOTE revised. 70 Figure 10.6 FRA2 Register; High-Speed On-Chip Oscillator Control Register 2 (1) revised. NOTE3 added. Figure 10.7 VCA2 Register; Voltage Detection Register 2(1) revised. NOTE5 added. 71 Figure 10.8 Examples of XIN Clock Connection Circuit; Ceramic resonator external circuit revised. 72 10.2.2 High-Speed On-Chip Oscillator Clock; On the 4th line revised. On the2nd line from the bottom; “Adjust the amount of high-speed on-chip oscillator frequency to 40 MHz and below by setting the FRA1 register.” added. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 1.00 Nov 15, 2006 75 10.4.1.3 Low-Speed On-Chip Oscillator Mode; On the 2nd line from the bottom; “To enter wait mode from low-speed clock mode, setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled) enables lower consumption current in wait mode.” added. 76 10.4.2.4 Exiting Wait Mode; On the 13th line from the bottom; Figure 10.9 shows the Time from Wait Mode to Interrupt Routine Execution. added. 77 Figure 10.9 Time from Wait Mode to Interrupt Routine Execution revised. 78 10.4.2.5 Reducing Internal Power Consumption and Figure 10.10 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit added 79 10.4.3.3 Exiting Stop Mode, on the 4th line; “Figure 10.11 shows the Time from Stop Mode to Interrupt Routine Execution.” added. 80 Figure 10.11 Time from Stop Mode to Interrupt Routine Execution added. 81 “Figure 10.10 State Transitions in Power Control Mode” → “Figure 10.12 State Transitions in Power Control Mode” corrected. 82 10.5.1 How to Use Oscillation Stop Detection Function, on the 6th line; “Figure 10.12” → “Figure 10.14” corrected. On the 10th line; “Figure 10.11” → “Figure 10.13” corrected. 83 “Figure 10.11 ~” → “Figure 10.13 ~” corrected. 84 “Figure 10.12 ~” → “Figure 10.15 ~” corrected. 85 “10.6 Notes on Clock Generation Circuit” revised. 94 Figure 12.5 Registers INT0IC to INT3IC; NOTE3; “INTOPL” → “INTiPL” corrected. 102 Figure 12.13 INTF Register revised 114 Figure 13.2 Registers OFS and WDC; Option Function Select Register(1); NOTE2 revised. Watchdog Timer Control Register revised. 117 Table 13.3 Watchdog Timer Specifications (with Count Source Protection Mode Enabled); NOTE2; “CSPRO” → “CSPROINI” corrected. 120 Figure 14.1 Block Diagram of Timer RA revised. 121 Figure 14.2 Registers TRACR and TRAIOC revised. 122 Figure 14.3 Registers TRAMR and TRAPRE Timer RA Mode Register(1); NOTE added. Timer RA Prescaler Register; NOTE1 revised. 123 Figure 14.4 TRA Register; NOTE1 revised. 124 Table 14.2 Timer Mode Specifications; “Write to Timer” revised. Figure 14.5 TRAIOC Register in Timer Mode; NOTES deleted. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 1.00 Nov 15, 2006 221 Table 14.31 Complementary PWM Mode Specifications, on the 3rd line from the bottom; “i = 0 to 2, j = either A, B, C or D” → “i = 0 or 1, j = either A, B, C or D” corrected. 222 Figure 14.85 TRDSTR Register in Complementary PWM Mode → Figure 14.85 TRDSTR Register in Complementary PWM Mode replaced. Timer RD Start Register(1); TRD0 count start bit(4) → “TRD0 count start flag(4)” corrected. “TRD1 count start bit(5)” → “TRD1 count start flag(5)” corrected. 232 Figure 14.98 Operating Example of Complementary PWM Mode → Figure 14.95 Operating Example of Complementary PWM Mode replaced. 235 Table 14.33 PWM3 Mode Specifications, on the bottom line; “j = either A, B, C or D” → “i = 0 or 1, j = either A, B, C or D” corrected. 236 Figure 14.100 TRDSTR Register in PWM3 Mode → Figure 14.97 TRDSTR Register in PWM3 Mode replaced. Timer RD Start Register(1); “TRD0 count start bit(4)” → “TRD0 count start flag(4)” corrected. “TRD1 count start bit(5)” → “TRD1 count start flag(5)” corrected. 239 Figure 14.103 TRDOCR Register in PWM3 Mode → Figure 14.100 TRDOCR Register in PWM3 Mode replaced. NOTE2 added. 249 14.3.12.4 Count Source Switch; “count clock source” → “count source” corrected.

14.3.12.7 Complementary PWM Mode, on the bottom line;

“Do not use the TRDGRC0 register in complementary PWM mode.” deleted. 265 Figure 15.4 UiMR Register (i = 0 or 1); “Serial Interface mode select bit(2,4)” → “Serial I/O mode select bit(2,4)” corrected. 266 Figure 15.5 Registers UiC0 and UiC1 (i = 0 or 1); UARTi Transmit/Receive Control Register 1 (i = 0 or 1) revised. NOTE2 added. 279 Table 16.1 Mode Selections revised. 283 Figure 16.3 SSCRL Register; NOTE2 revised 311 Figure 16.23 External Circuit Connection Example of Pins SCL and SDA revised. 338 Figure 16.47 Example of Register Setting in Master Receive Mode (I2C Bus Interface Mode); (1) “Set the ~ master receive mode ~” → “Set the ~ master transmit mode ~” corrected. 347 Figure 17.5 Example of Header Field Transmission Flowchart (1); Hard ware LIN Clear the status flags; “~ in LINST register” → “~ in LINST register: 0” corrected. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 1.00 Nov 15, 2006 351 Figure 17.9 Example of Header Field Reception Flowchart (2); “When the SBE bit in the LINCR register is 0(Unmasked after Synch Break is detected), timer RA is usable in timer mode after the SBDCT flag in the LINST register is set to 1.” added. 352 Figure 17.10 Example of Header Field Reception Flowchart (3); “When the SBE bit in the LINCR register is 1 (Unmasked after Synch Field measurement is completed), timer RA is usable in timer mode after the SFDCT flag in the LINST register is set to 1.” added. 354 17.4.4 Hardware LIN End Processing and Figure 17.12 Example of Hardware LIN Communication Completion Flowchart added. 365 Figure 18.6 ADCON0 Register in Repeat Mode, in the Function of Frequency select bit 0; “1: Select fOCO-F” → “Do not set” revised. 369 Figure 18.10 Internal Equivalent Circuit of Analog Input; “i = 4” → “i = 12” corrected. 371 18.7 Notes on A/D Converter, on the 5th line from the bottom; “Do not select the fOCO-F for the φAD.” added. 374 19.2 Memory Map, on the 4th line from the bottom; “When rewriting the block 2 and block 3 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite enables).” added. 375 Figure 19.1 Flash Memory Block Diagram for R8C/20 Group revised. 376 Figure 19.2 Flash Memory Block Diagram for R8C/21 Group revised. 378 Figure 19.4 OFS Register; NOTE2; “LVD0ON” → “LVD1ON” and “(voltage monitor 0 reset enabled after reset)” → “voltage monitor 0 reset enabled after reset)” corrected. 379 Table 19.3 Differences between EW0 Mode and EW1 Mode; Modes After Read Status Register added. 381 19.4.2.3 FMR02 Bit; “The block 1 and block 0 do not ~” → “The block0 block1 block2, and block3 do not ~” corrected. 389 19.4.3.1 Read Array Command, on the bottom line; “In addition, the MCU enters read array mode after a reset.” added.

19.4.3.2 Read Status Register Command, on the bottom line;

“The MCU remains in read status register mode until the next read array command is written.” added. 390 Figure 19.13 Program Command (When Suspend Function Enabled) revised. NOTE3 added. 393 Figure 19.15 Block Erase Command (When Erase-Suspend Function Enabled) revised. NOTE3 added. 396 Figure 19.16 Full Status Check and Handling Procedure for Individual Errors; “FMR06 = 0?” → “FMR06 = 1?” corrected. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 1.00 Nov 15, 2006 398 Table 19.8 Pin Functions (Flash Memory Standard Serial I/O Mode 3); P4_2/VREF deleted. P4_3 or P4_5 → P4_2 to P4_5 corrected. 404 19.7.1.7 Reset Flash Memory deleted.

19.7.1.8 Entering Stop Mode or Wait Mode

→ 19.7.1.7 Entering Stop Mode or Wait Mode corrected. 405 Table 20.1 Absolute Maximum Ratings; Power dissipation revised. Table 20.2 Recommended Operating Conditions; System clock revised. 410 Table 20.8 Voltage Monitor 1 Reset Circuit Electrical Characteristics → Table

20.8 Power-on Reset Circuit, Voltage Monitor 1 Reset Circuit Electrical

Characteristics(1) replaced. Table 20.8 revised. NOTE3 added. Table 20.9 Power-on Reset Circuit Electrical Characteristics deleted. Figure 20.3 Power-on Reset Circuit Electrical Characteristics revised. 411 Table 20.10 High-Speed On-Chip Oscillator Circuit Electrical Characteristics → Table 20.9 High-Speed On-Chip Oscillator Circuit Electrical Characteristics revised. 417 Table 20.15 Electrical Characteristics (1) [VCC = 5 V] → Table 20.14 Electrical Characteristics (1) [VCC = 5 V] revised. RAM Hold Voltage, Min.; “1.8” → “2.0” corrected. 418 Table 20.16 Electrical Characteristics (2) [Vcc = 5 V] → Table 20.15 Electrical Characteristics (2) [Vcc = 5 V] revised. Wait mode revised. 421 Table 20.21 Electrical Characteristics (3) [VCC = 3 V → Table 20.20 Electrical Characteristics (3) [VCC = 3 V] revised. RAM hold voltage, Min.; “1.8” → “2.0” corrected. 422 Table 20.22 Electrical Characteristics (4) [Vcc = 3 V] → Table 20.21 Electrical Characteristics (4) [Vcc = 3 V] revised. Wait mode revised. 21.1.2 Wait Mode added. 430 21.3.2 Notes on Timer RB; “Timer RB starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).” deleted. On the 8th line from the bottom; “- If the TSTOP bit ~ stops immediately.” added. On the 6th line from the bottom; “- If 1 is written to the TOSST or TOSSP bit ~ either 0 or 1.” added. 432 21.3.3.4 Count Source Switch; “count clock source” → “count source.” corrected. 442 21.7 Notes on A/D Converter; On the 6th line from the bottom; “Do not select the fOCO-F for the φAD.” added. 445 21.8.1.7 Reset Flash Memory deleted. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 1.00 Nov 15, 2006 447 22. Notes on On-Chip Debugger, (2); “ROM 128 KB Product (R5F2120CJFP, R5F2120CKFP, R5F2121CJFP, R5F2121CKFP) addresses 23800h to 23FFFh” added. (3); ROM 128 KB Product (R5F2120CJFP, R5F2120CKFP, R5F2121CJFP, R5F2121CKFP) addresses 03B00h to 03BFFh added. 448 23. Notes on Emulator Debugger added. 1.10 Oct 31, 2007 5 Table 1.3; Development status updated. 6 Table 1.4; Development status updated. 7 Figure 1.4; NOTE 3 added. 15 Table 4.1;

• 000Fh: “00011111b” → “00X11111b” 23 Figure 5.3 and Figure 5.4 NOTE1 revised. 25 Figure 5.5 and Figure 5.6 revised. 26 5.2 and Figure 5.7 revised. 31 Figure 6.4; VCA2 register NOTE5 revised. 52 Table 7.17 revised. 53 Table 7.19 revised. 56 Table 7.29 and Table 7.30 revised. 57 Table 7.33 revised. 66 Figure 10.2; NOTE4 revised. 69 Figure 10.5; FRA0 register NOTE2 revised and FRA1 register NOTE2 added. 70 Figure 10.7; VCA2 register NOTE5 revised. 73 10.3.2 revised. 75 10.4.1.3 revised. 76 Table 10.3; Watchdog Timer Interrupt deleted. 80 Figure 10.11; Remarks revised. 82 10.5.1; the second line from the bottom revised. 86 Figure 11.1; After Reset of PRCR register: “00XXX000b” → “00h” 89 12.1.3.1 revised. 101 12.2.1 revised. 106 Table 12.6 revised and NOTE2 added. 110 12.6.3 revised and Watchdog Timer Interrupt deleted. 111 Figure 12.20; NOTE2 revised. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 1.10 Oct 31, 2007 114 Figure 13.2;

• OFS register NOTE1 revised.
• After Reset of WDC register: “000xxxxxb” → “00X11111b” 125 Figure 14.6 Comment; “0 (During count)” → “1 (During count)” 136 14.1.6 revised. 137 14.2; the second line from the top revised. 140 Figure 14.16; TRBSC register NOTE3: “TRBPRE” → “TRBSC” TRBPR register NOTE2: “TRBPRE” → “TRBPR” 143 Figure 14.18 Comment; “0 (During count)” → “1 (During count)” 147 Table 14.9; NOTE2 added. 152 Table 14.10; NOTE2 added. 156 14.2.5.2 added. 157 14.2.5.3 added. 158 14.2.5.4 added. 170 Figure 14.33; “input capture signal” added. 183 Figure 14.46 revised. 185 Table 14.25; Count Stop Conditions revised. 201 Table 14.27; Count Stop Conditions revised. 214 Table 14.29; Count Stop Conditions revised. 221 Figure 14.84; NOTE1 revised. 238 Table 14.33; Count Stop Conditions revised. 267 Figure 15.3; Registers U0BRG and U1BRG: 271 Table 15.1; NOTE2 revised. 276 Table 15.4; NOTE1 revised. 277 Table 15.5; NOTE2 added. 278 Figure 15.10 revised. 281 15.3; the fourth line from the top added. 287 Figure 16.4; NOTE2 deleted. 288 Figure 16.5; NOTE1 deleted. 289 Figure 16.6; NOTE2 and NOTE7 revised. 290 Figure 16.7; NOTE5 revised. 291 Figure 16.8; SSTDR NOTE1 and SSRDR NOTE2 deleted. 311 16.2.8.1 deleted. 315 Figure 16.24; NOTE6 revised. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 1.10 Oct 31, 2007 316 Figure 16.25; NOTE5 deleted. 317 Figure 16.26; NOTE3 revised and NOTE7 deleted. 318 Figure 16.27; NOTE3 deleted. 319 Figure 16.28; NOTE7 revised. 324 Figure 16.32 revised. 326 Figure 16.33 and Figure 16.34 revised. 328 Figure 16.35 revised. 329 Figure 16.36 revised. 350 Figure 17.5; Procedure of Hardware LIN Clear the status flags: “LINST register ← 0” → “LINST register ← 1” 352 Figure 17.7 revised. 353 Figure 17.8; Bit name in the TRAMR register: “MOD0 to 2 bits” → “Bits TMOD0 to TMOD2” 354 Figure 17.9; Procedure of Hardware LIN Clear the status flags: “LINST register ← 0” → “LINST register ← 1” 356 Figure 17.11; Bit name in the LINST register: “SCDCT flag” → “BCDCT flag” 357 Figure 17.12; Procedure of Hardware LIN Clear the status flags: “LINST register ← 0” → “LINST register ← 1” 362 Figure 18.2; NOTE4 revised. 364 Table 18.2; Stop Condition revised. 365 Figure 18.4; NOTE4 revised. 368 Figure 18.6; NOTE4 revised. 372 Figure 18.10 revised. SW5 added. 373 18.6; the six line from the bottom: “A/D conversion mode with” → “A/D conversion mode without” 374 18.7 revised. 376 Table 19.2; Function of CPU Rewrite Mode: “any area other than the flash memory” → “the RAM” 381 Figure 19.4; NOTE1 revised. 382 Table 19.3; EW1 Mode: “ROM area” → “ROM or RAM area” 383 19.4.1 and 19.4.2; “td(SR-ES)” → “td(SR-SUS)” 384 19.4.2.4; the third line from the top: “in other than the flash memory” → “transferred to the RAM” 385 19.4.2.15 revised. 386 Figure 19.5; NOTE3 and NOTE5 revised. 388 Figure 19.7; NOTE5 revised. Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual 1.10 Oct 31, 2007 390 Figure 19.9; “any area other than the flash memory” → “the RAM” 391 Figure 19.11;

• “any area other than the flash memory” → “the RAM”
• NOTE4 deleted. 393 19.4.3.4 revised. 394 Figure 19.13 revised and NOTE4 added. 396 Figure 19.15 revised and NOTE4 added. 400 Table 19.7; MODE pin revised. 412 Table 20.6; NOTE4 added. 414 Table 20.11; NOTE1 revised. 423 Table 20.19 and Figure 20.11; 427 Table 20.25 and Figure 20.15; 429 21.2.3 revised and Watchdog Timer Interrupt deleted. 430 Figure 21.1; NOTE2 revised. 432 21.3.1 revised. 434 21.3.2.2 added. 435 21.3.2.3 added. 436 21.3.2.4 added. 444 21.4; the fourth line from the top added. 447 21.7 revised. 452 22 revised. 455 Appendix Figure 2.2 revised. 456 Appendix Figure 3.1 NOTE1 revised.

2.00 Aug 27, 2008 − “RENESAS TECHNICAL UPDATE” reflected: TN-16C-A172A/E

5, 6 Table 1.3, Table 1.4 revised Figure 1.2, Figure 1.3; ROM number “XXX” added 13, 14 Figure 3.1, Figure 3.2; “Expanding area” deleted 26 Figure 5.7 revised 120 Figure 14.1 “TSTART” → “TCSTF”, “TCKCUT bit” revised 137 Figure 14.13 “TCSTF” → “TSTART” revised and added 147 Table 14.9 “TRBP pin function” → “TRBO pin function” Rev. Date

REVISION HISTORY R8C/20 Group, R8C/21 Group Hardware Manual

2.00 Aug 27, 2008 172, 186,

225, 239 Figure 14.34, Figure 14.48, Figure 14.87, Figure 14.99; 199 Figure 14.62 revised 201 Table 14.27 revised 244 Figure 14.104 “Timer RD Status Register i (i = 0 or 1)(2)” NOTE2 deleted 286 Figure 16.3 revised 302 16.2.5.4 added 305 Figure 16.18 revised 351 Figure 17.6 revised 354 Figure 17.9 revised 375 Table 19.1; NOTE1 revised 398 Table 19.6 “FRM0 Register” → “FMR0 Register” 408 Table 20.2; NOTE2 revised 410 Table 20.4; NOTE2 and NOTE4 revised 411 Table 20.5; NOTE2 and NOTE5 revised 412 Table 20.6; “td(Vdet1-A)” added, NOTE5 added Table 20.7; “td(Vdet2-A)” and NOTE2 revised, NOTE5 added 413 Table 20.8; “trth” and NOTE2 revised Figure 20.3 revised Rev. Date

R8C/20 Group, R8C/21 Group Hardware Manual Publication Data: Rev.0.10 Sep 29, 2005 Rev.2.00 Aug 27, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. © 2008. Renesas Technology Corp., All rights reserved. Printed in Japan

2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan R8C/20 Group, R8C/21 Group Hardware Manual