R6986 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 62
Technical content
Datasheet sections
- 1 Application schematic
- 2 Pin settings
- 2.1 Pin connection
- 2.2 Pin description
- 2.3 Maximum ratings
- 2.4 Thermal data
- 2.5 ESD protection
- 3 Electrical characteristics
- 4 Datasheet parameters over the temperatur e range
- 5 Functional description
- 5.1 Power supply and voltage reference
- 5.2 Voltages monitor
- 5.3 Soft-start and inhibit
- 5.3.1 Ratiometric startup
- 5.3.2 Output voltage sequencing
- 5.4 Error amplifier
- 5.5 Light load operation
- 5.5.1 Low noise mode (LNM)
- 5.5.2 Low consumption mode (LCM)
- 5.6 Switchover feature
- 5.6.1 LCM
- 5.6.2 LNM
- 5.7 Overcurrent protection
- 5.8 Overvoltage protection
- 5.9 Thermal shutdown
Features
General features – 2 A DC output current – 4 V to 38 V operating input voltage – Large ambient temperature range: -40 °C to 125 °C – Low consumption mode or low noise mode – 30 µA IQ at light load (LCM V OUT = 3.3 V) –8 µ A IQ-SHTDWN – Adjustable f SW (250 kHz - 2 MHz) – Output voltage adjustable from
0.85 V to VIN
– Embedded output voltage supervisor – Synchronization – Adjustable soft-start time – Internal current limiting – Overvoltage protection – Output voltage sequencing – Peak current mode architecture DSON HS = 180 m, RDSON LS = 150 m – Thermal shutdown Aerospace and defense features – Suitable for use in aerospace and defense
applications
– Dedicated traceabilit y and part marking – Production parts approval documents available – Adapted extended life time and obsolescence management – Extended product change notification process – Designed and manufactured to meet sub- ppm quality goals – Advanced mold and frame designs for superior resilience in harsh environments (acceleration, EMI, thermal, humidity) – Extended screening ca pability on request Designed for aerospace applications Battery powered applications
Description
The R6986 device is a step-down monolithic switching regulator able to deliver up to 2 A DC. The output voltage adjustability ranges from 0.85 V to VIN. The 100% duty cycle, the wide input voltage range and the large ambient temperature range make it ideal for aerospace and defense applications. The “Low Consumption Mode” (LCM) is designed for always-on applications, so it maximizes the efficiency at light load with controlled output voltage ripple. The “Low Noise Mode” (LNM) makes the switching frequency constant and minimizes the output voltage ripple overload current range. The output voltage supervisor manages the reset phase for any digital load (µC, FPGA.). The RST open collector output can also implement output voltage sequencing during the power-up phase. The synchronous rectification, designed for high efficiency at medium - heavy load, and the high switching frequency capability make the size of the application compact. Pulse by pulse current sensing on both power elements implements an effective constant current protection. HTSSOP16 (RTH = 40 °C/W)
1 Application schematic
Figure 1. Application schematic
2 Pin settings
2.1 Pin connection
Figure 2. Pin connection (top view)
2.2 Pin description
Table 1. Pin description current generator (2 A typ.) charges the external capacitor to implement the soft-start.
4 SYNCH Master / slave synchronization
5F S W A pull up resistor (E24 series only) to VCC or pull down to GND selects the switching frequency. Pinstrapping is active only before the soft-start phase to minimize the IC consumption. phase to minimize the IC consumption. 7 COMP Output of the error amplifier. The designed compensation network is connected at this pin.
9 FB Inverting input of the error amplifier
10 SGND Signal GND
11 PGND Power GND
2.3 Maximum ratings
12 PGND Power GND
13 LX Switching node
14 LX Switching node
15 VIN DC input voltage
Table 1. Pin description (continued) Table 2. Absolute maximum ratings
2.4 Thermal data
2.5 ESD protection
Table 3. Thermal data Table 4. ESD protection
3 Electrical characteristics
TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified. Table 5. Electrical characteristics
Table 5. Electrical characteristics (continued)
All the population tested at TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.
- Parameter tested in static condition during testing phase. Parameter value may change over dynamic application condition.
- Not tested in production.
- LCM enables SLEEP mode at light load.
- Measured at fSW = 250 kHz.
Table 6. fSW selection
- Preferred codifications don't r equire any external resistor.
- Not tested in production.
All the population tested at TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified. Table 7. LNM / LCM selection
R6986 Datasheet parameters over the temperature range
4 Datasheet parameters ov er the temperature range
The 100% of the population in the production flow is tested at three different ambient temperatures (-40 °C, +25 °C, +135 °C) to guarantee the datasheet parameters inside the junction temperature range (-40 °C, +135 °C). The device operation is guaranteed when the junction temperature is inside the (-40 °C, +150 °C) temperature range. The designer can estimate the silicon temperature increase respect to the ambient temperature evaluating the internal power losses generated during the device operation. However the embedded thermal protection disables the switching activity to protect the device in case the junction temperature reaches the T SHTDWN (+165 °C typ.) temperature. All the datasheet parameters can be guaranteed to a maximum junction temperature of +135 °C to avoid triggering the thermal shutdown protection during the testing phase because of self-heating.
Functional description R6986
5 Functional description
The R6986 device is based on a “peak current mode”, constant frequency control. As a consequence, the intersection between the error amplifier output and the sensed inductor current generates the PWM control signal to drive the power switch. The device features LNM (low noise mode) that is forced PWM control, or LCM (low consumption mode) to increase the efficiency at light load. The main internal blocks shown in the block diagram in Figure 3 are: Embedded power elements. Thanks to the P-channel MOSFET as high-side switch the device features low dropout operation A fully integrated sawtooth oscillator with adjustable frequency A transconductance error amplifier The high-side current sense amplifier to sense the inductor current A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the embedded power elements The soft-start blocks to ramp the error amplifier reference voltage and so decreases the inrush current at power-up. The SS/INH pin inhibits the device when driven low. The switchover capability of the internal regulator to supply a portion of the quiescent current when the VBIAS pin is connected to an external output voltage The synchronization circuitry to manage master / slave operation and the synchronization to an external clock The current limitation circuit to implement the constant current protection, sensing pulse by pulse high-side / low-side switch current. In case of heavy short-circuit the current protection is fold back to decrease the stress of the external components A circuit to implement the thermal protection function The OVP circuitry to discharge the output capacitor in case of overvoltage event MLF pin strapping sets the LNM/LCM mode and the thresholds of the RST comparator FSW pinstrapping sets the switching frequency The RST open collector output
Figure 3. Internal block diagram
5.1 Power supply an d voltage reference
over the inhibits threshold). a regulated voltage that has a very low supply voltage noise sensitivity. quiescent current seen at VIN. (please refer to Section 5.6: Switchover feature on page 28).
5.2 Voltages monitor
good, the regulator starts operating. There is also a hysteresis on the VCC (UVLO). Figure 4. Internal circuit
5.3 Soft-start and inhibit
voltage below VINH threshold.
Figure 5. Soft-start phase The soft-start block supports the precharged output capacitor.
R6986 Functional description The maximum capacitor value has to be limited to guarantee the device can discharge it in case of thermal shutdown and UVLO events (see Figure 9), so restart the switching activity ramping the error amplifier reference voltage. Equation 2 where: Equation 3 The optional diode prevents to disable the device if the external source drops to ground. RUP value is selected in order to make the capacitor charge at first approximation independent from the internal current generator (4 A typ. current capability, see Table 5 on page 8), so: Equation 4 where: Equation 5 represents the SS/INH voltage correspondent to the end of the ramp on the error amplifier (see Figure 5); refer to Table 5 for VSS START, VFB and SSGAIN parameters. As a consequence the voltage across the soft-start capacitor can be written as: Equation 6 RSS_DOWN is selected to guarantee the device stays in inhibit mode when the internal generator sources 1 A typ. out of the SS/INH pin and VSTEP is not present: Equation 7 so: Equation 8 CSS 1 msec– RSS_EQ 1 VSS_FINAL 0.9 V– ln RSS_EQ RUP RDWN RDWN VSTEP VDIODE– VSS END– RUP VSS END VSS START VFB SSGAIN vSS t VSS_FINAL t RDWN ISS INHIBIT RDWN 1 A VINH 200 mV« RDWN 100 k
5.3.1 Ratiometric startup
Figure 10. Ratiometric startup where nR6986 represents the number of devices connected in parallel.
Figure 11. Ratiometric startup operation
5.3.2 Output voltage sequencing
outside regulation so implementing the sequencing (see Figure 12). Figure 12. Output voltage sequencing
5.4 Error amplifier
directly to the output voltage. Table 8. Uncompensated error amplifier characteristics
5.5 Light load operation
to Table 7: LNM / LCM selection on page 12).
5.5.1 Low noise mode (LNM)
different loading conditions. Figure 13. Low noise mode operation
5.5.2 Low consumption mode (LCM)
minimizes the quiescent current request in the meantime between the switching operation. (see Section 5.1: Power supply and voltage reference on page 15). drawn from the input voltage can be calculated as Equation 14.
Figure 14. LCM operation at zero load
Figure 17. The regulator works in CCM
5.6 Switchover feature
The switchover maximizes the efficiency at light load that is crucial for LCM applications.
5.6.1 LCM
3 V < VBIAS < 5.5 V (see Section 5.1: Power supply and voltage reference on page 15). and R6986 is the efficiency of the conversion in the working point.
5.6.2 LNM
medium load since the regulator always operates in continuous conduction mode.
R6986 Functional description
5.7 Overcurrent protection
The current protection circuitry features a constant current protection, so the device limits the maximum peak current (see Table 5: Electrical characteristics on page 8) in overcurrent condition. The R6986 device implements a pulse by pulse current sensing on both power elements (high-side and low-side switches) for effective current protection over the duty cycle range. The high-side current sensing is called “peak” the low-side sensing “valley”. The internal noise generated during the switching activity makes the current sensing circuitry ineffective for a minimum conduction time of the power element. This time is called “masking time” because the information from the analog circuitry is masked by the logic to prevent an erroneous detection of the overcurrent event. As a consequence, the peak current protection is disabled for a masking time after the high-side switch is turned on, the valley for a masking time after the low-side switch is turned on. In other words, the peak current protection can be ineffective at extremely low duty cycles, the valley current protection at extremely high duty cycles. The R6986 device assures an effective overcurrent protection sensing the current flowing in both power elements. In case one of the two current sensing circuitry is ineffective because of the masking time, the device is protected sensing the current on the opposite switch. Thus, the combination of the “peak” and “valley” current limits assure the effectiveness of the overcurrent protection even in extreme duty cycle conditions. The valley current threshold is designed higher than the peak to guarantee a proper operation. In case the current diverges because of the high-side masking time, the low-side power element is turned on until the switch current level drops below the valley current sense threshold. The low-side operation is able to prevent the high-side turn on, so the device can skip pulses decreasing the swathing frequency.
Figure 19. Peak current sense operation in overcurrent condition oscillations can be generated with huge discharging current levels (see Figure 20).
Figure 22. VBIAS in heavy short-circuit event
5.8 Overvoltage protection
discharge the output capacitor if the output voltage is 20% over the nominal value. even during the worst case scenario in term of load transitions. a consequence the output voltage regulation would be affected. dynamic performance not in line with the load request. reversed switch current during the overvoltage operation.
Figure 23. Overvoltage operation
5.9 Thermal shutdown
thermal protection runs away a new soft-start cycle will take place.
6 Closing the loop
Figure 24. Block diagram of the loop
6.1 G CO(s) control to output transfer function
given by the ESR of the output capacitor. error amplifier that introduces a double pole at one half of the switching frequency.
where: Equation 21 Sn represents the on time slope of the sensed inductor current, Se the on time slope of the external ramp (VPP peak-to-peak amplitude) that implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50%. Se can be calculated from the parameter VPP gCS given in Table 5 on page 8. The sampling effect contribution FH(s) is: Equation 22 where: Equation 23 mC 1 Se Sn Se VPP gCS fSW = Sn VIN VOUT– FH s 1 1 s Qp
6.2 Error amplifier compensation network
The typical compensation network required to stabilize the system is shown in Figure 25. Figure 25. Transconductance embedded error amplifier system stability but it is useful to reduce the noise at the output of the error amplifier.
6.3 Voltage divider
Figure 26. Leading network example
6.4 Total loop gain
respectively in Figure 27 and Figure 28. Figure 27. Module plot
Figure 28. Phase plot Equation 22 on page 36), the dotted blue trace neglects the contribution.
6.5 Compensation network design
where: Equation 35 p is defined by Equation 20 on page 36, gCS represents the current sense transconductance (see Table 5: Electrical characteristics on page 8) and gm TYP the error amplifier transconductance. Equation 36 Example 2 Considering VIN = 12 V, VOUT = 3.3 V, L = 6.8 H, COUT = 15 F, fSW = 500 kHz. The maximum system bandwidth is 80 kHz. Assuming to design the compensation network to achieve a system bandwidth of 70 kHz: Equation 37 Equation 38 so accordingly with Equation 34 and Equation 36: Equation 39 Equation 40 fPOLE CC fPOLE 6kHz= RLOAD VOUT IOUT RC 68k= CC 168pF 180pF=
7 Application notes
7.1 Output voltage adjustment
The error amplifier reference voltage is 0.85 V typical. Section 6.5: Compensation network design). Figure 29. R6986 application circuit
7.2 Switching frequency
pinstrapped and then driven floating in order to minimize the quiescent current from VIN.
7.3 MLF pin
floating in order to minimize the quiescent current from VIN.
codifications don't require any external resistor.
7.4 Voltage supervisor
a valid power supply, the device can delay the RST assertion with a programmable time. Figure 30. Voltage supervisor operation and Table 7: LNM / LCM selection on page 12). DELAY = 1.234 V (see Figure 30). The maximum suggested capacitor value is 270 nF.
7.5 Synchronization (LNM)
SYNCH pin is I/O able to deliver or recognize a frequency signal. Figure 31. Input RMS current
least 10 internal clock cycles. is able to synchronize to a clock signal in the range 275 kHz - 2 MHz (see Figure 34). pulse at 250 kHz (see Figure 36) in the SYNCH line. Figure 36. Slave to master mode transition counts to design the slope compensation. The same considerations above are also valid. Table 9. Example of oscillator frequency selection from Table 6 Symbol R VCC (E24 series) R GND (E24 series) f SW min. f SW typ. f SW max.
Figure 37. Master driving capability to synchronize the R6986
7.6 Design of the power components
7.6.1 Input capacitor selection
contributes to higher conversion efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as: Equation 44 Where IOUT is the maximum DC output current, D is the duty cycles, is the efficiency. This function has a maximum at D = 0.5 and, considering = 1, it is equal to Io/2. In a specific application the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: Equation 45 Equation 46 Where VHIGH_SIDE and VLOW_SIDE are the voltage drops across the embedded switches. The peak to peak voltage across the input filter can be calculated as: Equation 47 In case of negligible ESR (MLCC capacitor) the equation of CIN as a function of the target VPP can be written as follows: Equation 48 Considering this function has its maximum in D = 0.5: Equation 49 Typically CIN is dimensioned to keep the maximum peak-peak voltage across the input filter in the order of 5% VIN_MAX. IRMS IOUT 1 D ----– D ----= DMAX VOUT VLOWSIDE+ DMIN VOUT VLOWSIDE+ VPP IOUT ----– D CIN IOUT ----– D ----= CINMIN IOUT
7.6.2 Inductor selection
the current ripple lower than 20% - 40% of the output current over the input voltage range. where fSW is the switching frequency 1/(TON + TOFF). inductance value to have IL = 30% of IO is about 8.2 µH. output current that can be delivered, without reaching the current limit. In Table 11 some inductor part numbers are listed. Table 10. Input capacitors Table 11. Inductors
7.6.3 Output capacitor selection
selected in order to have a voltage ripple compliant with the application requirements. capacitor is a multi layer ceramic capacitor (MLCC). to sustain the output voltage for time response shorter than the loop response time. In Table 12 some capacitor series are listed. Table 12. Output capacitors
8 Efficiency curves
Figure 38. Efficiency curves over fsw: VIN = 13.5 V - VOUT = 3.3 V Figure 39. Efficiency curves over fsw: VIN = 13.5 V - VOUT = 3.3 V (log scale)
9 Package information
specifications, grade definitions and product status are available at: www.st.com. Figure 54. HTSSOP16 package outline
Table 13. HTSSOP16 package mechanical data
10 Order codes
Table 14. Order codes Table 15. Document revision history 06-Oct-2014 1 Initial release. Minor modifications throughout document.