R5650T

R5650T NISSHINBO | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 38

Technical content

3 to 5 Serial Cell Li-ion Battery Protection IC NO.EA-401-230324 OUTLINE The R5650T is an overcharge and discharge protection IC for 3- to 5- series cell Li -ion / Li -polymer rechargeable battery pack, further includes a short -circuit and protection circuits for charge / discharge overcurrent. The R5650T supports 3 to 5 cells connected in series, forcing a certain voltage on SEL1 and SEL2 pins can select any number of cells.

FEATURES

 Hi gh Voltage Tolerant Process  Low Supply Current  High-accuracy Voltage Detection Overdischarge detection voltage (VDET2n(1)) ················· 2.0 V to 3.2 V (in 5 mV steps) - provided, Max.value is 3.2 V. Discharge overcurrent detection voltage1 (VDET31) ········ 0.03 V to 0.10 V (in 10 mV steps) Discharge overcurrent detection voltage accuracy ········ 0.03 V to 0.05 V: ± 5 mV, 0.05 V to 0.10 V: ± 10% Discharge overcurrent detection voltage2 (VDET32) ········ 2 / 2.5 / 3 times VDET31 Charge overcurrent detection voltage (VDET4) ··············· -0.015 V to -0.025 V, -0.030 V to -0.050 V (in 5 mV steps) Charge overcurrent detection voltage accuracy ············ -0.015 V to -0.025 V: ± 5 mV, -0.030 V to -0.050 V: ± 20%, or Disable  Temperature Protection (2) VDET32 is not detected when VDET32 is higher than VSHORT.

NO.EA-401-230324  Each Detection Delay Time Overdischarge detection delay time settable by external capacitor Discharge overcurrent detection delay time 1/2 settable by external capacitor R5650TxxxBx: 8 ms  3 to 5 Cells Selectable Battery Protection  Delay Time Shortening Function  Temperature Protection by External NTC Thermistor  Discharging Current Detection for Temperature Protection

APPLICATIONS

■ Li-Ion or Li-Polymer Battery Protection for a power tool and cordless / robot vacuum cleaners.

NO.EA-401-230324 SELECTION GUIDE Set voltages, Delay times are, and Optional functions can be designated. Selection Guide Product Name Package Quantity per Reel Pb Free Halogen Free R5650Txxx$∗-E2-FE TSSOP-20 3,000 pcs Yes Yes xxx: Specify the combination of the following set output voltages. Refer to Product Code List for details. VDET1n(1) : 3.6 V to 4.5 V in 5 mV steps V REL1n(1) : VDET1n – 0.1 V to VDET1n – 0.4 V in 50 mV steps VDET2n(1) : 2.0 V to 3.2 V in 5 mV steps VREL2n(1) : VDET2n + 0.0 V to VDET2n + 0.7 V in 100 mV steps (Max. 3.2 V) VDET31 : 0.03 V to 0.10 V in 10 mV steps VDET32 : 2 or 2.5 or 3 times VDET31 VSHORT : 0.1 V to 0.6 V in 20 mV steps VDET4 : -0.015 V to -0.050 V, in 5 mV steps $: Specify the charge overcurrent delay time (tVDET4). Delay Time Code Table Code tVDET4 (ms) A 256 B 8 ∗: Specify the combination of functions. Refer to Function Code Table for details. Function Code Table Code Overcharge Detection Overdischarge Detection Charge Overcurrent 0V Battery Charging A Release Release Enable Permit B Release Release Disable Permit C Release Release Enable Inhibition D Release Release Disable Inhibition (1) VDET1n, VREL1n、VCBDn, VCBRn, VDET2n, VREL2n : n =1, 2, 3, 4, 5

NO.EA-401-230324 Product Code List The product code is determined by the combination of the set output voltages (O vercharge detection/release voltage: V DET1n/VREL1n, Overdischarge detection/ release voltage: VDET2n/VREL2n, Discharge overcurrent detection voltage1/2: V DET31/VDET32, Short -circuit detection voltage: V SHORT, Charge overcurrent detection voltage: VDET4) and the threshold temperatures for the temperature protection (Charge high-temperature: TDCH, Charge low-temperature: TDCL, Discharge high-temperature: TDDH). Product Name Set Voltage (V) Threshold Temperature(°C) [Release Temperature] VDET1n VREL1n VDET2n VREL2n VDET31 VDET32 VSHORT VDET4 VNOCHGN TDCH TDCL TDDH [40] [5] [55] [40] [2] [55] [50] [2] [55] [50] [2] [55] [50] [2] [55] [45] [5] [55] [45] [0] [60] [45] [0] [60] [50] [5] [60] [50] [5] [55] [40] [5] [55] [40] [2] [55] [50] [2] [55] [40] [2] [55] [40] [2] [55] [45] [5] [55] [45] [5] [55] [45] [5] [55] [50] [5] [60] Please contact our sales representatives if required a product code other than the above combinations.

NO.EA-401-230324 BLOCK DIAGRAM SEL1 VC1 VC2 VC3 VC4 Clamp1 Clamp2 Clamp3 Clamp4 VC5 VD1-1 VD2-1 VD1-2 VD2-2 VD1-3 VD2-3 VD1-4 VD2-4 Regulator DS Circuit VDD Logic Circuit Oscillator Counter Logic Circuit VD1-5 VD2-5 SEL2 CT1 CT2 Clamp5 VMP SENS VD3-1 COUT DOUT DRAIN Short CircuitDelay tVDET2 tVDET32Logic Circuit Regulator VD3-2 Logic Circuit VD4 VSS VR TEP Oscillator Counter Logic Circuit VRT CT3 tVDET31 ClampVR R5650T Block Diagram

NO.EA-401-230324 PIN DESCRIPTIONS TSSOP-20 Pin Configuration Pin No Symbol Pin Description

1 VDD VDD pin

2 VC1 Positive terminal pin for CELL1

3 VC2 Positive terminal pin for CELL 2

4 VC3 Positive terminal pin for CELL 3

5 VC4 Positive terminal pin for CELL 4

6 VC5 Positive terminal pin for CELL 5

7 VSS VSS / Ground pin for the IC

8 SENS Current sense pin

9 DRAIN Discharge overcurrent release output pin

10 DOUT Overdischarge detection output pin, CMOS output

11 COUT Overcharge detection output pin, Pch. Open-drain output

12 VMP Charger negative input pin

13 CT1 Capacitor connection pin for tVDET2 setting

14 CT2 Capacitor connection pin for tVDET31 setting

15 CT3 Capacitor connection pin for tVDET32 setting

16 TEP Temperature protection input pin

17 VRT Thermistor reference voltage pin

18 VR Internal VR output pin

19 SEL1 3- / 4- / 5-cell selectable pins 20 SEL2

NO.EA-401-230324 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings (Ta = 25°C, VSS = 0 V) Symbol Item Rating Unit VDD Power Supply Voltage −0.3 to 30 V VVC1 VVC2 VVC3 VVC4 VVC5 VVMP VSEL1 VSEL2 VSENS VCT1 VCT2 VCT3 VTEP VC1 Pin Input Voltage for CELL1 VC2 Pin Input Voltage for CELL2 VC3 Pin Input Voltage for CELL3 VC4 Pin Input Voltage for CELL4 VC5 Pin Input Voltage for CELL5 VMP Pin Input Voltage SEL1 Pin Input Voltage SEL2 Pin Input Voltage SENS Pin Input Voltage CT1 Pin Input Voltage CT2 Pin Input Voltage CT3 Pin Input Voltage TEP Pin Input Voltage VVC2 - 0.3 to VVC2 + 6.5 VVC3 - 0.3 to VVC3 + 6.5 VVC4 - 0.3 to VVC4 + 6.5 VVC5 - 0.3 to VVC5 + 6.5 - 0.3 to + 6.5 VDD - 30 to VDD + 0.3 −0.3 to VDD + 0.3 −0.3 to VDD + 0.3 VDD - 30 to VVR + 0.3 −0.3 to VVR + 0.3 −0.3 to VVR + 0.3 −0.3 to VVR + 0.3 −0.3 to VVR + 0.3 V V V V V V V V V V V V V VCOUT VDOUT VDRAIN VVR VVRT COUT Pin Output Voltage DOUT Pin Output Voltage DRAIN Pin Output Voltage VR Pin Output Voltage VRT Pin Output Voltage VDD - 30 to VDD + 0.3 −0.3 to VOH2 + 0.3 −0.3 to VOH3 + 0.3 −0.3 to VR + 0.3 −0.3 to VR + 0.3 V V V V V PD Power Dissipation Refer to Appendix “Power Dissipation” Tj Junction Temperature Range −40 to 125 °C Tstg Storage Temperature Range −55 to 125 °C ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause permanent damage and may degrade the lifetime and safety for both device and system using the device in the field. The functional operation at or over these absolute maximum ratings is not assured. RECOMMENDED OPERATING CONDITION Symbol Item Rating Unit VDD Operating Input Voltage 4.0 to 25.0 V Ta Operating Temperature Range −40 to 85 °C RECOMMENDED OPERATING CONDITIONS All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating conditions. The semiconductor devices cannot operate normally over the recommended operating conditions, even if they are used over such conditions by momentary electronic noise or surge. And the semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions.

NO.EA-401-230324

ELECTRICAL CHARACTERISTICS

VCELLn n = 1, 2, 3, 4, 5 (Ex. VCELL1 is a voltage difference between VC1 and VC2), unless otherwise noted. Symbol Parameter Conditions Ratings Unit Circuit (1) Min. Typ. Max. VDET1n CELLn overcharge detection voltage at rising edge of supply voltage VDET1n -0.025 VDET1n VDET1n +0.025 V A VREL1n CELLn overcharge release voltage at falling edge of supply voltage VREL1n -0.050 VREL1n VREL1n +0.050 V A tVDET1 Overcharge detection delay time VDD = VVC1, VCELLn = 3.4 V (n = 2, 3, 4, 5) VCELL1 = 3.4 V → VDET1n+0.2 V 0.7 1.0 1.3 s B tVREL1 Overcharge release delay time VDD = VVC1, VCELLn = 3.4 V (n = 2, 3, 4, 5) VCELL1 = VDET1n+0.2 V→ 3.4 V 11 16 21 ms B VDET2n CELLn overdischarge detection voltage Detect falling edge of supply voltage VDET2n -0.050 VDET2n VDET2n +0.050 V C VREL2n CELLn overdischarge release voltage Detect rising edge of supply voltage VREL2n -0.050 VREL2n VREL2n +0.050 V C ICT1 CT1 pin charge current VDD = VVC1, VCELLn = 3.4 V (n = 2, 3, 4, 5) VCELL1 = 3.4 V →1.5 V 350 500 650 nA D VDCT1 CT1 pin detection voltage VDD = VVC1, VCELLn = 3.4 V (n = 2, 3, 4, 5) VCELL1 = 1.5 V 1.44 1.80 2.16 V E tVDET2 Overdischarge detection delay time tVDET2 = CCT1 × VDCT1 / ICT1, CCT1 = 33 nF 83 119 155 ms - tVREL2 Overdischarge release delay time VDD = VVC1, VCELLn = 3.4 V (n = 2, 3, 4, 5) VCELL1 = 1.5 V → 3.4 V 0.7 1.1 1.7 ms F VDET31 Discharge overcurrent detection voltage1 VDD = VVC1, VCELLn = 3.4 V VMP = 4.0 V, at rising edge of SENS VDET31 < 0.05 VDET31 -0.005 VDET31 VDET31 +0.005 V G VDET31 ≥ 0.05 VDET31 -10% VDET31 +10% VDET32 Discharge overcurrent detection voltage2 VDD = VVC1, VCELLn = 3.4V VDET32 < 0.1 VDET32 -0.0125 VDET32 VDET32 +0.0125 V H VVMP = 4.0 V, at rising edge of SENS VDET32 ≥ 0.1 VDET32 -12.5% VDET32 +12.5% VREL3 Discharge overcurrent release voltage VDD = VVC1, VCELLn = 3.4 V VSENS = 0 V, at falling edge of VMP 0.8 1.0 1.2 V G ICT2 CT2 pin charge current VDD = VVC1, VCELLn = 3.4 V VSENS = 0 V → VDET31 + 0.02 V 350 500 650 nA H (1) Refer to TEST CIRCUITS for detail information.

NO.EA-401-230324 VCELLn n = 1, 2, 3, 4, 5 (Ex. VCELL1 is a voltage difference between VC1 and VC2), unless otherwise noted. Symbol Parameter Conditions Ratings Unit Circuit (1) Min. Typ. Max. VDCT2 CT2 pin charge detection voltage VDD = VVC1, VCELLn = 3.4 V (n = 2, 3, 4, 5) VSENS = VDET31 + 0.02 V VMP = 4.0 V 1.20 1.50 1.80 V I ICT3 CT3 pin charge current VDD = VVC1, VCELLn = 3.4 V VSENS = 0 V →VDET31 + 0.02 V 2.0 3.0 4.0 μA J VDCT3 CT3 pin charge detection voltage VDD = VVC1, VCELLn = 3.4 V (n = 2, 3, 4, 5) VSENS = VDET32 + 0.02 V, VMP = 4.0 V 1.20 1.50 1.80 V K tVDET31 Discharge overcurrent delay time1 tVDET31 = CCT2 ×VDCT2 / ICT2 CCT2 = 3.3 nF 6.9 9.9 12.9 ms - tVDET32 Discharge overcurrent delay time2 tVDET32 = CCT3 ×VDCT3 / ICT3 CCT3 = 3.3 nF 1.15 1.65 2.15 ms - tVREL3 Discharge overcurrent release delay time VDD = VVC1, VCELLn = 3.4 V VSENS = VSS, VMP = 4.0 V → VSS 0.7 1.1 1.7 ms I VSHORT Short protection voltage VDD = VVC1, VCELLn = 3.4 V, VMP = 4.0 V, at rising edge of SENS VSHORT ×0.8 VSHORT VSHORT ×1.2 V L tSHORT Short protection delay time VDD = VVC1, VCELLn = 3.4 V VSENS = 0 V → 2.0 V, VMP = 4.0 V 350 500 650 μs L VDET4 Charge overcurrent detection voltage4 VDD = VVC1, VCELLn = 3.4 V, VMP = −1.0 V, at falling edge of SENS VDET4 ≥ -0.025 VDET4 -0.005 VDET4 VDET4 +0.005 V M VDET4 < -0.025 VDET4 -20% VDET4 +20% VREL4 Charge overcurrent release voltage VDD = VVC1, VCELLn = 3.4 V, at rising edge of VMP 0.05 0.1 0.15 V M tVDET4 Charge overcurrent delay time VDD = VVC1, VCELLn = 3.4 V, VSENS = 0 V→−1.0 V tVDET4 -37.5% tVDET4 tVDET4 +37.5% ms M tVREL4 Charge overcurrent release delay time VDD = VVC1, VCELLn = 3.4 V, VSENS = VSS, VMP = −1.0 V →1.0 V 0.7 1.1 1.7 ms M VIH1 SEL1 pin input voltage , high VDD = VVC1, VCELLn = 3.4 V VDD - 0.3 V VDD + 0.3 V V N VIM1 SEL1 pin input voltage , middle VDD = VVC1, VCELLn = 3.4 V 4.0 VDD/2 - 0.5 V V N VIL1 SEL1 pin input voltage , low VDD = VVC1, VCELLn = 3.4 V VSS - 0.3 V VSS + 0.3 V V N (1) Refer to TEST CIRCUITS for detail information.

NO.EA-401-230324 VCELLn n = 1, 2, 3, 4, 5 (Ex. VCELL1 is a voltage difference between VC1 and VC2), unless otherwise noted. Symbol Parameter Conditions Ratings Unit Circuit (1) VIH2 SEL2 pin input voltage, high VDD = VVC1, VCELLn = 3.4 V VDD - 0.3 V VDD + 0.3 V V O VIM2 SEL2 pin input voltage, middle VDD = VVC1, VCELLn = 3.4 V 4.0 VDD/2 - 0.5 V V O VIL2 SEL2 pin input voltage, low VDD = VVC1, VCELLn = 3.4 V VSS - 0.3 V VSS + 0.3 V V O VOL2 DOUT pin Nch. ON voltage IOL = 50 μA, VDD = VVC1, VCELLn = 3.4 V 0.02 0.10 V P VOL3 DRAIN pin Nch. ON voltage IOL = 50 μA, VDD = VVC1, VCELLn = 3.4 V 0.04 0.20 V Q VOH1 COUT pin Pch. ON voltage IOH = −50 μA, VDD = VVC1, VCELLn = 3.4 V VDD - 0.5 V VDD - 0.1 V V R VVR12 VR12V output voltage IOH = −5 μA, VDD = VVC1, VCELLn = 3.4 V Measured to draw the current through DOUT 9.5 12 14 V S VOH2 DOUT pin Pch ON voltage(2) IOH = −50 μA, VDD = VVC1, VCELLn = 3.4 V VVR12 - 0.5 V VVR12 - 0.1 V V S VOH3 DRAIN pin Pch. ON voltage(2) IOH = −50 μA, VDD = VVC1, VCELLn = 3.4 V VSENS = VMP = 4.0 V VVR12 - 0.5 V VVR12 - 0.1 V V T ILCOUT COUT pin off-leakage current VDD = VVC1, VCELLn = 3.4 V, COUT = −13 V -0.1 μA U VVR VR pin output voltage VDD = VVC1, VCELLn = 3.4 V 3.5 3.6 3.7 V V VVRT VRT pin output voltage VDD = VVC1, VCELLn = 3.4 V IVRT = -80µA 3.47 3.57 3.67 V W TDCH Detection temperature for charge high-temperature VDD = VC1, VCELLn = 3.4 V TDCH -5 TDCH TDCH +5 °C X TRCH Release temperature for charge high-temperature VDD = VC1, VCELLn = 3.4 V TDCH -10 TDCH -5 TDCH °C X tDCHT Detection delay time for charge high-temperature VDD = VC1, VCELLn = 3.4 V, VTEP = 0.9 V → 0.3 V 42 60 78 ms X tRCHT Release delay time for charge high-temperature VDD = VC1, VCELLn = 3.4 V, VTEP = 0.3 V → 0.9 V 42 60 78 ms X (1) Refer to TEST CIRCUITS for detail information. (2) If the VDD pin voltage becomes lower than the output of the regulator, the output voltage (DOUT, DRAIN) becomes almost equal to VDD.

NO.EA-401-230324 VCELLn n = 1, 2, 3, 4, 5 (Ex. VCELL1 is a voltage difference between VC1 and VC2), unless otherwise noted. Symbol Parameter Conditions Ratings Unit Circuit (1) TDCL Detection temperature for charge low-temperature VDD = VVC1, VCELLn = 3.4 V TDCL -3 TDCL TDCL +3 °C X TRCL Release temperature for charge low-temperature VDD = VVC1, VCELLn = 3.4 V TDCL TDCL TDCL +8 °C X tDCLT Detection delay time for charge low-temperature VDD = VVC1, VCELLn = 3.4 V, VTEP = 0.9 V → 3.5 V 42 60 78 ms X tRCLT Release delay time for charge low-temperature VDD = VVC1, VCELLn = 3.4 V, VTEP = 3.5 V → 0.9 V 42 60 78 ms X TDDH Detection temperature for discharge high- temperature VDD = VVC1, VCELLn = 3.4 V TDDH -5 TDDH TDDH +5 °C X TRDH Release temperature for discharge high- temperature VDD = VVC1, VCELLn = 3.4 V TDDH -20 TDDH -15 TDDH -10 °C X tDDHT Detection delay time for discharge high- temperature VDD = VVC1, VCELLn = 3.4 V, VTEP = 0.9 V → 0 V 42 60 78 ms X tRDHT Release delay time for discharge high- temperature VDD = VVC1, VCELLn = 3.4 V, VTEP = 0 V → 0.9 V 42 60 78 ms X tVTT Temperature scanning cycle VDD = VVC1, VCELLn = 3.4 V 0.7 1 1.3 s Y VDSG Discharge state detection voltage (VMP – VSS) Detect rising edge of VMP 5 10 15 mV a VNOCHGn 0V battery charge inhibition voltage VDD = VVC1, VCELLn = 3.2 V VNOCHGn -0.2 VNOCHGn VNOCHGn +0.2 V A ISS1 Supply current 1 VDD = VVC1, COUT = OPEN VCELLn = VDET1n - 0.4 V 12 25 μA Z ISS2 Supply current 2 VDD = VVC1, COUT = OPEN VCELLn = 1.5 V 5 9 μA Z VSTB Standby mode threshold voltage VDD = VVC1 = 1.5 V, Detect rising edge of VMP 0.9 1.13 1.35 V G (1) Refer to TEST CIRCUITS for detail information.

NO.EA-401-230324 TEST CIRCUITS Ａ VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 V V V V V B C OSCILLOSCOPE VSS TEP VR CT1 CT2 CT3 VRT V V V V V OSCILLOSCOPE V V V V V OSCILLOSCOPE D V V V V V A VC1 VC2 VDD VC3 VC4 VC5 SENS DOUT DRAIN VSS VMP COUT SEL1 SEL2 TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT

NO.EA-401-230324 E F G V V V V V V V V V V OSCILLOSCOPE OSCILLOSCOPE V V V V V V OSCILLOSCOPE V V H V V V V V OSCILLOSCOPE A V V VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT

NO.EA-401-230324 I V V V V V OSCILLOSCOPE V J K V V V V V OSCILLOSCOPE V V V V V OSCILLOSCOPE A V V V L V V V V V OSCILLOSCOPE V VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT

NO.EA-401-230324 N O V V V V V OSCILLOSCOPE V V V V V V OSCILLOSCOPE V M V V V V V V V OSCILLOSCOPE P V V V V V V VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT

NO.EA-401-230324 Q R V V V V V V V V V V V V S T V V V V V V V V V V V V VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT

NO.EA-401-230324 U V V V V V A V V V V V V V W V V V V V V X V V V V V OSCILLOSCOPEOSCILLOSCOPE VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT

NO.EA-401-230324 Y V V V V V OSCILLOSCOPE A Z VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 VSS TEP VR CT1 CT2 CT3 VRT a VC1 VC2 VDD VC3 VC4 VC5 SENS VMP COUTDOUT DRAIN SEL1 SEL2 V V V V V OSCILLOSCOPE VSS TEP VR VRT V CT1 CT2 CT3

NO.EA-401-230324 THEORY OF OPERATION Overcharge Detector: VD1n (n = 1, 2, 3, 4, 5) During charging, the R5650T supervises the CELL1 voltage (V CELL1) between VC1 and VC2 pins, the CELL2 voltage (VCELL2) between VC2 and VC3 pins, the CELL3 voltage (V CELL3) between VC3 and VC4 pins, the CELL4 voltage (VCELL4) between VC4 and VC5 pins, and the CELL5 voltage (V CELL5) between VC5 and VSS pins. If at least one of the cells’ voltage becomes more than the overcharge detection voltage (V DET1n), the overcharge is detected, and COUT pin connected to an external pull -down resistor becomes “Hi -z”, and it makes the external FET turn off. Then, the charging stops. After detecting the overcharge, when the VMP pin input voltage (V VMP) becomes higher than the charge overcurrent release voltage (VREL4) by taking off the charger and connecting a load, all the cell voltage become lower than VDET1n, then COUT pin becomes “High”, and then the charging is available. Likewise, when VVMP becomes lower than VREL4 and all the cell voltage become lower than V REL1n, COUT pin becomes “High” and then the charging is available. The device has internal fixed delay times for overcharge detection and overcharge release. When the delay time passes while any one of cell voltages (VCELLn) is more than VDET1n, the overcharge is detected. However, all cell voltage (V CELLn) becomes lower than V DET1n within the overcharge detection delay time (t VDET1), the overcharge is not detected. Besides, if the release conditions do not hold within the overcharge release delay time (tVREL1) even though the release conditions hold once after detecting the overcharge, the device cannot release from the overcharge. Since COUT pin is a Pch. open- drain type, a “High” level of COU T pin is as same potential as the VDD pin voltage (VDD). Overdischarge Detector: VD2n (n = 1, 2, 3, 4, 5) During discharging, the R5650T supervises VCELL1, VCELL2, VCELL3, VCELL4, and VCELL5 as same as charging. If at least one of the cell voltages becomes less than the overdischarge detection voltage (VDET2n), the overdischarge is detected, and DOUT pin becomes “Low” . Then, the external FET is turned off and the discharging stops. The ov erdischarge detection i s released even if the charger is not connected when the all cell voltage (VCELLn) becomes higher than VREL2n, and then DOUT pin becomes “High”. The overdischarge detection delay time (tVDET2) is settable by the external capacitor (CCT1) connected to CT1 pin. When the delay time passes while any one of cell voltages (VCELLn) is lower than VDET2n, the overdischarge is detected. However, all cell voltage (VCELLn) becomes higher than VDET2n within tVDET2, the overdischarge is not detected. The overdischarge release delay time (tVREL2) is fixed internally. After detecting the overdischarge, the device stops unnecessary circuits to reduce the supply current to a minimum when VMP pin becomes “High”. DOUT pin, which is a CMOS output, outputs the internal regulator’s voltage (about 12 V) when “High” level and outputs the VSS pin voltage (VSS) when “Low” level.

NO.EA-401-230324 Discharge Overcurrent Detector: VD3 (n = 1, 2), Short-circuit Protector During charging and discharging, the R5650T supervises SENS pin voltage (VSENS). The discharge overcurrent is detected when V SENS becomes in between the discharge overcurrent detection voltage (VDET3n) and the short -circuit detection voltage (V SHORT) owing to a large load, and the short -circuit is detected when VSENS becomes more than VSHORT. Then, to prevent from flowing large current to circuits, DOUT pin is set to “Low” and the external FET is turned OFF. The device has two detection voltages (V DET31, VDET32) to detect the discharge overcurrent. Each detection voltage (V DET31, V DET32) ha s the delay time each other. The discharge overcurrent detection delay time 2 (tVDET32) is set to be shorter than the discharge overcurrent detection delay time 1 (t VDET31). The di scharge overcurrent detection delay time 1 (tVDET31) are settable by the external capacitor (C CT2) connected to CT2 pin. Likewise, the discharge overcurrent detection delay time2 (t VDET32) is settable by the CCT3 connected to CT3 pin. When VSENS becomes lower than V DET3n within the delay time, the discharge overcurrent is not detected. The discharge overcurrent release delay time (tVREL3) and the short-circuit detection delay time (tSHORT) are fixed internally. An external resistor for discharge overcurrent release must be mounted among each drain of the external FETs connected to DRAIN, COUT, and DOUT pins. After detecting the discharge overcurrent or the short-circuit, the external FET connected to DRAIN pin is turned ON, and the resistor for overcurrent release is connected to VSS. When a load is removed after detecting the discharge overcurrent or the short -circuit, the VMP pin voltage (VVMP) is pulled down to VSS via the resistor for the overcurrent release, and V VMP becomes less than VREL3. After a c ertain delay time, the discharge overcurrent detection state or the short-circuit protection state is released. When the discharge overcurrent detection is released, the external FET connected to DRAIN pin is turned OFF, and the resistor for the overcurrent release is disconnected from VSS. Charge Overcurrent Detector: VD4 During charging or discharging, the R5650T supervises the SENS pin voltage (VSENS). When an inappropriate current flow by an inappropriate charger, VSENS becomes less than the charge overcurrent detection voltage, and the charge overcurrent is detected. And, COUT pin with the external pull -down resistor becomes “Hi -z”. Tuning OFF the external FET can prevent from flowing large current to circuits. When SENS pin voltage (VSENS) becomes higher than VDET4 within the delay time, the charge overcurrent is not detected. The output delay times for charge overcurrent detection and charge overcurrent release are fixed internally. The VMP pin voltage (VVMP) becomes higher than the charge overcurrent release voltage (VREL4) when a load is connected after disconnecting the charger, and the charge overcurrent is released after passing the charge overcurrent release delay time (tVREL4).

NO.EA-401-230324 Standby Mode After the overdischarge protection, the R5650T sh ifts from normal mode to standby mode when VMP pin voltage (VVMP) is more than VSTB. In standby mode, some unnecessary circuits stop to reduce the supply current to a minimum. This device can return from standby mode to normal mode when VVMP is lower than V STB by connecting a charger. Operating Mode Switch by SEL1 and SEL2 Pins SEL1 and SEL2 pins are switching-control pins to select among 3- / 4- / 5-cell protection. When using for the 4-cell protection, connecting SEL1 pin to VSS and the SEL2 pin to VDD is required to stop the 5th cell protection circuit and shut signals. The overdischarge is not detected when VC5 pin is shortened to VSS. When using for the 3- cell protection, likewise, connecting SEL1 pin to V DD and SEL2 pin to VSS is required to stop the 5th and 4th cells protection circuits and shut signals. The overdischarge is not detected when VC4 and VC5 pins are shortened to VSS. SEL1 / SEL2 pin must be fixed to VDD / VSS when using the 3- / 4- / 5- cell protection. Setting SEL1 and SEL2 pins can select disabling/enabling the shorten mode 1 (approx. 1/70) or the shorten mode 2 (tVDET1:approx. 4ms). Refer to the following table for details of the operating mode. Operating Modes (1) “High”: VDD level, “Middle”: (VDD/2-0.5) V to (VDD-3) V, “Low”: VSS level (2) Reserved for test mode Input Voltage(1) Operation Mode SEL1 Pin SEL2 Pin High High 5-cell protection mode Low High 4-cell protection mode High Low 3-cell protection mode Low Low Delay time shortening mode 2 for 5-cell protection Low Middle Prohibition of use(2) Middle Low Prohibition of use(2) Middle Middle Delay time shortening mode 1 for 5-cell protection Middle High Delay time shortening mode 1 for 4-cell protection High Middle Delay time shortening mode 1 for 3-cell protection

NO.EA-401-230324 Delay Time Setting by CT1, CT2, and CT3 Pins CT1, CT2, and CT3 pins are used for setting each delay time of the overdischarge detection (tVDET2), the discharge overcurrent detection 1 (tVDET31) and the discharge overcurrent 2 (tVDET32) by connecting external capacitors CCTX. Each of tVDET2, tVDET31, and tVDET32 be calculated by the equation of CV = i∆t. (1) tVDET2 setting by external capacitor CCT1 tVDET2 = CCT1 (nF) × V DCT1 / I CT1 For example, if CCT1 = 33 nF, VDCT1 = 1.80 V, and I CT1 = 500 nA, tVDET2 = 118.8 ms. (2) tVDET31 setting by external capacitor CCT2 tVDET31 = CCT2 (nF) × VDCT2 / I CT2 For example, if CCT2 = 3.3 nF, VDCT2 = 1.50 V, and I CT2 = 500 nA, tVDET31 = 9.9 ms. (3) tVDET32 setting by external capacitor CCT3 tVDET32 = CCT3 (nF) × VDCT3 / I CT3 For example, if CCT3 = 3.3 nF, VDCT3 = 1.50 V, and I CT3 = 3 µA, tVDET32 = 1.65 ms.

NO.EA-401-230324 Temperature Protection by External NTC The R5650T has three temperature detector s to protect the c harge high temperature, the charge low temperature, and the discharge high temperature. VRT and TEP pins are used to supervise the temperature. VRT pin supplies a voltage divided between external series resistors of RTEP and NTC to TEP pin. The temperature is supervised only for 10 ms in the 1 s period to reduce supply current between R TEP and NTC. The discharge high temperature is detected when the supervised temperature is greater than T DDH in discharge state, and DOUT pin becomes “Low” to stop the discharge current. After that, the discharge high temperature is released when the supervised temperature is lower than TRDH, and DOUT pin becomes “High” to permit discharging. The charge high temperature is detected when the supervised temperature is greater than T DCH in non-discharge state, and COUT pin becomes “Hi-Z” to stop the charge current. After that, the charge high temperature is released when the supervised temperature is lower than TRCH, and COUT pin becomes “High” to permit charging. The charge low temperature is detected when the supervised temperature is lower than T DCL in non -discharge state, and COUT pin becomes “Hi -Z” to stop the charge current. After that, the charge low temperature is released when the supervised temperature is greater than TRCL, and COUT pin becomes “High” to permit charging. VMP pin supervises the discharge current by its input voltage. After detecting the charge high / low temperature, these protected states are released immediately when VMP pin voltage (VVMP) becomes higher than VDSG. The device has internal fixed delay times for temperature protection. For example, in the case of detecting the discharge high temperature, the internal timer counts 64 ms until the discharge high temperature is detected. Detecting and releasing at other temperatures also are set at the same delay time. Since VRT pin supplies a voltage source for the voltage divider. In standby mode, the temperature protection does not work. Reference resistance values for RTEP and NTC (1) ・RTEP : 33 kΩ ±1% ・NTC : 10 kΩ ±1% (Ta = 25°C, B-value(B25/85) = 3435K ±1% COUT and DOUT settings for temperature protection (1) Refer to Technical Notes on External Components for recommended parts. State Pin to 0°C (TDCL) 0°C (TDCL) to 45°C (TDCH) 45°C (TDCH) to 70°C (TDDH) 70°C (TDDH) and more Charge COUT Hi-z High Hi-z Hi-z DOUT High High High Low Discharge COUT High Hi-z DOUT High Low

NO.EA-401-230324

0 V Battery Charging [R5650TxxxxA / B Only]

Charging to each cell is enabled when COUT pin is “High” even if the voltage of one or more cells is 0 V. Since COUT pin is impossible to maintain the “High” output when the power supply voltage (V DD) becomes lower than 2.5 V, VDD of 2.5 V or more must be provided to charge cells. The below reference circuit indicates the charge control FET and its surrounding circuits. The input voltage of FET gate is the divided voltage between COUT and Charger Minus, V DIV. So, it is necessary to satisfy following condition to turn on the FET when its threshold voltage is defined as VTH. VDIV = (VCOUT – VCHGM) X RCO2 / (RCO1 + RCO2) > VTH

0 V Battery Detector: VNOCHG-n (n = 1, 2, 3, 4, 5) [R5650TxxxxC / D Only]

Since the device detects a charge inhibition voltage for each cell, if either of cell voltages is lower than the charge inhibition voltage, the charge inhibition is detected with the charger being connected to the battery pack. After detecting, COUT pin becomes “Hi-z”, and charging stops. RCO1 RCO2 COUT VCOUT VCHGM VDIV Charger Minus Charge Control FET FET Gate

NO.EA-401-230324 Timing Charts Overcharge Voltage and Charge Overcurrent Timing Diagram for Overcharge Voltage and Charge Overcurrent VDET11 VREL11 VC1 -VC2 t tVREL1 tVDET1 tVDET1 tVREL1 tVDET4 VDD COUT tVREL4 t VDET12 VREL12 VC2 -VC3 t VDET13 VREL13 VC3 -VC4 t VDET14 VREL14 VC4 -VC5 t Charge/ Discharge current t charge discharge connect charger VSS SENS VDET4 t VDET15 VREL15 VC5 -VSS t VSS VMP VREL4 t openconnect chargerdisconnect charger disconnect charger & connect load disconnect charger & connect load connect abnormal charger

NO.EA-401-230324 Overdischarge, Discharge Overcurrent 1/2, and Short-circuit Detection Timing Diagram for Overdischarge, Discharge Overcurrent, and Short-circuit VR12V DOUT VSS tVDET21 tVDET21 tVREL21 tVDET31 tshorttVDET32 tVREL3tVREL21 tVREL3 tVREL3 t VREL21 VDET21 VC1-VC2 t t VREL22 VDET22 VC2-VC3 t VREL23 VDET23 VC3-VC4 t VREL24 VDET24 VC4-VC5 t VREL24 VDET24 VC5-Vss t connect charger connect load open open open connect load connect load connect load connect charger connect load open VSS VDET4 SENS VDET3-1 VDET3-2 Vshort t VSS VMP t Charge/ Discharge current charge discharge

NO.EA-401-230324 Temperature Detection Charge/Discharge/ Temperature detection (inner signal) VMP Temperature detecting time (10 ms) COUT TDCUT TDCOT TDDOT 10mV DOUT tTDCUT tTRCUT tTDCOT tTDDOT tTRDOT tTRCOT Scan cycle time (1s) Timing Diagram for Temperature Detection

NO.EA-401-230324

APPLICATION INFORMATION

Typical Application Circuits The discharge current flows through a parasitic diode of its FET w hen the FET connected to COUT pin is turned OFF and a load is connected between Pack+ and Pack -. And, the charge current flows through the parasitic diode of its FET when the FET connected to DOUT pin is turned OFF and a charger is connected between Pack+ and Pack-. Thus, the FETs must be enough to flow the current. CVC1 VC1 VC2 CELL1 CELL2 CELL3 CELL4 CELL5 VC3 VC4 VC5 VSS VMP COUTDOUT SEL1 SEL2 CT1 CT2 RVC1 RVC2 RVC3 RVC4 RVC5 CVC2 CVC3 CVC4 CVC5 CVDDRVDD CCT1 CCT2 RSENS RDRAIN RCO1 RCO2 RVMP ZD1 TEP VR NTC CVR MCOMDO MDR R5650T VRT VDD SENS DRAIN RTEP CT3 CCT3 RSE Typical Application Circuit for 5-cell Protection

NO.EA-401-230324 CVC1 VC1 VC2 CELL1 CELL2 CELL3 CELL4 CELL5 VC3 VC4 VC5 VSS VMP COUTDOUT SEL1 SEL2 CT1 CT2 RVC1 RVC2 RVC3 RVC4 RVC5 CVC2 CVC3 CVC4 CVC5 CVDDRVDD CCT1 CCT2 RSENS RDRAIN RCO1 RCO2 RVMP ZD1 RSE TEP VR NTC CVR MCOMDO MDR R5650T VRT VDD SENS DRAIN RTEP CT3 CCT3 RVSS DVSS Typical Application Circuit for 5-cell Protection with Diode (DVSS) If <Battery- to Board-> line resistance is large, the discharge overcurrent causes a voltage difference between Battery- and VSS. Since VDET31, VDET32, and VSHORT become smaller than normal values owing to the difference value, please take notice to <Battery- to Board-> line resistance.

NO.EA-401-230324 CVC1 VC1 VC2 CELL1 CELL2 CELL3 CELL4 VC3 VC4 VC5 VSS VMP COUTDOUT SEL1 SEL2 CT1 CT2 RVC1 RVC2 RVC3 RVC4 CVC2 CVC3 CVC4 CVDDRVDD CCT1 CCT2 RSENS RDRAIN RCO1 RCO2 RVMP ZD1 TEP VR NTC CVR MCOMDO MDR R5650T VRT VDD SENS DRAIN RTEP CT3 CCT3 RSE Typical Application Circuit for 4-cell Protection

NO.EA-401-230324 CVC 1 VC1 VC2 CELL1 CELL2 CELL3 VC3 VC4 VC5 VSS VMP COUTDOUT SE L1 SE L2 CT1 CT2 RVC 1 RVC 2 RVC 3 CVC 2 CVC 3 CVD DRVD D CCT1 CCT2 RSE N S RDRA I N RCO1 RCO2 RVM P ZD1 TEP VR NTC CVR MCOMDO MDR R5650T VRT VDD SENS DRAIN RTEP CT3 CCT3 RSE Typical Application Circuit for 3-cell Protection

NO.EA-401-230324 External Components Selection Guide

• The typical application circuit diagrams are just examples. The operation in application circuits is not guaranteed. Be sure to perform a sufficient evaluation with the external components under the actual usage conditions for selection.
• Be careful not to apply the overvoltage and the overcurrent which exceed the rating to the protection IC and external components. Especially, select an FET with enough current capacity to endure the large current because a large current might flow through the FET during the time between an overcharge detection a blown fuse.
• When the cells are connected to IC first, the minus terminal of the lowest voltage side cell should be connected to IC at the first and other terminals should be connected to IC in turn from lower voltage side. Symbol Value (Typ.) Range Unit Remarks(1) RVDDX 330 330 to 1000 Ω Refer to Technical Note [1]. RVC1X 330 330 to 1000 Ω Refer to Technical Note [2]. RVC2X 330 330 to 1000 Ω RVC3X 330 330 to 1000 Ω RVC4X 330 330 to 1000 Ω RVC5X 330 330 to 1000 Ω RSENS 100 1 or more mΩ Depending on set value for overcurrent RSE 1 1 to 10 kΩ Refer to Technical Note [3]. RDRAIN 75 Note [4] kΩ Refer to Technical Note [4]. RCO1 1 Note [4] MΩ RCO2 2 Note [4] MΩ RVMP 0.01 0.01 to 10 MΩ CVDDX 1 0.1 to 1 µF Refer to Technical Note [1]. CVC1X 0.1 0.1 µF Refer to Technical Note [2]. CVC2X 0.1 0.1 µF CVC3X 0.1 0.1 µF CVC4X 0.1 0.1 µF CVC5X 0.1 0.1 µF CCT1 33 10 to 1000 nF - CVR 1 1 µF Refer to Technical Note [6]. ZD1 30 30 or less V Refer to Technical Note [7]. Recommended Component: MM1Z30 0.5W 30V J SOD-123 EIC RTEP 33 33 kΩ NTC 10 10 kΩ Recommended Components: 103AT-4-040 (SEMITEC) NTCG103JF103F or NTCG163JF103F(TDK) D1 - - Refer to Technical Note [10]. (1) Refer to “Technical Notes for External Components” for details.

NO.EA-401-230324 Symbol Value (Typ.) Range Unit Remarks(1) MCO - - Refer to Technical Note [8]. MDO - - MDR - - Refer to Technical Note [9]. Technical Notes on the Selection Components 【1】 RVDD and CVDD stabilize the supply voltage to the device. 【2】 RVCx and CVCx.stabilize the voltage fluctuation. If RVCx is large, the detection voltage increases due to the internal conduction current of the device. 【3】 Since a large RSE may shift the overcurrent detection voltage, a resistor of appror.10kΩ is appropriate. 【4】 Choose appropriate values for R DRAIN, RCO1, and R CO2 to satisfy the next equation, otherwise, the release from the discharge overcurrent and the short-circuit may be impossible. 𝑅𝑅𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 < 𝑉𝑉𝐷𝐷𝑅𝑅𝑅𝑅3 × (𝑅𝑅𝐶𝐶𝐶𝐶1 + 𝑅𝑅𝐶𝐶𝐶𝐶2) (𝑉𝑉𝐷𝐷𝐷𝐷 − 𝑉𝑉𝐷𝐷𝑅𝑅𝑅𝑅3⁄ ) I f small R CO1 or RCO2 is set, when the output of C OUT is "H", the supply current of protection circuit board increases. If large R CO1 or RCO2 is set, when the output of C OUT is "Hi-z", the speed for pull - down the gate of the charge FET becomes slow and turning off the FET will be slow. 【5】 If too small CCT2 or CCT3 is set, the discharge overcurrent detection delay time 1(tVDET31) or 2 (tVDET32) becomes shorter than the short-circuit delay time (tSHORT). 【6】 Connecting a 1.0µF capacitor to VR pin is required to make a stable VR output 【7】 It is recommended that a zener diode is connected to prevent a high voltage to the device. The zener diode must be directly connected between VDD pin of the device and VSS pin. 【8】 As for the charge control FET (MCO) and the discharge control FET (MDO), please make a sufficient consideration to their maximum voltage tolerance, current rating, maximum power consumption, and peak consumption when short-circuit. 【9】 As for the pull -down FET (MDR), please make a sufficient consideration to its maximum voltage tolerance. 【10】 Diode (D1) is required to prevent a drop in the VDD pin voltage (V DD), along with the battery voltage drop during the short-circuit. (1) Refer to “Technical Notes for External Components” for details.

NO.EA-401-230324 TECHNICAL NOTES A peripheral component or the device mounted on PCB should not exceed a rated voltage, a rated current or a rated power. When designing a peripheral circuit, please be fully aware of the following points.

• Please evaluate the product at the PCB level before use, as some symptoms may remain that cannot be confirmed by the evaluation at the IC level.
• When using any coating or underfill to improve moisture resistance or joining strength, evaluate them adequately before using. In certain materials or coating conditions, corrosion by contained co nstituents, current leakage by moisture absorption, crack and delamination by physical stress can happen. If the curing temperature of the coating material or underfill material exceeds the absolute maximum rating, the electrical characteristics of this product may change.
• When performing X -ray inspection in mass production process and evaluation build stage such as the product functions and characteristics confirmation, please confirm X-ray irradiation does not exceed 1.5Gy (absorbed dose for air).

POWER DISSIPATION TSSOP-20 PD-TSSOP-20-(85125)-JE- B i The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following measurement conditions are based on JEDEC STD. 51. Measurement Conditions Item Measurement Conditions Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Four-Layer Board) Board Dimensions 76.2 mm × 114.3 mm × 1.6 mm Copper Ratio Outer Layer (First Layer): Less than 10% of 62 mm Square Inner Layers (Second and Third Layers): Approx. 100% of 74.2 mm Square Outer Layer (Fourth Layer): Less than 10% of 62 mm Square Through-holes None Measurement Result (Ta = 25°C, Tjmax = 125°C) Item Measurement Result Power Dissipation 1380 mW Thermal Resistance (ja) ja = 72°C/W Thermal Characterization Parameter (ψjt) ψjt = 22°C/W ja: Junction-to-Ambient Thermal Resistance ψjt: Junction-to-Top Thermal Characterization Parameter Power Dissipation vs. Ambient Temperature Measurement Board Pattern 200 400 600 800 1000 1200 1400 1600 0 25 50 75 100 125 Power Dissipation (mW) Ambient Temperature (°C) 1380

PACKAGE DIMENSIONS TSSOP-20 Ver. A i

Ver. E i : Product Code … Refer to Part Marking List : Lot Number … Alphanumeric Serial Number R5650T (TSSOP-20) Part Markings NOTICE There can be variation in the marking when different AOI (Automated Optical Inspection) equipment is used. In the case of recognizing the marking characteristic with AOI, please contact our s ales or distributor before attempting to use AOI. R5650TxxxAA Part Marking List R5650TxxxBC Part Marking List R5650T401AA E401AA R5650T401BC E401BC R5650T402AA E402AA R5650T402BC E402BC R5650T403AA E403AA R5650T403BC E403BC R5650T405AA E405AA R5650T404BC E404BC R5650T406AA E406AA R5650T407BC E407BC R5650T409AA E409AA R5650T408BC E408BC R5650T410AA E410AA R5650T413BC E4 13 BC R5650T411AA E411AA R5650T414BC E4 14 BC R5650T412AA E412AA R5650T415BC E4 15 BC R5650T416AA E41 6 AA ⑦⑧⑨ ①②③④⑤⑥

1. T he products and the product specifications described in this document are subject to change or discontinuation of production without notice for reasons such as improvement. Therefore, before deciding to use the products, please refer to our sales representatives for the latest information thereon. 2. The materials in this document may not be copied or otherwise reproduced in whole or in part without the prior written consent of us. 3. This product and any technical information relating thereto are subject to complementary export controls (so- called KNOW controls) under the Foreign Exchange and Foreign Trade Law, and related politics ministerial ordinance of the law. (Note that the complementary export controls are inapplicable to any application-specific products, except rockets and pilotless aircraft, that are insusceptible to design or program changes.) Accordingly, when exporting or carrying abroad this product, follow the Foreign Exchange and Foreign Trade Control Law and its related regulations with respect to the complementary export controls. 4. The technical information described in this document shows typical characteristics and example application circuits for the products. The release of such information is not to be construed as a warranty of or a grant of license under our or any third party's intellectual property rights or any other rights. 5. The products listed in this document are intended and designed for use as general electronic components in standard applications (office equipment, telecommunication equipment, measuring instruments, consumer electronic products, amusement equipment etc.). Those customers intending to use a product in an application requiring extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of the product could result in human injury or death should first contact us.

• Aerospace Equipment
• Equipment Used in the Deep Sea
• Power Generator Control Equipment (nuclear, steam, hydraulic, etc.)
• Life Maintenance Medical Equipment
• Fire Alarms / Intruder Detectors
• Vehicle Control Equipment (automotive, airplane, railroad, ship, etc.)
• Various Safety Devices
• Traffic control system
• Combustion equipment In case your company desires to use this product for any applications other than general electronic equipment mentioned above, make sure to contact our company in advance. Note that the important requirements mentioned in this section are not applicable to cases where operation requirements such as application conditions are confirmed by our company in writing after consultation with your company. 6. We are making our continuous effort to improve the quality and reliability of our products, but semiconductor products are likely to fail with certain probability. In order to prevent any injury to persons or damages to property resulting from such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy feature, fire containment feature and fail-safe feature. We do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products. 7. The products have been designed and tested to function within controlled environmental conditions. Do not use products under conditions that deviate from methods or applications specified in this datasheet. Failure to employ the products in the proper applications can lead to deterioration, destruction or failure of the products. We shall not be responsible for any bodily injury, fires or accident, property damage or any consequential damages resulting from misuse or misapplication of the products. 8. Quality Warranty 8-1. Quality Warranty Period In the case of a product purchased through an authorized distributor or directly from us, the warranty period for this product shall be one (1) year after delivery to your company. For defective products that occurred during this period, we will take the quality warranty measures described in section 8-2. However, if there is an agreement on the warranty period in the basic transaction agreement, quality assurance agreement, delivery specifications, etc., it shall be followed. 8-2. Quality Warranty Remedies When it has been proved defective due to manufacturing factors as a result of defect analysis by us, we will either deliver a substitute for the defective product or refund the purchase price of the defective product. Note that such delivery or refund is sole and exclusive remedies to your company for the defective product. 8-3. Remedies after Quality Warranty Period With respect to any defect of this product found after the quality warranty period, the defect will be analyzed by us. On the basis of the defect analysis results, the scope and amounts of damage shall be determined by mutual agreement of both parties. Then we will deal with upper limit in Section 8-2. This provision is not intended to limit any legal rights of your company. 9. Anti-radiation design is not implemented in the products described in this document. 10. The X-ray exposure can influence functions and characteristics of the products. Confirm the product functions and characteristics in the evaluation stage. 11. WLCSP products should be used in light shielded environments. The light exposure can influence functions and characteristics of the products under operation or storage. 12. Warning for handling Gallium and Arsenic (GaAs) products (Applying to GaAs MMIC, Photo Reflector). These products use Gallium (Ga) and Arsenic (As) which are specified as poisonous chemicals by law. For the prevention of a hazard, do not burn, destroy, or process chemically to make them as gas or power. When the product is disposed of, please follow the related regulation and do not mix this with general industrial waste or household waste. 13. Please contact our sales representatives should you have any questions or comments concerning the products or the technical information. Official website https://www.nisshinbo-microdevices.co.jp/en/ Purchase information https://www.nisshinbo-microdevices.co.jp/en/buy/