R5601X NISSHINBO | Alldatasheet

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Technical content

Lithium-Ion/ Lithium Polymer Battery Management Analog Front-End No.EA-356-210506 OVERVIEW The R5601x is a battery management IC designed for use with a microcontroller and features and analog front-end with overcurrent protection for multi-cell Li-ion/ Li-polymer battery packs. The R5601x supports battery packs consisting of up to 5 cells in series. The R5601x provides a cell selection switch, a decoder that selects the cell to be monitored based on input signals from external devices, an amplifier that outputs the monitored battery voltage, an additional amplifier that monitors charge and discharge currents based on the voltage at both ends of external resistors and then converts the current values to voltage and outputs the voltage values, a low-current voltage regulator that provides voltage to the MCU, a thermal shutdown circuit, an alert output pin that notifies external devices of any errors, and various logic circuits. The R5601x is offered in a 16-pin TSSOP or a 20-pin QFN package.

FEATURES

Low Consumption Mode: Typ. 6.5 µA (Only VR and wakeup function operating) Standby Mode: Max. 2.0 µA Output-referred Voltage Error: ±5.4 mV R5601xxxxAC Gain: 5 ±0.8%, 10 ±1.0%

  • Short-circuit Current Detection ······················ The detector threshold/ time are settable using I2C interface. Detector Threshold: 0.10, 0.15, 0.20, 0.40 V Delay Time: 50, 100, 200, 400, 800 µs Temp. Characteristics: ±30 ppm/°C (0 ≤ Ta ≤ 50°C, Ta ≈ Tj)
  • Voltage Regulator Output Voltage ·················· 3.3 V, Output Voltage Accuracy: 1.5% (−20°C to 60°C) Output Current Limit: Min. 30 mA to reduce the consumption current. to reduc e the consumption current.

No.EA-356-210506

APPLICATIONS

  • Power Tools
  • Power Storages
  • Cordless Vacuum Cleaners/ Robot Vacuum Cleaners SELECTION GUIDE The I2C slave address and the IC functions are user-selectable options with the R5601x. Selection Guide Product Name Package Quantity per Reel Pb Free Halogen Free R5601TxxxYY-E2-FE TSSOP-16 2,500 pcs Yes Yes R5601LxxxYY-E1 QFN0303-20-P28 4,000 pcs Yes Yes xxx: Specify the I2C slave address from below. xxx I2C Slave Address 047 2Fh 063 3Fh YY: Specify the IC functions from below. YY VROUT Output Voltage Voltage Monitoring Gain Current Monitoring Gain External Output Reference Voltage AA 3.3 V 0.6 10/40 3.000 V AC 3.3 V 0.6 5/10 3.000 V

No.EA-356-210506 BLOCK DIAGRAM R5601x Block Diagram VROUT VC5 VC4 VC3 VBAT VCELL Decoder (Cell selector) SDA VREF circuit VREF Enable MUX LDO differential Amplifier Cell Balance FET Controller Thermal shutdown VC2 VC1 SCL I2C Interface VIOUT ALT RSP Rsens Current Sense Amplifier OUTPUT Controller Over Current Protector RSN MUX VSS OTP

No.EA-356-210506 PIN DESCRIPTIONS R5601T (TSSOP-16) R5601T (TSSOP-16) Pin Configuration R5601T Pin Descriptions Pin No. Pin Name Description

1 VROUT Voltage Regulator Output Pin

2 VCELL Cell Voltage Monitoring Output Pin

3 VREF External Reference Voltage Output Pin

4 VIOUT Current Monitoring Output Pin

5 ALT Alert I/O Pin

6 SDA Serial Data I/O Pin

7 SCL Serial Clock Input Pin

8 RSP RSENS Positive Input Pin

9 RSN RSENS Negative Input Pin

10 VSS IC Ground Pin

11 VC5 Positive Terminal of Cell 5

12 VC4 Positive Terminal of Cell 4

13 VC3 Positive Terminal of Cell 3

14 VC2 Positive Terminal of Cell 2

15 VC1 Positive Terminal of Cell 1

16 VBAT Power Supply Pin

No.EA-356-210506 R5601L (QFN0303-20-P28) R5601L (QFN0303-20-P28) Pin Configuration R5601L Pin Description Pin No. Pin Name Description

1 VCELL Cell Voltage Monitoring Output Pin

2 VREF External Reference Voltage Output Pin

3 VIOUT Current Monitoring Output Pin

4 ALT Alert I/O Pin

5 SDA Serial Data I/O Pin

6 SCL Serial Clock Input Pin

7 RSP RSENS Positive Input Pin

8 NC No Connection

16 NC No Connection

17 VBAT Power Supply Pin

18 NC No Connection

19 VROUT Voltage Regulator Output Pin

20 NC No Connection

∗ The tab on the bottom of the package is substrate level (VSS). It is recommended that the tab be connected to the VSS pin on the board, or otherwise be left floating. 1 3 4 5 1415 13 12 11 <TOP VIEW>

No.EA-356-210506 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings (Ta = 25°C, VSS = 0 V) Symbol Description Rating Unit VBAT Power Supply Voltage −0.3 to 32 V VC1 VC2 VC3 VC4 VC5 VSDA VSCL VRSN VRSP VALT [Input Voltage] Positive Terminal Pin Voltage of CELL1 Positive Terminal Pin Voltage of CELL2 Positive Terminal Pin Voltage of CELL3 Positive Terminal Pin Voltage of CELL4 Positive Terminal Pin Voltage of CELL5 SDA Input Voltage SCL Input Voltage RSN Pin Input Voltage RSP Pin Input Voltage ALT Pin Input Voltage VC2 −0.3 to VC2 +9.0, VC2 −0.3 to VSS +32 VC3 −0.3 to VC3 +9.0 VC4 −0.3 to VC4 +9.0, VC4 −0.3 to VSS + 24 VC5 −0.3 to VC5 +9.0 VSS −0.3 to VSS +9.0 VSS −0.3 to VROUT +0.3 VSS −0.3 to VROUT +0.3 VROUT −6.0 to VROUT +0.3 VROUT −6.0 to VROUT +0.3 −0.3 to 32 V V V V V V V V V V VCELL VIOUT VREF VROUT [Output Voltage] Cell Voltage Monitoring Output Voltage Current Monitoring Output Voltage External Reference Voltage Output Voltage VR Output Voltage VSS −0.3 to 6.5 VSS −0.3 to 6.5 VSS −0.3 to 6.5 VSS −0.3 to 6.5 V V V V ICELL IIOUT IREF IOUT [Output Current] Cell Voltage Monitoring Output Current Current Monitoring Output Current External Reference Voltage Output Current VR Output Current 1.0 1.0 1.0 mA mA mA mA PD Power Dissipation Refer to Appendix “Power Dissipation”. Tj Junction Temperature Range −40 to 125 °C Tstg Storage Temperature Range −55 to 125 °C ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause permanent damage and may degrade the lifetime and safety for both device and system using the device in the field. The functional operation at or over these absolute maximum ratings is not assured. RECOMMENDED OPERATING CONDITIONS Recommended Operating Conditions Symbol Item Rating Unit VBAT Input Voltage 4.0 to 22.5 V Ta Operating Temperature Range −40 to 85 °C RECOMMENDED OPERATING CONDITIONS All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating conditions. The semiconductor devices cannot operate normally over the recommended operating conditions, even if they are used over such conditions by momentary electronic noise or surge. And the semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions.

No.EA-356-210506

ELECTRICAL CHARACTERISTICS

R5601x Electrical Characteristics (Ta = 25°C, unless otherwise noted) Symbol Parameter Conditions Min. Typ. Max. Unit Input Section RCBn Built-in FET ON Resistance VCN = 4.0 V 10 Ω ILVCn Cell Voltage Input Leakage VCN = 4.5 V, Built-in FET: OFF Cell Voltage Monitoring: OFF 0.3 µA Voltage Regulator ∆VROUT Output Voltage Temperature Characteristics −20°C ≤ Ta ≤ 60°C, IOUT = 1 mA(1) −1.5 1.5 % ILIM Output Current Limit 30 mA ISC Short Current Limit VROUT = 0 V 20 mA VDIF I/O Voltage Difference IOUT = 30 mA, VROUT = 3.3 V RBAT = 10 Ω 0.7 V TSDD Thermal Shutdown Temperature (2) 150 °C TSDR Thermal Shutdown Released Temperature (2) 125 °C Cell Voltage Monitoring / External Reference Voltage VVCIN Cell Voltage Input Range 1.5 4.5 V VVCA Cell Voltage Monitoring Accuracy(3) (Output- Referred Voltage Error) IVC = 1 µA −5.4 5.4 mV −20°C ≤ Ta ≤ 60°C, IVC = 1 µA(1) −7.8 7.8 GVC Cell Voltage Monitoring Gain IVC = 1 µA 0.6 IVC Cell Voltage Monitoring Pin Output Current VBAT = 18 V 10 µA tvcset Cell Voltage Monitoring Output Delay Time CCEL = 0.1 µF(2) 200 µs VREF External Reference Voltage(4) IREF = 1 µA 2.9965 3.000 3.0035 V ∆VREF / ∆Ta External Reference Voltage Temperature Characteristics 0°C ≤ Ta ≤ 50°C, IREF = 1 µA (1) ±30 ppm/ °C −20°C ≤ Ta ≤ 60°C, IREF = 1 µA (1) ±60 IREF External Reference Voltage Output Current 10 µA (1) Measurements are performed in an environment in which Tj is nearly equal to Ta. High and low temperature tests are not executed at the mass production line, therefore, this specification in the specified temperature range is guaranteed by design. (2) guaranteed by design (3) The Input-referred voltage error can be calculated as VVCA / GVC. This is the after-correction value. (4) This is the after-correction value.

No.EA-356-210506 R5601x Electrical Characteristics (Continued) (Ta = 25°C, unless otherwise noted) Symbol Parameter Conditions Min. Typ. Max. Unit Current Monitor /Short-Circuit Protection VCUIN10 Voltage Input Range (Gain 10) −25 225 mV V CUIN40 Voltage Input Range (Gain 40) −6.25 56.25 mV VCUIN5 Voltage Input Range (Gain 5) −50 450 mV GCU10 Current Monitoring Gain 10 (1) (2) 10 GCU40 Current Monitoring Gain 40 (1) (2) 40 GCU5 Current Monitoring Gain 5 (1) (2) 5 GCUA10 Current Monitoring Gain Accuracy 10 When GCU10 is selected(1) −1.0 1.0 % GCUA40 Current Monitoring Gain Accuracy 40 When GCU40 is selected(1) −2.0 2.0 % GCUA5 Current Monitoring Gain Accuracy 5 When GCU5 is selected(1) −0.8 0.8 % VCU0 Zero-Current Output VRSP = 0 V 2.5 V ICU Current Monitoring Output Current 10 µA VSHORT Short-Circuit Detector Threshold Setting Range four-steps variable settings via I2C: VSTACC Short-Circuit Detector Threshold Accuracy −10 10 % tSHORT Short-Circuit Detect Output Delay Time Setting Range five-steps variable settings via I2C: 50, 100, 200, 400, 800 µs 50 800 µs tSTACC Short-Circuit Detect Output Delay Time Accuracy VRSP: 0V -> 1 V, VSHORT = 0.4 V TSHORT = 50 µs 100 µs TSHORT ≥ 100 µs −50 50 % (1) Settings depending on the preset product code. (2) Calculated from the minimum and maximum input voltage range at each gain.

No.EA-356-210506 R5601x Electrical Characteristics (Continued) (Ta = 25°C, unless otherwise noted) Symbol Parameter Conditions Min. Typ. Max. Unit Input Function VIHDA SDA “High” Input Voltage VROUT = 3.3 V VROUT x 0.8 V VILDA SDA “Low” Input Voltage VROUT = 3.3 V VROUT x 0.2 V VIHCL SCL “High” Input Voltage VROUT = 3.3 V VROUT x 0.8 V VILCL SCL “Low” Input Voltage VROUT = 3.3 V VROUT x 0.2 V VIHAL ALT “High” Input Voltage In standby mode 2.0 V VILAL ALT “Low” Input Voltage In standby mode 0.3 V IIHDA SDA “High” Input Current VROUT = 3.3 V −1 1 µA IIHCL SCL “High” Input Current VROUT = 3.3 V −1 1 µA IIHAL ATL “High” Input Current VBAT = 22.5 V −1 1 µA Output Function VOLDA SDA “Low” Output Voltage IOL = 3 mA, VROUT = 3.3 V 0.4 V VOLAL ALT “Low” Output Voltage IOL = 50 µA, VROUT = 3.3 V 0.4 V Wakeup /Standby Function VPOR Power ON Reset Voltage 2.0 2.5 V VWUP Wakeup Voltage Setting Range variable settings via I2C: 10 mV, 20 mV, 40 mV, or 80 mV. 10 80 mV VWUPAC Wakeup Voltage Accuracy VWUP = 10 mV −3 3 mV 20 mV ≤ VWUP −25 25 % twupdl Wakeup Delay Time Setting Range variable settings via I2C: 2 ms, 4 ms, 8 ms, 16 ms, 32 ms, 64 ms 2 64 ms twupac Wakeup Delay Time Accuracy TWUP ≤ 4 ms −50 50 4 ms < TWUP −30 30 ISS1 VBAT Supply Current 1 Normal mode, VCX = 3.7 V 36 48 µA IVCEL Cell Voltage Monitoring Operating Current VCX = 3.7 V 10 µA IVIO Current Monitoring Operating Current VCX = 3.7 V 10 µA IVREF External Reference Voltage Operating Current VCX = 3.7 V 10 µA ISS2 VBAT Supply Current 2 Low Power Mode (Only VR and wakeup function operating), VCX = 3.7 V 6.5 9.0 µA ISTB Standby Current VCX = 3.7 V 1.5 2.0 µA

No.EA-356-210506 R5601x Electrical Characteristics (Continued) (Ta = 25°C, unless otherwise noted) Symbol Parameter Conditions Min. Typ. Max. Unit Serial Interface AC Characteristics fclk SCL Clock Frequency 400 kHz tclk SCL Clock Cycle 2.5 µs tscll SCL Clock “Low” Time 1.3 µs tsclh SCL Clock “High” Time 0.6 µs tsu:sta Start Condition Setup Time 0.6 µs tsu:dat Data Setup Time 200 ns tsu:sto Stop Condition Setup Time 0.6 µs thd:sta Start Condition Hold Time 0.6 µs thd:dat Data Hold Time 0 ns tr SDA and SCL Rise Time(1) 300 ns tf SDA and SCL Fall Time(1) 300 ns tpl:dat SDA “Low” Determination Time after the Falling of SCL 0.9 µs tpz:dat SDA “High” Determination Time after the Falling of SCL 0.9 µs tsp Removal Spike Width by Input Filters 50 ns CB Capacitive Load for SDA and SCL Bus Lines 50 pF AC Specifications for the I2C Bus (Data Transfer Method) (1) The relationship between the I2C bus capacity (CB) and the pull-up resistance values (RP: 3.3 kΩ is recommended). S SCL tHD;STA tSCLH tSCLL tSCL tf tPL;DAT SDA(IN) SDA(OUT) tHD;DAT tSU;DAT tPZ;DAT tSP tr tSU;STA Sr tf tr P tSU;STO S Srスタートコンディション リピートスタートコンディションP ストップコンディション Start Condition Stop Condition Repeat-Start Condition

No.EA-356-210506 THEORY OF OPERATION Cell Voltage Monitoring The R5601x is an IC that monitors the voltage of each cell of lithium-ion and lithium polymer secondary batteries of up to five cells. If a cell whose voltage is to be monitored is selected by controlling the IC from the MCU via the I2C interface, the voltage of that cell will be multiplied by the gain and then output from the VCELL pin. Accordingly, the following equation can be obtained by calculating the battery voltage from the output voltage: Herein, the offset and the gain error are included in the output voltage, therefore values for adjustment are stored in the registers of each IC. Adjustment can be done by the next formula. Correction value for voltage monitoring offset: CVOS Correction value for voltage monitoring gain: CGVC Note: When you monitor the voltage between VC 5 and VSS, 0V should be input VCx+1. If there is no cell voltage output instruction from the external MCU, or if a cell voltage monitoring amplifier stop instruction has been issued, or if the R5601x is in standby mode, the output will be pulled down to the VSS by an internal resistor. To ensure accurate monitoring of the cell voltage, make measurements with the built-in FET switch turned off. If you do not do so, the input resistance and current will cause the voltage to drop when the current flows through the built- in FET switch, thereby preventing the expected level of voltage from being output from the VCELL pin. Internal FET Control By controlling the internal FET by the external MCU via the I2C Interface, the R5601x can flow the discharge current into the IC from each cell. The discharge current can be set by external resistor. When select external resistor, pay attention to the power dissipation of the external resistor and the input current tolerance of the IC. The internal FET must be controlled so that the adjacent internal FET is not also turned on at the same time. When selecting a cell for voltage monitoring during the internal FET’s on, the internal FET capability is limited. Gvc VvcVC VCx x = −+1 Gvc VCCGVCCVOSVvcVC VC x x x )1010 1 ( 1

No.EA-356-210506 Current Monitoring The R5601x outputs a current that flows through the RSENS resistor located between the RSN and RSP pins after conversion to a voltage. The R5601x always outputs a positive voltage, but outputs VCU0 at zero current. Because the voltage of the RSP pin is inversely amplified by the GCU gain, the output will be smaller than VCU0 when a discharge current flows and will be larger than VCU0 when the charging current flows. Moreover, the built-in multiplexer enables switching between RSP input and RSN input, in which case the following equation can be used by the host to adjust the current value to the more accurate ISENS value: GCU can be switched via I2C communication. The following table shows the amplifier input and output ranges. The ISENS range in the table shows discharge current as positive values and charging current as negative values. When RSENS is 1 mΩ and a 10-bit ADC is used GCU VCU0 [V] RSP Input Voltage Range [mV] VIOUT Output Voltage Range [V] ISENS Range [A] (RSENS = 1 mΩ) ISENS Resolution [mA] (When 10-bit ADC 5 2.5 −50 450 0.25 2.75 −50 450 586 10 2.5 −25 225 0.25 2.75 −25 225 293 When RSENS is 0.5 mΩ and a 10-bit ADC is used GCU VCU0 [V] RSP Input Voltage Range [mV] VIOUT Output Voltage Range [V] ISENS Range [A] (RSENS = 0.5 mΩ) ISENS Resolution [mA] (When 10-bit ADC 5 2.5 −50 450 0.25 2.75 −100 900 1172 10 2.5 −25 225 0.25 2.75 −50 450 586 When RSENS is 0.5 mΩ and a 12-bit ADC is used GCU VCU0 [V] RSP Input Voltage Range [mV] VIOUT Output Voltage Range [V] ISENS Range [A] (RSENS = 0.5 mΩ) ISENS Resolution [mA] (When 12-bit ADC 5 2.5 −50 450 0.25 2.75 −100 900 293 10 2.5 −25 225 0.25 2.75 −50 450 146 If the stop command is set for the external voltage reference output or the current monitoring amplifier by the MCU, or if the R5601x is in standby mode, the output will be pulled down to the VSS by an internal resistor. RSENS GCU RSN VCU RSP VCU ISENS

No.EA-356-210506 External Reference Voltage Output The R5601x outputs the reference voltage that is used by the external A/D converters and for current monitoring. If an external reference voltage output stop instruction is received from the external MCU or if the R5601x is in standby mode, the output will be pulled down to the VSS by the internal resistor. The externally output reference voltage has an offset against the preset value. This offset value is stored in the register. Short-circuit Current Detection The R5601x contains a function that detects a short-circuit current through the discharge path and makes the output of the ALT pin to "Low" by monitoring the RSP pin voltage as both ends of the resistor located on the discharge path. If the load is removed and identified opening the load, the output of the ALT pin can be changed into "Hi-Z" by a reset command from the external MCU. Not only the short detector threshold and delay time can be changed, but also the short-circuit detection function can be invalid by the external MCU command. Voltage Regulator The R5601x contains a 30-mA voltage regulator for operation of the external MCU. The voltage regulator operates when the voltage of the VBAT pin is between 4.0 and 22.5 V. When the R5601x is in standby mode, the output will be pulled down to the VSS by the internal resistor. The R5601x also contains a thermal shutdown function to protect itself from overheating. If the heat generated by the voltage regulator causes the junction temperature (Tj) to exceed 150°C (Typ.), the output driver will turn off to protect the IC, thereby causing the output of the voltage regulator to turn off. If the junction temperature (Tj) drops below 125°C (Typ.), the output driver will turn on and the output of the voltage regulator will turn on. Operation of the thermal shutdown function can be stopped from the external MCU. ALT pin Output Function The R5601x can drive the output of the ALT (normally Hi-Z) low to prevent the reporting of an event that the R5601x itself has detected to external devices. The output format of the ALT pin is N-channel Open Drain. Because information on an event that has been detected is stored in an internal register, the MCU can identify the event by reading the event information in the register via the I 2C interface. To return the ALT pin’s output from "Low" to "Hi-Z", write “0” to all EVT registers while R5601x is not detecting an event. Wakeup Function The R5601x has a wakeup function. When detected the increase of the voltage of the RSP pin by the action of the discharge current and the sense resistance (R SENS), the R5601x's action varies with modes. In the case of the standby mode, the R5601x is restored after a preprogrammed delay time. Also, in the case of the other modes except the standby mode, after the delay time, the R5601x sets the ALT pin to "Low" and provides notification of this event to the MCU. The RSP pin voltage and delay time for this event and the enabled / disabled of the wakeup circuit can be set by the MCU via the I2C interface. Standby Function The R5601x has a standby function. The MCU provides an instruction to switch to standby mode to the R5601x via the I2C interface. The R5601x can restore from the standby mode by the wakeup function, or else by the ALT pin's pulled-up.

No.EA-356-210506 I2C SERIAL COMMUNICATIONS Overview: The I2C interface for the R5601x chip is used in slave mode. I2C Interface Pins Signal Name I/O Polarity Description Remarks SDA I/O - Serial Data Input/ Output Open Drain SCL I - Serial Clock Input CMOS Input [Slave Address] The slave address consists of seven bits and is fixed as “xxxxxxx : yyh”. (For details about the settings of the slave address, see the Selection Guide.) [Read / Write Processing] The following are the specifications of the read/write processing as viewed from the MCU: 0: Write processing (Input the data transferred from the MCU at the rising edge of SCL) 1: Read processing (Output the data at the falling edge of SCL) Data Transfer Method (1) Start and stop conditions Basically, the I2C bus must remain in a constant state while the SCL signal level is high during data transfers, as shown in Figure A. Figure A. SCL and SDA Signals Both the SCL and SDA signals are high when no data is being transferred. If the SDA signal changes from high to low while both the SCL and SDA signals are high, a start condition occurs, and access processing starts. However, if the SDA signal changes from low to high while the SCL signal is high, a stop condition occurs and access processing ends. (See Figure B.) Start and stop conditions are always generated by the master. SCL SDA tSU;DAT tHD;DAT

No.EA-356-210506 Figure B. Start and Stop Conditions (2) Data transfer and acknowledgment (ACK) After a start condition is generated, data is transferred one byte (eight bits) at a time. Any number of bytes of data can be transferred in succession. An ACK signal is sent from the receiver to the sender to acknowledge that eight bits of data has been received. As soon as the clock pulse of the eighth bit of the SCL signal in the transfer data goes low, an ACK signal is generated that causes the sender that has been asserting the bus up to that point to release the SDA pin and the receiver to drive the SDA signal low. If there is another byte of transfer data to be received after the receiver has sent an ACK signal, the sender will transfer the data. If the master is the receiver, the master will not generate an ACK signal after the last byte of data has been sent from the slave in order to notify the sender device that the data transfer is complete. In this case, the slave which is the sender will leave the SDA pin in the released state so that the master can generate a stop condition. Figure C. Data Transfer and ACK Signal Basically, the I2C bus must remain in a constant state while the SCL signal is high during data transfers, as shown in Figure A. SCL SDA tHD;STA tSU;STO Start Condition Stop Condition Start Condition SCL from Master SDA from Transmitting SDA from Receiving ACK Signal

No.EA-356-210506 Data Write Method Figure D shows the data write format. 1st byte: Slave address + Write instruction. 2nd byte: Address of the internal register to which the data is to be written. 3rd byte: Data to be written to the address specified in the second byte. 4th and subsequent bytes: Data to be written to the automatically incremented address. The master issues a start condition, and the slave receives the first byte of data that follows the start condition and returns an ACK signal to the master. If the slave address that the slave receives matches its own address, the slave receives the second and subsequent bytes of data in order and returns an ACK signal to the master each time a byte is received. After all necessary data has been written, the master will issue a stop condition to end the write operation. If, however, the slave address that the slave receives does not match its own address, the slave will not return an ACK signal to the master. Figure D. Data Write Method D7 D0 D7 D0 D7 D0 D7 D0 Hi-Z SDA (IN) SDA (OUT) SCL Slave ACK Slave ACK Slave ACK Slave ACK 1st byte 2nd byte 3rd byte 4th byteS P Slave address W Resister address ｎ Address n Data Address n+1 Data Write data of master (MSB 1st tranfer) S : Start condition (from Master) P：Stop condition (from Master)

No.EA-356-210506 Data Read Method Figure E shows the data read format. 1st byte: Slave address + Write instruction. 2nd byte: Address of the internal register from which the data is to be read. 3rd byte: Slave address + Read instruction. 4th byte: Data to be read from the address specified in the second byte. 5th and subsequent bytes: Data to be read from the automatically incremented address. The master issues a start condition, and the slave receives the first byte of data that follows the start condition and returns an ACK signal to the master. If the slave address that the slave receives matches its own address, the slave receives the second byte of data and returns an ACK signal to the master. Next, the master issues a repeated start condition, sends the slave address and a read instruction with the third byte of data, and then switches the serial access direction. The data with the address specified as the second byte of data is read as the fourth byte of data, and the master issues an ACK signal. The fifth and subsequent bytes of data are read sequentially by automatically incrementing the address. When all necessary data has been read, the master does not return an ACK signal to notify the slave that the read processing has completed. Instead, the master issues a stop condition to end the read operation. Figure E. Data Read Method Master ACK D7 D0 D7 D0 D7 D0D7 D0 Hi-Z SDA (IN) SDA (OUT) SCL Slave ACK 1st byte 2nd byte 5th byte 6th byte S Slave address W Resister address n Address n+1 Data Address n+2 Data Write data from master (MSB 1st transfer) S:Start condition (from Master) P:Stop condition (from Master) Sr: Repeat start condition(from Master) D7 D0 D7 D0 3rd byte 4th byte Slave address R Sr Address n Data Master ACK Slave ACK Slave ACK Master NACK P Read data from slave (MSB 1st transfer)

No.EA-356-210506 Repeated Start Condition Figure F shows the format of a repeated start condition. The master issues a repeated start condition, and the slave receives the first byte of data that follows the repeated start condition and returns an ACK signal to the master. After a repeated start condition is issued, the write instruction writes data by using the same procedure that is used for a normal start condition. This is shown in the seventh to the tenth bytes of data in Figure F. After a repeated start condition is issued, the read instruction starts to read from the addresses specified as the second and eighth bytes of data in Figure F. Each time an ACK signal is returned from the master, the address is automatically incremented and the data at that address is read. Figure F. Repeated Start Condition D7 D7 D0 D7 D0D7 D0 SDA SCL Slave ACK 1st byte 2nd byte 5th byte 6th byte S Slave address W Resister address n Address n+1 Data Address n+2 Data Write data from master (MSB 1st transfer) S:Start condition (from Master) P:Stop condition (from Master) Sr:Repeat start condition (from Master) D7 D7 D0 3rd byte 4th byte Slave address R Sr Address n Data Master ACK Slave ACK Slave ACK Read data from slave (MSB 1st transfer) Master ACK Sr D7 D7 D0 7th byte 8th byte Slave address W Resister address m Slave ACK Slave ACK write read read write D7 D0 9th byte 10th byte Address m data Address m+1 Data Slave ACK Slave ACK Sr D7 D7 D0 11th byte 12th byte Slave address W Address m+1 data Slave ACK Master NACK write read D0D0 D7 D0 P

No.EA-356-210506 Error Processing

  • If an ACK signal is not returned from the slave during data write processing, temporarily terminate the write processing, issue a stop condition or repeated start condition, and the restart the write processing.
  • If, for some reason, a data transfer either has been stopped or has stopped during communication, issue another start condition and then restart the data transfer from scratch according to the specified procedure.
  • If the master device is turned off and then on again when the slave is active, communication might not be possible, depending on the slave status when the maser device is turned off (for example, when the slave is in read mode). In such cases, continue to send clock signals from the master, and issue a start condition when the slave receives an ACK signal from the master.

No.EA-356-210506

APPLICATION INFORMATION

Typical Applications（5 Cells /4 Cells / 3 Cells） For battery pack assembly, it is recommended to start with the VSS connection, followed by the (+) terminal of the lowest (most negative) cell, to avoid undesired current flowing from a cell to the IC. R5601x Typical Application for 5 Cells

No.EA-356-210506 R5601x Typical Application for 4 Cells R5601x VSS VC5 VC4 VC2 VC1 VC3 VROUT VREF VCEL MCU SDA SCL VBAT CBAT CVC1 CVC2 CVC3 CVC4 CVR CREF CCEL RVC1 RVC2 RVC3 RVC4 RSDA RSCL VIOUT CIO ALT RSN RSP RSENS RRSN RRSP CRSP CRSN RALT RBAT VROUT VROUT VROUT VROUT RVC5

No.EA-356-210506 R5601x Typical Application for 3 Cells R5601x VSS VC5 VC4 VC2 VC1 VC3 VROUT VREF VCEL MCU SDA SCL VBAT CBAT CVC1 CVC2 CVC3 CVR CREF CCEL RVC1 RVC2 RVC3 RVC4 RSDA RSCL VIOUT CIO ALT RSN RSP RSENS RRSN RRSP CRSP CRSN RALT RBAT VROUT VROUT VROUT VROUT

No.EA-356-210506 External Components List Symbol Typ. Unit Setting Range Remarks RBAT 10 Ω 10 or more Pay careful attention to the power dissipation for RBAT. RVC1 100 Ω 100 to 1000 (1) RVC2 100 Ω 100 to 1000 (1) RVC3 100 Ω 100 to 1000 (1) RVC4 100 Ω 100 to 1000 (1) RVC5 100 Ω 100 to 1000 (1) RSDA 3.3 kΩ 3.3 or more RSCL 3.3 kΩ 3.3 or more RALT 1 MΩ 1 or more RSENS 1 mΩ 0.5 or more (2) RRSN 1 kΩ 0.1 to 10 RRSP 1 kΩ 0.1 to 10 (3) CBAT 4.7 µF 1.0 or more CVC1 0.47 µF 0.1 or more CVC2 0.47 µF 0.1 or more CVC3 0.47 µF 0.1 or more CVC4 0.47 µF 0.1 or more CVC5 0.47 µF 0.1 or more CVR 1 µF 1.0 to 4.7 CREF 0.1 µF 0.1 to 1 CCEL 0.1 µF 0.1 to 1 CIO 0.1 µF 0.1 to 1 CRSN 0.1 µF CRSP 0.1 µF (3) Technical Notes for External Components

  • The typical application circuit diagrams are just examples. This circuit performance largely depends on the PCB layout and external components. In the actual application, fully evaluation is necessary. (1) This value affects internal FET current (2) RSENS affects the range and resolution of current monitoring. For detailed information, see tables in Current Monitoring section of THEORY OF OPERATION chapter. (3) This value affects short detector delay time and wake-up detector delay time.

No.EA-356-210506 REGISTER DESCRIPTION Address Map The table below shows the register address map. The data width of each internal register is eight bits, and data is accessed one byte at a time. Address Map of Internal Registers Address (hex) Settings R/W Remarks

00 Operation Mode Selection R/W

01 Cell Selection R/W

02 Built-in FET Control R/W

03 Current Monitoring, Short-Circuit Operation Settings R/W

04 Event Storage Register R/W

05 Wakeup Settings R/W

06 Short-Circuit Detection Settings R/W

07 External Output VREF Offset Correction Value R

08 Voltage Monitoring Offset Correction Value R

09 Voltage Monitoring Gain Correction Value R

Note: A hyphen (-) indicates an unused bit. It is not possible to write to register bits that are not used. Reading these register bits results in a “0” value. Operation Mode Selection Register (Read/Write) This register is used to set the operation mode. Address Name D7 D6 D5 D4 D3 D2 D1 D0

00 STB - STB [6:0]

Initial Value 0 0 0 0 0 0 0 0 1. STB [6:0] Setting a bit to “1” stops the corresponding internal circuit. The correspondence between each bit and its internal circuit is as follows: (1) Stopping the external reference voltage output automatically stops the current monitoring amplifier.

No.EA-356-210506 Cell Selection Register (Read/Write) This register selects a monitoring cell. Address Name D7 D6 D5 D4 D3 D2 D1 D0 Initial Value 0 0 0 0 0 0 0 0 SEL [2:0] Entering the values shown in the table below in the register decodes the values internally and multiplies each cell voltage by the gain before output from the VCELL pin. If the voltage monitoring amplifier has been stopped by setting the operation mode, no cell voltage will be output even though values have been entered in register SEL [x]. Combination of Cell Selection and SEL Register Input D2 D1 D0 VCELL 0 0 0 Pull-Down 0 0 1 Cell 1 Voltage Monitoring 0 1 0 Cell 2 Voltage Monitoring 0 1 1 Cell 3 Voltage Monitoring 1 0 0 Cell 4 Voltage Monitoring 1 0 1 Cell 5 Voltage Monitoring 1 1 0 Pull-Down 1 1 1 Pull-Down Built-in FET Switch Control Register (Read/Write) This register selects the cell whose built-in FET is to be turned on. Address Name D7 D6 D5 D4 D3 D2 D1 D0 Initial Value 0 0 0 0 0 0 0 0 The built-in FET is turned on by writing a “1” to the bit corresponding to the cell whose built-in FET is to be turned on. The correspondence of bit and cell is as follows: CB [0] (= D0): Turns on the built-in FET switch for the first cell. CB [1] (= D1): Turns on the built-in FET switch for the second cell. CB [2] (= D2): Turns on the built-in FET switch for the third cell. CB [3] (= D3): Turns on the built-in FET switch for the fourth cell. CB [4] (= D4): Turns on the built-in FET switch for the fifth cell. Built-in FETs must be controlled so that two adjacent FETs do not turn on simultaneously. When two adjacent FETs turn on, the status before writing is maintained.

No.EA-356-210506 Current Monitoring Settings Register (Read/Write) This register sets up current monitoring. Address Name D7 D6 D5 D4 D3 D2 D1 D0 Initial Value 0 0 0 0 0 0 0 0 RS [0] (= D0): Conversion from a VSS-RSP voltage when this bit is “0”. Conversion from a VSS-RSN voltage when this bit is “1”. RS [1] (= D1): Output gain is Low (1) when this bit is “0”. Output gain is High (1) when this bit is “1”. Event Storage Register (Read/Write) This register stores events detected by the R5601x. Address Name D7 D6 D5 D4 D3 D2 D1 D0 Initial Value 0 0 0 0 0 0 0 0 The correspondence of bit and event is as follows: EVT [0] (= D0): Detected a short-circuit. EVT [1] (= D1): Detected a momentary voltage drop. EVT [2] (= D2): Detected a wakeup. EVT [3] (= D3): Detected an error in the IC. Momentary voltage drop detection: the IC detects an internal reset condition by a drop of VROUT pin voltage (VROUT). Error detection in the IC: the IC detects an error to correction values stored in itself. When at least one of the above-mentioned registers becomes “1”, the output of ALT pin becomes "Low". To return the ALT pin’s output from "Low" to "Hi-Z", write “0” to all EVT registers while the R5601x is not detecting an event. (1) The value is different by the product code option.

No.EA-356-210506 Wakeup Settings Register (Read/Write) This register sets the voltage and the delay time of RSP that detects wakeup. Address Name D7 D6 D5 D4 D3 D2 D1 D0

05 WU - WUD [4:0] WUV [1:0]

Initial Value 0 0 0 0 0 0 0 0 Entering the values shown in the following table in the register decodes the values internally and sets the corresponding detection thresholds. Setting WUV [1] WUV [2] D0 Detector Threshold (mV) 1 0 0 10 2 0 1 20 3 1 0 40 4 1 1 80 Entering the values shown in the following table in the register decodes the values internally and sets the corresponding delay times at wakeup detection. Setting WUD [4] WUD [3] WUD [2] WUD [1] WUD [0] Delay Time (ms) 1 0 0 0 0 0 2 2 0 0 0 0 1 4 3 0 0 0 1 0 8 4 0 0 1 0 0 16 5 0 1 0 0 0 32 6 1 0 0 0 0 64 Any operations are not guaranteed other than the settings shown in the table above.

No.EA-356-210506 Short-circuit Detection Settings Register (Read/Write) The short-circuit detection voltage and the delay time are set to this register. Address Name D7 D6 D5 D4 D3 D2 D1 D0

06 SC SCD [3:0] SCV [3:0]

Initial Value 0 0 0 0 0 0 0 0 The short-circuit detector threshold is set as shown in the next table according to the registers SCV [3:0]. Any operations are not guaranteed other than the settings showing in the next table. Setting SCV [3] SCV [2] SCV [1] SCV [0] D0 Short-Circuit Detector Threshold (V) 1 0 0 0 0 0.400 2 0 0 0 1 0.200 3 0 1 0 1 0.150 4 0 0 1 1 0.100 The short-circuit detector output delay time is set as shown in the next table according to the registers SCD [3:0]. If "1" is set to two or more registers, the shorter delay time is set. Setting SCD [3] SCD [2] SCD [1] SCD [0] Short-Circuit Detect Output Delay Time (µs) 1 0 0 0 0 50 2 0 0 0 1 100 3 0 0 1 0 200 4 0 1 0 0 400 5 1 0 0 0 800

No.EA-356-210506 Offset Correction Value for External Output VREF Register (Read) This register stores the offset correction value for the R5601x external output VREF. Address Name D7 D6 D5 D4 D3 D2 D1 D0

07 RF RF [7] RF [6:0]

Initial Value Correction Value of Individual IC RF [0 to 6] (= D0 to D6): Expresses the absolute value of a VREF offset as 0 to 12.7 mV in 0.1 mV increments. RF [7] (= D7): Expresses the sign of a VREF offset. “0” indicates plus, and “1” indicates minus. For example, in our test environment, if the output is 2.9980 V when the external output VREF is set to 3.0000 V, −2.0 mV is stored in this register. Correction Value for Cell Voltage Monitoring Offset Register (Read) This register stores the offset correction value of the Cell voltage monitoring. Address Name D7 D6 D5 D4 D3 D2 D1 D0

08 VOS VOS [7] VOS [6:0]

Initial Value Correction Value of Individual IC VOS [0 to 6] (= D0 to 6): Reflects the absolute value of the correction value for cell voltage monitoring offset as 0 to 127. VOS [7] (= D7): Reflects the plus or minus sign of the cell voltage monitoring offset. ”0”: plus, “1”: minus. Correction Value for Cell Voltage Monitoring Gain Register (Read) This register stores the gain correction value of the Cell voltage monitoring. Address Name D7 D6 D5 D4 D3 D2 D1 D0

09 VCG VCG [7] VCG [6:0]

Initial Value Correction Value of Individual IC VCG [0 to 6] (= D0 to 6): Reflects the absolute value of the correction value for cell voltage monitoring gain as 0 to 127. VCG [7] (= D7): Reflects the plus or minus sign of the gain correction value for cell voltage monitoring. “0”: plus, “1”: minus.

POWER DISSIPATION TSSOP-16 Ver. B i The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following measurement conditions are based on JEDEC STD. 51-7. Measurement Conditions Item Measurement Conditions Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Four-Layer Board) Board Dimensions 76.2 mm × 114.3 mm × 1.6 mm Copper Ratio Outer Layers (First and Fourth Layers): Approx. 10%, 60 mm square Inner Layers (Second and Third Layers): Approx. 100%, 74.2 mm square Through-holes  0.85 mm × 44 pcs Measurement Result ( T a = 2 5 ° C , T j m a x = 125°C) Item Measurement Result Power Dissipation 850 mW Thermal Resistance (ja) ja = 118 °C/W Thermal Characterization Parameter (ψjt) ψjt = 35 °C/W ja: Junction-to-Ambient Thermal Resistance ψjt: Junction-to-Top Thermal Characterization Parameter Power Dissipation vs. Ambient Temperature Measurement Board Pattern 100 200 300 400 500 600 700 800 900 1000 0 2 55 07 5 1 0 0 1 2 5 1 5 0 Power Dissipation (mW) Ambient Temperature (°C) 850

POWER DISSIPATION QFN0303-20 PD-QFN0303-20-(85125)-JE- A i The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following measurement conditions are based on JEDEC STD. 51 Measurement Conditions Item Measurement Conditions Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Four-Layer Board) Board Dimensions 76.2 mm × 114.3 mm × 1.6 mm Copper Ratio Outer Layer (First Layer): Less than 10% of 74.2mm Square Inner Layers (Second and Third Layers): Approx. 100% of 74.2 mm Square Outer Layer (Fourth Layer): Less than 10% of 74.2mm Square Through-holes  0.3 mm × 4pcs Measurement Result (Ta = 25°C, Tjmax = 125°C) Item Measurement Result Power Dissipation 1850mW Thermal Resistance (ja) ja = 54°C/W Thermal Characterization Parameter (ψjt) ψjt = 16°C/W ja: Junction-to-Ambient Thermal Resistance ψjt: Junction-to-Top Thermal Characterization Parameter Power Dissipation vs. Ambient Temperature Measurement Board Pattern 200 400 600 800 1000 1200 1400 1600 1800 2000 0 25 50 75 100 125 Power Dissipation (mW) Ambient Temperature (°C) 1850 74.2 74.2 76.2 114.3

PACKAGE DIMENSIONS TSSOP-16 Ver. A i

PACKAGE DIMENSIONS QFN0303-20-P28 Ver. A i

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