R5436T NISSHINBO | Alldatasheet

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Technical content

3 to 5 Serial Cell Li-Ion or Li-Polymer Battery Protection IC NO.EA-322-240531 OUTLINE The R5436T is an overcharge, overdischarge and overcurrent protection IC for Li-ion or Li-polymer secondary battery. Overcharge, Overdischarge, Charge Overcurrent and Discharge Overcurrent for 3 to 5 serial cells can be detected. By cascade connection using the R5436T , it is also possible to protect 6-serial or more cells rechargeable battery pack. The R5436T provides a cell -balancing function to equalize imbalance between cells, and it provides an open- wire detection to detect a broken wire between a battery and the circuit board. The open-wire detection is optionally selectable.

FEATURES

 High Voltage Tolerant Process  Low Supply Current  High-accuracy Voltage Detection Overdischarge detection voltage (VDET2n (1)) ················· 2.0 V to 3.2 V (in 5 mV steps) Discharge overcurrent detection voltage1 (VDET31) (2) ····· 0.05 V to 0.25 V (in 10 mV steps) Discharge overcurrent detection voltage1 accuracy ······ ±15 mV(VDET31 ≤ 0.15V) / ±20 mV(VDET31 > 0.15V) Discharge overcurrent detection voltage2 (VDET32) ········ VDET31 × 3 Discharge overcurrent detection voltage2 accuracy ······ ±25 mV(VDET31 ≤ 0.10V) / ±50 mV(VDET31 > 0.10V) Charge overcurrent detection voltage accuracy (VDET4) ·· ±15 mV (VDET4 = −0.05 V / −0.1 V) / ±30 mV (VDET4 = −0.2 V) –provided, max.value is 3.2V. Cell-balancing detection voltage (VCBDn (1)) ·················· 3.45V to 4.45V (in 5 mV steps)  Each Detection Delay Time Overdischarge detection delay time settable by external capacitor Discharge overcurrent detection delay time 1/2 settable by external capacitor (1) VDET1n, VCBDn : n =1, 2, 3, 4, 5 (2) Set to meet the following equation: (3×VDET31+0.05<0.8×VSHORT). (3) VDET32 is not detected when VDET32 is higher than VSHORT.

NO.EA-322-240531  Overcharge Release Voltage Condition ············· Voltage release type  Overdischarge Release Voltage Condition ········· Latch type / Voltage release type  3 to 5 Cells Selectable Battery Protection  Delay Time Shortening Function  External NTC temperature protection function

APPLICATIONS

■ Li-ion/Li-polymer battery protection for electric tool and electric bicycle, etc.

NO.EA-322-240531 SELECTION GUIDE In the R5436T, the set voltage, the delay time, and the optional function can be designated. Selection Guide Product Name Package Quantity per Reel Pb Free Halogen Free R5436Txxx∗$-E2-FF TSSOP-28 3,000 pcs Yes Yes xxx: Specify a combination of the following set output voltages. Refer to Product Code List for details. VDET1n (1): 3.6 V to 4.5 V in 5 mV steps V REL1n (1): VDET1n − 0.1 V to VDET1n − 0.4 V in 10 mV steps (Min.3.45 V) VCBDn (1): 3.45 V to 4.45 V in 5mV steps VCBRn (1): VCBDn − 0.0 V to VCBDn − 0.4 V in 10 mV steps (Min.3.45 V) VDET2n (1): 2.0 V to 3.2 V in 5 mV steps VREL2n (1): VDET2n + 0.0 V to VDET2n + 0.7 V in 50 mV steps (Max. 3.2 V) VDET31: 0.05 V to 0.25 V in 10 mV steps VDET32: Fixed to three times VDET31 VSHORT: 0.25 V to 1.0 V in 20 mV steps VDET4: −0.05V, −0.1V, or −0.2V ∗: Specify a combination of the following each detection delay time. Code tVDET1 [s] tVDET2 [ms] tVDET31 [ms] tVDET32 [ms] tVDET4 [ms] tSHORT [µs] B 1.0 3.60×CCT1 [nF] 3.00×CCT2 [nF] tVDET31/6 8 330 $: Specify a combination of the optional functions. Code Overcharge Released Type Overdischarge Released Type

0 V Battery

A Voltage Release Latch Available Available B Voltage Release Voltage Release Available Unavailable (1) VDET1n, VREL1n、VCBDn, VCBRn, VDET2n, VREL2n : n =1, 2, 3, 4, 5

NO.EA-322-240531 Product Code List The product code is determined by the combination of the set voltages (Overcharge Detection Voltage: VDET1n, Overcharge Release Voltage: VREL1n, Cell-balancing Detection Voltage: VCBDn, Cell-balancing Release Voltage: VCBRn, Overdischarge Detection Voltage: VDET2n, Overdischarge Release Voltage: V REL2n, Discharge Overcurrent Detection Voltage 1/2: VDET31 / VDET32, Short-circuit Detection Voltage: VSHORT, Charge Overcurrent Detection Voltage: VDET4), the delay time code, and the optional function code. Product Name (Product Code) Set Voltage [V] VDET1n VREL1n VCBDn VCBRn VDET2n VREL2n VDET31 VDET32 VSHORT VDET4 R5436T502BA R5436T502BB R5436T503BA R5436T503BB R5436T504BA R5436T504BB R5436T505BA R5436T505BB R5436T506BA R5436T506BB R5436T507BA R5436T507BB R5436T508BA R5436T508BB R5436T511BA R5436T511BB

NO.EA-322-240531 Product Name (Product Code) Set Voltage [V] VDET1n VREL1n VCBDn VCBRn VDET2n VREL2n VDET31 VDET32 VSHORT VDET4 Please contact our sales representatives if required a product code other than the above combinations.

NO.EA-322-240531 BLOCK DIAGRAM CB Circuit-1 CB Circuit-2 CB Circuit-5 SEL1 VC1 VC2 VC3 VC4 0Vdet/ Vnochg1 Vnochg2 0Vdet/ Vnochg3 0Vdet/ Vnochg4 VC5 VD1-1 VD2-1 VD1-2 VD2-2 VD1-3 VD2-3 VD1-4 VD2-4 Regulator DS Circuit VDD Logic Circuit Oscillator Counter Logic Circuit VSS0 VD1-5 VD2-5 SEL2 CT1 CT2 0Vdet/ Vnochg5 VMP SENS VD3-1 COUT DOUT DRAIN Short CircuitDelay tVDET2 tVDET3Logic Circuit Regulator VD3-2 Logic Circuit Logic Circuit odd_sw even_sw CB1 CB2 CB3 CB4 CB5 CB Circuit-4 CB Circuit-3 VD4 CTLD CTLC VSS Logic Circuit VHC VR TEP Oscillator Counter 0Vdet/ R5436T Block Diagram

NO.EA-322-240531 PIN DESCRIPTIONS R5436T (TSSOP-28) Pin Configuration R5436T Pin Description Pin No. Symbol Description

1 CTLC COUT control pin

2 CTLD DOUT control pin

3 COUT Overcharge detection output pin, Pch. open-drain output

4 VMP Charger negative input pin

5 DRAIN FET’s gate connection pin for discharge overcurrent release voltage

6 DOUT Overdischarge detection output pin, CMOS output

7 VHC Transmission pin for VMP input signal

8 SENS Current sense pin

9 VR Internal VR output pin

10 TEP Temperature protection input pin

11 VSS Ground pin for the IC

12 CT1 Capacitor (CCT1) connection pin for setting tVDET2

13 CT2 Capacitor (CCT2) connection pin for setting tVDET3

14 SEL1 3- / 4- / 5-cell selectable pins 15 SEL2

16 VSS0 Negative terminal for CELL5

17 CB5 Cell balance control pin for CELL5

18 VC5 Positive terminal for CELL5

19 CB4 Cell balance control pin for CELL4

20 VC4 Positive terminal for CELL4

21 CB3 Cell balance control pin for CELL3

22 VC3 Positive terminal for CELL3

23 CB2 Cell balance control pin for CELL2

24 VC2 Positive terminal for CELL2

25 CB1 Cell balance control pin for CELL1

26 NC No Connection

27 VC1 Positive terminal for CELL1

28 VDD VDD pin

NO.EA-322-240531 ABSOLUTE MAXIMUM RATINGS (Ta = 25°C, VSS = 0 V) Symbol Parameter Rating Unit VDD Supply voltage −0.3 to 30 V VC1 VC2 VC3 VC4 VC5 VSS0 VMP VSEL1 VSEL2 VCTLC VCTLD VSENS VCT1 VCT2 VTEP CELL1 positive input pin voltage CELL2 positive input pin voltage CELL3 positive input pin voltage CELL4 positive input pin voltage CELL5 positive input pin voltage CELL5 negative input pin voltage Charger negative input pin voltage SEL1 pin input voltage SEL2 pin input voltage COUT control pin voltage DOUT control pin voltage Current sense pin voltage Delay time setting 1 pin voltage Delay time setting 2 pin voltage Temperature protection input pin voltage VC2−0.3 to VC2+6.5 VC3−0.3 to VC3+6.5 VC4−0.3 to VC4+6.5 VC5−0.3 to VC5+6.5 VSS0−0.3 to VSS0+6.5 −0.3 to VC5+0.3 VDD−30 to VDD+0.3 −0.3 to VDD+0.3 −0.3 to VDD+0.3 −0.3 to VDD+25 < 48 −0.3 to VDD+25 < 48 VVR−6.5 to VVR+0.3 −0.3 to VVR+0.3 −0.3 to VVR+0.3 −0.3 to VVR+0.3 V V V V V V V V V V V V V V V VCOUT VDOUT VDRAIN VCB1 VCB2 VCB3 VCB4 VCB5 VVHC VVR COUT pin output voltage DOUT pin output voltage DRAIN pin output voltage CB1 pin output voltage CB2 pin output voltage CB3 pin output voltage CB4 pin output voltage CB5 pin output voltage VHC pin output voltage VR pin output voltage VDD−30 to VDD+0.3 −0.3 to VOH2+0.3 −0.3 to VOH3+0.3 VC2−0.3 to VC2+6.5 VC3−0.3 to VC3+6.5 VC4−0.3 to VC4+6.5 VC5−0.3 to VC5+6.5 −0.3 to 6.5 VDD−3 to VDD+5 −0.3 to VVR+0.3 V V V V V V V V V V PD Power Dissipation Refer to Appendix “Power Dissipation”. Tj Junction Temperature Range −40 to 125 °C Tstg Storage Temperature Range −55 to 125 °C ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause permanent damage and may degrade the lifetime and safety for both device and system using the device in the field. The functional operation at or over these absolute maximum ratings is not assured.

NO.EA-322-240531 RECOMMENDED OPERATING CONDITION Symbol Parameter Rating Unit VDD Operating Input Voltage 2.5 to 25 V Ta Operating Temperature Range −40 to 85 °C RECOMMENDED OPERATING CONDITIONS All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating conditions. The semiconductor devices cannot operate normally over the recommended operating conditions, even if they are used over such conditions by momentary electronic noise or surge. And the semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions.

NO.EA-322-240531

ELECTRICAL CHARACTERISTICS

VCELLn = CELLn (Ex. VCELL1 is a voltage difference between VC1 and VC2) n = 1, 2, 3, 4, 5, unless otherwise noted. R5436TxxxBA / R5436TxxxBB Electrical Characteristics (Ta = 25°C) Symbol Parameter Conditions Min. Typ. Max. Unit Circuit (1) VDET1n CELLn overcharge detection voltage At rising edge detection of supply voltage VDET1n −0.025V VDET1n VDET1n +0.025V V A VREL1n CELLn overcharge release voltage At falling edge detection of supply voltage VREL1n −0.050V VREL1n VREL1n +0.050V V A tVDET1 Overcharge detection delay time VDD=VC1, VCELLn=3.5V (n=2,3,4,5) tVREL1 Overcharge release delay time VDD=VC1, VCELLn=3.5V (n=2,3,4,5) VCELL1=4.5V → 3.0V 11 16 21 ms B VCBDn CELLn cell balance detection voltage At rising edge detection of supply voltage VCBDn −0.025V VCBDn VCBDn +0.025V V C VCBRn CELLn cell balance release voltage (2) At falling edge detection of supply voltage VCBRn −0.050V VCBRn VCBRn +0.050V or VCBDn +0.025V V C tVCBD CELLn cell balance detection delay time VDD=VC1, VCELLn=3.5V (n=2,3,4,5) VCELL1=3.5V → VCBDn 11 16 21 ms C VDET2n CELLn overdischarge detection voltage At falling edge detection of supply voltage VDET2n x 0.975V VDET2n VDET2n x1.025V V D VREL2n CELLn overdischarge release voltage At rising edge detection of supply voltage VREL2n x 0.975V VREN2n VREN2n x1.025V V D ICT1 CT1 charging current VDD=VC1, VCELLn=3.5V (n=2,3,4,5) VCELL1=3.5V → 1.5V 350 500 650 nA E VDCT1 CT1 detection voltage VDD=VC1, VCELLn=3.5V (n=2,3,4,5), VCELL1=1.5V 1.44 1.80 2.16 V F tVDET2 Overdischarge detection delay time tVDET2=CCT1xVDCT1/ICT1, CCT1=33nF 83 119 155 ms - tVREL2 Overdischarge release delay time VDD=VC1, VCELLn=3.5V (n=2,3,4,5) VDET31 Discharge overcurrent detection voltage 1 VDD=VC1, VCELLn=3.5V, VMP=4.0V, At rising edge detection of SENS pin VDET31 ≤ 0.15V VDET31 −0.015V VDET31 VDET31 +0.015V V H VDET31 > 0.15V VDET31 −0.020V VDET31 +0.020V VDET32 Discharge overcurrent detection voltage 2 VDD=VC1, VCELLn=3.5V, VMP=4.0V, At rising edge detection of SENS pin VDET31 ≤ 0.10V VDET32 −0.025V VDET32 VDET32 +0.025V V I VDET31 > 0.10V VDET32 −0.050V VDET32 +0.050V VREL3 Discharge overcurrent release voltage VDD=VC1, VCELLn=3.5V, SENS=0.0V, At falling edge detection of VMP pin 0.8 1.0 1.2 V H ICT231 CT2 charge current 1 VDD=VC1, VCELLn=3.5V, SENS=VSS→0.4V 350 500 650 nA I (1) Refer to TEST CIRCUITS for detail information. (2) Max.value is equal to the lower value of VCBRn+0.050V or VCBDn+0.025V.

NO.EA-322-240531 VCELLn = CELLn (Ex. VCELL1 is a voltage difference between VC1 and VC2) n = 1, 2, 3, 4, 5, unless otherwise noted. R5436TxxxBA / R5436TxxxBB Electrical Characteristics (Continued) (Ta = 25°C) Symbol Parameter Conditions Min. Typ. Max. Unit Circuit (1) ICT232 CT2 charge current 2 VDD=VC1, VCELLn=3.5V SENS=VSS→0.7V 2.0 3.0 4.0 µA I VDCT2 CT2 detection voltage VDD=VC1, VCELLn=3.5V tVDET31 Discharge overcurrent detection delay time 1 tVDET31 = CCT2×VDCT2/ICT231 CCT2=3.3nF 6.9 9.9 12.9 ms - tVDET32 Discharge overcurrent detection delay time 2 tVDET32 = CCT2×VDCT2/ICT232 CCT2=3.3nF 1.1 1.65 2.2 ms - tVREL3 Discharge overcurrent release delay time VDD=VC1, VCELLn=3.5V, SENS=VSS, VMP= 4.0V→VSS 0.7 1.2 1.7 ms H VSHORT Short-circuit detection voltage VDD=VC1, VCELLn=3.5V, VMP=4.0V, At rising edge detection of SENS pin VSHORT ×0.8 VSHORT VSHORT ×1.2 V K tSHORT Short-circuit detection delay time VDD=VC1, VCELLn=3.5V, SENS=0.0V→2.0V, VMP=4.0V 230 330 430 µs K VDET4 Charge overcurrent detection voltage VDD=VC1, VCELLn=3.5V, VMP= −1.0V, At falling edge detection of SENS pin VDET4 ≥ −0.1V VDET4 −0.015V VDET4 VDET4 +0.015V V L VDET4 < −0.1V VDET4 −0.030V VDET4 +0.030V VREL4 Charge overcurrent release voltage VDD=VC1, VCELLn=3.5V At rising edge detection of VMP pin 0.05 0.1 0.15 V L tVDET4 Charge overcurrent detection delay time VDD=VC1, VCELLn=3.5V, SENS=0.0V→−1.0V 5 8 11 ms L tVREL4 Charge overcurrent release delay time VDD=VC1, VCELLn =3.5V, SENS=VSS, VIH1 SEL1 pin ”High” input voltage VDD=VC1, VCELLn =3.4V VDD−0.3V VDD+0.3V V M VIM1 SEL1 pin ”Middle” input voltage VDD=VC1, VCELLn =3.4V 4.0 VDD/2 −0.5V V M VIL1 SEL1 pin ”Low” input voltage VDD=VC1, VCELLn =3.4V VSS−0.3V VSS+0.3V V M VIH2 SEL2 pin ”High” input voltage VDD=VC1, VCELLn =3.4V VDD−0.3V VDD+0.3V V N VIM2 SEL2 pin ”Middle” input voltage VDD=VC1, VCELLn =3.4V 4.0 VDD/2 −0.5V V N VIL2 SEL2 pin “Low” input voltage VDD=VC1, VCELLn =3.4V VSS−0.3V VSS+0.3V V N VCTLC1H CTLC pin ”High” threshold voltage 1 VDD=VC1, VCELLn =3.4V 17.5 18.1 18.7 V O VCTLC2H CTLC pin ”High” threshold voltage 2 VDD=VC1, VCELLn =3.4V 15.1 16.1 16.6 V O VCTLD1H CTLD pin ”High” threshold voltage 1 VDD=VC1, VCELLn =3.4V 17.5 18.1 18.7 V P VCTLD2H CTLD pin ”High” threshold voltage 2 VDD=VC1, VCELLn =3.4V 15.1 16.1 16.6 V P (1) Refer to TEST CIRCUITS for detail information.

NO.EA-322-240531 VCELLn = CELLn (Ex. VCELL1 is a voltage difference between VC1 and VC2) n = 1, 2, 3, 4, 5, unless otherwise noted. R5436TxxxBA / R5436TxxxBB Electrical Characteristics (Continued) (Ta = 25°C) Symbol Item Conditions Min. Typ. Max. Unit Circuit (1) tCTLD1 CTLD pin input delay time 1 (R5436TxxxBB only) VDD=VC1, VCELLn =3.4V CTLD=VDD+0.5V→VDD+1.7V 1.5 6 ms P tCTLD2 CTLD pin input delay time 2 (R5436TxxxBB only) VDD=VC1, VCELLn =3.4V CTLD=VDD+1.7V→VDD+0.5V 1.5 6 ms P VOL2 DOUT pin Nch.ON voltage IOL=50μA, VDD=VC1, CTLD=VDD VCELLn =3.4V 0.1 0.5 V Q VOL3 DRAIN pin Nch.ON voltage IOL=50μA, VDD=VC1, VCELLn =3.4V 0.1 0.5 V R VOL4 CB1 pin Nch.ON voltage IOL=50μA, VDD=VC1, VCELLn =3.4V VC2+0.2V VC2+0.5V V S VOL5 CB2 pin Nch.ON voltage IOL=50μA, VDD=VC1, VCELLn =3.4V VC3+0.2V VC3+0.5V V S VOL6 CB3 pin Nch.ON voltage IOL=50μA, VDD=VC1, VCELLn =3.4V VC4+0.2V VC4+0.5V V S VOL7 CB4 pin Nch.ON voltage IOL=50μA, VDD=VC1, VCELLn =3.4V VC5+0.2V VC5+0.5V V S VOL8 CB5 pin Nch.ON voltage IOL=50μA, VDD=VC1, VCELLn =3.4V 0.2V 0.5V V S VOH1 COUT pin Pch.ON voltage IOH=−50μA, VDD=VC1, CTLC=VSS, VCELLn=3.4V VDD−0.5V VDD−0.1V V T VVR12 VR12V output voltage IOH=−5μA, VDD=VC1, CTLD=VSS, VCELLn =3.4V, The measured value by pulling current through DOUT pin. 9.5 12 14 V U VOH2(2) DOUT pin Pch.ON voltage IOH= −50μA, VDD=VC1, CTLD= VSS, VCELLn =3.2V VVR12−0.5V VVR12−0.1V V U VOH3（2） DRAIN pin Pch.ON voltage IOH= −50μA, VDD=VC1, VCELL = 3.2V, SENS=VMP=4.0V VVR12−0.5V VVR12−0.1V V V VOH4 CB1 pin Pch.ON voltage IOH= −50μA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=2,3,4,5) VC1−0.5V VC1−0.3V V W VOH5 CB2 pin Pch.ON voltage IOH= −50μA, VDD=VC1, VC2=4.5V, VCELLn=3.2V (n=1,3,4,5) VC2−0.5V VC2−0.3V V W VOH6 CB3 pin Pch.ON voltage IOH= −50μA, VDD=VC1, VC3=4.5V, VCELLn=3.2V (n=1,2,4,5) VC3−0.5V VC3−0.3V V W VOH7 CB4 pin Pch.ON voltage IOH= −50μA, VDD=VC1, VC4=4.5V, VCELLn=3.2V (n=1,2,3,5) VC4−0.5V VC4−0.3V V W VOH8 CB5 pin Pch.ON voltage IOH= −50μA, VDD=VC1, VC5=4.5V, VCELLn=3.2V (n=1,2,3,4) VC5−0.5V VC5−0.3V V W (1) Refer to TEST CIRCUITS for detail information. (2) When VDD < VVR12-0.1V, DOUT / DRAIN pin voltage (VOH2/VOH3) becomes almost equal to VDD.

NO.EA-322-240531 VCELLn = CELLn (Ex. VCELL1 is a voltage difference between VC1 and VC2) n = 1, 2, 3, 4, 5, unless otherwise noted. R5436TxxxBA / R5436TxxxBB Characteristics (Continued) (Ta = 25°C) Symbol Item Conditions Min. Typ. Max. Unit Circuit (1) ILCOUT COUT pin off leakage- current VDD=VC1, VCELLn=3.4V,CTLC=VDD, COUT= −14V −0.1 µA X VVR VR output voltage VDD=VC1, VCELLn=3.4V 3.5 3.6 3.7 V Y VT_DET Detection voltage of TEP temperature protection VDD=VC1, VCELLn=3.4V VT_DET −0.027 VT_DET(2 VT_DET +0.035 V Z VT_REL Release voltage of TEP temperature protection VDD=VC1, VCELLn=3.4V VT_REL −0.043 VT_REL2 VT_REL +0.050 V Z tT_DET TEP detection delay time VDD=VC1, VCELLn=3.4V, VTEP=0V→2V 5 8 11 ms Z tT_REL TEP release delay time VDD=VC1, VCELLn=3.4V, VTEP=2V→0V 11 16 21 ms Z tLT Broken wire scanning cycle VDD=VC1, VCELLn=VCBDn+0.05V 0.7 1.25 1.8 S a VHCO1 VHC pin Nch.ON voltage IOH= 2μA, VDD=VC1, VCELLn=3.4V, VMP=0V 14.5 15.5 16.5 V c VHCO2 VHC pin Nch.ON voltage IOH=10μA, VDD=VC1, VCELLn=3.4V, VMP=0V VHC1+0.3 VHC1+0.5 V c ILVHC VHC pin off leakage- current VDD=VC1, VCELLn=3.4V, VMP=0.5V, VHC=32V 0.1 µA b ISS1 Supply current 1 VDD=VC1, COUT=OPEN VCELLn =VDET1n - 0.4V 12 30 µA d ISS2 Supply current 2 VDD=VC1, COUT=OPEN VCELLn =1.5V 6 12 µA d VSTB Power ON voltage at standby mode VDD=VC1=1.5V, VCELLn=3.4V (n=2,3,4,5), At rising edge detection of VMP pin 0.9 1.13 1.35 V H (1) Refer to TEST CIRCUITS for detail information. (2) VT_DET=20/21*VVR, VT_REL=27/29*VVR (VVR:VR pin output voltage)

NO.EA-322-240531 TEST CIRCUITS Ａ VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 V V V V V B VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB6 SENS VMP DOUT CTLC DRAIN SEL1 SEL2 CTLD COUT C V V V V V D OSCILLOSCOPE VSS CT2 VHC TEP VR CT0VSS CT1 TEP VR VHC VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1VSS CT2 VHC TEP VR VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1VSS CT2 VHC TEP VR V V V V V

NO.EA-322-240531 E VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 F G H VSS CT2 VHC TEP VR A VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 VSS CT2 VHC TEP VR VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 VSS CT2 VHC TEP VR V VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 VSS CT2 VHC TEP VR V V

NO.EA-322-240531 I J K L VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 VSS CT2 VHC TEP VR V A VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 VSS CT2 VHC TEP VR V VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 VSS CT2 VHC TEP VR V VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 VSS CT2 VHC TEP VR V

NO.EA-322-240531 M N O P VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 VSS CT2 VHC TEP VR V VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 VSS CT2 VHC TEP VR V VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 VSS CT2 VHC TEP VR V VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 VSS CT2 VHC TEP VR V

NO.EA-322-240531 Q R S V V V V V T VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1VSS CT2 VHC TEP VR V VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1VSS CT2 VHC TEP VR V VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1VSS CT2 VHC TEP VR V VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1VSS CT2 VHC TEP VR V

NO.EA-322-240531 U V W V V V V V X VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1VSS CT2 VHC TEP VR VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1VSS CT2 VHC TEP VR V V VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1VSS CT2 VHC TEP VR A VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1VSS CT2 VHC TEP VR V

NO.EA-322-240531 Y Z a V b V A VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD VR TEP CT1VSS CT2 VHC VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD VR TEP CT1VSS CT2 VHC VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD VR TEP CT1VSS CT2 VHC VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD VR TEP CT1VSS CT2 VHC

NO.EA-322-240531 c d A V A A VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD VR TEP CT1VSS CT2 VHC VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD VR TEP CT1VSS CT2 VHC

NO.EA-322-240531 THEORY OF OPERATION Overcharge Detection: VD1-n (n = 1, 2, 3, 4, 5) During charging, the device supervises the voltage between VC1 and VC2 pins ( the CELL1 voltage), the voltage between VC2 and VC3 pins (the CELL2 voltage), the voltage between VC3 and VC4 pins (the CELL3 voltage), the voltage between VC4 and VC5 pins ( the CELL4 voltage), and the voltage between VC5 and VSS0 pins ( the CELL5 voltage). If at least one of the cells’ voltage becomes more than the overcharge detection voltage, the overcharge is detected, and COUT pin connected to an external pull -down resistor becomes “Hi-z”, and it makes the external Nch.FET turn off. Then, the charging stops. After detecting the overcharge, when all the cell voltage become lower than the overcharge detection voltage by connecting a load, COUT pin becomes “High”, and it makes the external Nch.FET turn on, and the charging restarts. Even If all the cell voltage become lower than the overcharge release voltage with no load, COUT pin becomes “High” and the charging is available. The device has internal fixed output delay times for overcharge detection and overcharge release. When the output delay time passes while any one of cell voltages is more than the overcharge detection voltage, the overcharge is detected. However, all cell voltage becomes lower than the overcharge detection voltage within the overcharge detection delay time, even if anyone of cells' voltage becomes more than the overcharge detection voltage, the overcharge is not detected. Besides, after detecting the overcharge, any one of their cell voltages becomes more than the overcharge release voltage within the overcharge release delay time, even if all the cell voltage becomes lower than the overcharge release voltage, the device does not release from the overcharge. Overdischarge Detection: VD2-n (n = 1, 2, 3, 4, 5) During discharging, the device supervises the voltage between VC1 and VC2 pins (the CELL1 voltage) , the voltage between VC2 and VC3 pins (the CELL2 voltage), the voltage between VC3 and VC4 pins (the CELL3 voltage), the voltage between VC4 and VC5 pins (the CELL4 voltage), and the voltage between VC5 and VSS0 pins (the CELL5 voltage). If at least one of the cells’ voltage becomes less than the overdischarge detection voltage, the overdischarge is detected, and DOUT pin becomes “Low” , and it makes the external Nch.FET turn off. Then, the discharging stops. The release condition from the overdischarge detection is different depending on optional functions. One is the latch type, after detecting the overdischarge, when the battery becomes higher than the overdischarge release voltage by connecting a charger, DOUT pin becomes “High”. And, the other is the voltage release type, when the cell voltage becomes higher than the overdischarge release voltage, the device releases from the overdischarge even if the charger is not connected, and DOUT pin becomes “High”. An output delay time for overdischarge detection is settable by the external capacitor (C CT1) connected to CT1 pin. When the output delay time passes while any one of each cell voltage is lower than the overdischarge detection voltage, the overdischarge is detected. However, all cell voltage becomes higher than the overdischarge detection voltage within the overdischarge detection delay time even if anyone of cells' voltage becomes lower than the overdischarge detection voltage, the over discharge is not detected. An output delay time for overdischarge release is fixed internally.

NO.EA-322-240531 After detecting the overdischarge, the device stops unnecessary circuits to reduce the consumption current to a minimum when VMP pin becomes “High”. DOUT pin, which is CMOS output, outputs the internal regulator’s voltage (about 12 V) at “High” level and outputs VSS pin voltage at “Low” level. Discharge Overcurrent Detection: VD3-n (n = 1, 2) and Short-circuit Detection During discharging, the device supervises SENS pin voltage (VSENS). The discharge overcurrent is detected when SENS pin voltage (V SENS) becomes in between the discharge overcurrent detection voltage (V DET3n) and the short -circuit detection voltage (V SHORT) owing to a large load, and the short-circuit is detected when V SENS becomes more than V SHORT. Then, to prevent from flowing large current to circuits, DOUT pin is set to “Low” and the external FET is turned OFF. The device has two detection thresholds to detect the discharge overcurrent. Each detection threshold has the output delay time each other. The discharge overcurrent detection delay time 2 ( tVDET32) is set to be short er than the discharge overcurrent detection delay time 1 (tVDET31). An output delay time for discharge overcurrent detection is settable by the external capacitor (CCT2) connected to CT2 pin. When VSENS becomes lower than VDET3n within the output delay time even if V SENS is in between VDET3x and VSHORT, the discharge overcurrent is not detected. The output delay times for discharge overcurrent release and short-circuit are fixed internally. Connect an external resistor for discharge overcurrent release among each drain of the external FETs connected to DRAIN, COUT, and DOUT pins. After detecting the discharge over current, or the short -circuit, turn ON the external FET connected to DRAIN pin, and connect a resistor for overcurrent release to VSS. When load is released and opened after detecting the discharge overcurrent or the short-circuit, The VMP pin voltage (VVMP) is pulled down to VSS via the resistor for the overcurrent release, and VVMP becomes less than VREL3. After a certain delay time, the discharge overcurrent detection stat e or the short-circuit detection state is released. When the discharge overcurrent detection is released, the external FET connected to DRAIN pin is turned OFF, and the resistor for the overcurrent release is disconnected from VSS. Charge Overcurrent Detection: VD4 During charging or discharging, the device supervises SENS pin voltage (VSENS). When a large current flow by charging with an inappropriate charger, SENS pin voltage becomes less than the charge overcurrent detection voltage, and the charge overcurrent is detected. COUT pin with the external pull- down resistor becomes “Hi- z”. And, tuning OFF the external FET can prevent from flowing large current to circuits. When SENS pin voltage (V SENS) becomes higher than VDET4 within the output delay time even if VSENS becomes lower than the charge overcurrent detection voltage, the charge overcurrent is not detected. The output delay times for charge overcurrent detection and charge overcurrent release are fixed internally. To release from the charge overcurrent, connect a load without the charger, and VMP pin voltage has to become higher than the charge overcurrent release voltage over the charge overcurrent release delay time.

NO.EA-322-240531 VC5 - VSS0 Overcharge / Charge Overcurrent Operation Timing Chart

NO.EA-322-240531 VC5 - VSS0 Overdischarge / Discharge Overcurrent / Short-circuit Operation Timing Chart

NO.EA-322-240531 Standby Mode This device can change from normal mode to standby mode when overdischarge is detected and VMP pin voltage (VVMP) becomes higher than VSTB. In the standby mode, the device stops unnecessary circuits to reduce the consumption current to a minimum. At that time, VR pin output voltage becomes equal to the VSS level. And, this device can return to the normal mode when VVMP becomes lower than VSTB by connecting a charger. Cell Imbalance When any one of CELLs detects an overcharge and either one detects an overdischarge, COUT pin becomes “Hi-z” and DOUT pin becomes “Low”. SEL1 and SEL2 Pins SEL1 and SEL2 pins are switching-control pins to select among 3- / 4- / 5-cell protection. When using for the 4-cell protection, connecting SEL1 pin to VSS and the SEL2 pin to VDD is required to stop the 5th cell protection circuit and shut signals. The overdischarge is not detected when VC5 pin is shortened to VSS0. When using for the 3- cell protection, likewise, connecting SEL1 pin to V DD and SEL2 pin to VSS is required to stop the 5th and 4th cells protection circuits and shut signals. The overdischarge is not detected when VC4 and VC5 pins are shortened to VSS0. SEL1 / SEL2 pin must be fixed to VDD / VSS when using the 3- / 4- / 5- cell protection. Setting SEL1 and SEL2 pins can select disabling/enabling the open-wire detection(1) and the shorten mode 1/2. Refer to the following table for details of the operation mode. Operation Modes (1) R5436TxxxBB does not support the open-wire detection. (2) “High”: VDD level, “Middle”: (VDD/2-0.5) V to (VDD-3) V, “Low”: VSS level Input Voltage(2) Operation Mode SEL1 Pin SEL2 Pin High High Enable the 5-cell protection mode Low High Enable the 4-cell protection mode High Low Enable the 3-cell protection mode Low Low Disable the open-wire detection mode for 5-cell protection Low Middle Disable the open-wire detection mode for 4-cell protection Middle Low Disable the open-wire detection mode for 3-cell protection Middle Middle Enable the delay time shorten mode 1 (approx.1/70) for 5-cell protection Middle High Enable the delay time shorten mode 2 (approx.4 ms) for 5-cell protection High Middle Enable the open-wire detecting test for 5-cell protection

NO.EA-322-240531 CTLC and CTLD Pins When using cascade connection, the R5436T can transfer each state of overcharge, overdischarge, and open- wire detections by connecting between COUT and CTLC pins and between DOUT and CTLD pins. When not using it, CTLC and CTLD pins must be connected to VSS. When CTLC / CTLD pin voltage is higher than the value of “High” threshold voltage 1 (VCTLC1H / VCTLD1H), or when CTLC / CTLD pin voltage is lower than the value of “High” threshold voltage 2 (VCTLC2H / VCTLD2H), COUT / DOUT pin becomes “High” after normal operation. By applying a voltage of between VCTLC1H and VCTLC2H to CTLC pin, COUT pin with an external pull-down resistor becomes “Hi-z” forcedly. And, by applying a voltage of between V CTLD1H and VCTLD2H to CTLD pin, DOUT pin with an external pull -down resistor becomes “Low” forcedly. Don’t make CTLC and CTLD pins open. The following table indicates a relationship between the control pins (CTLC and CTLD) and the state of the external FETs for COUT and DOUT pins. External FET’s state by CTLx pins CTLC / CTLD pins External FET for COUT / DOUT pins 2VDD to VCTLC1H / VCTLD1H ON (Normal operation) VCTLC1H / VCTLD1H to VCTLC2H / VCTLD2H Forced OFF VSS to VCTLC2H / VCTLD2H ON (Normal operation) When VDD = 17 V (Refer to “Electrical Characteristics”), VCTLC1H / VCTLD1H: Typ.18.1 V VCTLC2H / VCTLD2H: Typ.16.1 V VDD VSS VDD2 CTLC/CTLDInput voltage (1) Normal mode (2) Forced OFF (1) Normal mode 16.1V 18.1V (VDD=17V)

NO.EA-322-240531 CT1 and CT2 Pins CT1 and CT2 pins are used for setting each output delay time of the overdischarge detection (t VDET2), and the discharge overcurrent detection 1/2 (tVDET31 / tVDET32) by connecting external capacitors CCT1 and CCT2. tVDET2 can be set with CT1 pin. t VDET31 and tVDET32 can be set with CT2 pin. Each delay time can be calculated by following Equation 1: ■ Delay time (tVDET2) setting with external capacitor (CCT1) By substitution of Equation1, If CCT1 = 33 nF, VDCT1 = 1.8 V, ICT1 = 500 nA (Refer to “Electrical Characteristics”). When substituting values to Equation 2, tVDET2 is as follows: tVDET2 = 33 nF x 1.8 V / 500 nA = 118.8 ms ■ Delay time (tVDET31, tVDET32) setting with external capacitor (CCT2) By substitution of Equation1, If CCT1 = 3.3 nF, VDCT1 = 1.5 V, ICT1 = 500 nA (Refer to “Electrical Characteristics”). When substituting values to Equation 3 / Equation 4, tVDET31 and tVDET32 are as follows: tVDET31 = 3.3 nF × 1.5 V / 500 nA = 9.9 ms tVDET32 = 9.9 ms / 6 = 1.65 ms Cell Balance Function When the cell voltage exceeds the cell balance detection voltage (VCBDn, n=1,2,3,4,5), CBn pin become “High” by cell balancing. By turning ON an external Nch. FET for cell balance, a current flow through the discharge path in parallel with the cell in order to reduce the charging current or to discharge the cell voltage. And, when the cell voltage is less than the cell balance release voltage (VCBRn, n=1,2,3,4,5), CBn pin become “Low” after

NO.EA-322-240531 the cell balancing is released, and the external Nch.FET is turned OFF. When not using this function, CBn pin must be open. V DET11 VREL11 ・VC1-VC2 t・CB1-VC2 （Voltage difference） t VDD ・COUT t ・Charge/ Discharge current t Charge current Discharge current charge current bypass current charge current - bypass current CB REL1 CBDET1 discharge current + bypass current idle tVDET1 discharge current Cell balance operation Over charge statetVCBD CELL1 Balancing Timing Chart

NO.EA-322-240531 VDET1x V REL1x Cellx voltage t CBx output t VDD COUT output Charge/ Discharge current t Charge current Discharge current charger VCBRx VCBDx idle tVDET1 Over charge state L charger - bypass charger - bypass idlebypass bypass charger Cell1 Cell2 CB1 operating CB2 operating Cell1 Cell2 t tVCBD tVCBD CELL1/2 Balancing Timing Chart

NO.EA-322-240531 Open-wire Detection (R5436TxxxBA only) When using the 5-cell protectio n, the voltage of VDD (= VC1) becomes lower than VC2 voltage if the connection between the battery and VDD (= VC1) is open. And, the voltage of VSS (= VSS0) becomes higher than VC5 voltage if the connection between t he battery and VSS (= VSS0) is open. The voltage variation is detected as “Open-wire”. When the open-wire is detected, COUT becomes “HI-z” and DOUT becomes “Low”. But, if VC1 or VSS0 line is cut off when each VC1 and VSS0 pins are connected with separate lines, only DOUT pin will become “Low”. Likewise, as for an open-wire detection between VDD and VSS pins, if VDD or VSS line is cut off, COUT pin will become “Hi-z” and DOUT pin will become “Low”. Open-wire detection for VC2, VC3, VC4, and VC5 is performed at interval of 1.25 seconds. The cell switch for VC1, VC3, and VC5 and the cell switch for VC2 and VC4 are alternately turned ON by even_sw and odd_sw signals. The internal impedance between pins, which are turned the switch ON, is lowered for about 140 ms. If not detecting the open-wire, this cycle will exit and the next cycle will start. If detecting the open-wire, the VC voltage will be shifted according to the difference of the internal impedance caused by turning ON either of two switches. This voltage change is detected during the delay time of 0.5 ms or more, the open-wire detection works. Then, COUT pin becomes “Hi-z” and DOUT pin becomes “Low”. By applying a certain voltage to SEL1 and SEL2 pins, the open-wire detection for VC2, VC3, VC4, and VC5 is disabled . The open-wire detection is disabled even when this device is in standby mode - b ut the open -wire detection for VDD and VSS lines is enabled. When using the 10-cell protection, if VSS of the higher-voltage device and VDD of the lower-voltage device in cascade connection are connected with the battery’s line, an open-wire in this line cannot be detected. [Limitations of Open-wire detection for VC2, VC3, VC4, and VC5] When using the open-wire detection for VC2, VC3, VC4, and VC5, confirm the limitations below:

  • The cycle time of open- wire detection is 1.25 second, and the open- wire detection is performed for 140 ms in each cycle. The device controls these internal-set times.
  • When the battery voltage is low er even when this device is not in standby, an open-wire might not be detected due to some factors: the device’s distribution, the cell balancing in the battery, the operating environment, the characteristics of the external components, etc.
  • D uring the overcharge detection delay time, the device does not shift to the open- wire detection until the overcharge detection is finished. The overcharge detection does not start even if the battery voltage is higher than the overcharge detection voltage. After the completion of the open-wire detection, the overcharge detection will start if the battery voltage is more than the overcharge detection voltage. That is, the overcharge detection delay time increases for the time required for the open-wire detection.
  • Likewise, the device does not shift to the open-wire detection during the overdischarge detection delay time, and the device does not start the overdischarge detection when the battery voltage is less than the overdischarge detection voltage during the open- wire detection. But, after the completion of the open- wire detection, the overdischarge detection delay time increases for the time required for the open-wire detection.

NO.EA-322-240531 odd_sw (inner signal) even_sw (inner signal) VC3 voltage (VC3 line break) Open-wire detecting time （about 140ms） reset (inner signal) VC3,VC5 wire detecting VC2/VC4 wire detecting Open-wire scanning cycle （about 1.25s） COUT DOUT (VC3 line break) Open-wire detecting threshold Line break happan VC3,VC5 wire detecting Open-wire detecting time （about 140ms） Open-wire Detection Timing Chart

NO.EA-322-240531 Temperature Protection by External NTC The temperature protection is realized with VR and TEP pins. VR pin supplies a source voltage to be divided by a series of resistors of RTEP and NTC. The divided voltage becomes an input to TEP pin. When rising of the temperature under the NTC’s supervising, TEP pin voltage, which is the divided voltage, rises depending on a reduction of the NTC resistance value. When the delay time ( tT_DET) has passed while holding the divided voltage being higher than the temperature protection detection voltage (V T_DET), the temperature protection will function, and changing COUT pin to “Hi -z” and D OUT pin to “Low” can stop charging/ discharging. After the temperature falling, the delay time (tT_REL) has passed while holding the divided voltage being lower than the temperature protection release voltage (VT_REL), COUT and DOUT pins return “High”, and charging / discharging is available. VR pin cannot supply a large current because of supplying a source voltage for the voltage divider. In standby mode, the temperature protection stops since VR pin becomes “Low” to reduce the consumption current. When using the temperature protection at desired temperature, each resistance v alue of NTC and R TEP can be calculated by following Equation: 𝑅𝑅𝑇𝑇𝑇𝑇𝑇𝑇 𝑅𝑅𝑇𝑇𝑇𝑇𝑇𝑇 + 𝑅𝑅𝑁𝑁𝑇𝑇𝑁𝑁 × 𝑉𝑉𝑅𝑅 = 20 2 1 × 𝑉𝑉𝑅𝑅 RTEP = 20 RNTC For example, when using the following requirements: NTC resistor: SNS104B24B24360FE1L050ET Available temperature for protection: 65°C RNTC = 17.63 kΩ (at 65°C) Then, RTEP = 20 x RNTC = 352.6 (kΩ) As a result, choose a nearest value and normal type resistance: R TEP=348KΩ.

NO.EA-322-240531

APPLICATION INFORMATION

For battery pack assembly, it is recommended to start with the VSS connection, followed by the (+) terminal of the lowest cell in ascending voltage order. Typical Application Circuits 1 3-cell Protection Battery Charger CVC1 VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 RVC1 RVC2 RVC3 RCB1 RCB2 RCB3 CVC2 CVC3 CVDD RVDD CCT1 CCT2 RSENS RDRAIN RCO1 RCO2 RVMP ZD1 RSE TEP VR VSS VHC RTEP NTC CVR MCOMDO MDR CVHC RVSS DVSS R5436 CVSS1 CVSS2 Typical Application Circuit for 3-cell Protection Battery Charger

NO.EA-322-240531 Typical Application Circuits 2 4-cell Protection Battery Charger with Cell-balancing Disabled CVC1 VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 Cell4 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 RVC1 RVC2 RVC3 RVC4 CVC2 CVC3 CVC4 CVDD RVDD CCT1 CCT2 RSENS RDRAIN RCO1 RCO2 RVMP ZD1 RSE TEP VR VSS VHC RTEP NTC CVR MCOMDO MDR CVHC RVSS DVSS R5436 CVSS1 CVSS2 Typical Application Circuit for 4-cell Protection Battery Charger with Cell-balancing Disabled

NO.EA-322-240531 4-cell Protection Battery Charger with Cell-balancing Enabled CVC1 VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 Cell4 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 RVC1 RVC2 RVC3 RVC4 RCB1 RCB2 RCB3 RCB4 CVC2 CVC3 CVC4 CVDD RVDD CCT1 CCT2 RSENS RDRAIN RCO1 RCO2 RVMP ZD1 RSE TEP VR VSS VHC RTEP NTC CVR MCOMDO MDR CVHC RVSS DVSS R5436T CVSS1 CVSS2 Typical Application Circuit for 4-cell Protection Battery Charger with Cell-balancing Enabled

NO.EA-322-240531 Typical Application Circuits 3 5-cell Protection Battery Charger with Cell-balancing Enabled CVC1 VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 Cell4 Cell5 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 RVC1 RVC2 RVC3 RVC4 RVC5 RCB1 RCB2 RCB3 RCB4 RCB5 CVC2 CVC3 CVC4 CVC5 CVDD RVDD CCT1 CCT2 RSENS RDRAIN RCO1 RCO2 RVMP ZD1 RSE TEP VR VSS VHC RTEP NTC CVR MCOMDO MDR CVHC RVSS DVSS R5436T CVSS1 CVSS2 Typical Application Circuit for 5-cell Protection Battery Charger with Cell-balancing Enabled

NO.EA-322-240531 Typical Application Circuits 4 6-cell Protection Battery Charger with Cell-balancing Enabled CVC1 VC1 VC2 VDD Cell4 CB1 Cell5 Cell6 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 RVC1 RVC2 RVC3 RCB1 RCB2 RCB3 CVC2 CVC3 CVDD RVDD CCT1 CCT2 RSENS RDRAIN RCO1 RCO2 RVMP ZD1 RSE TEP VR VSS VHC CVC1 VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 RVC1 RVC2 RVC3 RCB1 RCB2 RCB3 CVC2 CVC3 CVDD RVDD CCT1 ZD1 TEP VR VSS VHC RUCO RCTLC RCTLD RTEP NTC NTC RVHC RTEP CVR CVR MCOMDO MDR CVHC1 VHC2C RVSS DVSS CCTLD RVMP2 R5436T R5436T CVSS1 CVSS2 Typical Application Circuit for 6-cell Protection Battery Charger with Cell-balancing Enabled

NO.EA-322-240531 Typical Application Circuits 5 7-cell Protection Battery Charger with Cell-balancing Enabled CVC1 VC1 VC2 VDD Cell4 CB1 Cell5 Cell6 Cell7 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 RVC1 RVC2 RVC3 RVC4 RCB1 RCB2 RCB3 RCB4 CVC2 CVC3 CVC4 CVDD RVDD CCT1 CCT2 RSENS RDRAIN RCO1 RCO2 RVMP ZD1 RSE TEP VR VSS VHC CVC1 VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 RVC1 RVC2 RVC3 RCB1 RCB2 RCB3 CVC2 CVC3 CVDD RVDD CCT1 ZD1 TEP VR VSS VHC RUCO RCTLC RCTLD RTEP NTC NTC RVHC RTEP CVR CVR MCOMDO MDR CVHC1 VHC2C RVSS DVSS CCTLD RVMP2 R5436T R5436T CVSS1 CVSS2 Typical Application Circuit for 7-cell Protection Battery Charger with Cell-balancing Enabled

NO.EA-322-240531 Typical Application Circuits 6 8-cell Protection Battery Charger with Cell-balancing Enabled CVC 1 VC1 VC2 VDD Cell5 CB 1 Cell6 Cell7 Cell8 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RCB 1 RCB 2 RCB 3 RCB 4 CVC 2 CVC 3 CVC 4 CVD D RVD D CCT 1 CCT 2 RSENS RDR AIN RCO 1 RCO 2 RVMP ZD1 RSE TEP VR VSS VHC CVC 1 VC1 VC2 VDD Cell1 CB 1 Cell2 Cell3 Cell4 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RCB 1 RCB 2 RCB 3 RCB 4 CVC 2 CVC 3 CVC 4 CVD D RVD D CCT 1 ZD1 TEP VR VSS VHC RUC O RCT LC RCT LD RTEP NTC NTC RVH C RTEP CVR CVR MCOMDO MDR CVH C1 VH C2C RVSS DVSS CCT LD RVMP2 R5436T R5436T CVSS1 CVSS 2 Typical Application Circuit for 8-cell Protection Battery Charger with Cell-balancing Enabled

NO.EA-322-240531 Typical Application Circuits 7 9-cell Protection Battery Charger with Cell-balancing Enabled CVC1 VC1 VC2 VDD Cell5 CB1 Cell6 Cell7 Cell8 Cell9 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 RVC1 RVC2 RVC3 RVC4 RVC5 RCB1 RCB2 RCB3 RCB4 RCB5 CVC2 CVC3 CVC4 CVC5 CVDD RVDD CCT1 CCT2 RSENS RDRAIN RCO1 RCO2 RVMP ZD1 RSE TEP VR VSS VHC CVC1 VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 Cell4 VC3 VC4 VC5 VSS0 CB2 CB3 CB4 CB5 SENS VMP COUT DOUT CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 RVC1 RVC2 RVC3 RVC4 RCB1 RCB2 RCB3 RCB4 CVC2 CVC3 CVC4 CVDD RVDD CCT1 ZD1 TEP VR VSS VHC RUCO RCTLC RCTLD RTEP NTC NTC RVHC RTEP CVR CVR MCOMDO MDR CVHC1 VHC2C RVSS DVSS CCTLD RVMP2 R5436T R5436T CVSS1 CVSS2 Typical Application Circuit for 9-cell Protection Battery Charger with Cell-balancing Enabled

NO.EA-322-240531 Typical Application Circuits 8 10-cell Protection Battery Charger with Cell-balancing Enabled CVC 1 VC1 VC2 VDD Cell6 CB 1 Cell7 Cell8 Cell9 Cell10 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RVC 5 RCB 1 RCB 2 RCB 3 RCB 4 RCB 5 CVC 2 CVC 3 CVC 4 CVC 5 CVD D RVD D CCT 1 CCT 2 RSENS RDR AIN RCO 1 RCO 2 RVMP ZD1 RSE TEP VR VSS VHC CVC 1 VC1 VC2 VDD Cell1 CB 1 Cell2 Cell3 Cell4 Cell5 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RVC 5 RCB 1 RCB 2 RCB 3 RCB 4 RCB 5 CVC 2 CVC 3 CVC 4 CVC 5 CVD D RVD D CCT 1 ZD1 TEP VR VSS VHC RUC O RCT LC RCT LD RTEP NTC NTC RVH C RTEP CVR CVR MCOMDO MDR CVH C1 VH C2C RVSS DVSS CCT LD RVMP2 R5436T R5436T CVSS1 CVSS 2 Typical Application Circuit for 10-cell Protection Battery Charger with Cell-balancing Enabled

NO.EA-322-240531 Typical Application Circuits 9 11-cell Protection Battery Charger with Cell-balancing Enabled (Cascade Connection) CVC 1 VC1 VC2 VDD Cell8 CB 1 Cell9 Cell10 Cell11 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RCB 1 RCB 2 RCB 3 RCB 4 CVC 2 CVC 3 CVC 4 CVD D RVD D CCT 1 CCT 2 RSENS RDR AIN RCO 1 RCO 2 RVMP ZD1 RSE TEP VR VSS VHC CVC 1 VC1 VC2 VDD Cell4 CB 1 Cell5 Cell6 Cell7 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RCB 1 RCB 2 RCB 3 RCB 4 CVC 2 CVC 3 CVC 4 CVD D RVD D2 CCT 1 ZD2 TEP VR VSS VHC RUC O RCT LC RCT LD RTEP NTC NTC RVH C2 RTEP CVR CVR MCOMDO MDR CVH C1 RVSS DVSS CCT LD RVMP2 R5436T R5436T CVC 1 VC1 VC2 VDD Cell1 CB 1 Cell2 Cell3 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLD DRAIN SEL 1 SEL 2 CTLC CT1 CT2 RVC 13 RCB 13 CVC 2 CVC 3 CVD D3 RVD D3 CCT 1 ZD3 TEP VR VSS VHC RUC O RCT LC RCT LD NTC RVH C RTEP CVR CVH C1 VH C3C CCT LD RVMP2 R5436T RCB 12 RCB 11 RVC 12 RVC 11 CVSS1 CVSS 2 Typical Application Circuit for 11-cell Protection Battery Charger with Cell-balancing Enabled (Cascade Connection)

NO.EA-322-240531 Typical Application Circuits 10 12-cell Protection Battery Charger with Cell-balancing Enabled (Cascade Connection) CVC 1 VC1 VC2 VDD Cell9 CB 1 Cell10 Cell11 Cell12 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RCB 1 RCB 2 RCB 3 RCB 4 CVC 2 CVC 3 CVC 4 CVD D RVD D CCT 1 CCT 2 RSENS RDR AIN RCO 1 RCO 2 RVMP ZD1 RSE TEP VR VSS VHC CVC 1 VC1 VC2 VDD Cell5 CB 1 Cell6 Cell7 Cell8 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RCB 1 RCB 2 RCB 3 RCB 4 CVC 2 CVC 3 CVC 4 CVD D RVD D2 CCT 1 ZD2 TEP VR VSS VHC RUC O RCT LC RCT LD RTEP NTC NTC RVH C2 RTEP CVR CVR MCOMDO MDR CVH C1 RVSS DVSS CCT LD RVMP2 R5436T R5436T CVC 1 VC1 VC2 VDD Cell1 CB 1 Cell2 Cell3 Cell4 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLD DRAIN SEL 1 SEL 2 CTLC CT1 CT2 RVC 13 RCB 13 CVC 2 CVC 3 CVC 4 CVD D3 RVD D3 CCT 1 ZD3 TEP VR VSS VHC RUC O RCT LC RCT LD NTC RVH C RTEP CVR CVH C1 VH C3C CCT LD RVMP2 R5436T RCB 12 RCB 11 RCB 10 RVC 12 RVC 11 RVC 10 CVSS1 CVSS 2 Typical Application Circuit for 12-cell Protection Battery Charger with Cell-balancing Enabled (Cascade Connection)

NO.EA-322-240531 Typical Application Circuits 11 13-cell Protection Battery Charger with Cell-balancing Enabled (Cascade Connection) CVC 1 VC1 VC2 VDD Cell9 CB 1 Cell10 Cell11 Cell12 Cell13 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RVC 5 RCB 1 RCB 2 RCB 3 RCB 4 RCB 5 CVC 2 CVC 3 CVC 4 CVC 5 CVD D RVD D CCT 1 CCT 2 RSENS RDR AIN RCO 1 RCO 2 RVMP ZD1 RSE TEP VR VSS VHC CVC 1 VC1 VC2 VDD Cell5 CB 1 Cell6 Cell7 Cell8 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RCB 1 RCB 2 RCB 3 RCB 4 CVC 2 CVC 3 CVC 4 CVD D RVD D2 CCT 1 ZD2 TEP VR VSS VHC RUC O RCT LC RCT LD RTEP NTC NTC RVH C2 RTEP CVR CVR MCOMDO MDR CVH C1 RVSS DVSS CCT LD RVMP2 R5436T R5436T CVC 1 VC1 VC2 VDD Cell1 CB 1 Cell2 Cell3 Cell4 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLD DRAIN SEL 1 SEL 2 CTLC CT1 CT2 RVC 13 RCB 13 CVC 2 CVC 3 CVC 4 CVD D3 RVD D3 CCT 1 ZD3 TEP VR VSS VHC RUC O RCT LC RCT LD NTC RVH C RTEP CVR CVH C1 VH C3C CCT LD RVMP2 R5436T RCB 12 RCB 11 RCB 10 RVC 12 RVC 11 RVC 10 CVSS1 CVSS 2 Typical Application Circuit for 13-cell Protection Battery Charger with Cell-balancing Enabled (Cascade Connection)

NO.EA-322-240531 Typical Application Circuits 12 14-cell Protection Battery Charger with Cell-balancing Enabled (Cascade Connection) CVC 1 VC1 VC2 VDD Cell10 CB 1 Cell11 Cell12 Cell13 Cell14 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RVC 5 RCB 1 RCB 2 RCB 3 RCB 4 RCB 5 CVC 2 CVC 3 CVC 4 CVC 5 CVD D RVD D CCT 1 CCT 2 RSENS RDR AIN RCO 1 RCO 2 RVMP ZD1 RSE TEP VR VSS VHC CVC 1 VC1 VC2 VDD Cell5 CB 1 Cell6 Cell7 Cell8 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RCB 1 RCB 2 RCB 3 RCB 4 CVC 2 CVC 3 CVC 4 CVD D RVD D2 CCT 1 ZD2 TEP VR VSS VHC RUC O RCT LC RCT LD RTEP NTC NTC RVH C2 RTEP CVR CVR MCOMDO MDR CVH C1 RVSS DVSS CCT LD RVMP2 R5436T R5436T CVC 1 VC1 VC2 VDD Cell1 CB 1 Cell2 Cell3 Cell4 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLD DRAIN SEL 1 SEL 2 CTLC CT1 CT2 RVC 13 RCB 13 CVC 2 CVC 3 CVC 4 CVD D3 RVD D3 CCT 1 ZD3 TEP VR VSS VHC RUC O RCT LC RCT LD NTC RVH C RTEP CVR CVH C1 VH C3C CCT LD RVMP2 R5436T RCB 12 RCB 11 RCB 10 RVC 12 RVC 11 RVC 10 CVSS1 CVSS 2 RVC5 CVC5 Cell9 RCB5 Typical Application Circuit for 14-cell Protection Battery Charger with Cell-balancing Enabled (Cascade Connection)

NO.EA-322-240531 Typical Application Circuits 13 15-cell Protection Battery Charger with Cell-balancing Enabled (Cascade Connection) CVC 1 VC1 VC2 VDD Cell11 CB 1 Cell12 Cell13 Cell14 Cell15 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RVC 5 RCB 1 RCB 2 RCB 3 RCB 4 RCB 5 CVC 2 CVC 3 CVC 4 CVC 5 CVD D RVD D CCT 1 CCT 2 RSENS RDR AIN RCO 1 RCO 2 RVMP ZD1 RSE TEP VR VSS VHC CVC 1 VC1 VC2 VDD Cell6 CB 1 Cell7 Cell8 Cell9 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLC DRAIN SEL 1 SEL 2 CTLD CT1 CT2 RVC 1 RVC 2 RVC 3 RVC 4 RCB 1 RCB 2 RCB 3 RCB 4 CVC 2 CVC 3 CVC 4 CVD D RVD D2 CCT 1 ZD2 TEP VR VSS VHC RUC O RCT LC RCT LD RTEP NTC NTC RVH C2 RTEP CVR CVR MCOMDO MDR CVH C1 RVSS DVSS CCT LD RVMP2 R5436T R5436T CVC 1 VC1 VC2 VDD Cell1 CB 1 Cell2 Cell3 Cell4 VC3 VC4 VC5 VSS0 CB 2 CB 3 CB 4 CB 5 SEN S VMP COUT DOUT CTLD DRAIN SEL 1 SEL 2 CTLC CT1 CT2 R VC 1 R CB 1 CVC 2 CVC 3 CVC 4 CVD D3 RVD D3 CCT 1 ZD3 TEP VR VSS VHC RUC O RCT LC RCT LD NTC RVH C RTEP CVR CVH C1 VH C3C CCT LD RVMP2 R5436T R CB2 R CB3 R CB4 R VC2 R VC3 R VC4 CVSS1 CVSS 2 Cell5 CVC5 R CB5 Cell10 RCB5 CVC5 R VC5 Typical Application Circuit for 15-cell Protection Battery Charger with Cell-balancing Enabled (Cascade Connection)

NO.EA-322-240531 External Components Symbol Value (Typ.) Range Unit Remarks(1) RVDDX 330 330 to 1000 Ω Refer to Technical Note [1]. RVC1X 330 330 to 1000 Ω Refer to Technical Note [2]. RVC2X 330 330 to 1000 Ω RVC3X 330 330 to 1000 Ω RVC4X 330 330 to 1000 Ω RVC5X 330 330 to 1000 Ω RCB1X 100 Note [3] Ω Refer to Technical Note [3]. RCB2X 100 Note [3] Ω RCB3X 100 Note [3] Ω RCB4X 100 Note [3] Ω RCB5X 100 Note [3] Ω RSENS 100 1 or more mΩ Depending on Set Value of Overcurrent RSE 10 1 to 10 kΩ Refer to Technical Note [4]. RDRAIN 75 Note [5] kΩ Refer to Technical Note [5]. RCO1 1 Note [5] MΩ RCO2 2 Note [5] MΩ RVMP1 10 0.01 to 10 MΩ Refer to Technical Note [6]. RVMP2 1 1 MΩ RVMP3 1 1 MΩ RCTLC 1 1 to 10 kΩ - RCTLD 10 10 to 100 kΩ Refer to Technical Note [17]. RUCOX, RUDO 3 3 MΩ Refer to Technical Note [7] and [19]. RVSS 10 10 Ω Refer to Technical Note [15]. CVSS1 1 1 µF CVSS2 1 0.1 to 1 µF CVDDX 1 0.1 to 1 µF Refer to Technical Note [1]. CVC1X 0.1 0.1 µF Refer to Technical Note [2]. CVC2X 0.1 0.1 µF CVC3X 0.1 0.1 µF CVC4X 0.1 0.1 µF CVC5X 0.1 0.1 µF CCT1X 33 10 to 1000 nF - (1) Refer to “Technical Notes for External Components” for details.

NO.EA-322-240531 Symbol Value (Typ.) Range Unit Remarks(1) CCT2X 3.3 2.2 or more nF Refer to Technical Note [8]. CVRX 1 1 µF Refer to Technical Note [9]. CCTLD 33 10 to 100 nF Refer to Technical Note [17]. CVHCX 10 3.3 to 10 nF Refer to Technical Note [18]. ZDX 30 30 or less V Refer to Technical Note [10]. Recommended Component: MM1Z30_0.5W_30V_J_SOD-123_EIC RVHCX 5 5 to 10 MΩ Refer to Technical Note [11]. RTEPX 350 300 and more kΩ Refer to Technical Note [12]. 100 kΩ level at ambient temperature NTCX 100 100 kΩ Refer to Technical Note [12]. SBDVSS - - Refer to Technical Note [15]. Recommended Component: RB491D_SOT-23 DX - - Refer to Technical Note [16]. Recommended Component: 1N4148_100mA/100V_4nS_SOT-23 MCO - - Refer to Technical Note [13]. MDO - - MDR - - Refer to Technical Note [14]. Component Selection Guide

  • The typical application circuit diagrams are just examples. The operation in application circuits is not guaranteed. Be sure to perform a sufficient evaluation with the external components under the actual usage conditions for selection.
  • Be careful not to apply the overvoltage and the overcurrent which exceed the rating to the protection IC and external components . Especially, select an FET with enough current capacity to endure the large current because a large current might flow through the FET during the time between an overcharge detection a blown fuse. Technical Notes for External Components 【1】 The voltage fluctuation is stabilized with R VDD and CVDD. If a small R VDD is set, in the case of the large transient may happen to the cell voltage, by the flowing current, the IC may be unstable. If a large RVDD is set, by the consumption current of the IC itself, the voltage difference between V DD pin and VC1 pin is generated, and unexpected operation may result. Therefore, the appropriate value range of R VDD is from 330Ω to 1kΩ. To make a stable operation of the IC, the appropriate value range of C VDD is from 0.1µF to 1.0µF. (1) Refer to “Technical Notes for External Components” for details.

NO.EA-322-240531 【2】 RVCxx, CVCxx stabilize the voltage fluctuation. If large RVCxx is set, the detector threshold will be high because of the internal conduction current of the IC. The operation error of open-wire detector function may happen easily by the distribution of the ICs or environment. If small R VCxx is set, the effect by noise will be large. Therefore, the appropriate value range of R VCxx is from 330Ω to 1k Ω. To make stable operation, use 0.1µF as CVCxx. 【3】 When the cell balance function is necessary, RCBxx must be chosen carefully with considering the bypass current, and consumption power by the bypass current, and the external MOSFET. Especially, if a small resistance (to set the large bypass current) is set, fully evaluation is necessary. If a large resistance (to set the small bypass current) is set, the time for cell balance will be long. 【4】 When the cascade connection is used, if short circuit is happened, by the short current and the R SENS enlarges the voltage, and as a result, if the voltage of SENS pin becomes larger than the VDD of the IC, during the short circuit output delay time, the current flows into SENS pin. Therefore, if a small RSE is set, a large current may flow into SENS pin. If a large RSE is set, the over-current detector threshold may shift. Therefore, the appropriate value is around 10kΩ. 【5】 Choose appropriate values for RDRAIN, RCO1, and RCO2 to satisfy the next equation, otherwise, the release from excess discharge current and short may be impossible. 𝑅𝑅𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝑁𝑁 < 𝑉𝑉𝐷𝐷𝑇𝑇𝑅𝑅3 × (𝑅𝑅𝑁𝑁𝐶𝐶1 + 𝑅𝑅𝑁𝑁𝐶𝐶2) 𝑉𝑉𝐷𝐷𝐷𝐷⁄ If small RCO1 or RCO2 is set, when the output of C OUT is "H", the consumption current of protection circuit board increases. If large RCO1 or RCO2 is set, when the output of COUT is "Hi-z", the speed for pull-down the gate of the charge FET becomes slow and turning off the FET will be slow. Dividing between the "Hi -z" output and the resistance might be not enough to turn OFF the charge FET. If a small RDRAIN is set, when the excess discharge current and short circuit is detected, the large current may flow until the load is removed. 【6】 When the cascade connection is used, if DOUT turns off, VMP pin is pulled up via RVMP to the top cell. In this case, the current flows via RVMP and the internal diode, therefore, appropriate value must be chosen (usually MΩ level). If the cascade connection is not used, around 10kΩ is acceptable. 【7】 Set RUCO to satisfy RUCO=RCO1+RCO2. If an extremely large resistance is set, when the output of C OUT is "Hi-Z", by the dividing resistance, CTLC pin may not be pulled down. If a small resistance is used, when the output of COUT is "H", the consumption current via RUCO increases. 【8】 If a too small CCT2 is set, excess discharge current detector output delay time 2 becomes shorter than the short circuit output delay time. Therefore, use a capacitor with 0.0022µF or more.

NO.EA-322-240531 【9】 To make a stable VR output, it should connect a 1.0µF capacitor to VR pin. 【10】 Considering the break-down of the resistors and capacitors to stabilize the fluctuation of the voltage, to avoid that the high voltage is directly forced to the IC, adding a zener diode is our recommendation. Connect the zener diode between VDD pin of the IC and VSS pin directly. (Refer to the typical application circuits.) Zener diode MM1Z30_0.5W_30V_J_SOD-123_EIC is recommended. 【11】 When the cascade connection is used, the lower side IC can transfer the VMP signal to upper side IC through VHC pin by pulling up VHC pin to the upper side IC’s VC5 level through RVHC. The recommended value of RVHC is 5MΩ. If the upper side IC works at 4-cell protection mode, VHC pin should be pulled up to upper side IC’s VC4 level. If the upper side IC works at 3- cell protection mode, VHC pin should be pulled up to upper side IC’s VC3 level. 【12】 The temperature protection function is realized by the voltage divider between a resistor of RTEP and an NTC thermistor. RTEP is equal to 20 times RNTC at the desired protecting temperature. Choose an NTC thermistor with a high resistance capability to reduce the IC consumption current since VR pin cannot supply a large current. Using the high-accuracy thermistor and resistor can b e realized more high- accuracy temperature protection. 【13】 As for the charge control FET (MCO) and the discharge control FET (MDO), be sure to perform a sufficient consideration of their maximum voltage tolerance, current rating, maximum power consumption and peak consumption when short-circuit. 【14】 As for the pull -down FET (MDR), be sure to perform a sufficient consideration to its maximum voltage tolerance. 【15】 Schottky Diode (SBDVSS) is required to prevent VSS pin voltage from being larger than VSS0 pin voltage. 【16】 Diode (DX) is required to prevent a drop in the VDD pin voltage (VDD), along with the battery voltage drop. 【17】 CCTLD and RCTLD make CTLD pin’s transmission stable. 【18】 CVHC makes VHC pin signal stable.

NO.EA-322-240531 TECHNICAL NOTES A peripheral component or the device mounted on PCB should not exceed a rated voltage, a rated current or a rated power. When designing a peripheral circuit, please be fully aware of the following points.

  • Please evaluate the product at the PCB level before use, as some symptoms may remain that cannot be confirmed by the evaluation at the IC level.
  • When using any coating or underfill to improve moisture resistance or joining strength, evaluate them adequately before using. In certain materials or coating conditions, corrosion by contained constituents, current leakage by moisture absorption, crack and delamination by physical stress can happen. If the curing temperature of the coating material or underfill material exceeds the absolute maximum rating, the electrical characteristics of this product may change.
  • When performing X-ray inspection in mass production process and evaluation build stage such as the product functions and characteristics confirmation, please confirm X -ray irradiation does not exceed 1.5Gy (absorbed dose for air).

POWER DISSIPATION TSSOP-28 PD-TSSOP-28-(85125)-JE-D i The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following measurement conditions are based on JEDEC STD.51. Measurement Conditions Item Measurement Conditions Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Four-Layer Board) Board Dimensions 76.2 mm × 114.3 mm × 1.6 mm Copper Ratio Outer Layers (First and Fourth Layers): Less than 10% of 60 mm Square Inner Layers (Second and Third Layers): 100% of 74.2 mm Square Through-holes  0.85 mm × 44 pcs Measurement Result (Ta = 25°C, Tjmax = 125°C) Measurement Result Power Dissipation 1250 mW Thermal Resistance ja = (125 − 25°C) / 1.25 W = 80°C/W jc = 25°C/W Power Dissipation vs. Ambient Temperature Measurement Board Pattern 76.2 114.3 1750 1500 1250 1000 750 500 250 Ambient Temperature (°C) Power Dissipation PD (mW) 100 125 1250

PACKAGE DIMENSIONS TSSOP-28 Ver. A i

Ver. AW i : Product Code … Refer to Part Marking List : Lot Number … Alphanumeric Serial Number R5436T (TSSOP-28) Part Markings NOTICE There can be variation in the marking when different AOI (Automated Optical Inspection) equipment is used. In the case of recognizing the marking characteristic with AOI, please contact our s ales or distributor before attempting to use AOI. R5436T Part Marking List R5436TxxxBA R5436TxxxBB R5436T502BA D502BA R5436T502BB D502BB R5436T503BA D503BA R5436T503BB D503BB R5436T504BA D504BA R5436T504BB D504BB R5436T505BA D505BA R5436T505BB D505BB R5436T506BA D506BA R5436T506BB D506 BB R5436T507BA D507BA R5436T507BB D507B B R5436T508BA D508BA R5436T508BB D508BB R5436T509BA D509BA R5436T511BB D511BB R5436T510BA D510BA R5436T512BB D512 BB R5436T511BA D511BA R5436T513BB D513BB R5436T516BA D516 BA R5436T514BB D514BB R5436T401BA D401BA R5436T515BB D515 BB 

Ver. AW ii R5436T Part Marking List (Continued) R5436TxxxBA R5436TxxxBB R5436T517BB D517 BB R5436T518BB D518 BB R5436T519BB D519 BB R5436T520BB D5 20 BB R5436T521BB D5 21 BB R5436T522BB D5 22 BB R5436T524BB D5 2 4 BB

  1. T he products and the product specifications described in this document are subject to change or discontinuation of production without notice for reasons such as improvement. Therefore, before deciding to use the products, please refer to our sales representatives for the latest information thereon. 2. The materials in this document may not be copied or otherwise reproduced in whole or in part without the prior written consent of us. 3. This product and any technical information relating thereto are subject to complementary export controls (so- called KNOW controls) under the Foreign Exchange and Foreign Trade Law, and related politics ministerial ordinance of the law. (Note that the complementary export controls are inapplicable to any application-specific products, except rockets and pilotless aircraft, that are insusceptible to design or program changes.) Accordingly, when exporting or carrying abroad this product, follow the Foreign Exchange and Foreign Trade Control Law and its related regulations with respect to the complementary export controls. 4. The technical information described in this document shows typical characteristics and example application circuits for the products. The release of such information is not to be construed as a warranty of or a grant of license under our or any third party's intellectual property rights or any other rights. 5. The products listed in this document are intended and designed for use as general electronic components in standard applications (office equipment, telecommunication equipment, measuring instruments, consumer electronic products, amusement equipment etc.). Those customers intending to use a product in an application requiring extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of the product could result in human injury or death should first contact us.
  • Aerospace Equipment
  • Equipment Used in the Deep Sea
  • Power Generator Control Equipment (nuclear, steam, hydraulic, etc.)
  • Life Maintenance Medical Equipment
  • Fire Alarms / Intruder Detectors
  • Vehicle Control Equipment (automotive, airplane, railroad, ship, etc.)
  • Various Safety Devices
  • Traffic control system
  • Combustion equipment In case your company desires to use this product for any applications other than general electronic equipment mentioned above, make sure to contact our company in advance. Note that the important requirements mentioned in this section are not applicable to cases where operation requirements such as application conditions are confirmed by our company in writing after consultation with your company. 6. We are making our continuous effort to improve the quality and reliability of our products, but semiconductor products are likely to fail with certain probability. In order to prevent any injury to persons or damages to property resulting from such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy feature, fire containment feature and fail-safe feature. We do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products. 7. The products have been designed and tested to function within controlled environmental conditions. Do not use products under conditions that deviate from methods or applications specified in this datasheet. Failure to employ the products in the proper applications can lead to deterioration, destruction or failure of the products. We shall not be responsible for any bodily injury, fires or accident, property damage or any consequential damages resulting from misuse or misapplication of the products. 8. Quality Warranty 8-1. Quality Warranty Period In the case of a product purchased through an authorized distributor or directly from us, the warranty period for this product shall be one (1) year after delivery to your company. For defective products that occurred during this period, we will take the quality warranty measures described in section 8-2. However, if there is an agreement on the warranty period in the basic transaction agreement, quality assurance agreement, delivery specifications, etc., it shall be followed. 8-2. Quality Warranty Remedies When it has been proved defective due to manufacturing factors as a result of defect analysis by us, we will either deliver a substitute for the defective product or refund the purchase price of the defective product. Note that such delivery or refund is sole and exclusive remedies to your company for the defective product. 8-3. Remedies after Quality Warranty Period With respect to any defect of this product found after the quality warranty period, the defect will be analyzed by us. On the basis of the defect analysis results, the scope and amounts of damage shall be determined by mutual agreement of both parties. Then we will deal with upper limit in Section 8-2. This provision is not intended to limit any legal rights of your company. 9. Anti-radiation design is not implemented in the products described in this document. 10. The X-ray exposure can influence functions and characteristics of the products. Confirm the product functions and characteristics in the evaluation stage. 11. WLCSP products should be used in light shielded environments. The light exposure can influence functions and characteristics of the products under operation or storage. 12. Warning for handling Gallium and Arsenic (GaAs) products (Applying to GaAs MMIC, Photo Reflector). These products use Gallium (Ga) and Arsenic (As) which are specified as poisonous chemicals by law. For the prevention of a hazard, do not burn, destroy, or process chemically to make them as gas or power. When the product is disposed of, please follow the related regulation and do not mix this with general industrial waste or household waste. 13. Please contact our sales representatives should you have any questions or comments concerning the products or the technical information. Official website https://www.nisshinbo-microdevices.co.jp/en/ Purchase information https://www.nisshinbo-microdevices.co.jp/en/buy/