R5432V503BB

Nisshinbo Micro Devices...

3 to 5 Cells Li-ion Battery Protector IC

Manufacturer: Nisshinbo Micro Devices...

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R5432V NISSHINBO | Alldatasheet

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3 to 5 Cells Li-ion Battery Protector IC NO.EA-263-1600711 OUTLINE The R5432V is a high voltage CMOS-based protection IC for overcharge /discharge of rechargeable three-cell / four-cell / five- cell Lithium-ion / Lithium- polymer battery, further include a short circuit and the protection circuits against the excess discharge current and excess charge current. Each of these ICs is composed of eighteen voltage detectors (fourteen for 3cell protection type, sixteen for 4cell protection type), a reference circuit, a delay circuit, a short detector circuit, an oscillator, a counter and a logic circuit. The output of COUT is P-channel open-drain type, and DOUT is CMOS type. If the overcharge voltage or over charge current is detected by the R5432V, after the preset output delay time, the output of COUT becomes Hi-Z. While the overdischarge voltage or current is detected, after the preset output delay time, the output of DOUT becomes ”L”. After detecting overcharge voltage, when the cell voltage returns lower than the overcharge released voltage, then overcharge is released and the output of COUT becomes “H”. After detecting overcharge current, by disconnecting a charger and connecting a load, then overcharge current is released and the output of COUT becomes “H”. After detecting overdischarge voltage, when the cell voltage becomes the released voltage from overdischarge or more, then overdischarge is released and the output of DOUT becomes “H”. After detecting overdischarge current and short circuit, by disconnecting the load, the function of the output of DRAIN pin, the external NMOSFET turns on, and VMP pin voltage is pulled down by the resistance connected to GND and released overdischarge current or short and the output of DOUT becomes “H”. By forcing a certain voltage to SEL1 and SEL2 pins, the testing time of protection circuits can be short. Specifically, overcharge, discharge, over current delay time can be shortening into approximately 1/80. The R5432V can protect 6-cell or more by connecting 2 pieces of the R5432V in cascade. High side IC’s COUT and DOUT must connect to CTLC and CTLD respectively of the low side IC. As a result, the signal of the high side of COUT and DOUT is transmit to the lower side IC, and control FETs for charge and discharge. The R5432V has cell-balance function to solve the unbalance condition of serially connected cells. If cell voltage is beyond the cell balance detector threshold, by the output of the cell balance control pin, the external NMOSFET turns on, and a current path is made, and during charge, charge current is bypassed, otherwise, cell is discharged until the cell voltage becomes the released voltage from cell-balance operation. If the connection between a cell and a protection board is broken, the open-wire condition is detected by the R5432V, and the output of COUT becomes Hi-Z. After detecting the open-wire, when the cell and the protection board is connected again, the open-wire detector is released and the output of COUT becomes “H”.

FEATURES

Detector thresholds range and accuracy 0.1V to 0.2V (10mV step) (±20mV) for AD/BD ver. 0.25V to 0.40V for BB/BC ver. 0.25V/0.3V(Vdet3-1+0.1V or more) for AD/BD ver.

NO.EA-263-160711 0.75V for BB/BC ver. Vdet3-2 x 1.67 for AD/BD ver. up to 3.4V Output delay time Functions discharge voltage and current is reduced approximately 1/80. Overcharge delay time can be shorten into around 4ms for testing. overdischarge, the output of COUT becomes “Hi-Z”, the output of DOUT becomes “L”. state “H”(VDD), Detected state “Hi-Z”. DOUT: 12V regulator source CMOS output. Normal state “H”(12V), Detected state “L”. supervised.

NO.EA-263-160711 BLOCK DIAGRAMS R5432VxxxBA VC2 VC1 Vnochg1 VD2-1 VD1-1 Vnochg2 VD2-2 VD1-2 Vnochg3 VD2-3 VD1-3 Vnochg4 VD2-4 VD1-4 VC3 VC4 VC5 SEL1 VDD VD2-5 VD1-5 Vnochg5 VSS Logic Circuit SEL2 Logic Circuit CB2 CB1 CB3 CB4 CTLT CB5 CB Circuit-1 CB Circuit-2 CB Circuit-3 CB Circuit-4 CB Circuit-5 Delay Short Circuit SENS Ds Circuit Logic Circuit Logic Circuit Regulator Regulator CT1 CT2 DRAIN VMP CTLD CTLC Logic Circuit DOUT COUT tVDET2 VD3-2 VD3-1 VD4 T Stop T Start odd sw even sw tVDET3 Counter Oscillatpr

NO.EA-263-160711 SELECTION GUIDE Product Name Package Quantity per Reel Pb Free Halogen Free R5432Vxxx$∗ SSOP-24 3000 Yes Yes xxx :Serial Number for the R5432V designating voltages such as overcharge threshold, overcharge released voltage, Cell-balance threshold, Cell-balance released voltage, overdischarge threshold, o verdischarge released voltage, overdischarge current1/2, overcharge current, short voltage. $ : Designation of Output delay option. Overcharge Delay time (s) Overdischarge Delay time (ms) Overdischarge Current Delay time1 (ms) Overdischarge Current Delay time2 (ms) Overcharge Current Delay time (ms) Short Delay time (µs) A 1.0 3.64×CCT1 (nF) 3.05×CCT2 (nF) tVDET31/ 100 8 300 B 1.0 3.88×CCT1 (nF) 3.26×CCT2 (nF) tVDET31/ 6 8 300 *capacitor for CT1: CCT1, capacitor for CT2:CCT2. ∗ : Designation of Output delay option. Overcharge Released condition Overdischarge Released condition 0V battery Charge Short detector Threshold Open-wire detection Cascade connection A Auto Release Auto Release Acceptable 1.0V Available Available B Auto Release Auto Release Unacceptable 0.75V Available Available C Auto Release Auto Release Acceptable 0.75V Available Available D Auto Release with hysteresis cancellation Auto Release Acceptable VDET32 x 1.67 Available Available

NO.EA-263-160711 1) Product Code List Code VDET1n (V) *1 VREL1n (V) *1 VCBDn (V) *1 VCBRn (V) *1 VDET2n (V) *1 VREL2n (V) *1 VDET31 (V) VDET32 (V) VSHORT (V) VDET4 (V) *1：n＝1,2,3,4,5

NO.EA-263-160711 PIN DESCRIPTIONS SSOP-24 1 5 2 3 4 6 7 8 16 15 14 13 9 10 11 12 17 18 19 20 21 22 23 24 Pin No Symbol Pin Description

1 CTLC COUT control pin

2 CTLD D OUT control pin

3 COUT Output pin of overcharge detection, Pch OPEN DRAIN output

4 VMP Pin for charger negative input

5 DRAIN Release from Excess discharge-current threshold Pin

6 DOUT Output pin of overdischarge detection,CMOS output

7 SENS Current sense pin

8 CTLT Disconnection detection movement interval setting capacitance pin

9 VSS VSS pin. Ground pin for the IC

10 CT1 tVDET2 setting capacitance connection pin

11 CT2 tVDET3 setting capacitance connection pin

12 SEL1 3cell/4cell/5cell alternative pin1

13 SEL2 3cell/4cell/5cell alternative pin2

14 CB5 CELL5 Cell balance Control pin

15 VC5 Positive terminal pin for Cell5

16 CB4 CELL4 Cell balance Control pin

17 VC4 Positive terminal pin for Cell4

18 CB3 CELL3 Cell balance Control pin

19 VC3 Positive terminal pin for Cell3

20 CB2 CELL2 Cell balance Control pin

21 VC2 Positive terminal pin for Cell2

22 CB1 CELL1 Cell balance Control pin

23 VC1 Positive terminal pin for Cell1

24 VDD VDD pin

NO.EA-263-160711 ABSOLUTE MAXIMUM RATINGS Symbol Item Rating Unit VDD Supply voltage -0.3 to 30 V Input voltage VC1 Positive input pin for Cell1 VC2-0.3 to VC2+6.5 V VC2 Positive input pin for Cell2 VC3-0.3 to VC3+6.5 V VC3 Positive input pin for Cell3 VC4-0.3 to VC4+6.5 V VC4 Positive input pin for Cell4 VC5-0.3 to VC5+6.5 V VC5 Positive input pin for Cell5 -0.3 to 6.5 V VMP Charger negative terminal input pin -0.3 to 30.0 V VSEL1 3Cell/4Cell/5Cell alternative pin1 -0.3 to VDD+0.3 V VSEL2 3Cell/4Cell/5Cell alternative pin2 -0.3 to VDD+0.3 V VCTLC COUT control pin -0.3 to VDD+25 V -0.3 to 48 VCTLD DOUT control pin -0.3 to VDD+25 V -0.3 to 48 VSENSE Current sense pin -0.3 to VDD+0.3 V VCT1 Delay time setting pin1 -0.3 to 3.5 V VCT2 Delay time setting pin2 -0.3 to 3.5 V VCTLT Disconnection detection movement interval setting capacitance pin -0.3 to 3.5 V Output voltage VCOUT Output pin of overcharge detection,CMOS output VDD-30 to VDD+0.3 V VDOUT Output pin of overdischarge detection,CMOS output -0.3 to VOH2+0.3 V VDRAIN Release from Excess discharge-current threshold Pin -0.3 to VOH3+0.3 V VCB1 Cell balance Control pin for Cell1 VC2-0.3 to VC2+6.5 V VCB2 Cell balance Control pin for Cell2 VC3-0.3 to VC3+6.5 V VCB3 Cell balance Control pin for Cell3 VC4-0.3 to VC4+6.5 V VCB4 Cell balance Control pin for Cell4 VC5-0.3 to VC5+6.5 V VCB5 Cell balance Control pin for Cell5 -0.3 to 6.5 V PD Power dissipation(1) 770 mW Ta Operating temperature range -40 to 85 °C Tstg Storage temperature range -55 to 125 °C ABSOLUTE MAXIMUM RATINGS Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause the permanent damages and may degrade the life time and safety for both device and system using the device in the field. The functional operations at or over these absolute maximum ratings are not assured. (1) Refer to POWER DISSIPATION for detailed information.

NO.EA-263-160711

ELECTRICAL CHARACTERISTICS

R5432VxxxBA Unless otherwise specified, Ta=25°C Symbol Items Conditions Min. Typ. Max. Unit Circuit VDD1 Operating input voltage V DD-VSS 2 25 V - VDET1n CELLn Overcharge threshold (n=1,2,3,4,5) Detect rising edge of supply voltage VDET1n -0.025 VDET1n VDET1n +0.025 V A VREL1n CELLn Overcharge released Voltage (n=1,2,3,4,5) Detect falling edge of supply voltage VREL1n -0.050 VREL1n VREL1n +0.050 V A tVDET1 Output delay of overcharge VDD=VC1,VCELLn=3.5V (n=2,3,4,5), tVREL1 Output delay of release from overcharge VDD=VC1, VCELLn=3.5V (n=2,3,4,5), VCELL1=4.5V→3.5V 11 16 21 ms B VCBDn CELLn balance threshold (n=1,2,3,4,5) Detect rising edge of supply voltage VCBDn -0.025 VCBDn VCBDn +0.025 V C VCBRn CELLn balance released threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VCBRn -0.050 VCBRn Lower of VCBRn +0.050 or VCBDn +0.025 V C VDET2n CELLn Overdischarge threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VDET2n ×0.975 VDET2n VDET2n ×1.025 V D VREL2n CELLn Overdischarge released Voltage (n=1,2,3,4,5) Detect rising edge of supply voltage VREL2n ×0.975 VREL2n VREL2n ×1.025 V D ICT1 CT1 charge Current VDD=VC1, VCELLn=3.5V (n=2, 3, 4, 5), VCELL1=3.5V→1.5V 350 500 650 nA E VDCT1 CT1 detector voltage VDD=VC1, VCELLn=3.5V tVDET2 Output delay of overdischarge tVDET2=CCT1×VDCT1/ICT1 CCT1=33nF 89 128 167 ms - tVREL2 Output delay of release from overdischarge VDD=VC1, VCELLn=3.5V VCELL1=1.5V→3.5V 0.7 1.2 1.7 ms G VDET31 Excess discharge-current threshold1 VDD=VC1, VCELLn=3.5V Detect rising edge of supply voltage VDET31 -0.020 VDET31 VDET31 +0.020 V H VDET32 Excess discharge-current Threshold2 VDD=VC1, VCELLn=3.5V Detect rising edge of supply voltage 0.500 0.600 0.700 V I VREL3 Output delay of release from Excess discharge-current threshold VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), SENSE=0V Detect falling edge of supply voltage VDET31 ×0.50 VDET31 ×0.75 VDET31 ×１.00 V H ICT231 CT2 Charge Current1 VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS→0.4V 350 500 650 nA I ICT232 CT2 Charge Current2 VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS→0.7V 2.0 3.0 4.0 µA I VDCT2 CT2 Charge voltage VDD=VC1, VCELLn =3.5V (n=2,3,4,5) tVDET31 Output delay of Excess discharge-current threshold1 tVDET31=CCT2×VDCT2/ICT231 CCT2=3.3nF 7.3 10.8 14.7 ms - tVDET32 Output delay of Excess discharge-current Threshold2 tVDET32=CCT2×VDCT2/ICT232 CCT2=3.3nF 1.25 1.8 2.4 ms - tVREL3 Output delay of release from Excess discharge-current Threshold VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5) SENS=0.4V, VMP= 4.0V 0.7 1.2 1.7 ms H

NO.EA-263-160711 Symbol Items Conditions Min. Typ. Max. Unit Circuit Vshort Short protection voltage VDD=VC1, VCELLn=3.5V Detect rising of supply voltage 0.7 1.0 1.7 V K tshort Output Delay of Short protection VDD=VC1, VCELLn =3.5V VMP=4.0V 180 300 550 µs K VDET4 Excess charge-current threshold VDD=VC1, VCELLn=3.5V Detect falling edge of supply voltage VDET4 -0.030 VDET4 VDET4 +0.030 V L tVDET4 Output delay of Excess charge-current threshold VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V→-1.0V 5 8 11 ms L tVrel4 Output delay of release from Excess charge-current threshold VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=VSS,VMP=-1.0V→1.0V 0.7 1.2 1.7 ms L VIH1 SEL1 pin “H” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V M VIM1 SEL1 pin “M” input voltage VDD=VC1, VCELLn =3.2V -0.5V V M VIL1 SEL1 pin “L” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +1.0 V M VIH2 SEL2 pin “H” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V N VIM2 SEL2 pin “M” input voltage VDD=VC1, VCELLn =3.2V -0.5V V N VIL2 SEL2 pin “L” input voltage VDD=VC, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V N CTLC1H C TLC pin “H1” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD +2.0 V O CTLC2H C TLC pin “H2” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V O CTLC1L C TLC pin “L” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V O CTLD1H C TLD pin “H1” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD +2.0 V P CTLD2H C TLD pin “H2” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V P CTLD1L C TLD pin “L” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V P VOL2 D OUT Nch ON voltage IOL=50μA, VDD=VC1, CTLD=VDD VCELLn =3.2V (n=1,2,3,4,5) 0.1 0.5 V Q VOL3 DRAIN Nch ON voltage IOL=50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) 0.1 0.5 V R VOL4 CB1 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC2 +0.2 VC2 +0.5 V S VOL5 CB2 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC3 +0.2 VC3 +0.5 V S VOL6 CB3 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC4 +0.2 VC4 +0.5 V S VOL7 CB4 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC5 +0.2 VC5 +0.5 V S VOL8 CB5 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) 0.2 0.5 V S

NO.EA-263-160711 Symbol Items Conditions Min. Typ. Max. Unit Circuit VOH1 C OUT Pch ON voltage IOH=-50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLC=VSS VDD -0.5 VDD -0.1 V T VVR12 VR 12V output voltage (*1) IOH=-5µA, VDD=VC1, CTLD=VSS, VCELL=3.2V (n=1, 2, 3, 4, 5) Measured to draw the current through DOUT 10 12 14 V U VOH2 D OUT Pch ON voltage (*1) IOH=-50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLD= VSS VVR12 -0.5V VVR12 -0.1V V U V OH3 DRAIN Pch ON voltage (*1) IOH=-50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) SENS =VMP =4.0V VVR12 -0.5V VVR12 -0.1V V V VOH4 CB1 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=2, 3, 4, 5) VC1 -0.5 VC1 -0.3 V W VOH5 CB2 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 3, 4, 5) VC2 -0.5 VC2 -0.3 V W VOH6 CB3 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 4, 5) VC3 -0.5 VC3 -0.3 V W V OH7 CB4 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 5) VC4 -0.5 VC4 -0.3 V W V OH8 CB5 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 4) VC5 -0.5 VC5 -0.3 V W I LCOUT C OUT pin off leak current VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) CTLC=VDD, COUT=-14V -0.1 µA X I CTLT C TLT Charge Current VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) 145 205 264 nA Y V DTLT C TLT detector threshold VDD=VC1, VCELLn=3.2V (n=1, 2, 4, 5) VC3=VD1+0.2V 1.58 2.00 2.42 V Z V RTLT C TLT released voltage VDD=VC1, VCELLn=3.2V t LT Disconnection detection Test Interval CCTLT×(VDTLT-VRTLT)/ICTLT CCTLT =3.3µF 21 30 39 s - I SS1 Supply Currnt1 VDD=VC1,COUT=OPEN VCELLn=VDET1n-0.4V (n=1, 2, 3, 4, 5) 12 30 µA a I SS2 Supply Currnt2 VDD=VC1,COUT=OPEN VCELLn=1.5V (n=1, 2, 3, 4, 5) 10 25 µA a ∗ VCELLn=CELLn voltage n=1, 2, 3, 4, 5 (*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD. RECOMMENDED OPERATING CONDITIONS (ELECTRICAL CHARACTERISTICS ) All of electronic equipment should be designed that the mounted semiconductor devices operate within the recommended operating conditions. The semiconductor devices cannot operate normally over the recommended operating conditions, even if when they are used over such conditions by momentary electronic noise or surge. The semiconductor devices may receive serious damage when they continue to operate over the recommended operating conditions.

NO.EA-263-160711

R5432VxxxBB/BC Unless otherwise specified, Ta=25°C Symbol Items Conditions Min. Typ. Max. Unit Circuit VDD1 Operating input voltage VDD-VSS 2 25 V - VDET1n CELLn Overcharge threshold (n=1,2,3,4,5) Detect rising edge of supply voltage VDET1n -0.025 VDET1n VDET1n +0.025 V A VREL1n CELLn Overcharge released Voltage (n=1,2,3,4,5) Detect falling edge of supply voltage VREL1n -0.050 VREL1n VREL1n +0.050 V A tVDET1 Output delay of overcharge VDD=VC1,VCELLn=3.5V tVREL1 Output delay of release from overcharge VDD=VC1, VCELLn=3.5V (n=2,3,4,5), VCELL1=4.5V→3.5V 11 16 21 ms B VCBDn CELLn balance threshold (n=1,2,3,4,5) Detect rising edge of supply voltage VCBDn -0.025 VCBDn VCBDn +0.025 V C VCBRn CELLn balance released threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VCBRn -0.050 VCBRn Lower of VCBRn +0.050 or VCBDn +0.025 V C VDET2n CELLn Overdischarge threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VDET2n ×0.975 VDET2n VDET2n ×1.025 V D VREL2n CELLn Overdischarge released Voltage (n=1,2,3,4,5) Detect rising edge of supply voltage VREL2n ×0.975 VREL2n VREL2n ×1.025 V D ICT1 CT1 charge Current VDD=VC1, VCELLn=3.5V (n=2, 3, 4, 5), VCELL1=3.5V→1.5V 350 500 650 nA E VDCT1 CT1 detector voltage VDD=VC1, VCELLn=3.5V tVDET2 Output delay of overdischarge tVDET2=CCT1×VDCT1/ICT1 CCT1=33nF 89 128 167 ms - tVREL2 Output delay of release from overdischarge VDD=VC1, VCELLn=3.5V VCELL1=1.5V→3.5V 0.7 1.2 1.7 ms G VDET31 Excess discharge-current threshold1 VDD=VC1, VCELLn=3.5V Detect rising edge of supply voltage VDET31 -0.020 VDET31 VDET31 +0.020 V H VDET32 Excess discharge-current Threshold2 VDD=VC1, VCELLn=3.5V Detect rising edge of supply voltage VDET32 -0.070 VDET32 VDET32 +0.070 V I VREL3 Output delay of release from Excess discharge-current threshold VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), SENSE=0V Detect falling edge of supply voltage VDET31 ×0.50 VDET31 ×0.75 VDET31 ×１.00 V H ICT231 CT2 Charge Current1 VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS→0.4V 350 500 650 nA I ICT232 CT2 Charge Current2 VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS→0.7V 2.0 3.0 4.0 µA I VDCT2 CT2 Charge voltage VDD=VC1, VCELLn =3.5V (n=2,3,4,5) SENSE=0.4V, VMP=4.0V 1.23 1.55 1.87 V J tVDET31 Output delay of Excess discharge-current threshold1 tVDET31=CCT2×VDCT2/ICT231 CCT2=3.3nF 7.3 10.8 14.7 ms - tVDET32 Output delay of Excess discharge-current Threshold2 tVDET32=CCT2×VDCT2/ICT232 CCT2=3.3nF 1.25 1.80 2.40 ms - tVREL3 Output delay of release from Excess discharge-current Threshold VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5) SENS=0.4V, VMP= 4.0V 0.7 1.2 1.7 ms H

NO.EA-263-160711 Symbol Items Conditions Min. Typ. Max. Unit Circuit Vshort Short protection voltage VDD=VC1, VCELLn=3.5V Detect rising of supply voltage 0.7 1.0 1.7 V K tshort Output Delay of Short protection VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V→2.0V,VMP=4.0V 180 300 550 μs K VDET4 Excess charge-current threshold VDD=VC1, VCELLn=3.5V Detect falling edge of supply voltage VDET4 -0.030 VDET4 VDET4 +0.030 V L tVDET4 Output delay of Excess charge-current threshold VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V→-1.0V 5 8 11 ms L tVrel4 Output delay of release from Excess charge-current threshold VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=VSS,VMP=-1.0V→1.0V 0.7 1.2 1.7 ms L VIH1 SEL1 pin “H” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V M VIM1 SEL1 pin “M” input voltage VDD=VC1, VCELLn =3.2V -0.5V V M VIL1 SEL1 pin “L” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +1.0 V M VIH2 SEL2 pin “H” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V N VIM2 SEL2 pin “M” input voltage VDD=VC1, VCELLn =3.2V -0.5V V N VIL2 SEL2 pin “L” input voltage VDD=VC, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V N CTLC1H C TLC pin “H1” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD +2.0 V O CTLC2H C TLC pin “H2” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V O CTLC1L C TLC pin “L” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V O CTLD1H C TLD pin “H1” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD +2.0 V P CTLD2H C TLD pin “H2” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V P CTLD1L C TLD pin “L” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V P VOL2 D OUT Nch ON voltage IOL=50μA, VDD=VC1, CTLD=VDD VCELLn =3.2V (n=1,2,3,4,5) 0.1 0.5 V Q VOL3 DRAIN Nch ON voltage IOL=50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) 0.1 0.5 V R VOL4 CB1 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC2 +0.2 VC2 +0.5 V S VOL5 CB2 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC3 +0.2 VC3 +0.5 V S VOL6 CB3 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC4 +0.2 VC4 +0.5 V S VOL7 CB4 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC5 +0.2 VC5 +0.5 V S VOL8 CB5 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) 0.2 0.5 V S VOH1 C OUT Pch ON voltage IOH=-50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLC=VSS VDD-0.5 V DD-0.1 V T

NO.EA-263-160711 Symbol Items Conditions Min. Typ. Max. Unit Circuit VVR12 VR 12V output voltage(*1) IOH=-5µA, VDD=VC1, CTLD=VSS, VCELL=3.2V (n=1, 2, 3, 4, 5) Measured to draw the current through DOUT 10 12 14 V U VOH2 D OUT Pch ON voltage(*1) IOH=-50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLD= VSS VVR12 -0.5V VVR12 -0.1V V U V OH3 DRAIN Pch ON voltage(*1) IOH=-50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) SENS =VMP =4.0V VVR12 -0.5V VVR12 -0.1V V V VOH4 CB1 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=2, 3, 4, 5) VC1 -0.5 VC1 -0.3 V W VOH5 CB2 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 3, 4, 5) VC2 -0.5 VC2 -0.3 V W VOH6 CB3 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 4, 5) VC3 -0.5 VC3 -0.3 V W V OH7 CB4 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 5) VC4 -0.5 VC4 -0.3 V W V OH8 CB5 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 4) VC5 -0.5 VC5 -0.3 V W I LCOUT C OUT pin off leak current VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) CTLC=VDD, COUT=-14V -0.1 µA X I CTLT C TLT Charge Current VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) 145 205 264 nA Y V DTLT C TLT detector threshold VDD=VC1, VCELLn=3.2V (n=1, 2, 4, 5) VC3=VD1+0.2V 1.58 2.00 2.42 V Z V RTLT C TLT released voltage VDD=VC1, VCELLn=3.2V tLT Disconnection detection Test Interval CCTLT×(VDTLT-VRTLT)/ICTLT CCTLT =3.3µF 21 30 39 s - Vnochgn CELLn charge inhibit maximum voltage (n=1,2,3,4,5)-for R5432V4xxxB VDD=VC1 1.100 V A I SS1 Supply Currnt1 VDD=VC1,COUT=OPEN VCELLn=VDET1n-0.4V (n=1, 2, 3, 4, 5) 12 30 µA a I SS2 Supply Currnt2 VDD=VC1,COUT=OPEN VCELLn=1.5V (n=1, 2, 3, 4, 5) 10 25 µA a ∗ VCELLn=CELLn voltage n=1, 2, 3, 4, 5 (*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD.

NO.EA-263-160711

R5432VxxxBD Unless otherwise specified, Ta=25°C Symbol Items Conditions Min. Typ. Max. Unit Circuit VDD1 Operating input voltage V DD-VSS 2 25 V - VDET1n CELLn Overcharge threshold (n=1,2,3,4,5) Detect rising edge of supply voltage VDET1n -0.025 VDET1n VDET1n +0.025 V A VREL1n CELLn Overcharge released Voltage (n=1,2,3,4,5) Detect falling edge of supply voltage VREL1n -0.050 VREL1n VREL1n +0.050 V A tVDET1 Output delay of overcharge VDD=VC1,VCELLn=3.5V tVREL1 Output delay of release from overcharge VDD=VC1, VCELLn=3.5V (n=2,3,4,5), VCELL1=4.5V→3.5V 11 16 21 ms B VCBDn CELLn balance threshold (n=1,2,3,4,5) Detect rising edge of supply voltage VCBDn -0.025 VCBDn VCBDn +0.025 V C VCBRn CELLn balance released threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VCBRn -0.050 VCBRn Lower of VCBRn +0.050 or VCBDn +0.025 V C VDET2n CELLn Overdischarge threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VDET2n ×0.975 VDET2n VDET2n ×1.025 V D VREL2n CELLn Overdischarge released Voltage (n=1,2,3,4,5) Detect rising edge of supply voltage VREL2n ×0.975 VREL2n VREL2n ×1.025 V D ICT1 CT1 charge Current VDD=VC1, VCELLn=3.5V (n=2, 3, 4, 5), VCELL1=3.5V→1.5V 350 500 650 nA E VDCT1 CT1 detector voltage VDD=VC1, VCELLn=3.5V tVDET2 Output delay of overdischarge tVDET2=CCT1×VDCT1/ICT1 CCT1=33nF 89 128 167 ms - tVREL2 Output delay of release from overdischarge VDD=VC1, VCELLn=3.5V VCELL1=1.5V→3.5V 0.7 1.2 1.7 ms G VDET31 Excess discharge-current threshold1 VDD=VC1, VCELLn=3.5V Detect rising edge of supply voltage VDET31 -0.020 VDET31 VDET31 +0.020 V H VDET32 Excess discharge-current Threshold2 VDD=VC1, VCELLn=3.5V Detect rising edge of supply voltage VDET32 -0.055 VDET32 VDET32 +0.055 V I VREL3 Output delay of release from Excess discharge-current threshold VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), SENSE=0V Detect falling edge of supply voltage VDET31 ×0.50 VDET31 ×0.75 VDET31 ×１.00 V H ICT231 CT2 Charge Current1 VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS→0.4V 350 500 650 nA I ICT232 CT2 Charge Current2 VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS→0.7V 2.0 3.0 4.0 µA I VDCT2 CT2 Charge voltage VDD=VC1, VCELLn =3.5V (n=2,3,4,5) SENSE=0.4V, VMP=4.0V 1.23 1.55 1.87 V J tVDET31 Output delay of Excess discharge-current threshold1 tVDET31=CCT2×VDCT2/ICT231 CCT2=3.3nF 7.3 10.8 14.7 ms - tVDET32 Output delay of Excess discharge-current Threshold2 tVDET32=CCT2×VDCT2/ICT232 CCT2=3.3nF 1.25 1.80 2.40 ms - tVREL3 Output delay of release from Excess discharge-current Threshold VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5) SENS=0.4V, VMP= 4.0V 0.7 1.2 1.7 ms H

NO.EA-263-160711 Symbol Items Conditions Min. Typ. Max. Unit Circuit Vshort Short protection voltage VDD=VC1, VCELLn=3.5V Detect rising of supply voltage Vshort -0.12 VDET32 x1.67 Vshort +0.17 V K tshort Output Delay of Short protection VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V→2.0V, VMP=4.0V 180 300 550 μs K VDET4 Excess charge-current threshold VDD=VC1, VCELLn=3.5V Detect falling edge of supply voltage VDET4 -0.030 VDET4 VDET4 +0.030 V L tVDET4 Output delay of Excess charge-current threshold VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=0.0V→-1.0V 5 8 11 ms L tVrel4 Output delay of release from Excess charge-current threshold VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=VSS,VMP=-1.0V→1.0V 0.7 1.2 1.7 ms L VIH1 SEL1 pin “H” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V M VIM1 SEL1 pin “M” input voltage VDD=VC1, VCELLn =3.2V -0.5V V M VIL1 SEL1 pin “L” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +1.0 V M VIH2 SEL2 pin “H” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V N VIM2 SEL2 pin “M” input voltage VDD=VC1, VCELLn =3.2V -0.5V V N VIL2 SEL2 pin “L” input voltage VDD=VC, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V N CTLC1H C TLC pin “H1” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD +2.0 V O CTLC2H C TLC pin “H2” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V O CTLC1L C TLC pin “L” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V O CTLD1H C TLD pin “H1” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD +2.0 V P CTLD2H C TLD pin “H2” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V P CTLD1L C TLD pin “L” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V P VOL2 D OUT Nch ON voltage IOL=50μA, VDD=VC1, CTLD=VDD VCELLn =3.2V (n=1,2,3,4,5) 0.1 0.5 V Q VOL3 DRAIN Nch ON voltage IOL=50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) 0.1 0.5 V R VOL4 CB1 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC2 +0.2 VC2 +0.5 V S VOL5 CB2 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC3 +0.2 VC3 +0.5 V S VOL6 CB3 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC4 +0.2 VC4 +0.5 V S VOL7 CB4 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC5 +0.2 VC5 +0.5 V S VOL8 CB5 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) 0.2 0.5 V S VOH1 C OUT Pch ON voltage IOH=-50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLC=VSS VDD -0.5 VDD -0.1 V T

NO.EA-263-160711 Symbol Items Conditions Min. Typ. Max. Unit Circuit VVR12 VR 12V output voltage(*1) IOH=-5µA, VDD=VC1, CTLD=VSS, VCELL=3.2V (n=1, 2, 3, 4, 5) Measured to draw the current through DOUT 10 12 14 V U VOH2 D OUT Pch ON voltage(*1) IOH=-50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLD= VSS VVR12 -0.5V VVR12 -0.1V V U V OH3 DRAIN Pch ON voltage(*1) IOH=-50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) SENS =VMP =4.0V VVR12 -0.5V VVR12 -0.1V V V VOH4 CB1 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=2, 3, 4, 5) VC1 -0.5 VC1 -0.3 V W VOH5 CB2 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 3, 4, 5) VC2 -0.5 VC2 -0.3 V W VOH6 CB3 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 4, 5) VC3 -0.5 VC3 -0.3 V W V OH7 CB4 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 5) VC4 -0.5 VC4 -0.3 V W V OH8 CB5 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 4) VC5 -0.5 VC5 -0.3 V W I LCOUT C OUT pin off leak current VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) CTLC=VDD, COUT=-14V -0.1 µA X I CTLT C TLT Charge Current VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) 145 205 264 nA Y V DTLT C TLT detector threshold VDD=VC1, VCELLn=3.2V (n=1, 2, 4, 5) VC3=VD1+0.2V 1.58 2.00 2.42 V Z V RTLT C TLT released voltage VDD=VC1, VCELLn=3.2V tLT Disconnection detection Test Interval CCTLT×(VDTLT-VRTLT)/ICTLT CCTLT =3.3µF 21 30 39 s - I SS1 Supply Currnt1 VDD=VC1,COUT=OPEN VCELLn=VDET1n-0.4V (n=1, 2, 3, 4, 5) 12 30 µA a I SS2 Supply Currnt2 VDD=VC1,COUT=OPEN VCELLn=1.5V (n=1, 2, 3, 4, 5) 10 25 µA a ∗ VCELLn=CELLn voltage n=1, 2, 3, 4, 5 (*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD.

NO.EA-263-160711

R5432VxxxAD Unless otherwise specified, Ta=25°C Symbol Items Conditions Min. Typ. Max. Unit Circuit VDD1 Operating input voltage V DD-VSS 2 25 V - VDET1n CELLn Overcharge threshold (n=1,2,3,4,5) Detect rising edge of supply voltage VDET1n -0.025 VDET1n VDET1n +0.025 V A VREL1n CELLn Overcharge released Voltage (n=1,2,3,4,5) Detect falling edge of supply voltage VREL1n -0.050 VREL1n VREL1n +0.050 V A tVDET1 Output delay of overcharge VDD=VC1,VCELLn=3.5V tVREL1 Output delay of release from overcharge VDD=VC1, VCELLn=3.5V (n=2,3,4,5), VCELL1=4.5V→3.5V 11 16 21 ms B VCBDn CELLn balance threshold (n=1,2,3,4,5) Detect rising edge of supply voltage VCBDn -0.025 VCBDn VCBDn +0.025 V C VCBRn CELLn balance released threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VCBRn -0.050 VCBRn Lower of VCBRn +0.050 or VCBDn +0.025 V C VDET2n CELLn Overdischarge threshold (n=1,2,3,4,5) Detect falling edge of supply voltage VDET2n ×0.975 VDET2n VDET2n ×1.025 V D VREL2n CELLn Overdischarge released Voltage (n=1,2,3,4,5) Detect rising edge of supply voltage VREL2n ×0.975 VREL2n VREL2n ×1.025 V D ICT1 CT1 charge Current VDD=VC1, VCELLn=3.5V (n=2, 3, 4, 5), VCELL1=3.5V→1.5V 350 500 650 nA E VDCT1 CT1 detector voltage VDD=VC1, VCELLn=3.5V tVDET2 Output delay of overdischarge tVDET2=CCT1×VDCT1/ICT1 CCT1=330nF 840 1200 1560 ms - tVREL2 Output delay of release from overdischarge VDD=VC1, VCELLn=3.5V VCELL1=1.5V→3.5V 0.7 1.2 1.7 ms G VDET31 Excess discharge-current threshold1 VDD=VC1, VCELLn=3.5V Detect rising edge of supply voltage VDET31 -0.020 VDET31 VDET31 +0.020 V H VDET32 Excess discharge-current Threshold2 VDD=VC1, VCELLn=3.5V Detect rising edge of supply voltage VDET32 -0.055 VDET32 VDET32 +0.055 V I VREL3 Output delay of release from Excess discharge-current threshold VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5), SENSE=0V Detect falling edge of supply voltage VDET31 ×0.50 VDET31 ×0.75 VDET31 ×１.00 V H ICT231 CT2 Charge Current1 VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS→0.4V 350 500 650 nA I ICT232 CT2 Charge Current2 VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENSE=VSS→0.7V 3.5 5 .0 6.5 µA I VDCT2 CT2 Charge voltage VDD=VC1, VCELLn =3.5V (n=2,3,4,5) SENSE=0.4V, VMP=4.0V 1.23 1.55 1.87 V J tVDET31 Output delay of Excess discharge-current threshold1 tVDET31=CCT2×VDCT2/ICT231 CCT2=330nF 700 1000 1 300 ms - tVDET32 Output delay of Excess discharge-current Threshold2 tVDET32=CCT2×VDCT2/ICT232 CCT2=330nF 7 10 13 ms - tVREL3 Output delay of release from Excess discharge-current Threshold VDD=VC1, VCELLn=3.5V (n=1,2,3,4,5) SENS=0.4V, VMP= 4.0V 0.7 1.2 1.7 ms H

NO.EA-263-160711 Symbol Items Conditions Min. Typ. Max. Unit Circuit Vshort Short protection voltage VDD=VC1, VCELLn=3.5V Detect rising of supply voltage Vshort -0.12 VDET32 x1.67 Vshort +0.17 V K tshort Output Delay of Short protection VDD=VC1, VCELLn =3.5V VMP=4.0V 180 300 550 μs K VDET4 Excess charge-current threshold VDD=VC1, VCELLn=3.5V Detect falling edge of supply voltage VDET4 -0.030 VDET4 VDET4 +0.030 V L tVDET4 Output delay of Excess charge-current threshold VDD=VC1, VCELLn =3.5V tVrel4 Output delay of release from Excess charge- current threshold VDD=VC1, VCELLn =3.5V (n=1,2,3,4,5) SENS=VSS,VMP=-1.0V→1.0V 0.7 1.2 1.7 ms L VIH1 SEL1 pin “H” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V M VIM1 SEL1 pin “M” input voltage VDD=VC1, VCELLn =3.2V -0.5V V M VIL1 SEL1 pin “L” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V M VIH2 SEL2 pin “H” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V N VIM2 SEL2 pin “M” input voltage VDD=VC1, VCELLn =3.2V -0.5V V N VIL2 SEL2 pin “L” input voltage VDD=VC, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V N CTLC1H C TLC pin “H1” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD +2.0 V O CTLC2H C TLC pin “H2” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V O CTLC1L C TLC pin “L” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V O CTLD1H C TLD pin “H1” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD +2.0 V P CTLD2H C TLD pin “H2” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VDD -0.3 VDD +0.3 V P CTLD1L C TLD pin “L” input voltage VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) VSS -0.3 VSS +0.3 V P VOL2 D OUT Nch ON voltage IOL=50μA, VDD=VC1, CTLD=VDD VCELLn =3.2V (n=1,2,3,4,5) 0.1 0.5 V Q VOL3 DRAIN Nch ON voltage IOL=50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) 0.1 0.5 V R VOL4 CB1 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC2 +0.2 VC2 +0.5 V S VOL5 CB2 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC3 +0.2 VC3 +0.5 V S VOL6 CB3 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC4 +0.2 VC4 +0.5 V S VOL7 CB4 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) VC5 +0.2 VC5 +0.5 V S VOL8 CB5 Nch ON voltage IOL=50μA, VDD=VC1, VCELLn=3.2V (n=1,2,3,4,5) 0.2 0.5 V S VOH1 C OUT Pch ON voltage IOH=-50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLC=VSS VDD -0.5 VDD -0.1 V T

NO.EA-263-160711 Symbol Items Conditions Min. Typ. Max. Unit Circuit VVR12 VR 12V output voltage(*1) IOH=-5µA, VDD=VC1, CTLD=VSS, VCELL=3.2V (n=1, 2, 3, 4, 5) Measured to draw the current through DOUT 10 12 14 V U VOH2 D OUT Pch ON voltage(*1) IOH=-50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) CTLD= VSS VVR12 -0.5V VVR12 -0.1V V U V OH3 DRAIN Pch ON voltage(*1) IOH=-50μA, VDD=VC1, VCELLn =3.2V (n=1,2,3,4,5) SENS =VMP =4.0V VVR12 -0.5V VVR12 -0.1V V V VOH4 CB1 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=2, 3, 4, 5) VC1 -0.5 VC1 -0.3 V W VOH5 CB2 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 3, 4, 5) VC2 -0.5 VC2 -0.3 V W VOH6 CB3 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 4, 5) VC3 -0.5 VC3 -0.3 V W V OH7 CB4 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 5) VC4 -0.5 VC4 -0.3 V W V OH8 CB5 Pch ON voltage IOH=-50µA, VDD=VC1, VC1=4.5V, VCELLn=3.2V (n=1, 2, 3, 4) VC5 -0.5 VC5 -0.3 V W I LCOUT C OUT pin off leak current VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) CTLC=VDD, COUT=-14V -0.1 µA X I CTLT C TLT Charge Current VDD=VC1, VCELLn=3.2V (n=1, 2, 3, 4, 5) 145 205 264 nA Y V DTLT C TLT detector threshold VDD=VC1, VCELLn=3.2V (n=1, 2, 4, 5) VC3=VD1+0.2V 1.58 2.00 2.42 V Z V RTLT C TLT released voltage VDD=VC1, VCELLn=3.2V tLT Disconnection detection Test Interval CCTLT×(VDTLT-VRTLT)/ICTLT CCTLT =3.3µF 21 30 39 s - I SS1 Supply Currnt1 VDD=VC1,COUT=OPEN VCELLn=VDET1n-0.4V (n=1, 2, 3, 4, 5) 12 30 µA a I SS2 Supply Currnt2 VDD=VC1,COUT=OPEN VCELLn=1.5V (n=1, 2, 3, 4, 5) 10 25 µA a ∗ VCELLn=CELLn voltage n=1, 2, 3, 4, 5 (*1) If VDD pin voltage becomes lower than the output of the regulator, the output voltage becomes almost equal to VDD.

NO.EA-263-160711 OPERATION

VDET1n / Overcharge Detectors (n=1, 2, 3, 4, 5) While the cell is charged, the voltage between VC1 pin and VC2 pin (voltage of the Cell-1), the voltage between VC2 pin and VC3 pin (voltage of the Cell-2), the voltage between VC3 pin and VC4 pin (voltage of the Cell-3), the voltage of VC4 pin and VC5 pin (voltage of Cell-4), and the voltage between V C5 pin and VSS pin (voltage of the Cell -5) are supervised. If at least one of the cells’ voltage becomes equal or more than the over charge detector threshold, the overcharge is detected, and C OUT pin connected to an external pull down resistance outputs "Hi -Z", and by turning off the external N-channel MOSFET by the pull- down resister, charge cycle stops. BA/BB/BC ver.: To reset the overcharge and make the C OUT pin level to "H" again after detecting over charge, in such condition that a time when all the cells’ voltages become lower than the overcharge released voltage. Then, the output voltage of COUT pin becomes "H", and it makes an external N-channel MOSFET turn on, and charge cycle is available. The over charge detectors have hysteresis. AD/BD ver.: To reset the overcharge, when all the cell voltage become lower than the released voltage from overcharge, COUT pin becomes “H”, charge is acceptable. After detecting overcharge, by connecting a load, and when all the cell voltage becomes lower than the overcharge voltage detector threshold, COUT voltage becomes “H” and charge will be possible. Internal fixed output delay times for overcharge detection and release from overcharge exist. Even if one of cells' voltage keeps its level more than the overcharge detector threshold, and the output delay time passes, overcharge voltage is detected. Even if the voltage of each cell becomes equal or higher than VDET1 if these voltages would be back to be lower than the overcharge detector threshold within the output delay time, the overcharge is not detected. Besides, after detecting overcharge, each cell voltage is lower than the overcharge detector released voltage, even if just one of cells' voltage becomes equal or more than the overcharge released voltage within the released output delay time, overcharge is not released. The output type of the COUT pin is P-channel open drain and "H" level of COUT pin is VDD pin voltage.
VDET2n / Overdischarge Detectors (n=1, 2, 3, 4, 5) While the cells are discharged, the voltage between V C1 pin and VC2 pin (the voltage of Cell-1), the voltage between VC2 pin and VC3 pin (Cell-2 voltage), the voltage between V C3 pin and VC4 pin (Cell-3 voltage), the voltage between VC4 pin and V C5 pin (Cell-4 voltage), and the voltage between VC5 pin and Vss pin (Cell-5 voltage) are supervised. If at least one of the cells’ voltage becomes equal or less than the overdischarge detector threshold, the overdischarge is detected and discharge stops by the external discharge control N-channel MOSFET turning off with the DOUT pin being at "L". The condition to release over discharge voltage detector is that after detecting overdischarge voltage, all the cells' voltage becomes higher than the overdischarge released voltage, DOUT pin becomes “H” level, and by turning on the external N-channel MOSFET, discharge becomes possible. The over discharge detectors have hysteresis. The output delay time for over discharge detect is set with an external capacitor C CT1 connected to CT1 pin. If at least one of the cells' voltage becomes down to equal or lower than the overdischarge detector threshold, and the voltage of each cell would be back to higher than the over discharge detector threshold within the output delay time, the overdischarge is not detected. The output delay time for release from overdischarge is also set internally. After detecting over discharge, supply current would be reduced and be into standby by halting unnecessary circuits and consumption current of the IC itself is made as small as possible. When a cell voltage equals to zero, if the voltage of each cell is lower than the charge inhibit maximum voltage, charge is not acceptable. All the cell voltages are higher than the charge inhibit maximum voltage, COUT pin becomes "H" and the IC allows the system to charge. The output type of DOUT pin is CMOS having "H" level around 12V of the internal regulator and "L" level of VSS.

NO.EA-263-160711

VDET3-n (n=1, 2) /Excess discharge-current Detector, Short Circuit Protector When the charge and discharge is acceptable, SENS pin voltage is supervised, if the load is short and SENS pin voltage becomes equal or more than excess discharge current threshold, and equal or less than the short detector threshold, the status becomes excess discharge current detected condition. If SENS pin voltage becomes equal or more than the short circuit detector threshold, the status becomes short circuit detected, then DOUT pin outputs "L" and by turning off the external MOSFET, the IC prevents the circuit from flowing large current. The excess discharge current detector has two thresholds, and each threshold has the output delay time. In terms of the output delay times, the delay time for the excess discharge current detector 2 is set shorter than the excess discharge current 1. The output delay times for the excess discharge-current detectors are set by an external capacitor C CT2 connected to CT2 pin. A quick recovery of SENS pin level from a value between the excess discharge current detector and the short circuit detector threshold within the delay time, may keep the status as before excess discharge current detected. Output delay time for the release from excess discharge-current detection is also set internally. When the short circuit protector is enabled, the delay time exists as well as other protection circuits. Between the drain of the external FET connected to DRAIN pin, and the drain of an external FET connected to C OUT and DOUT, an external resistor should be mounted to release from overdischarge. After an excess discharge-current or short circuit protection is detected, an external FET connected to DRAIN pin turns on and the resistance of release from the excess-discharge current is connected to V SS. After detecting the excess discharge current or short circuit, load is removed and opened, VMP pin level is connected to the VSS pin level, through the pulled down resistor for release from excess discharge, and when the VMP pin becomes equal or less than VREL3, the circuit is released from excess discharge or short automatically. When the excess -discharge current is released, the external FET connected to DRAIN pin turns off and resisters for the release from excess-discharge current status is separated from VSS.
VDET4/ Excess charge-current detector When the battery pack is chargeable and discharge is also possible, V DET4 senses SENS pin voltage. For example, in case that a battery pack is charged by an inappropriate charger, excess current flows, then the voltage of SENS pin becomes equal or less than the excess charge-current detector threshold, then the output of C OUT pin becomes "Hi-Z", and by turning off the external N-channel MOSFET with the pull-down resister, flowing excess current in the circuit is prevented. Output delay of the excess charge current is internally fixed. Even the voltage level of SENS pin becomes equal or lower than the excess charge-current detector threshold, if the voltage becomes higher than the excess charge current threshold within the delay time, the excess charge current is not detected. Output delay for the release from excess charge current exists as well as other protection circuits. V DET4 can be released by disconnecting a charger and connecting a load and when the VMP pin voltage becomes equal or more than VREL3.
Operation against cell unbalance If one of the cells detects overcharge and either of the cells detects overdischarge, both outputs of COUT and DOUT become "L".
CTLC/CTLD pin If the ICs are stacked and function with two chips, by connecting C OUT and CTLC, and connecting DOUT and CTLD shown as in the example circuit (10-cell protection), overcharge, overdischarge, open-wire state can be transferred. If stacked connection is unnecessary, CTLC/CTLD pins must be set at VSS voltage level. If CTLC/CTLD pins are in the range of VSS ± 0.3V, or larger than VDD+2.0V, the IC operates in normal way. By forcing VDD voltage level (between V DD-0.3V and VDD+0.3V) to CTLC pin, the output of C OUT connected an external pull - down resister can be forcibly set to "L". However, if short circuit is detected, the output of COUT cannot be made "L". By forcing VDD voltage level (between VDD-1.0V and VDD+3.0V) to CTLD pin, the output of DOUT can be forcibly set to "L".

NO.EA-263-160711 If the voltage in the range from Vss+0.3V to VDD-0.3V is forced to the CTLC/CTLD pin, the operation may change by the voltage between VDD and VSS. The voltage in the range from VSS + 0.3V to VDD-0.3V should not be forced to CTLC/CTLD continuously. CTL pin input and outputs of COUT and DOUT CTLC/CTLD pin input COUT/DOUT external FET equal or more than VDD+2.0 Normal Operation VDD-0.3V to VDD+0.3V Forced off VSS-0.3 to VSS+0.3 Normal Operation Open, other than the above Indefinite

SEL1, SEL2 pin SEL1 and SEL2 pins are used as switch over 3-cell protector, 4-cell protector and 5-cell protector. If 4-cell protection is selected, by forcing VSS voltage level to SEL1 pin and forcing VDD voltage level to SEL2 pin, the operation of 5th cell's protection circuit, the signal is shut down, therefore, even if the VC5 is shortened to GND, overdischarge is not detected and operates as a 4-cell protector IC. To select 3-cell protection mode, by forcing VDD voltage level to SEL1 pin, VSS voltage level to SEL2 pin, the operation of 5th cell and 4th cell stop, and the signal is cut off. Therefore, if V C4, VC5 and VSS are shorted, overdischarge is not detected and operates as a 3-cell protector IC. SELn pins must be set as VDD voltage or VSS voltage level. Depending on the combination of SEL1 pin and SEL2 pin input, delay time shortening function mode 1 (down to 1/100 delay) or delay time shortening function mode 2 (overcharge detector threshold delay time is shortened into 4ms) is realized. Middle voltage of the table below means in the range from 4.0V to V DD/2-0.5V. SEL1 and SEL2 pin input combination, and the operation mode SEL1 pin input SEL2 pin input Operation Mode High High 5-cell protector Low High 4-cell protector High Low 3-cell protector Low Low Delay shortening mode 1 for 5-cell protector Low Middle Delay shortening mode 1 for 4-cell protector Middle Low Delay shortening mode 1 for 3-cell protector Middle Middle Delay shortening mode 2 for 5-cell protector Middle High Delay shortening mode 2 for 4-cell protector High Middle Delay shortening mode 2 for 3-cell protector
CT1, CT2 pin CT1 and CT2 pins are used for setting the output delay time of overdischarge (tVDET2), the excess discharge current 1 (tVDET31), and the excess discharge current 2 (tVDET32) by connecting external capacitors CCT1 and CCT2. tVDET2 can be set with CT1 pin. tVDET31 and tVDET32 can be set with CT2 pin. (1) tVDET2 external capacitor CCT1 setting tVDET2 can be set as in the next formula. Delay time code : A tVDET2(msec) = 3.64 × CCT1(nF) Delay time code : B tVDET2(msec) = 3.88 × CCT1(nF)

NO.EA-263-160711 (2) tVDET31 and tVDET32 external capacitor CCT2 setting tVDET31 and tVDET32 can be set as in the next formulas. Delay time code : A tVDET31(msec) = 3.05 × CCT2(nF) tVDET32(msec) = tVDET31/100 Delay time code : B tVDET31(msec) = 3.26 × CCT2(nF) tVDET32(msec) = tVDET31/6

Cell balance function CB circuit-n (n=1,2,3,4,5) While a battery is being charged, and the cell voltage is beyond the cell balance voltage VCBDn (n=1,2,3,4,5) , against the cell which becomes equal or more than the cell balance voltage VCBDn, the output of CBn pin (n=1,2,3,4,5) becomes "H" and an external N-channel transistor for cell balance turns on, and discharge path is connected in parallel with the cell and charge current is reduced. When the cell voltage becomes equal or less than the cell balance released voltage VCBRn (n=1,2,3,4,5), then cell balance function is released and the output of CBn pin (n=1,2,3,4,5) becomes "L". The resister used for the discharge path, absolute ratings must be cared. If the cell balance function is unnecessary, CBn pin must be left open. Open-wire Detector Function Open-wire detect of VDD (VC1) and VSS for 5-cell protector If VDD line is cut, the voltage between VC1 and VC2 is less than 0V. If VSS line is cut, the voltage between VC5 and VSS is less than 0V. The voltage is detected by the 0V -detector circuit. If open-wire is detected, the P-channel open drain of the COUT turns off.
Open-wire detector for VC2, VC3, VC4, VC5 for 5-cell protection When using the 5-cell protection, the voltage of VDD (= VC1) becomes lower than VC2 voltage if the connection between the battery and VDD (= VC1) is open. And, the voltage of VSS becomes higher than VC5 voltage if the connection between the battery and VSS is open. The voltage variation is detected as “Open -wire”. When the open-wire is detected, the P -channel open drain of the COUT turns off. In case of the 3.3µF capacitor is attached to the CTLT pin, open-wire detector operates every 30 seconds. The built in switch of VC1, VC3, VC5 cell, and the switch attached to the VC2 and VC4 turn on alternatively by the even_sw and the odd_sw signal. The internal impedance of the cell whose switch turns on becomes low for about 1.2 seconds by the low resistance connected to the switch. If the wire is not broken, the capacitor of the CTLT is discharged and the next cycle starts for checking. While the wire is broken, the difference of the internal impedance of the IC generated by the switch's tuning on makes VC shift and detected by the comparator for V DET1. If the open-wire is detected and the condition continues for about 4ms, then even_sw and odd_sw turn off and the capacitor of CTLT is discharged and the P -channel open drain of the C OUT turns off. While the overdischarge voltage is detected, the open-wire of VC2, VC3, VC4 and VC5 does not operate.
Open-wire detector for VDD (VC1) and VSS for 10-cell protection If the ICs are connected in cascade, the V DD of the high side IC and V SS (VSS2) of the low side IC, the open-wire detector is able to work as well as 5-cell protection type. As for the VSS (VSS1) of high side IC and VDD (VDD2) of low side IC, if they are connected with common one wire from the battery, and if the wire is broken, two lines, V SS1 and VDD2's wire are broken, as a result, open-wire may not be able to be detected correctly. As for the V SS1 and VDD2, connect with two wires so that either V SS1 or VDD2 is connected to the battery, and by the pull-down

NO.EA-263-160711 resistance of COUT of high side is connected to the VDD2 of the low side IC, if either of VSS1 or VDD2 breaks the wire, the open- wire detector is able to operate. Refer to the typical application circuit. (10-cell, cell-balance, open-wire detector are in use.) *Limitation of the open-wire detector for VC2, VC3, VC4, VC5. If the open-wire detecting function is necessary, confirm the limitations below; External components must be CCTLT=3.3µF CCT1 range: from 0.47µF to 1.0µF CVCx=0.1µF Even if the protection IC does not detect overdischarge, if the cell voltage is low, depending on the distribution of the ICs, cell balance state, the operating environment, the characteristics of the external components, open-wire function may not operate correctly. During the delay time of the overcharge voltage, if the open-wire is detected, the overcharge detect operation is once cancelled, and the open-wire operation will be dominant. During the open-wire detection, even if the cell voltage becomes equal or more than the overcharge detector threshold, overcharge is not detected. In this case, after detecting open-wire operation, if the cell voltage is still equal or more than the overcharge detector threshold, overcharge detector operation starts again. For this reason, overcharge detector output delay time may longer than 1s. (Refer to the timing chart.) During the overdischarge delay time, if the open-wire detector's operation starts, the overdischarge detector's operation is once cancelled and the open-wire operation will be dominant. During the open-wire, detector's operation is active, even if the cell voltage becomes equal or less than the overdischarge detector threshold, the overdischarge detector does not start. In this case, after detecting open-wire operation, if the cell voltage is still equal or less than the overdischarge detector threshold, overdischarge detector operation starts again. For this reason, the output delay time of overdischarge detector may be longer than the preset value. (Refer to the timing chart.) Charge Inhibit Detector Circuit Vnochg-n (n-1,2,3,4,5) In the R5432VxxxBB, for each cell, charge inhibit detector is built-in. If either of cells’ voltage is lower than the charge inhibit voltage, when a charger is connected to the battery pack, charge inhibit is detected and COUT with external pull-down becomes “Hi-Z” and an external MOSFET turns off by the pull-down resistance and charge stops. When the charge inhibit is detected, the cell voltage which is inhibit charge is equal or lower than the overdischarge detector threshold, therefore the output of COUT becomes “Hi-Z”, and the output of DOUT becomes “L”, and both external FETs turn off.

NO.EA-263-160711 TIMING CHART

Overcharge, Excess charge current VDET11 VREL11 VC1-VC2 t tVREL1 tVDET1 tVDET1 tVREL1 tVDET4 VDD VMP COUT tVREL4 t VDET12 VREL12 VC2-VC3 t VDET13 VREL13 VC3-VC4 t VDET14 VREL14 VC4-VC5 t Charge/ Discharge current t charge discharge connect charger connect load connect charger charger open & connect load VSS SENS VDET31 VDET4 t VDET14 VREL14 VC5-Vss t VSS VMP VDET31 VDET4 t openconnect chargerconnect load

NO.EA-263-160711

Overdischarge, Excess discharge current1/2, Short detector VR12V DOUT VSS tVDET21 tVDET21 tVREL21 tVDET31 tshorttVDET32 tVREL3tVREL21 tVREL3 tVREL3 t VREL21 VDET21 VC1-VC2 t t VREL22 VDET22 VC2-VC3 t VREL23 VDET23 VC3-VC4 t VREL24 VDET24 VC4-VC5 t VREL24 VDET24 VC5-Vss t connect charger connect load open open open connect load connect load connect load connect charger connect load open VSS VDET4 SENS VDET3-1 VDET3-2 Vshort t VSS VMP t Charge/ Discharge current charge discharge

NO.EA-263-160711 CELL BALANCE OPERATION In the case that CELL1 operates CELL balance VDET11 VREL11 ・V C1-VC2 t・CB1-VC2 (Voltage difference) t VDD ・COUT ・Charge/ Discharge current t Charge current Discharge current charge current bypass current charge current - bypass current CBREL1 CBDET1 discharge current + bypass current idle tVDET1 discharge current Cell balance operation Over charge state t

NO.EA-263-160711 Balance operation with CELL1 and CELL2 VDET1x VREL1x Cellx voltage t CBx output t VDD COUT output Charge/ Discharge current t Charge current Discharge current charger CBRELx CBDETx idle tVDET1 Over charge state charger - bypass charger - bypass idlebypass bypass charger Cell1 Cell2 CB1 operating CB2 operating Cell1 Cell2 t

NO.EA-263-160711

Open-wire Detection Open-wire detector's operation of VC2, VC3, VC4, and VC5 for 5-cell protector In case of the 3.3 µF capacitor is attached to the CTLT pin, open- wire detection operates every 30 seconds. The built in switch of V C1, VC3, VC5 cell, and the switch attached to the V C2 and VC4 turn on alternatively by the even_sw and the odd_sw signal. The internal impedance of the cell whose switch turns on becomes low for about 1.2 seconds by the low resistance connected to the switch in serial. If the wire is not open, the capacitor of the CTLT is discharged and the next cycle starts for checking. While the wire is open, the difference of the internal impedance of the IC generated by the switch's tuning on makes V C shift and detected by the comparator for VDET1 . If the open- wire is detected and the condition continues for about 4ms, then even_sw and odd_sw turn off and the capacitor of CTLT is discharged and the P - channel open drain of the C OUT turns off. While the overdischarge voltage is detected, the open-wire of V C2, VC3, VC4 and VC5 does not operate. The timing chart of open-wire of VC2, VC3, VC4, VC5 is shown below: ∗1) The change of V C is not always increasing. Depending on the cell balance or the internal impedance, the V C increases or decreases. CTLT Pin COUT Output (VC3 at open-wire） 1.2seconds (CTLT = 3.3µF) At VC3 at Open-wire VC3 Voltage odd_sw (IC Internal signal) even_sw (IC Internal signal） Open-wire VDET1detection level 30seconds (CTLT = 3.3µF) ∗1) VC3, VC5 open-wire VC2, VC4 open-wire VC3, VC5 open-wire

NO.EA-263-160711

Overcharge detector operation and Open-wire detector operation The output delay time of overcharge is normally set at 1s, however, the effect of the open-wire detector, the output delay time may be longer than 1s. Case 1: During the operation of detecting overcharge, if th e open-wire is detected, once the operation of the overcharge detector is cancelled, and after detecting the open-wire, the operation of the overcharge detector starts again. Case 2: During the operation of the open-wire detector, if the cell voltage becomes more than the overcharge detector threshold, after detecting the open-wire, the operation of the overcharge detector starts. The timing chart shown below is for the operation of the case 1. When the overcharge is detected, internal node "vd1" becomes "H", then, if the open-wire is detected, the internal node "It_en" becomes "H", then "vd1" signal returns to "L". After the open- wire detector is released, then "It_en" returns to "L", then the "vd1" becomes "H", and overcharge detector's function restar. Open-wire test operation starts, overcharge detector's operation is cancelled. Overcharge detector's maximum output delay : Max_tVDET1 = B＋C＋tVDET1. COUT vd1 (internal signal) lt_en (internal signal) VCELLn CTLT tVDET1 B≤tVDET1 Check Open-wire tLT t t t t t H L B C VDET1n A (n=1,2,3,4, 5)

NO.EA-263-160711

Overdischarge operation and disconnection detector operation The output delay time of the overcharge detector can be set by an external capacitor, but the delay time might be longer than the present value due to the open-wire detector's operation. 1. During the operation of detecting over discharge, if the open-wire is detected, once the operation of the over discharge detector is cancelled, and after detecting the open-wire is detected, once the operation of the 2. Overdischarge can not be detected during disconnection detection. It can operate after disconnection detect. The timing chart which start to detect disconnect during overdischarge is displayed as follows. The internal signal "vd1" become "H" after it is equal or less than overdischarge threshold. It comes back "L" after which is the detecting disconnection internal s ignal become "H". "vd1" become "H" after "It_en" comes back "L". . Overdischarge can be detected. Check Open-wire VDET2n DOUT vd2 (internal signal) lt_en (internal signal) VCELLn (n=1, 2, 3, 4, 5) CTLT tVDET2 B≤tVDET2 tLT t t t t t H L B C A Overcharge detecting is cancelled, after operating disconnection test. So max output of overcharge delay : Max_tVDET2 = B＋C＋tVDET2

NO.EA-263-160711 TYPICAL APPLICATION AND TECHNICAL NOTES (R5432VxxxBA)

Circuit example (for -5cell protection, detecting disconnection, at operating cell-balance function) When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack -, the discharge current flows through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between Pack+ and Pack -, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those current enough. CVC1 Protect IC VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 Cell4 Cell5 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD VSS VSS CT1 CT2 CTLT RVC1 RVC2 RVC3 RVC4 RVC5 RCB1 RCB2 RCB3 RCB4 RCB5 CVC2 CVC3 CVC4 CVC5 CVDD RVDD CCT1 CCT2 CCTLT RSENS RDRAIN RCO1 RCO2 RVMP RSE ZD1

NO.EA-263-160711

Circuit example (for 4cell protection, detecting disconnection, at not operating cell-balance function) When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack -, the discharge current flows through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between Pack+ and Pack -, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those current enough. Protect IC VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 Cell4 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD VSS VSS CT1 CT2 VSS CTLT CVC1 RVC1 RVC2 RVC3 RVC4 RCB1 RCB2 RCB3 RCB4 CVC2 CVC3 CVC4 CVDD RVDD RSENS RDRAIN RCO1 RVMP RSE RCO2 CCT1 CCT2 ZD1

NO.EA-263-160711

Circuit example (for 3cell, detecting disconnection, at not operating cell-balance function) When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack -, the discharge current flows through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between Pack+ and Pack -, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those current enough. Protect IC VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD VSS VSS CT1 CT2 VSS CTLT CVC1 RVC1 RVC2 RVC3 CVC2 CVC3 CVDD RVDD CCT1 CCT2 CCTLT RSENS RDRAIN RCO1 RCO2 RVMP RSE ZD1

NO.EA-263-160711

Circuit example (for 7cell, detecting disconnection, at operating cell-balance function) If the open-wire detector is used, for Vss of the high side IC or VDD of the low side IC, these two lines must be separated. If they are common, the both pins' open-wire cannot be detected. Refer to the operation explanation. When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack -, the discharge current flows through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between Pack+ and Pack-, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those current enough. Protect IC VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 Protect IC VC1 VC2 VDD Cell4 CB1 Cell5 Cell6 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT CTLT CVC1 RVC1 RVC2 RVC3 RVC4 RCB1 RCB2 RCB3 CVC2 CVC3 CVDD1 RVDD1 CCT11 CCTLT1 CVC6 RVC6 RVC7 RVC8 RCB6 RCB7 RCB8 CVC7 CVC8 CVDD2 RVDD2 CCT12 CCTLT2CCT22 RSENS RDRAIN RCO1 RCO2 RVMP RSE RCTLD RCTLC RUCO ZD1 ZD2 VSS VSS Cell7 RCB9 CVC9 RVC9

NO.EA-263-160711 Circuit example (for 10cell, detecting open-wire, with cell-balance function) If the open-wire detector is used, for Vss of the high side IC or VDD of the low side IC, these two lines must be separated. If they are common, the both pins' open-wire cannot be detected. Refer to the operation explanation. When the FET connected to Cout is OFF and the load is connected between Pack+ and Pack -, the discharge current flows through the parasitic diode of that FET, and when the FET connected to Dout is OFF and the charger is connected between Pack+ and Pack -, the charge current flows through the parasitic diode of that FET. Choose the FETs which can flow those current enough. Protect IC VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 Cell4 Cell5 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 Protect IC VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 Cell4 Cell5 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT CTLT CVC1 RVC1 RVC2 RVC3 RVC4 RVC5 RCB1 RCB2 RCB3 RCB4 RCB5 CVC2 CVC3 CVC4 CVC5 CVDD1 RVDD1 CCT11 CCTLT1 CVC6 RVC6 RVC7 RVC8 RVC9 RVC10 RCB6 RCB7 RCB8 RCB9 RCB10 CVC7 CVC8 CVC9 CVC10 CVDD2 RVDD2 CCT12 CCTLT2CCT22 RSENS RDRAIN RCO1 RCO2 RVMP RSE RCTLD RCTLC RUCO ZD1 ZD2

NO.EA-263-160711

Circuit example (for 10-cell protection with cell-balance, open-wire, overcharge hysteresis cancellation: AD/BD ver.) If the open-wire detector is used, for Vss of the high side IC or VDD of the low side IC, these two lines must be separated. If they are common, the both pins' open-wire cannot be detected. Refer to the operation explanation. Protect IC Protect IC CCT22 VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 Cell4 Cell5 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 Cell4 Cell5 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT CTLT CVC1 RVC1 RVC2 RVC3 RVC4 RVC5 RCB1 RCB2 RCB3 RCB4 RCB5 CVC2 CVC3 CVC4 CVC5 CVDD1 RVDD1 CCT11 CCTLT1 CVC6 RVC6 RVC7 RVC8 RVC9 RVC10 RCB6 RCB7 RCB8 RCB9 RCB10 CVC7 CVC8 CVC9 CVC10 CVDD2 RVDD2 CCT12 CCTLT2 RSENS RDRAIN RCO1 RCO2 RVMP RSE RCTLD RCTLC RUCO ZD1 ZD2 ROP1 ROP２ ROP３ ROP５ ROP４ ROP７ ROP６ ROP８ QOP1 MOP1 MOP２ MOP３ MOP４

NO.EA-263-160711

External parts ratings Symbol Typ. Unit Range Remarks RVDD 330 Ω 330 to 1000 ∗1 RVC1 330 Ω 330 to 1000 ∗2 RVC2 330 Ω 330 to 1000 ∗2 RVC3 330 Ω 330 to 1000 ∗2 RVC4 330 Ω 330 to 1000 ∗2 RVC5 330 Ω 330 to 1000 ∗2 RCB1 100 Ω 40 or more ∗3 RCB2 100 Ω 40 or more ∗3 RCB3 100 Ω 40 or more ∗3 RCB4 100 Ω 40 or more ∗3 RCB5 100 Ω 40 or more ∗3 RSENS 100 mΩ 1.0 or more It is determined by the value of over current RSE 10 kΩ 1 to 10 ∗4 RDRAIN ∗5 MΩ ∗5 ∗5 RDRAIN<VDET31x(RCO1+RCO2)/50 RCO1 1 MΩ ∗5 ∗5 RCO2 2 MΩ ∗5 ∗5 RVMP 10 MΩ 0.01 to 10 ∗6 RCTLC 1 kΩ 1 to 10 RCTLD 1 kΩ 1 to 10 RUCO 3 MΩ 0.1 to 10 ∗7 CVDD 1 µF 0.1 to 1 ∗1 CVC1 0.1 µF 0.1 ∗2 CVC2 0.1 µF 0.1 ∗2 CVC3 0.1 µF 0.1 ∗2 CVC4 0.1 µF 0.1 ∗2 CVC5 0.1 µF 0.1 ∗2 CCT1 0.47 µF 0.01 to 1.0 ∗8 CCT2 0.0033 µF 0.0022 or more ∗9 CCTLT 3.3 µF 3.3 ∗10 ZD1 30 V 30 or less ∗11 ROP1 10 kΩ 10 or more Input resistance of QOP1 ROP2 10 MΩ 5 or more ROP3 10 MΩ 5 or more ROP4 10 MΩ 5 or more ROP5 10 MΩ 5 or more ROP6 20 MΩ 10 or more ROP7 10 MΩ 5 or more MOP1 Consider the Voltage rating of VGS and VDS MOP2 Consider the Voltage rating of VGS and VDS MOP3 Consider the Voltage rating of VGS and VDS MOP4 Consider the Voltage rating of VGS and VDS QOP1 Consider the Voltage rating of VGS and VDS Please refer to the external circuits of next page for "∗" of remarks Please confirm "Precautions before Use".

NO.EA-263-160711 Technical Notes on External Circuits and Components *1) The voltage fluctuation is stabilized with RVDD and CVDD. If a small RVDD is set, in the case of the large transient may happen to the cell voltage, by the flowing current, the IC may be unstable. If a large R VDD is set, by the consumption current of the IC itself, the voltage difference between V DD pin and VC1 pin is generated, and unexpected operation may result. Therefore, the appropriate value range of RVDD is from 330Ω to 1kΩ. To make a stable operation of the IC, the appropriate value range of CVDD is from 0.1µF to 1.0µF. *2) RVC1 to RVC10, CVC1 to CVC10 stabilize the voltage fluctuation. If large RVC1 to RVC10 is set, the detector threshold will be high because of the internal conduction current of the IC. The operation error of open-wire detector function may happen easily by the distribution of the ICs or environment. If small RVC1 to RVC10 is set, the effect by noise will be large. Therefore the appropriate value range of RVC1 to RVC10 is from 330Ω to 1kΩ. To make stable operation, use 0.1µF as CVC1 to CVC10. *3) When the cell balance function is necessary, RCB1 to RCB10 must be chosen carefully with considering the bypass current, and consumption power by the bypass current, and the external MOSFET. Especially, if a small resistance (to set the large bypass current) is set, fully evaluation is necessary. If a large resistance (to set the small bypass current) is set, the time for cell balance will be long. *4) When the cascade connection is used, if short circuit is happened, by the short current and the R SENS enlarges the voltage, and as a result, if the voltage of SENS pin becomes larger than the VDD of the IC, during the short circuit output delay time, the current flows into SENS pin. Therefore, if a small R SE is set, a large current may flow into SENS pin. If a large RSE is set, the overcurrent detector threshold may shift. Therefore the appropriate value is around 10kΩ. *5) Choose appropriate values for R DRAIN, RCO1, and R CO2 to satisfy the next formula, otherwise, the release from excess discharge current and short may be impossible. R DRAIN<VDET31x(RCO1+RCO2)/50 If small RCO1 or RCO2 is set, when the output of C OUT is "H", the consumption current of protection circuit board increases. If large RCO1 or RCO2 is set, when the output of COUT is "Hi-Z", the speed for pull-down the gate of the charge FET becomes slow and turning off the FET will be slow. Not only that, by dividing between the "Hi -Z" output and the resistance, turning off the charge FET may be difficult. If a small R DRAIN is set, when the excess discharge current and short circuit is detected, the large current may flow until the load is removed. *6) In terms of R VMP, when the cascade connection is made, if D OUT turns off, VMP pin is pulled up via RVMP to the top cell. In this case, the current flows via R VMP and the internal diode, therefore, appropriate value must be chosen. If the cascade connection is not used, around 10kΩ is acceptable. *7) Set R UCO to satisfy RUCO=RCO1+RCO2. If a extremely large resistance is set, when the output of COUT is "Hi-Z", by the dividing resistance, CTLC pin may not be pulled down. If a small resistance is used, when the output of C OUT is "H", the consumption current via RUCO increases. *8) If the open-wire detector function of V C2 to VC5 is used, use 0.47µ F to 1µF as C CT1. If the open-wire detector function is unnecessary, use a capacitor of 0.01µF or more. *9) If a too small C CT2 is set, excess discharge current detector output delay time 2 becomes shorter than the short circuit output delay time. Therefore, use a capacitor with 0.0022µF or more.

NO.EA-263-160711 *10) If the open-wire detector of VC2 to VC5 is used, use 3.3µF as CCTLT. If the open-wire detector of VC2 to VC5 is not necessary, pull down to VSS. *11) Considering the break down of the resistors and capacitors to stabilize the fluctuation of the voltage, to avoid that the high voltage is directly forced to the IC, adding a zener diode is our recommendation. Connect the zener diode between VDD pin of the IC and VSS pin directly. (Refer to the typical application circuits.) To set the number of connecting cells, SEL1/SEL2 pin must be connected to VDD level. In these cases, connect the pin inside the filter for stabilizing V DD pin voltage. If SEL1/SEL2 is connected outside the filter, during the operation, the voltage difference between SEL1/SEL2 and VDD may be generated, and unstable operation or excess current flow may result. The typical application circuit diagrams ar e just examples. This c ircuit performance largely depends on the PCB l ayout and external components. In the actual application, fully evaluation is nec essary. Overvoltage and the over current beyond the absolute maximum rating should not be forced to the protection IC and external components. Especially, if the pack+ and Pack- are short, although the short protection circuit is built-in the IC, but during the output delay time, large current may flow through the FE T. By the current during the output delay, in order not to destruct the FET, choose the FET with enough current rating. Our company cannot as sume responsibility for use of any circuitry other than circuitry entirely embodied in our product s. If technical notes are not complied with the circuit which is used our product s, we are not responsible for any damages and any accidents. To connect the protection IC and cells, connect VSS pin first. If the connect order is wrong, by flowing unexpected current, the IC m ay be damaged. If charge control FET and discharge control FET are connected in serial, if the control FET for charge turns off and discharge big current, or when the FET for discharge turns off and if charge with big current is done without discharge control FET tur ning off, big current flows through the parasitic diode of the FET, the FET may be burnt. To avoid this, separate the charge and discharge current path and when the FET turns off, in order not to flow large current through parasitic diode, choose an FET with large current capac ity.

NO.EA-263-160711 TEST CIRCUITS A VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V V V V V B VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT Cout C VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V V V V V D VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V V V V V OSCILLOSCOPE

NO.EA-263-160711 E VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT A F VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V G VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT H VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V V

NO.EA-263-160711 I VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT VA K VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V L VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V J VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V

NO.EA-263-160711 O VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V M VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT P VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V V N VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V

NO.EA-263-160711 Q VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V S VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLTV T VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V R VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V V V V V V

NO.EA-263-160711 U VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V V VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT V W VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLTV X VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT A V V V V V

NO.EA-263-160711 Y VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT Cout A Z VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT Cout V VC1 VC2 VDD CB1 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC DRAIN SEL1 SEL2 CTLD CT1 CT2 CTLT A a A

NO.EA-263-160711 TYPICAL CHRACTERSTICS Part1. Temperature Characteristics 1) Overcharge voltage threshold (CELLn) 2) Overcharge Released Voltage (CELLn) 3) Overcharge Detector Delay 4) Released from Overcharged Delay time Temperature 5) CELL balance detector (CELLn) threshold 6) CELL balance released Voltage (CELLn) R5432V404BA 4.22 4.23 4.24 4.25 4.26 4.27 4.28 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VDET1n(V) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA 4.07 4.08 4.09 4.10 4.11 4.12 4.13 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VREL1n(V) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA 0.4 0.6 0.8 1.0 1.2 1.4 1.6 -60 -40 -20 0 20 40 60 80 100 Ta (°C) tVDET1(sec) VCELLn=3.2V, VCELL1=3.2V->4.5V n=2, 3, 4, 5 R5432V404BA -60 -40 -20 0 20 40 60 80 100 Ta (°C) tVREL1(msec) VCELLn=3.2V, VCELL1=4.5V->3.2V n=2, 3, 4, 5 R5432V404BA 4.17 4.18 4.19 4.20 4.21 4.22 4.23 -60 -40 -20 0 20 40 60 80 100 Ta (°C) CBDETn(V) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA 4.17 4.18 4.19 4.20 4.21 4.22 4.23 -60 -40 -20 0 20 40 60 80 100 Ta (°C) CBRELn(V) VCELLn=3.2V n=1, 2, 3, 4, 5

NO.EA-263-160711 7) Overdischarge Detector Threshold (CELLn) 8) Released Voltage from overdischarge (CELLn) 9) Output Delay time of Overdischarge (CELLn) 10) Output Delay Time of Released from Overdischarge (CELLn) 11) Excess Discharge Current Detector Thershold1 12) Excess Discharge Current Detector Thershold2 R5432V404BA 2.47 2.48 2.49 2.50 2.51 2.52 2.53 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VDET2n(V) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA 2.97 2.98 2.99 3.00 3.01 3.02 3.03 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VREL2n(V) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA 100 120 140 160 180 -60 -40 -20 0 20 40 60 80 100 Ta (°C) tVDET2(msec) VCELLn=3.2V, VCELL1=3.2V->1.5V, C1=33nF n=2, 3, 4, 5 R5432V404BA 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -60 -40 -20 0 20 40 60 80 100 Ta (°C) tVREL2(msec) VCELLn=3.2V, VCELL1=1.5V->3.2V n=2, 3, 4, 5 R5432V404BA 0.17 0.18 0.19 0.20 0.21 0.22 0.23 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VDET31(V) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA 0.54 0.56 0.58 0.60 0.62 0.64 0.66 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VDET32(V) VCELLn=3.2V n=1, 2, 3, 4, 5

NO.EA-263-160711 13) Short Detector Threshold 14) Excess discharge Current Detector Output Delay Time 1 15) Excess discharge Current detector Output Delay Time2 16) Short Detector Output Delay Time 17) Excess discharge Current released delay time 18) Excess charge Current Detector Threshold R5432V404BA 0.70 0.80 0.90 1.00 1.10 1.20 1.30 -60 -40 -20 0 20 40 60 80 100 Ta (°C) Vshort(V) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA -60 -40 -20 0 20 40 60 80 100 Ta (°C) tVDET31(msec) VCELLn=3.2V, SENS=VSS->0.4V, C2=3.3nF n=1, 2, 3, 4, 5 R5432V404BA 1.2 1.4 1.6 1.8 2.0 2.2 2.4 -60 -40 -20 0 20 40 60 80 100 Ta (°C) tVDET32(msec) VCELLn=3.2V, SENS=VSS->0.7V, C2=3.3nF n=1, 2, 3, 4, 5 R5432V404BA 0.0 0.1 0.2 0.3 0.4 0.5 0.6 -60 -40 -20 0 20 40 60 80 100 Ta (°C) tshort(msec) VCELLn=3.2V, SENS=VSS->1.5V n=1, 2, 3, 4, 5 R5432V404BA 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -60 -40 -20 0 20 40 60 80 100 Ta (°C) tVREL3(msec) VCELLn=3.2V, VMP=0.4V->VSS n=1, 2, 3, 4, 5 R5432V404BA -0.23 -0.22 -0.21 -0.20 -0.19 -0.18 -0.17 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VDET4(V) VCELLn=3.2V n=1, 2, 3, 4, 5

NO.EA-263-160711 19) Excess Charge Current Output Delay Time 20) Excess Charge Current Delay Time of Released 21) CTLC Pin "H" Input Voltage 22) CTLC Pin "H2" Input Voltage 23) CTLD Pin "H1" Input Voltage 24) CTLD Pin "H2" Input Voltage R5432V404BA -60 -40 -20 0 20 40 60 80 100 Ta (°C) tVDET4(msec) VCELLn=3.2V, SENS=VSS->-0.4V n=1, 2, 3, 4, 5 R5432V404BA 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -60 -40 -20 0 20 40 60 80 100 Ta (°C) tVREL4(msec) VCELLn=3.2V, VMP=-1.0V->1.0V n=1, 2, 3, 4, 5 R5432V404BA 16.0 16.4 16.8 17.2 17.6 18.0 18.4 -60 -40 -20 0 20 40 60 80 100 Ta (°C) CTLC1H(V) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA 13.6 14.0 14.4 14.8 15.2 15.6 16.0 -60 -40 -20 0 20 40 60 80 100 Ta (°C) CTLC2H(V) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA 16.0 16.4 16.8 17.2 17.6 18.0 18.4 -60 -40 -20 0 20 40 60 80 100 Ta (°C) CTLD1H(V) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA 13.6 14.0 14.4 14.8 15.2 15.6 16.0 -60 -40 -20 0 20 40 60 80 100 Ta (°C) CTLD2H(V) VCELLn=3.2V n=1, 2, 3, 4, 5

NO.EA-263-160711 25) DOUT Nch ON Voltage 26) DRAIN Nch ON Voltage 27) CB1 Nch ON Voltage 28) CB2 Nch ON Voltage 29) CB3 Nch ON Voltage 30) CB4 Nch ON Voltage R5432V404BA 0.00 0.02 0.04 0.06 0.08 0.10 0.12 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOL2(V) VCELLn=3.2V, I OL=-50uA n=1, 2, 3, 4, 5 R5432V404BA 0.00 0.02 0.04 0.06 0.08 0.10 0.12 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOL3(V) VCELLn=3.2V, I OL=-50uA n=1, 2, 3, 4, 5 R5432V404BA 0.00 0.05 0.10 0.15 0.20 0.25 0.30 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOL4-VC2(V) VCELLn=3.2V, I OL=-50uA n=1, 2, 3, 4, 5 R5432V404BA 0.00 0.05 0.10 0.15 0.20 0.25 0.30 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOL5-VC3(V) VCELLn=3.2V, I OL=-50uA n=1, 2, 3, 4, 5 R5432V404BA 0.00 0.05 0.10 0.15 0.20 0.25 0.30 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOL6-VC4(V) VCELLn=3.2V, I OL=-50uA n=1, 2, 3, 4, 5 R5432V404BA 0.00 0.05 0.10 0.15 0.20 0.25 0.30 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOL7-VC5(V) VCELLn=3.2V, I OL=-50uA n=1, 2, 3, 4, 5

NO.EA-263-160711 31) CB5 Nch ON Voltage 32) VR12V Output Voltage 33) COUT Pch ON Voltage 34) DOUT Pch ON Voltage 35) DRAIN Pch ON Voltage 36) CB1 Pch ON Voltage R5432V404BA 0.00 0.05 0.10 0.15 0.20 0.25 0.30 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOL8(V) VCELLn=3.2V, I OL=-50uA n=1, 2, 3, 4, 5 R5432V404BA 10.5 11.0 11.5 12.0 12.5 13.0 13.5 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VVR12(V) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOH1-VDD(V) VCELLn=3.2V, I OH=-50uA n=1, 2, 3, 4, 5 R5432V404BA -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOH2-VVR12(V) VCELLn=3.2V, I OH=-50uA n=1, 2, 3, 4, 5 R5432V404BA -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOH4-VC1(V) VCELLn=3.2V、VCELL1=4.5V, I OH=-50uA n=2, 3, 4, 5R5432V404BA -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0.00 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOH3-VVR12(V) VCELLn=3.2V, I OH=-50uA n=1, 2, 3, 4, 5

NO.EA-263-160711 37) CB2 Pch ON Voltage 38) CB3 Pch ON Voltage 39) CB4 Pch ON Voltage 40) CB4 Pch ON Voltage 41) CTLT Detector threshold 42) CTLT release Voltage R5432V404BA -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOH5-VC2(V) VCELLn=3.2V, VCELL2=4.5V, I OH=-50uA n=1, 3, 4, 5 R5432V404BA -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOH6-VC3(V) VCELLn=3.2V, VCELL3=4.5V, I OH=-50uA n=1, 2, 4, 5 R5432V404BA -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOH7-VC4(V) VCELLn=3.2V, VCELL4=4.5V, I OH=-50uA n=1, 2, 3, 5 R5432V404BA -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VOH8-VC5(V) VCELLn=3.2V, VCELL5=4.5V, I OH=-50uA n=1, 2, 3, 4 R5432V404BA 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VDTLT(V) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA 0.00 0.05 0.10 0.15 0.20 0.25 0.30 -60 -40 -20 0 20 40 60 80 100 Ta (°C) VRTLT(V) VCELLn=3.2V n=1, 2, 3, 4, 5

NO.EA-263-160711 43) CTLT Excess charge Current 44) Open-wire test interval time 45) COUT Off leak current 46) Supply Current1 47) Supply Current2 R5432V404BA 0.0 0.1 0.2 0.3 0.4 0.5 0.6 -60 -40 -20 0 20 40 60 80 100 Ta (°C) ICTLT(uA) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA -60 -40 -20 0 20 40 60 80 100 Ta (°C) tLT(sec) VCELLn=3.2V, C3=3.3uF n=1, 2, 3, 4, 5 R5432V404BA 0.0 0.2 0.4 0.6 0.8 1.0 1.2 -60 -40 -20 0 20 40 60 80 100 Ta (°C) ILCOUT(uA) VCELLn=3.2V、CTLC=VDD、COUT=-14V n=1, 2, 3, 4, 5 R5432V404BA -60 -40 -20 0 20 40 60 80 100 Ta (°C) Iss1(uA) VCELLn=3.2V n=1, 2, 3, 4, 5 R5432V404BA -60 -40 -20 0 20 40 60 80 100 Ta (°C) Iss2(uA) VCELLn=1.5V n=1, 2, 3, 4, 5

NO.EA-263-160711 Part2.Output Delay Time VDD dependence 1) Overcharge detector output Delay Time 2) Overcharge Released Delay Time 3) Overdischarge detector output Delay Time 4) Overdischarge Released Delay Time 5) Excess discharge current detector Delay Time 1 6) Excess discharge current detector Delay Time 2 R5432V404BA 0.4 0.6 0.8 1.2 1.4 1.6 VCELLn (V) tVDET1 (sec) VCELL1=3.2V, 3.6V, 4.0V->4.5V, SEL1=SEL2=VDD n=2, 3, 4, 5 R5432V404BA VCELLn (V) tVREL1 (msec) VCELL1=4.5V->3.2V, 3.6V, 4.0V, SEL1=SEL2=VDD n=2, 3, 4, 5 R5432V404BA 100 120 140 160 180 VCELLn (V) tVDET2 (msec) VCELL1=3.2V, 3.6V, 4.0V->2.0V, SEL1=SEL2=VDD n=2, 3, 4, 5 R5432V404BA 0.6 0.8 1.2 1.4 1.6 1.8 VCELLn (V) tVREL2 (msec) VCELL1=2.0V->3.2V, 3.6V, 4.0V, SEL1=SEL2=VDD n=2, 3, 4, 5 R5432V404BA VCELLn (V) tVDET31 (msec) SENS=Vss->Vss+0.4V, SEL1=SEL2=VDD n=1, 2, 3, 4, 5 R5432V404BA 1.2 1.4 1.6 1.8 2.2 2.4 VCELLn (V) tVDET32 (msec) SENS=Vss->Vss+0.7V, SEL1=SEL2=VDD n=1, 2, 3, 4, 5

NO.EA-263-160711 7) Short detector output delay time1 8) Excess discharge current released delay time2 9) Excess charge current detector output Delay Time 10) Excess charge current released delay time R5432V404BA 0.1 0.2 0.3 0.4 0.5 0.6 VCELLn (V) tshort (msec) SENS=Vss->Vss+1.5V, SEL1=SEL2=VDD n=1, 2, 3, 4, 5 R5432V404BA 0.6 0.8 1.2 1.4 1.6 1.8 VCELLn (V) tVREL3 (msec) V-=Vss+0.4V->Vss, SEL1=SEL2=VDD n=1, 2, 3, 4, 5 R5432V404BA VCELLn (V) tVDET4 (msec) V-=Vss->Vss-0.4V, SEL1=SEL2=VDD n=1, 2, 3, 4, 5 R5432V404BA 0.6 0.8 1.2 1.4 1.6 1.8 VCELLn (V) tVREL4 (msec) V-=Vss-0.4V->Vss+0.4V, SEL1=SEL2=V DD n=1, 2, 3, 4, 5

NO.EA-263-160711

Part3. Supply Current VDD dependence (R5432V404BA) Supply Current for 5-cell protection 0.1uF 330Ω VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 Cell4 Cell5 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC 10MΩ DRAIN 2MΩ SEL1 SEL2 CTLD 10kΩ VSS VSS CT1 CT2 10kΩ 1MΩ 0.1uF 0.1uF 0.1uF 0.1uF 1uF 0.47uF 3.3nF CTLT A 330Ω 330Ω 330Ω 330Ω 330Ω 100mΩ 0 5 10 15 20 25 VDD(V) Supply Current Iss(μA)

NO.EA-263-160711 Part4. External resistance dependence (R5432V404BA) Overcharge Detector/Released Voltage from Overcharge Overdischarge Detector/Released Voltage from Overdischarge vs. R1 (CELL1) vs. R1 (CELL1) 0.1uF VC1 VC2 VDD Cell1 CB1 Cell2 Cell3 Cell4 Cell5 VC3 VC4 VC5 VSS CB2 CB3 CB4 CB5 SENS VMP Cout Dout CTLC 10MΩ DRAIN 2MΩ SEL1 SEL2 CTLD 100mΩ 10kΩ VSS VSS CT1 CT2 10kΩ 1MΩ 0.1uF 0.1uF 0.1uF 0.1uF 1uF 0.47uF 3.3nF CTLT 330Ω 330Ω 330Ω 330Ω 330Ω 2.485 2.490 2.495 2.500 2.505 2.510 2.515 0 500 1000 1500 2000 R1(Ω) VDET21(V) 2.980 2.985 2.990 2.995 3.000 3.005 3.010 VREL21(V) VDET21 VREL21 4.235 4.240 4.245 4.250 4.255 4.260 4.265 0 500 1000 1500 2000 R1(Ω) VDET11(V) 4.090 4.095 4.100 4.105 4.110 4.115 4.120 VREL11(V) VDET11 VREL11

NO.EA-263-160711 CELL balance detector / Released Voltage from CELL balance vs. R1 (CELL1) 4.185 4.190 4.195 4.200 4.205 4.210 4.215 0 500 1000 1500 2000 R1(Ω) CBDET1(V) 4.185 4.190 4.195 4.200 4.205 4.210 4.215 CBREL1(V) CBDET1 CBREL1

Ver. A i The power dissipation of the package is dependent on PCB material, layout, and environmental conditions. The following conditions are used in this measurement. Measurement Conditions Standard Test Land Pattern Environment Mounting on Board (Wind Velocity = 0 m/s) Board Material Glass Cloth Epoxy Plastic (Double-Sided Board) Board Dimensions 40 mm × 40 mm × 1.6 mm Copper Ratio Top Side: Approx. 50% Bottom Side: Approx. 50% Through-holes f 0.5 mm × 44 pcs Measurement Result (Ta = 25°C, Tjmax = 125°C) Standard Test Land Pattern Power Dissipation 770 mW Thermal Resistance qja = (125 − 25°C) / 0.770 W = 130°C/W IC Mount Area (mm) Power Dissipation vs. Ambient Temperature Measurement Board Pattern 0 25 50 75 100 125 150 Ambient Temperature (°C) Power Dissipation (mW) 1000 800 600 400 200 770 Standard Test Land Pattern

PACKAGE DIMENSIONS SSOP-24 Ver. A i 0.375 TYP. 0.22-0.05 1.15±0.1 0.65 0.10 +0.1 0.15 M 0.1±0.05 1.4Max. 7.9±0.2 7.6±0.2 5.6±0.2 0.15-0.05 +0.1 0.5±0.2 0 to 10 °

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Product Information

R5432V503BB specifications and overview.

Summary

3 to 5 Cells Li-ion Battery Protector IC

Description

3 to 5 Cells Li-ion Battery Protector IC

Source title R5432V503BB Datasheet(PDF) - Nisshinbo Micro Devices Inc.

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